linux/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c

/*
 * Copyright 2023 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 */

#include "amdgpu.h"
#include "amdgpu_jpeg.h"
#include "amdgpu_pm.h"
#include "soc15.h"
#include "soc15d.h"
#include "jpeg_v4_0_3.h"

#include "vcn/vcn_5_0_0_offset.h"
#include "vcn/vcn_5_0_0_sh_mask.h"
#include "ivsrcid/vcn/irqsrcs_vcn_4_0.h"
#include "jpeg_v5_0_0.h"

static void jpeg_v5_0_0_set_dec_ring_funcs(struct amdgpu_device *adev);
static void jpeg_v5_0_0_set_irq_funcs(struct amdgpu_device *adev);
static int jpeg_v5_0_0_set_powergating_state(void *handle,
				enum amd_powergating_state state);

/**
 * jpeg_v5_0_0_early_init - set function pointers
 *
 * @handle: amdgpu_device pointer
 *
 * Set ring and irq function pointers
 */
static int jpeg_v5_0_0_early_init(void *handle)
{ … }

/**
 * jpeg_v5_0_0_sw_init - sw init for JPEG block
 *
 * @handle: amdgpu_device pointer
 *
 * Load firmware and sw initialization
 */
static int jpeg_v5_0_0_sw_init(void *handle)
{ … }

/**
 * jpeg_v5_0_0_sw_fini - sw fini for JPEG block
 *
 * @handle: amdgpu_device pointer
 *
 * JPEG suspend and free up sw allocation
 */
static int jpeg_v5_0_0_sw_fini(void *handle)
{ … }

/**
 * jpeg_v5_0_0_hw_init - start and test JPEG block
 *
 * @handle: amdgpu_device pointer
 *
 */
static int jpeg_v5_0_0_hw_init(void *handle)
{ … }

/**
 * jpeg_v5_0_0_hw_fini - stop the hardware block
 *
 * @handle: amdgpu_device pointer
 *
 * Stop the JPEG block, mark ring as not ready any more
 */
static int jpeg_v5_0_0_hw_fini(void *handle)
{ … }

/**
 * jpeg_v5_0_0_suspend - suspend JPEG block
 *
 * @handle: amdgpu_device pointer
 *
 * HW fini and suspend JPEG block
 */
static int jpeg_v5_0_0_suspend(void *handle)
{ … }

/**
 * jpeg_v5_0_0_resume - resume JPEG block
 *
 * @handle: amdgpu_device pointer
 *
 * Resume firmware and hw init JPEG block
 */
static int jpeg_v5_0_0_resume(void *handle)
{ … }

static void jpeg_v5_0_0_disable_clock_gating(struct amdgpu_device *adev)
{ … }

static void jpeg_v5_0_0_enable_clock_gating(struct amdgpu_device *adev)
{ … }

static int jpeg_v5_0_0_disable_power_gating(struct amdgpu_device *adev)
{ … }

static int jpeg_v5_0_0_enable_power_gating(struct amdgpu_device *adev)
{ … }

static void jpeg_engine_5_0_0_dpg_clock_gating_mode(struct amdgpu_device *adev,
	       int inst_idx, uint8_t indirect)
{ … }

/**
 * jpeg_v5_0_0_start_dpg_mode - Jpeg start with dpg mode
 *
 * @adev: amdgpu_device pointer
 * @inst_idx: instance number index
 * @indirect: indirectly write sram
 *
 * Start JPEG block with dpg mode
 */
static int jpeg_v5_0_0_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect)
{ … }

/**
 * jpeg_v5_0_0_stop_dpg_mode - Jpeg stop with dpg mode
 *
 * @adev: amdgpu_device pointer
 * @inst_idx: instance number index
 *
 * Stop JPEG block with dpg mode
 */
static void jpeg_v5_0_0_stop_dpg_mode(struct amdgpu_device *adev, int inst_idx)
{ … }

/**
 * jpeg_v5_0_0_start - start JPEG block
 *
 * @adev: amdgpu_device pointer
 *
 * Setup and start the JPEG block
 */
static int jpeg_v5_0_0_start(struct amdgpu_device *adev)
{ … }

/**
 * jpeg_v5_0_0_stop - stop JPEG block
 *
 * @adev: amdgpu_device pointer
 *
 * stop the JPEG block
 */
static int jpeg_v5_0_0_stop(struct amdgpu_device *adev)
{ … }

/**
 * jpeg_v5_0_0_dec_ring_get_rptr - get read pointer
 *
 * @ring: amdgpu_ring pointer
 *
 * Returns the current hardware read pointer
 */
static uint64_t jpeg_v5_0_0_dec_ring_get_rptr(struct amdgpu_ring *ring)
{ … }

/**
 * jpeg_v5_0_0_dec_ring_get_wptr - get write pointer
 *
 * @ring: amdgpu_ring pointer
 *
 * Returns the current hardware write pointer
 */
static uint64_t jpeg_v5_0_0_dec_ring_get_wptr(struct amdgpu_ring *ring)
{ … }

/**
 * jpeg_v5_0_0_dec_ring_set_wptr - set write pointer
 *
 * @ring: amdgpu_ring pointer
 *
 * Commits the write pointer to the hardware
 */
static void jpeg_v5_0_0_dec_ring_set_wptr(struct amdgpu_ring *ring)
{ … }

static bool jpeg_v5_0_0_is_idle(void *handle)
{ … }

static int jpeg_v5_0_0_wait_for_idle(void *handle)
{ … }

static int jpeg_v5_0_0_set_clockgating_state(void *handle,
					  enum amd_clockgating_state state)
{ … }

static int jpeg_v5_0_0_set_powergating_state(void *handle,
					  enum amd_powergating_state state)
{ … }

static int jpeg_v5_0_0_set_interrupt_state(struct amdgpu_device *adev,
					struct amdgpu_irq_src *source,
					unsigned int type,
					enum amdgpu_interrupt_state state)
{ … }

static int jpeg_v5_0_0_process_interrupt(struct amdgpu_device *adev,
				      struct amdgpu_irq_src *source,
				      struct amdgpu_iv_entry *entry)
{ … }

static const struct amd_ip_funcs jpeg_v5_0_0_ip_funcs = …;

static const struct amdgpu_ring_funcs jpeg_v5_0_0_dec_ring_vm_funcs = …;

static void jpeg_v5_0_0_set_dec_ring_funcs(struct amdgpu_device *adev)
{ … }

static const struct amdgpu_irq_src_funcs jpeg_v5_0_0_irq_funcs = …;

static void jpeg_v5_0_0_set_irq_funcs(struct amdgpu_device *adev)
{ … }

const struct amdgpu_ip_block_version jpeg_v5_0_0_ip_block = …;