/* * Copyright 2014 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #include <linux/firmware.h> #include <linux/module.h> #include "amdgpu.h" #include "amdgpu_ih.h" #include "amdgpu_gfx.h" #include "cikd.h" #include "cik.h" #include "cik_structs.h" #include "atom.h" #include "amdgpu_ucode.h" #include "clearstate_ci.h" #include "dce/dce_8_0_d.h" #include "dce/dce_8_0_sh_mask.h" #include "bif/bif_4_1_d.h" #include "bif/bif_4_1_sh_mask.h" #include "gca/gfx_7_0_d.h" #include "gca/gfx_7_2_enum.h" #include "gca/gfx_7_2_sh_mask.h" #include "gmc/gmc_7_0_d.h" #include "gmc/gmc_7_0_sh_mask.h" #include "oss/oss_2_0_d.h" #include "oss/oss_2_0_sh_mask.h" #define NUM_SIMD_PER_CU … #define GFX7_NUM_GFX_RINGS … #define GFX7_MEC_HPD_SIZE … static void gfx_v7_0_set_ring_funcs(struct amdgpu_device *adev); static void gfx_v7_0_set_irq_funcs(struct amdgpu_device *adev); static void gfx_v7_0_set_gds_init(struct amdgpu_device *adev); MODULE_FIRMWARE(…) …; MODULE_FIRMWARE(…) …; MODULE_FIRMWARE(…) …; MODULE_FIRMWARE(…) …; MODULE_FIRMWARE(…) …; MODULE_FIRMWARE(…) …; MODULE_FIRMWARE(…) …; MODULE_FIRMWARE(…) …; MODULE_FIRMWARE(…) …; MODULE_FIRMWARE(…) …; MODULE_FIRMWARE(…) …; MODULE_FIRMWARE(…) …; MODULE_FIRMWARE(…) …; MODULE_FIRMWARE(…) …; MODULE_FIRMWARE(…) …; MODULE_FIRMWARE(…) …; MODULE_FIRMWARE(…) …; MODULE_FIRMWARE(…) …; MODULE_FIRMWARE(…) …; MODULE_FIRMWARE(…) …; MODULE_FIRMWARE(…) …; MODULE_FIRMWARE(…) …; MODULE_FIRMWARE(…) …; MODULE_FIRMWARE(…) …; MODULE_FIRMWARE(…) …; MODULE_FIRMWARE(…) …; static const struct amdgpu_gds_reg_offset amdgpu_gds_reg_offset[] = …; static const u32 spectre_rlc_save_restore_register_list[] = …; static const u32 kalindi_rlc_save_restore_register_list[] = …; static u32 gfx_v7_0_get_csb_size(struct amdgpu_device *adev); static void gfx_v7_0_get_csb_buffer(struct amdgpu_device *adev, volatile u32 *buffer); static void gfx_v7_0_init_pg(struct amdgpu_device *adev); static void gfx_v7_0_get_cu_info(struct amdgpu_device *adev); static void gfx_v7_0_free_microcode(struct amdgpu_device *adev) { … } /* * Core functions */ /** * gfx_v7_0_init_microcode - load ucode images from disk * * @adev: amdgpu_device pointer * * Use the firmware interface to load the ucode images into * the driver (not loaded into hw). * Returns 0 on success, error on failure. */ static int gfx_v7_0_init_microcode(struct amdgpu_device *adev) { … } /** * gfx_v7_0_tiling_mode_table_init - init the hw tiling table * * @adev: amdgpu_device pointer * * Starting with SI, the tiling setup is done globally in a * set of 32 tiling modes. Rather than selecting each set of * parameters per surface as on older asics, we just select * which index in the tiling table we want to use, and the * surface uses those parameters (CIK). */ static void gfx_v7_0_tiling_mode_table_init(struct amdgpu_device *adev) { … } /** * gfx_v7_0_select_se_sh - select which SE, SH to address * * @adev: amdgpu_device pointer * @se_num: shader engine to address * @sh_num: sh block to address * @instance: Certain registers are instanced per SE or SH. * 0xffffffff means broadcast to all SEs or SHs (CIK). * @xcc_id: xcc accelerated compute core id * Select which SE, SH combinations to address. */ static void gfx_v7_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance, int xcc_id) { … } /** * gfx_v7_0_get_rb_active_bitmap - computes the mask of enabled RBs * * @adev: amdgpu_device pointer * * Calculates the bitmask of enabled RBs (CIK). * Returns the enabled RB bitmask. */ static u32 gfx_v7_0_get_rb_active_bitmap(struct amdgpu_device *adev) { … } static void gfx_v7_0_raster_config(struct amdgpu_device *adev, u32 *rconf, u32 *rconf1) { … } static void gfx_v7_0_write_harvested_raster_configs(struct amdgpu_device *adev, u32 raster_config, u32 raster_config_1, unsigned rb_mask, unsigned num_rb) { … } /** * gfx_v7_0_setup_rb - setup the RBs on the asic * * @adev: amdgpu_device pointer * * Configures per-SE/SH RB registers (CIK). */ static void gfx_v7_0_setup_rb(struct amdgpu_device *adev) { … } #define DEFAULT_SH_MEM_BASES … /** * gfx_v7_0_init_compute_vmid - gart enable * * @adev: amdgpu_device pointer * * Initialize compute vmid sh_mem registers * */ static void gfx_v7_0_init_compute_vmid(struct amdgpu_device *adev) { … } static void gfx_v7_0_init_gds_vmid(struct amdgpu_device *adev) { … } static void gfx_v7_0_config_init(struct amdgpu_device *adev) { … } /** * gfx_v7_0_constants_init - setup the 3D engine * * @adev: amdgpu_device pointer * * init the gfx constants such as the 3D engine, tiling configuration * registers, maximum number of quad pipes, render backends... */ static void gfx_v7_0_constants_init(struct amdgpu_device *adev) { … } /** * gfx_v7_0_ring_test_ring - basic gfx ring test * * @ring: amdgpu_ring structure holding ring information * * Allocate a scratch register and write to it using the gfx ring (CIK). * Provides a basic gfx ring test to verify that the ring is working. * Used by gfx_v7_0_cp_gfx_resume(); * Returns 0 on success, error on failure. */ static int gfx_v7_0_ring_test_ring(struct amdgpu_ring *ring) { … } /** * gfx_v7_0_ring_emit_hdp_flush - emit an hdp flush on the cp * * @ring: amdgpu_ring structure holding ring information * * Emits an hdp flush on the cp. */ static void gfx_v7_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) { … } static void gfx_v7_0_ring_emit_vgt_flush(struct amdgpu_ring *ring) { … } /** * gfx_v7_0_ring_emit_fence_gfx - emit a fence on the gfx ring * * @ring: amdgpu_ring structure holding ring information * @addr: address * @seq: sequence number * @flags: fence related flags * * Emits a fence sequence number on the gfx ring and flushes * GPU caches. */ static void gfx_v7_0_ring_emit_fence_gfx(struct amdgpu_ring *ring, u64 addr, u64 seq, unsigned flags) { … } /** * gfx_v7_0_ring_emit_fence_compute - emit a fence on the compute ring * * @ring: amdgpu_ring structure holding ring information * @addr: address * @seq: sequence number * @flags: fence related flags * * Emits a fence sequence number on the compute ring and flushes * GPU caches. */ static void gfx_v7_0_ring_emit_fence_compute(struct amdgpu_ring *ring, u64 addr, u64 seq, unsigned flags) { … } /* * IB stuff */ /** * gfx_v7_0_ring_emit_ib_gfx - emit an IB (Indirect Buffer) on the ring * * @ring: amdgpu_ring structure holding ring information * @job: job to retrieve vmid from * @ib: amdgpu indirect buffer object * @flags: options (AMDGPU_HAVE_CTX_SWITCH) * * Emits an DE (drawing engine) or CE (constant engine) IB * on the gfx ring. IBs are usually generated by userspace * acceleration drivers and submitted to the kernel for * scheduling on the ring. This function schedules the IB * on the gfx ring for execution by the GPU. */ static void gfx_v7_0_ring_emit_ib_gfx(struct amdgpu_ring *ring, struct amdgpu_job *job, struct amdgpu_ib *ib, uint32_t flags) { … } static void gfx_v7_0_ring_emit_ib_compute(struct amdgpu_ring *ring, struct amdgpu_job *job, struct amdgpu_ib *ib, uint32_t flags) { … } static void gfx_v7_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags) { … } /** * gfx_v7_0_ring_test_ib - basic ring IB test * * @ring: amdgpu_ring structure holding ring information * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT * * Allocate an IB and execute it on the gfx ring (CIK). * Provides a basic gfx ring test to verify that IBs are working. * Returns 0 on success, error on failure. */ static int gfx_v7_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) { … } /* * CP. * On CIK, gfx and compute now have independent command processors. * * GFX * Gfx consists of a single ring and can process both gfx jobs and * compute jobs. The gfx CP consists of three microengines (ME): * PFP - Pre-Fetch Parser * ME - Micro Engine * CE - Constant Engine * The PFP and ME make up what is considered the Drawing Engine (DE). * The CE is an asynchronous engine used for updating buffer desciptors * used by the DE so that they can be loaded into cache in parallel * while the DE is processing state update packets. * * Compute * The compute CP consists of two microengines (ME): * MEC1 - Compute MicroEngine 1 * MEC2 - Compute MicroEngine 2 * Each MEC supports 4 compute pipes and each pipe supports 8 queues. * The queues are exposed to userspace and are programmed directly * by the compute runtime. */ /** * gfx_v7_0_cp_gfx_enable - enable/disable the gfx CP MEs * * @adev: amdgpu_device pointer * @enable: enable or disable the MEs * * Halts or unhalts the gfx MEs. */ static void gfx_v7_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable) { … } /** * gfx_v7_0_cp_gfx_load_microcode - load the gfx CP ME ucode * * @adev: amdgpu_device pointer * * Loads the gfx PFP, ME, and CE ucode. * Returns 0 for success, -EINVAL if the ucode is not available. */ static int gfx_v7_0_cp_gfx_load_microcode(struct amdgpu_device *adev) { … } /** * gfx_v7_0_cp_gfx_start - start the gfx ring * * @adev: amdgpu_device pointer * * Enables the ring and loads the clear state context and other * packets required to init the ring. * Returns 0 for success, error for failure. */ static int gfx_v7_0_cp_gfx_start(struct amdgpu_device *adev) { … } /** * gfx_v7_0_cp_gfx_resume - setup the gfx ring buffer registers * * @adev: amdgpu_device pointer * * Program the location and size of the gfx ring buffer * and test it to make sure it's working. * Returns 0 for success, error for failure. */ static int gfx_v7_0_cp_gfx_resume(struct amdgpu_device *adev) { … } static u64 gfx_v7_0_ring_get_rptr(struct amdgpu_ring *ring) { … } static u64 gfx_v7_0_ring_get_wptr_gfx(struct amdgpu_ring *ring) { … } static void gfx_v7_0_ring_set_wptr_gfx(struct amdgpu_ring *ring) { … } static u64 gfx_v7_0_ring_get_wptr_compute(struct amdgpu_ring *ring) { … } static void gfx_v7_0_ring_set_wptr_compute(struct amdgpu_ring *ring) { … } /** * gfx_v7_0_cp_compute_enable - enable/disable the compute CP MEs * * @adev: amdgpu_device pointer * @enable: enable or disable the MEs * * Halts or unhalts the compute MEs. */ static void gfx_v7_0_cp_compute_enable(struct amdgpu_device *adev, bool enable) { … } /** * gfx_v7_0_cp_compute_load_microcode - load the compute CP ME ucode * * @adev: amdgpu_device pointer * * Loads the compute MEC1&2 ucode. * Returns 0 for success, -EINVAL if the ucode is not available. */ static int gfx_v7_0_cp_compute_load_microcode(struct amdgpu_device *adev) { … } /** * gfx_v7_0_cp_compute_fini - stop the compute queues * * @adev: amdgpu_device pointer * * Stop the compute queues and tear down the driver queue * info. */ static void gfx_v7_0_cp_compute_fini(struct amdgpu_device *adev) { … } static void gfx_v7_0_mec_fini(struct amdgpu_device *adev) { … } static int gfx_v7_0_mec_init(struct amdgpu_device *adev) { … } static void gfx_v7_0_compute_pipe_init(struct amdgpu_device *adev, int mec, int pipe) { … } static int gfx_v7_0_mqd_deactivate(struct amdgpu_device *adev) { … } static void gfx_v7_0_mqd_init(struct amdgpu_device *adev, struct cik_mqd *mqd, uint64_t mqd_gpu_addr, struct amdgpu_ring *ring) { … } static int gfx_v7_0_mqd_commit(struct amdgpu_device *adev, struct cik_mqd *mqd) { … } static int gfx_v7_0_compute_queue_init(struct amdgpu_device *adev, int ring_id) { … } /** * gfx_v7_0_cp_compute_resume - setup the compute queue registers * * @adev: amdgpu_device pointer * * Program the compute queues and test them to make sure they * are working. * Returns 0 for success, error for failure. */ static int gfx_v7_0_cp_compute_resume(struct amdgpu_device *adev) { … } static void gfx_v7_0_cp_enable(struct amdgpu_device *adev, bool enable) { … } static int gfx_v7_0_cp_load_microcode(struct amdgpu_device *adev) { … } static void gfx_v7_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, bool enable) { … } static int gfx_v7_0_cp_resume(struct amdgpu_device *adev) { … } /** * gfx_v7_0_ring_emit_pipeline_sync - cik vm flush using the CP * * @ring: the ring to emit the commands to * * Sync the command pipeline with the PFP. E.g. wait for everything * to be completed. */ static void gfx_v7_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) { … } /* * vm * VMID 0 is the physical GPU addresses as used by the kernel. * VMIDs 1-15 are used for userspace clients and are handled * by the amdgpu vm/hsa code. */ /** * gfx_v7_0_ring_emit_vm_flush - cik vm flush using the CP * * @ring: amdgpu_ring pointer * @vmid: vmid number to use * @pd_addr: address * * Update the page table base and flush the VM TLB * using the CP (CIK). */ static void gfx_v7_0_ring_emit_vm_flush(struct amdgpu_ring *ring, unsigned vmid, uint64_t pd_addr) { … } static void gfx_v7_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val) { … } /* * RLC * The RLC is a multi-purpose microengine that handles a * variety of functions. */ static int gfx_v7_0_rlc_init(struct amdgpu_device *adev) { … } static void gfx_v7_0_enable_lbpw(struct amdgpu_device *adev, bool enable) { … } static void gfx_v7_0_wait_for_rlc_serdes(struct amdgpu_device *adev) { … } static void gfx_v7_0_update_rlc(struct amdgpu_device *adev, u32 rlc) { … } static u32 gfx_v7_0_halt_rlc(struct amdgpu_device *adev) { … } static bool gfx_v7_0_is_rlc_enabled(struct amdgpu_device *adev) { … } static void gfx_v7_0_set_safe_mode(struct amdgpu_device *adev, int xcc_id) { … } static void gfx_v7_0_unset_safe_mode(struct amdgpu_device *adev, int xcc_id) { … } /** * gfx_v7_0_rlc_stop - stop the RLC ME * * @adev: amdgpu_device pointer * * Halt the RLC ME (MicroEngine) (CIK). */ static void gfx_v7_0_rlc_stop(struct amdgpu_device *adev) { … } /** * gfx_v7_0_rlc_start - start the RLC ME * * @adev: amdgpu_device pointer * * Unhalt the RLC ME (MicroEngine) (CIK). */ static void gfx_v7_0_rlc_start(struct amdgpu_device *adev) { … } static void gfx_v7_0_rlc_reset(struct amdgpu_device *adev) { … } /** * gfx_v7_0_rlc_resume - setup the RLC hw * * @adev: amdgpu_device pointer * * Initialize the RLC registers, load the ucode, * and start the RLC (CIK). * Returns 0 for success, -EINVAL if the ucode is not available. */ static int gfx_v7_0_rlc_resume(struct amdgpu_device *adev) { … } static void gfx_v7_0_update_spm_vmid(struct amdgpu_device *adev, struct amdgpu_ring *ring, unsigned vmid) { … } static void gfx_v7_0_enable_cgcg(struct amdgpu_device *adev, bool enable) { … } static void gfx_v7_0_enable_mgcg(struct amdgpu_device *adev, bool enable) { … } static void gfx_v7_0_update_cg(struct amdgpu_device *adev, bool enable) { … } static void gfx_v7_0_enable_sclk_slowdown_on_pu(struct amdgpu_device *adev, bool enable) { … } static void gfx_v7_0_enable_sclk_slowdown_on_pd(struct amdgpu_device *adev, bool enable) { … } static void gfx_v7_0_enable_cp_pg(struct amdgpu_device *adev, bool enable) { … } static void gfx_v7_0_enable_gds_pg(struct amdgpu_device *adev, bool enable) { … } static int gfx_v7_0_cp_pg_table_num(struct amdgpu_device *adev) { … } static void gfx_v7_0_enable_gfx_cgpg(struct amdgpu_device *adev, bool enable) { … } static void gfx_v7_0_set_user_cu_inactive_bitmap(struct amdgpu_device *adev, u32 bitmap) { … } static u32 gfx_v7_0_get_cu_active_bitmap(struct amdgpu_device *adev) { … } static void gfx_v7_0_init_ao_cu_mask(struct amdgpu_device *adev) { … } static void gfx_v7_0_enable_gfx_static_mgpg(struct amdgpu_device *adev, bool enable) { … } static void gfx_v7_0_enable_gfx_dynamic_mgpg(struct amdgpu_device *adev, bool enable) { … } #define RLC_SAVE_AND_RESTORE_STARTING_OFFSET … #define RLC_CLEAR_STATE_DESCRIPTOR_OFFSET … static void gfx_v7_0_init_gfx_cgpg(struct amdgpu_device *adev) { … } static void gfx_v7_0_update_gfx_pg(struct amdgpu_device *adev, bool enable) { … } static u32 gfx_v7_0_get_csb_size(struct amdgpu_device *adev) { … } static void gfx_v7_0_get_csb_buffer(struct amdgpu_device *adev, volatile u32 *buffer) { … } static void gfx_v7_0_init_pg(struct amdgpu_device *adev) { … } static void gfx_v7_0_fini_pg(struct amdgpu_device *adev) { … } /** * gfx_v7_0_get_gpu_clock_counter - return GPU clock counter snapshot * * @adev: amdgpu_device pointer * * Fetches a GPU clock counter snapshot (SI). * Returns the 64 bit clock counter snapshot. */ static uint64_t gfx_v7_0_get_gpu_clock_counter(struct amdgpu_device *adev) { … } static void gfx_v7_0_ring_emit_gds_switch(struct amdgpu_ring *ring, uint32_t vmid, uint32_t gds_base, uint32_t gds_size, uint32_t gws_base, uint32_t gws_size, uint32_t oa_base, uint32_t oa_size) { … } static void gfx_v7_0_ring_soft_recovery(struct amdgpu_ring *ring, unsigned vmid) { … } static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address) { … } static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t thread, uint32_t regno, uint32_t num, uint32_t *out) { … } static void gfx_v7_0_read_wave_data(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields) { … } static void gfx_v7_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t start, uint32_t size, uint32_t *dst) { … } static void gfx_v7_0_select_me_pipe_q(struct amdgpu_device *adev, u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id) { … } static const struct amdgpu_gfx_funcs gfx_v7_0_gfx_funcs = …; static const struct amdgpu_rlc_funcs gfx_v7_0_rlc_funcs = …; static int gfx_v7_0_early_init(void *handle) { … } static int gfx_v7_0_late_init(void *handle) { … } static void gfx_v7_0_gpu_early_init(struct amdgpu_device *adev) { … } static int gfx_v7_0_compute_ring_init(struct amdgpu_device *adev, int ring_id, int mec, int pipe, int queue) { … } static int gfx_v7_0_sw_init(void *handle) { … } static int gfx_v7_0_sw_fini(void *handle) { … } static int gfx_v7_0_hw_init(void *handle) { … } static int gfx_v7_0_hw_fini(void *handle) { … } static int gfx_v7_0_suspend(void *handle) { … } static int gfx_v7_0_resume(void *handle) { … } static bool gfx_v7_0_is_idle(void *handle) { … } static int gfx_v7_0_wait_for_idle(void *handle) { … } static int gfx_v7_0_soft_reset(void *handle) { … } static void gfx_v7_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev, enum amdgpu_interrupt_state state) { … } static void gfx_v7_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev, int me, int pipe, enum amdgpu_interrupt_state state) { … } static int gfx_v7_0_set_priv_reg_fault_state(struct amdgpu_device *adev, struct amdgpu_irq_src *src, unsigned type, enum amdgpu_interrupt_state state) { … } static int gfx_v7_0_set_priv_inst_fault_state(struct amdgpu_device *adev, struct amdgpu_irq_src *src, unsigned type, enum amdgpu_interrupt_state state) { … } static int gfx_v7_0_set_eop_interrupt_state(struct amdgpu_device *adev, struct amdgpu_irq_src *src, unsigned type, enum amdgpu_interrupt_state state) { … } static int gfx_v7_0_eop_irq(struct amdgpu_device *adev, struct amdgpu_irq_src *source, struct amdgpu_iv_entry *entry) { … } static void gfx_v7_0_fault(struct amdgpu_device *adev, struct amdgpu_iv_entry *entry) { … } static int gfx_v7_0_priv_reg_irq(struct amdgpu_device *adev, struct amdgpu_irq_src *source, struct amdgpu_iv_entry *entry) { … } static int gfx_v7_0_priv_inst_irq(struct amdgpu_device *adev, struct amdgpu_irq_src *source, struct amdgpu_iv_entry *entry) { … } static int gfx_v7_0_set_clockgating_state(void *handle, enum amd_clockgating_state state) { … } static int gfx_v7_0_set_powergating_state(void *handle, enum amd_powergating_state state) { … } static void gfx_v7_0_emit_mem_sync(struct amdgpu_ring *ring) { … } static void gfx_v7_0_emit_mem_sync_compute(struct amdgpu_ring *ring) { … } static const struct amd_ip_funcs gfx_v7_0_ip_funcs = …; static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_gfx = …; static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_compute = …; static void gfx_v7_0_set_ring_funcs(struct amdgpu_device *adev) { … } static const struct amdgpu_irq_src_funcs gfx_v7_0_eop_irq_funcs = …; static const struct amdgpu_irq_src_funcs gfx_v7_0_priv_reg_irq_funcs = …; static const struct amdgpu_irq_src_funcs gfx_v7_0_priv_inst_irq_funcs = …; static void gfx_v7_0_set_irq_funcs(struct amdgpu_device *adev) { … } static void gfx_v7_0_set_gds_init(struct amdgpu_device *adev) { … } static void gfx_v7_0_get_cu_info(struct amdgpu_device *adev) { … } const struct amdgpu_ip_block_version gfx_v7_1_ip_block = …; const struct amdgpu_ip_block_version gfx_v7_2_ip_block = …; const struct amdgpu_ip_block_version gfx_v7_3_ip_block = …;
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