/* * Copyright (C) 2017 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included * in all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #ifndef _hdp_4_0_SH_MASK_HEADER #define _hdp_4_0_SH_MASK_HEADER // addressBlock: hdp_hdpdec //HDP_MMHUB_TLVL #define HDP_MMHUB_TLVL__HDP_WR_TLVL__SHIFT … #define HDP_MMHUB_TLVL__HDP_RD_TLVL__SHIFT … #define HDP_MMHUB_TLVL__XDP_WR_TLVL__SHIFT … #define HDP_MMHUB_TLVL__XDP_RD_TLVL__SHIFT … #define HDP_MMHUB_TLVL__XDP_MBX_WR_TLVL__SHIFT … #define HDP_MMHUB_TLVL__HDP_WR_TLVL_MASK … #define HDP_MMHUB_TLVL__HDP_RD_TLVL_MASK … #define HDP_MMHUB_TLVL__XDP_WR_TLVL_MASK … #define HDP_MMHUB_TLVL__XDP_RD_TLVL_MASK … #define HDP_MMHUB_TLVL__XDP_MBX_WR_TLVL_MASK … //HDP_MMHUB_UNITID #define HDP_MMHUB_UNITID__HDP_UNITID__SHIFT … #define HDP_MMHUB_UNITID__XDP_UNITID__SHIFT … #define HDP_MMHUB_UNITID__XDP_MBX_UNITID__SHIFT … #define HDP_MMHUB_UNITID__HDP_UNITID_MASK … #define HDP_MMHUB_UNITID__XDP_UNITID_MASK … #define HDP_MMHUB_UNITID__XDP_MBX_UNITID_MASK … //HDP_NONSURFACE_BASE #define HDP_NONSURFACE_BASE__NONSURF_BASE_39_8__SHIFT … #define HDP_NONSURFACE_BASE__NONSURF_BASE_39_8_MASK … //HDP_NONSURFACE_INFO #define HDP_NONSURFACE_INFO__NONSURF_SWAP__SHIFT … #define HDP_NONSURFACE_INFO__NONSURF_VMID__SHIFT … #define HDP_NONSURFACE_INFO__NONSURF_SWAP_MASK … #define HDP_NONSURFACE_INFO__NONSURF_VMID_MASK … //HDP_NONSURFACE_BASE_HI #define HDP_NONSURFACE_BASE_HI__NONSURF_BASE_47_40__SHIFT … #define HDP_NONSURFACE_BASE_HI__NONSURF_BASE_47_40_MASK … //HDP_NONSURF_FLAGS #define HDP_NONSURF_FLAGS__NONSURF_WRITE_FLAG__SHIFT … #define HDP_NONSURF_FLAGS__NONSURF_READ_FLAG__SHIFT … #define HDP_NONSURF_FLAGS__NONSURF_WRITE_FLAG_MASK … #define HDP_NONSURF_FLAGS__NONSURF_READ_FLAG_MASK … //HDP_NONSURF_FLAGS_CLR #define HDP_NONSURF_FLAGS_CLR__NONSURF_WRITE_FLAG_CLR__SHIFT … #define HDP_NONSURF_FLAGS_CLR__NONSURF_READ_FLAG_CLR__SHIFT … #define HDP_NONSURF_FLAGS_CLR__NONSURF_WRITE_FLAG_CLR_MASK … #define HDP_NONSURF_FLAGS_CLR__NONSURF_READ_FLAG_CLR_MASK … //HDP_HOST_PATH_CNTL #define HDP_HOST_PATH_CNTL__WR_STALL_TIMER__SHIFT … #define HDP_HOST_PATH_CNTL__RD_STALL_TIMER__SHIFT … #define HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER_PRELOAD_CFG__SHIFT … #define HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER__SHIFT … #define HDP_HOST_PATH_CNTL__WRITE_COMBINE_EN__SHIFT … #define HDP_HOST_PATH_CNTL__WRITE_COMBINE_64B_EN__SHIFT … #define HDP_HOST_PATH_CNTL__ALL_SURFACES_DIS__SHIFT … #define HDP_HOST_PATH_CNTL__WRITE_THROUGH_CACHE_DIS__SHIFT … #define HDP_HOST_PATH_CNTL__LIN_RD_CACHE_DIS__SHIFT … #define HDP_HOST_PATH_CNTL__WR_STALL_TIMER_MASK … #define HDP_HOST_PATH_CNTL__RD_STALL_TIMER_MASK … #define HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER_PRELOAD_CFG_MASK … #define HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER_MASK … #define HDP_HOST_PATH_CNTL__WRITE_COMBINE_EN_MASK … #define HDP_HOST_PATH_CNTL__WRITE_COMBINE_64B_EN_MASK … #define HDP_HOST_PATH_CNTL__ALL_SURFACES_DIS_MASK … #define HDP_HOST_PATH_CNTL__WRITE_THROUGH_CACHE_DIS_MASK … #define HDP_HOST_PATH_CNTL__LIN_RD_CACHE_DIS_MASK … //HDP_SW_SEMAPHORE #define HDP_SW_SEMAPHORE__SW_SEMAPHORE__SHIFT … #define HDP_SW_SEMAPHORE__SW_SEMAPHORE_MASK … //HDP_DEBUG0 #define HDP_DEBUG0__HDP_DEBUG__SHIFT … #define HDP_DEBUG0__HDP_DEBUG_MASK … //HDP_LAST_SURFACE_HIT #define HDP_LAST_SURFACE_HIT__LAST_SURFACE_HIT__SHIFT … #define HDP_LAST_SURFACE_HIT__LAST_SURFACE_HIT_MASK … //HDP_READ_CACHE_INVALIDATE #define HDP_READ_CACHE_INVALIDATE__READ_CACHE_INVALIDATE__SHIFT … #define HDP_READ_CACHE_INVALIDATE__READ_CACHE_INVALIDATE_MASK … //HDP_OUTSTANDING_REQ #define HDP_OUTSTANDING_REQ__WRITE_REQ__SHIFT … #define HDP_OUTSTANDING_REQ__READ_REQ__SHIFT … #define HDP_OUTSTANDING_REQ__WRITE_REQ_MASK … #define HDP_OUTSTANDING_REQ__READ_REQ_MASK … //HDP_MISC_CNTL #define HDP_MISC_CNTL__FLUSH_INVALIDATE_CACHE__SHIFT … #define HDP_MISC_CNTL__IDLE_HYSTERESIS_CNTL__SHIFT … #define HDP_MISC_CNTL__OUTSTANDING_WRITE_COUNT_1024__SHIFT … #define HDP_MISC_CNTL__MULTIPLE_READS__SHIFT … #define HDP_MISC_CNTL__SIMULTANEOUS_READS_WRITES__SHIFT … #define HDP_MISC_CNTL__READ_BUFFER_WATERMARK__SHIFT … #define HDP_MISC_CNTL__FED_ENABLE__SHIFT … #define HDP_MISC_CNTL__SYSHUB_CHANNEL_PRIORITY__SHIFT … #define HDP_MISC_CNTL__MMHUB_WRBURST_ENABLE__SHIFT … #define HDP_MISC_CNTL__ALL_FUNCTION_CACHELINE_INVALID__SHIFT … #define HDP_MISC_CNTL__HDP_MMHUB_PENDING_WR_TAG_CHECK__SHIFT … #define HDP_MISC_CNTL__XDP_MMHUB_PENDING_WR_TAG_CHECK__SHIFT … #define HDP_MISC_CNTL__VARIABLE_CACHELINE_SIZE__SHIFT … #define HDP_MISC_CNTL__ADAPTIVE_CACHELINE_SIZE__SHIFT … #define HDP_MISC_CNTL__MMHUB_WRBURST_SIZE__SHIFT … #define HDP_MISC_CNTL__FLUSH_INVALIDATE_CACHE_MASK … #define HDP_MISC_CNTL__IDLE_HYSTERESIS_CNTL_MASK … #define HDP_MISC_CNTL__OUTSTANDING_WRITE_COUNT_1024_MASK … #define HDP_MISC_CNTL__MULTIPLE_READS_MASK … #define HDP_MISC_CNTL__SIMULTANEOUS_READS_WRITES_MASK … #define HDP_MISC_CNTL__READ_BUFFER_WATERMARK_MASK … #define HDP_MISC_CNTL__FED_ENABLE_MASK … #define HDP_MISC_CNTL__SYSHUB_CHANNEL_PRIORITY_MASK … #define HDP_MISC_CNTL__MMHUB_WRBURST_ENABLE_MASK … #define HDP_MISC_CNTL__ALL_FUNCTION_CACHELINE_INVALID_MASK … #define HDP_MISC_CNTL__HDP_MMHUB_PENDING_WR_TAG_CHECK_MASK … #define HDP_MISC_CNTL__XDP_MMHUB_PENDING_WR_TAG_CHECK_MASK … #define HDP_MISC_CNTL__VARIABLE_CACHELINE_SIZE_MASK … #define HDP_MISC_CNTL__ADAPTIVE_CACHELINE_SIZE_MASK … #define HDP_MISC_CNTL__MMHUB_WRBURST_SIZE_MASK … //HDP_MEM_POWER_LS #define HDP_MEM_POWER_LS__LS_ENABLE__SHIFT … #define HDP_MEM_POWER_LS__LS_HOLD__SHIFT … #define HDP_MEM_POWER_LS__LS_ENABLE_MASK … #define HDP_MEM_POWER_LS__LS_HOLD_MASK … //HDP_MMHUB_CNTL #define HDP_MMHUB_CNTL__HDP_MMHUB_RO__SHIFT … #define HDP_MMHUB_CNTL__HDP_MMHUB_GCC__SHIFT … #define HDP_MMHUB_CNTL__HDP_MMHUB_SNOOP__SHIFT … #define HDP_MMHUB_CNTL__HDP_MMHUB_RO_MASK … #define HDP_MMHUB_CNTL__HDP_MMHUB_GCC_MASK … #define HDP_MMHUB_CNTL__HDP_MMHUB_SNOOP_MASK … //HDP_EDC_CNT #define HDP_EDC_CNT__MEM0_SED_COUNT__SHIFT … #define HDP_EDC_CNT__MEM1_SED_COUNT__SHIFT … #define HDP_EDC_CNT__MEM0_SED_COUNT_MASK … #define HDP_EDC_CNT__MEM1_SED_COUNT_MASK … //HDP_VERSION #define HDP_VERSION__MINVER__SHIFT … #define HDP_VERSION__MAJVER__SHIFT … #define HDP_VERSION__REV__SHIFT … #define HDP_VERSION__MINVER_MASK … #define HDP_VERSION__MAJVER_MASK … #define HDP_VERSION__REV_MASK … //HDP_CLK_CNTL #define HDP_CLK_CNTL__REG_CLK_ENABLE_COUNT__SHIFT … #define HDP_CLK_CNTL__REG_WAKE_DYN_CLK__SHIFT … #define HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE__SHIFT … #define HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE__SHIFT … #define HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE__SHIFT … #define HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE__SHIFT … #define HDP_CLK_CNTL__REG_CLK_ENABLE_COUNT_MASK … #define HDP_CLK_CNTL__REG_WAKE_DYN_CLK_MASK … #define HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK … #define HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK … #define HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK … #define HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK … //HDP_MEMIO_CNTL #define HDP_MEMIO_CNTL__MEMIO_SEND__SHIFT … #define HDP_MEMIO_CNTL__MEMIO_OP__SHIFT … #define HDP_MEMIO_CNTL__MEMIO_BE__SHIFT … #define HDP_MEMIO_CNTL__MEMIO_WR_STROBE__SHIFT … #define HDP_MEMIO_CNTL__MEMIO_RD_STROBE__SHIFT … #define HDP_MEMIO_CNTL__MEMIO_ADDR_UPPER__SHIFT … #define HDP_MEMIO_CNTL__MEMIO_CLR_WR_ERROR__SHIFT … #define HDP_MEMIO_CNTL__MEMIO_CLR_RD_ERROR__SHIFT … #define HDP_MEMIO_CNTL__MEMIO_VF__SHIFT … #define HDP_MEMIO_CNTL__MEMIO_VFID__SHIFT … #define HDP_MEMIO_CNTL__MEMIO_SEND_MASK … #define HDP_MEMIO_CNTL__MEMIO_OP_MASK … #define HDP_MEMIO_CNTL__MEMIO_BE_MASK … #define HDP_MEMIO_CNTL__MEMIO_WR_STROBE_MASK … #define HDP_MEMIO_CNTL__MEMIO_RD_STROBE_MASK … #define HDP_MEMIO_CNTL__MEMIO_ADDR_UPPER_MASK … #define HDP_MEMIO_CNTL__MEMIO_CLR_WR_ERROR_MASK … #define HDP_MEMIO_CNTL__MEMIO_CLR_RD_ERROR_MASK … #define HDP_MEMIO_CNTL__MEMIO_VF_MASK … #define HDP_MEMIO_CNTL__MEMIO_VFID_MASK … //HDP_MEMIO_ADDR #define HDP_MEMIO_ADDR__MEMIO_ADDR_LOWER__SHIFT … #define HDP_MEMIO_ADDR__MEMIO_ADDR_LOWER_MASK … //HDP_MEMIO_STATUS #define HDP_MEMIO_STATUS__MEMIO_WR_STATUS__SHIFT … #define HDP_MEMIO_STATUS__MEMIO_RD_STATUS__SHIFT … #define HDP_MEMIO_STATUS__MEMIO_WR_ERROR__SHIFT … #define HDP_MEMIO_STATUS__MEMIO_RD_ERROR__SHIFT … #define HDP_MEMIO_STATUS__MEMIO_WR_STATUS_MASK … #define HDP_MEMIO_STATUS__MEMIO_RD_STATUS_MASK … #define HDP_MEMIO_STATUS__MEMIO_WR_ERROR_MASK … #define HDP_MEMIO_STATUS__MEMIO_RD_ERROR_MASK … //HDP_MEMIO_WR_DATA #define HDP_MEMIO_WR_DATA__MEMIO_WR_DATA__SHIFT … #define HDP_MEMIO_WR_DATA__MEMIO_WR_DATA_MASK … //HDP_MEMIO_RD_DATA #define HDP_MEMIO_RD_DATA__MEMIO_RD_DATA__SHIFT … #define HDP_MEMIO_RD_DATA__MEMIO_RD_DATA_MASK … //HDP_XDP_DIRECT2HDP_FIRST #define HDP_XDP_DIRECT2HDP_FIRST__RESERVED__SHIFT … #define HDP_XDP_DIRECT2HDP_FIRST__RESERVED_MASK … //HDP_XDP_D2H_FLUSH #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_FLUSH_NUM__SHIFT … #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ENC_DATA__SHIFT … #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ADDR_SEL__SHIFT … #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_XPB_CLG__SHIFT … #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_SEND_HOST__SHIFT … #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_ALTER_FLUSH_NUM__SHIFT … #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_0__SHIFT … #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_1__SHIFT … #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_FLUSH_NUM_MASK … #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ENC_DATA_MASK … #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ADDR_SEL_MASK … #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_XPB_CLG_MASK … #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_SEND_HOST_MASK … #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_ALTER_FLUSH_NUM_MASK … #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_0_MASK … #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_1_MASK … //HDP_XDP_D2H_BAR_UPDATE #define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_ADDR__SHIFT … #define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_FLUSH_NUM__SHIFT … #define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_BAR_NUM__SHIFT … #define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_ADDR_MASK … #define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_FLUSH_NUM_MASK … #define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_BAR_NUM_MASK … //HDP_XDP_D2H_RSVD_3 #define HDP_XDP_D2H_RSVD_3__RESERVED__SHIFT … #define HDP_XDP_D2H_RSVD_3__RESERVED_MASK … //HDP_XDP_D2H_RSVD_4 #define HDP_XDP_D2H_RSVD_4__RESERVED__SHIFT … #define HDP_XDP_D2H_RSVD_4__RESERVED_MASK … //HDP_XDP_D2H_RSVD_5 #define HDP_XDP_D2H_RSVD_5__RESERVED__SHIFT … #define HDP_XDP_D2H_RSVD_5__RESERVED_MASK … //HDP_XDP_D2H_RSVD_6 #define HDP_XDP_D2H_RSVD_6__RESERVED__SHIFT … #define HDP_XDP_D2H_RSVD_6__RESERVED_MASK … //HDP_XDP_D2H_RSVD_7 #define HDP_XDP_D2H_RSVD_7__RESERVED__SHIFT … #define HDP_XDP_D2H_RSVD_7__RESERVED_MASK … //HDP_XDP_D2H_RSVD_8 #define HDP_XDP_D2H_RSVD_8__RESERVED__SHIFT … #define HDP_XDP_D2H_RSVD_8__RESERVED_MASK … //HDP_XDP_D2H_RSVD_9 #define HDP_XDP_D2H_RSVD_9__RESERVED__SHIFT … #define HDP_XDP_D2H_RSVD_9__RESERVED_MASK … //HDP_XDP_D2H_RSVD_10 #define HDP_XDP_D2H_RSVD_10__RESERVED__SHIFT … #define HDP_XDP_D2H_RSVD_10__RESERVED_MASK … //HDP_XDP_D2H_RSVD_11 #define HDP_XDP_D2H_RSVD_11__RESERVED__SHIFT … #define HDP_XDP_D2H_RSVD_11__RESERVED_MASK … //HDP_XDP_D2H_RSVD_12 #define HDP_XDP_D2H_RSVD_12__RESERVED__SHIFT … #define HDP_XDP_D2H_RSVD_12__RESERVED_MASK … //HDP_XDP_D2H_RSVD_13 #define HDP_XDP_D2H_RSVD_13__RESERVED__SHIFT … #define HDP_XDP_D2H_RSVD_13__RESERVED_MASK … //HDP_XDP_D2H_RSVD_14 #define HDP_XDP_D2H_RSVD_14__RESERVED__SHIFT … #define HDP_XDP_D2H_RSVD_14__RESERVED_MASK … //HDP_XDP_D2H_RSVD_15 #define HDP_XDP_D2H_RSVD_15__RESERVED__SHIFT … #define HDP_XDP_D2H_RSVD_15__RESERVED_MASK … //HDP_XDP_D2H_RSVD_16 #define HDP_XDP_D2H_RSVD_16__RESERVED__SHIFT … #define HDP_XDP_D2H_RSVD_16__RESERVED_MASK … //HDP_XDP_D2H_RSVD_17 #define HDP_XDP_D2H_RSVD_17__RESERVED__SHIFT … #define HDP_XDP_D2H_RSVD_17__RESERVED_MASK … //HDP_XDP_D2H_RSVD_18 #define HDP_XDP_D2H_RSVD_18__RESERVED__SHIFT … #define HDP_XDP_D2H_RSVD_18__RESERVED_MASK … //HDP_XDP_D2H_RSVD_19 #define HDP_XDP_D2H_RSVD_19__RESERVED__SHIFT … #define HDP_XDP_D2H_RSVD_19__RESERVED_MASK … //HDP_XDP_D2H_RSVD_20 #define HDP_XDP_D2H_RSVD_20__RESERVED__SHIFT … #define HDP_XDP_D2H_RSVD_20__RESERVED_MASK … //HDP_XDP_D2H_RSVD_21 #define HDP_XDP_D2H_RSVD_21__RESERVED__SHIFT … #define HDP_XDP_D2H_RSVD_21__RESERVED_MASK … //HDP_XDP_D2H_RSVD_22 #define HDP_XDP_D2H_RSVD_22__RESERVED__SHIFT … #define HDP_XDP_D2H_RSVD_22__RESERVED_MASK … //HDP_XDP_D2H_RSVD_23 #define HDP_XDP_D2H_RSVD_23__RESERVED__SHIFT … #define HDP_XDP_D2H_RSVD_23__RESERVED_MASK … //HDP_XDP_D2H_RSVD_24 #define HDP_XDP_D2H_RSVD_24__RESERVED__SHIFT … #define HDP_XDP_D2H_RSVD_24__RESERVED_MASK … //HDP_XDP_D2H_RSVD_25 #define HDP_XDP_D2H_RSVD_25__RESERVED__SHIFT … #define HDP_XDP_D2H_RSVD_25__RESERVED_MASK … //HDP_XDP_D2H_RSVD_26 #define HDP_XDP_D2H_RSVD_26__RESERVED__SHIFT … #define HDP_XDP_D2H_RSVD_26__RESERVED_MASK … //HDP_XDP_D2H_RSVD_27 #define HDP_XDP_D2H_RSVD_27__RESERVED__SHIFT … #define HDP_XDP_D2H_RSVD_27__RESERVED_MASK … //HDP_XDP_D2H_RSVD_28 #define HDP_XDP_D2H_RSVD_28__RESERVED__SHIFT … #define HDP_XDP_D2H_RSVD_28__RESERVED_MASK … //HDP_XDP_D2H_RSVD_29 #define HDP_XDP_D2H_RSVD_29__RESERVED__SHIFT … #define HDP_XDP_D2H_RSVD_29__RESERVED_MASK … //HDP_XDP_D2H_RSVD_30 #define HDP_XDP_D2H_RSVD_30__RESERVED__SHIFT … #define HDP_XDP_D2H_RSVD_30__RESERVED_MASK … //HDP_XDP_D2H_RSVD_31 #define HDP_XDP_D2H_RSVD_31__RESERVED__SHIFT … #define HDP_XDP_D2H_RSVD_31__RESERVED_MASK … //HDP_XDP_D2H_RSVD_32 #define HDP_XDP_D2H_RSVD_32__RESERVED__SHIFT … #define HDP_XDP_D2H_RSVD_32__RESERVED_MASK … //HDP_XDP_D2H_RSVD_33 #define HDP_XDP_D2H_RSVD_33__RESERVED__SHIFT … #define HDP_XDP_D2H_RSVD_33__RESERVED_MASK … //HDP_XDP_D2H_RSVD_34 #define HDP_XDP_D2H_RSVD_34__RESERVED__SHIFT … #define HDP_XDP_D2H_RSVD_34__RESERVED_MASK … //HDP_XDP_DIRECT2HDP_LAST #define HDP_XDP_DIRECT2HDP_LAST__RESERVED__SHIFT … #define HDP_XDP_DIRECT2HDP_LAST__RESERVED_MASK … //HDP_XDP_P2P_BAR_CFG #define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_ADDR_SIZE__SHIFT … #define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_BAR_FROM__SHIFT … #define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_ADDR_SIZE_MASK … #define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_BAR_FROM_MASK … //HDP_XDP_P2P_MBX_OFFSET #define HDP_XDP_P2P_MBX_OFFSET__P2P_MBX_OFFSET__SHIFT … #define HDP_XDP_P2P_MBX_OFFSET__P2P_MBX_OFFSET_MASK … //HDP_XDP_P2P_MBX_ADDR0 #define HDP_XDP_P2P_MBX_ADDR0__VALID__SHIFT … #define HDP_XDP_P2P_MBX_ADDR0__ADDR_35_19__SHIFT … #define HDP_XDP_P2P_MBX_ADDR0__ADDR_39_36__SHIFT … #define HDP_XDP_P2P_MBX_ADDR0__ADDR_47_40__SHIFT … #define HDP_XDP_P2P_MBX_ADDR0__VALID_MASK … #define HDP_XDP_P2P_MBX_ADDR0__ADDR_35_19_MASK … #define HDP_XDP_P2P_MBX_ADDR0__ADDR_39_36_MASK … #define HDP_XDP_P2P_MBX_ADDR0__ADDR_47_40_MASK … //HDP_XDP_P2P_MBX_ADDR1 #define HDP_XDP_P2P_MBX_ADDR1__VALID__SHIFT … #define HDP_XDP_P2P_MBX_ADDR1__ADDR_35_19__SHIFT … #define HDP_XDP_P2P_MBX_ADDR1__ADDR_39_36__SHIFT … #define HDP_XDP_P2P_MBX_ADDR1__ADDR_47_40__SHIFT … #define HDP_XDP_P2P_MBX_ADDR1__VALID_MASK … #define HDP_XDP_P2P_MBX_ADDR1__ADDR_35_19_MASK … #define HDP_XDP_P2P_MBX_ADDR1__ADDR_39_36_MASK … #define HDP_XDP_P2P_MBX_ADDR1__ADDR_47_40_MASK … //HDP_XDP_P2P_MBX_ADDR2 #define HDP_XDP_P2P_MBX_ADDR2__VALID__SHIFT … #define HDP_XDP_P2P_MBX_ADDR2__ADDR_35_19__SHIFT … #define HDP_XDP_P2P_MBX_ADDR2__ADDR_39_36__SHIFT … #define HDP_XDP_P2P_MBX_ADDR2__ADDR_47_40__SHIFT … #define HDP_XDP_P2P_MBX_ADDR2__VALID_MASK … #define HDP_XDP_P2P_MBX_ADDR2__ADDR_35_19_MASK … #define HDP_XDP_P2P_MBX_ADDR2__ADDR_39_36_MASK … #define HDP_XDP_P2P_MBX_ADDR2__ADDR_47_40_MASK … //HDP_XDP_P2P_MBX_ADDR3 #define HDP_XDP_P2P_MBX_ADDR3__VALID__SHIFT … #define HDP_XDP_P2P_MBX_ADDR3__ADDR_35_19__SHIFT … #define HDP_XDP_P2P_MBX_ADDR3__ADDR_39_36__SHIFT … #define HDP_XDP_P2P_MBX_ADDR3__ADDR_47_40__SHIFT … #define HDP_XDP_P2P_MBX_ADDR3__VALID_MASK … #define HDP_XDP_P2P_MBX_ADDR3__ADDR_35_19_MASK … #define HDP_XDP_P2P_MBX_ADDR3__ADDR_39_36_MASK … #define HDP_XDP_P2P_MBX_ADDR3__ADDR_47_40_MASK … //HDP_XDP_P2P_MBX_ADDR4 #define HDP_XDP_P2P_MBX_ADDR4__VALID__SHIFT … #define HDP_XDP_P2P_MBX_ADDR4__ADDR_35_19__SHIFT … #define HDP_XDP_P2P_MBX_ADDR4__ADDR_39_36__SHIFT … #define HDP_XDP_P2P_MBX_ADDR4__ADDR_47_40__SHIFT … #define HDP_XDP_P2P_MBX_ADDR4__VALID_MASK … #define HDP_XDP_P2P_MBX_ADDR4__ADDR_35_19_MASK … #define HDP_XDP_P2P_MBX_ADDR4__ADDR_39_36_MASK … #define HDP_XDP_P2P_MBX_ADDR4__ADDR_47_40_MASK … //HDP_XDP_P2P_MBX_ADDR5 #define HDP_XDP_P2P_MBX_ADDR5__VALID__SHIFT … #define HDP_XDP_P2P_MBX_ADDR5__ADDR_35_19__SHIFT … #define HDP_XDP_P2P_MBX_ADDR5__ADDR_39_36__SHIFT … #define HDP_XDP_P2P_MBX_ADDR5__ADDR_47_40__SHIFT … #define HDP_XDP_P2P_MBX_ADDR5__VALID_MASK … #define HDP_XDP_P2P_MBX_ADDR5__ADDR_35_19_MASK … #define HDP_XDP_P2P_MBX_ADDR5__ADDR_39_36_MASK … #define HDP_XDP_P2P_MBX_ADDR5__ADDR_47_40_MASK … //HDP_XDP_P2P_MBX_ADDR6 #define HDP_XDP_P2P_MBX_ADDR6__VALID__SHIFT … #define HDP_XDP_P2P_MBX_ADDR6__ADDR_35_19__SHIFT … #define HDP_XDP_P2P_MBX_ADDR6__ADDR_39_36__SHIFT … #define HDP_XDP_P2P_MBX_ADDR6__ADDR_47_40__SHIFT … #define HDP_XDP_P2P_MBX_ADDR6__VALID_MASK … #define HDP_XDP_P2P_MBX_ADDR6__ADDR_35_19_MASK … #define HDP_XDP_P2P_MBX_ADDR6__ADDR_39_36_MASK … #define HDP_XDP_P2P_MBX_ADDR6__ADDR_47_40_MASK … //HDP_XDP_HDP_MBX_MC_CFG #define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_QOS__SHIFT … #define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_SWAP__SHIFT … #define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_VMID__SHIFT … #define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_RO__SHIFT … #define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_GCC__SHIFT … #define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_SNOOP__SHIFT … #define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_QOS_MASK … #define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_SWAP_MASK … #define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_VMID_MASK … #define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_RO_MASK … #define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_GCC_MASK … #define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_SNOOP_MASK … //HDP_XDP_HDP_MC_CFG #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_SNOOP__SHIFT … #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_SWAP__SHIFT … #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_VMID__SHIFT … #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_RO__SHIFT … #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_GCC__SHIFT … #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_XDP_HIGHER_PRI_THRESH__SHIFT … #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_SNOOP_MASK … #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_SWAP_MASK … #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_VMID_MASK … #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_RO_MASK … #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_GCC_MASK … #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_XDP_HIGHER_PRI_THRESH_MASK … //HDP_XDP_HST_CFG #define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_EN__SHIFT … #define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_TIMER__SHIFT … #define HDP_XDP_HST_CFG__HST_CFG_WR_BURST_EN__SHIFT … #define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_64B_EN__SHIFT … #define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_TIMER_PRELOAD_CFG__SHIFT … #define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_EN_MASK … #define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_TIMER_MASK … #define HDP_XDP_HST_CFG__HST_CFG_WR_BURST_EN_MASK … #define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_64B_EN_MASK … #define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_TIMER_PRELOAD_CFG_MASK … //HDP_XDP_HDP_IPH_CFG #define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_SYS_FIFO_DEPTH_OVERRIDE__SHIFT … #define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_XDP_FIFO_DEPTH_OVERRIDE__SHIFT … #define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_INVERSE_PEER_TAG_MATCHING__SHIFT … #define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_P2P_RD_EN__SHIFT … #define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_SYS_FIFO_DEPTH_OVERRIDE_MASK … #define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_XDP_FIFO_DEPTH_OVERRIDE_MASK … #define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_INVERSE_PEER_TAG_MATCHING_MASK … #define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_P2P_RD_EN_MASK … //HDP_XDP_P2P_BAR0 #define HDP_XDP_P2P_BAR0__ADDR__SHIFT … #define HDP_XDP_P2P_BAR0__FLUSH__SHIFT … #define HDP_XDP_P2P_BAR0__VALID__SHIFT … #define HDP_XDP_P2P_BAR0__ADDR_MASK … #define HDP_XDP_P2P_BAR0__FLUSH_MASK … #define HDP_XDP_P2P_BAR0__VALID_MASK … //HDP_XDP_P2P_BAR1 #define HDP_XDP_P2P_BAR1__ADDR__SHIFT … #define HDP_XDP_P2P_BAR1__FLUSH__SHIFT … #define HDP_XDP_P2P_BAR1__VALID__SHIFT … #define HDP_XDP_P2P_BAR1__ADDR_MASK … #define HDP_XDP_P2P_BAR1__FLUSH_MASK … #define HDP_XDP_P2P_BAR1__VALID_MASK … //HDP_XDP_P2P_BAR2 #define HDP_XDP_P2P_BAR2__ADDR__SHIFT … #define HDP_XDP_P2P_BAR2__FLUSH__SHIFT … #define HDP_XDP_P2P_BAR2__VALID__SHIFT … #define HDP_XDP_P2P_BAR2__ADDR_MASK … #define HDP_XDP_P2P_BAR2__FLUSH_MASK … #define HDP_XDP_P2P_BAR2__VALID_MASK … //HDP_XDP_P2P_BAR3 #define HDP_XDP_P2P_BAR3__ADDR__SHIFT … #define HDP_XDP_P2P_BAR3__FLUSH__SHIFT … #define HDP_XDP_P2P_BAR3__VALID__SHIFT … #define HDP_XDP_P2P_BAR3__ADDR_MASK … #define HDP_XDP_P2P_BAR3__FLUSH_MASK … #define HDP_XDP_P2P_BAR3__VALID_MASK … //HDP_XDP_P2P_BAR4 #define HDP_XDP_P2P_BAR4__ADDR__SHIFT … #define HDP_XDP_P2P_BAR4__FLUSH__SHIFT … #define HDP_XDP_P2P_BAR4__VALID__SHIFT … #define HDP_XDP_P2P_BAR4__ADDR_MASK … #define HDP_XDP_P2P_BAR4__FLUSH_MASK … #define HDP_XDP_P2P_BAR4__VALID_MASK … //HDP_XDP_P2P_BAR5 #define HDP_XDP_P2P_BAR5__ADDR__SHIFT … #define HDP_XDP_P2P_BAR5__FLUSH__SHIFT … #define HDP_XDP_P2P_BAR5__VALID__SHIFT … #define HDP_XDP_P2P_BAR5__ADDR_MASK … #define HDP_XDP_P2P_BAR5__FLUSH_MASK … #define HDP_XDP_P2P_BAR5__VALID_MASK … //HDP_XDP_P2P_BAR6 #define HDP_XDP_P2P_BAR6__ADDR__SHIFT … #define HDP_XDP_P2P_BAR6__FLUSH__SHIFT … #define HDP_XDP_P2P_BAR6__VALID__SHIFT … #define HDP_XDP_P2P_BAR6__ADDR_MASK … #define HDP_XDP_P2P_BAR6__FLUSH_MASK … #define HDP_XDP_P2P_BAR6__VALID_MASK … //HDP_XDP_P2P_BAR7 #define HDP_XDP_P2P_BAR7__ADDR__SHIFT … #define HDP_XDP_P2P_BAR7__FLUSH__SHIFT … #define HDP_XDP_P2P_BAR7__VALID__SHIFT … #define HDP_XDP_P2P_BAR7__ADDR_MASK … #define HDP_XDP_P2P_BAR7__FLUSH_MASK … #define HDP_XDP_P2P_BAR7__VALID_MASK … //HDP_XDP_FLUSH_ARMED_STS #define HDP_XDP_FLUSH_ARMED_STS__FLUSH_ARMED_STS__SHIFT … #define HDP_XDP_FLUSH_ARMED_STS__FLUSH_ARMED_STS_MASK … //HDP_XDP_FLUSH_CNTR0_STS #define HDP_XDP_FLUSH_CNTR0_STS__FLUSH_CNTR0_STS__SHIFT … #define HDP_XDP_FLUSH_CNTR0_STS__FLUSH_CNTR0_STS_MASK … //HDP_XDP_BUSY_STS #define HDP_XDP_BUSY_STS__BUSY_BITS__SHIFT … #define HDP_XDP_BUSY_STS__BUSY_BITS_MASK … //HDP_XDP_STICKY #define HDP_XDP_STICKY__STICKY_STS__SHIFT … #define HDP_XDP_STICKY__STICKY_W1C__SHIFT … #define HDP_XDP_STICKY__STICKY_STS_MASK … #define HDP_XDP_STICKY__STICKY_W1C_MASK … //HDP_XDP_CHKN #define HDP_XDP_CHKN__CHKN_0_RSVD__SHIFT … #define HDP_XDP_CHKN__CHKN_1_RSVD__SHIFT … #define HDP_XDP_CHKN__CHKN_2_RSVD__SHIFT … #define HDP_XDP_CHKN__CHKN_3_RSVD__SHIFT … #define HDP_XDP_CHKN__CHKN_0_RSVD_MASK … #define HDP_XDP_CHKN__CHKN_1_RSVD_MASK … #define HDP_XDP_CHKN__CHKN_2_RSVD_MASK … #define HDP_XDP_CHKN__CHKN_3_RSVD_MASK … //HDP_XDP_BARS_ADDR_39_36 #define HDP_XDP_BARS_ADDR_39_36__BAR0_ADDR_39_36__SHIFT … #define HDP_XDP_BARS_ADDR_39_36__BAR1_ADDR_39_36__SHIFT … #define HDP_XDP_BARS_ADDR_39_36__BAR2_ADDR_39_36__SHIFT … #define HDP_XDP_BARS_ADDR_39_36__BAR3_ADDR_39_36__SHIFT … #define HDP_XDP_BARS_ADDR_39_36__BAR4_ADDR_39_36__SHIFT … #define HDP_XDP_BARS_ADDR_39_36__BAR5_ADDR_39_36__SHIFT … #define HDP_XDP_BARS_ADDR_39_36__BAR6_ADDR_39_36__SHIFT … #define HDP_XDP_BARS_ADDR_39_36__BAR7_ADDR_39_36__SHIFT … #define HDP_XDP_BARS_ADDR_39_36__BAR0_ADDR_39_36_MASK … #define HDP_XDP_BARS_ADDR_39_36__BAR1_ADDR_39_36_MASK … #define HDP_XDP_BARS_ADDR_39_36__BAR2_ADDR_39_36_MASK … #define HDP_XDP_BARS_ADDR_39_36__BAR3_ADDR_39_36_MASK … #define HDP_XDP_BARS_ADDR_39_36__BAR4_ADDR_39_36_MASK … #define HDP_XDP_BARS_ADDR_39_36__BAR5_ADDR_39_36_MASK … #define HDP_XDP_BARS_ADDR_39_36__BAR6_ADDR_39_36_MASK … #define HDP_XDP_BARS_ADDR_39_36__BAR7_ADDR_39_36_MASK … //HDP_XDP_MC_VM_FB_LOCATION_BASE #define HDP_XDP_MC_VM_FB_LOCATION_BASE__FB_BASE__SHIFT … #define HDP_XDP_MC_VM_FB_LOCATION_BASE__FB_BASE_MASK … //HDP_XDP_GPU_IOV_VIOLATION_LOG #define HDP_XDP_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS__SHIFT … #define HDP_XDP_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS__SHIFT … #define HDP_XDP_GPU_IOV_VIOLATION_LOG__ADDRESS__SHIFT … #define HDP_XDP_GPU_IOV_VIOLATION_LOG__OPCODE__SHIFT … #define HDP_XDP_GPU_IOV_VIOLATION_LOG__VF__SHIFT … #define HDP_XDP_GPU_IOV_VIOLATION_LOG__VFID__SHIFT … #define HDP_XDP_GPU_IOV_VIOLATION_LOG__INITIATOR_ID__SHIFT … #define HDP_XDP_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS_MASK … #define HDP_XDP_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS_MASK … #define HDP_XDP_GPU_IOV_VIOLATION_LOG__ADDRESS_MASK … #define HDP_XDP_GPU_IOV_VIOLATION_LOG__OPCODE_MASK … #define HDP_XDP_GPU_IOV_VIOLATION_LOG__VF_MASK … #define HDP_XDP_GPU_IOV_VIOLATION_LOG__VFID_MASK … #define HDP_XDP_GPU_IOV_VIOLATION_LOG__INITIATOR_ID_MASK … //HDP_XDP_MMHUB_ERROR #define HDP_XDP_MMHUB_ERROR__HDP_BRESP_01__SHIFT … #define HDP_XDP_MMHUB_ERROR__HDP_BRESP_10__SHIFT … #define HDP_XDP_MMHUB_ERROR__HDP_BRESP_11__SHIFT … #define HDP_XDP_MMHUB_ERROR__HDP_BUSER_NACK_01__SHIFT … #define HDP_XDP_MMHUB_ERROR__HDP_BUSER_NACK_10__SHIFT … #define HDP_XDP_MMHUB_ERROR__HDP_BUSER_NACK_11__SHIFT … #define HDP_XDP_MMHUB_ERROR__HDP_RRESP_01__SHIFT … #define HDP_XDP_MMHUB_ERROR__HDP_RRESP_10__SHIFT … #define HDP_XDP_MMHUB_ERROR__HDP_RRESP_11__SHIFT … #define HDP_XDP_MMHUB_ERROR__HDP_RUSER_NACK_01__SHIFT … #define HDP_XDP_MMHUB_ERROR__HDP_RUSER_NACK_10__SHIFT … #define HDP_XDP_MMHUB_ERROR__HDP_RUSER_NACK_11__SHIFT … #define HDP_XDP_MMHUB_ERROR__XDP_BRESP_01__SHIFT … #define HDP_XDP_MMHUB_ERROR__XDP_BRESP_10__SHIFT … #define HDP_XDP_MMHUB_ERROR__XDP_BRESP_11__SHIFT … #define HDP_XDP_MMHUB_ERROR__XDP_BUSER_NACK_01__SHIFT … #define HDP_XDP_MMHUB_ERROR__XDP_BUSER_NACK_10__SHIFT … #define HDP_XDP_MMHUB_ERROR__XDP_BUSER_NACK_11__SHIFT … #define HDP_XDP_MMHUB_ERROR__HDP_BRESP_01_MASK … #define HDP_XDP_MMHUB_ERROR__HDP_BRESP_10_MASK … #define HDP_XDP_MMHUB_ERROR__HDP_BRESP_11_MASK … #define HDP_XDP_MMHUB_ERROR__HDP_BUSER_NACK_01_MASK … #define HDP_XDP_MMHUB_ERROR__HDP_BUSER_NACK_10_MASK … #define HDP_XDP_MMHUB_ERROR__HDP_BUSER_NACK_11_MASK … #define HDP_XDP_MMHUB_ERROR__HDP_RRESP_01_MASK … #define HDP_XDP_MMHUB_ERROR__HDP_RRESP_10_MASK … #define HDP_XDP_MMHUB_ERROR__HDP_RRESP_11_MASK … #define HDP_XDP_MMHUB_ERROR__HDP_RUSER_NACK_01_MASK … #define HDP_XDP_MMHUB_ERROR__HDP_RUSER_NACK_10_MASK … #define HDP_XDP_MMHUB_ERROR__HDP_RUSER_NACK_11_MASK … #define HDP_XDP_MMHUB_ERROR__XDP_BRESP_01_MASK … #define HDP_XDP_MMHUB_ERROR__XDP_BRESP_10_MASK … #define HDP_XDP_MMHUB_ERROR__XDP_BRESP_11_MASK … #define HDP_XDP_MMHUB_ERROR__XDP_BUSER_NACK_01_MASK … #define HDP_XDP_MMHUB_ERROR__XDP_BUSER_NACK_10_MASK … #define HDP_XDP_MMHUB_ERROR__XDP_BUSER_NACK_11_MASK … #endif
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