linux/drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c

/*
 * Copyright 2020 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 */
#include "amdgpu.h"
#include "amdgpu_atombios.h"
#include "hdp_v4_0.h"
#include "amdgpu_ras.h"

#include "hdp/hdp_4_0_offset.h"
#include "hdp/hdp_4_0_sh_mask.h"
#include <uapi/linux/kfd_ioctl.h>

/* for Vega20 register name change */
#define mmHDP_MEM_POWER_CTRL …
#define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK …
#define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK …
#define HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK …
#define HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK …
#define mmHDP_MEM_POWER_CTRL_BASE_IDX …

static void hdp_v4_0_flush_hdp(struct amdgpu_device *adev,
				struct amdgpu_ring *ring)
{ … }

static void hdp_v4_0_invalidate_hdp(struct amdgpu_device *adev,
				    struct amdgpu_ring *ring)
{ … }

static void hdp_v4_0_query_ras_error_count(struct amdgpu_device *adev,
					   void *ras_error_status)
{
	struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;

	err_data->ue_count = 0;
	err_data->ce_count = 0;

	if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__HDP))
		return;

	/* HDP SRAM errors are uncorrectable ones (i.e. fatal errors) */
	err_data->ue_count += RREG32_SOC15(HDP, 0, mmHDP_EDC_CNT);
};

static void hdp_v4_0_reset_ras_error_count(struct amdgpu_device *adev)
{ … }

static void hdp_v4_0_update_clock_gating(struct amdgpu_device *adev,
					 bool enable)
{ … }

static void hdp_v4_0_get_clockgating_state(struct amdgpu_device *adev,
					    u64 *flags)
{ … }

static void hdp_v4_0_init_registers(struct amdgpu_device *adev)
{ … }

struct amdgpu_ras_block_hw_ops hdp_v4_0_ras_hw_ops = …;

struct amdgpu_hdp_ras hdp_v4_0_ras = …;

const struct amdgpu_hdp_funcs hdp_v4_0_funcs = …;