/* * Copyright 2017 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * * Authors: AMD * */ #ifndef DM_PP_SMU_IF__H #define DM_PP_SMU_IF__H /* * interface to PPLIB/SMU to setup clocks and pstate requirements on SoC */ enum pp_smu_ver { … }; struct pp_smu { … }; enum pp_smu_status { … }; #define PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN … #define PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX … enum wm_type { … }; /* This structure is a copy of WatermarkRowGeneric_t defined by smuxx_driver_if.h*/ struct pp_smu_wm_set_range { … }; #define MAX_WATERMARK_SETS … struct pp_smu_wm_range_sets { … }; struct pp_smu_funcs_rv { … }; /* Used by pp_smu_funcs_nv.set_voltage_by_freq * */ enum pp_smu_nv_clock_id { … }; /* * Used by pp_smu_funcs_nv.get_maximum_sustainable_clocks */ struct pp_smu_nv_clock_table { … }; struct pp_smu_funcs_nv { … }; #define PP_SMU_NUM_SOCCLK_DPM_LEVELS … #define PP_SMU_NUM_DCFCLK_DPM_LEVELS … #define PP_SMU_NUM_FCLK_DPM_LEVELS … #define PP_SMU_NUM_MEMCLK_DPM_LEVELS … #define PP_SMU_NUM_DCLK_DPM_LEVELS … #define PP_SMU_NUM_VCLK_DPM_LEVELS … #define PP_SMU_NUM_VPECLK_DPM_LEVELS … struct dpm_clock { … }; /* this is a copy of the structure defined in smuxx_driver_if.h*/ struct dpm_clocks { … }; struct pp_smu_funcs_rn { … }; struct pp_smu_funcs_vgh { … }; struct pp_smu_funcs { … }; #endif /* DM_PP_SMU_IF__H */
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