/* * Copyright 2019 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. */ #ifndef __AMDGPU_SMU_H__ #define __AMDGPU_SMU_H__ #include <linux/acpi_amd_wbrf.h> #include <linux/units.h> #include "amdgpu.h" #include "kgd_pp_interface.h" #include "dm_pp_interface.h" #include "dm_pp_smu.h" #include "smu_types.h" #include "linux/firmware.h" #define SMU_THERMAL_MINIMUM_ALERT_TEMP … #define SMU_THERMAL_MAXIMUM_ALERT_TEMP … #define SMU_TEMPERATURE_UNITS_PER_CENTIGRADES … #define SMU_FW_NAME_LEN … #define SMU_DPM_USER_PROFILE_RESTORE … #define SMU_CUSTOM_FAN_SPEED_RPM … #define SMU_CUSTOM_FAN_SPEED_PWM … // Power Throttlers #define SMU_THROTTLER_PPT0_BIT … #define SMU_THROTTLER_PPT1_BIT … #define SMU_THROTTLER_PPT2_BIT … #define SMU_THROTTLER_PPT3_BIT … #define SMU_THROTTLER_SPL_BIT … #define SMU_THROTTLER_FPPT_BIT … #define SMU_THROTTLER_SPPT_BIT … #define SMU_THROTTLER_SPPT_APU_BIT … // Current Throttlers #define SMU_THROTTLER_TDC_GFX_BIT … #define SMU_THROTTLER_TDC_SOC_BIT … #define SMU_THROTTLER_TDC_MEM_BIT … #define SMU_THROTTLER_TDC_VDD_BIT … #define SMU_THROTTLER_TDC_CVIP_BIT … #define SMU_THROTTLER_EDC_CPU_BIT … #define SMU_THROTTLER_EDC_GFX_BIT … #define SMU_THROTTLER_APCC_BIT … // Temperature #define SMU_THROTTLER_TEMP_GPU_BIT … #define SMU_THROTTLER_TEMP_CORE_BIT … #define SMU_THROTTLER_TEMP_MEM_BIT … #define SMU_THROTTLER_TEMP_EDGE_BIT … #define SMU_THROTTLER_TEMP_HOTSPOT_BIT … #define SMU_THROTTLER_TEMP_SOC_BIT … #define SMU_THROTTLER_TEMP_VR_GFX_BIT … #define SMU_THROTTLER_TEMP_VR_SOC_BIT … #define SMU_THROTTLER_TEMP_VR_MEM0_BIT … #define SMU_THROTTLER_TEMP_VR_MEM1_BIT … #define SMU_THROTTLER_TEMP_LIQUID0_BIT … #define SMU_THROTTLER_TEMP_LIQUID1_BIT … #define SMU_THROTTLER_VRHOT0_BIT … #define SMU_THROTTLER_VRHOT1_BIT … #define SMU_THROTTLER_PROCHOT_CPU_BIT … #define SMU_THROTTLER_PROCHOT_GFX_BIT … // Other #define SMU_THROTTLER_PPM_BIT … #define SMU_THROTTLER_FIT_BIT … struct smu_hw_power_state { … }; struct smu_power_state; enum smu_state_ui_label { … }; enum smu_state_classification_flag { … }; struct smu_state_classification_block { … }; struct smu_state_pcie_block { … }; enum smu_refreshrate_source { … }; struct smu_state_display_block { … }; struct smu_state_memory_block { … }; struct smu_state_software_algorithm_block { … }; struct smu_temperature_range { … }; struct smu_state_validation_block { … }; struct smu_uvd_clocks { … }; /** * Structure to hold a SMU Power State. */ struct smu_power_state { … }; enum smu_power_src_type { … }; enum smu_ppt_limit_type { … }; enum smu_ppt_limit_level { … }; enum smu_memory_pool_size { … }; struct smu_user_dpm_profile { … }; #define SMU_TABLE_INIT(tables, table_id, s, a, d) … struct smu_table { … }; enum smu_perf_level_designation { … }; struct smu_performance_level { … }; struct smu_clock_info { … }; struct smu_bios_boot_up_values { … }; enum smu_table_id { … }; struct smu_table_context { … }; struct smu_context; struct smu_dpm_policy; struct smu_dpm_policy_desc { … }; struct smu_dpm_policy { … }; struct smu_dpm_policy_ctxt { … }; struct smu_dpm_context { … }; struct smu_power_gate { … }; struct smu_power_context { … }; #define SMU_FEATURE_MAX … struct smu_feature { … }; struct smu_clocks { … }; #define MAX_REGULAR_DPM_NUM … struct mclk_latency_entries { … }; struct mclock_latency_table { … }; enum smu_reset_mode { … }; enum smu_baco_state { … }; struct smu_baco_context { … }; struct smu_freq_info { … }; struct pstates_clk_freq { … }; struct smu_umd_pstate_table { … }; struct cmn2asic_msg_mapping { … }; struct cmn2asic_mapping { … }; struct stb_context { … }; enum smu_fw_status { … }; #define WORKLOAD_POLICY_MAX … /* * Configure wbrf event handling pace as there can be only one * event processed every SMU_WBRF_EVENT_HANDLING_PACE ms. */ #define SMU_WBRF_EVENT_HANDLING_PACE … struct smu_context { … }; struct i2c_adapter; /** * struct pptable_funcs - Callbacks used to interact with the SMU. */ struct pptable_funcs { … }; MetricsMember_t; enum smu_cmn2asic_mapping_type { … }; enum smu_baco_seq { … }; #define MSG_MAP(msg, index, flags) … #define CLK_MAP(clk, index) … #define FEA_MAP(fea) … #define FEA_MAP_REVERSE(fea) … #define FEA_MAP_HALF_REVERSE(fea) … #define TAB_MAP(tab) … #define TAB_MAP_VALID(tab) … #define TAB_MAP_INVALID(tab) … #define PWR_MAP(tab) … #define WORKLOAD_MAP(profile, workload) … /** * smu_memcpy_trailing - Copy the end of one structure into the middle of another * * @dst: Pointer to destination struct * @first_dst_member: The member name in @dst where the overwrite begins * @last_dst_member: The member name in @dst where the overwrite ends after * @src: Pointer to the source struct * @first_src_member: The member name in @src where the copy begins * */ #define smu_memcpy_trailing(dst, first_dst_member, last_dst_member, \ src, first_src_member) … WifiOneBand_t; WifiBandEntryTable_t; #define STR_SOC_PSTATE_POLICY … #define STR_XGMI_PLPD_POLICY … struct smu_dpm_policy *smu_get_pm_policy(struct smu_context *smu, enum pp_pm_policy p_type); #if !defined(SWSMU_CODE_LAYER_L2) && !defined(SWSMU_CODE_LAYER_L3) && !defined(SWSMU_CODE_LAYER_L4) int smu_get_power_limit(void *handle, uint32_t *limit, enum pp_power_limit_level pp_limit_level, enum pp_power_type pp_power_type); bool smu_mode1_reset_is_support(struct smu_context *smu); bool smu_mode2_reset_is_support(struct smu_context *smu); int smu_mode1_reset(struct smu_context *smu); extern const struct amd_ip_funcs smu_ip_funcs; bool is_support_sw_smu(struct amdgpu_device *adev); bool is_support_cclk_dpm(struct amdgpu_device *adev); int smu_write_watermarks_table(struct smu_context *smu); int smu_get_dpm_freq_range(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t *min, uint32_t *max); int smu_set_soft_freq_range(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t min, uint32_t max); int smu_set_gfx_power_up_by_imu(struct smu_context *smu); int smu_set_ac_dc(struct smu_context *smu); int smu_set_xgmi_plpd_mode(struct smu_context *smu, enum pp_xgmi_plpd_mode mode); int smu_get_entrycount_gfxoff(struct smu_context *smu, u64 *value); int smu_get_residency_gfxoff(struct smu_context *smu, u32 *value); int smu_set_residency_gfxoff(struct smu_context *smu, bool value); int smu_get_status_gfxoff(struct smu_context *smu, uint32_t *value); int smu_handle_passthrough_sbr(struct smu_context *smu, bool enable); int smu_wait_for_event(struct smu_context *smu, enum smu_event_type event, uint64_t event_arg); int smu_get_ecc_info(struct smu_context *smu, void *umc_ecc); int smu_stb_collect_info(struct smu_context *smu, void *buff, uint32_t size); void amdgpu_smu_stb_debug_fs_init(struct amdgpu_device *adev); int smu_send_hbm_bad_pages_num(struct smu_context *smu, uint32_t size); int smu_send_hbm_bad_channel_flag(struct smu_context *smu, uint32_t size); int smu_send_rma_reason(struct smu_context *smu); int smu_set_pm_policy(struct smu_context *smu, enum pp_pm_policy p_type, int level); ssize_t smu_get_pm_policy_info(struct smu_context *smu, enum pp_pm_policy p_type, char *sysbuf); #endif #endif
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