linux/drivers/gpu/drm/amd/amdgpu/smu_v13_0_10.c

/*
 * Copyright 2023 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 */

#include "smu_v13_0_10.h"
#include "amdgpu_reset.h"
#include "amdgpu_dpm.h"
#include "amdgpu_job.h"
#include "amdgpu_ring.h"
#include "amdgpu_ras.h"
#include "amdgpu_psp.h"

static bool smu_v13_0_10_is_mode2_default(struct amdgpu_reset_control *reset_ctl)
{ … }

static struct amdgpu_reset_handler *
smu_v13_0_10_get_reset_handler(struct amdgpu_reset_control *reset_ctl,
			    struct amdgpu_reset_context *reset_context)
{ … }

static int smu_v13_0_10_mode2_suspend_ip(struct amdgpu_device *adev)
{ … }

static int
smu_v13_0_10_mode2_prepare_hwcontext(struct amdgpu_reset_control *reset_ctl,
				  struct amdgpu_reset_context *reset_context)
{ … }

static int smu_v13_0_10_mode2_reset(struct amdgpu_device *adev)
{ … }

static void smu_v13_0_10_async_reset(struct work_struct *work)
{ … }
static int
smu_v13_0_10_mode2_perform_reset(struct amdgpu_reset_control *reset_ctl,
			      struct amdgpu_reset_context *reset_context)
{ … }

static int smu_v13_0_10_mode2_restore_ip(struct amdgpu_device *adev)
{ … }

static int
smu_v13_0_10_mode2_restore_hwcontext(struct amdgpu_reset_control *reset_ctl,
				  struct amdgpu_reset_context *reset_context)
{ … }

static struct amdgpu_reset_handler smu_v13_0_10_mode2_handler = …;

static struct amdgpu_reset_handler
	*smu_v13_0_10_rst_handlers[AMDGPU_RESET_MAX_HANDLERS] = …;

int smu_v13_0_10_reset_init(struct amdgpu_device *adev)
{ … }

int smu_v13_0_10_reset_fini(struct amdgpu_device *adev)
{ … }