soc21.c | Explore in Territory

/*
 * Copyright 2021 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 */
#include <linux/firmware.h>
#include <linux/slab.h>
#include <linux/module.h>
#include <linux/pci.h>

#include "amdgpu.h"
#include "amdgpu_atombios.h"
#include "amdgpu_ih.h"
#include "amdgpu_uvd.h"
#include "amdgpu_vce.h"
#include "amdgpu_ucode.h"
#include "amdgpu_psp.h"
#include "amdgpu_smu.h"
#include "atom.h"
#include "amd_pcie.h"

#include "gc/gc_11_0_0_offset.h"
#include "gc/gc_11_0_0_sh_mask.h"
#include "mp/mp_13_0_0_offset.h"

#include "soc15.h"
#include "soc15_common.h"
#include "soc21.h"
#include "mxgpu_nv.h"

static const struct amd_ip_funcs soc21_common_ip_funcs;

/* SOC21 */
static const struct amdgpu_video_codec_info vcn_4_0_0_video_codecs_encode_array_vcn0[] = …;

static const struct amdgpu_video_codec_info vcn_4_0_0_video_codecs_encode_array_vcn1[] = …;

static const struct amdgpu_video_codecs vcn_4_0_0_video_codecs_encode_vcn0 = …;

static const struct amdgpu_video_codecs vcn_4_0_0_video_codecs_encode_vcn1 = …;

static const struct amdgpu_video_codec_info vcn_4_0_0_video_codecs_decode_array_vcn0[] = …;

static const struct amdgpu_video_codec_info vcn_4_0_0_video_codecs_decode_array_vcn1[] = …;

static const struct amdgpu_video_codecs vcn_4_0_0_video_codecs_decode_vcn0 = …;

static const struct amdgpu_video_codecs vcn_4_0_0_video_codecs_decode_vcn1 = …;

/* SRIOV SOC21, not const since data is controlled by host */
static struct amdgpu_video_codec_info sriov_vcn_4_0_0_video_codecs_encode_array_vcn0[] = …;

static struct amdgpu_video_codec_info sriov_vcn_4_0_0_video_codecs_encode_array_vcn1[] = …;

static struct amdgpu_video_codecs sriov_vcn_4_0_0_video_codecs_encode_vcn0 = …;

static struct amdgpu_video_codecs sriov_vcn_4_0_0_video_codecs_encode_vcn1 = …;

static struct amdgpu_video_codec_info sriov_vcn_4_0_0_video_codecs_decode_array_vcn0[] = …;

static struct amdgpu_video_codec_info sriov_vcn_4_0_0_video_codecs_decode_array_vcn1[] = …;

static struct amdgpu_video_codecs sriov_vcn_4_0_0_video_codecs_decode_vcn0 = …;

static struct amdgpu_video_codecs sriov_vcn_4_0_0_video_codecs_decode_vcn1 = …;

static int soc21_query_video_codecs(struct amdgpu_device *adev, bool encode,
				 const struct amdgpu_video_codecs **codecs)
{ … }

static u32 soc21_didt_rreg(struct amdgpu_device *adev, u32 reg)
{ … }

static void soc21_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
{ … }

static u32 soc21_get_config_memsize(struct amdgpu_device *adev)
{ … }

static u32 soc21_get_xclk(struct amdgpu_device *adev)
{ … }


void soc21_grbm_select(struct amdgpu_device *adev,
		     u32 me, u32 pipe, u32 queue, u32 vmid)
{ … }

static bool soc21_read_disabled_bios(struct amdgpu_device *adev)
{ … }

static struct soc15_allowed_register_entry soc21_allowed_read_registers[] = …;

static uint32_t soc21_read_indexed_register(struct amdgpu_device *adev, u32 se_num,
					 u32 sh_num, u32 reg_offset)
{ … }

static uint32_t soc21_get_register_value(struct amdgpu_device *adev,
				      bool indexed, u32 se_num,
				      u32 sh_num, u32 reg_offset)
{ … }

static int soc21_read_register(struct amdgpu_device *adev, u32 se_num,
			    u32 sh_num, u32 reg_offset, u32 *value)
{ … }

#if 0
static int soc21_asic_mode1_reset(struct amdgpu_device *adev)
{
	u32 i;
	int ret = 0;

	amdgpu_atombios_scratch_regs_engine_hung(adev, true);

	/* disable BM */
	pci_clear_master(adev->pdev);

	amdgpu_device_cache_pci_state(adev->pdev);

	if (amdgpu_dpm_is_mode1_reset_supported(adev)) {
		dev_info(adev->dev, "GPU smu mode1 reset\n");
		ret = amdgpu_dpm_mode1_reset(adev);
	} else {
		dev_info(adev->dev, "GPU psp mode1 reset\n");
		ret = psp_gpu_reset(adev);
	}

	if (ret)
		dev_err(adev->dev, "GPU mode1 reset failed\n");
	amdgpu_device_load_pci_state(adev->pdev);

	/* wait for asic to come out of reset */
	for (i = 0; i < adev->usec_timeout; i++) {
		u32 memsize = adev->nbio.funcs->get_memsize(adev);

		if (memsize != 0xffffffff)
			break;
		udelay(1);
	}

	amdgpu_atombios_scratch_regs_engine_hung(adev, false);

	return ret;
}
#endif

static enum amd_reset_method
soc21_asic_reset_method(struct amdgpu_device *adev)
{ … }

static int soc21_asic_reset(struct amdgpu_device *adev)
{ … }

static int soc21_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
{ … }

static int soc21_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk)
{ … }

static void soc21_program_aspm(struct amdgpu_device *adev)
{ … }

const struct amdgpu_ip_block_version soc21_common_ip_block = …;

static bool soc21_need_full_reset(struct amdgpu_device *adev)
{ … }

static bool soc21_need_reset_on_init(struct amdgpu_device *adev)
{ … }

static void soc21_init_doorbell_index(struct amdgpu_device *adev)
{ … }

static void soc21_pre_asic_init(struct amdgpu_device *adev)
{ … }

static int soc21_update_umd_stable_pstate(struct amdgpu_device *adev,
					  bool enter)
{ … }

static const struct amdgpu_asic_funcs soc21_asic_funcs = …;

static int soc21_common_early_init(void *handle)
{ … }

static int soc21_common_late_init(void *handle)
{ … }

static int soc21_common_sw_init(void *handle)
{ … }

static int soc21_common_sw_fini(void *handle)
{ … }

static int soc21_common_hw_init(void *handle)
{ … }

static int soc21_common_hw_fini(void *handle)
{ … }

static int soc21_common_suspend(void *handle)
{ … }

static bool soc21_need_reset_on_resume(struct amdgpu_device *adev)
{ … }

static int soc21_common_resume(void *handle)
{ … }

static bool soc21_common_is_idle(void *handle)
{ … }

static int soc21_common_wait_for_idle(void *handle)
{ … }

static int soc21_common_soft_reset(void *handle)
{ … }

static int soc21_common_set_clockgating_state(void *handle,
					   enum amd_clockgating_state state)
{ … }

static int soc21_common_set_powergating_state(void *handle,
					   enum amd_powergating_state state)
{ … }

static void soc21_common_get_clockgating_state(void *handle, u64 *flags)
{ … }

static const struct amd_ip_funcs soc21_common_ip_funcs = …;
linux/drivers/gpu/drm/amd/amdgpu/soc21.c
