/* * UVD_5_0 Register documentation * * Copyright (C) 2014 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included * in all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #ifndef UVD_5_0_D_H #define UVD_5_0_D_H #define mmUVD_SEMA_ADDR_LOW … #define mmUVD_SEMA_ADDR_HIGH … #define mmUVD_SEMA_CMD … #define mmUVD_GPCOM_VCPU_CMD … #define mmUVD_GPCOM_VCPU_DATA0 … #define mmUVD_GPCOM_VCPU_DATA1 … #define mmUVD_ENGINE_CNTL … #define mmUVD_UDEC_ADDR_CONFIG … #define mmUVD_UDEC_DB_ADDR_CONFIG … #define mmUVD_UDEC_DBW_ADDR_CONFIG … #define mmUVD_NO_OP … #define mmUVD_LMI_RBC_RB_64BIT_BAR_LOW … #define mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH … #define mmUVD_LMI_RBC_IB_64BIT_BAR_LOW … #define mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH … #define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW … #define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH … #define mmUVD_SEMA_CNTL … #define mmUVD_LMI_EXT40_ADDR … #define mmUVD_CTX_INDEX … #define mmUVD_CTX_DATA … #define mmUVD_CGC_GATE … #define mmUVD_CGC_STATUS … #define mmUVD_CGC_CTRL … #define mmUVD_CGC_UDEC_STATUS … #define mmUVD_LMI_CTRL2 … #define mmUVD_MASTINT_EN … #define mmUVD_LMI_ADDR_EXT … #define mmUVD_LMI_CTRL … #define mmUVD_LMI_STATUS … #define mmUVD_LMI_SWAP_CNTL … #define mmUVD_MP_SWAP_CNTL … #define mmUVD_MPC_CNTL … #define mmUVD_MPC_SET_MUXA0 … #define mmUVD_MPC_SET_MUXA1 … #define mmUVD_MPC_SET_MUXB0 … #define mmUVD_MPC_SET_MUXB1 … #define mmUVD_MPC_SET_MUX … #define mmUVD_MPC_SET_ALU … #define mmUVD_VCPU_CACHE_OFFSET0 … #define mmUVD_VCPU_CACHE_SIZE0 … #define mmUVD_VCPU_CACHE_OFFSET1 … #define mmUVD_VCPU_CACHE_SIZE1 … #define mmUVD_VCPU_CACHE_OFFSET2 … #define mmUVD_VCPU_CACHE_SIZE2 … #define mmUVD_VCPU_CNTL … #define mmUVD_SOFT_RESET … #define mmUVD_LMI_RBC_IB_VMID … #define mmUVD_RBC_IB_SIZE … #define mmUVD_LMI_RBC_RB_VMID … #define mmUVD_RBC_RB_RPTR … #define mmUVD_RBC_RB_WPTR … #define mmUVD_RBC_RB_WPTR_CNTL … #define mmUVD_RBC_RB_CNTL … #define mmUVD_RBC_RB_RPTR_ADDR … #define mmUVD_STATUS … #define mmUVD_SEMA_TIMEOUT_STATUS … #define mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL … #define mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL … #define mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL … #define mmUVD_CONTEXT_ID … #define mmUVD_RBC_IB_SIZE_UPDATE … #define mmUVD_SUVD_CGC_GATE … #define mmUVD_SUVD_CGC_STATUS … #define mmUVD_SUVD_CGC_CTRL … #define ixUVD_LMI_VMID_INTERNAL … #define ixUVD_LMI_VMID_INTERNAL2 … #define ixUVD_LMI_CACHE_CTRL … #define ixUVD_LMI_SWAP_CNTL2 … #define ixUVD_LMI_ADDR_EXT2 … #define ixUVD_CGC_MEM_CTRL … #define ixUVD_CGC_CTRL2 … #define ixUVD_LMI_VMID_INTERNAL3 … #define mmUVD_PGFSM_CONFIG … #define mmUVD_PGFSM_READ_TILE1 … #define mmUVD_PGFSM_READ_TILE2 … #define mmUVD_POWER_STATUS … #define mmUVD_PGFSM_READ_TILE3 … #define mmUVD_PGFSM_READ_TILE4 … #define mmUVD_PGFSM_READ_TILE5 … #define mmUVD_PGFSM_READ_TILE6 … #define mmUVD_PGFSM_READ_TILE7 … #define mmUVD_MIF_CURR_ADDR_CONFIG … #define mmUVD_MIF_REF_ADDR_CONFIG … #define mmUVD_MIF_RECON1_ADDR_CONFIG … #define ixUVD_MIF_SCLR_ADDR_CONFIG … #define mmUVD_JPEG_ADDR_CONFIG … #endif /* UVD_5_0_D_H */
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