linux/drivers/gpu/drm/amd/include/asic_reg/hdp/hdp_6_0_0_offset.h

/*
 * Copyright 2021 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 */
#ifndef _hdp_6_0_0_OFFSET_HEADER
#define _hdp_6_0_0_OFFSET_HEADER



// addressBlock: hdp_hdpdec
// base address: 0x3c80
#define regHDP_NONSURFACE_BASE
#define regHDP_NONSURFACE_BASE_BASE_IDX
#define regHDP_NONSURFACE_INFO
#define regHDP_NONSURFACE_INFO_BASE_IDX
#define regHDP_NONSURFACE_BASE_HI
#define regHDP_NONSURFACE_BASE_HI_BASE_IDX
#define regHDP_SURFACE_WRITE_FLAGS
#define regHDP_SURFACE_WRITE_FLAGS_BASE_IDX
#define regHDP_SURFACE_READ_FLAGS
#define regHDP_SURFACE_READ_FLAGS_BASE_IDX
#define regHDP_SURFACE_WRITE_FLAGS_CLR
#define regHDP_SURFACE_WRITE_FLAGS_CLR_BASE_IDX
#define regHDP_SURFACE_READ_FLAGS_CLR
#define regHDP_SURFACE_READ_FLAGS_CLR_BASE_IDX
#define regHDP_NONSURF_FLAGS
#define regHDP_NONSURF_FLAGS_BASE_IDX
#define regHDP_NONSURF_FLAGS_CLR
#define regHDP_NONSURF_FLAGS_CLR_BASE_IDX
#define regHDP_HOST_PATH_CNTL
#define regHDP_HOST_PATH_CNTL_BASE_IDX
#define regHDP_SW_SEMAPHORE
#define regHDP_SW_SEMAPHORE_BASE_IDX
#define regHDP_DEBUG0
#define regHDP_DEBUG0_BASE_IDX
#define regHDP_LAST_SURFACE_HIT
#define regHDP_LAST_SURFACE_HIT_BASE_IDX
#define regHDP_OUTSTANDING_REQ
#define regHDP_OUTSTANDING_REQ_BASE_IDX
#define regHDP_MISC_CNTL
#define regHDP_MISC_CNTL_BASE_IDX
#define regHDP_MEM_POWER_CTRL
#define regHDP_MEM_POWER_CTRL_BASE_IDX
#define regHDP_MMHUB_CNTL
#define regHDP_MMHUB_CNTL_BASE_IDX
#define regHDP_VERSION
#define regHDP_VERSION_BASE_IDX
#define regHDP_CLK_CNTL
#define regHDP_CLK_CNTL_BASE_IDX
#define regHDP_MEMIO_CNTL
#define regHDP_MEMIO_CNTL_BASE_IDX
#define regHDP_MEMIO_ADDR
#define regHDP_MEMIO_ADDR_BASE_IDX
#define regHDP_MEMIO_STATUS
#define regHDP_MEMIO_STATUS_BASE_IDX
#define regHDP_MEMIO_WR_DATA
#define regHDP_MEMIO_WR_DATA_BASE_IDX
#define regHDP_MEMIO_RD_DATA
#define regHDP_MEMIO_RD_DATA_BASE_IDX
#define regHDP_XDP_DIRECT2HDP_FIRST
#define regHDP_XDP_DIRECT2HDP_FIRST_BASE_IDX
#define regHDP_XDP_D2H_FLUSH
#define regHDP_XDP_D2H_FLUSH_BASE_IDX
#define regHDP_XDP_D2H_BAR_UPDATE
#define regHDP_XDP_D2H_BAR_UPDATE_BASE_IDX
#define regHDP_XDP_D2H_RSVD_3
#define regHDP_XDP_D2H_RSVD_3_BASE_IDX
#define regHDP_XDP_D2H_RSVD_4
#define regHDP_XDP_D2H_RSVD_4_BASE_IDX
#define regHDP_XDP_D2H_RSVD_5
#define regHDP_XDP_D2H_RSVD_5_BASE_IDX
#define regHDP_XDP_D2H_RSVD_6
#define regHDP_XDP_D2H_RSVD_6_BASE_IDX
#define regHDP_XDP_D2H_RSVD_7
#define regHDP_XDP_D2H_RSVD_7_BASE_IDX
#define regHDP_XDP_D2H_RSVD_8
#define regHDP_XDP_D2H_RSVD_8_BASE_IDX
#define regHDP_XDP_D2H_RSVD_9
#define regHDP_XDP_D2H_RSVD_9_BASE_IDX
#define regHDP_XDP_D2H_RSVD_10
#define regHDP_XDP_D2H_RSVD_10_BASE_IDX
#define regHDP_XDP_D2H_RSVD_11
#define regHDP_XDP_D2H_RSVD_11_BASE_IDX
#define regHDP_XDP_D2H_RSVD_12
#define regHDP_XDP_D2H_RSVD_12_BASE_IDX
#define regHDP_XDP_D2H_RSVD_13
#define regHDP_XDP_D2H_RSVD_13_BASE_IDX
#define regHDP_XDP_D2H_RSVD_14
#define regHDP_XDP_D2H_RSVD_14_BASE_IDX
#define regHDP_XDP_D2H_RSVD_15
#define regHDP_XDP_D2H_RSVD_15_BASE_IDX
#define regHDP_XDP_D2H_RSVD_16
#define regHDP_XDP_D2H_RSVD_16_BASE_IDX
#define regHDP_XDP_D2H_RSVD_17
#define regHDP_XDP_D2H_RSVD_17_BASE_IDX
#define regHDP_XDP_D2H_RSVD_18
#define regHDP_XDP_D2H_RSVD_18_BASE_IDX
#define regHDP_XDP_D2H_RSVD_19
#define regHDP_XDP_D2H_RSVD_19_BASE_IDX
#define regHDP_XDP_D2H_RSVD_20
#define regHDP_XDP_D2H_RSVD_20_BASE_IDX
#define regHDP_XDP_D2H_RSVD_21
#define regHDP_XDP_D2H_RSVD_21_BASE_IDX
#define regHDP_XDP_D2H_RSVD_22
#define regHDP_XDP_D2H_RSVD_22_BASE_IDX
#define regHDP_XDP_D2H_RSVD_23
#define regHDP_XDP_D2H_RSVD_23_BASE_IDX
#define regHDP_XDP_D2H_RSVD_24
#define regHDP_XDP_D2H_RSVD_24_BASE_IDX
#define regHDP_XDP_D2H_RSVD_25
#define regHDP_XDP_D2H_RSVD_25_BASE_IDX
#define regHDP_XDP_D2H_RSVD_26
#define regHDP_XDP_D2H_RSVD_26_BASE_IDX
#define regHDP_XDP_D2H_RSVD_27
#define regHDP_XDP_D2H_RSVD_27_BASE_IDX
#define regHDP_XDP_D2H_RSVD_28
#define regHDP_XDP_D2H_RSVD_28_BASE_IDX
#define regHDP_XDP_D2H_RSVD_29
#define regHDP_XDP_D2H_RSVD_29_BASE_IDX
#define regHDP_XDP_D2H_RSVD_30
#define regHDP_XDP_D2H_RSVD_30_BASE_IDX
#define regHDP_XDP_D2H_RSVD_31
#define regHDP_XDP_D2H_RSVD_31_BASE_IDX
#define regHDP_XDP_D2H_RSVD_32
#define regHDP_XDP_D2H_RSVD_32_BASE_IDX
#define regHDP_XDP_D2H_RSVD_33
#define regHDP_XDP_D2H_RSVD_33_BASE_IDX
#define regHDP_XDP_D2H_RSVD_34
#define regHDP_XDP_D2H_RSVD_34_BASE_IDX
#define regHDP_XDP_DIRECT2HDP_LAST
#define regHDP_XDP_DIRECT2HDP_LAST_BASE_IDX
#define regHDP_XDP_P2P_BAR_CFG
#define regHDP_XDP_P2P_BAR_CFG_BASE_IDX
#define regHDP_XDP_P2P_MBX_OFFSET
#define regHDP_XDP_P2P_MBX_OFFSET_BASE_IDX
#define regHDP_XDP_P2P_MBX_ADDR0
#define regHDP_XDP_P2P_MBX_ADDR0_BASE_IDX
#define regHDP_XDP_P2P_MBX_ADDR1
#define regHDP_XDP_P2P_MBX_ADDR1_BASE_IDX
#define regHDP_XDP_P2P_MBX_ADDR2
#define regHDP_XDP_P2P_MBX_ADDR2_BASE_IDX
#define regHDP_XDP_P2P_MBX_ADDR3
#define regHDP_XDP_P2P_MBX_ADDR3_BASE_IDX
#define regHDP_XDP_P2P_MBX_ADDR4
#define regHDP_XDP_P2P_MBX_ADDR4_BASE_IDX
#define regHDP_XDP_P2P_MBX_ADDR5
#define regHDP_XDP_P2P_MBX_ADDR5_BASE_IDX
#define regHDP_XDP_P2P_MBX_ADDR6
#define regHDP_XDP_P2P_MBX_ADDR6_BASE_IDX
#define regHDP_XDP_HDP_MBX_MC_CFG
#define regHDP_XDP_HDP_MBX_MC_CFG_BASE_IDX
#define regHDP_XDP_HDP_MC_CFG
#define regHDP_XDP_HDP_MC_CFG_BASE_IDX
#define regHDP_XDP_HST_CFG
#define regHDP_XDP_HST_CFG_BASE_IDX
#define regHDP_XDP_HDP_IPH_CFG
#define regHDP_XDP_HDP_IPH_CFG_BASE_IDX
#define regHDP_XDP_P2P_BAR0
#define regHDP_XDP_P2P_BAR0_BASE_IDX
#define regHDP_XDP_P2P_BAR1
#define regHDP_XDP_P2P_BAR1_BASE_IDX
#define regHDP_XDP_P2P_BAR2
#define regHDP_XDP_P2P_BAR2_BASE_IDX
#define regHDP_XDP_P2P_BAR3
#define regHDP_XDP_P2P_BAR3_BASE_IDX
#define regHDP_XDP_P2P_BAR4
#define regHDP_XDP_P2P_BAR4_BASE_IDX
#define regHDP_XDP_P2P_BAR5
#define regHDP_XDP_P2P_BAR5_BASE_IDX
#define regHDP_XDP_P2P_BAR6
#define regHDP_XDP_P2P_BAR6_BASE_IDX
#define regHDP_XDP_P2P_BAR7
#define regHDP_XDP_P2P_BAR7_BASE_IDX
#define regHDP_XDP_FLUSH_ARMED_STS
#define regHDP_XDP_FLUSH_ARMED_STS_BASE_IDX
#define regHDP_XDP_FLUSH_CNTR0_STS
#define regHDP_XDP_FLUSH_CNTR0_STS_BASE_IDX
#define regHDP_XDP_BUSY_STS
#define regHDP_XDP_BUSY_STS_BASE_IDX
#define regHDP_XDP_STICKY
#define regHDP_XDP_STICKY_BASE_IDX
#define regHDP_XDP_CHKN
#define regHDP_XDP_CHKN_BASE_IDX
#define regHDP_XDP_BARS_ADDR_39_36
#define regHDP_XDP_BARS_ADDR_39_36_BASE_IDX
#define regHDP_XDP_MC_VM_FB_LOCATION_BASE
#define regHDP_XDP_MC_VM_FB_LOCATION_BASE_BASE_IDX
#define regHDP_XDP_MMHUB_ERROR
#define regHDP_XDP_MMHUB_ERROR_BASE_IDX

#endif