/* * Copyright (C) 2017 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included * in all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #if !defined (_vega10_ENUM_HEADER) #define _vega10_ENUM_HEADER #ifndef _DRIVER_BUILD #ifndef GL_ZERO #define GL__ZERO … #define GL__ONE … #define GL__SRC_COLOR … #define GL__ONE_MINUS_SRC_COLOR … #define GL__DST_COLOR … #define GL__ONE_MINUS_DST_COLOR … #define GL__SRC_ALPHA … #define GL__ONE_MINUS_SRC_ALPHA … #define GL__DST_ALPHA … #define GL__ONE_MINUS_DST_ALPHA … #define GL__SRC_ALPHA_SATURATE … #define GL__CONSTANT_COLOR … #define GL__ONE_MINUS_CONSTANT_COLOR … #define GL__CONSTANT_ALPHA … #define GL__ONE_MINUS_CONSTANT_ALPHA … #endif #endif /******************************************************* * GDS DATA_TYPE Enums *******************************************************/ #ifndef ENUMS_GDS_PERFCOUNT_SELECT_H #define ENUMS_GDS_PERFCOUNT_SELECT_H GDS_PERFCOUNT_SELECT; #endif /*ENUMS_GDS_PERFCOUNT_SELECT_H*/ /******************************************************* * Chip Enums *******************************************************/ /* * MEM_PWR_FORCE_CTRL enum */ MEM_PWR_FORCE_CTRL; /* * MEM_PWR_FORCE_CTRL2 enum */ MEM_PWR_FORCE_CTRL2; /* * MEM_PWR_DIS_CTRL enum */ MEM_PWR_DIS_CTRL; /* * MEM_PWR_SEL_CTRL enum */ MEM_PWR_SEL_CTRL; /* * MEM_PWR_SEL_CTRL2 enum */ MEM_PWR_SEL_CTRL2; /* * RowSize enum */ RowSize; /* * SurfaceEndian enum */ SurfaceEndian; /* * ArrayMode enum */ ArrayMode; /* * NumPipes enum */ NumPipes; /* * NumBanksConfig enum */ NumBanksConfig; /* * PipeInterleaveSize enum */ PipeInterleaveSize; /* * BankInterleaveSize enum */ BankInterleaveSize; /* * NumShaderEngines enum */ NumShaderEngines; /* * NumRbPerShaderEngine enum */ NumRbPerShaderEngine; /* * NumGPUs enum */ NumGPUs; /* * NumMaxCompressedFragments enum */ NumMaxCompressedFragments; /* * ShaderEngineTileSize enum */ ShaderEngineTileSize; /* * MultiGPUTileSize enum */ MultiGPUTileSize; /* * NumLowerPipes enum */ NumLowerPipes; /* * ColorTransform enum */ ColorTransform; /* * CompareRef enum */ CompareRef; /* * ReadSize enum */ ReadSize; /* * DepthFormat enum */ DepthFormat; /* * ZFormat enum */ ZFormat; /* * StencilFormat enum */ StencilFormat; /* * CmaskMode enum */ CmaskMode; /* * QuadExportFormat enum */ QuadExportFormat; /* * QuadExportFormatOld enum */ QuadExportFormatOld; /* * ColorFormat enum */ ColorFormat; /* * SurfaceFormat enum */ SurfaceFormat; /* * BUF_DATA_FORMAT enum */ BUF_DATA_FORMAT; /* * IMG_DATA_FORMAT enum */ IMG_DATA_FORMAT; /* * BUF_NUM_FORMAT enum */ BUF_NUM_FORMAT; /* * IMG_NUM_FORMAT enum */ IMG_NUM_FORMAT; /* * IMG_NUM_FORMAT_FMASK enum */ IMG_NUM_FORMAT_FMASK; /* * IMG_NUM_FORMAT_N_IN_16 enum */ IMG_NUM_FORMAT_N_IN_16; /* * IMG_NUM_FORMAT_ASTC_2D enum */ IMG_NUM_FORMAT_ASTC_2D; /* * IMG_NUM_FORMAT_ASTC_3D enum */ IMG_NUM_FORMAT_ASTC_3D; /* * TileType enum */ TileType; /* * NonDispTilingOrder enum */ NonDispTilingOrder; /* * MicroTileMode enum */ MicroTileMode; /* * TileSplit enum */ TileSplit; /* * SampleSplit enum */ SampleSplit; /* * PipeConfig enum */ PipeConfig; /* * SeEnable enum */ SeEnable; /* * NumBanks enum */ NumBanks; /* * BankWidth enum */ BankWidth; /* * BankHeight enum */ BankHeight; /* * BankWidthHeight enum */ BankWidthHeight; /* * MacroTileAspect enum */ MacroTileAspect; /* * GATCL1RequestType enum */ GATCL1RequestType; /* * UTCL1RequestType enum */ UTCL1RequestType; /* * UTCL1FaultType enum */ UTCL1FaultType; /* * TCC_CACHE_POLICIES enum */ TCC_CACHE_POLICIES; /* * MTYPE enum */ MTYPE; /* * RMI_CID enum */ RMI_CID; /* * PERFMON_COUNTER_MODE enum */ PERFMON_COUNTER_MODE; /* * PERFMON_SPM_MODE enum */ PERFMON_SPM_MODE; /* * SurfaceTiling enum */ SurfaceTiling; /* * SurfaceArray enum */ SurfaceArray; /* * ColorArray enum */ ColorArray; /* * DepthArray enum */ DepthArray; /* * ENUM_NUM_SIMD_PER_CU enum */ ENUM_NUM_SIMD_PER_CU; /* * DSM_ENABLE_ERROR_INJECT enum */ DSM_ENABLE_ERROR_INJECT; /* * DSM_SELECT_INJECT_DELAY enum */ DSM_SELECT_INJECT_DELAY; /* * SWIZZLE_TYPE_ENUM enum */ SWIZZLE_TYPE_ENUM; /* * TC_MICRO_TILE_MODE enum */ TC_MICRO_TILE_MODE; /* * SWIZZLE_MODE_ENUM enum */ SWIZZLE_MODE_ENUM; /* * PipeTiling enum */ PipeTiling; /* * BankTiling enum */ BankTiling; /* * GroupInterleave enum */ GroupInterleave; /* * RowTiling enum */ RowTiling; /* * BankSwapBytes enum */ BankSwapBytes; /* * SampleSplitBytes enum */ SampleSplitBytes; /******************************************************* * AZSTREAM Enums *******************************************************/ /* * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR enum */ OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR; /* * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR enum */ OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR; /* * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS enum */ OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS; /* * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY enum */ OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY; /* * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE enum */ OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE; /* * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE enum */ OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE; /* * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE enum */ OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE; /* * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN enum */ OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN; /* * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET enum */ OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET; /* * OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE enum */ OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE; /* * OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE enum */ OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE; /* * OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR enum */ OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR; /* * OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE enum */ OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE; /* * OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS enum */ OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS; /******************************************************* * BLNDV Enums *******************************************************/ /* * BLNDV_CONTROL_BLND_MODE enum */ BLNDV_CONTROL_BLND_MODE; /* * BLNDV_CONTROL_BLND_STEREO_TYPE enum */ BLNDV_CONTROL_BLND_STEREO_TYPE; /* * BLNDV_CONTROL_BLND_STEREO_POLARITY enum */ BLNDV_CONTROL_BLND_STEREO_POLARITY; /* * BLNDV_CONTROL_BLND_FEEDTHROUGH_EN enum */ BLNDV_CONTROL_BLND_FEEDTHROUGH_EN; /* * BLNDV_CONTROL_BLND_ALPHA_MODE enum */ BLNDV_CONTROL_BLND_ALPHA_MODE; /* * BLNDV_CONTROL_BLND_ACTIVE_OVERLAP_ONLY enum */ BLNDV_CONTROL_BLND_ACTIVE_OVERLAP_ONLY; /* * BLNDV_CONTROL_BLND_MULTIPLIED_MODE enum */ BLNDV_CONTROL_BLND_MULTIPLIED_MODE; /* * BLNDV_SM_CONTROL2_SM_MODE enum */ BLNDV_SM_CONTROL2_SM_MODE; /* * BLNDV_SM_CONTROL2_SM_FRAME_ALTERNATE enum */ BLNDV_SM_CONTROL2_SM_FRAME_ALTERNATE; /* * BLNDV_SM_CONTROL2_SM_FIELD_ALTERNATE enum */ BLNDV_SM_CONTROL2_SM_FIELD_ALTERNATE; /* * BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL enum */ BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL; /* * BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL enum */ BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL; /* * BLNDV_CONTROL2_PTI_ENABLE enum */ BLNDV_CONTROL2_PTI_ENABLE; /* * BLNDV_CONTROL2_BLND_SUPERAA_DEGAMMA_EN enum */ BLNDV_CONTROL2_BLND_SUPERAA_DEGAMMA_EN; /* * BLNDV_CONTROL2_BLND_SUPERAA_REGAMMA_EN enum */ BLNDV_CONTROL2_BLND_SUPERAA_REGAMMA_EN; /* * BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK enum */ BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK; /* * BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK enum */ BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK; /* * BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK enum */ BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK; /* * BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK enum */ BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK; /* * BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK enum */ BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK; /* * BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK enum */ BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK; /* * BLNDV_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK enum */ BLNDV_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK; /* * BLNDV_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK enum */ BLNDV_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK; /* * BLNDV_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE enum */ BLNDV_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE; /* * BLNDV_DEBUG_BLND_CNV_MUX_SELECT enum */ BLNDV_DEBUG_BLND_CNV_MUX_SELECT; /* * BLNDV_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN enum */ BLNDV_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN; /******************************************************* * LBV Enums *******************************************************/ /* * LBV_PIXEL_DEPTH enum */ LBV_PIXEL_DEPTH; /* * LBV_PIXEL_EXPAN_MODE enum */ LBV_PIXEL_EXPAN_MODE; /* * LBV_INTERLEAVE_EN enum */ LBV_INTERLEAVE_EN; /* * LBV_PIXEL_REDUCE_MODE enum */ LBV_PIXEL_REDUCE_MODE; /* * LBV_DYNAMIC_PIXEL_DEPTH enum */ LBV_DYNAMIC_PIXEL_DEPTH; /* * LBV_DITHER_EN enum */ LBV_DITHER_EN; /* * LBV_DOWNSCALE_PREFETCH_EN enum */ LBV_DOWNSCALE_PREFETCH_EN; /* * LBV_MEMORY_CONFIG enum */ LBV_MEMORY_CONFIG; /* * LBV_SYNC_RESET_SEL2 enum */ LBV_SYNC_RESET_SEL2; /* * LBV_SYNC_DURATION enum */ LBV_SYNC_DURATION; /******************************************************* * CRTC Enums *******************************************************/ /* * CRTC_CONTROL_CRTC_START_POINT_CNTL enum */ CRTC_CONTROL_CRTC_START_POINT_CNTL; /* * CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL enum */ CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL; /* * CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL enum */ CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL; /* * CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY enum */ CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY; /* * CRTC_CONTROL_CRTC_DISP_READ_REQUEST_DISABLE enum */ CRTC_CONTROL_CRTC_DISP_READ_REQUEST_DISABLE; /* * CRTC_CONTROL_CRTC_SOF_PULL_EN enum */ CRTC_CONTROL_CRTC_SOF_PULL_EN; /* * CRTC_H_SYNC_B_CNTL_CRTC_H_SYNC_B_POL enum */ CRTC_H_SYNC_B_CNTL_CRTC_H_SYNC_B_POL; /* * CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MAX_SEL enum */ CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MAX_SEL; /* * CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MIN_SEL enum */ CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MIN_SEL; /* * CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_EN enum */ CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_EN; /* * CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_TO_MASTER_VSYNC enum */ CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_TO_MASTER_VSYNC; /* * CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_ON_EVENT enum */ CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_ON_EVENT; /* * CRTC_V_TOTAL_INT_STATUS_CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK enum */ CRTC_V_TOTAL_INT_STATUS_CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK; /* * CRTC_VSYNC_NOM_INT_STATUS_CRTC_VSYNC_NOM_INT_CLEAR enum */ CRTC_VSYNC_NOM_INT_STATUS_CRTC_VSYNC_NOM_INT_CLEAR; /* * CRTC_V_SYNC_B_CNTL_CRTC_V_SYNC_B_POL enum */ CRTC_V_SYNC_B_CNTL_CRTC_V_SYNC_B_POL; /* * CRTC_DTMTEST_CNTL_CRTC_DTMTEST_CRTC_EN enum */ CRTC_DTMTEST_CNTL_CRTC_DTMTEST_CRTC_EN; /* * CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT enum */ CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT; /* * CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT enum */ CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT; /* * CRTC_TRIGA_CNTL_CRTC_TRIGA_RESYNC_BYPASS_EN enum */ CRTC_TRIGA_CNTL_CRTC_TRIGA_RESYNC_BYPASS_EN; /* * CRTC_TRIGA_CNTL_CRTC_TRIGA_CLEAR enum */ CRTC_TRIGA_CNTL_CRTC_TRIGA_CLEAR; /* * CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT enum */ CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT; /* * CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT enum */ CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT; /* * CRTC_TRIGB_CNTL_CRTC_TRIGB_RESYNC_BYPASS_EN enum */ CRTC_TRIGB_CNTL_CRTC_TRIGB_RESYNC_BYPASS_EN; /* * CRTC_TRIGB_CNTL_CRTC_TRIGB_CLEAR enum */ CRTC_TRIGB_CNTL_CRTC_TRIGB_CLEAR; /* * CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE enum */ CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE; /* * CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CHECK enum */ CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CHECK; /* * CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_TRIG_SEL enum */ CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_TRIG_SEL; /* * CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CLEAR enum */ CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CLEAR; /* * CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT enum */ CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT; /* * CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_POLARITY enum */ CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_POLARITY; /* * CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_GRANULARITY enum */ CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_GRANULARITY; /* * CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE enum */ CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE; /* * CRTC_CONTROL_CRTC_MASTER_EN enum */ CRTC_CONTROL_CRTC_MASTER_EN; /* * CRTC_BLANK_CONTROL_CRTC_BLANK_DATA_EN enum */ CRTC_BLANK_CONTROL_CRTC_BLANK_DATA_EN; /* * CRTC_BLANK_CONTROL_CRTC_BLANK_DE_MODE enum */ CRTC_BLANK_CONTROL_CRTC_BLANK_DE_MODE; /* * CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_ENABLE enum */ CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_ENABLE; /* * CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD enum */ CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD; /* * CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_INDICATION_OUTPUT_POLARITY enum */ CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_INDICATION_OUTPUT_POLARITY; /* * CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_ALIGNMENT enum */ CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_ALIGNMENT; /* * CRTC_COUNT_CONTROL_CRTC_HORZ_COUNT_BY2_EN enum */ CRTC_COUNT_CONTROL_CRTC_HORZ_COUNT_BY2_EN; /* * CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE enum */ CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE; /* * CRTC_VERT_SYNC_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR enum */ CRTC_VERT_SYNC_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR; /* * CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE enum */ CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE; /* * CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_OUTPUT_POLARITY enum */ CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_OUTPUT_POLARITY; /* * CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_SELECT_POLARITY enum */ CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_SELECT_POLARITY; /* * CRTC_STEREO_CONTROL_CRTC_STEREO_EYE_FLAG_POLARITY enum */ CRTC_STEREO_CONTROL_CRTC_STEREO_EYE_FLAG_POLARITY; /* * CRTC_STEREO_CONTROL_CRTC_STEREO_EN enum */ CRTC_STEREO_CONTROL_CRTC_STEREO_EN; /* * CRTC_SNAPSHOT_STATUS_CRTC_SNAPSHOT_CLEAR enum */ CRTC_SNAPSHOT_STATUS_CRTC_SNAPSHOT_CLEAR; /* * CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL enum */ CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL; /* * CRTC_START_LINE_CONTROL_CRTC_PROGRESSIVE_START_LINE_EARLY enum */ CRTC_START_LINE_CONTROL_CRTC_PROGRESSIVE_START_LINE_EARLY; /* * CRTC_START_LINE_CONTROL_CRTC_INTERLACE_START_LINE_EARLY enum */ CRTC_START_LINE_CONTROL_CRTC_INTERLACE_START_LINE_EARLY; /* * CRTC_START_LINE_CONTROL_CRTC_LEGACY_REQUESTOR_EN enum */ CRTC_START_LINE_CONTROL_CRTC_LEGACY_REQUESTOR_EN; /* * CRTC_START_LINE_CONTROL_CRTC_PREFETCH_EN enum */ CRTC_START_LINE_CONTROL_CRTC_PREFETCH_EN; /* * CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_MSK enum */ CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_MSK; /* * CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_TYPE enum */ CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_TYPE; /* * CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_MSK enum */ CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_MSK; /* * CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_TYPE enum */ CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_TYPE; /* * CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_MSK enum */ CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_MSK; /* * CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_TYPE enum */ CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_TYPE; /* * CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK enum */ CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK; /* * CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE enum */ CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE; /* * CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_MSK enum */ CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_MSK; /* * CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_TYPE enum */ CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_TYPE; /* * CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_MSK enum */ CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_MSK; /* * CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_TYPE enum */ CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_TYPE; /* * CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_MSK enum */ CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_MSK; /* * CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_TYPE enum */ CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_TYPE; /* * CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_MSK enum */ CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_MSK; /* * CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_TYPE enum */ CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_TYPE; /* * CRTC_UPDATE_LOCK_CRTC_UPDATE_LOCK enum */ CRTC_UPDATE_LOCK_CRTC_UPDATE_LOCK; /* * CRTC_DOUBLE_BUFFER_CONTROL_CRTC_UPDATE_INSTANTLY enum */ CRTC_DOUBLE_BUFFER_CONTROL_CRTC_UPDATE_INSTANTLY; /* * CRTC_DOUBLE_BUFFER_CONTROL_CRTC_BLANK_DATA_DOUBLE_BUFFER_EN enum */ CRTC_DOUBLE_BUFFER_CONTROL_CRTC_BLANK_DATA_DOUBLE_BUFFER_EN; /* * CRTC_DOUBLE_BUFFER_CONTROL_CRTC_RANGE_TIMING_DBUF_UPDATE_MODE enum */ CRTC_DOUBLE_BUFFER_CONTROL_CRTC_RANGE_TIMING_DBUF_UPDATE_MODE; /* * CRTC_VGA_PARAMETER_CAPTURE_MODE_CRTC_VGA_PARAMETER_CAPTURE_MODE enum */ CRTC_VGA_PARAMETER_CAPTURE_MODE_CRTC_VGA_PARAMETER_CAPTURE_MODE; /* * CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_EN enum */ CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_EN; /* * CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE enum */ CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE; /* * CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_DYNAMIC_RANGE enum */ CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_DYNAMIC_RANGE; /* * CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT enum */ CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT; /* * MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK enum */ MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK; /* * MASTER_UPDATE_LOCK_GSL_CONTROL_MASTER_UPDATE_LOCK enum */ MASTER_UPDATE_LOCK_GSL_CONTROL_MASTER_UPDATE_LOCK; /* * MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK enum */ MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK; /* * MASTER_UPDATE_MODE_MASTER_UPDATE_MODE enum */ MASTER_UPDATE_MODE_MASTER_UPDATE_MODE; /* * MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE enum */ MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE; /* * CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE enum */ CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE; /* * CRTC_MVP_STATUS_CRTC_FLIP_NOW_CLEAR enum */ CRTC_MVP_STATUS_CRTC_FLIP_NOW_CLEAR; /* * CRTC_MVP_STATUS_CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR enum */ CRTC_MVP_STATUS_CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR; /* * CRTC_V_UPDATE_INT_STATUS_CRTC_V_UPDATE_INT_CLEAR enum */ CRTC_V_UPDATE_INT_STATUS_CRTC_V_UPDATE_INT_CLEAR; /* * CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY enum */ CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY; /* * CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_ENABLE enum */ CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_ENABLE; /* * CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_CLEAR enum */ CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_CLEAR; /* * CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_TYPE enum */ CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_TYPE; /* * CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_CLEAR enum */ CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_CLEAR; /* * CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_ENABLE enum */ CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_ENABLE; /* * CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_TYPE enum */ CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_TYPE; /* * CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_CLEAR enum */ CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_CLEAR; /* * CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_ENABLE enum */ CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_ENABLE; /* * CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_TYPE enum */ CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_TYPE; /* * CRTC_CRC_CNTL_CRTC_CRC_EN enum */ CRTC_CRC_CNTL_CRTC_CRC_EN; /* * CRTC_CRC_CNTL_CRTC_CRC_CONT_EN enum */ CRTC_CRC_CNTL_CRTC_CRC_CONT_EN; /* * CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE enum */ CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE; /* * CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE enum */ CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE; /* * CRTC_CRC_CNTL_CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS enum */ CRTC_CRC_CNTL_CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS; /* * CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT enum */ CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT; /* * CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT enum */ CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT; /* * CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE enum */ CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE; /* * CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE enum */ CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE; /* * CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE enum */ CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE; /* * CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW enum */ CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW; /* * CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE enum */ CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE; /* * CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE enum */ CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE; /* * CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY enum */ CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY; /* * CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY enum */ CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY; /* * CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_INTERLACE_MODE enum */ CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_INTERLACE_MODE; /* * CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE enum */ CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE; /* * CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_CLEAR enum */ CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_CLEAR; /* * CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE enum */ CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE; /* * CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT enum */ CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT; /* * CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_ENABLE enum */ CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_ENABLE; /* * CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_CLEAR enum */ CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_CLEAR; /* * CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_TYPE enum */ CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_TYPE; /* * CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE enum */ CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE; /* * CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR enum */ CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR; /* * CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE enum */ CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE; /* * CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_ENABLE enum */ CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_ENABLE; /* * CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_CLEAR enum */ CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_CLEAR; /* * CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_TYPE enum */ CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_TYPE; /* * CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE enum */ CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE; /* * CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_VALUE enum */ CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_VALUE; /* * CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN enum */ CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN; /* * CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_DB enum */ CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_DB; /* * CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE enum */ CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE; /* * CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_STEREO_SEL_OVR enum */ CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_STEREO_SEL_OVR; /* * CRTC_V_SYNC_A_POL enum */ CRTC_V_SYNC_A_POL; /* * CRTC_H_SYNC_A_POL enum */ CRTC_H_SYNC_A_POL; /* * CRTC_HORZ_REPETITION_COUNT enum */ CRTC_HORZ_REPETITION_COUNT; /* * CRTC_DRR_MODE_DBUF_UPDATE_MODE enum */ CRTC_DRR_MODE_DBUF_UPDATE_MODE; /******************************************************* * FMT Enums *******************************************************/ /* * FMT_CONTROL_PIXEL_ENCODING enum */ FMT_CONTROL_PIXEL_ENCODING; /* * FMT_CONTROL_SUBSAMPLING_MODE enum */ FMT_CONTROL_SUBSAMPLING_MODE; /* * FMT_CONTROL_SUBSAMPLING_ORDER enum */ FMT_CONTROL_SUBSAMPLING_ORDER; /* * FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS enum */ FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS; /* * FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE enum */ FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE; /* * FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH enum */ FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH; /* * FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH enum */ FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH; /* * FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH enum */ FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH; /* * FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL enum */ FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL; /* * FMT_BIT_DEPTH_CONTROL_25FRC_SEL enum */ FMT_BIT_DEPTH_CONTROL_25FRC_SEL; /* * FMT_BIT_DEPTH_CONTROL_50FRC_SEL enum */ FMT_BIT_DEPTH_CONTROL_50FRC_SEL; /* * FMT_BIT_DEPTH_CONTROL_75FRC_SEL enum */ FMT_BIT_DEPTH_CONTROL_75FRC_SEL; /* * FMT_TEMPORAL_DITHER_PATTERN_CONTROL_SELECT enum */ FMT_TEMPORAL_DITHER_PATTERN_CONTROL_SELECT; /* * FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0 enum */ FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0; /* * FMT_CLAMP_CNTL_COLOR_FORMAT enum */ FMT_CLAMP_CNTL_COLOR_FORMAT; /* * FMT_CRC_CNTL_CONT_EN enum */ FMT_CRC_CNTL_CONT_EN; /* * FMT_CRC_CNTL_INCLUDE_OVERSCAN enum */ FMT_CRC_CNTL_INCLUDE_OVERSCAN; /* * FMT_CRC_CNTL_ONLY_BLANKB enum */ FMT_CRC_CNTL_ONLY_BLANKB; /* * FMT_CRC_CNTL_PSR_MODE_ENABLE enum */ FMT_CRC_CNTL_PSR_MODE_ENABLE; /* * FMT_CRC_CNTL_INTERLACE_MODE enum */ FMT_CRC_CNTL_INTERLACE_MODE; /* * FMT_CRC_CNTL_EVEN_ODD_PIX_ENABLE enum */ FMT_CRC_CNTL_EVEN_ODD_PIX_ENABLE; /* * FMT_CRC_CNTL_EVEN_ODD_PIX_SELECT enum */ FMT_CRC_CNTL_EVEN_ODD_PIX_SELECT; /* * FMT_DEBUG_CNTL_COLOR_SELECT enum */ FMT_DEBUG_CNTL_COLOR_SELECT; /* * FMT_SPATIAL_DITHER_MODE enum */ FMT_SPATIAL_DITHER_MODE; /* * FMT_STEREOSYNC_OVR_POL enum */ FMT_STEREOSYNC_OVR_POL; /* * FMT_DYNAMIC_EXP_MODE enum */ FMT_DYNAMIC_EXP_MODE; /******************************************************* * HPD Enums *******************************************************/ /* * HPD_INT_CONTROL_ACK enum */ HPD_INT_CONTROL_ACK; /* * HPD_INT_CONTROL_POLARITY enum */ HPD_INT_CONTROL_POLARITY; /* * HPD_INT_CONTROL_RX_INT_ACK enum */ HPD_INT_CONTROL_RX_INT_ACK; /******************************************************* * LB Enums *******************************************************/ /* * LB_DATA_FORMAT_PIXEL_DEPTH enum */ LB_DATA_FORMAT_PIXEL_DEPTH; /* * LB_DATA_FORMAT_PIXEL_EXPAN_MODE enum */ LB_DATA_FORMAT_PIXEL_EXPAN_MODE; /* * LB_DATA_FORMAT_PIXEL_REDUCE_MODE enum */ LB_DATA_FORMAT_PIXEL_REDUCE_MODE; /* * LB_DATA_FORMAT_DYNAMIC_PIXEL_DEPTH enum */ LB_DATA_FORMAT_DYNAMIC_PIXEL_DEPTH; /* * LB_DATA_FORMAT_INTERLEAVE_EN enum */ LB_DATA_FORMAT_INTERLEAVE_EN; /* * LB_DATA_FORMAT_REQUEST_MODE enum */ LB_DATA_FORMAT_REQUEST_MODE; /* * LB_DATA_FORMAT_ALPHA_EN enum */ LB_DATA_FORMAT_ALPHA_EN; /* * LB_VLINE_START_END_VLINE_INV enum */ LB_VLINE_START_END_VLINE_INV; /* * LB_VLINE2_START_END_VLINE2_INV enum */ LB_VLINE2_START_END_VLINE2_INV; /* * LB_INTERRUPT_MASK_VBLANK_INTERRUPT_MASK enum */ LB_INTERRUPT_MASK_VBLANK_INTERRUPT_MASK; /* * LB_INTERRUPT_MASK_VLINE_INTERRUPT_MASK enum */ LB_INTERRUPT_MASK_VLINE_INTERRUPT_MASK; /* * LB_INTERRUPT_MASK_VLINE2_INTERRUPT_MASK enum */ LB_INTERRUPT_MASK_VLINE2_INTERRUPT_MASK; /* * LB_VLINE_STATUS_VLINE_ACK enum */ LB_VLINE_STATUS_VLINE_ACK; /* * LB_VLINE_STATUS_VLINE_INTERRUPT_TYPE enum */ LB_VLINE_STATUS_VLINE_INTERRUPT_TYPE; /* * LB_VLINE2_STATUS_VLINE2_ACK enum */ LB_VLINE2_STATUS_VLINE2_ACK; /* * LB_VLINE2_STATUS_VLINE2_INTERRUPT_TYPE enum */ LB_VLINE2_STATUS_VLINE2_INTERRUPT_TYPE; /* * LB_VBLANK_STATUS_VBLANK_ACK enum */ LB_VBLANK_STATUS_VBLANK_ACK; /* * LB_VBLANK_STATUS_VBLANK_INTERRUPT_TYPE enum */ LB_VBLANK_STATUS_VBLANK_INTERRUPT_TYPE; /* * LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL enum */ LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL; /* * LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL2 enum */ LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL2; /* * LB_SYNC_RESET_SEL_LB_SYNC_DURATION enum */ LB_SYNC_RESET_SEL_LB_SYNC_DURATION; /* * LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_EN enum */ LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_EN; /* * LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_REP_EN enum */ LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_REP_EN; /* * LB_BUFFER_STATUS_LB_BUFFER_EMPTY_ACK enum */ LB_BUFFER_STATUS_LB_BUFFER_EMPTY_ACK; /* * LB_BUFFER_STATUS_LB_BUFFER_FULL_ACK enum */ LB_BUFFER_STATUS_LB_BUFFER_FULL_ACK; /* * LB_MVP_AFR_FLIP_MODE_MVP_AFR_FLIP_MODE enum */ LB_MVP_AFR_FLIP_MODE_MVP_AFR_FLIP_MODE; /* * LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET enum */ LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET; /* * LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACK enum */ LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACK; /* * LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE enum */ LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE; /* * LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_AUTO_ENABLE enum */ LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_AUTO_ENABLE; /* * LB_DC_MVP_LB_CONTROL_MVP_SWAP_LOCK_IN_MODE enum */ LB_DC_MVP_LB_CONTROL_MVP_SWAP_LOCK_IN_MODE; /* * LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_SEL enum */ LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_SEL; /* * LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_ONE enum */ LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_ONE; /* * LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO enum */ LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO; /* * LB_TEST_DEBUG_INDEX_LB_TEST_DEBUG_WRITE_EN enum */ LB_TEST_DEBUG_INDEX_LB_TEST_DEBUG_WRITE_EN; /******************************************************* * DIG Enums *******************************************************/ /* * HDMI_KEEPOUT_MODE enum */ HDMI_KEEPOUT_MODE; /* * HDMI_DATA_SCRAMBLE_EN enum */ HDMI_DATA_SCRAMBLE_EN; /* * HDMI_CLOCK_CHANNEL_RATE enum */ HDMI_CLOCK_CHANNEL_RATE; /* * HDMI_NO_EXTRA_NULL_PACKET_FILLED enum */ HDMI_NO_EXTRA_NULL_PACKET_FILLED; /* * HDMI_PACKET_GEN_VERSION enum */ HDMI_PACKET_GEN_VERSION; /* * HDMI_ERROR_ACK enum */ HDMI_ERROR_ACK; /* * HDMI_ERROR_MASK enum */ HDMI_ERROR_MASK; /* * HDMI_DEEP_COLOR_DEPTH enum */ HDMI_DEEP_COLOR_DEPTH; /* * HDMI_AUDIO_DELAY_EN enum */ HDMI_AUDIO_DELAY_EN; /* * HDMI_AUDIO_SEND_MAX_PACKETS enum */ HDMI_AUDIO_SEND_MAX_PACKETS; /* * HDMI_ACR_SEND enum */ HDMI_ACR_SEND; /* * HDMI_ACR_CONT enum */ HDMI_ACR_CONT; /* * HDMI_ACR_SELECT enum */ HDMI_ACR_SELECT; /* * HDMI_ACR_SOURCE enum */ HDMI_ACR_SOURCE; /* * HDMI_ACR_N_MULTIPLE enum */ HDMI_ACR_N_MULTIPLE; /* * HDMI_ACR_AUDIO_PRIORITY enum */ HDMI_ACR_AUDIO_PRIORITY; /* * HDMI_NULL_SEND enum */ HDMI_NULL_SEND; /* * HDMI_GC_SEND enum */ HDMI_GC_SEND; /* * HDMI_GC_CONT enum */ HDMI_GC_CONT; /* * HDMI_ISRC_SEND enum */ HDMI_ISRC_SEND; /* * HDMI_ISRC_CONT enum */ HDMI_ISRC_CONT; /* * HDMI_AVI_INFO_SEND enum */ HDMI_AVI_INFO_SEND; /* * HDMI_AVI_INFO_CONT enum */ HDMI_AVI_INFO_CONT; /* * HDMI_AUDIO_INFO_SEND enum */ HDMI_AUDIO_INFO_SEND; /* * HDMI_AUDIO_INFO_CONT enum */ HDMI_AUDIO_INFO_CONT; /* * HDMI_MPEG_INFO_SEND enum */ HDMI_MPEG_INFO_SEND; /* * HDMI_MPEG_INFO_CONT enum */ HDMI_MPEG_INFO_CONT; /* * HDMI_GENERIC0_SEND enum */ HDMI_GENERIC0_SEND; /* * HDMI_GENERIC0_CONT enum */ HDMI_GENERIC0_CONT; /* * HDMI_GENERIC1_SEND enum */ HDMI_GENERIC1_SEND; /* * HDMI_GENERIC1_CONT enum */ HDMI_GENERIC1_CONT; /* * HDMI_GC_AVMUTE_CONT enum */ HDMI_GC_AVMUTE_CONT; /* * HDMI_PACKING_PHASE_OVERRIDE enum */ HDMI_PACKING_PHASE_OVERRIDE; /* * HDMI_GENERIC2_SEND enum */ HDMI_GENERIC2_SEND; /* * HDMI_GENERIC2_CONT enum */ HDMI_GENERIC2_CONT; /* * HDMI_GENERIC3_SEND enum */ HDMI_GENERIC3_SEND; /* * HDMI_GENERIC3_CONT enum */ HDMI_GENERIC3_CONT; /* * TMDS_PIXEL_ENCODING enum */ TMDS_PIXEL_ENCODING; /* * TMDS_COLOR_FORMAT enum */ TMDS_COLOR_FORMAT; /* * TMDS_STEREOSYNC_CTL_SEL_REG enum */ TMDS_STEREOSYNC_CTL_SEL_REG; /* * TMDS_CTL0_DATA_SEL enum */ TMDS_CTL0_DATA_SEL; /* * TMDS_CTL0_DATA_INVERT enum */ TMDS_CTL0_DATA_INVERT; /* * TMDS_CTL0_DATA_MODULATION enum */ TMDS_CTL0_DATA_MODULATION; /* * TMDS_CTL0_PATTERN_OUT_EN enum */ TMDS_CTL0_PATTERN_OUT_EN; /* * TMDS_CTL1_DATA_SEL enum */ TMDS_CTL1_DATA_SEL; /* * TMDS_CTL1_DATA_INVERT enum */ TMDS_CTL1_DATA_INVERT; /* * TMDS_CTL1_DATA_MODULATION enum */ TMDS_CTL1_DATA_MODULATION; /* * TMDS_CTL1_PATTERN_OUT_EN enum */ TMDS_CTL1_PATTERN_OUT_EN; /* * TMDS_CTL2_DATA_SEL enum */ TMDS_CTL2_DATA_SEL; /* * TMDS_CTL2_DATA_INVERT enum */ TMDS_CTL2_DATA_INVERT; /* * TMDS_CTL2_DATA_MODULATION enum */ TMDS_CTL2_DATA_MODULATION; /* * TMDS_CTL2_PATTERN_OUT_EN enum */ TMDS_CTL2_PATTERN_OUT_EN; /* * TMDS_CTL3_DATA_INVERT enum */ TMDS_CTL3_DATA_INVERT; /* * TMDS_CTL3_DATA_MODULATION enum */ TMDS_CTL3_DATA_MODULATION; /* * TMDS_CTL3_PATTERN_OUT_EN enum */ TMDS_CTL3_PATTERN_OUT_EN; /* * TMDS_CTL3_DATA_SEL enum */ TMDS_CTL3_DATA_SEL; /* * DIG_FE_CNTL_SOURCE_SELECT enum */ DIG_FE_CNTL_SOURCE_SELECT; /* * DIG_FE_CNTL_STEREOSYNC_SELECT enum */ DIG_FE_CNTL_STEREOSYNC_SELECT; /* * DIG_FIFO_READ_CLOCK_SRC enum */ DIG_FIFO_READ_CLOCK_SRC; /* * DIG_OUTPUT_CRC_CNTL_LINK_SEL enum */ DIG_OUTPUT_CRC_CNTL_LINK_SEL; /* * DIG_OUTPUT_CRC_DATA_SEL enum */ DIG_OUTPUT_CRC_DATA_SEL; /* * DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN enum */ DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN; /* * DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL enum */ DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL; /* * DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN enum */ DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN; /* * DIG_TEST_PATTERN_RANDOM_PATTERN_RESET enum */ DIG_TEST_PATTERN_RANDOM_PATTERN_RESET; /* * DIG_TEST_PATTERN_EXTERNAL_RESET_EN enum */ DIG_TEST_PATTERN_EXTERNAL_RESET_EN; /* * DIG_RANDOM_PATTERN_SEED_RAN_PAT enum */ DIG_RANDOM_PATTERN_SEED_RAN_PAT; /* * DIG_FIFO_STATUS_USE_OVERWRITE_LEVEL enum */ DIG_FIFO_STATUS_USE_OVERWRITE_LEVEL; /* * DIG_FIFO_ERROR_ACK enum */ DIG_FIFO_ERROR_ACK; /* * DIG_FIFO_STATUS_FORCE_RECAL_AVERAGE enum */ DIG_FIFO_STATUS_FORCE_RECAL_AVERAGE; /* * DIG_FIFO_STATUS_FORCE_RECOMP_MINMAX enum */ DIG_FIFO_STATUS_FORCE_RECOMP_MINMAX; /* * AFMT_INTERRUPT_STATUS_CHG_MASK enum */ AFMT_INTERRUPT_STATUS_CHG_MASK; /* * HDMI_GC_AVMUTE enum */ HDMI_GC_AVMUTE; /* * HDMI_DEFAULT_PAHSE enum */ HDMI_DEFAULT_PAHSE; /* * AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD enum */ AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD; /* * AUDIO_LAYOUT_SELECT enum */ AUDIO_LAYOUT_SELECT; /* * AFMT_AUDIO_CRC_CONTROL_CONT enum */ AFMT_AUDIO_CRC_CONTROL_CONT; /* * AFMT_AUDIO_CRC_CONTROL_SOURCE enum */ AFMT_AUDIO_CRC_CONTROL_SOURCE; /* * AFMT_AUDIO_CRC_CONTROL_CH_SEL enum */ AFMT_AUDIO_CRC_CONTROL_CH_SEL; /* * AFMT_RAMP_CONTROL0_SIGN enum */ AFMT_RAMP_CONTROL0_SIGN; /* * AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND enum */ AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND; /* * AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS enum */ AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS; /* * AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE enum */ AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE; /* * AFMT_AUDIO_SRC_CONTROL_SELECT enum */ AFMT_AUDIO_SRC_CONTROL_SELECT; /* * DIG_BE_CNTL_MODE enum */ DIG_BE_CNTL_MODE; /* * DIG_BE_CNTL_HPD_SELECT enum */ DIG_BE_CNTL_HPD_SELECT; /* * LVTMA_RANDOM_PATTERN_SEED_RAN_PAT enum */ LVTMA_RANDOM_PATTERN_SEED_RAN_PAT; /* * TMDS_SYNC_PHASE enum */ TMDS_SYNC_PHASE; /* * TMDS_DATA_SYNCHRONIZATION_DSINTSEL enum */ TMDS_DATA_SYNCHRONIZATION_DSINTSEL; /* * TMDS_TRANSMITTER_ENABLE_HPD_MASK enum */ TMDS_TRANSMITTER_ENABLE_HPD_MASK; /* * TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK enum */ TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK; /* * TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK enum */ TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK; /* * TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK enum */ TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK; /* * TMDS_TRANSMITTER_CONTROL_IDSCKSELA enum */ TMDS_TRANSMITTER_CONTROL_IDSCKSELA; /* * TMDS_TRANSMITTER_CONTROL_IDSCKSELB enum */ TMDS_TRANSMITTER_CONTROL_IDSCKSELB; /* * TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN enum */ TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN; /* * TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK enum */ TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK; /* * TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS enum */ TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS; /* * TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS enum */ TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS; /* * TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN enum */ TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN; /* * TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA enum */ TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA; /* * TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB enum */ TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB; /* * TMDS_REG_TEST_OUTPUTA_CNTLA enum */ TMDS_REG_TEST_OUTPUTA_CNTLA; /* * TMDS_REG_TEST_OUTPUTB_CNTLB enum */ TMDS_REG_TEST_OUTPUTB_CNTLB; /******************************************************* * DCP Enums *******************************************************/ /* * DCP_GRPH_ENABLE enum */ DCP_GRPH_ENABLE; /* * DCP_GRPH_KEYER_ALPHA_SEL enum */ DCP_GRPH_KEYER_ALPHA_SEL; /* * DCP_GRPH_DEPTH enum */ DCP_GRPH_DEPTH; /* * DCP_GRPH_NUM_BANKS enum */ DCP_GRPH_NUM_BANKS; /* * DCP_GRPH_NUM_PIPES enum */ DCP_GRPH_NUM_PIPES; /* * DCP_GRPH_FORMAT enum */ DCP_GRPH_FORMAT; /* * DCP_GRPH_ADDRESS_TRANSLATION_ENABLE enum */ DCP_GRPH_ADDRESS_TRANSLATION_ENABLE; /* * DCP_GRPH_SW_MODE enum */ DCP_GRPH_SW_MODE; /* * DCP_GRPH_COLOR_EXPANSION_MODE enum */ DCP_GRPH_COLOR_EXPANSION_MODE; /* * DCP_GRPH_LUT_10BIT_BYPASS_EN enum */ DCP_GRPH_LUT_10BIT_BYPASS_EN; /* * DCP_GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN enum */ DCP_GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN; /* * DCP_GRPH_ENDIAN_SWAP enum */ DCP_GRPH_ENDIAN_SWAP; /* * DCP_GRPH_RED_CROSSBAR enum */ DCP_GRPH_RED_CROSSBAR; /* * DCP_GRPH_GREEN_CROSSBAR enum */ DCP_GRPH_GREEN_CROSSBAR; /* * DCP_GRPH_BLUE_CROSSBAR enum */ DCP_GRPH_BLUE_CROSSBAR; /* * DCP_GRPH_ALPHA_CROSSBAR enum */ DCP_GRPH_ALPHA_CROSSBAR; /* * DCP_GRPH_PRIMARY_DFQ_ENABLE enum */ DCP_GRPH_PRIMARY_DFQ_ENABLE; /* * DCP_GRPH_SECONDARY_DFQ_ENABLE enum */ DCP_GRPH_SECONDARY_DFQ_ENABLE; /* * DCP_GRPH_INPUT_GAMMA_MODE enum */ DCP_GRPH_INPUT_GAMMA_MODE; /* * DCP_GRPH_MODE_UPDATE_PENDING enum */ DCP_GRPH_MODE_UPDATE_PENDING; /* * DCP_GRPH_MODE_UPDATE_TAKEN enum */ DCP_GRPH_MODE_UPDATE_TAKEN; /* * DCP_GRPH_SURFACE_UPDATE_PENDING enum */ DCP_GRPH_SURFACE_UPDATE_PENDING; /* * DCP_GRPH_SURFACE_UPDATE_TAKEN enum */ DCP_GRPH_SURFACE_UPDATE_TAKEN; /* * DCP_GRPH_SURFACE_XDMA_PENDING_ENABLE enum */ DCP_GRPH_SURFACE_XDMA_PENDING_ENABLE; /* * DCP_GRPH_UPDATE_LOCK enum */ DCP_GRPH_UPDATE_LOCK; /* * DCP_GRPH_SURFACE_IGNORE_UPDATE_LOCK enum */ DCP_GRPH_SURFACE_IGNORE_UPDATE_LOCK; /* * DCP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE enum */ DCP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE; /* * DCP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE enum */ DCP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE; /* * DCP_GRPH_SURFACE_UPDATE_H_RETRACE_EN enum */ DCP_GRPH_SURFACE_UPDATE_H_RETRACE_EN; /* * DCP_GRPH_XDMA_SUPER_AA_EN enum */ DCP_GRPH_XDMA_SUPER_AA_EN; /* * DCP_GRPH_DFQ_RESET enum */ DCP_GRPH_DFQ_RESET; /* * DCP_GRPH_DFQ_SIZE enum */ DCP_GRPH_DFQ_SIZE; /* * DCP_GRPH_DFQ_MIN_FREE_ENTRIES enum */ DCP_GRPH_DFQ_MIN_FREE_ENTRIES; /* * DCP_GRPH_DFQ_RESET_ACK enum */ DCP_GRPH_DFQ_RESET_ACK; /* * DCP_GRPH_PFLIP_INT_CLEAR enum */ DCP_GRPH_PFLIP_INT_CLEAR; /* * DCP_GRPH_PFLIP_INT_MASK enum */ DCP_GRPH_PFLIP_INT_MASK; /* * DCP_GRPH_PFLIP_INT_TYPE enum */ DCP_GRPH_PFLIP_INT_TYPE; /* * DCP_GRPH_PRESCALE_SELECT enum */ DCP_GRPH_PRESCALE_SELECT; /* * DCP_GRPH_PRESCALE_R_SIGN enum */ DCP_GRPH_PRESCALE_R_SIGN; /* * DCP_GRPH_PRESCALE_G_SIGN enum */ DCP_GRPH_PRESCALE_G_SIGN; /* * DCP_GRPH_PRESCALE_B_SIGN enum */ DCP_GRPH_PRESCALE_B_SIGN; /* * DCP_GRPH_PRESCALE_BYPASS enum */ DCP_GRPH_PRESCALE_BYPASS; /* * DCP_INPUT_CSC_GRPH_MODE enum */ DCP_INPUT_CSC_GRPH_MODE; /* * DCP_OUTPUT_CSC_GRPH_MODE enum */ DCP_OUTPUT_CSC_GRPH_MODE; /* * DCP_DENORM_MODE enum */ DCP_DENORM_MODE; /* * DCP_DENORM_14BIT_OUT enum */ DCP_DENORM_14BIT_OUT; /* * DCP_OUT_ROUND_TRUNC_MODE enum */ DCP_OUT_ROUND_TRUNC_MODE; /* * DCP_KEY_MODE enum */ DCP_KEY_MODE; /* * DCP_GRPH_DEGAMMA_MODE enum */ DCP_GRPH_DEGAMMA_MODE; /* * DCP_CURSOR_DEGAMMA_MODE enum */ DCP_CURSOR_DEGAMMA_MODE; /* * DCP_GRPH_GAMUT_REMAP_MODE enum */ DCP_GRPH_GAMUT_REMAP_MODE; /* * DCP_SPATIAL_DITHER_EN enum */ DCP_SPATIAL_DITHER_EN; /* * DCP_SPATIAL_DITHER_MODE enum */ DCP_SPATIAL_DITHER_MODE; /* * DCP_SPATIAL_DITHER_DEPTH enum */ DCP_SPATIAL_DITHER_DEPTH; /* * DCP_FRAME_RANDOM_ENABLE enum */ DCP_FRAME_RANDOM_ENABLE; /* * DCP_RGB_RANDOM_ENABLE enum */ DCP_RGB_RANDOM_ENABLE; /* * DCP_HIGHPASS_RANDOM_ENABLE enum */ DCP_HIGHPASS_RANDOM_ENABLE; /* * DCP_CURSOR_EN enum */ DCP_CURSOR_EN; /* * DCP_CUR_INV_TRANS_CLAMP enum */ DCP_CUR_INV_TRANS_CLAMP; /* * DCP_CURSOR_MODE enum */ DCP_CURSOR_MODE; /* * DCP_CURSOR_MAX_OUTSTANDING_GROUP_NUM enum */ DCP_CURSOR_MAX_OUTSTANDING_GROUP_NUM; /* * DCP_CURSOR_2X_MAGNIFY enum */ DCP_CURSOR_2X_MAGNIFY; /* * DCP_CURSOR_FORCE_MC_ON enum */ DCP_CURSOR_FORCE_MC_ON; /* * DCP_CURSOR_URGENT_CONTROL enum */ DCP_CURSOR_URGENT_CONTROL; /* * DCP_CURSOR_UPDATE_PENDING enum */ DCP_CURSOR_UPDATE_PENDING; /* * DCP_CURSOR_UPDATE_TAKEN enum */ DCP_CURSOR_UPDATE_TAKEN; /* * DCP_CURSOR_UPDATE_LOCK enum */ DCP_CURSOR_UPDATE_LOCK; /* * DCP_CURSOR_DISABLE_MULTIPLE_UPDATE enum */ DCP_CURSOR_DISABLE_MULTIPLE_UPDATE; /* * DCP_CURSOR_UPDATE_STEREO_MODE enum */ DCP_CURSOR_UPDATE_STEREO_MODE; /* * DCP_CUR2_INV_TRANS_CLAMP enum */ DCP_CUR2_INV_TRANS_CLAMP; /* * DCP_CUR_REQUEST_FILTER_DIS enum */ DCP_CUR_REQUEST_FILTER_DIS; /* * DCP_CURSOR_STEREO_EN enum */ DCP_CURSOR_STEREO_EN; /* * DCP_CURSOR_STEREO_OFFSET_YNX enum */ DCP_CURSOR_STEREO_OFFSET_YNX; /* * DCP_DC_LUT_RW_MODE enum */ DCP_DC_LUT_RW_MODE; /* * DCP_DC_LUT_VGA_ACCESS_ENABLE enum */ DCP_DC_LUT_VGA_ACCESS_ENABLE; /* * DCP_DC_LUT_AUTOFILL enum */ DCP_DC_LUT_AUTOFILL; /* * DCP_DC_LUT_AUTOFILL_DONE enum */ DCP_DC_LUT_AUTOFILL_DONE; /* * DCP_DC_LUT_INC_B enum */ DCP_DC_LUT_INC_B; /* * DCP_DC_LUT_DATA_B_SIGNED_EN enum */ DCP_DC_LUT_DATA_B_SIGNED_EN; /* * DCP_DC_LUT_DATA_B_FLOAT_POINT_EN enum */ DCP_DC_LUT_DATA_B_FLOAT_POINT_EN; /* * DCP_DC_LUT_DATA_B_FORMAT enum */ DCP_DC_LUT_DATA_B_FORMAT; /* * DCP_DC_LUT_INC_G enum */ DCP_DC_LUT_INC_G; /* * DCP_DC_LUT_DATA_G_SIGNED_EN enum */ DCP_DC_LUT_DATA_G_SIGNED_EN; /* * DCP_DC_LUT_DATA_G_FLOAT_POINT_EN enum */ DCP_DC_LUT_DATA_G_FLOAT_POINT_EN; /* * DCP_DC_LUT_DATA_G_FORMAT enum */ DCP_DC_LUT_DATA_G_FORMAT; /* * DCP_DC_LUT_INC_R enum */ DCP_DC_LUT_INC_R; /* * DCP_DC_LUT_DATA_R_SIGNED_EN enum */ DCP_DC_LUT_DATA_R_SIGNED_EN; /* * DCP_DC_LUT_DATA_R_FLOAT_POINT_EN enum */ DCP_DC_LUT_DATA_R_FLOAT_POINT_EN; /* * DCP_DC_LUT_DATA_R_FORMAT enum */ DCP_DC_LUT_DATA_R_FORMAT; /* * DCP_CRC_ENABLE enum */ DCP_CRC_ENABLE; /* * DCP_CRC_SOURCE_SEL enum */ DCP_CRC_SOURCE_SEL; /* * DCP_CRC_LINE_SEL enum */ DCP_CRC_LINE_SEL; /* * DCP_GRPH_FLIP_RATE enum */ DCP_GRPH_FLIP_RATE; /* * DCP_GRPH_FLIP_RATE_ENABLE enum */ DCP_GRPH_FLIP_RATE_ENABLE; /* * DCP_GSL0_EN enum */ DCP_GSL0_EN; /* * DCP_GSL1_EN enum */ DCP_GSL1_EN; /* * DCP_GSL2_EN enum */ DCP_GSL2_EN; /* * DCP_GSL_MASTER_EN enum */ DCP_GSL_MASTER_EN; /* * DCP_GSL_XDMA_GROUP enum */ DCP_GSL_XDMA_GROUP; /* * DCP_GSL_XDMA_GROUP_UNDERFLOW_EN enum */ DCP_GSL_XDMA_GROUP_UNDERFLOW_EN; /* * DCP_GSL_SYNC_SOURCE enum */ DCP_GSL_SYNC_SOURCE; /* * DCP_GSL_USE_CHECKPOINT_WINDOW_IN_VSYNC enum */ DCP_GSL_USE_CHECKPOINT_WINDOW_IN_VSYNC; /* * DCP_GSL_DELAY_SURFACE_UPDATE_PENDING enum */ DCP_GSL_DELAY_SURFACE_UPDATE_PENDING; /* * DCP_TEST_DEBUG_WRITE_EN enum */ DCP_TEST_DEBUG_WRITE_EN; /* * DCP_GRPH_STEREOSYNC_FLIP_EN enum */ DCP_GRPH_STEREOSYNC_FLIP_EN; /* * DCP_GRPH_STEREOSYNC_FLIP_MODE enum */ DCP_GRPH_STEREOSYNC_FLIP_MODE; /* * DCP_GRPH_STEREOSYNC_SELECT_DISABLE enum */ DCP_GRPH_STEREOSYNC_SELECT_DISABLE; /* * DCP_GRPH_ROTATION_ANGLE enum */ DCP_GRPH_ROTATION_ANGLE; /* * DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN enum */ DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN; /* * DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE enum */ DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE; /* * DCP_GRPH_REGAMMA_MODE enum */ DCP_GRPH_REGAMMA_MODE; /* * DCP_ALPHA_ROUND_TRUNC_MODE enum */ DCP_ALPHA_ROUND_TRUNC_MODE; /* * DCP_CURSOR_ALPHA_BLND_ENA enum */ DCP_CURSOR_ALPHA_BLND_ENA; /* * DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK enum */ DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK; /* * DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK enum */ DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK; /* * DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK enum */ DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK; /* * DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK enum */ DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK; /* * DCP_GRPH_SURFACE_COUNTER_EN enum */ DCP_GRPH_SURFACE_COUNTER_EN; /* * DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT enum */ DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT; /* * DCP_GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED enum */ DCP_GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED; /* * DCP_GRPH_XDMA_FLIP_TYPE_CLEAR enum */ DCP_GRPH_XDMA_FLIP_TYPE_CLEAR; /* * DCP_GRPH_XDMA_DRR_MODE_ENABLE enum */ DCP_GRPH_XDMA_DRR_MODE_ENABLE; /* * DCP_GRPH_XDMA_MULTIFLIP_ENABLE enum */ DCP_GRPH_XDMA_MULTIFLIP_ENABLE; /* * DCP_GRPH_XDMA_FLIP_TIMEOUT_MASK enum */ DCP_GRPH_XDMA_FLIP_TIMEOUT_MASK; /* * DCP_GRPH_XDMA_FLIP_TIMEOUT_ACK enum */ DCP_GRPH_XDMA_FLIP_TIMEOUT_ACK; /******************************************************* * DC_PERFMON Enums *******************************************************/ /* * PERFCOUNTER_CVALUE_SEL enum */ PERFCOUNTER_CVALUE_SEL; /* * PERFCOUNTER_INC_MODE enum */ PERFCOUNTER_INC_MODE; /* * PERFCOUNTER_HW_CNTL_SEL enum */ PERFCOUNTER_HW_CNTL_SEL; /* * PERFCOUNTER_RUNEN_MODE enum */ PERFCOUNTER_RUNEN_MODE; /* * PERFCOUNTER_CNTOFF_START_DIS enum */ PERFCOUNTER_CNTOFF_START_DIS; /* * PERFCOUNTER_RESTART_EN enum */ PERFCOUNTER_RESTART_EN; /* * PERFCOUNTER_INT_EN enum */ PERFCOUNTER_INT_EN; /* * PERFCOUNTER_OFF_MASK enum */ PERFCOUNTER_OFF_MASK; /* * PERFCOUNTER_ACTIVE enum */ PERFCOUNTER_ACTIVE; /* * PERFCOUNTER_INT_TYPE enum */ PERFCOUNTER_INT_TYPE; /* * PERFCOUNTER_COUNTED_VALUE_TYPE enum */ PERFCOUNTER_COUNTED_VALUE_TYPE; /* * PERFCOUNTER_CNTL_SEL enum */ PERFCOUNTER_CNTL_SEL; /* * PERFCOUNTER_CNT0_STATE enum */ PERFCOUNTER_CNT0_STATE; /* * PERFCOUNTER_STATE_SEL0 enum */ PERFCOUNTER_STATE_SEL0; /* * PERFCOUNTER_CNT1_STATE enum */ PERFCOUNTER_CNT1_STATE; /* * PERFCOUNTER_STATE_SEL1 enum */ PERFCOUNTER_STATE_SEL1; /* * PERFCOUNTER_CNT2_STATE enum */ PERFCOUNTER_CNT2_STATE; /* * PERFCOUNTER_STATE_SEL2 enum */ PERFCOUNTER_STATE_SEL2; /* * PERFCOUNTER_CNT3_STATE enum */ PERFCOUNTER_CNT3_STATE; /* * PERFCOUNTER_STATE_SEL3 enum */ PERFCOUNTER_STATE_SEL3; /* * PERFCOUNTER_CNT4_STATE enum */ PERFCOUNTER_CNT4_STATE; /* * PERFCOUNTER_STATE_SEL4 enum */ PERFCOUNTER_STATE_SEL4; /* * PERFCOUNTER_CNT5_STATE enum */ PERFCOUNTER_CNT5_STATE; /* * PERFCOUNTER_STATE_SEL5 enum */ PERFCOUNTER_STATE_SEL5; /* * PERFCOUNTER_CNT6_STATE enum */ PERFCOUNTER_CNT6_STATE; /* * PERFCOUNTER_STATE_SEL6 enum */ PERFCOUNTER_STATE_SEL6; /* * PERFCOUNTER_CNT7_STATE enum */ PERFCOUNTER_CNT7_STATE; /* * PERFCOUNTER_STATE_SEL7 enum */ PERFCOUNTER_STATE_SEL7; /* * PERFMON_STATE enum */ PERFMON_STATE; /* * PERFMON_CNTOFF_AND_OR enum */ PERFMON_CNTOFF_AND_OR; /* * PERFMON_CNTOFF_INT_EN enum */ PERFMON_CNTOFF_INT_EN; /* * PERFMON_CNTOFF_INT_TYPE enum */ PERFMON_CNTOFF_INT_TYPE; /******************************************************* * SCL Enums *******************************************************/ /* * SCL_C_RAM_TAP_PAIR_IDX enum */ SCL_C_RAM_TAP_PAIR_IDX; /* * SCL_C_RAM_PHASE enum */ SCL_C_RAM_PHASE; /* * SCL_C_RAM_FILTER_TYPE enum */ SCL_C_RAM_FILTER_TYPE; /* * SCL_MODE_SEL enum */ SCL_MODE_SEL; /* * SCL_PSCL_EN enum */ SCL_PSCL_EN; /* * SCL_V_NUM_OF_TAPS enum */ SCL_V_NUM_OF_TAPS; /* * SCL_H_NUM_OF_TAPS enum */ SCL_H_NUM_OF_TAPS; /* * SCL_BOUNDARY_MODE enum */ SCL_BOUNDARY_MODE; /* * SCL_EARLY_EOL_MOD enum */ SCL_EARLY_EOL_MOD; /* * SCL_BYPASS_MODE enum */ SCL_BYPASS_MODE; /* * SCL_V_MANUAL_REPLICATE_FACTOR enum */ SCL_V_MANUAL_REPLICATE_FACTOR; /* * SCL_H_MANUAL_REPLICATE_FACTOR enum */ SCL_H_MANUAL_REPLICATE_FACTOR; /* * SCL_V_CALC_AUTO_RATIO_EN enum */ SCL_V_CALC_AUTO_RATIO_EN; /* * SCL_H_CALC_AUTO_RATIO_EN enum */ SCL_H_CALC_AUTO_RATIO_EN; /* * SCL_H_FILTER_PICK_NEAREST enum */ SCL_H_FILTER_PICK_NEAREST; /* * SCL_H_2TAP_HARDCODE_COEF_EN enum */ SCL_H_2TAP_HARDCODE_COEF_EN; /* * SCL_V_FILTER_PICK_NEAREST enum */ SCL_V_FILTER_PICK_NEAREST; /* * SCL_V_2TAP_HARDCODE_COEF_EN enum */ SCL_V_2TAP_HARDCODE_COEF_EN; /* * SCL_UPDATE_TAKEN enum */ SCL_UPDATE_TAKEN; /* * SCL_UPDATE_LOCK enum */ SCL_UPDATE_LOCK; /* * SCL_COEF_UPDATE_COMPLETE enum */ SCL_COEF_UPDATE_COMPLETE; /* * SCL_HF_SHARP_SCALE_FACTOR enum */ SCL_HF_SHARP_SCALE_FACTOR; /* * SCL_HF_SHARP_EN enum */ SCL_HF_SHARP_EN; /* * SCL_VF_SHARP_SCALE_FACTOR enum */ SCL_VF_SHARP_SCALE_FACTOR; /* * SCL_VF_SHARP_EN enum */ SCL_VF_SHARP_EN; /* * SCL_ALU_DISABLE enum */ SCL_ALU_DISABLE; /* * SCL_HOST_CONFLICT_MASK enum */ SCL_HOST_CONFLICT_MASK; /* * SCL_SCL_MODE_CHANGE_MASK enum */ SCL_SCL_MODE_CHANGE_MASK; /******************************************************* * SCLV Enums *******************************************************/ /* * SCLV_MODE_SEL enum */ SCLV_MODE_SEL; /* * SCLV_INTERLACE_SOURCE enum */ SCLV_INTERLACE_SOURCE; /* * SCLV_UPDATE_LOCK enum */ SCLV_UPDATE_LOCK; /* * SCLV_COEF_UPDATE_COMPLETE enum */ SCLV_COEF_UPDATE_COMPLETE; /******************************************************* * DPRX_SD Enums *******************************************************/ /* * DPRX_SD_PIXEL_ENCODING enum */ DPRX_SD_PIXEL_ENCODING; /* * DPRX_SD_COMPONENT_DEPTH enum */ DPRX_SD_COMPONENT_DEPTH; /******************************************************* * AZF0STREAM Enums *******************************************************/ /* * AZ_LATENCY_COUNTER_CONTROL enum */ AZ_LATENCY_COUNTER_CONTROL; /******************************************************* * BLND Enums *******************************************************/ /* * BLND_CONTROL_BLND_MODE enum */ BLND_CONTROL_BLND_MODE; /* * BLND_CONTROL_BLND_STEREO_TYPE enum */ BLND_CONTROL_BLND_STEREO_TYPE; /* * BLND_CONTROL_BLND_STEREO_POLARITY enum */ BLND_CONTROL_BLND_STEREO_POLARITY; /* * BLND_CONTROL_BLND_FEEDTHROUGH_EN enum */ BLND_CONTROL_BLND_FEEDTHROUGH_EN; /* * BLND_CONTROL_BLND_ALPHA_MODE enum */ BLND_CONTROL_BLND_ALPHA_MODE; /* * BLND_CONTROL_BLND_ACTIVE_OVERLAP_ONLY enum */ BLND_CONTROL_BLND_ACTIVE_OVERLAP_ONLY; /* * BLND_CONTROL_BLND_MULTIPLIED_MODE enum */ BLND_CONTROL_BLND_MULTIPLIED_MODE; /* * BLND_SM_CONTROL2_SM_MODE enum */ BLND_SM_CONTROL2_SM_MODE; /* * BLND_SM_CONTROL2_SM_FRAME_ALTERNATE enum */ BLND_SM_CONTROL2_SM_FRAME_ALTERNATE; /* * BLND_SM_CONTROL2_SM_FIELD_ALTERNATE enum */ BLND_SM_CONTROL2_SM_FIELD_ALTERNATE; /* * BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL enum */ BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL; /* * BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL enum */ BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL; /* * BLND_CONTROL2_PTI_ENABLE enum */ BLND_CONTROL2_PTI_ENABLE; /* * BLND_CONTROL2_BLND_SUPERAA_DEGAMMA_EN enum */ BLND_CONTROL2_BLND_SUPERAA_DEGAMMA_EN; /* * BLND_CONTROL2_BLND_SUPERAA_REGAMMA_EN enum */ BLND_CONTROL2_BLND_SUPERAA_REGAMMA_EN; /* * BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK enum */ BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK; /* * BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK enum */ BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK; /* * BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK enum */ BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK; /* * BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK enum */ BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK; /* * BLND_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK enum */ BLND_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK; /* * BLND_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK enum */ BLND_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK; /* * BLND_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK enum */ BLND_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK; /* * BLND_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK enum */ BLND_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK; /* * BLND_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE enum */ BLND_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE; /* * BLND_DEBUG_BLND_CNV_MUX_SELECT enum */ BLND_DEBUG_BLND_CNV_MUX_SELECT; /* * BLND_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN enum */ BLND_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN; /******************************************************* * AZF0ENDPOINT Enums *******************************************************/ /* * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE enum */ AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE; /* * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP enum */ AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP; /* * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL enum */ AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL; /* * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL enum */ AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL; /* * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST enum */ AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST; /* * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY enum */ AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY; /* * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET enum */ AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET; /* * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE enum */ AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE; /* * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE enum */ AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE; /* * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE enum */ AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE; /* * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT enum */ AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT; /* * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT enum */ AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT; /* * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES enum */ AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES; /* * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE enum */ AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE; /* * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP enum */ AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP; /* * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL enum */ AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL; /* * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL enum */ AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL; /* * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST enum */ AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST; /* * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY enum */ AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY; /* * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET enum */ AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET; /* * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE enum */ AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE; /* * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE enum */ AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE; /* * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT enum */ AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT; /* * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT enum */ AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT; /* * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE enum */ AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE; /* * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS enum */ AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS; /* * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE enum */ AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE; /* * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE enum */ AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE; /* * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE enum */ AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE; /* * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY enum */ AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY; /* * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED enum */ AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED; /* * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE enum */ AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE; /* * AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE enum */ AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE; /* * AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE enum */ AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE; /******************************************************* * AZF0INPUTENDPOINT Enums *******************************************************/ /* * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE enum */ AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE; /* * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP enum */ AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP; /* * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL enum */ AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL; /* * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL enum */ AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL; /* * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST enum */ AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST; /* * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY enum */ AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY; /* * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET enum */ AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET; /* * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE enum */ AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE; /* * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE enum */ AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE; /* * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE enum */ AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE; /* * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT enum */ AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT; /* * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT enum */ AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT; /* * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES enum */ AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES; /* * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE enum */ AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE; /* * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP enum */ AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP; /* * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL enum */ AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL; /* * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL enum */ AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL; /* * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST enum */ AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST; /* * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY enum */ AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY; /* * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET enum */ AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET; /* * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE enum */ AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE; /* * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE enum */ AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE; /* * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT enum */ AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT; /* * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT enum */ AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT; /* * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP enum */ AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP; /* * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE enum */ AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE; /* * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI enum */ AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI; /* * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS enum */ AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS; /* * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE enum */ AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE; /* * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE enum */ AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE; /* * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE enum */ AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE; /* * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY enum */ AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY; /* * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED enum */ AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED; /* * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE enum */ AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE; /* * AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE enum */ AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE; /******************************************************* * UNP Enums *******************************************************/ /* * UNP_GRPH_EN enum */ UNP_GRPH_EN; /* * UNP_GRPH_DEPTH enum */ UNP_GRPH_DEPTH; /* * UNP_GRPH_NUM_BANKS enum */ UNP_GRPH_NUM_BANKS; /* * UNP_GRPH_BANK_WIDTH enum */ UNP_GRPH_BANK_WIDTH; /* * UNP_GRPH_BANK_HEIGHT enum */ UNP_GRPH_BANK_HEIGHT; /* * UNP_GRPH_TILE_SPLIT enum */ UNP_GRPH_TILE_SPLIT; /* * UNP_GRPH_ADDRESS_TRANSLATION_ENABLE enum */ UNP_GRPH_ADDRESS_TRANSLATION_ENABLE; /* * UNP_GRPH_MACRO_TILE_ASPECT enum */ UNP_GRPH_MACRO_TILE_ASPECT; /* * UNP_GRPH_COLOR_EXPANSION_MODE enum */ UNP_GRPH_COLOR_EXPANSION_MODE; /* * UNP_VIDEO_FORMAT enum */ UNP_VIDEO_FORMAT; /* * UNP_GRPH_ENDIAN_SWAP enum */ UNP_GRPH_ENDIAN_SWAP; /* * UNP_GRPH_RED_CROSSBAR enum */ UNP_GRPH_RED_CROSSBAR; /* * UNP_GRPH_GREEN_CROSSBAR enum */ UNP_GRPH_GREEN_CROSSBAR; /* * UNP_GRPH_BLUE_CROSSBAR enum */ UNP_GRPH_BLUE_CROSSBAR; /* * UNP_GRPH_MODE_UPDATE_LOCKG enum */ UNP_GRPH_MODE_UPDATE_LOCKG; /* * UNP_GRPH_SURFACE_IGNORE_UPDATE_LOCK enum */ UNP_GRPH_SURFACE_IGNORE_UPDATE_LOCK; /* * UNP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE enum */ UNP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE; /* * UNP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE enum */ UNP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE; /* * UNP_GRPH_STEREOSYNC_FLIP_EN enum */ UNP_GRPH_STEREOSYNC_FLIP_EN; /* * UNP_GRPH_STEREOSYNC_FLIP_MODE enum */ UNP_GRPH_STEREOSYNC_FLIP_MODE; /* * UNP_GRPH_STACK_INTERLACE_FLIP_EN enum */ UNP_GRPH_STACK_INTERLACE_FLIP_EN; /* * UNP_GRPH_STACK_INTERLACE_FLIP_MODE enum */ UNP_GRPH_STACK_INTERLACE_FLIP_MODE; /* * UNP_GRPH_STEREOSYNC_SELECT_DISABLE enum */ UNP_GRPH_STEREOSYNC_SELECT_DISABLE; /* * UNP_CRC_SOURCE_SEL enum */ UNP_CRC_SOURCE_SEL; /* * UNP_CRC_LINE_SEL enum */ UNP_CRC_LINE_SEL; /* * UNP_ROTATION_ANGLE enum */ UNP_ROTATION_ANGLE; /* * UNP_PIXEL_DROP enum */ UNP_PIXEL_DROP; /* * UNP_BUFFER_MODE enum */ UNP_BUFFER_MODE; /******************************************************* * DP Enums *******************************************************/ /* * DP_LINK_TRAINING_COMPLETE enum */ DP_LINK_TRAINING_COMPLETE; /* * DP_EMBEDDED_PANEL_MODE enum */ DP_EMBEDDED_PANEL_MODE; /* * DP_PIXEL_ENCODING enum */ DP_PIXEL_ENCODING; /* * DP_DYN_RANGE enum */ DP_DYN_RANGE; /* * DP_YCBCR_RANGE enum */ DP_YCBCR_RANGE; /* * DP_COMPONENT_DEPTH enum */ DP_COMPONENT_DEPTH; /* * DP_MSA_MISC0_OVERRIDE_ENABLE enum */ DP_MSA_MISC0_OVERRIDE_ENABLE; /* * DP_MSA_MISC1_BIT7_OVERRIDE_ENABLE enum */ DP_MSA_MISC1_BIT7_OVERRIDE_ENABLE; /* * DP_UDI_LANES enum */ DP_UDI_LANES; /* * DP_VID_STREAM_DIS_DEFER enum */ DP_VID_STREAM_DIS_DEFER; /* * DP_STEER_OVERFLOW_ACK enum */ DP_STEER_OVERFLOW_ACK; /* * DP_STEER_OVERFLOW_MASK enum */ DP_STEER_OVERFLOW_MASK; /* * DP_TU_OVERFLOW_ACK enum */ DP_TU_OVERFLOW_ACK; /* * DPHY_ALT_SCRAMBLER_RESET_EN enum */ DPHY_ALT_SCRAMBLER_RESET_EN; /* * DPHY_ALT_SCRAMBLER_RESET_SEL enum */ DPHY_ALT_SCRAMBLER_RESET_SEL; /* * DP_VID_TIMING_MODE enum */ DP_VID_TIMING_MODE; /* * DP_VID_M_N_DOUBLE_BUFFER_MODE enum */ DP_VID_M_N_DOUBLE_BUFFER_MODE; /* * DP_VID_M_N_GEN_EN enum */ DP_VID_M_N_GEN_EN; /* * DP_VID_M_DOUBLE_VALUE_EN enum */ DP_VID_M_DOUBLE_VALUE_EN; /* * DP_VID_ENHANCED_FRAME_MODE enum */ DP_VID_ENHANCED_FRAME_MODE; /* * DP_VID_MSA_TOP_FIELD_MODE enum */ DP_VID_MSA_TOP_FIELD_MODE; /* * DP_VID_VBID_FIELD_POL enum */ DP_VID_VBID_FIELD_POL; /* * DP_VID_STREAM_DISABLE_ACK enum */ DP_VID_STREAM_DISABLE_ACK; /* * DP_VID_STREAM_DISABLE_MASK enum */ DP_VID_STREAM_DISABLE_MASK; /* * DPHY_ATEST_SEL_LANE0 enum */ DPHY_ATEST_SEL_LANE0; /* * DPHY_ATEST_SEL_LANE1 enum */ DPHY_ATEST_SEL_LANE1; /* * DPHY_ATEST_SEL_LANE2 enum */ DPHY_ATEST_SEL_LANE2; /* * DPHY_ATEST_SEL_LANE3 enum */ DPHY_ATEST_SEL_LANE3; /* * DPHY_SCRAMBLER_SEL enum */ DPHY_SCRAMBLER_SEL; /* * DPHY_BYPASS enum */ DPHY_BYPASS; /* * DPHY_SKEW_BYPASS enum */ DPHY_SKEW_BYPASS; /* * DPHY_TRAINING_PATTERN_SEL enum */ DPHY_TRAINING_PATTERN_SEL; /* * DPHY_8B10B_RESET enum */ DPHY_8B10B_RESET; /* * DP_DPHY_8B10B_EXT_DISP enum */ DP_DPHY_8B10B_EXT_DISP; /* * DPHY_8B10B_CUR_DISP enum */ DPHY_8B10B_CUR_DISP; /* * DPHY_PRBS_EN enum */ DPHY_PRBS_EN; /* * DPHY_PRBS_SEL enum */ DPHY_PRBS_SEL; /* * DPHY_SCRAMBLER_DIS enum */ DPHY_SCRAMBLER_DIS; /* * DPHY_SCRAMBLER_ADVANCE enum */ DPHY_SCRAMBLER_ADVANCE; /* * DPHY_SCRAMBLER_KCODE enum */ DPHY_SCRAMBLER_KCODE; /* * DPHY_LOAD_BS_COUNT_START enum */ DPHY_LOAD_BS_COUNT_START; /* * DPHY_CRC_EN enum */ DPHY_CRC_EN; /* * DPHY_CRC_CONT_EN enum */ DPHY_CRC_CONT_EN; /* * DPHY_CRC_FIELD enum */ DPHY_CRC_FIELD; /* * DPHY_CRC_SEL enum */ DPHY_CRC_SEL; /* * DPHY_RX_FAST_TRAINING_CAPABLE enum */ DPHY_RX_FAST_TRAINING_CAPABLE; /* * DP_SEC_COLLISION_ACK enum */ DP_SEC_COLLISION_ACK; /* * DP_SEC_AUDIO_MUTE enum */ DP_SEC_AUDIO_MUTE; /* * DP_SEC_TIMESTAMP_MODE enum */ DP_SEC_TIMESTAMP_MODE; /* * DP_SEC_ASP_PRIORITY enum */ DP_SEC_ASP_PRIORITY; /* * DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE enum */ DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE; /* * DP_MSE_SAT_UPDATE_ACT enum */ DP_MSE_SAT_UPDATE_ACT; /* * DP_MSE_LINK_LINE enum */ DP_MSE_LINK_LINE; /* * DP_MSE_BLANK_CODE enum */ DP_MSE_BLANK_CODE; /* * DP_MSE_TIMESTAMP_MODE enum */ DP_MSE_TIMESTAMP_MODE; /* * DP_MSE_ZERO_ENCODER enum */ DP_MSE_ZERO_ENCODER; /* * DP_MSE_OUTPUT_DPDBG_DATA enum */ DP_MSE_OUTPUT_DPDBG_DATA; /* * DP_DPHY_HBR2_PATTERN_CONTROL_MODE enum */ DP_DPHY_HBR2_PATTERN_CONTROL_MODE; /* * DPHY_CRC_MST_PHASE_ERROR_ACK enum */ DPHY_CRC_MST_PHASE_ERROR_ACK; /* * DPHY_SW_FAST_TRAINING_START enum */ DPHY_SW_FAST_TRAINING_START; /* * DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN enum */ DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN; /* * DP_DPHY_FAST_TRAINING_COMPLETE_MASK enum */ DP_DPHY_FAST_TRAINING_COMPLETE_MASK; /* * DP_DPHY_FAST_TRAINING_COMPLETE_ACK enum */ DP_DPHY_FAST_TRAINING_COMPLETE_ACK; /* * DP_MSA_V_TIMING_OVERRIDE_EN enum */ DP_MSA_V_TIMING_OVERRIDE_EN; /* * DP_SEC_GSP0_PRIORITY enum */ DP_SEC_GSP0_PRIORITY; /* * DP_SEC_GSP0_SEND enum */ DP_SEC_GSP0_SEND; /******************************************************* * COL_MAN Enums *******************************************************/ /* * COL_MAN_UPDATE_LOCK enum */ COL_MAN_UPDATE_LOCK; /* * COL_MAN_DISABLE_MULTIPLE_UPDATE enum */ COL_MAN_DISABLE_MULTIPLE_UPDATE; /* * COL_MAN_INPUTCSC_MODE enum */ COL_MAN_INPUTCSC_MODE; /* * COL_MAN_INPUTCSC_TYPE enum */ COL_MAN_INPUTCSC_TYPE; /* * COL_MAN_INPUTCSC_CONVERT enum */ COL_MAN_INPUTCSC_CONVERT; /* * COL_MAN_PRESCALE_MODE enum */ COL_MAN_PRESCALE_MODE; /* * COL_MAN_INPUT_GAMMA_MODE enum */ COL_MAN_INPUT_GAMMA_MODE; /* * COL_MAN_OUTPUT_CSC_MODE enum */ COL_MAN_OUTPUT_CSC_MODE; /* * COL_MAN_DENORM_CLAMP_CONTROL enum */ COL_MAN_DENORM_CLAMP_CONTROL; /* * COL_MAN_REGAMMA_MODE_CONTROL enum */ COL_MAN_REGAMMA_MODE_CONTROL; /* * COL_MAN_GLOBAL_PASSTHROUGH_ENABLE enum */ COL_MAN_GLOBAL_PASSTHROUGH_ENABLE; /* * COL_MAN_DEGAMMA_MODE enum */ COL_MAN_DEGAMMA_MODE; /* * COL_MAN_GAMUT_REMAP_MODE enum */ COL_MAN_GAMUT_REMAP_MODE; /******************************************************* * MCIF_WB Enums *******************************************************/ /******************************************************* * DP_AUX Enums *******************************************************/ /* * DP_AUX_CONTROL_HPD_SEL enum */ DP_AUX_CONTROL_HPD_SEL; /* * DP_AUX_CONTROL_TEST_MODE enum */ DP_AUX_CONTROL_TEST_MODE; /* * DP_AUX_SW_CONTROL_SW_GO enum */ DP_AUX_SW_CONTROL_SW_GO; /* * DP_AUX_SW_CONTROL_LS_READ_TRIG enum */ DP_AUX_SW_CONTROL_LS_READ_TRIG; /* * DP_AUX_ARB_CONTROL_ARB_PRIORITY enum */ DP_AUX_ARB_CONTROL_ARB_PRIORITY; /* * DP_AUX_ARB_CONTROL_USE_AUX_REG_REQ enum */ DP_AUX_ARB_CONTROL_USE_AUX_REG_REQ; /* * DP_AUX_ARB_CONTROL_DONE_USING_AUX_REG enum */ DP_AUX_ARB_CONTROL_DONE_USING_AUX_REG; /* * DP_AUX_INT_ACK enum */ DP_AUX_INT_ACK; /* * DP_AUX_LS_UPDATE_ACK enum */ DP_AUX_LS_UPDATE_ACK; /* * DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL enum */ DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL; /* * DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE enum */ DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE; /* * DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN enum */ DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN; /* * DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY enum */ DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY; /* * DP_AUX_DPHY_RX_CONTROL_START_WINDOW enum */ DP_AUX_DPHY_RX_CONTROL_START_WINDOW; /* * DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW enum */ DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW; /* * DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN enum */ DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN; /* * DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_PHASE_DETECT enum */ DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_PHASE_DETECT; /* * DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_START enum */ DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_START; /* * DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_STOP enum */ DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_STOP; /* * DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN enum */ DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN; /* * DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN enum */ DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN; /* * DP_AUX_DPHY_RX_DETECTION_THRESHOLD enum */ DP_AUX_DPHY_RX_DETECTION_THRESHOLD; /* * DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ enum */ DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ; /* * DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW enum */ DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW; /* * DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT enum */ DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT; /* * DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN enum */ DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN; /* * DP_AUX_ERR_OCCURRED_ACK enum */ DP_AUX_ERR_OCCURRED_ACK; /* * DP_AUX_POTENTIAL_ERR_REACHED_ACK enum */ DP_AUX_POTENTIAL_ERR_REACHED_ACK; /* * DP_AUX_DEFINITE_ERR_REACHED_ACK enum */ DP_AUX_DEFINITE_ERR_REACHED_ACK; /* * DP_AUX_RESET enum */ DP_AUX_RESET; /* * DP_AUX_RESET_DONE enum */ DP_AUX_RESET_DONE; /******************************************************* * DSI Enums *******************************************************/ /* * DSI_COMMAND_MODE_SRC_FORMAT enum */ DSI_COMMAND_MODE_SRC_FORMAT; /* * DSI_COMMAND_MODE_DST_FORMAT enum */ DSI_COMMAND_MODE_DST_FORMAT; /* * DSI_FLAG_CLR enum */ DSI_FLAG_CLR; /* * DSI_BIT_SWAP enum */ DSI_BIT_SWAP; /* * DSI_CLK_GATING enum */ DSI_CLK_GATING; /* * DSI_LANE_ULPS_REQUEST enum */ DSI_LANE_ULPS_REQUEST; /* * DSI_LANE_ULPS_EXIT enum */ DSI_LANE_ULPS_EXIT; /* * DSI_LANE_FORCE_TX_STOP enum */ DSI_LANE_FORCE_TX_STOP; /* * DSI_CLOCK_LANE_HS_FORCE_REQUEST enum */ DSI_CLOCK_LANE_HS_FORCE_REQUEST; /* * DSI_CONTROLLER_EN enum */ DSI_CONTROLLER_EN; /* * DSI_VIDEO_MODE_EN enum */ DSI_VIDEO_MODE_EN; /* * DSI_CMD_MODE_EN enum */ DSI_CMD_MODE_EN; /* * DSI_DATA_LANE0_EN enum */ DSI_DATA_LANE0_EN; /* * DSI_DATA_LANE1_EN enum */ DSI_DATA_LANE1_EN; /* * DSI_DATA_LANE2_EN enum */ DSI_DATA_LANE2_EN; /* * DSI_DATA_LANE3_EN enum */ DSI_DATA_LANE3_EN; /* * DSI_CLOCK_LANE_EN enum */ DSI_CLOCK_LANE_EN; /* * DSI_PHY_DATA_LANE0_EN enum */ DSI_PHY_DATA_LANE0_EN; /* * DSI_PHY_DATA_LANE1_EN enum */ DSI_PHY_DATA_LANE1_EN; /* * DSI_PHY_DATA_LANE2_EN enum */ DSI_PHY_DATA_LANE2_EN; /* * DSI_PHY_DATA_LANE3_EN enum */ DSI_PHY_DATA_LANE3_EN; /* * DSI_RESET_DISPCLK enum */ DSI_RESET_DISPCLK; /* * DSI_RESET_DSICLK enum */ DSI_RESET_DSICLK; /* * DSI_RESET_BYTECLK enum */ DSI_RESET_BYTECLK; /* * DSI_RESET_ESCCLK enum */ DSI_RESET_ESCCLK; /* * DSI_CRTC_SEL enum */ DSI_CRTC_SEL; /* * DSI_PACKET_BYTE_MSB_LSB_FLIP enum */ DSI_PACKET_BYTE_MSB_LSB_FLIP; /* * DSI_VIDEO_MODE_DST_FORMAT enum */ DSI_VIDEO_MODE_DST_FORMAT; /* * DSI_VIDEO_TRAFFIC_MODE enum */ DSI_VIDEO_TRAFFIC_MODE; /* * DSI_VIDEO_BLLP_PWR_MODE enum */ DSI_VIDEO_BLLP_PWR_MODE; /* * DSI_VIDEO_EOF_BLLP_PWR_MODE enum */ DSI_VIDEO_EOF_BLLP_PWR_MODE; /* * DSI_VIDEO_PWR_MODE enum */ DSI_VIDEO_PWR_MODE; /* * DSI_VIDEO_PULSE_MODE_OPT enum */ DSI_VIDEO_PULSE_MODE_OPT; /* * DSI_RGB_SWAP enum */ DSI_RGB_SWAP; /* * DSI_CMD_PACKET_TYPE enum */ DSI_CMD_PACKET_TYPE; /* * DSI_CMD_PWR_MODE enum */ DSI_CMD_PWR_MODE; /* * DSI_CMD_EMBEDDED_MODE enum */ DSI_CMD_EMBEDDED_MODE; /* * DSI_CMD_ORDER enum */ DSI_CMD_ORDER; /* * DSI_DATA_BUFFER_ID enum */ DSI_DATA_BUFFER_ID; /* * DSI_DWORD_BYTE_SWAP enum */ DSI_DWORD_BYTE_SWAP; /* * DSI_INSERT_DCS_COMMAND enum */ DSI_INSERT_DCS_COMMAND; /* * DSI_DMAFIFO_WRITE_WATERMARK enum */ DSI_DMAFIFO_WRITE_WATERMARK; /* * DSI_DMAFIFO_READ_WATERMARK enum */ DSI_DMAFIFO_READ_WATERMARK; /* * DSI_USE_DENG_LENGTH enum */ DSI_USE_DENG_LENGTH; /* * DSI_COMMAND_TRIGGER_MODE enum */ DSI_COMMAND_TRIGGER_MODE; /* * DSI_COMMAND_TRIGGER_SEL enum */ DSI_COMMAND_TRIGGER_SEL; /* * DSI_HW_SOURCE_SEL enum */ DSI_HW_SOURCE_SEL; /* * DSI_COMMAND_TRIGGER_ORDER enum */ DSI_COMMAND_TRIGGER_ORDER; /* * DSI_TE_SRC_SEL enum */ DSI_TE_SRC_SEL; /* * DSI_EXT_TE_MUX enum */ DSI_EXT_TE_MUX; /* * DSI_EXT_TE_MODE enum */ DSI_EXT_TE_MODE; /* * DSI_EXT_RESET_POL enum */ DSI_EXT_RESET_POL; /* * DSI_EXT_TE_POL enum */ DSI_EXT_TE_POL; /* * DSI_RESET_PANEL enum */ DSI_RESET_PANEL; /* * DSI_CRC_ENABLE enum */ DSI_CRC_ENABLE; /* * DSI_TX_EOT_APPEND enum */ DSI_TX_EOT_APPEND; /* * DSI_RX_EOT_IGNORE enum */ DSI_RX_EOT_IGNORE; /* * DSI_MIPI_BIST_RESET enum */ DSI_MIPI_BIST_RESET; /* * DSI_MIPI_BIST_VIDEO_FRMT enum */ DSI_MIPI_BIST_VIDEO_FRMT; /* * DSI_MIPI_BIST_START enum */ DSI_MIPI_BIST_START; /* * DSI_DBG_CLK_SEL enum */ DSI_DBG_CLK_SEL; /* * DSI_DENG_FIFO_USE_OVERWRITE_LEVEL enum */ DSI_DENG_FIFO_USE_OVERWRITE_LEVEL; /* * DSI_DENG_FIFO_FORCE_RECAL_AVERAGE enum */ DSI_DENG_FIFO_FORCE_RECAL_AVERAGE; /* * DSI_DENG_FIFO_FORCE_RECOMP_MINMAX enum */ DSI_DENG_FIFO_FORCE_RECOMP_MINMAX; /* * DSI_DENG_FIFO_START enum */ DSI_DENG_FIFO_START; /* * DSI_USE_CMDFIFO enum */ DSI_USE_CMDFIFO; /* * DSI_CRTC_FREEZE_TRIG enum */ DSI_CRTC_FREEZE_TRIG; /* * DSI_PERF_LATENCY_SEL enum */ DSI_PERF_LATENCY_SEL; /* * DSI_DEBUG_DSICLK_SEL enum */ DSI_DEBUG_DSICLK_SEL; /* * DSI_DEBUG_BYTECLK_SEL enum */ DSI_DEBUG_BYTECLK_SEL; /******************************************************* * DCIO_CHIP Enums *******************************************************/ /* * DCIOCHIP_HPD_SEL enum */ DCIOCHIP_HPD_SEL; /* * DCIOCHIP_PAD_MODE enum */ DCIOCHIP_PAD_MODE; /* * DCIOCHIP_AUXSLAVE_PAD_MODE enum */ DCIOCHIP_AUXSLAVE_PAD_MODE; /* * DCIOCHIP_INVERT enum */ DCIOCHIP_INVERT; /* * DCIOCHIP_PD_EN enum */ DCIOCHIP_PD_EN; /* * DCIOCHIP_GPIO_MASK_EN enum */ DCIOCHIP_GPIO_MASK_EN; /* * DCIOCHIP_MASK enum */ DCIOCHIP_MASK; /* * DCIOCHIP_GPIO_I2C_MASK enum */ DCIOCHIP_GPIO_I2C_MASK; /* * DCIOCHIP_GPIO_I2C_DRIVE enum */ DCIOCHIP_GPIO_I2C_DRIVE; /* * DCIOCHIP_GPIO_I2C_EN enum */ DCIOCHIP_GPIO_I2C_EN; /* * DCIOCHIP_MASK_4BIT enum */ DCIOCHIP_MASK_4BIT; /* * DCIOCHIP_ENABLE_4BIT enum */ DCIOCHIP_ENABLE_4BIT; /* * DCIOCHIP_MASK_5BIT enum */ DCIOCHIP_MASK_5BIT; /* * DCIOCHIP_ENABLE_5BIT enum */ DCIOCHIP_ENABLE_5BIT; /* * DCIOCHIP_MASK_2BIT enum */ DCIOCHIP_MASK_2BIT; /* * DCIOCHIP_ENABLE_2BIT enum */ DCIOCHIP_ENABLE_2BIT; /* * DCIOCHIP_REF_27_SRC_SEL enum */ DCIOCHIP_REF_27_SRC_SEL; /* * DCIOCHIP_DVO_VREFPON enum */ DCIOCHIP_DVO_VREFPON; /* * DCIOCHIP_DVO_VREFSEL enum */ DCIOCHIP_DVO_VREFSEL; /* * DCIOCHIP_SPDIF1_IMODE enum */ DCIOCHIP_SPDIF1_IMODE; /* * DCIOCHIP_AUX_FALLSLEWSEL enum */ DCIOCHIP_AUX_FALLSLEWSEL; /* * DCIOCHIP_AUX_SPIKESEL enum */ DCIOCHIP_AUX_SPIKESEL; /* * DCIOCHIP_AUX_CSEL0P9 enum */ DCIOCHIP_AUX_CSEL0P9; /* * DCIOCHIP_AUX_CSEL1P1 enum */ DCIOCHIP_AUX_CSEL1P1; /* * DCIOCHIP_AUX_RSEL0P9 enum */ DCIOCHIP_AUX_RSEL0P9; /* * DCIOCHIP_AUX_RSEL1P1 enum */ DCIOCHIP_AUX_RSEL1P1; /******************************************************* * AZCONTROLLER Enums *******************************************************/ /* * GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL enum */ GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL; /* * GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL_RESERVED enum */ GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL_RESERVED; /* * GENERIC_AZ_CONTROLLER_REGISTER_STATUS enum */ GENERIC_AZ_CONTROLLER_REGISTER_STATUS; /* * GENERIC_AZ_CONTROLLER_REGISTER_STATUS_RESERVED enum */ GENERIC_AZ_CONTROLLER_REGISTER_STATUS_RESERVED; /* * AZ_GLOBAL_CAPABILITIES enum */ AZ_GLOBAL_CAPABILITIES; /* * GLOBAL_CONTROL_ACCEPT_UNSOLICITED_RESPONSE enum */ GLOBAL_CONTROL_ACCEPT_UNSOLICITED_RESPONSE; /* * GLOBAL_CONTROL_FLUSH_CONTROL enum */ GLOBAL_CONTROL_FLUSH_CONTROL; /* * GLOBAL_CONTROL_CONTROLLER_RESET enum */ GLOBAL_CONTROL_CONTROLLER_RESET; /* * AZ_STATE_CHANGE_STATUS enum */ AZ_STATE_CHANGE_STATUS; /* * GLOBAL_STATUS_FLUSH_STATUS enum */ GLOBAL_STATUS_FLUSH_STATUS; /* * STREAM_0_SYNCHRONIZATION enum */ STREAM_0_SYNCHRONIZATION; /* * STREAM_1_SYNCHRONIZATION enum */ STREAM_1_SYNCHRONIZATION; /* * STREAM_2_SYNCHRONIZATION enum */ STREAM_2_SYNCHRONIZATION; /* * STREAM_3_SYNCHRONIZATION enum */ STREAM_3_SYNCHRONIZATION; /* * STREAM_4_SYNCHRONIZATION enum */ STREAM_4_SYNCHRONIZATION; /* * STREAM_5_SYNCHRONIZATION enum */ STREAM_5_SYNCHRONIZATION; /* * STREAM_6_SYNCHRONIZATION enum */ STREAM_6_SYNCHRONIZATION; /* * STREAM_7_SYNCHRONIZATION enum */ STREAM_7_SYNCHRONIZATION; /* * STREAM_8_SYNCHRONIZATION enum */ STREAM_8_SYNCHRONIZATION; /* * STREAM_9_SYNCHRONIZATION enum */ STREAM_9_SYNCHRONIZATION; /* * STREAM_10_SYNCHRONIZATION enum */ STREAM_10_SYNCHRONIZATION; /* * STREAM_11_SYNCHRONIZATION enum */ STREAM_11_SYNCHRONIZATION; /* * STREAM_12_SYNCHRONIZATION enum */ STREAM_12_SYNCHRONIZATION; /* * STREAM_13_SYNCHRONIZATION enum */ STREAM_13_SYNCHRONIZATION; /* * STREAM_14_SYNCHRONIZATION enum */ STREAM_14_SYNCHRONIZATION; /* * STREAM_15_SYNCHRONIZATION enum */ STREAM_15_SYNCHRONIZATION; /* * CORB_READ_POINTER_RESET enum */ CORB_READ_POINTER_RESET; /* * AZ_CORB_SIZE enum */ AZ_CORB_SIZE; /* * AZ_RIRB_WRITE_POINTER_RESET enum */ AZ_RIRB_WRITE_POINTER_RESET; /* * RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL enum */ RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL; /* * RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL enum */ RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL; /* * AZ_RIRB_SIZE enum */ AZ_RIRB_SIZE; /* * IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID enum */ IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID; /* * IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_BUSY enum */ IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_BUSY; /* * DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE enum */ DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE; /******************************************************* * AZENDPOINT Enums *******************************************************/ /* * AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE enum */ AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE; /* * AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE enum */ AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE; /* * AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE enum */ AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE; /* * AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR enum */ AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR; /* * AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE enum */ AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE; /* * AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS enum */ AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS; /* * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L enum */ AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L; /* * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO enum */ AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO; /* * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO enum */ AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO; /* * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY enum */ AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY; /* * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE enum */ AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE; /* * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VCFG enum */ AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VCFG; /* * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V enum */ AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V; /* * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN enum */ AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN; /* * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE enum */ AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE; /* * AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE enum */ AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE; /* * AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE enum */ AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE; /* * AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DOWN_MIX_INHIBIT enum */ AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DOWN_MIX_INHIBIT; /* * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTE enum */ AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTE; /* * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTE enum */ AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTE; /* * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTE enum */ AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTE; /* * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTE enum */ AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTE; /* * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE enum */ AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE; /* * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE enum */ AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE; /* * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE enum */ AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE; /* * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE enum */ AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE; /* * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE enum */ AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE; /******************************************************* * AZF0CONTROLLER Enums *******************************************************/ /* * AZALIA_SOFT_RESET_REFCLK_SOFT_RESET enum */ AZALIA_SOFT_RESET_REFCLK_SOFT_RESET; /******************************************************* * AZF0ROOT Enums *******************************************************/ /* * CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY enum */ CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY; /* * CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY enum */ CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY; /******************************************************* * AZINPUTENDPOINT Enums *******************************************************/ /* * AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE enum */ AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE; /* * AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE enum */ AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE; /* * AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE enum */ AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE; /* * AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR enum */ AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR; /* * AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE enum */ AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE; /* * AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS enum */ AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS; /* * AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN enum */ AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN; /* * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE enum */ AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE; /* * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE enum */ AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE; /* * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTE enum */ AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTE; /* * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE enum */ AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE; /* * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTE enum */ AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTE; /* * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE enum */ AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE; /* * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTE enum */ AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTE; /* * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE enum */ AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE; /* * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTE enum */ AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTE; /* * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE enum */ AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE; /******************************************************* * AZROOT Enums *******************************************************/ /* * AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_RESET enum */ AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_RESET; /******************************************************* * DCCG Enums *******************************************************/ /* * ENABLE enum */ ENABLE; /* * ENABLE_CLOCK enum */ ENABLE_CLOCK; /* * FORCE_VBI enum */ FORCE_VBI; /* * OVERRIDE_CGTT_SCLK enum */ OVERRIDE_CGTT_SCLK; /* * CLEAR_SMU_INTR enum */ CLEAR_SMU_INTR; /* * STATIC_SCREEN_SMU_INTR enum */ STATIC_SCREEN_SMU_INTR; /* * JITTER_REMOVE_DISABLE enum */ JITTER_REMOVE_DISABLE; /* * DS_REF_SRC enum */ DS_REF_SRC; /* * DISABLE_CLOCK_GATING enum */ DISABLE_CLOCK_GATING; /* * DISABLE_CLOCK_GATING_IN_DCO enum */ DISABLE_CLOCK_GATING_IN_DCO; /* * DCCG_DEEP_COLOR_CNTL enum */ DCCG_DEEP_COLOR_CNTL; /* * REFCLK_CLOCK_EN enum */ REFCLK_CLOCK_EN; /* * REFCLK_SRC_SEL enum */ REFCLK_SRC_SEL; /* * DPREFCLK_SRC_SEL enum */ DPREFCLK_SRC_SEL; /* * XTAL_REF_SEL enum */ XTAL_REF_SEL; /* * XTAL_REF_CLOCK_SOURCE_SEL enum */ XTAL_REF_CLOCK_SOURCE_SEL; /* * MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL enum */ MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL; /* * ALLOW_SR_ON_TRANS_REQ enum */ ALLOW_SR_ON_TRANS_REQ; /* * MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL enum */ MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL; /* * PIPE_PIXEL_RATE_SOURCE enum */ PIPE_PIXEL_RATE_SOURCE; /* * PIPE_PHYPLL_PIXEL_RATE_SOURCE enum */ PIPE_PHYPLL_PIXEL_RATE_SOURCE; /* * PIPE_PIXEL_RATE_PLL_SOURCE enum */ PIPE_PIXEL_RATE_PLL_SOURCE; /* * DP_DTO_DS_DISABLE enum */ DP_DTO_DS_DISABLE; /* * CRTC_ADD_PIXEL enum */ CRTC_ADD_PIXEL; /* * CRTC_DROP_PIXEL enum */ CRTC_DROP_PIXEL; /* * SYMCLK_FE_FORCE_EN enum */ SYMCLK_FE_FORCE_EN; /* * SYMCLK_FE_FORCE_SRC enum */ SYMCLK_FE_FORCE_SRC; /* * DPDBG_CLK_FORCE_EN enum */ DPDBG_CLK_FORCE_EN; /* * DVOACLK_COARSE_SKEW_CNTL enum */ DVOACLK_COARSE_SKEW_CNTL; /* * DVOACLK_FINE_SKEW_CNTL enum */ DVOACLK_FINE_SKEW_CNTL; /* * DVOACLKD_IN_PHASE enum */ DVOACLKD_IN_PHASE; /* * DVOACLKC_IN_PHASE enum */ DVOACLKC_IN_PHASE; /* * DVOACLKC_MVP_IN_PHASE enum */ DVOACLKC_MVP_IN_PHASE; /* * DVOACLKC_MVP_SKEW_PHASE_OVERRIDE enum */ DVOACLKC_MVP_SKEW_PHASE_OVERRIDE; /* * MVP_CLK_SRC_SEL enum */ MVP_CLK_SRC_SEL; /* * DCCG_AUDIO_DTO0_SOURCE_SEL enum */ DCCG_AUDIO_DTO0_SOURCE_SEL; /* * DCCG_AUDIO_DTO_SEL enum */ DCCG_AUDIO_DTO_SEL; /* * DCCG_AUDIO_DTO2_SOURCE_SEL enum */ DCCG_AUDIO_DTO2_SOURCE_SEL; /* * DCCG_AUDIO_DTO_USE_512FBR_DTO enum */ DCCG_AUDIO_DTO_USE_512FBR_DTO; /* * DCCG_DBG_EN enum */ DCCG_DBG_EN; /* * DCCG_DBG_BLOCK_SEL enum */ DCCG_DBG_BLOCK_SEL; /* * DISPCLK_FREQ_RAMP_DONE enum */ DISPCLK_FREQ_RAMP_DONE; /* * DCCG_FIFO_ERRDET_RESET enum */ DCCG_FIFO_ERRDET_RESET; /* * DCCG_FIFO_ERRDET_STATE enum */ DCCG_FIFO_ERRDET_STATE; /* * DCCG_FIFO_ERRDET_OVR_EN enum */ DCCG_FIFO_ERRDET_OVR_EN; /* * DISPCLK_CHG_FWD_CORR_DISABLE enum */ DISPCLK_CHG_FWD_CORR_DISABLE; /* * DC_MEM_GLOBAL_PWR_REQ_DIS enum */ DC_MEM_GLOBAL_PWR_REQ_DIS; /* * DCCG_PERF_RUN enum */ DCCG_PERF_RUN; /* * DCCG_PERF_MODE_VSYNC enum */ DCCG_PERF_MODE_VSYNC; /* * DCCG_PERF_MODE_HSYNC enum */ DCCG_PERF_MODE_HSYNC; /* * DCCG_PERF_CRTC_SELECT enum */ DCCG_PERF_CRTC_SELECT; /* * CLOCK_BRANCH_SOFT_RESET enum */ CLOCK_BRANCH_SOFT_RESET; /* * PLL_CFG_IF_SOFT_RESET enum */ PLL_CFG_IF_SOFT_RESET; /* * DVO_ENABLE_RST enum */ DVO_ENABLE_RST; /******************************************************* * DCI Enums *******************************************************/ /* * LptNumPipes enum */ LptNumPipes; /* * LptNumBanks enum */ LptNumBanks; /* * OVERRIDE_CGTT_DCEFCLK enum */ OVERRIDE_CGTT_DCEFCLK; /******************************************************* * DCIO Enums *******************************************************/ /* * DCIO_DC_GENERICA_SEL enum */ DCIO_DC_GENERICA_SEL; /* * DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL enum */ DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL; /* * DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL enum */ DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL; /* * DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL enum */ DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL; /* * DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL enum */ DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL; /* * DCIO_DC_GENERICB_SEL enum */ DCIO_DC_GENERICB_SEL; /* * DCIO_DC_PAD_EXTERN_SIG_SEL enum */ DCIO_DC_PAD_EXTERN_SIG_SEL; /* * DCIO_DC_PAD_EXTERN_SIG_MVP_PIXEL_SRC_STATUS enum */ DCIO_DC_PAD_EXTERN_SIG_MVP_PIXEL_SRC_STATUS; /* * DCIO_DC_REF_CLK_CNTL_HSYNCA_OUTPUT_SEL enum */ DCIO_DC_REF_CLK_CNTL_HSYNCA_OUTPUT_SEL; /* * DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL enum */ DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL; /* * DCIO_DC_GPIO_VIP_DEBUG enum */ DCIO_DC_GPIO_VIP_DEBUG; /* * DCIO_DC_GPIO_MACRO_DEBUG enum */ DCIO_DC_GPIO_MACRO_DEBUG; /* * DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL enum */ DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL; /* * DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN enum */ DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN; /* * DCIO_DC_GPIO_DEBUG_DPRX_LOOPBACK_ENABLE enum */ DCIO_DC_GPIO_DEBUG_DPRX_LOOPBACK_ENABLE; /* * DCIO_UNIPHY_LINK_CNTL_MINIMUM_PIXVLD_LOW_DURATION enum */ DCIO_UNIPHY_LINK_CNTL_MINIMUM_PIXVLD_LOW_DURATION; /* * DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT enum */ DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT; /* * DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK enum */ DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK; /* * DCIO_UNIPHY_CHANNEL_XBAR_SOURCE enum */ DCIO_UNIPHY_CHANNEL_XBAR_SOURCE; /* * DCIO_DC_DVODATA_CONFIG_VIP_MUX_EN enum */ DCIO_DC_DVODATA_CONFIG_VIP_MUX_EN; /* * DCIO_DC_DVODATA_CONFIG_VIP_ALTER_MAPPING_EN enum */ DCIO_DC_DVODATA_CONFIG_VIP_ALTER_MAPPING_EN; /* * DCIO_DC_DVODATA_CONFIG_DVO_ALTER_MAPPING_EN enum */ DCIO_DC_DVODATA_CONFIG_DVO_ALTER_MAPPING_EN; /* * DCIO_LVTMA_PWRSEQ_CNTL_DISABLE_SYNCEN_CONTROL_OF_TX_EN enum */ DCIO_LVTMA_PWRSEQ_CNTL_DISABLE_SYNCEN_CONTROL_OF_TX_EN; /* * DCIO_LVTMA_PWRSEQ_CNTL_TARGET_STATE enum */ DCIO_LVTMA_PWRSEQ_CNTL_TARGET_STATE; /* * DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_SYNCEN_POL enum */ DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_SYNCEN_POL; /* * DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON enum */ DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON; /* * DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON_POL enum */ DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON_POL; /* * DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON enum */ DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON; /* * DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON_POL enum */ DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON_POL; /* * DCIO_LVTMA_PWRSEQ_DELAY2_LVTMA_VARY_BL_OVERRIDE_EN enum */ DCIO_LVTMA_PWRSEQ_DELAY2_LVTMA_VARY_BL_OVERRIDE_EN; /* * DCIO_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN enum */ DCIO_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN; /* * DCIO_BL_PWM_CNTL_BL_PWM_EN enum */ DCIO_BL_PWM_CNTL_BL_PWM_EN; /* * DCIO_BL_PWM_CNTL2_DBG_BL_PWM_INPUT_REFCLK_SELECT enum */ DCIO_BL_PWM_CNTL2_DBG_BL_PWM_INPUT_REFCLK_SELECT; /* * DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE enum */ DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE; /* * DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN enum */ DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN; /* * DCIO_BL_PWM_GRP1_REG_LOCK enum */ DCIO_BL_PWM_GRP1_REG_LOCK; /* * DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START enum */ DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START; /* * DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL enum */ DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL; /* * DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN enum */ DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN; /* * DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN enum */ DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN; /* * DCIO_GSL_SEL enum */ DCIO_GSL_SEL; /* * DCIO_GENLK_CLK_GSL_MASK enum */ DCIO_GENLK_CLK_GSL_MASK; /* * DCIO_GENLK_VSYNC_GSL_MASK enum */ DCIO_GENLK_VSYNC_GSL_MASK; /* * DCIO_SWAPLOCK_A_GSL_MASK enum */ DCIO_SWAPLOCK_A_GSL_MASK; /* * DCIO_SWAPLOCK_B_GSL_MASK enum */ DCIO_SWAPLOCK_B_GSL_MASK; /* * DCIO_GSL_VSYNC_SEL enum */ DCIO_GSL_VSYNC_SEL; /* * DCIO_GSL0_TIMING_SYNC_SEL enum */ DCIO_GSL0_TIMING_SYNC_SEL; /* * DCIO_GSL0_GLOBAL_UNLOCK_SEL enum */ DCIO_GSL0_GLOBAL_UNLOCK_SEL; /* * DCIO_GSL1_TIMING_SYNC_SEL enum */ DCIO_GSL1_TIMING_SYNC_SEL; /* * DCIO_GSL1_GLOBAL_UNLOCK_SEL enum */ DCIO_GSL1_GLOBAL_UNLOCK_SEL; /* * DCIO_GSL2_TIMING_SYNC_SEL enum */ DCIO_GSL2_TIMING_SYNC_SEL; /* * DCIO_GSL2_GLOBAL_UNLOCK_SEL enum */ DCIO_GSL2_GLOBAL_UNLOCK_SEL; /* * DCIO_DC_GPU_TIMER_START_POSITION enum */ DCIO_DC_GPU_TIMER_START_POSITION; /* * DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL enum */ DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL; /* * DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS enum */ DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS; /* * DCIO_DCO_DCFE_EXT_VSYNC_MUX enum */ DCIO_DCO_DCFE_EXT_VSYNC_MUX; /* * DCIO_DCO_EXT_VSYNC_MASK enum */ DCIO_DCO_EXT_VSYNC_MASK; /* * DCIO_DSYNC_SOFT_RESET enum */ DCIO_DSYNC_SOFT_RESET; /* * DCIO_DACA_SOFT_RESET enum */ DCIO_DACA_SOFT_RESET; /* * DCIO_DCRXPHY_SOFT_RESET enum */ DCIO_DCRXPHY_SOFT_RESET; /* * DCIO_DPHY_LANE_SEL enum */ DCIO_DPHY_LANE_SEL; /* * DCIO_DPCS_INTERRUPT_TYPE enum */ DCIO_DPCS_INTERRUPT_TYPE; /* * DCIO_DPCS_INTERRUPT_MASK enum */ DCIO_DPCS_INTERRUPT_MASK; /* * DCIO_DC_GPU_TIMER_READ_SELECT enum */ DCIO_DC_GPU_TIMER_READ_SELECT; /* * DCIO_IMPCAL_STEP_DELAY enum */ DCIO_IMPCAL_STEP_DELAY; /* * DCIO_UNIPHY_IMPCAL_SEL enum */ DCIO_UNIPHY_IMPCAL_SEL; /* * DCIO_DBG_ASYNC_BLOCK_SEL enum */ DCIO_DBG_ASYNC_BLOCK_SEL; /* * DCIO_DBG_ASYNC_4BIT_SEL enum */ DCIO_DBG_ASYNC_4BIT_SEL; /******************************************************* * AOUT Enums *******************************************************/ /* * AOUT_EN enum */ AOUT_EN; /* * AOUT_FIFO_START_ADDR enum */ AOUT_FIFO_START_ADDR; /* * AOUT_CRC_TEST_EN enum */ AOUT_CRC_TEST_EN; /* * AOUT_CRC_SOFT_RESET enum */ AOUT_CRC_SOFT_RESET; /* * AOUT_CRC_CONT_EN enum */ AOUT_CRC_CONT_EN; /* * I2S_WORD_SIZE enum */ I2S_WORD_SIZE; /* * I2S_SAMPLE_ALIGNMENT enum */ I2S_SAMPLE_ALIGNMENT; /* * I2S_SAMPLE_BIT_ORDER enum */ I2S_SAMPLE_BIT_ORDER; /* * I2S_LRCLK_POLARITY enum */ I2S_LRCLK_POLARITY; /* * I2S_WORD_ALIGNMENT enum */ I2S_WORD_ALIGNMENT; /* * SPDIF_INVERT_EN enum */ SPDIF_INVERT_EN; /******************************************************* * DCO Enums *******************************************************/ /* * DPDBG_EN enum */ DPDBG_EN; /* * DPDBG_INPUT_EN enum */ DPDBG_INPUT_EN; /* * DPDBG_ERROR_DETECTION_MODE enum */ DPDBG_ERROR_DETECTION_MODE; /* * DPDBG_FIFO_OVERFLOW_INTERRUPT_MASK enum */ DPDBG_FIFO_OVERFLOW_INTERRUPT_MASK; /* * DPDBG_FIFO_OVERFLOW_INTERRUPT_TYPE enum */ DPDBG_FIFO_OVERFLOW_INTERRUPT_TYPE; /* * DPDBG_FIFO_OVERFLOW_INTERRUPT_ACK enum */ DPDBG_FIFO_OVERFLOW_INTERRUPT_ACK; /* * PM_ASSERT_RESET enum */ PM_ASSERT_RESET; /* * DAC_MUX_SELECT enum */ DAC_MUX_SELECT; /* * TMDS_DVO_MUX_SELECT enum */ TMDS_DVO_MUX_SELECT; /* * DACA_SOFT_RESET enum */ DACA_SOFT_RESET; /* * I2S0_SPDIF0_SOFT_RESET enum */ I2S0_SPDIF0_SOFT_RESET; /* * I2S1_SOFT_RESET enum */ I2S1_SOFT_RESET; /* * SPDIF1_SOFT_RESET enum */ SPDIF1_SOFT_RESET; /* * DB_CLK_SOFT_RESET enum */ DB_CLK_SOFT_RESET; /* * FMT0_SOFT_RESET enum */ FMT0_SOFT_RESET; /* * FMT1_SOFT_RESET enum */ FMT1_SOFT_RESET; /* * FMT2_SOFT_RESET enum */ FMT2_SOFT_RESET; /* * FMT3_SOFT_RESET enum */ FMT3_SOFT_RESET; /* * FMT4_SOFT_RESET enum */ FMT4_SOFT_RESET; /* * FMT5_SOFT_RESET enum */ FMT5_SOFT_RESET; /* * MVP_SOFT_RESET enum */ MVP_SOFT_RESET; /* * ABM_SOFT_RESET enum */ ABM_SOFT_RESET; /* * DVO_SOFT_RESET enum */ DVO_SOFT_RESET; /* * DIGA_FE_SOFT_RESET enum */ DIGA_FE_SOFT_RESET; /* * DIGA_BE_SOFT_RESET enum */ DIGA_BE_SOFT_RESET; /* * DIGB_FE_SOFT_RESET enum */ DIGB_FE_SOFT_RESET; /* * DIGB_BE_SOFT_RESET enum */ DIGB_BE_SOFT_RESET; /* * DIGC_FE_SOFT_RESET enum */ DIGC_FE_SOFT_RESET; /* * DIGC_BE_SOFT_RESET enum */ DIGC_BE_SOFT_RESET; /* * DIGD_FE_SOFT_RESET enum */ DIGD_FE_SOFT_RESET; /* * DIGD_BE_SOFT_RESET enum */ DIGD_BE_SOFT_RESET; /* * DIGE_FE_SOFT_RESET enum */ DIGE_FE_SOFT_RESET; /* * DIGE_BE_SOFT_RESET enum */ DIGE_BE_SOFT_RESET; /* * DIGF_FE_SOFT_RESET enum */ DIGF_FE_SOFT_RESET; /* * DIGF_BE_SOFT_RESET enum */ DIGF_BE_SOFT_RESET; /* * DIGG_FE_SOFT_RESET enum */ DIGG_FE_SOFT_RESET; /* * DIGG_BE_SOFT_RESET enum */ DIGG_BE_SOFT_RESET; /* * DPDBG_SOFT_RESET enum */ DPDBG_SOFT_RESET; /* * DIGLPA_FE_SOFT_RESET enum */ DIGLPA_FE_SOFT_RESET; /* * DIGLPA_BE_SOFT_RESET enum */ DIGLPA_BE_SOFT_RESET; /* * DIGLPB_FE_SOFT_RESET enum */ DIGLPB_FE_SOFT_RESET; /* * DIGLPB_BE_SOFT_RESET enum */ DIGLPB_BE_SOFT_RESET; /* * GENERICA_STEREOSYNC_SEL enum */ GENERICA_STEREOSYNC_SEL; /* * GENERICB_STEREOSYNC_SEL enum */ GENERICB_STEREOSYNC_SEL; /* * DCO_DBG_BLOCK_SEL enum */ DCO_DBG_BLOCK_SEL; /* * DCO_HDMI_RXSTATUS_TIMER_CONTROL_DCO_HDMI_RXSTATUS_TIMER_TYPE enum */ DCO_HDMI_RXSTATUS_TIMER_CONTROL_DCO_HDMI_RXSTATUS_TIMER_TYPE; /* * FMT420_MEMORY_SOURCE_SEL enum */ FMT420_MEMORY_SOURCE_SEL; /******************************************************* * DOUT_I2C Enums *******************************************************/ /* * DOUT_I2C_CONTROL_GO enum */ DOUT_I2C_CONTROL_GO; /* * DOUT_I2C_CONTROL_SOFT_RESET enum */ DOUT_I2C_CONTROL_SOFT_RESET; /* * DOUT_I2C_CONTROL_SEND_RESET enum */ DOUT_I2C_CONTROL_SEND_RESET; /* * DOUT_I2C_CONTROL_SW_STATUS_RESET enum */ DOUT_I2C_CONTROL_SW_STATUS_RESET; /* * DOUT_I2C_CONTROL_DDC_SELECT enum */ DOUT_I2C_CONTROL_DDC_SELECT; /* * DOUT_I2C_CONTROL_TRANSACTION_COUNT enum */ DOUT_I2C_CONTROL_TRANSACTION_COUNT; /* * DOUT_I2C_CONTROL_DBG_REF_SEL enum */ DOUT_I2C_CONTROL_DBG_REF_SEL; /* * DOUT_I2C_ARBITRATION_SW_PRIORITY enum */ DOUT_I2C_ARBITRATION_SW_PRIORITY; /* * DOUT_I2C_ARBITRATION_NO_QUEUED_SW_GO enum */ DOUT_I2C_ARBITRATION_NO_QUEUED_SW_GO; /* * DOUT_I2C_ARBITRATION_ABORT_XFER enum */ DOUT_I2C_ARBITRATION_ABORT_XFER; /* * DOUT_I2C_ARBITRATION_USE_I2C_REG_REQ enum */ DOUT_I2C_ARBITRATION_USE_I2C_REG_REQ; /* * DOUT_I2C_ARBITRATION_DONE_USING_I2C_REG enum */ DOUT_I2C_ARBITRATION_DONE_USING_I2C_REG; /* * DOUT_I2C_ACK enum */ DOUT_I2C_ACK; /* * DOUT_I2C_DDC_SPEED_THRESHOLD enum */ DOUT_I2C_DDC_SPEED_THRESHOLD; /* * DOUT_I2C_DDC_SETUP_DATA_DRIVE_EN enum */ DOUT_I2C_DDC_SETUP_DATA_DRIVE_EN; /* * DOUT_I2C_DDC_SETUP_DATA_DRIVE_SEL enum */ DOUT_I2C_DDC_SETUP_DATA_DRIVE_SEL; /* * DOUT_I2C_DDC_SETUP_EDID_DETECT_MODE enum */ DOUT_I2C_DDC_SETUP_EDID_DETECT_MODE; /* * DOUT_I2C_DDC_SETUP_CLK_DRIVE_EN enum */ DOUT_I2C_DDC_SETUP_CLK_DRIVE_EN; /* * DOUT_I2C_TRANSACTION_STOP_ON_NACK enum */ DOUT_I2C_TRANSACTION_STOP_ON_NACK; /* * DOUT_I2C_DATA_INDEX_WRITE enum */ DOUT_I2C_DATA_INDEX_WRITE; /* * DOUT_I2C_EDID_DETECT_CTRL_SEND_RESET enum */ DOUT_I2C_EDID_DETECT_CTRL_SEND_RESET; /* * DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE enum */ DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE; /******************************************************* * FBC Enums *******************************************************/ /* * FBC_IDLE_MASK_MASK_BITS enum */ FBC_IDLE_MASK_MASK_BITS; /******************************************************* * DPCSRX Enums *******************************************************/ /* * DPCSRX_RX_CLOCK_CNTL_DPCS_SYMCLK_RX_SEL enum */ DPCSRX_RX_CLOCK_CNTL_DPCS_SYMCLK_RX_SEL; /* * DPCSRX_DBG_CFGCLK_SEL enum */ DPCSRX_DBG_CFGCLK_SEL; /* * DPCSRX_RX_SYMCLK_SEL enum */ DPCSRX_RX_SYMCLK_SEL; /******************************************************* * DPCSTX Enums *******************************************************/ /* * DPCSTX_DBG_CFGCLK_SEL enum */ DPCSTX_DBG_CFGCLK_SEL; /* * DPCSTX_TX_SYMCLK_SEL enum */ DPCSTX_TX_SYMCLK_SEL; /* * DPCSTX_TX_SYMCLK_DIV2_SEL enum */ DPCSTX_TX_SYMCLK_DIV2_SEL; /******************************************************* * CB Enums *******************************************************/ /* * SurfaceNumber enum */ SurfaceNumber; /* * SurfaceSwap enum */ SurfaceSwap; /* * CBMode enum */ CBMode; /* * RoundMode enum */ RoundMode; /* * SourceFormat enum */ SourceFormat; /* * BlendOp enum */ BlendOp; /* * CombFunc enum */ CombFunc; /* * BlendOpt enum */ BlendOpt; /* * CmaskCode enum */ CmaskCode; /* * CmaskAddr enum */ CmaskAddr; /* * MemArbMode enum */ MemArbMode; /* * CBPerfSel enum */ CBPerfSel; /* * CBPerfOpFilterSel enum */ CBPerfOpFilterSel; /* * CBPerfClearFilterSel enum */ CBPerfClearFilterSel; /******************************************************* * TC Enums *******************************************************/ /* * TC_OP_MASKS enum */ TC_OP_MASKS; /* * TC_OP enum */ TC_OP; /* * TC_CHUB_REQ_CREDITS_ENUM enum */ TC_CHUB_REQ_CREDITS_ENUM; /* * CHUB_TC_RET_CREDITS_ENUM enum */ CHUB_TC_RET_CREDITS_ENUM; /* * TC_NACKS enum */ TC_NACKS; /* * TC_EA_CID enum */ TC_EA_CID; /******************************************************* * SPI Enums *******************************************************/ /* * SPI_SAMPLE_CNTL enum */ SPI_SAMPLE_CNTL; /* * SPI_FOG_MODE enum */ SPI_FOG_MODE; /* * SPI_PNT_SPRITE_OVERRIDE enum */ SPI_PNT_SPRITE_OVERRIDE; /* * SPI_PERFCNT_SEL enum */ SPI_PERFCNT_SEL; /* * SPI_SHADER_FORMAT enum */ SPI_SHADER_FORMAT; /* * SPI_SHADER_EX_FORMAT enum */ SPI_SHADER_EX_FORMAT; /* * CLKGATE_SM_MODE enum */ CLKGATE_SM_MODE; /* * CLKGATE_BASE_MODE enum */ CLKGATE_BASE_MODE; /******************************************************* * SQ Enums *******************************************************/ /* * SQ_TEX_CLAMP enum */ SQ_TEX_CLAMP; /* * SQ_TEX_XY_FILTER enum */ SQ_TEX_XY_FILTER; /* * SQ_TEX_Z_FILTER enum */ SQ_TEX_Z_FILTER; /* * SQ_TEX_MIP_FILTER enum */ SQ_TEX_MIP_FILTER; /* * SQ_TEX_ANISO_RATIO enum */ SQ_TEX_ANISO_RATIO; /* * SQ_TEX_DEPTH_COMPARE enum */ SQ_TEX_DEPTH_COMPARE; /* * SQ_TEX_BORDER_COLOR enum */ SQ_TEX_BORDER_COLOR; /* * SQ_RSRC_BUF_TYPE enum */ SQ_RSRC_BUF_TYPE; /* * SQ_RSRC_IMG_TYPE enum */ SQ_RSRC_IMG_TYPE; /* * SQ_RSRC_FLAT_TYPE enum */ SQ_RSRC_FLAT_TYPE; /* * SQ_IMG_FILTER_TYPE enum */ SQ_IMG_FILTER_TYPE; /* * SQ_SEL_XYZW01 enum */ SQ_SEL_XYZW01; /* * SQ_WAVE_TYPE enum */ SQ_WAVE_TYPE; /* * SQ_THREAD_TRACE_TOKEN_TYPE enum */ SQ_THREAD_TRACE_TOKEN_TYPE; /* * SQ_THREAD_TRACE_MISC_TOKEN_TYPE enum */ SQ_THREAD_TRACE_MISC_TOKEN_TYPE; /* * SQ_THREAD_TRACE_INST_TYPE enum */ SQ_THREAD_TRACE_INST_TYPE; /* * SQ_THREAD_TRACE_REG_TYPE enum */ SQ_THREAD_TRACE_REG_TYPE; /* * SQ_THREAD_TRACE_REG_OP enum */ SQ_THREAD_TRACE_REG_OP; /* * SQ_THREAD_TRACE_MODE_SEL enum */ SQ_THREAD_TRACE_MODE_SEL; /* * SQ_THREAD_TRACE_CAPTURE_MODE enum */ SQ_THREAD_TRACE_CAPTURE_MODE; /* * SQ_THREAD_TRACE_VM_ID_MASK enum */ SQ_THREAD_TRACE_VM_ID_MASK; /* * SQ_THREAD_TRACE_WAVE_MASK enum */ SQ_THREAD_TRACE_WAVE_MASK; /* * SQ_THREAD_TRACE_ISSUE enum */ SQ_THREAD_TRACE_ISSUE; /* * SQ_THREAD_TRACE_ISSUE_MASK enum */ SQ_THREAD_TRACE_ISSUE_MASK; /* * SQ_PERF_SEL enum */ SQ_PERF_SEL; /* * SQ_CAC_POWER_SEL enum */ SQ_CAC_POWER_SEL; /* * SQ_IND_CMD_CMD enum */ SQ_IND_CMD_CMD; /* * SQ_IND_CMD_MODE enum */ SQ_IND_CMD_MODE; /* * SQ_EDC_INFO_SOURCE enum */ SQ_EDC_INFO_SOURCE; /* * SQ_ROUND_MODE enum */ SQ_ROUND_MODE; /* * SQ_INTERRUPT_WORD_ENCODING enum */ SQ_INTERRUPT_WORD_ENCODING; /* * ENUM_SQ_EXPORT_RAT_INST enum */ ENUM_SQ_EXPORT_RAT_INST; /* * SQ_IBUF_ST enum */ SQ_IBUF_ST; /* * SQ_INST_STR_ST enum */ SQ_INST_STR_ST; /* * SQ_WAVE_IB_ECC_ST enum */ SQ_WAVE_IB_ECC_ST; /* * SH_MEM_ADDRESS_MODE enum */ SH_MEM_ADDRESS_MODE; /* * SH_MEM_ALIGNMENT_MODE enum */ SH_MEM_ALIGNMENT_MODE; /* * SQ_THREAD_TRACE_WAVE_START_COUNT_PREFIX enum */ SQ_THREAD_TRACE_WAVE_START_COUNT_PREFIX; /* * SQ_LB_CTR_SEL_VALUES enum */ SQ_LB_CTR_SEL_VALUES; /* * SQ_WAVE_TYPE value */ #define SQ_WAVE_TYPE_PS0 … /* * SQIND_PARTITIONS value */ #define SQIND_GLOBAL_REGS_OFFSET … #define SQIND_GLOBAL_REGS_SIZE … #define SQIND_LOCAL_REGS_OFFSET … #define SQIND_LOCAL_REGS_SIZE … #define SQIND_WAVE_HWREGS_OFFSET … #define SQIND_WAVE_HWREGS_SIZE … #define SQIND_WAVE_SGPRS_OFFSET … #define SQIND_WAVE_SGPRS_SIZE … #define SQIND_WAVE_VGPRS_OFFSET … #define SQIND_WAVE_VGPRS_SIZE … /* * SQ_GFXDEC value */ #define SQ_GFXDEC_BEGIN … #define SQ_GFXDEC_END … #define SQ_GFXDEC_STATE_ID_SHIFT … /* * SQDEC value */ #define SQDEC_BEGIN … #define SQDEC_END … /* * SQPERFSDEC value */ #define SQPERFSDEC_BEGIN … #define SQPERFSDEC_END … /* * SQPERFDDEC value */ #define SQPERFDDEC_BEGIN … #define SQPERFDDEC_END … /* * SQGFXUDEC value */ #define SQGFXUDEC_BEGIN … #define SQGFXUDEC_END … /* * SQPWRDEC value */ #define SQPWRDEC_BEGIN … #define SQPWRDEC_END … /* * SQ_DISPATCHER value */ #define SQ_DISPATCHER_GFX_MIN … #define SQ_DISPATCHER_GFX_CNT_PER_RING … /* * SQ_MAX value */ #define SQ_MAX_PGM_SGPRS … #define SQ_MAX_PGM_VGPRS … /* * SQ_THREAD_TRACE_TIME_UNIT value */ #define SQ_THREAD_TRACE_TIME_UNIT … /* * SQ_EXCP_BITS value */ #define SQ_EX_MODE_EXCP_VALU_BASE … #define SQ_EX_MODE_EXCP_VALU_SIZE … #define SQ_EX_MODE_EXCP_INVALID … #define SQ_EX_MODE_EXCP_INPUT_DENORM … #define SQ_EX_MODE_EXCP_DIV0 … #define SQ_EX_MODE_EXCP_OVERFLOW … #define SQ_EX_MODE_EXCP_UNDERFLOW … #define SQ_EX_MODE_EXCP_INEXACT … #define SQ_EX_MODE_EXCP_INT_DIV0 … #define SQ_EX_MODE_EXCP_ADDR_WATCH0 … #define SQ_EX_MODE_EXCP_MEM_VIOL … /* * SQ_EXCP_HI_BITS value */ #define SQ_EX_MODE_EXCP_HI_ADDR_WATCH1 … #define SQ_EX_MODE_EXCP_HI_ADDR_WATCH2 … #define SQ_EX_MODE_EXCP_HI_ADDR_WATCH3 … /* * HW_INSERTED_INST_ID value */ #define INST_ID_PRIV_START … #define INST_ID_ECC_INTERRUPT_MSG … #define INST_ID_TTRACE_NEW_PC_MSG … #define INST_ID_HW_TRAP … #define INST_ID_KILL_SEQ … #define INST_ID_SPI_WREXEC … #define INST_ID_HOST_REG_TRAP_MSG … /* * SIMM16_WAITCNT_PARTITIONS value */ #define SIMM16_WAITCNT_VM_CNT_START … #define SIMM16_WAITCNT_VM_CNT_SIZE … #define SIMM16_WAITCNT_EXP_CNT_START … #define SIMM16_WAITCNT_EXP_CNT_SIZE … #define SIMM16_WAITCNT_LGKM_CNT_START … #define SIMM16_WAITCNT_LGKM_CNT_SIZE … #define SIMM16_WAITCNT_VM_CNT_HI_START … #define SIMM16_WAITCNT_VM_CNT_HI_SIZE … /* * SQ_EDC_FUE_CNTL_BITS value */ #define SQ_EDC_FUE_CNTL_SQ … #define SQ_EDC_FUE_CNTL_LDS … #define SQ_EDC_FUE_CNTL_SIMD0 … #define SQ_EDC_FUE_CNTL_SIMD1 … #define SQ_EDC_FUE_CNTL_SIMD2 … #define SQ_EDC_FUE_CNTL_SIMD3 … #define SQ_EDC_FUE_CNTL_TA … #define SQ_EDC_FUE_CNTL_TD … #define SQ_EDC_FUE_CNTL_TCP … /******************************************************* * COMP Enums *******************************************************/ /* * CSDATA_TYPE enum */ CSDATA_TYPE; /* * CSDATA_TYPE_WIDTH value */ #define CSDATA_TYPE_WIDTH … /* * CSDATA_ADDR_WIDTH value */ #define CSDATA_ADDR_WIDTH … /* * CSDATA_DATA_WIDTH value */ #define CSDATA_DATA_WIDTH … /******************************************************* * VGT Enums *******************************************************/ /* * VGT_OUT_PRIM_TYPE enum */ VGT_OUT_PRIM_TYPE; /* * VGT_DI_PRIM_TYPE enum */ VGT_DI_PRIM_TYPE; /* * VGT_DI_SOURCE_SELECT enum */ VGT_DI_SOURCE_SELECT; /* * VGT_DI_MAJOR_MODE_SELECT enum */ VGT_DI_MAJOR_MODE_SELECT; /* * VGT_DI_INDEX_SIZE enum */ VGT_DI_INDEX_SIZE; /* * VGT_EVENT_TYPE enum */ VGT_EVENT_TYPE; /* * VGT_DMA_SWAP_MODE enum */ VGT_DMA_SWAP_MODE; /* * VGT_INDEX_TYPE_MODE enum */ VGT_INDEX_TYPE_MODE; /* * VGT_DMA_BUF_TYPE enum */ VGT_DMA_BUF_TYPE; /* * VGT_OUTPATH_SELECT enum */ VGT_OUTPATH_SELECT; /* * VGT_GRP_PRIM_TYPE enum */ VGT_GRP_PRIM_TYPE; /* * VGT_GRP_PRIM_ORDER enum */ VGT_GRP_PRIM_ORDER; /* * VGT_GROUP_CONV_SEL enum */ VGT_GROUP_CONV_SEL; /* * VGT_GS_MODE_TYPE enum */ VGT_GS_MODE_TYPE; /* * VGT_GS_CUT_MODE enum */ VGT_GS_CUT_MODE; /* * VGT_GS_OUTPRIM_TYPE enum */ VGT_GS_OUTPRIM_TYPE; /* * VGT_CACHE_INVALID_MODE enum */ VGT_CACHE_INVALID_MODE; /* * VGT_TESS_TYPE enum */ VGT_TESS_TYPE; /* * VGT_TESS_PARTITION enum */ VGT_TESS_PARTITION; /* * VGT_TESS_TOPOLOGY enum */ VGT_TESS_TOPOLOGY; /* * VGT_RDREQ_POLICY enum */ VGT_RDREQ_POLICY; /* * VGT_DIST_MODE enum */ VGT_DIST_MODE; /* * VGT_STAGES_LS_EN enum */ VGT_STAGES_LS_EN; /* * VGT_STAGES_HS_EN enum */ VGT_STAGES_HS_EN; /* * VGT_STAGES_ES_EN enum */ VGT_STAGES_ES_EN; /* * VGT_STAGES_GS_EN enum */ VGT_STAGES_GS_EN; /* * VGT_STAGES_VS_EN enum */ VGT_STAGES_VS_EN; /* * VGT_PERFCOUNT_SELECT enum */ VGT_PERFCOUNT_SELECT; /* * IA_PERFCOUNT_SELECT enum */ IA_PERFCOUNT_SELECT; /* * WD_PERFCOUNT_SELECT enum */ WD_PERFCOUNT_SELECT; /* * WD_IA_DRAW_TYPE enum */ WD_IA_DRAW_TYPE; /* * WD_IA_DRAW_REG_XFER enum */ WD_IA_DRAW_REG_XFER; /* * WD_IA_DRAW_SOURCE enum */ WD_IA_DRAW_SOURCE; /* * GS_THREADID_SIZE value */ #define GSTHREADID_SIZE … /******************************************************* * GB Enums *******************************************************/ /* * GB_EDC_DED_MODE enum */ GB_EDC_DED_MODE; /* * VALUE_GB_TILING_CONFIG_TABLE_SIZE value */ #define GB_TILING_CONFIG_TABLE_SIZE … /* * VALUE_GB_TILING_CONFIG_MACROTABLE_SIZE value */ #define GB_TILING_CONFIG_MACROTABLE_SIZE … /******************************************************* * TP Enums *******************************************************/ /* * TA_TC_ADDR_MODES enum */ TA_TC_ADDR_MODES; /* * TA_PERFCOUNT_SEL enum */ TA_PERFCOUNT_SEL; /* * TD_PERFCOUNT_SEL enum */ TD_PERFCOUNT_SEL; /* * TCP_PERFCOUNT_SELECT enum */ TCP_PERFCOUNT_SELECT; /* * TCP_CACHE_POLICIES enum */ TCP_CACHE_POLICIES; /* * TCP_CACHE_STORE_POLICIES enum */ TCP_CACHE_STORE_POLICIES; /* * TCP_WATCH_MODES enum */ TCP_WATCH_MODES; /* * TCP_DSM_DATA_SEL enum */ TCP_DSM_DATA_SEL; /* * TCP_DSM_SINGLE_WRITE enum */ TCP_DSM_SINGLE_WRITE; /* * TCP_DSM_INJECT_SEL enum */ TCP_DSM_INJECT_SEL; /******************************************************* * TCC Enums *******************************************************/ /* * TCC_PERF_SEL enum */ TCC_PERF_SEL; /* * TCA_PERF_SEL enum */ TCA_PERF_SEL; /******************************************************* * GRBM Enums *******************************************************/ /* * GRBM_PERF_SEL enum */ GRBM_PERF_SEL; /* * GRBM_SE0_PERF_SEL enum */ GRBM_SE0_PERF_SEL; /* * GRBM_SE1_PERF_SEL enum */ GRBM_SE1_PERF_SEL; /* * GRBM_SE2_PERF_SEL enum */ GRBM_SE2_PERF_SEL; /* * GRBM_SE3_PERF_SEL enum */ GRBM_SE3_PERF_SEL; /******************************************************* * CP Enums *******************************************************/ /* * CP_RING_ID enum */ CP_RING_ID; /* * CP_PIPE_ID enum */ CP_PIPE_ID; /* * CP_ME_ID enum */ CP_ME_ID; /* * SPM_PERFMON_STATE enum */ SPM_PERFMON_STATE; /* * CP_PERFMON_STATE enum */ CP_PERFMON_STATE; /* * CP_PERFMON_ENABLE_MODE enum */ CP_PERFMON_ENABLE_MODE; /* * CPG_PERFCOUNT_SEL enum */ CPG_PERFCOUNT_SEL; /* * CPF_PERFCOUNT_SEL enum */ CPF_PERFCOUNT_SEL; /* * CPC_PERFCOUNT_SEL enum */ CPC_PERFCOUNT_SEL; /* * CP_ALPHA_TAG_RAM_SEL enum */ CP_ALPHA_TAG_RAM_SEL; /* * SEM_RESPONSE value */ #define SEM_ECC_ERROR … #define SEM_TRANS_ERROR … #define SEM_FAILED … #define SEM_PASSED … /* * IQ_RETRY_TYPE value */ #define IQ_QUEUE_SLEEP … #define IQ_OFFLOAD_RETRY … #define IQ_SCH_WAVE_MSG … #define IQ_SEM_REARM … #define IQ_DEQUEUE_RETRY … /* * IQ_INTR_TYPE value */ #define IQ_INTR_TYPE_PQ … #define IQ_INTR_TYPE_IB … #define IQ_INTR_TYPE_MQD … /* * VMID_SIZE value */ #define VMID_SZ … /* * CONFIG_SPACE value */ #define CONFIG_SPACE_START … #define CONFIG_SPACE_END … /* * CONFIG_SPACE1 value */ #define CONFIG_SPACE1_START … #define CONFIG_SPACE1_END … /* * CONFIG_SPACE2 value */ #define CONFIG_SPACE2_START … #define CONFIG_SPACE2_END … /* * UCONFIG_SPACE value */ #define UCONFIG_SPACE_START … #define UCONFIG_SPACE_END … /* * PERSISTENT_SPACE value */ #define PERSISTENT_SPACE_START … #define PERSISTENT_SPACE_END … /* * CONTEXT_SPACE value */ #define CONTEXT_SPACE_START … #define CONTEXT_SPACE_END … /******************************************************* * SQ_UC Enums *******************************************************/ /* * VALUE_SQ_ENC_SOP1 value */ #define SQ_ENC_SOP1_BITS … #define SQ_ENC_SOP1_MASK … #define SQ_ENC_SOP1_FIELD … /* * VALUE_SQ_ENC_SOPC value */ #define SQ_ENC_SOPC_BITS … #define SQ_ENC_SOPC_MASK … #define SQ_ENC_SOPC_FIELD … /* * VALUE_SQ_ENC_SOPP value */ #define SQ_ENC_SOPP_BITS … #define SQ_ENC_SOPP_MASK … #define SQ_ENC_SOPP_FIELD … /* * VALUE_SQ_ENC_SOPK value */ #define SQ_ENC_SOPK_BITS … #define SQ_ENC_SOPK_MASK … #define SQ_ENC_SOPK_FIELD … /* * VALUE_SQ_ENC_SOP2 value */ #define SQ_ENC_SOP2_BITS … #define SQ_ENC_SOP2_MASK … #define SQ_ENC_SOP2_FIELD … /* * VALUE_SQ_ENC_SMEM value */ #define SQ_ENC_SMEM_BITS … #define SQ_ENC_SMEM_MASK … #define SQ_ENC_SMEM_FIELD … /* * VALUE_SQ_ENC_VOP1 value */ #define SQ_ENC_VOP1_BITS … #define SQ_ENC_VOP1_MASK … #define SQ_ENC_VOP1_FIELD … /* * VALUE_SQ_ENC_VOPC value */ #define SQ_ENC_VOPC_BITS … #define SQ_ENC_VOPC_MASK … #define SQ_ENC_VOPC_FIELD … /* * VALUE_SQ_ENC_VOP2 value */ #define SQ_ENC_VOP2_BITS … #define SQ_ENC_VOP2_MASK … #define SQ_ENC_VOP2_FIELD … /* * VALUE_SQ_ENC_VINTRP value */ #define SQ_ENC_VINTRP_BITS … #define SQ_ENC_VINTRP_MASK … #define SQ_ENC_VINTRP_FIELD … /* * VALUE_SQ_ENC_VOP3P value */ #define SQ_ENC_VOP3P_BITS … #define SQ_ENC_VOP3P_MASK … #define SQ_ENC_VOP3P_FIELD … /* * VALUE_SQ_ENC_VOP3 value */ #define SQ_ENC_VOP3_BITS … #define SQ_ENC_VOP3_MASK … #define SQ_ENC_VOP3_FIELD … /* * VALUE_SQ_ENC_DS value */ #define SQ_ENC_DS_BITS … #define SQ_ENC_DS_MASK … #define SQ_ENC_DS_FIELD … /* * VALUE_SQ_ENC_MUBUF value */ #define SQ_ENC_MUBUF_BITS … #define SQ_ENC_MUBUF_MASK … #define SQ_ENC_MUBUF_FIELD … /* * VALUE_SQ_ENC_MTBUF value */ #define SQ_ENC_MTBUF_BITS … #define SQ_ENC_MTBUF_MASK … #define SQ_ENC_MTBUF_FIELD … /* * VALUE_SQ_ENC_MIMG value */ #define SQ_ENC_MIMG_BITS … #define SQ_ENC_MIMG_MASK … #define SQ_ENC_MIMG_FIELD … /* * VALUE_SQ_ENC_EXP value */ #define SQ_ENC_EXP_BITS … #define SQ_ENC_EXP_MASK … #define SQ_ENC_EXP_FIELD … /* * VALUE_SQ_ENC_FLAT value */ #define SQ_ENC_FLAT_BITS … #define SQ_ENC_FLAT_MASK … #define SQ_ENC_FLAT_FIELD … /* * VALUE_SQ_V_OP3_INTRP_COUNT value */ #define SQ_V_OP3_INTRP_COUNT … /* * VALUE_SQ_SENDMSG_SYSTEM_SIZE value */ #define SQ_SENDMSG_SYSTEM_SIZE … /* * VALUE_SQ_HWREG_ID_SIZE value */ #define SQ_HWREG_ID_SIZE … /* * VALUE_SQ_V_OPC_COUNT value */ #define SQ_V_OPC_COUNT … /* * VALUE_SQ_NUM_VGPR value */ #define SQ_NUM_VGPR … /* * VALUE_SQ_WAITCNT_LGKM_SHIFT value */ #define SQ_WAITCNT_LGKM_SHIFT … /* * VALUE_SQ_HWREG_ID_SHIFT value */ #define SQ_HWREG_ID_SHIFT … /* * VALUE_SQ_EXP_NUM_POS value */ #define SQ_EXP_NUM_POS … /* * VALUE_SQ_XLATE_VOP3_TO_VOPC_OFFSET value */ #define SQ_XLATE_VOP3_TO_VOPC_OFFSET … /* * VALUE_SQ_V_OP3_2IN_OFFSET value */ #define SQ_V_OP3_2IN_OFFSET … /* * VALUE_SQ_XLATE_VOP3_TO_VOP2_OFFSET value */ #define SQ_XLATE_VOP3_TO_VOP2_OFFSET … /* * VALUE_SQ_EXP_NUM_MRT value */ #define SQ_EXP_NUM_MRT … /* * VALUE_SQ_NUM_TTMP value */ #define SQ_NUM_TTMP … /* * VALUE_SQ_SENDMSG_STREAMID_SHIFT value */ #define SQ_SENDMSG_STREAMID_SHIFT … /* * VALUE_SQ_V_OP1_COUNT value */ #define SQ_V_OP1_COUNT … /* * VALUE_SQ_WAITCNT_LGKM_SIZE value */ #define SQ_WAITCNT_LGKM_SIZE … /* * VALUE_SQ_XLATE_VOP3_TO_VOPC_COUNT value */ #define SQ_XLATE_VOP3_TO_VOPC_COUNT … /* * VALUE_SQ_SENDMSG_MSG_SHIFT value */ #define SQ_SENDMSG_MSG_SHIFT … /* * VALUE_SQ_V_OP3_3IN_OFFSET value */ #define SQ_V_OP3_3IN_OFFSET … /* * VALUE_SQ_HWREG_OFFSET_SHIFT value */ #define SQ_HWREG_OFFSET_SHIFT … /* * VALUE_SQ_HWREG_SIZE_SHIFT value */ #define SQ_HWREG_SIZE_SHIFT … /* * VALUE_SQ_HWREG_OFFSET_SIZE value */ #define SQ_HWREG_OFFSET_SIZE … /* * VALUE_SQ_V_OP3_3IN_COUNT value */ #define SQ_V_OP3_3IN_COUNT … /* * VALUE_SQ_SENDMSG_MSG_SIZE value */ #define SQ_SENDMSG_MSG_SIZE … /* * VALUE_SQ_XLATE_VOP3_TO_VOP1_COUNT value */ #define SQ_XLATE_VOP3_TO_VOP1_COUNT … /* * VALUE_SQ_EXP_NUM_GDS value */ #define SQ_EXP_NUM_GDS … /* * VALUE_SQ_V_OP2_COUNT value */ #define SQ_V_OP2_COUNT … /* * VALUE_SQ_SENDMSG_GSOP_SIZE value */ #define SQ_SENDMSG_GSOP_SIZE … /* * VALUE_SQ_WAITCNT_VM_SHIFT value */ #define SQ_WAITCNT_VM_SHIFT … /* * VALUE_SQ_XLATE_VOP3_TO_VOP3P_COUNT value */ #define SQ_XLATE_VOP3_TO_VOP3P_COUNT … /* * VALUE_SQ_V_OP3_2IN_COUNT value */ #define SQ_V_OP3_2IN_COUNT … /* * VALUE_SQ_SENDMSG_SYSTEM_SHIFT value */ #define SQ_SENDMSG_SYSTEM_SHIFT … /* * VALUE_SQ_WAITCNT_VM_SIZE value */ #define SQ_WAITCNT_VM_SIZE … /* * VALUE_SQ_XLATE_VOP3_TO_VOP3P_OFFSET value */ #define SQ_XLATE_VOP3_TO_VOP3P_OFFSET … /* * VALUE_SQ_WAITCNT_EXP_SHIFT value */ #define SQ_WAITCNT_EXP_SHIFT … /* * VALUE_SQ_XLATE_VOP3_TO_VOP2_COUNT value */ #define SQ_XLATE_VOP3_TO_VOP2_COUNT … /* * VALUE_SQ_EXP_NUM_PARAM value */ #define SQ_EXP_NUM_PARAM … /* * VALUE_SQ_HWREG_SIZE_SIZE value */ #define SQ_HWREG_SIZE_SIZE … /* * VALUE_SQ_WAITCNT_EXP_SIZE value */ #define SQ_WAITCNT_EXP_SIZE … /* * VALUE_SQ_V_OP3_INTRP_OFFSET value */ #define SQ_V_OP3_INTRP_OFFSET … /* * VALUE_SQ_SENDMSG_GSOP_SHIFT value */ #define SQ_SENDMSG_GSOP_SHIFT … /* * VALUE_SQ_XLATE_VOP3_TO_VINTRP_OFFSET value */ #define SQ_XLATE_VOP3_TO_VINTRP_OFFSET … /* * VALUE_SQ_NUM_ATTR value */ #define SQ_NUM_ATTR … /* * VALUE_SQ_NUM_SGPR value */ #define SQ_NUM_SGPR … /* * VALUE_SQ_SRC_VGPR_BIT value */ #define SQ_SRC_VGPR_BIT … /* * VALUE_SQ_V_INTRP_COUNT value */ #define SQ_V_INTRP_COUNT … /* * VALUE_SQ_SENDMSG_STREAMID_SIZE value */ #define SQ_SENDMSG_STREAMID_SIZE … /* * VALUE_SQ_V_OP3P_COUNT value */ #define SQ_V_OP3P_COUNT … /* * VALUE_SQ_XLATE_VOP3_TO_VOP1_OFFSET value */ #define SQ_XLATE_VOP3_TO_VOP1_OFFSET … /* * VALUE_SQ_XLATE_VOP3_TO_VINTRP_COUNT value */ #define SQ_XLATE_VOP3_TO_VINTRP_COUNT … /* * VALUE_SQ_SSRC_SPECIAL_DPP value */ #define SQ_SRC_DPP … /* * VALUE_SQ_OP_MTBUF value */ #define SQ_TBUFFER_LOAD_FORMAT_X … #define SQ_TBUFFER_LOAD_FORMAT_XY … #define SQ_TBUFFER_LOAD_FORMAT_XYZ … #define SQ_TBUFFER_LOAD_FORMAT_XYZW … #define SQ_TBUFFER_STORE_FORMAT_X … #define SQ_TBUFFER_STORE_FORMAT_XY … #define SQ_TBUFFER_STORE_FORMAT_XYZ … #define SQ_TBUFFER_STORE_FORMAT_XYZW … #define SQ_TBUFFER_LOAD_FORMAT_D16_X … #define SQ_TBUFFER_LOAD_FORMAT_D16_XY … #define SQ_TBUFFER_LOAD_FORMAT_D16_XYZ … #define SQ_TBUFFER_LOAD_FORMAT_D16_XYZW … #define SQ_TBUFFER_STORE_FORMAT_D16_X … #define SQ_TBUFFER_STORE_FORMAT_D16_XY … #define SQ_TBUFFER_STORE_FORMAT_D16_XYZ … #define SQ_TBUFFER_STORE_FORMAT_D16_XYZW … /* * VALUE_SQ_OP_FLAT_GLBL value */ #define SQ_GLOBAL_LOAD_UBYTE … #define SQ_GLOBAL_LOAD_SBYTE … #define SQ_GLOBAL_LOAD_USHORT … #define SQ_GLOBAL_LOAD_SSHORT … #define SQ_GLOBAL_LOAD_DWORD … #define SQ_GLOBAL_LOAD_DWORDX2 … #define SQ_GLOBAL_LOAD_DWORDX3 … #define SQ_GLOBAL_LOAD_DWORDX4 … #define SQ_GLOBAL_STORE_BYTE … #define SQ_GLOBAL_STORE_SHORT … #define SQ_GLOBAL_STORE_DWORD … #define SQ_GLOBAL_STORE_DWORDX2 … #define SQ_GLOBAL_STORE_DWORDX3 … #define SQ_GLOBAL_STORE_DWORDX4 … #define SQ_GLOBAL_ATOMIC_SWAP … #define SQ_GLOBAL_ATOMIC_CMPSWAP … #define SQ_GLOBAL_ATOMIC_ADD … #define SQ_GLOBAL_ATOMIC_SUB … #define SQ_GLOBAL_ATOMIC_SMIN … #define SQ_GLOBAL_ATOMIC_UMIN … #define SQ_GLOBAL_ATOMIC_SMAX … #define SQ_GLOBAL_ATOMIC_UMAX … #define SQ_GLOBAL_ATOMIC_AND … #define SQ_GLOBAL_ATOMIC_OR … #define SQ_GLOBAL_ATOMIC_XOR … #define SQ_GLOBAL_ATOMIC_INC … #define SQ_GLOBAL_ATOMIC_DEC … #define SQ_GLOBAL_ATOMIC_SWAP_X2 … #define SQ_GLOBAL_ATOMIC_CMPSWAP_X2 … #define SQ_GLOBAL_ATOMIC_ADD_X2 … #define SQ_GLOBAL_ATOMIC_SUB_X2 … #define SQ_GLOBAL_ATOMIC_SMIN_X2 … #define SQ_GLOBAL_ATOMIC_UMIN_X2 … #define SQ_GLOBAL_ATOMIC_SMAX_X2 … #define SQ_GLOBAL_ATOMIC_UMAX_X2 … #define SQ_GLOBAL_ATOMIC_AND_X2 … #define SQ_GLOBAL_ATOMIC_OR_X2 … #define SQ_GLOBAL_ATOMIC_XOR_X2 … #define SQ_GLOBAL_ATOMIC_INC_X2 … #define SQ_GLOBAL_ATOMIC_DEC_X2 … /* * VALUE_SQ_VGPR value */ #define SQ_VGPR0 … /* * VALUE_SQ_OP_FLAT_SCRATCH value */ #define SQ_SCRATCH_LOAD_UBYTE … #define SQ_SCRATCH_LOAD_SBYTE … #define SQ_SCRATCH_LOAD_USHORT … #define SQ_SCRATCH_LOAD_SSHORT … #define SQ_SCRATCH_LOAD_DWORD … #define SQ_SCRATCH_LOAD_DWORDX2 … #define SQ_SCRATCH_LOAD_DWORDX3 … #define SQ_SCRATCH_LOAD_DWORDX4 … #define SQ_SCRATCH_STORE_BYTE … #define SQ_SCRATCH_STORE_SHORT … #define SQ_SCRATCH_STORE_DWORD … #define SQ_SCRATCH_STORE_DWORDX2 … #define SQ_SCRATCH_STORE_DWORDX3 … #define SQ_SCRATCH_STORE_DWORDX4 … /* * VALUE_SQ_VCC value */ #define SQ_VCC_ALL … /* * VALUE_SQ_SSRC_0_63_INLINES value */ #define SQ_SRC_0 … #define SQ_SRC_1_INT … #define SQ_SRC_2_INT … #define SQ_SRC_3_INT … #define SQ_SRC_4_INT … #define SQ_SRC_5_INT … #define SQ_SRC_6_INT … #define SQ_SRC_7_INT … #define SQ_SRC_8_INT … #define SQ_SRC_9_INT … #define SQ_SRC_10_INT … #define SQ_SRC_11_INT … #define SQ_SRC_12_INT … #define SQ_SRC_13_INT … #define SQ_SRC_14_INT … #define SQ_SRC_15_INT … #define SQ_SRC_16_INT … #define SQ_SRC_17_INT … #define SQ_SRC_18_INT … #define SQ_SRC_19_INT … #define SQ_SRC_20_INT … #define SQ_SRC_21_INT … #define SQ_SRC_22_INT … #define SQ_SRC_23_INT … #define SQ_SRC_24_INT … #define SQ_SRC_25_INT … #define SQ_SRC_26_INT … #define SQ_SRC_27_INT … #define SQ_SRC_28_INT … #define SQ_SRC_29_INT … #define SQ_SRC_30_INT … #define SQ_SRC_31_INT … #define SQ_SRC_32_INT … #define SQ_SRC_33_INT … #define SQ_SRC_34_INT … #define SQ_SRC_35_INT … #define SQ_SRC_36_INT … #define SQ_SRC_37_INT … #define SQ_SRC_38_INT … #define SQ_SRC_39_INT … #define SQ_SRC_40_INT … #define SQ_SRC_41_INT … #define SQ_SRC_42_INT … #define SQ_SRC_43_INT … #define SQ_SRC_44_INT … #define SQ_SRC_45_INT … #define SQ_SRC_46_INT … #define SQ_SRC_47_INT … #define SQ_SRC_48_INT … #define SQ_SRC_49_INT … #define SQ_SRC_50_INT … #define SQ_SRC_51_INT … #define SQ_SRC_52_INT … #define SQ_SRC_53_INT … #define SQ_SRC_54_INT … #define SQ_SRC_55_INT … #define SQ_SRC_56_INT … #define SQ_SRC_57_INT … #define SQ_SRC_58_INT … #define SQ_SRC_59_INT … #define SQ_SRC_60_INT … #define SQ_SRC_61_INT … #define SQ_SRC_62_INT … #define SQ_SRC_63_INT … /* * VALUE_SQ_OP_MIMG value */ #define SQ_IMAGE_LOAD … #define SQ_IMAGE_LOAD_MIP … #define SQ_IMAGE_LOAD_PCK … #define SQ_IMAGE_LOAD_PCK_SGN … #define SQ_IMAGE_LOAD_MIP_PCK … #define SQ_IMAGE_LOAD_MIP_PCK_SGN … #define SQ_IMAGE_STORE … #define SQ_IMAGE_STORE_MIP … #define SQ_IMAGE_STORE_PCK … #define SQ_IMAGE_STORE_MIP_PCK … #define SQ_IMAGE_GET_RESINFO … #define SQ_IMAGE_ATOMIC_SWAP … #define SQ_IMAGE_ATOMIC_CMPSWAP … #define SQ_IMAGE_ATOMIC_ADD … #define SQ_IMAGE_ATOMIC_SUB … #define SQ_IMAGE_ATOMIC_SMIN … #define SQ_IMAGE_ATOMIC_UMIN … #define SQ_IMAGE_ATOMIC_SMAX … #define SQ_IMAGE_ATOMIC_UMAX … #define SQ_IMAGE_ATOMIC_AND … #define SQ_IMAGE_ATOMIC_OR … #define SQ_IMAGE_ATOMIC_XOR … #define SQ_IMAGE_ATOMIC_INC … #define SQ_IMAGE_ATOMIC_DEC … #define SQ_IMAGE_SAMPLE … #define SQ_IMAGE_SAMPLE_CL … #define SQ_IMAGE_SAMPLE_D … #define SQ_IMAGE_SAMPLE_D_CL … #define SQ_IMAGE_SAMPLE_L … #define SQ_IMAGE_SAMPLE_B … #define SQ_IMAGE_SAMPLE_B_CL … #define SQ_IMAGE_SAMPLE_LZ … #define SQ_IMAGE_SAMPLE_C … #define SQ_IMAGE_SAMPLE_C_CL … #define SQ_IMAGE_SAMPLE_C_D … #define SQ_IMAGE_SAMPLE_C_D_CL … #define SQ_IMAGE_SAMPLE_C_L … #define SQ_IMAGE_SAMPLE_C_B … #define SQ_IMAGE_SAMPLE_C_B_CL … #define SQ_IMAGE_SAMPLE_C_LZ … #define SQ_IMAGE_SAMPLE_O … #define SQ_IMAGE_SAMPLE_CL_O … #define SQ_IMAGE_SAMPLE_D_O … #define SQ_IMAGE_SAMPLE_D_CL_O … #define SQ_IMAGE_SAMPLE_L_O … #define SQ_IMAGE_SAMPLE_B_O … #define SQ_IMAGE_SAMPLE_B_CL_O … #define SQ_IMAGE_SAMPLE_LZ_O … #define SQ_IMAGE_SAMPLE_C_O … #define SQ_IMAGE_SAMPLE_C_CL_O … #define SQ_IMAGE_SAMPLE_C_D_O … #define SQ_IMAGE_SAMPLE_C_D_CL_O … #define SQ_IMAGE_SAMPLE_C_L_O … #define SQ_IMAGE_SAMPLE_C_B_O … #define SQ_IMAGE_SAMPLE_C_B_CL_O … #define SQ_IMAGE_SAMPLE_C_LZ_O … #define SQ_IMAGE_GATHER4 … #define SQ_IMAGE_GATHER4_CL … #define SQ_IMAGE_GATHER4H … #define SQ_IMAGE_GATHER4_L … #define SQ_IMAGE_GATHER4_B … #define SQ_IMAGE_GATHER4_B_CL … #define SQ_IMAGE_GATHER4_LZ … #define SQ_IMAGE_GATHER4_C … #define SQ_IMAGE_GATHER4_C_CL … #define SQ_IMAGE_GATHER4H_PCK … #define SQ_IMAGE_GATHER8H_PCK … #define SQ_IMAGE_GATHER4_C_L … #define SQ_IMAGE_GATHER4_C_B … #define SQ_IMAGE_GATHER4_C_B_CL … #define SQ_IMAGE_GATHER4_C_LZ … #define SQ_IMAGE_GATHER4_O … #define SQ_IMAGE_GATHER4_CL_O … #define SQ_IMAGE_GATHER4_L_O … #define SQ_IMAGE_GATHER4_B_O … #define SQ_IMAGE_GATHER4_B_CL_O … #define SQ_IMAGE_GATHER4_LZ_O … #define SQ_IMAGE_GATHER4_C_O … #define SQ_IMAGE_GATHER4_C_CL_O … #define SQ_IMAGE_GATHER4_C_L_O … #define SQ_IMAGE_GATHER4_C_B_O … #define SQ_IMAGE_GATHER4_C_B_CL_O … #define SQ_IMAGE_GATHER4_C_LZ_O … #define SQ_IMAGE_GET_LOD … #define SQ_IMAGE_SAMPLE_CD … #define SQ_IMAGE_SAMPLE_CD_CL … #define SQ_IMAGE_SAMPLE_C_CD … #define SQ_IMAGE_SAMPLE_C_CD_CL … #define SQ_IMAGE_SAMPLE_CD_O … #define SQ_IMAGE_SAMPLE_CD_CL_O … #define SQ_IMAGE_SAMPLE_C_CD_O … #define SQ_IMAGE_SAMPLE_C_CD_CL_O … #define SQ_IMAGE_RSRC256 … #define SQ_IMAGE_SAMPLER … /* * VALUE_SQ_HW_REG value */ #define SQ_HW_REG_MODE … #define SQ_HW_REG_STATUS … #define SQ_HW_REG_TRAPSTS … #define SQ_HW_REG_HW_ID … #define SQ_HW_REG_GPR_ALLOC … #define SQ_HW_REG_LDS_ALLOC … #define SQ_HW_REG_IB_STS … #define SQ_HW_REG_PC_LO … #define SQ_HW_REG_PC_HI … #define SQ_HW_REG_INST_DW0 … #define SQ_HW_REG_INST_DW1 … #define SQ_HW_REG_IB_DBG0 … #define SQ_HW_REG_IB_DBG1 … #define SQ_HW_REG_FLUSH_IB … #define SQ_HW_REG_SH_MEM_BASES … #define SQ_HW_REG_SQ_SHADER_TBA_LO … #define SQ_HW_REG_SQ_SHADER_TBA_HI … #define SQ_HW_REG_SQ_SHADER_TMA_LO … #define SQ_HW_REG_SQ_SHADER_TMA_HI … /* * VALUE_SQ_OP_SOP1 value */ #define SQ_S_MOV_B32 … #define SQ_S_MOV_B64 … #define SQ_S_CMOV_B32 … #define SQ_S_CMOV_B64 … #define SQ_S_NOT_B32 … #define SQ_S_NOT_B64 … #define SQ_S_WQM_B32 … #define SQ_S_WQM_B64 … #define SQ_S_BREV_B32 … #define SQ_S_BREV_B64 … #define SQ_S_BCNT0_I32_B32 … #define SQ_S_BCNT0_I32_B64 … #define SQ_S_BCNT1_I32_B32 … #define SQ_S_BCNT1_I32_B64 … #define SQ_S_FF0_I32_B32 … #define SQ_S_FF0_I32_B64 … #define SQ_S_FF1_I32_B32 … #define SQ_S_FF1_I32_B64 … #define SQ_S_FLBIT_I32_B32 … #define SQ_S_FLBIT_I32_B64 … #define SQ_S_FLBIT_I32 … #define SQ_S_FLBIT_I32_I64 … #define SQ_S_SEXT_I32_I8 … #define SQ_S_SEXT_I32_I16 … #define SQ_S_BITSET0_B32 … #define SQ_S_BITSET0_B64 … #define SQ_S_BITSET1_B32 … #define SQ_S_BITSET1_B64 … #define SQ_S_GETPC_B64 … #define SQ_S_SETPC_B64 … #define SQ_S_SWAPPC_B64 … #define SQ_S_RFE_B64 … #define SQ_S_AND_SAVEEXEC_B64 … #define SQ_S_OR_SAVEEXEC_B64 … #define SQ_S_XOR_SAVEEXEC_B64 … #define SQ_S_ANDN2_SAVEEXEC_B64 … #define SQ_S_ORN2_SAVEEXEC_B64 … #define SQ_S_NAND_SAVEEXEC_B64 … #define SQ_S_NOR_SAVEEXEC_B64 … #define SQ_S_XNOR_SAVEEXEC_B64 … #define SQ_S_QUADMASK_B32 … #define SQ_S_QUADMASK_B64 … #define SQ_S_MOVRELS_B32 … #define SQ_S_MOVRELS_B64 … #define SQ_S_MOVRELD_B32 … #define SQ_S_MOVRELD_B64 … #define SQ_S_CBRANCH_JOIN … #define SQ_S_MOV_REGRD_B32 … #define SQ_S_ABS_I32 … #define SQ_S_MOV_FED_B32 … #define SQ_S_SET_GPR_IDX_IDX … #define SQ_S_ANDN1_SAVEEXEC_B64 … #define SQ_S_ORN1_SAVEEXEC_B64 … #define SQ_S_ANDN1_WREXEC_B64 … #define SQ_S_ANDN2_WREXEC_B64 … #define SQ_S_BITREPLICATE_B64_B32 … /* * VALUE_SQ_CNT value */ #define SQ_CNT1 … #define SQ_CNT2 … #define SQ_CNT3 … #define SQ_CNT4 … /* * VALUE_SQ_OP_VOP3 value */ #define SQ_V_MAD_LEGACY_F32 … #define SQ_V_MAD_F32 … #define SQ_V_MAD_I32_I24 … #define SQ_V_MAD_U32_U24 … #define SQ_V_CUBEID_F32 … #define SQ_V_CUBESC_F32 … #define SQ_V_CUBETC_F32 … #define SQ_V_CUBEMA_F32 … #define SQ_V_BFE_U32 … #define SQ_V_BFE_I32 … #define SQ_V_BFI_B32 … #define SQ_V_FMA_F32 … #define SQ_V_FMA_F64 … #define SQ_V_LERP_U8 … #define SQ_V_ALIGNBIT_B32 … #define SQ_V_ALIGNBYTE_B32 … #define SQ_V_MIN3_F32 … #define SQ_V_MIN3_I32 … #define SQ_V_MIN3_U32 … #define SQ_V_MAX3_F32 … #define SQ_V_MAX3_I32 … #define SQ_V_MAX3_U32 … #define SQ_V_MED3_F32 … #define SQ_V_MED3_I32 … #define SQ_V_MED3_U32 … #define SQ_V_SAD_U8 … #define SQ_V_SAD_HI_U8 … #define SQ_V_SAD_U16 … #define SQ_V_SAD_U32 … #define SQ_V_CVT_PK_U8_F32 … #define SQ_V_DIV_FIXUP_F32 … #define SQ_V_DIV_FIXUP_F64 … #define SQ_V_DIV_SCALE_F32 … #define SQ_V_DIV_SCALE_F64 … #define SQ_V_DIV_FMAS_F32 … #define SQ_V_DIV_FMAS_F64 … #define SQ_V_MSAD_U8 … #define SQ_V_QSAD_PK_U16_U8 … #define SQ_V_MQSAD_PK_U16_U8 … #define SQ_V_MQSAD_U32_U8 … #define SQ_V_MAD_U64_U32 … #define SQ_V_MAD_I64_I32 … #define SQ_V_MAD_LEGACY_F16 … #define SQ_V_MAD_LEGACY_U16 … #define SQ_V_MAD_LEGACY_I16 … #define SQ_V_PERM_B32 … #define SQ_V_FMA_LEGACY_F16 … #define SQ_V_DIV_FIXUP_LEGACY_F16 … #define SQ_V_CVT_PKACCUM_U8_F32 … #define SQ_V_MAD_U32_U16 … #define SQ_V_MAD_I32_I16 … #define SQ_V_XAD_U32 … #define SQ_V_MIN3_F16 … #define SQ_V_MIN3_I16 … #define SQ_V_MIN3_U16 … #define SQ_V_MAX3_F16 … #define SQ_V_MAX3_I16 … #define SQ_V_MAX3_U16 … #define SQ_V_MED3_F16 … #define SQ_V_MED3_I16 … #define SQ_V_MED3_U16 … #define SQ_V_LSHL_ADD_U32 … #define SQ_V_ADD_LSHL_U32 … #define SQ_V_ADD3_U32 … #define SQ_V_LSHL_OR_B32 … #define SQ_V_AND_OR_B32 … #define SQ_V_OR3_B32 … #define SQ_V_MAD_F16 … #define SQ_V_MAD_U16 … #define SQ_V_MAD_I16 … #define SQ_V_FMA_F16 … #define SQ_V_DIV_FIXUP_F16 … #define SQ_V_INTERP_P1LL_F16 … #define SQ_V_INTERP_P1LV_F16 … #define SQ_V_INTERP_P2_LEGACY_F16 … #define SQ_V_INTERP_P2_F16 … #define SQ_V_ADD_F64 … #define SQ_V_MUL_F64 … #define SQ_V_MIN_F64 … #define SQ_V_MAX_F64 … #define SQ_V_LDEXP_F64 … #define SQ_V_MUL_LO_U32 … #define SQ_V_MUL_HI_U32 … #define SQ_V_MUL_HI_I32 … #define SQ_V_LDEXP_F32 … #define SQ_V_READLANE_B32 … #define SQ_V_WRITELANE_B32 … #define SQ_V_BCNT_U32_B32 … #define SQ_V_MBCNT_LO_U32_B32 … #define SQ_V_MBCNT_HI_U32_B32 … #define SQ_V_MAC_LEGACY_F32 … #define SQ_V_LSHLREV_B64 … #define SQ_V_LSHRREV_B64 … #define SQ_V_ASHRREV_I64 … #define SQ_V_TRIG_PREOP_F64 … #define SQ_V_BFM_B32 … #define SQ_V_CVT_PKNORM_I16_F32 … #define SQ_V_CVT_PKNORM_U16_F32 … #define SQ_V_CVT_PKRTZ_F16_F32 … #define SQ_V_CVT_PK_U16_U32 … #define SQ_V_CVT_PK_I16_I32 … #define SQ_V_CVT_PKNORM_I16_F16 … #define SQ_V_CVT_PKNORM_U16_F16 … #define SQ_V_READLANE_REGRD_B32 … #define SQ_V_ADD_I32 … #define SQ_V_SUB_I32 … #define SQ_V_ADD_I16 … #define SQ_V_SUB_I16 … #define SQ_V_PACK_B32_F16 … /* * VALUE_SQ_SSRC_SPECIAL_LIT value */ #define SQ_SRC_LITERAL … /* * VALUE_SQ_DPP_CTRL value */ #define SQ_DPP_QUAD_PERM … #define SQ_DPP_ROW_SL1 … #define SQ_DPP_ROW_SL2 … #define SQ_DPP_ROW_SL3 … #define SQ_DPP_ROW_SL4 … #define SQ_DPP_ROW_SL5 … #define SQ_DPP_ROW_SL6 … #define SQ_DPP_ROW_SL7 … #define SQ_DPP_ROW_SL8 … #define SQ_DPP_ROW_SL9 … #define SQ_DPP_ROW_SL10 … #define SQ_DPP_ROW_SL11 … #define SQ_DPP_ROW_SL12 … #define SQ_DPP_ROW_SL13 … #define SQ_DPP_ROW_SL14 … #define SQ_DPP_ROW_SL15 … #define SQ_DPP_ROW_SR1 … #define SQ_DPP_ROW_SR2 … #define SQ_DPP_ROW_SR3 … #define SQ_DPP_ROW_SR4 … #define SQ_DPP_ROW_SR5 … #define SQ_DPP_ROW_SR6 … #define SQ_DPP_ROW_SR7 … #define SQ_DPP_ROW_SR8 … #define SQ_DPP_ROW_SR9 … #define SQ_DPP_ROW_SR10 … #define SQ_DPP_ROW_SR11 … #define SQ_DPP_ROW_SR12 … #define SQ_DPP_ROW_SR13 … #define SQ_DPP_ROW_SR14 … #define SQ_DPP_ROW_SR15 … #define SQ_DPP_ROW_RR1 … #define SQ_DPP_ROW_RR2 … #define SQ_DPP_ROW_RR3 … #define SQ_DPP_ROW_RR4 … #define SQ_DPP_ROW_RR5 … #define SQ_DPP_ROW_RR6 … #define SQ_DPP_ROW_RR7 … #define SQ_DPP_ROW_RR8 … #define SQ_DPP_ROW_RR9 … #define SQ_DPP_ROW_RR10 … #define SQ_DPP_ROW_RR11 … #define SQ_DPP_ROW_RR12 … #define SQ_DPP_ROW_RR13 … #define SQ_DPP_ROW_RR14 … #define SQ_DPP_ROW_RR15 … #define SQ_DPP_WF_SL1 … #define SQ_DPP_WF_RL1 … #define SQ_DPP_WF_SR1 … #define SQ_DPP_WF_RR1 … #define SQ_DPP_ROW_MIRROR … #define SQ_DPP_ROW_HALF_MIRROR … #define SQ_DPP_ROW_BCAST15 … #define SQ_DPP_ROW_BCAST31 … /* * VALUE_SQ_FLAT_SCRATCH_LOHI value */ #define SQ_FLAT_SCRATCH_LO … #define SQ_FLAT_SCRATCH_HI … /* * VALUE_SQ_OP_VOP1 value */ #define SQ_V_NOP … #define SQ_V_MOV_B32 … #define SQ_V_READFIRSTLANE_B32 … #define SQ_V_CVT_I32_F64 … #define SQ_V_CVT_F64_I32 … #define SQ_V_CVT_F32_I32 … #define SQ_V_CVT_F32_U32 … #define SQ_V_CVT_U32_F32 … #define SQ_V_CVT_I32_F32 … #define SQ_V_MOV_FED_B32 … #define SQ_V_CVT_F16_F32 … #define SQ_V_CVT_F32_F16 … #define SQ_V_CVT_RPI_I32_F32 … #define SQ_V_CVT_FLR_I32_F32 … #define SQ_V_CVT_OFF_F32_I4 … #define SQ_V_CVT_F32_F64 … #define SQ_V_CVT_F64_F32 … #define SQ_V_CVT_F32_UBYTE0 … #define SQ_V_CVT_F32_UBYTE1 … #define SQ_V_CVT_F32_UBYTE2 … #define SQ_V_CVT_F32_UBYTE3 … #define SQ_V_CVT_U32_F64 … #define SQ_V_CVT_F64_U32 … #define SQ_V_TRUNC_F64 … #define SQ_V_CEIL_F64 … #define SQ_V_RNDNE_F64 … #define SQ_V_FLOOR_F64 … #define SQ_V_FRACT_F32 … #define SQ_V_TRUNC_F32 … #define SQ_V_CEIL_F32 … #define SQ_V_RNDNE_F32 … #define SQ_V_FLOOR_F32 … #define SQ_V_EXP_F32 … #define SQ_V_LOG_F32 … #define SQ_V_RCP_F32 … #define SQ_V_RCP_IFLAG_F32 … #define SQ_V_RSQ_F32 … #define SQ_V_RCP_F64 … #define SQ_V_RSQ_F64 … #define SQ_V_SQRT_F32 … #define SQ_V_SQRT_F64 … #define SQ_V_SIN_F32 … #define SQ_V_COS_F32 … #define SQ_V_NOT_B32 … #define SQ_V_BFREV_B32 … #define SQ_V_FFBH_U32 … #define SQ_V_FFBL_B32 … #define SQ_V_FFBH_I32 … #define SQ_V_FREXP_EXP_I32_F64 … #define SQ_V_FREXP_MANT_F64 … #define SQ_V_FRACT_F64 … #define SQ_V_FREXP_EXP_I32_F32 … #define SQ_V_FREXP_MANT_F32 … #define SQ_V_CLREXCP … #define SQ_V_MOV_PRSV_B32 … #define SQ_V_CVT_F16_U16 … #define SQ_V_CVT_F16_I16 … #define SQ_V_CVT_U16_F16 … #define SQ_V_CVT_I16_F16 … #define SQ_V_RCP_F16 … #define SQ_V_SQRT_F16 … #define SQ_V_RSQ_F16 … #define SQ_V_LOG_F16 … #define SQ_V_EXP_F16 … #define SQ_V_FREXP_MANT_F16 … #define SQ_V_FREXP_EXP_I16_F16 … #define SQ_V_FLOOR_F16 … #define SQ_V_CEIL_F16 … #define SQ_V_TRUNC_F16 … #define SQ_V_RNDNE_F16 … #define SQ_V_FRACT_F16 … #define SQ_V_SIN_F16 … #define SQ_V_COS_F16 … #define SQ_V_EXP_LEGACY_F32 … #define SQ_V_LOG_LEGACY_F32 … #define SQ_V_CVT_NORM_I16_F16 … #define SQ_V_CVT_NORM_U16_F16 … #define SQ_V_SAT_PK_U8_I16 … #define SQ_V_WRITELANE_IMM32 … #define SQ_V_SWAP_B32 … /* * VALUE_SQ_OP_FLAT value */ #define SQ_FLAT_LOAD_UBYTE … #define SQ_FLAT_LOAD_SBYTE … #define SQ_FLAT_LOAD_USHORT … #define SQ_FLAT_LOAD_SSHORT … #define SQ_FLAT_LOAD_DWORD … #define SQ_FLAT_LOAD_DWORDX2 … #define SQ_FLAT_LOAD_DWORDX3 … #define SQ_FLAT_LOAD_DWORDX4 … #define SQ_FLAT_STORE_BYTE … #define SQ_FLAT_STORE_SHORT … #define SQ_FLAT_STORE_DWORD … #define SQ_FLAT_STORE_DWORDX2 … #define SQ_FLAT_STORE_DWORDX3 … #define SQ_FLAT_STORE_DWORDX4 … #define SQ_FLAT_ATOMIC_SWAP … #define SQ_FLAT_ATOMIC_CMPSWAP … #define SQ_FLAT_ATOMIC_ADD … #define SQ_FLAT_ATOMIC_SUB … #define SQ_FLAT_ATOMIC_SMIN … #define SQ_FLAT_ATOMIC_UMIN … #define SQ_FLAT_ATOMIC_SMAX … #define SQ_FLAT_ATOMIC_UMAX … #define SQ_FLAT_ATOMIC_AND … #define SQ_FLAT_ATOMIC_OR … #define SQ_FLAT_ATOMIC_XOR … #define SQ_FLAT_ATOMIC_INC … #define SQ_FLAT_ATOMIC_DEC … #define SQ_FLAT_ATOMIC_SWAP_X2 … #define SQ_FLAT_ATOMIC_CMPSWAP_X2 … #define SQ_FLAT_ATOMIC_ADD_X2 … #define SQ_FLAT_ATOMIC_SUB_X2 … #define SQ_FLAT_ATOMIC_SMIN_X2 … #define SQ_FLAT_ATOMIC_UMIN_X2 … #define SQ_FLAT_ATOMIC_SMAX_X2 … #define SQ_FLAT_ATOMIC_UMAX_X2 … #define SQ_FLAT_ATOMIC_AND_X2 … #define SQ_FLAT_ATOMIC_OR_X2 … #define SQ_FLAT_ATOMIC_XOR_X2 … #define SQ_FLAT_ATOMIC_INC_X2 … #define SQ_FLAT_ATOMIC_DEC_X2 … /* * VALUE_SQ_OP_DS value */ #define SQ_DS_ADD_U32 … #define SQ_DS_SUB_U32 … #define SQ_DS_RSUB_U32 … #define SQ_DS_INC_U32 … #define SQ_DS_DEC_U32 … #define SQ_DS_MIN_I32 … #define SQ_DS_MAX_I32 … #define SQ_DS_MIN_U32 … #define SQ_DS_MAX_U32 … #define SQ_DS_AND_B32 … #define SQ_DS_OR_B32 … #define SQ_DS_XOR_B32 … #define SQ_DS_MSKOR_B32 … #define SQ_DS_WRITE_B32 … #define SQ_DS_WRITE2_B32 … #define SQ_DS_WRITE2ST64_B32 … #define SQ_DS_CMPST_B32 … #define SQ_DS_CMPST_F32 … #define SQ_DS_MIN_F32 … #define SQ_DS_MAX_F32 … #define SQ_DS_NOP … #define SQ_DS_ADD_F32 … #define SQ_DS_WRITE_ADDTID_B32 … #define SQ_DS_WRITE_B8 … #define SQ_DS_WRITE_B16 … #define SQ_DS_ADD_RTN_U32 … #define SQ_DS_SUB_RTN_U32 … #define SQ_DS_RSUB_RTN_U32 … #define SQ_DS_INC_RTN_U32 … #define SQ_DS_DEC_RTN_U32 … #define SQ_DS_MIN_RTN_I32 … #define SQ_DS_MAX_RTN_I32 … #define SQ_DS_MIN_RTN_U32 … #define SQ_DS_MAX_RTN_U32 … #define SQ_DS_AND_RTN_B32 … #define SQ_DS_OR_RTN_B32 … #define SQ_DS_XOR_RTN_B32 … #define SQ_DS_MSKOR_RTN_B32 … #define SQ_DS_WRXCHG_RTN_B32 … #define SQ_DS_WRXCHG2_RTN_B32 … #define SQ_DS_WRXCHG2ST64_RTN_B32 … #define SQ_DS_CMPST_RTN_B32 … #define SQ_DS_CMPST_RTN_F32 … #define SQ_DS_MIN_RTN_F32 … #define SQ_DS_MAX_RTN_F32 … #define SQ_DS_WRAP_RTN_B32 … #define SQ_DS_ADD_RTN_F32 … #define SQ_DS_READ_B32 … #define SQ_DS_READ2_B32 … #define SQ_DS_READ2ST64_B32 … #define SQ_DS_READ_I8 … #define SQ_DS_READ_U8 … #define SQ_DS_READ_I16 … #define SQ_DS_READ_U16 … #define SQ_DS_SWIZZLE_B32 … #define SQ_DS_PERMUTE_B32 … #define SQ_DS_BPERMUTE_B32 … #define SQ_DS_ADD_U64 … #define SQ_DS_SUB_U64 … #define SQ_DS_RSUB_U64 … #define SQ_DS_INC_U64 … #define SQ_DS_DEC_U64 … #define SQ_DS_MIN_I64 … #define SQ_DS_MAX_I64 … #define SQ_DS_MIN_U64 … #define SQ_DS_MAX_U64 … #define SQ_DS_AND_B64 … #define SQ_DS_OR_B64 … #define SQ_DS_XOR_B64 … #define SQ_DS_MSKOR_B64 … #define SQ_DS_WRITE_B64 … #define SQ_DS_WRITE2_B64 … #define SQ_DS_WRITE2ST64_B64 … #define SQ_DS_CMPST_B64 … #define SQ_DS_CMPST_F64 … #define SQ_DS_MIN_F64 … #define SQ_DS_MAX_F64 … #define SQ_DS_ADD_RTN_U64 … #define SQ_DS_SUB_RTN_U64 … #define SQ_DS_RSUB_RTN_U64 … #define SQ_DS_INC_RTN_U64 … #define SQ_DS_DEC_RTN_U64 … #define SQ_DS_MIN_RTN_I64 … #define SQ_DS_MAX_RTN_I64 … #define SQ_DS_MIN_RTN_U64 … #define SQ_DS_MAX_RTN_U64 … #define SQ_DS_AND_RTN_B64 … #define SQ_DS_OR_RTN_B64 … #define SQ_DS_XOR_RTN_B64 … #define SQ_DS_MSKOR_RTN_B64 … #define SQ_DS_WRXCHG_RTN_B64 … #define SQ_DS_WRXCHG2_RTN_B64 … #define SQ_DS_WRXCHG2ST64_RTN_B64 … #define SQ_DS_CMPST_RTN_B64 … #define SQ_DS_CMPST_RTN_F64 … #define SQ_DS_MIN_RTN_F64 … #define SQ_DS_MAX_RTN_F64 … #define SQ_DS_READ_B64 … #define SQ_DS_READ2_B64 … #define SQ_DS_READ2ST64_B64 … #define SQ_DS_CONDXCHG32_RTN_B64 … #define SQ_DS_ADD_SRC2_U32 … #define SQ_DS_SUB_SRC2_U32 … #define SQ_DS_RSUB_SRC2_U32 … #define SQ_DS_INC_SRC2_U32 … #define SQ_DS_DEC_SRC2_U32 … #define SQ_DS_MIN_SRC2_I32 … #define SQ_DS_MAX_SRC2_I32 … #define SQ_DS_MIN_SRC2_U32 … #define SQ_DS_MAX_SRC2_U32 … #define SQ_DS_AND_SRC2_B32 … #define SQ_DS_OR_SRC2_B32 … #define SQ_DS_XOR_SRC2_B32 … #define SQ_DS_WRITE_SRC2_B32 … #define SQ_DS_MIN_SRC2_F32 … #define SQ_DS_MAX_SRC2_F32 … #define SQ_DS_ADD_SRC2_F32 … #define SQ_DS_GWS_SEMA_RELEASE_ALL … #define SQ_DS_GWS_INIT … #define SQ_DS_GWS_SEMA_V … #define SQ_DS_GWS_SEMA_BR … #define SQ_DS_GWS_SEMA_P … #define SQ_DS_GWS_BARRIER … #define SQ_DS_READ_ADDTID_B32 … #define SQ_DS_CONSUME … #define SQ_DS_APPEND … #define SQ_DS_ORDERED_COUNT … #define SQ_DS_ADD_SRC2_U64 … #define SQ_DS_SUB_SRC2_U64 … #define SQ_DS_RSUB_SRC2_U64 … #define SQ_DS_INC_SRC2_U64 … #define SQ_DS_DEC_SRC2_U64 … #define SQ_DS_MIN_SRC2_I64 … #define SQ_DS_MAX_SRC2_I64 … #define SQ_DS_MIN_SRC2_U64 … #define SQ_DS_MAX_SRC2_U64 … #define SQ_DS_AND_SRC2_B64 … #define SQ_DS_OR_SRC2_B64 … #define SQ_DS_XOR_SRC2_B64 … #define SQ_DS_WRITE_SRC2_B64 … #define SQ_DS_MIN_SRC2_F64 … #define SQ_DS_MAX_SRC2_F64 … #define SQ_DS_WRITE_B96 … #define SQ_DS_WRITE_B128 … #define SQ_DS_CONDXCHG32_RTN_B128 … #define SQ_DS_READ_B96 … #define SQ_DS_READ_B128 … /* * VALUE_SQ_OP_SMEM value */ #define SQ_S_LOAD_DWORD … #define SQ_S_LOAD_DWORDX2 … #define SQ_S_LOAD_DWORDX4 … #define SQ_S_LOAD_DWORDX8 … #define SQ_S_LOAD_DWORDX16 … #define SQ_S_SCRATCH_LOAD_DWORD … #define SQ_S_SCRATCH_LOAD_DWORDX2 … #define SQ_S_SCRATCH_LOAD_DWORDX4 … #define SQ_S_BUFFER_LOAD_DWORD … #define SQ_S_BUFFER_LOAD_DWORDX2 … #define SQ_S_BUFFER_LOAD_DWORDX4 … #define SQ_S_BUFFER_LOAD_DWORDX8 … #define SQ_S_BUFFER_LOAD_DWORDX16 … #define SQ_S_STORE_DWORD … #define SQ_S_STORE_DWORDX2 … #define SQ_S_STORE_DWORDX4 … #define SQ_S_SCRATCH_STORE_DWORD … #define SQ_S_SCRATCH_STORE_DWORDX2 … #define SQ_S_SCRATCH_STORE_DWORDX4 … #define SQ_S_BUFFER_STORE_DWORD … #define SQ_S_BUFFER_STORE_DWORDX2 … #define SQ_S_BUFFER_STORE_DWORDX4 … #define SQ_S_DCACHE_INV … #define SQ_S_DCACHE_WB … #define SQ_S_DCACHE_INV_VOL … #define SQ_S_DCACHE_WB_VOL … #define SQ_S_MEMTIME … #define SQ_S_MEMREALTIME … #define SQ_S_ATC_PROBE … #define SQ_S_ATC_PROBE_BUFFER … #define SQ_S_BUFFER_ATOMIC_SWAP … #define SQ_S_BUFFER_ATOMIC_CMPSWAP … #define SQ_S_BUFFER_ATOMIC_ADD … #define SQ_S_BUFFER_ATOMIC_SUB … #define SQ_S_BUFFER_ATOMIC_SMIN … #define SQ_S_BUFFER_ATOMIC_UMIN … #define SQ_S_BUFFER_ATOMIC_SMAX … #define SQ_S_BUFFER_ATOMIC_UMAX … #define SQ_S_BUFFER_ATOMIC_AND … #define SQ_S_BUFFER_ATOMIC_OR … #define SQ_S_BUFFER_ATOMIC_XOR … #define SQ_S_BUFFER_ATOMIC_INC … #define SQ_S_BUFFER_ATOMIC_DEC … #define SQ_S_BUFFER_ATOMIC_SWAP_X2 … #define SQ_S_BUFFER_ATOMIC_CMPSWAP_X2 … #define SQ_S_BUFFER_ATOMIC_ADD_X2 … #define SQ_S_BUFFER_ATOMIC_SUB_X2 … #define SQ_S_BUFFER_ATOMIC_SMIN_X2 … #define SQ_S_BUFFER_ATOMIC_UMIN_X2 … #define SQ_S_BUFFER_ATOMIC_SMAX_X2 … #define SQ_S_BUFFER_ATOMIC_UMAX_X2 … #define SQ_S_BUFFER_ATOMIC_AND_X2 … #define SQ_S_BUFFER_ATOMIC_OR_X2 … #define SQ_S_BUFFER_ATOMIC_XOR_X2 … #define SQ_S_BUFFER_ATOMIC_INC_X2 … #define SQ_S_BUFFER_ATOMIC_DEC_X2 … #define SQ_S_ATOMIC_SWAP … #define SQ_S_ATOMIC_CMPSWAP … #define SQ_S_ATOMIC_ADD … #define SQ_S_ATOMIC_SUB … #define SQ_S_ATOMIC_SMIN … #define SQ_S_ATOMIC_UMIN … #define SQ_S_ATOMIC_SMAX … #define SQ_S_ATOMIC_UMAX … #define SQ_S_ATOMIC_AND … #define SQ_S_ATOMIC_OR … #define SQ_S_ATOMIC_XOR … #define SQ_S_ATOMIC_INC … #define SQ_S_ATOMIC_DEC … #define SQ_S_ATOMIC_SWAP_X2 … #define SQ_S_ATOMIC_CMPSWAP_X2 … #define SQ_S_ATOMIC_ADD_X2 … #define SQ_S_ATOMIC_SUB_X2 … #define SQ_S_ATOMIC_SMIN_X2 … #define SQ_S_ATOMIC_UMIN_X2 … #define SQ_S_ATOMIC_SMAX_X2 … #define SQ_S_ATOMIC_UMAX_X2 … #define SQ_S_ATOMIC_AND_X2 … #define SQ_S_ATOMIC_OR_X2 … #define SQ_S_ATOMIC_XOR_X2 … #define SQ_S_ATOMIC_INC_X2 … #define SQ_S_ATOMIC_DEC_X2 … /* * VALUE_SQ_OP_VOP2 value */ #define SQ_V_CNDMASK_B32 … #define SQ_V_ADD_F32 … #define SQ_V_SUB_F32 … #define SQ_V_SUBREV_F32 … #define SQ_V_MUL_LEGACY_F32 … #define SQ_V_MUL_F32 … #define SQ_V_MUL_I32_I24 … #define SQ_V_MUL_HI_I32_I24 … #define SQ_V_MUL_U32_U24 … #define SQ_V_MUL_HI_U32_U24 … #define SQ_V_MIN_F32 … #define SQ_V_MAX_F32 … #define SQ_V_MIN_I32 … #define SQ_V_MAX_I32 … #define SQ_V_MIN_U32 … #define SQ_V_MAX_U32 … #define SQ_V_LSHRREV_B32 … #define SQ_V_ASHRREV_I32 … #define SQ_V_LSHLREV_B32 … #define SQ_V_AND_B32 … #define SQ_V_OR_B32 … #define SQ_V_XOR_B32 … #define SQ_V_MAC_F32 … #define SQ_V_MADMK_F32 … #define SQ_V_MADAK_F32 … #define SQ_V_ADD_CO_U32 … #define SQ_V_SUB_CO_U32 … #define SQ_V_SUBREV_CO_U32 … #define SQ_V_ADDC_CO_U32 … #define SQ_V_SUBB_CO_U32 … #define SQ_V_SUBBREV_CO_U32 … #define SQ_V_ADD_F16 … #define SQ_V_SUB_F16 … #define SQ_V_SUBREV_F16 … #define SQ_V_MUL_F16 … #define SQ_V_MAC_F16 … #define SQ_V_MADMK_F16 … #define SQ_V_MADAK_F16 … #define SQ_V_ADD_U16 … #define SQ_V_SUB_U16 … #define SQ_V_SUBREV_U16 … #define SQ_V_MUL_LO_U16 … #define SQ_V_LSHLREV_B16 … #define SQ_V_LSHRREV_B16 … #define SQ_V_ASHRREV_I16 … #define SQ_V_MAX_F16 … #define SQ_V_MIN_F16 … #define SQ_V_MAX_U16 … #define SQ_V_MAX_I16 … #define SQ_V_MIN_U16 … #define SQ_V_MIN_I16 … #define SQ_V_LDEXP_F16 … #define SQ_V_ADD_U32 … #define SQ_V_SUB_U32 … #define SQ_V_SUBREV_U32 … /* * VALUE_SQ_SYSMSG_OP value */ #define SQ_SYSMSG_OP_ECC_ERR_INTERRUPT … #define SQ_SYSMSG_OP_REG_RD … #define SQ_SYSMSG_OP_HOST_TRAP_ACK … #define SQ_SYSMSG_OP_TTRACE_PC … #define SQ_SYSMSG_OP_ILLEGAL_INST_INTERRUPT … #define SQ_SYSMSG_OP_MEMVIOL_INTERRUPT … /* * VALUE_SQ_SSRC_SPECIAL_VCCZ value */ #define SQ_SRC_VCCZ … /* * VALUE_SQ_CHAN value */ #define SQ_CHAN_X … #define SQ_CHAN_Y … #define SQ_CHAN_Z … #define SQ_CHAN_W … /* * VALUE_SQ_OP_SOPK value */ #define SQ_S_MOVK_I32 … #define SQ_S_CMOVK_I32 … #define SQ_S_CMPK_EQ_I32 … #define SQ_S_CMPK_LG_I32 … #define SQ_S_CMPK_GT_I32 … #define SQ_S_CMPK_GE_I32 … #define SQ_S_CMPK_LT_I32 … #define SQ_S_CMPK_LE_I32 … #define SQ_S_CMPK_EQ_U32 … #define SQ_S_CMPK_LG_U32 … #define SQ_S_CMPK_GT_U32 … #define SQ_S_CMPK_GE_U32 … #define SQ_S_CMPK_LT_U32 … #define SQ_S_CMPK_LE_U32 … #define SQ_S_ADDK_I32 … #define SQ_S_MULK_I32 … #define SQ_S_CBRANCH_I_FORK … #define SQ_S_GETREG_B32 … #define SQ_S_SETREG_B32 … #define SQ_S_GETREG_REGRD_B32 … #define SQ_S_SETREG_IMM32_B32 … #define SQ_S_CALL_B64 … /* * VALUE_SQ_DPP_CTRL_L_1_15 value */ #define SQ_L1 … #define SQ_L2 … #define SQ_L3 … #define SQ_L4 … #define SQ_L5 … #define SQ_L6 … #define SQ_L7 … #define SQ_L8 … #define SQ_L9 … #define SQ_L10 … #define SQ_L11 … #define SQ_L12 … #define SQ_L13 … #define SQ_L14 … #define SQ_L15 … /* * VALUE_SQ_SGPR value */ #define SQ_SGPR0 … /* * VALUE_SQ_OP_VOP3P value */ #define SQ_V_PK_MAD_I16 … #define SQ_V_PK_MUL_LO_U16 … #define SQ_V_PK_ADD_I16 … #define SQ_V_PK_SUB_I16 … #define SQ_V_PK_LSHLREV_B16 … #define SQ_V_PK_LSHRREV_B16 … #define SQ_V_PK_ASHRREV_I16 … #define SQ_V_PK_MAX_I16 … #define SQ_V_PK_MIN_I16 … #define SQ_V_PK_MAD_U16 … #define SQ_V_PK_ADD_U16 … #define SQ_V_PK_SUB_U16 … #define SQ_V_PK_MAX_U16 … #define SQ_V_PK_MIN_U16 … #define SQ_V_PK_MAD_F16 … #define SQ_V_PK_ADD_F16 … #define SQ_V_PK_MUL_F16 … #define SQ_V_PK_MIN_F16 … #define SQ_V_PK_MAX_F16 … #define SQ_V_MAD_MIX_F32 … #define SQ_V_MAD_MIXLO_F16 … #define SQ_V_MAD_MIXHI_F16 … /* * VALUE_SQ_OP_VINTRP value */ #define SQ_V_INTERP_P1_F32 … #define SQ_V_INTERP_P2_F32 … #define SQ_V_INTERP_MOV_F32 … /* * VALUE_SQ_DPP_CTRL_R_1_15 value */ #define SQ_R1 … #define SQ_R2 … #define SQ_R3 … #define SQ_R4 … #define SQ_R5 … #define SQ_R6 … #define SQ_R7 … #define SQ_R8 … #define SQ_R9 … #define SQ_R10 … #define SQ_R11 … #define SQ_R12 … #define SQ_R13 … #define SQ_R14 … #define SQ_R15 … /* * VALUE_SQ_OP_SOP2 value */ #define SQ_S_ADD_U32 … #define SQ_S_SUB_U32 … #define SQ_S_ADD_I32 … #define SQ_S_SUB_I32 … #define SQ_S_ADDC_U32 … #define SQ_S_SUBB_U32 … #define SQ_S_MIN_I32 … #define SQ_S_MIN_U32 … #define SQ_S_MAX_I32 … #define SQ_S_MAX_U32 … #define SQ_S_CSELECT_B32 … #define SQ_S_CSELECT_B64 … #define SQ_S_AND_B32 … #define SQ_S_AND_B64 … #define SQ_S_OR_B32 … #define SQ_S_OR_B64 … #define SQ_S_XOR_B32 … #define SQ_S_XOR_B64 … #define SQ_S_ANDN2_B32 … #define SQ_S_ANDN2_B64 … #define SQ_S_ORN2_B32 … #define SQ_S_ORN2_B64 … #define SQ_S_NAND_B32 … #define SQ_S_NAND_B64 … #define SQ_S_NOR_B32 … #define SQ_S_NOR_B64 … #define SQ_S_XNOR_B32 … #define SQ_S_XNOR_B64 … #define SQ_S_LSHL_B32 … #define SQ_S_LSHL_B64 … #define SQ_S_LSHR_B32 … #define SQ_S_LSHR_B64 … #define SQ_S_ASHR_I32 … #define SQ_S_ASHR_I64 … #define SQ_S_BFM_B32 … #define SQ_S_BFM_B64 … #define SQ_S_MUL_I32 … #define SQ_S_BFE_U32 … #define SQ_S_BFE_I32 … #define SQ_S_BFE_U64 … #define SQ_S_BFE_I64 … #define SQ_S_CBRANCH_G_FORK … #define SQ_S_ABSDIFF_I32 … #define SQ_S_RFE_RESTORE_B64 … #define SQ_S_MUL_HI_U32 … #define SQ_S_MUL_HI_I32 … #define SQ_S_LSHL1_ADD_U32 … #define SQ_S_LSHL2_ADD_U32 … #define SQ_S_LSHL3_ADD_U32 … #define SQ_S_LSHL4_ADD_U32 … #define SQ_S_PACK_LL_B32_B16 … #define SQ_S_PACK_LH_B32_B16 … #define SQ_S_PACK_HH_B32_B16 … /* * VALUE_SQ_SEG value */ #define SQ_FLAT … #define SQ_SCRATCH … #define SQ_GLOBAL … /* * VALUE_SQ_SDST_EXEC value */ #define SQ_EXEC_LO … #define SQ_EXEC_HI … /* * VALUE_SQ_SSRC_SPECIAL_NOLIT value */ #define SQ_SRC_64_INT … #define SQ_SRC_M_1_INT … #define SQ_SRC_M_2_INT … #define SQ_SRC_M_3_INT … #define SQ_SRC_M_4_INT … #define SQ_SRC_M_5_INT … #define SQ_SRC_M_6_INT … #define SQ_SRC_M_7_INT … #define SQ_SRC_M_8_INT … #define SQ_SRC_M_9_INT … #define SQ_SRC_M_10_INT … #define SQ_SRC_M_11_INT … #define SQ_SRC_M_12_INT … #define SQ_SRC_M_13_INT … #define SQ_SRC_M_14_INT … #define SQ_SRC_M_15_INT … #define SQ_SRC_M_16_INT … #define SQ_SRC_0_5 … #define SQ_SRC_M_0_5 … #define SQ_SRC_1 … #define SQ_SRC_M_1 … #define SQ_SRC_2 … #define SQ_SRC_M_2 … #define SQ_SRC_4 … #define SQ_SRC_M_4 … #define SQ_SRC_INV_2PI … /* * VALUE_SQ_VCC_LOHI value */ #define SQ_VCC_LO … #define SQ_VCC_HI … /* * VALUE_SQ_TGT value */ #define SQ_EXP_MRT0 … #define SQ_EXP_MRTZ … #define SQ_EXP_NULL … #define SQ_EXP_POS0 … #define SQ_EXP_PARAM0 … /* * VALUE_SQ_OP_SOPP value */ #define SQ_S_NOP … #define SQ_S_ENDPGM … #define SQ_S_BRANCH … #define SQ_S_WAKEUP … #define SQ_S_CBRANCH_SCC0 … #define SQ_S_CBRANCH_SCC1 … #define SQ_S_CBRANCH_VCCZ … #define SQ_S_CBRANCH_VCCNZ … #define SQ_S_CBRANCH_EXECZ … #define SQ_S_CBRANCH_EXECNZ … #define SQ_S_BARRIER … #define SQ_S_SETKILL … #define SQ_S_WAITCNT … #define SQ_S_SETHALT … #define SQ_S_SLEEP … #define SQ_S_SETPRIO … #define SQ_S_SENDMSG … #define SQ_S_SENDMSGHALT … #define SQ_S_TRAP … #define SQ_S_ICACHE_INV … #define SQ_S_INCPERFLEVEL … #define SQ_S_DECPERFLEVEL … #define SQ_S_TTRACEDATA … #define SQ_S_CBRANCH_CDBGSYS … #define SQ_S_CBRANCH_CDBGUSER … #define SQ_S_CBRANCH_CDBGSYS_OR_USER … #define SQ_S_CBRANCH_CDBGSYS_AND_USER … #define SQ_S_ENDPGM_SAVED … #define SQ_S_SET_GPR_IDX_OFF … #define SQ_S_SET_GPR_IDX_MODE … #define SQ_S_ENDPGM_ORDERED_PS_DONE … /* * VALUE_SQ_OP_EXP value */ #define SQ_EXP … /* * VALUE_SQ_SSRC_SPECIAL_POPS_EXITING_WAVE_ID value */ #define SQ_SRC_POPS_EXITING_WAVE_ID … /* * VALUE_SQ_XNACK_MASK_LOHI value */ #define SQ_XNACK_MASK_LO … #define SQ_XNACK_MASK_HI … /* * VALUE_SQ_OMOD value */ #define SQ_OMOD_OFF … #define SQ_OMOD_M2 … #define SQ_OMOD_M4 … #define SQ_OMOD_D2 … /* * VALUE_SQ_SSRC_SPECIAL_EXECZ value */ #define SQ_SRC_EXECZ … /* * VALUE_SQ_COMPI value */ #define SQ_F … #define SQ_LT … #define SQ_EQ … #define SQ_LE … #define SQ_GT … #define SQ_NE … #define SQ_GE … #define SQ_T … /* * VALUE_SQ_DPP_BOUND_CTRL value */ #define SQ_DPP_BOUND_OFF … #define SQ_DPP_BOUND_ZERO … /* * VALUE_SQ_SDST_M0 value */ #define SQ_M0 … /* * VALUE_SQ_MSG value */ #define SQ_MSG_INTERRUPT … #define SQ_MSG_GS … #define SQ_MSG_GS_DONE … #define SQ_MSG_SAVEWAVE … #define SQ_MSG_STALL_WAVE_GEN … #define SQ_MSG_HALT_WAVES … #define SQ_MSG_ORDERED_PS_DONE … #define SQ_MSG_EARLY_PRIM_DEALLOC … #define SQ_MSG_GS_ALLOC_REQ … #define SQ_MSG_SYSMSG … /* * VALUE_SQ_PARAM value */ #define SQ_PARAM_P10 … #define SQ_PARAM_P20 … #define SQ_PARAM_P0 … /* * VALUE_SQ_OPU_VOP3 value */ #define SQ_V_OPC_OFFSET … #define SQ_V_OP2_OFFSET … #define SQ_V_OP1_OFFSET … #define SQ_V_INTRP_OFFSET … #define SQ_V_OP3P_OFFSET … /* * VALUE_SQ_SSRC_SPECIAL_SDWA value */ #define SQ_SRC_SDWA … /* * VALUE_SQ_SSRC_SPECIAL_APERTURE value */ #define SQ_SRC_SHARED_BASE … #define SQ_SRC_SHARED_LIMIT … #define SQ_SRC_PRIVATE_BASE … #define SQ_SRC_PRIVATE_LIMIT … /* * VALUE_SQ_COMPF value */ #define SQ_F … #define SQ_LT … #define SQ_EQ … #define SQ_LE … #define SQ_GT … #define SQ_LG … #define SQ_GE … #define SQ_O … #define SQ_U … #define SQ_NGE … #define SQ_NLG … #define SQ_NGT … #define SQ_NLE … #define SQ_NEQ … #define SQ_NLT … #define SQ_TRU … /* * VALUE_SQ_SDWA_UNUSED value */ #define SQ_SDWA_UNUSED_PAD … #define SQ_SDWA_UNUSED_SEXT … #define SQ_SDWA_UNUSED_PRESERVE … /* * VALUE_SQ_SSRC_SPECIAL_SCC value */ #define SQ_SRC_SCC … /* * VALUE_SQ_OP_VOPC value */ #define SQ_V_CMP_CLASS_F32 … #define SQ_V_CMPX_CLASS_F32 … #define SQ_V_CMP_CLASS_F64 … #define SQ_V_CMPX_CLASS_F64 … #define SQ_V_CMP_CLASS_F16 … #define SQ_V_CMPX_CLASS_F16 … #define SQ_V_CMP_F_F16 … #define SQ_V_CMP_LT_F16 … #define SQ_V_CMP_EQ_F16 … #define SQ_V_CMP_LE_F16 … #define SQ_V_CMP_GT_F16 … #define SQ_V_CMP_LG_F16 … #define SQ_V_CMP_GE_F16 … #define SQ_V_CMP_O_F16 … #define SQ_V_CMP_U_F16 … #define SQ_V_CMP_NGE_F16 … #define SQ_V_CMP_NLG_F16 … #define SQ_V_CMP_NGT_F16 … #define SQ_V_CMP_NLE_F16 … #define SQ_V_CMP_NEQ_F16 … #define SQ_V_CMP_NLT_F16 … #define SQ_V_CMP_TRU_F16 … #define SQ_V_CMPX_F_F16 … #define SQ_V_CMPX_LT_F16 … #define SQ_V_CMPX_EQ_F16 … #define SQ_V_CMPX_LE_F16 … #define SQ_V_CMPX_GT_F16 … #define SQ_V_CMPX_LG_F16 … #define SQ_V_CMPX_GE_F16 … #define SQ_V_CMPX_O_F16 … #define SQ_V_CMPX_U_F16 … #define SQ_V_CMPX_NGE_F16 … #define SQ_V_CMPX_NLG_F16 … #define SQ_V_CMPX_NGT_F16 … #define SQ_V_CMPX_NLE_F16 … #define SQ_V_CMPX_NEQ_F16 … #define SQ_V_CMPX_NLT_F16 … #define SQ_V_CMPX_TRU_F16 … #define SQ_V_CMP_F_F32 … #define SQ_V_CMP_LT_F32 … #define SQ_V_CMP_EQ_F32 … #define SQ_V_CMP_LE_F32 … #define SQ_V_CMP_GT_F32 … #define SQ_V_CMP_LG_F32 … #define SQ_V_CMP_GE_F32 … #define SQ_V_CMP_O_F32 … #define SQ_V_CMP_U_F32 … #define SQ_V_CMP_NGE_F32 … #define SQ_V_CMP_NLG_F32 … #define SQ_V_CMP_NGT_F32 … #define SQ_V_CMP_NLE_F32 … #define SQ_V_CMP_NEQ_F32 … #define SQ_V_CMP_NLT_F32 … #define SQ_V_CMP_TRU_F32 … #define SQ_V_CMPX_F_F32 … #define SQ_V_CMPX_LT_F32 … #define SQ_V_CMPX_EQ_F32 … #define SQ_V_CMPX_LE_F32 … #define SQ_V_CMPX_GT_F32 … #define SQ_V_CMPX_LG_F32 … #define SQ_V_CMPX_GE_F32 … #define SQ_V_CMPX_O_F32 … #define SQ_V_CMPX_U_F32 … #define SQ_V_CMPX_NGE_F32 … #define SQ_V_CMPX_NLG_F32 … #define SQ_V_CMPX_NGT_F32 … #define SQ_V_CMPX_NLE_F32 … #define SQ_V_CMPX_NEQ_F32 … #define SQ_V_CMPX_NLT_F32 … #define SQ_V_CMPX_TRU_F32 … #define SQ_V_CMP_F_F64 … #define SQ_V_CMP_LT_F64 … #define SQ_V_CMP_EQ_F64 … #define SQ_V_CMP_LE_F64 … #define SQ_V_CMP_GT_F64 … #define SQ_V_CMP_LG_F64 … #define SQ_V_CMP_GE_F64 … #define SQ_V_CMP_O_F64 … #define SQ_V_CMP_U_F64 … #define SQ_V_CMP_NGE_F64 … #define SQ_V_CMP_NLG_F64 … #define SQ_V_CMP_NGT_F64 … #define SQ_V_CMP_NLE_F64 … #define SQ_V_CMP_NEQ_F64 … #define SQ_V_CMP_NLT_F64 … #define SQ_V_CMP_TRU_F64 … #define SQ_V_CMPX_F_F64 … #define SQ_V_CMPX_LT_F64 … #define SQ_V_CMPX_EQ_F64 … #define SQ_V_CMPX_LE_F64 … #define SQ_V_CMPX_GT_F64 … #define SQ_V_CMPX_LG_F64 … #define SQ_V_CMPX_GE_F64 … #define SQ_V_CMPX_O_F64 … #define SQ_V_CMPX_U_F64 … #define SQ_V_CMPX_NGE_F64 … #define SQ_V_CMPX_NLG_F64 … #define SQ_V_CMPX_NGT_F64 … #define SQ_V_CMPX_NLE_F64 … #define SQ_V_CMPX_NEQ_F64 … #define SQ_V_CMPX_NLT_F64 … #define SQ_V_CMPX_TRU_F64 … #define SQ_V_CMP_F_I16 … #define SQ_V_CMP_LT_I16 … #define SQ_V_CMP_EQ_I16 … #define SQ_V_CMP_LE_I16 … #define SQ_V_CMP_GT_I16 … #define SQ_V_CMP_NE_I16 … #define SQ_V_CMP_GE_I16 … #define SQ_V_CMP_T_I16 … #define SQ_V_CMP_F_U16 … #define SQ_V_CMP_LT_U16 … #define SQ_V_CMP_EQ_U16 … #define SQ_V_CMP_LE_U16 … #define SQ_V_CMP_GT_U16 … #define SQ_V_CMP_NE_U16 … #define SQ_V_CMP_GE_U16 … #define SQ_V_CMP_T_U16 … #define SQ_V_CMPX_F_I16 … #define SQ_V_CMPX_LT_I16 … #define SQ_V_CMPX_EQ_I16 … #define SQ_V_CMPX_LE_I16 … #define SQ_V_CMPX_GT_I16 … #define SQ_V_CMPX_NE_I16 … #define SQ_V_CMPX_GE_I16 … #define SQ_V_CMPX_T_I16 … #define SQ_V_CMPX_F_U16 … #define SQ_V_CMPX_LT_U16 … #define SQ_V_CMPX_EQ_U16 … #define SQ_V_CMPX_LE_U16 … #define SQ_V_CMPX_GT_U16 … #define SQ_V_CMPX_NE_U16 … #define SQ_V_CMPX_GE_U16 … #define SQ_V_CMPX_T_U16 … #define SQ_V_CMP_F_I32 … #define SQ_V_CMP_LT_I32 … #define SQ_V_CMP_EQ_I32 … #define SQ_V_CMP_LE_I32 … #define SQ_V_CMP_GT_I32 … #define SQ_V_CMP_NE_I32 … #define SQ_V_CMP_GE_I32 … #define SQ_V_CMP_T_I32 … #define SQ_V_CMP_F_U32 … #define SQ_V_CMP_LT_U32 … #define SQ_V_CMP_EQ_U32 … #define SQ_V_CMP_LE_U32 … #define SQ_V_CMP_GT_U32 … #define SQ_V_CMP_NE_U32 … #define SQ_V_CMP_GE_U32 … #define SQ_V_CMP_T_U32 … #define SQ_V_CMPX_F_I32 … #define SQ_V_CMPX_LT_I32 … #define SQ_V_CMPX_EQ_I32 … #define SQ_V_CMPX_LE_I32 … #define SQ_V_CMPX_GT_I32 … #define SQ_V_CMPX_NE_I32 … #define SQ_V_CMPX_GE_I32 … #define SQ_V_CMPX_T_I32 … #define SQ_V_CMPX_F_U32 … #define SQ_V_CMPX_LT_U32 … #define SQ_V_CMPX_EQ_U32 … #define SQ_V_CMPX_LE_U32 … #define SQ_V_CMPX_GT_U32 … #define SQ_V_CMPX_NE_U32 … #define SQ_V_CMPX_GE_U32 … #define SQ_V_CMPX_T_U32 … #define SQ_V_CMP_F_I64 … #define SQ_V_CMP_LT_I64 … #define SQ_V_CMP_EQ_I64 … #define SQ_V_CMP_LE_I64 … #define SQ_V_CMP_GT_I64 … #define SQ_V_CMP_NE_I64 … #define SQ_V_CMP_GE_I64 … #define SQ_V_CMP_T_I64 … #define SQ_V_CMP_F_U64 … #define SQ_V_CMP_LT_U64 … #define SQ_V_CMP_EQ_U64 … #define SQ_V_CMP_LE_U64 … #define SQ_V_CMP_GT_U64 … #define SQ_V_CMP_NE_U64 … #define SQ_V_CMP_GE_U64 … #define SQ_V_CMP_T_U64 … #define SQ_V_CMPX_F_I64 … #define SQ_V_CMPX_LT_I64 … #define SQ_V_CMPX_EQ_I64 … #define SQ_V_CMPX_LE_I64 … #define SQ_V_CMPX_GT_I64 … #define SQ_V_CMPX_NE_I64 … #define SQ_V_CMPX_GE_I64 … #define SQ_V_CMPX_T_I64 … #define SQ_V_CMPX_F_U64 … #define SQ_V_CMPX_LT_U64 … #define SQ_V_CMPX_EQ_U64 … #define SQ_V_CMPX_LE_U64 … #define SQ_V_CMPX_GT_U64 … #define SQ_V_CMPX_NE_U64 … #define SQ_V_CMPX_GE_U64 … #define SQ_V_CMPX_T_U64 … /* * VALUE_SQ_GS_OP value */ #define SQ_GS_OP_NOP … #define SQ_GS_OP_CUT … #define SQ_GS_OP_EMIT … #define SQ_GS_OP_EMIT_CUT … /* * VALUE_SQ_SSRC_SPECIAL_LDS value */ #define SQ_SRC_LDS_DIRECT … /* * VALUE_SQ_ATTR value */ #define SQ_ATTR0 … /* * VALUE_SQ_TGT_INTERNAL value */ #define SQ_EXP_GDS0 … /* * VALUE_SQ_OP_SOPC value */ #define SQ_S_CMP_EQ_I32 … #define SQ_S_CMP_LG_I32 … #define SQ_S_CMP_GT_I32 … #define SQ_S_CMP_GE_I32 … #define SQ_S_CMP_LT_I32 … #define SQ_S_CMP_LE_I32 … #define SQ_S_CMP_EQ_U32 … #define SQ_S_CMP_LG_U32 … #define SQ_S_CMP_GT_U32 … #define SQ_S_CMP_GE_U32 … #define SQ_S_CMP_LT_U32 … #define SQ_S_CMP_LE_U32 … #define SQ_S_BITCMP0_B32 … #define SQ_S_BITCMP1_B32 … #define SQ_S_BITCMP0_B64 … #define SQ_S_BITCMP1_B64 … #define SQ_S_SETVSKIP … #define SQ_S_SET_GPR_IDX_ON … #define SQ_S_CMP_EQ_U64 … #define SQ_S_CMP_LG_U64 … /* * VALUE_SQ_TRAP value */ #define SQ_TTMP0 … #define SQ_TTMP1 … #define SQ_TTMP2 … #define SQ_TTMP3 … #define SQ_TTMP4 … #define SQ_TTMP5 … #define SQ_TTMP6 … #define SQ_TTMP7 … #define SQ_TTMP8 … #define SQ_TTMP9 … #define SQ_TTMP10 … #define SQ_TTMP11 … #define SQ_TTMP12 … #define SQ_TTMP13 … #define SQ_TTMP14 … #define SQ_TTMP15 … /* * VALUE_SQ_SRC_VGPR value */ #define SQ_SRC_VGPR0 … /* * VALUE_SQ_OP_MUBUF value */ #define SQ_BUFFER_LOAD_FORMAT_X … #define SQ_BUFFER_LOAD_FORMAT_XY … #define SQ_BUFFER_LOAD_FORMAT_XYZ … #define SQ_BUFFER_LOAD_FORMAT_XYZW … #define SQ_BUFFER_STORE_FORMAT_X … #define SQ_BUFFER_STORE_FORMAT_XY … #define SQ_BUFFER_STORE_FORMAT_XYZ … #define SQ_BUFFER_STORE_FORMAT_XYZW … #define SQ_BUFFER_LOAD_FORMAT_D16_X … #define SQ_BUFFER_LOAD_FORMAT_D16_XY … #define SQ_BUFFER_LOAD_FORMAT_D16_XYZ … #define SQ_BUFFER_LOAD_FORMAT_D16_XYZW … #define SQ_BUFFER_STORE_FORMAT_D16_X … #define SQ_BUFFER_STORE_FORMAT_D16_XY … #define SQ_BUFFER_STORE_FORMAT_D16_XYZ … #define SQ_BUFFER_STORE_FORMAT_D16_XYZW … #define SQ_BUFFER_LOAD_UBYTE … #define SQ_BUFFER_LOAD_SBYTE … #define SQ_BUFFER_LOAD_USHORT … #define SQ_BUFFER_LOAD_SSHORT … #define SQ_BUFFER_LOAD_DWORD … #define SQ_BUFFER_LOAD_DWORDX2 … #define SQ_BUFFER_LOAD_DWORDX3 … #define SQ_BUFFER_LOAD_DWORDX4 … #define SQ_BUFFER_STORE_BYTE … #define SQ_BUFFER_STORE_SHORT … #define SQ_BUFFER_STORE_DWORD … #define SQ_BUFFER_STORE_DWORDX2 … #define SQ_BUFFER_STORE_DWORDX3 … #define SQ_BUFFER_STORE_DWORDX4 … #define SQ_BUFFER_STORE_LDS_DWORD … #define SQ_BUFFER_WBINVL1 … #define SQ_BUFFER_WBINVL1_VOL … #define SQ_BUFFER_ATOMIC_SWAP … #define SQ_BUFFER_ATOMIC_CMPSWAP … #define SQ_BUFFER_ATOMIC_ADD … #define SQ_BUFFER_ATOMIC_SUB … #define SQ_BUFFER_ATOMIC_SMIN … #define SQ_BUFFER_ATOMIC_UMIN … #define SQ_BUFFER_ATOMIC_SMAX … #define SQ_BUFFER_ATOMIC_UMAX … #define SQ_BUFFER_ATOMIC_AND … #define SQ_BUFFER_ATOMIC_OR … #define SQ_BUFFER_ATOMIC_XOR … #define SQ_BUFFER_ATOMIC_INC … #define SQ_BUFFER_ATOMIC_DEC … #define SQ_BUFFER_ATOMIC_SWAP_X2 … #define SQ_BUFFER_ATOMIC_CMPSWAP_X2 … #define SQ_BUFFER_ATOMIC_ADD_X2 … #define SQ_BUFFER_ATOMIC_SUB_X2 … #define SQ_BUFFER_ATOMIC_SMIN_X2 … #define SQ_BUFFER_ATOMIC_UMIN_X2 … #define SQ_BUFFER_ATOMIC_SMAX_X2 … #define SQ_BUFFER_ATOMIC_UMAX_X2 … #define SQ_BUFFER_ATOMIC_AND_X2 … #define SQ_BUFFER_ATOMIC_OR_X2 … #define SQ_BUFFER_ATOMIC_XOR_X2 … #define SQ_BUFFER_ATOMIC_INC_X2 … #define SQ_BUFFER_ATOMIC_DEC_X2 … /* * VALUE_SQ_SDWA_SEL value */ #define SQ_SDWA_BYTE_0 … #define SQ_SDWA_BYTE_1 … #define SQ_SDWA_BYTE_2 … #define SQ_SDWA_BYTE_3 … #define SQ_SDWA_WORD_0 … #define SQ_SDWA_WORD_1 … #define SQ_SDWA_DWORD … /******************************************************* * SX Enums *******************************************************/ /* * SX_BLEND_OPT enum */ SX_BLEND_OPT; /* * SX_OPT_COMB_FCN enum */ SX_OPT_COMB_FCN; /* * SX_DOWNCONVERT_FORMAT enum */ SX_DOWNCONVERT_FORMAT; /* * SX_PERFCOUNTER_VALS enum */ SX_PERFCOUNTER_VALS; /******************************************************* * DB Enums *******************************************************/ /* * ForceControl enum */ ForceControl; /* * ZSamplePosition enum */ ZSamplePosition; /* * ZOrder enum */ ZOrder; /* * ZpassControl enum */ ZpassControl; /* * ZModeForce enum */ ZModeForce; /* * ZLimitSumm enum */ ZLimitSumm; /* * CompareFrag enum */ CompareFrag; /* * StencilOp enum */ StencilOp; /* * ConservativeZExport enum */ ConservativeZExport; /* * DbPSLControl enum */ DbPSLControl; /* * DbPRTFaultBehavior enum */ DbPRTFaultBehavior; /* * PerfCounter_Vals enum */ PerfCounter_Vals; /* * RingCounterControl enum */ RingCounterControl; /* * DbMemArbWatermarks enum */ DbMemArbWatermarks; /* * DFSMFlushEvents enum */ DFSMFlushEvents; /* * PixelPipeCounterId enum */ PixelPipeCounterId; /* * PixelPipeStride enum */ PixelPipeStride; /******************************************************* * TA Enums *******************************************************/ /* * TEX_BORDER_COLOR_TYPE enum */ TEX_BORDER_COLOR_TYPE; /* * TEX_CHROMA_KEY enum */ TEX_CHROMA_KEY; /* * TEX_CLAMP enum */ TEX_CLAMP; /* * TEX_COORD_TYPE enum */ TEX_COORD_TYPE; /* * TEX_DEPTH_COMPARE_FUNCTION enum */ TEX_DEPTH_COMPARE_FUNCTION; /* * TEX_DIM enum */ TEX_DIM; /* * TEX_FORMAT_COMP enum */ TEX_FORMAT_COMP; /* * TEX_MAX_ANISO_RATIO enum */ TEX_MAX_ANISO_RATIO; /* * TEX_MIP_FILTER enum */ TEX_MIP_FILTER; /* * TEX_REQUEST_SIZE enum */ TEX_REQUEST_SIZE; /* * TEX_SAMPLER_TYPE enum */ TEX_SAMPLER_TYPE; /* * TEX_XY_FILTER enum */ TEX_XY_FILTER; /* * TEX_Z_FILTER enum */ TEX_Z_FILTER; /* * VTX_CLAMP enum */ VTX_CLAMP; /* * VTX_FETCH_TYPE enum */ VTX_FETCH_TYPE; /* * VTX_FORMAT_COMP_ALL enum */ VTX_FORMAT_COMP_ALL; /* * VTX_MEM_REQUEST_SIZE enum */ VTX_MEM_REQUEST_SIZE; /* * TVX_DATA_FORMAT enum */ TVX_DATA_FORMAT; /* * TVX_DST_SEL enum */ TVX_DST_SEL; /* * TVX_ENDIAN_SWAP enum */ TVX_ENDIAN_SWAP; /* * TVX_INST enum */ TVX_INST; /* * TVX_NUM_FORMAT_ALL enum */ TVX_NUM_FORMAT_ALL; /* * TVX_SRC_SEL enum */ TVX_SRC_SEL; /* * TVX_SRF_MODE_ALL enum */ TVX_SRF_MODE_ALL; /* * TVX_TYPE enum */ TVX_TYPE; /******************************************************* * PA Enums *******************************************************/ /* * SU_PERFCNT_SEL enum */ SU_PERFCNT_SEL; /* * SC_PERFCNT_SEL enum */ SC_PERFCNT_SEL; /* * SePairXsel enum */ SePairXsel; /* * SePairYsel enum */ SePairYsel; /* * SePairMap enum */ SePairMap; /* * SeXsel enum */ SeXsel; /* * SeYsel enum */ SeYsel; /* * SeMap enum */ SeMap; /* * ScXsel enum */ ScXsel; /* * ScYsel enum */ ScYsel; /* * ScMap enum */ ScMap; /* * PkrXsel2 enum */ PkrXsel2; /* * PkrXsel enum */ PkrXsel; /* * PkrYsel enum */ PkrYsel; /* * PkrMap enum */ PkrMap; /* * RbXsel enum */ RbXsel; /* * RbYsel enum */ RbYsel; /* * RbXsel2 enum */ RbXsel2; /* * RbMap enum */ RbMap; /* * BinningMode enum */ BinningMode; /* * BinEventCntl enum */ BinEventCntl; /* * CovToShaderSel enum */ CovToShaderSel; /******************************************************* * RMI Enums *******************************************************/ /* * RMIPerfSel enum */ RMIPerfSel; /******************************************************* * IH Enums *******************************************************/ /* * IH_PERF_SEL enum */ IH_PERF_SEL; /******************************************************* * SEM Enums *******************************************************/ /* * SEM_PERF_SEL enum */ SEM_PERF_SEL; /******************************************************* * SDMA Enums *******************************************************/ /* * SDMA_PERF_SEL enum */ SDMA_PERF_SEL; /******************************************************* * SMUIO Enums *******************************************************/ /* * ROM_SIGNATURE value */ #define ROM_SIGNATURE … /******************************************************* * XDMA_CMN Enums *******************************************************/ /* * ENUM_XDMA_LOCAL_SW_MODE enum */ ENUM_XDMA_LOCAL_SW_MODE; /******************************************************* * XDMA_SLV Enums *******************************************************/ /* * ENUM_XDMA_SLV_ALPHA_POSITION enum */ ENUM_XDMA_SLV_ALPHA_POSITION; /******************************************************* * XDMA_MSTR Enums *******************************************************/ /* * ENUM_XDMA_MSTR_ALPHA_POSITION enum */ ENUM_XDMA_MSTR_ALPHA_POSITION; /* * ENUM_XDMA_MSTR_VSYNC_GSL_CHECK_SEL enum */ ENUM_XDMA_MSTR_VSYNC_GSL_CHECK_SEL; #endif /*_vega10_ENUM_HEADER*/
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