/* SPDX-License-Identifier: GPL-2.0 */ /* * This file contains definitions from Hyper-V Hypervisor Top-Level Functional * Specification (TLFS): * https://docs.microsoft.com/en-us/virtualization/hyper-v-on-windows/reference/tlfs */ #ifndef _ASM_X86_HYPERV_TLFS_H #define _ASM_X86_HYPERV_TLFS_H #include <linux/types.h> #include <asm/page.h> /* * The below CPUID leaves are present if VersionAndFeatures.HypervisorPresent * is set by CPUID(HvCpuIdFunctionVersionAndFeatures). */ #define HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS … #define HYPERV_CPUID_INTERFACE … #define HYPERV_CPUID_VERSION … #define HYPERV_CPUID_FEATURES … #define HYPERV_CPUID_ENLIGHTMENT_INFO … #define HYPERV_CPUID_IMPLEMENT_LIMITS … #define HYPERV_CPUID_CPU_MANAGEMENT_FEATURES … #define HYPERV_CPUID_NESTED_FEATURES … #define HYPERV_CPUID_ISOLATION_CONFIG … #define HYPERV_CPUID_VIRT_STACK_INTERFACE … #define HYPERV_VS_INTERFACE_EAX_SIGNATURE … #define HYPERV_CPUID_VIRT_STACK_PROPERTIES … /* Support for the extended IOAPIC RTE format */ #define HYPERV_VS_PROPERTIES_EAX_EXTENDED_IOAPIC_RTE … #define HYPERV_HYPERVISOR_PRESENT_BIT … #define HYPERV_CPUID_MIN … #define HYPERV_CPUID_MAX … /* * Group D Features. The bit assignments are custom to each architecture. * On x86/x64 these are HYPERV_CPUID_FEATURES.EDX bits. */ /* The MWAIT instruction is available (per section MONITOR / MWAIT) */ #define HV_X64_MWAIT_AVAILABLE … /* Guest debugging support is available */ #define HV_X64_GUEST_DEBUGGING_AVAILABLE … /* Performance Monitor support is available*/ #define HV_X64_PERF_MONITOR_AVAILABLE … /* Support for physical CPU dynamic partitioning events is available*/ #define HV_X64_CPU_DYNAMIC_PARTITIONING_AVAILABLE … /* * Support for passing hypercall input parameter block via XMM * registers is available */ #define HV_X64_HYPERCALL_XMM_INPUT_AVAILABLE … /* Support for a virtual guest idle state is available */ #define HV_X64_GUEST_IDLE_STATE_AVAILABLE … /* Frequency MSRs available */ #define HV_FEATURE_FREQUENCY_MSRS_AVAILABLE … /* Crash MSR available */ #define HV_FEATURE_GUEST_CRASH_MSR_AVAILABLE … /* Support for debug MSRs available */ #define HV_FEATURE_DEBUG_MSRS_AVAILABLE … /* Support for extended gva ranges for flush hypercalls available */ #define HV_FEATURE_EXT_GVA_RANGES_FLUSH … /* * Support for returning hypercall output block via XMM * registers is available */ #define HV_X64_HYPERCALL_XMM_OUTPUT_AVAILABLE … /* stimer Direct Mode is available */ #define HV_STIMER_DIRECT_MODE_AVAILABLE … /* * Implementation recommendations. Indicates which behaviors the hypervisor * recommends the OS implement for optimal performance. * These are HYPERV_CPUID_ENLIGHTMENT_INFO.EAX bits. */ /* * Recommend using hypercall for address space switches rather * than MOV to CR3 instruction */ #define HV_X64_AS_SWITCH_RECOMMENDED … /* Recommend using hypercall for local TLB flushes rather * than INVLPG or MOV to CR3 instructions */ #define HV_X64_LOCAL_TLB_FLUSH_RECOMMENDED … /* * Recommend using hypercall for remote TLB flushes rather * than inter-processor interrupts */ #define HV_X64_REMOTE_TLB_FLUSH_RECOMMENDED … /* * Recommend using MSRs for accessing APIC registers * EOI, ICR and TPR rather than their memory-mapped counterparts */ #define HV_X64_APIC_ACCESS_RECOMMENDED … /* Recommend using the hypervisor-provided MSR to initiate a system RESET */ #define HV_X64_SYSTEM_RESET_RECOMMENDED … /* * Recommend using relaxed timing for this partition. If used, * the VM should disable any watchdog timeouts that rely on the * timely delivery of external interrupts */ #define HV_X64_RELAXED_TIMING_RECOMMENDED … /* * Recommend not using Auto End-Of-Interrupt feature */ #define HV_DEPRECATING_AEOI_RECOMMENDED … /* * Recommend using cluster IPI hypercalls. */ #define HV_X64_CLUSTER_IPI_RECOMMENDED … /* Recommend using the newer ExProcessorMasks interface */ #define HV_X64_EX_PROCESSOR_MASKS_RECOMMENDED … /* Indicates that the hypervisor is nested within a Hyper-V partition. */ #define HV_X64_HYPERV_NESTED … /* Recommend using enlightened VMCS */ #define HV_X64_ENLIGHTENED_VMCS_RECOMMENDED … /* Use hypercalls for MMIO config space access */ #define HV_X64_USE_MMIO_HYPERCALLS … /* * CPU management features identification. * These are HYPERV_CPUID_CPU_MANAGEMENT_FEATURES.EAX bits. */ #define HV_X64_START_LOGICAL_PROCESSOR … #define HV_X64_CREATE_ROOT_VIRTUAL_PROCESSOR … #define HV_X64_PERFORMANCE_COUNTER_SYNC … #define HV_X64_RESERVED_IDENTITY_BIT … /* * Virtual processor will never share a physical core with another virtual * processor, except for virtual processors that are reported as sibling SMT * threads. */ #define HV_X64_NO_NONARCH_CORESHARING … /* Nested features. These are HYPERV_CPUID_NESTED_FEATURES.EAX bits. */ #define HV_X64_NESTED_DIRECT_FLUSH … #define HV_X64_NESTED_GUEST_MAPPING_FLUSH … #define HV_X64_NESTED_MSR_BITMAP … /* Nested features #2. These are HYPERV_CPUID_NESTED_FEATURES.EBX bits. */ #define HV_X64_NESTED_EVMCS1_PERF_GLOBAL_CTRL … /* * This is specific to AMD and specifies that enlightened TLB flush is * supported. If guest opts in to this feature, ASID invalidations only * flushes gva -> hpa mapping entries. To flush the TLB entries derived * from NPT, hypercalls should be used (HvFlushGuestPhysicalAddressSpace * or HvFlushGuestPhysicalAddressList). */ #define HV_X64_NESTED_ENLIGHTENED_TLB … /* HYPERV_CPUID_ISOLATION_CONFIG.EAX bits. */ #define HV_PARAVISOR_PRESENT … /* HYPERV_CPUID_ISOLATION_CONFIG.EBX bits. */ #define HV_ISOLATION_TYPE … #define HV_SHARED_GPA_BOUNDARY_ACTIVE … #define HV_SHARED_GPA_BOUNDARY_BITS … enum hv_isolation_type { … }; /* Hyper-V specific model specific registers (MSRs) */ /* MSR used to identify the guest OS. */ #define HV_X64_MSR_GUEST_OS_ID … /* MSR used to setup pages used to communicate with the hypervisor. */ #define HV_X64_MSR_HYPERCALL … /* MSR used to provide vcpu index */ #define HV_X64_MSR_VP_INDEX … /* MSR used to reset the guest OS. */ #define HV_X64_MSR_RESET … /* MSR used to provide vcpu runtime in 100ns units */ #define HV_X64_MSR_VP_RUNTIME … /* MSR used to read the per-partition time reference counter */ #define HV_X64_MSR_TIME_REF_COUNT … /* A partition's reference time stamp counter (TSC) page */ #define HV_X64_MSR_REFERENCE_TSC … /* MSR used to retrieve the TSC frequency */ #define HV_X64_MSR_TSC_FREQUENCY … /* MSR used to retrieve the local APIC timer frequency */ #define HV_X64_MSR_APIC_FREQUENCY … /* Define the virtual APIC registers */ #define HV_X64_MSR_EOI … #define HV_X64_MSR_ICR … #define HV_X64_MSR_TPR … #define HV_X64_MSR_VP_ASSIST_PAGE … /* Define synthetic interrupt controller model specific registers. */ #define HV_X64_MSR_SCONTROL … #define HV_X64_MSR_SVERSION … #define HV_X64_MSR_SIEFP … #define HV_X64_MSR_SIMP … #define HV_X64_MSR_EOM … #define HV_X64_MSR_SINT0 … #define HV_X64_MSR_SINT1 … #define HV_X64_MSR_SINT2 … #define HV_X64_MSR_SINT3 … #define HV_X64_MSR_SINT4 … #define HV_X64_MSR_SINT5 … #define HV_X64_MSR_SINT6 … #define HV_X64_MSR_SINT7 … #define HV_X64_MSR_SINT8 … #define HV_X64_MSR_SINT9 … #define HV_X64_MSR_SINT10 … #define HV_X64_MSR_SINT11 … #define HV_X64_MSR_SINT12 … #define HV_X64_MSR_SINT13 … #define HV_X64_MSR_SINT14 … #define HV_X64_MSR_SINT15 … /* * Define synthetic interrupt controller model specific registers for * nested hypervisor. */ #define HV_X64_MSR_NESTED_SCONTROL … #define HV_X64_MSR_NESTED_SVERSION … #define HV_X64_MSR_NESTED_SIEFP … #define HV_X64_MSR_NESTED_SIMP … #define HV_X64_MSR_NESTED_EOM … #define HV_X64_MSR_NESTED_SINT0 … /* * Synthetic Timer MSRs. Four timers per vcpu. */ #define HV_X64_MSR_STIMER0_CONFIG … #define HV_X64_MSR_STIMER0_COUNT … #define HV_X64_MSR_STIMER1_CONFIG … #define HV_X64_MSR_STIMER1_COUNT … #define HV_X64_MSR_STIMER2_CONFIG … #define HV_X64_MSR_STIMER2_COUNT … #define HV_X64_MSR_STIMER3_CONFIG … #define HV_X64_MSR_STIMER3_COUNT … /* Hyper-V guest idle MSR */ #define HV_X64_MSR_GUEST_IDLE … /* Hyper-V guest crash notification MSR's */ #define HV_X64_MSR_CRASH_P0 … #define HV_X64_MSR_CRASH_P1 … #define HV_X64_MSR_CRASH_P2 … #define HV_X64_MSR_CRASH_P3 … #define HV_X64_MSR_CRASH_P4 … #define HV_X64_MSR_CRASH_CTL … /* TSC emulation after migration */ #define HV_X64_MSR_REENLIGHTENMENT_CONTROL … #define HV_X64_MSR_TSC_EMULATION_CONTROL … #define HV_X64_MSR_TSC_EMULATION_STATUS … /* TSC invariant control */ #define HV_X64_MSR_TSC_INVARIANT_CONTROL … /* HV_X64_MSR_TSC_INVARIANT_CONTROL bits */ #define HV_EXPOSE_INVARIANT_TSC … /* * To support arch-generic code calling hv_set/get_register: * - On x86, HV_MSR_ indicates an MSR accessed via rdmsrl/wrmsrl * - On ARM, HV_MSR_ indicates a VP register accessed via hypercall */ #define HV_MSR_CRASH_P0 … #define HV_MSR_CRASH_P1 … #define HV_MSR_CRASH_P2 … #define HV_MSR_CRASH_P3 … #define HV_MSR_CRASH_P4 … #define HV_MSR_CRASH_CTL … #define HV_MSR_VP_INDEX … #define HV_MSR_TIME_REF_COUNT … #define HV_MSR_REFERENCE_TSC … #define HV_MSR_SINT0 … #define HV_MSR_SVERSION … #define HV_MSR_SCONTROL … #define HV_MSR_SIEFP … #define HV_MSR_SIMP … #define HV_MSR_EOM … #define HV_MSR_NESTED_SCONTROL … #define HV_MSR_NESTED_SVERSION … #define HV_MSR_NESTED_SIEFP … #define HV_MSR_NESTED_SIMP … #define HV_MSR_NESTED_EOM … #define HV_MSR_NESTED_SINT0 … #define HV_MSR_STIMER0_CONFIG … #define HV_MSR_STIMER0_COUNT … /* * Registers are only accessible via HVCALL_GET_VP_REGISTERS hvcall and * there is not associated MSR address. */ #define HV_X64_REGISTER_VSM_VP_STATUS … #define HV_X64_VTL_MASK … /* Hyper-V memory host visibility */ enum hv_mem_host_visibility { … }; /* HvCallModifySparseGpaPageHostVisibility hypercall */ #define HV_MAX_MODIFY_GPA_REP_COUNT … struct hv_gpa_range_for_visibility { … } __packed; /* * Declare the MSR used to setup pages used to communicate with the hypervisor. */ hv_x64_msr_hypercall_contents; hv_vp_assist_msr_contents; struct hv_reenlightenment_control { … } __packed; struct hv_tsc_emulation_control { … } __packed; struct hv_tsc_emulation_status { … } __packed; #define HV_X64_MSR_HYPERCALL_ENABLE … #define HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT … #define HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_MASK … #define HV_X64_MSR_CRASH_PARAMS … #define HV_IPI_LOW_VECTOR … #define HV_IPI_HIGH_VECTOR … #define HV_X64_MSR_VP_ASSIST_PAGE_ENABLE … #define HV_X64_MSR_VP_ASSIST_PAGE_ADDRESS_SHIFT … #define HV_X64_MSR_VP_ASSIST_PAGE_ADDRESS_MASK … /* Hyper-V Enlightened VMCS version mask in nested features CPUID */ #define HV_X64_ENLIGHTENED_VMCS_VERSION … #define HV_X64_MSR_TSC_REFERENCE_ENABLE … #define HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT … /* Number of XMM registers used in hypercall input/output */ #define HV_HYPERCALL_MAX_XMM_REGISTERS … struct hv_nested_enlightenments_control { … } __packed; /* Define virtual processor assist page structure. */ struct hv_vp_assist_page { … } __packed; struct hv_enlightened_vmcs { … } __packed; #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_NONE … #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_IO_BITMAP … #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_MSR_BITMAP … #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_GRP2 … #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_GRP1 … #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_PROC … #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_EVENT … #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_ENTRY … #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_EXCPN … #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CRDR … #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_XLAT … #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_GUEST_BASIC … #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_GUEST_GRP1 … #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_GUEST_GRP2 … #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_HOST_POINTER … #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_HOST_GRP1 … #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_ENLIGHTENMENTSCONTROL … #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_ALL … /* * Note, Hyper-V isn't actually stealing bit 28 from Intel, just abusing it by * pairing it with architecturally impossible exit reasons. Bit 28 is set only * on SMI exits to a SMI transfer monitor (STM) and if and only if a MTF VM-Exit * is pending. I.e. it will never be set by hardware for non-SMI exits (there * are only three), nor will it ever be set unless the VMM is an STM. */ #define HV_VMX_SYNTHETIC_EXIT_REASON_TRAP_AFTER_FLUSH … /* * Hyper-V uses the software reserved 32 bytes in VMCB control area to expose * SVM enlightenments to guests. */ struct hv_vmcb_enlightenments { … } __packed; /* * Hyper-V uses the software reserved clean bit in VMCB. */ #define HV_VMCB_NESTED_ENLIGHTENMENTS … /* Synthetic VM-Exit */ #define HV_SVM_EXITCODE_ENL … #define HV_SVM_ENL_EXITCODE_TRAP_AFTER_FLUSH … struct hv_partition_assist_pg { … }; enum hv_interrupt_type { … }; hv_msi_address_register __packed; hv_msi_data_register __packed; /* HvRetargetDeviceInterrupt hypercall */ hv_msi_entry; struct hv_x64_segment_register { … } __packed; struct hv_x64_table_register { … } __packed; struct hv_init_vp_context { … } __packed; hv_input_vtl __packed; struct hv_enable_vp_vtl { … } __packed; struct hv_get_vp_from_apic_id_in { … } __packed; #include <asm-generic/hyperv-tlfs.h> #endif
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