/*
* Copyright 2020 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef _mmhub_1_7_OFFSET_HEADER
#define _mmhub_1_7_OFFSET_HEADER
// addressBlock: mmhub_dagb_dagbdec0
// base address: 0x68000
#define regDAGB0_RDCLI0 0x0000
#define regDAGB0_RDCLI0_BASE_IDX 0
#define regDAGB0_RDCLI1 0x0001
#define regDAGB0_RDCLI1_BASE_IDX 0
#define regDAGB0_RDCLI2 0x0002
#define regDAGB0_RDCLI2_BASE_IDX 0
#define regDAGB0_RDCLI3 0x0003
#define regDAGB0_RDCLI3_BASE_IDX 0
#define regDAGB0_RDCLI4 0x0004
#define regDAGB0_RDCLI4_BASE_IDX 0
#define regDAGB0_RDCLI5 0x0005
#define regDAGB0_RDCLI5_BASE_IDX 0
#define regDAGB0_RDCLI6 0x0006
#define regDAGB0_RDCLI6_BASE_IDX 0
#define regDAGB0_RDCLI7 0x0007
#define regDAGB0_RDCLI7_BASE_IDX 0
#define regDAGB0_RDCLI8 0x0008
#define regDAGB0_RDCLI8_BASE_IDX 0
#define regDAGB0_RDCLI9 0x0009
#define regDAGB0_RDCLI9_BASE_IDX 0
#define regDAGB0_RDCLI10 0x000a
#define regDAGB0_RDCLI10_BASE_IDX 0
#define regDAGB0_RDCLI11 0x000b
#define regDAGB0_RDCLI11_BASE_IDX 0
#define regDAGB0_RDCLI12 0x000c
#define regDAGB0_RDCLI12_BASE_IDX 0
#define regDAGB0_RDCLI13 0x000d
#define regDAGB0_RDCLI13_BASE_IDX 0
#define regDAGB0_RDCLI14 0x000e
#define regDAGB0_RDCLI14_BASE_IDX 0
#define regDAGB0_RDCLI15 0x000f
#define regDAGB0_RDCLI15_BASE_IDX 0
#define regDAGB0_RD_CNTL 0x0010
#define regDAGB0_RD_CNTL_BASE_IDX 0
#define regDAGB0_RD_GMI_CNTL 0x0011
#define regDAGB0_RD_GMI_CNTL_BASE_IDX 0
#define regDAGB0_RD_ADDR_DAGB 0x0012
#define regDAGB0_RD_ADDR_DAGB_BASE_IDX 0
#define regDAGB0_RD_OUTPUT_DAGB_MAX_BURST 0x0013
#define regDAGB0_RD_OUTPUT_DAGB_MAX_BURST_BASE_IDX 0
#define regDAGB0_RD_OUTPUT_DAGB_LAZY_TIMER 0x0014
#define regDAGB0_RD_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 0
#define regDAGB0_RD_CGTT_CLK_CTRL 0x0015
#define regDAGB0_RD_CGTT_CLK_CTRL_BASE_IDX 0
#define regDAGB0_L1TLB_RD_CGTT_CLK_CTRL 0x0016
#define regDAGB0_L1TLB_RD_CGTT_CLK_CTRL_BASE_IDX 0
#define regDAGB0_ATCVM_RD_CGTT_CLK_CTRL 0x0017
#define regDAGB0_ATCVM_RD_CGTT_CLK_CTRL_BASE_IDX 0
#define regDAGB0_RD_ADDR_DAGB_MAX_BURST0 0x0018
#define regDAGB0_RD_ADDR_DAGB_MAX_BURST0_BASE_IDX 0
#define regDAGB0_RD_ADDR_DAGB_LAZY_TIMER0 0x0019
#define regDAGB0_RD_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 0
#define regDAGB0_RD_ADDR_DAGB_MAX_BURST1 0x001a
#define regDAGB0_RD_ADDR_DAGB_MAX_BURST1_BASE_IDX 0
#define regDAGB0_RD_ADDR_DAGB_LAZY_TIMER1 0x001b
#define regDAGB0_RD_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 0
#define regDAGB0_RD_VC0_CNTL 0x001c
#define regDAGB0_RD_VC0_CNTL_BASE_IDX 0
#define regDAGB0_RD_VC1_CNTL 0x001d
#define regDAGB0_RD_VC1_CNTL_BASE_IDX 0
#define regDAGB0_RD_VC2_CNTL 0x001e
#define regDAGB0_RD_VC2_CNTL_BASE_IDX 0
#define regDAGB0_RD_VC3_CNTL 0x001f
#define regDAGB0_RD_VC3_CNTL_BASE_IDX 0
#define regDAGB0_RD_VC4_CNTL 0x0020
#define regDAGB0_RD_VC4_CNTL_BASE_IDX 0
#define regDAGB0_RD_VC5_CNTL 0x0021
#define regDAGB0_RD_VC5_CNTL_BASE_IDX 0
#define regDAGB0_RD_VC6_CNTL 0x0022
#define regDAGB0_RD_VC6_CNTL_BASE_IDX 0
#define regDAGB0_RD_VC7_CNTL 0x0023
#define regDAGB0_RD_VC7_CNTL_BASE_IDX 0
#define regDAGB0_RD_CNTL_MISC 0x0024
#define regDAGB0_RD_CNTL_MISC_BASE_IDX 0
#define regDAGB0_RD_TLB_CREDIT 0x0025
#define regDAGB0_RD_TLB_CREDIT_BASE_IDX 0
#define regDAGB0_RD_RDRET_CREDIT_CNTL 0x0026
#define regDAGB0_RD_RDRET_CREDIT_CNTL_BASE_IDX 0
#define regDAGB0_RD_RDRET_CREDIT_CNTL2 0x0027
#define regDAGB0_RD_RDRET_CREDIT_CNTL2_BASE_IDX 0
#define regDAGB0_RDCLI_ASK_PENDING 0x0028
#define regDAGB0_RDCLI_ASK_PENDING_BASE_IDX 0
#define regDAGB0_RDCLI_GO_PENDING 0x0029
#define regDAGB0_RDCLI_GO_PENDING_BASE_IDX 0
#define regDAGB0_RDCLI_GBLSEND_PENDING 0x002a
#define regDAGB0_RDCLI_GBLSEND_PENDING_BASE_IDX 0
#define regDAGB0_RDCLI_TLB_PENDING 0x002b
#define regDAGB0_RDCLI_TLB_PENDING_BASE_IDX 0
#define regDAGB0_RDCLI_OARB_PENDING 0x002c
#define regDAGB0_RDCLI_OARB_PENDING_BASE_IDX 0
#define regDAGB0_RDCLI_OSD_PENDING 0x002d
#define regDAGB0_RDCLI_OSD_PENDING_BASE_IDX 0
#define regDAGB0_WRCLI0 0x002e
#define regDAGB0_WRCLI0_BASE_IDX 0
#define regDAGB0_WRCLI1 0x002f
#define regDAGB0_WRCLI1_BASE_IDX 0
#define regDAGB0_WRCLI2 0x0030
#define regDAGB0_WRCLI2_BASE_IDX 0
#define regDAGB0_WRCLI3 0x0031
#define regDAGB0_WRCLI3_BASE_IDX 0
#define regDAGB0_WRCLI4 0x0032
#define regDAGB0_WRCLI4_BASE_IDX 0
#define regDAGB0_WRCLI5 0x0033
#define regDAGB0_WRCLI5_BASE_IDX 0
#define regDAGB0_WRCLI6 0x0034
#define regDAGB0_WRCLI6_BASE_IDX 0
#define regDAGB0_WRCLI7 0x0035
#define regDAGB0_WRCLI7_BASE_IDX 0
#define regDAGB0_WRCLI8 0x0036
#define regDAGB0_WRCLI8_BASE_IDX 0
#define regDAGB0_WRCLI9 0x0037
#define regDAGB0_WRCLI9_BASE_IDX 0
#define regDAGB0_WRCLI10 0x0038
#define regDAGB0_WRCLI10_BASE_IDX 0
#define regDAGB0_WRCLI11 0x0039
#define regDAGB0_WRCLI11_BASE_IDX 0
#define regDAGB0_WRCLI12 0x003a
#define regDAGB0_WRCLI12_BASE_IDX 0
#define regDAGB0_WRCLI13 0x003b
#define regDAGB0_WRCLI13_BASE_IDX 0
#define regDAGB0_WRCLI14 0x003c
#define regDAGB0_WRCLI14_BASE_IDX 0
#define regDAGB0_WRCLI15 0x003d
#define regDAGB0_WRCLI15_BASE_IDX 0
#define regDAGB0_WR_CNTL 0x003e
#define regDAGB0_WR_CNTL_BASE_IDX 0
#define regDAGB0_WR_GMI_CNTL 0x003f
#define regDAGB0_WR_GMI_CNTL_BASE_IDX 0
#define regDAGB0_WR_ADDR_DAGB 0x0040
#define regDAGB0_WR_ADDR_DAGB_BASE_IDX 0
#define regDAGB0_WR_OUTPUT_DAGB_MAX_BURST 0x0041
#define regDAGB0_WR_OUTPUT_DAGB_MAX_BURST_BASE_IDX 0
#define regDAGB0_WR_OUTPUT_DAGB_LAZY_TIMER 0x0042
#define regDAGB0_WR_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 0
#define regDAGB0_WR_CGTT_CLK_CTRL 0x0043
#define regDAGB0_WR_CGTT_CLK_CTRL_BASE_IDX 0
#define regDAGB0_L1TLB_WR_CGTT_CLK_CTRL 0x0044
#define regDAGB0_L1TLB_WR_CGTT_CLK_CTRL_BASE_IDX 0
#define regDAGB0_ATCVM_WR_CGTT_CLK_CTRL 0x0045
#define regDAGB0_ATCVM_WR_CGTT_CLK_CTRL_BASE_IDX 0
#define regDAGB0_WR_ADDR_DAGB_MAX_BURST0 0x0046
#define regDAGB0_WR_ADDR_DAGB_MAX_BURST0_BASE_IDX 0
#define regDAGB0_WR_ADDR_DAGB_LAZY_TIMER0 0x0047
#define regDAGB0_WR_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 0
#define regDAGB0_WR_ADDR_DAGB_MAX_BURST1 0x0048
#define regDAGB0_WR_ADDR_DAGB_MAX_BURST1_BASE_IDX 0
#define regDAGB0_WR_ADDR_DAGB_LAZY_TIMER1 0x0049
#define regDAGB0_WR_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 0
#define regDAGB0_WR_DATA_DAGB 0x004a
#define regDAGB0_WR_DATA_DAGB_BASE_IDX 0
#define regDAGB0_WR_DATA_DAGB_MAX_BURST0 0x004b
#define regDAGB0_WR_DATA_DAGB_MAX_BURST0_BASE_IDX 0
#define regDAGB0_WR_DATA_DAGB_LAZY_TIMER0 0x004c
#define regDAGB0_WR_DATA_DAGB_LAZY_TIMER0_BASE_IDX 0
#define regDAGB0_WR_DATA_DAGB_MAX_BURST1 0x004d
#define regDAGB0_WR_DATA_DAGB_MAX_BURST1_BASE_IDX 0
#define regDAGB0_WR_DATA_DAGB_LAZY_TIMER1 0x004e
#define regDAGB0_WR_DATA_DAGB_LAZY_TIMER1_BASE_IDX 0
#define regDAGB0_WR_VC0_CNTL 0x004f
#define regDAGB0_WR_VC0_CNTL_BASE_IDX 0
#define regDAGB0_WR_VC1_CNTL 0x0050
#define regDAGB0_WR_VC1_CNTL_BASE_IDX 0
#define regDAGB0_WR_VC2_CNTL 0x0051
#define regDAGB0_WR_VC2_CNTL_BASE_IDX 0
#define regDAGB0_WR_VC3_CNTL 0x0052
#define regDAGB0_WR_VC3_CNTL_BASE_IDX 0
#define regDAGB0_WR_VC4_CNTL 0x0053
#define regDAGB0_WR_VC4_CNTL_BASE_IDX 0
#define regDAGB0_WR_VC5_CNTL 0x0054
#define regDAGB0_WR_VC5_CNTL_BASE_IDX 0
#define regDAGB0_WR_VC6_CNTL 0x0055
#define regDAGB0_WR_VC6_CNTL_BASE_IDX 0
#define regDAGB0_WR_VC7_CNTL 0x0056
#define regDAGB0_WR_VC7_CNTL_BASE_IDX 0
#define regDAGB0_WR_CNTL_MISC 0x0057
#define regDAGB0_WR_CNTL_MISC_BASE_IDX 0
#define regDAGB0_WR_TLB_CREDIT 0x0058
#define regDAGB0_WR_TLB_CREDIT_BASE_IDX 0
#define regDAGB0_WR_DATA_CREDIT 0x0059
#define regDAGB0_WR_DATA_CREDIT_BASE_IDX 0
#define regDAGB0_WR_MISC_CREDIT 0x005a
#define regDAGB0_WR_MISC_CREDIT_BASE_IDX 0
#define regDAGB0_WR_OSD_CREDIT_CNTL1 0x005b
#define regDAGB0_WR_OSD_CREDIT_CNTL1_BASE_IDX 0
#define regDAGB0_WR_OSD_CREDIT_CNTL2 0x005c
#define regDAGB0_WR_OSD_CREDIT_CNTL2_BASE_IDX 0
#define regDAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1 0x005d
#define regDAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1_BASE_IDX 0
#define regDAGB0_WRCLI_GPU_SNOOP_OVERRIDE 0x005e
#define regDAGB0_WRCLI_GPU_SNOOP_OVERRIDE_BASE_IDX 0
#define regDAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE 0x005f
#define regDAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE_BASE_IDX 0
#define regDAGB0_WRCLI_ASK_PENDING 0x0060
#define regDAGB0_WRCLI_ASK_PENDING_BASE_IDX 0
#define regDAGB0_WRCLI_GO_PENDING 0x0061
#define regDAGB0_WRCLI_GO_PENDING_BASE_IDX 0
#define regDAGB0_WRCLI_GBLSEND_PENDING 0x0062
#define regDAGB0_WRCLI_GBLSEND_PENDING_BASE_IDX 0
#define regDAGB0_WRCLI_TLB_PENDING 0x0063
#define regDAGB0_WRCLI_TLB_PENDING_BASE_IDX 0
#define regDAGB0_WRCLI_OARB_PENDING 0x0064
#define regDAGB0_WRCLI_OARB_PENDING_BASE_IDX 0
#define regDAGB0_WRCLI_OSD_PENDING 0x0065
#define regDAGB0_WRCLI_OSD_PENDING_BASE_IDX 0
#define regDAGB0_WRCLI_DBUS_ASK_PENDING 0x0066
#define regDAGB0_WRCLI_DBUS_ASK_PENDING_BASE_IDX 0
#define regDAGB0_WRCLI_DBUS_GO_PENDING 0x0067
#define regDAGB0_WRCLI_DBUS_GO_PENDING_BASE_IDX 0
#define regDAGB0_DAGB_DLY 0x0068
#define regDAGB0_DAGB_DLY_BASE_IDX 0
#define regDAGB0_CNTL_MISC 0x0069
#define regDAGB0_CNTL_MISC_BASE_IDX 0
#define regDAGB0_CNTL_MISC2 0x006a
#define regDAGB0_CNTL_MISC2_BASE_IDX 0
#define regDAGB0_FATAL_ERROR_CNTL 0x006b
#define regDAGB0_FATAL_ERROR_CNTL_BASE_IDX 0
#define regDAGB0_FATAL_ERROR_CLEAR 0x006c
#define regDAGB0_FATAL_ERROR_CLEAR_BASE_IDX 0
#define regDAGB0_FATAL_ERROR_STATUS0 0x006d
#define regDAGB0_FATAL_ERROR_STATUS0_BASE_IDX 0
#define regDAGB0_FATAL_ERROR_STATUS1 0x006e
#define regDAGB0_FATAL_ERROR_STATUS1_BASE_IDX 0
#define regDAGB0_FATAL_ERROR_STATUS2 0x006f
#define regDAGB0_FATAL_ERROR_STATUS2_BASE_IDX 0
#define regDAGB0_FATAL_ERROR_STATUS3 0x0070
#define regDAGB0_FATAL_ERROR_STATUS3_BASE_IDX 0
#define regDAGB0_FIFO_EMPTY 0x0071
#define regDAGB0_FIFO_EMPTY_BASE_IDX 0
#define regDAGB0_FIFO_FULL 0x0072
#define regDAGB0_FIFO_FULL_BASE_IDX 0
#define regDAGB0_WR_CREDITS_FULL 0x0073
#define regDAGB0_WR_CREDITS_FULL_BASE_IDX 0
#define regDAGB0_RD_CREDITS_FULL 0x0074
#define regDAGB0_RD_CREDITS_FULL_BASE_IDX 0
#define regDAGB0_PERFCOUNTER_LO 0x0075
#define regDAGB0_PERFCOUNTER_LO_BASE_IDX 0
#define regDAGB0_PERFCOUNTER_HI 0x0076
#define regDAGB0_PERFCOUNTER_HI_BASE_IDX 0
#define regDAGB0_PERFCOUNTER0_CFG 0x0077
#define regDAGB0_PERFCOUNTER0_CFG_BASE_IDX 0
#define regDAGB0_PERFCOUNTER1_CFG 0x0078
#define regDAGB0_PERFCOUNTER1_CFG_BASE_IDX 0
#define regDAGB0_PERFCOUNTER2_CFG 0x0079
#define regDAGB0_PERFCOUNTER2_CFG_BASE_IDX 0
#define regDAGB0_PERFCOUNTER_RSLT_CNTL 0x007a
#define regDAGB0_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0
#define regDAGB0_L1TLB_REG_RW 0x007b
#define regDAGB0_L1TLB_REG_RW_BASE_IDX 0
#define regDAGB0_RESERVE1 0x007c
#define regDAGB0_RESERVE1_BASE_IDX 0
#define regDAGB0_RESERVE2 0x007d
#define regDAGB0_RESERVE2_BASE_IDX 0
#define regDAGB0_RESERVE3 0x007e
#define regDAGB0_RESERVE3_BASE_IDX 0
#define regDAGB0_RESERVE4 0x007f
#define regDAGB0_RESERVE4_BASE_IDX 0
// addressBlock: mmhub_dagb_dagbdec1
// base address: 0x68200
#define regDAGB1_RDCLI0 0x0080
#define regDAGB1_RDCLI0_BASE_IDX 0
#define regDAGB1_RDCLI1 0x0081
#define regDAGB1_RDCLI1_BASE_IDX 0
#define regDAGB1_RDCLI2 0x0082
#define regDAGB1_RDCLI2_BASE_IDX 0
#define regDAGB1_RDCLI3 0x0083
#define regDAGB1_RDCLI3_BASE_IDX 0
#define regDAGB1_RDCLI4 0x0084
#define regDAGB1_RDCLI4_BASE_IDX 0
#define regDAGB1_RDCLI5 0x0085
#define regDAGB1_RDCLI5_BASE_IDX 0
#define regDAGB1_RDCLI6 0x0086
#define regDAGB1_RDCLI6_BASE_IDX 0
#define regDAGB1_RDCLI7 0x0087
#define regDAGB1_RDCLI7_BASE_IDX 0
#define regDAGB1_RDCLI8 0x0088
#define regDAGB1_RDCLI8_BASE_IDX 0
#define regDAGB1_RDCLI9 0x0089
#define regDAGB1_RDCLI9_BASE_IDX 0
#define regDAGB1_RDCLI10 0x008a
#define regDAGB1_RDCLI10_BASE_IDX 0
#define regDAGB1_RDCLI11 0x008b
#define regDAGB1_RDCLI11_BASE_IDX 0
#define regDAGB1_RDCLI12 0x008c
#define regDAGB1_RDCLI12_BASE_IDX 0
#define regDAGB1_RDCLI13 0x008d
#define regDAGB1_RDCLI13_BASE_IDX 0
#define regDAGB1_RDCLI14 0x008e
#define regDAGB1_RDCLI14_BASE_IDX 0
#define regDAGB1_RDCLI15 0x008f
#define regDAGB1_RDCLI15_BASE_IDX 0
#define regDAGB1_RD_CNTL 0x0090
#define regDAGB1_RD_CNTL_BASE_IDX 0
#define regDAGB1_RD_GMI_CNTL 0x0091
#define regDAGB1_RD_GMI_CNTL_BASE_IDX 0
#define regDAGB1_RD_ADDR_DAGB 0x0092
#define regDAGB1_RD_ADDR_DAGB_BASE_IDX 0
#define regDAGB1_RD_OUTPUT_DAGB_MAX_BURST 0x0093
#define regDAGB1_RD_OUTPUT_DAGB_MAX_BURST_BASE_IDX 0
#define regDAGB1_RD_OUTPUT_DAGB_LAZY_TIMER 0x0094
#define regDAGB1_RD_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 0
#define regDAGB1_RD_CGTT_CLK_CTRL 0x0095
#define regDAGB1_RD_CGTT_CLK_CTRL_BASE_IDX 0
#define regDAGB1_L1TLB_RD_CGTT_CLK_CTRL 0x0096
#define regDAGB1_L1TLB_RD_CGTT_CLK_CTRL_BASE_IDX 0
#define regDAGB1_ATCVM_RD_CGTT_CLK_CTRL 0x0097
#define regDAGB1_ATCVM_RD_CGTT_CLK_CTRL_BASE_IDX 0
#define regDAGB1_RD_ADDR_DAGB_MAX_BURST0 0x0098
#define regDAGB1_RD_ADDR_DAGB_MAX_BURST0_BASE_IDX 0
#define regDAGB1_RD_ADDR_DAGB_LAZY_TIMER0 0x0099
#define regDAGB1_RD_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 0
#define regDAGB1_RD_ADDR_DAGB_MAX_BURST1 0x009a
#define regDAGB1_RD_ADDR_DAGB_MAX_BURST1_BASE_IDX 0
#define regDAGB1_RD_ADDR_DAGB_LAZY_TIMER1 0x009b
#define regDAGB1_RD_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 0
#define regDAGB1_RD_VC0_CNTL 0x009c
#define regDAGB1_RD_VC0_CNTL_BASE_IDX 0
#define regDAGB1_RD_VC1_CNTL 0x009d
#define regDAGB1_RD_VC1_CNTL_BASE_IDX 0
#define regDAGB1_RD_VC2_CNTL 0x009e
#define regDAGB1_RD_VC2_CNTL_BASE_IDX 0
#define regDAGB1_RD_VC3_CNTL 0x009f
#define regDAGB1_RD_VC3_CNTL_BASE_IDX 0
#define regDAGB1_RD_VC4_CNTL 0x00a0
#define regDAGB1_RD_VC4_CNTL_BASE_IDX 0
#define regDAGB1_RD_VC5_CNTL 0x00a1
#define regDAGB1_RD_VC5_CNTL_BASE_IDX 0
#define regDAGB1_RD_VC6_CNTL 0x00a2
#define regDAGB1_RD_VC6_CNTL_BASE_IDX 0
#define regDAGB1_RD_VC7_CNTL 0x00a3
#define regDAGB1_RD_VC7_CNTL_BASE_IDX 0
#define regDAGB1_RD_CNTL_MISC 0x00a4
#define regDAGB1_RD_CNTL_MISC_BASE_IDX 0
#define regDAGB1_RD_TLB_CREDIT 0x00a5
#define regDAGB1_RD_TLB_CREDIT_BASE_IDX 0
#define regDAGB1_RD_RDRET_CREDIT_CNTL 0x00a6
#define regDAGB1_RD_RDRET_CREDIT_CNTL_BASE_IDX 0
#define regDAGB1_RD_RDRET_CREDIT_CNTL2 0x00a7
#define regDAGB1_RD_RDRET_CREDIT_CNTL2_BASE_IDX 0
#define regDAGB1_RDCLI_ASK_PENDING 0x00a8
#define regDAGB1_RDCLI_ASK_PENDING_BASE_IDX 0
#define regDAGB1_RDCLI_GO_PENDING 0x00a9
#define regDAGB1_RDCLI_GO_PENDING_BASE_IDX 0
#define regDAGB1_RDCLI_GBLSEND_PENDING 0x00aa
#define regDAGB1_RDCLI_GBLSEND_PENDING_BASE_IDX 0
#define regDAGB1_RDCLI_TLB_PENDING 0x00ab
#define regDAGB1_RDCLI_TLB_PENDING_BASE_IDX 0
#define regDAGB1_RDCLI_OARB_PENDING 0x00ac
#define regDAGB1_RDCLI_OARB_PENDING_BASE_IDX 0
#define regDAGB1_RDCLI_OSD_PENDING 0x00ad
#define regDAGB1_RDCLI_OSD_PENDING_BASE_IDX 0
#define regDAGB1_WRCLI0 0x00ae
#define regDAGB1_WRCLI0_BASE_IDX 0
#define regDAGB1_WRCLI1 0x00af
#define regDAGB1_WRCLI1_BASE_IDX 0
#define regDAGB1_WRCLI2 0x00b0
#define regDAGB1_WRCLI2_BASE_IDX 0
#define regDAGB1_WRCLI3 0x00b1
#define regDAGB1_WRCLI3_BASE_IDX 0
#define regDAGB1_WRCLI4 0x00b2
#define regDAGB1_WRCLI4_BASE_IDX 0
#define regDAGB1_WRCLI5 0x00b3
#define regDAGB1_WRCLI5_BASE_IDX 0
#define regDAGB1_WRCLI6 0x00b4
#define regDAGB1_WRCLI6_BASE_IDX 0
#define regDAGB1_WRCLI7 0x00b5
#define regDAGB1_WRCLI7_BASE_IDX 0
#define regDAGB1_WRCLI8 0x00b6
#define regDAGB1_WRCLI8_BASE_IDX 0
#define regDAGB1_WRCLI9 0x00b7
#define regDAGB1_WRCLI9_BASE_IDX 0
#define regDAGB1_WRCLI10 0x00b8
#define regDAGB1_WRCLI10_BASE_IDX 0
#define regDAGB1_WRCLI11 0x00b9
#define regDAGB1_WRCLI11_BASE_IDX 0
#define regDAGB1_WRCLI12 0x00ba
#define regDAGB1_WRCLI12_BASE_IDX 0
#define regDAGB1_WRCLI13 0x00bb
#define regDAGB1_WRCLI13_BASE_IDX 0
#define regDAGB1_WRCLI14 0x00bc
#define regDAGB1_WRCLI14_BASE_IDX 0
#define regDAGB1_WRCLI15 0x00bd
#define regDAGB1_WRCLI15_BASE_IDX 0
#define regDAGB1_WR_CNTL 0x00be
#define regDAGB1_WR_CNTL_BASE_IDX 0
#define regDAGB1_WR_GMI_CNTL 0x00bf
#define regDAGB1_WR_GMI_CNTL_BASE_IDX 0
#define regDAGB1_WR_ADDR_DAGB 0x00c0
#define regDAGB1_WR_ADDR_DAGB_BASE_IDX 0
#define regDAGB1_WR_OUTPUT_DAGB_MAX_BURST 0x00c1
#define regDAGB1_WR_OUTPUT_DAGB_MAX_BURST_BASE_IDX 0
#define regDAGB1_WR_OUTPUT_DAGB_LAZY_TIMER 0x00c2
#define regDAGB1_WR_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 0
#define regDAGB1_WR_CGTT_CLK_CTRL 0x00c3
#define regDAGB1_WR_CGTT_CLK_CTRL_BASE_IDX 0
#define regDAGB1_L1TLB_WR_CGTT_CLK_CTRL 0x00c4
#define regDAGB1_L1TLB_WR_CGTT_CLK_CTRL_BASE_IDX 0
#define regDAGB1_ATCVM_WR_CGTT_CLK_CTRL 0x00c5
#define regDAGB1_ATCVM_WR_CGTT_CLK_CTRL_BASE_IDX 0
#define regDAGB1_WR_ADDR_DAGB_MAX_BURST0 0x00c6
#define regDAGB1_WR_ADDR_DAGB_MAX_BURST0_BASE_IDX 0
#define regDAGB1_WR_ADDR_DAGB_LAZY_TIMER0 0x00c7
#define regDAGB1_WR_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 0
#define regDAGB1_WR_ADDR_DAGB_MAX_BURST1 0x00c8
#define regDAGB1_WR_ADDR_DAGB_MAX_BURST1_BASE_IDX 0
#define regDAGB1_WR_ADDR_DAGB_LAZY_TIMER1 0x00c9
#define regDAGB1_WR_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 0
#define regDAGB1_WR_DATA_DAGB 0x00ca
#define regDAGB1_WR_DATA_DAGB_BASE_IDX 0
#define regDAGB1_WR_DATA_DAGB_MAX_BURST0 0x00cb
#define regDAGB1_WR_DATA_DAGB_MAX_BURST0_BASE_IDX 0
#define regDAGB1_WR_DATA_DAGB_LAZY_TIMER0 0x00cc
#define regDAGB1_WR_DATA_DAGB_LAZY_TIMER0_BASE_IDX 0
#define regDAGB1_WR_DATA_DAGB_MAX_BURST1 0x00cd
#define regDAGB1_WR_DATA_DAGB_MAX_BURST1_BASE_IDX 0
#define regDAGB1_WR_DATA_DAGB_LAZY_TIMER1 0x00ce
#define regDAGB1_WR_DATA_DAGB_LAZY_TIMER1_BASE_IDX 0
#define regDAGB1_WR_VC0_CNTL 0x00cf
#define regDAGB1_WR_VC0_CNTL_BASE_IDX 0
#define regDAGB1_WR_VC1_CNTL 0x00d0
#define regDAGB1_WR_VC1_CNTL_BASE_IDX 0
#define regDAGB1_WR_VC2_CNTL 0x00d1
#define regDAGB1_WR_VC2_CNTL_BASE_IDX 0
#define regDAGB1_WR_VC3_CNTL 0x00d2
#define regDAGB1_WR_VC3_CNTL_BASE_IDX 0
#define regDAGB1_WR_VC4_CNTL 0x00d3
#define regDAGB1_WR_VC4_CNTL_BASE_IDX 0
#define regDAGB1_WR_VC5_CNTL 0x00d4
#define regDAGB1_WR_VC5_CNTL_BASE_IDX 0
#define regDAGB1_WR_VC6_CNTL 0x00d5
#define regDAGB1_WR_VC6_CNTL_BASE_IDX 0
#define regDAGB1_WR_VC7_CNTL 0x00d6
#define regDAGB1_WR_VC7_CNTL_BASE_IDX 0
#define regDAGB1_WR_CNTL_MISC 0x00d7
#define regDAGB1_WR_CNTL_MISC_BASE_IDX 0
#define regDAGB1_WR_TLB_CREDIT 0x00d8
#define regDAGB1_WR_TLB_CREDIT_BASE_IDX 0
#define regDAGB1_WR_DATA_CREDIT 0x00d9
#define regDAGB1_WR_DATA_CREDIT_BASE_IDX 0
#define regDAGB1_WR_MISC_CREDIT 0x00da
#define regDAGB1_WR_MISC_CREDIT_BASE_IDX 0
#define regDAGB1_WR_OSD_CREDIT_CNTL1 0x00db
#define regDAGB1_WR_OSD_CREDIT_CNTL1_BASE_IDX 0
#define regDAGB1_WR_OSD_CREDIT_CNTL2 0x00dc
#define regDAGB1_WR_OSD_CREDIT_CNTL2_BASE_IDX 0
#define regDAGB1_WR_ATOMIC_FIFO_CREDIT_CNTL1 0x00dd
#define regDAGB1_WR_ATOMIC_FIFO_CREDIT_CNTL1_BASE_IDX 0
#define regDAGB1_WRCLI_GPU_SNOOP_OVERRIDE 0x00de
#define regDAGB1_WRCLI_GPU_SNOOP_OVERRIDE_BASE_IDX 0
#define regDAGB1_WRCLI_GPU_SNOOP_OVERRIDE_VALUE 0x00df
#define regDAGB1_WRCLI_GPU_SNOOP_OVERRIDE_VALUE_BASE_IDX 0
#define regDAGB1_WRCLI_ASK_PENDING 0x00e0
#define regDAGB1_WRCLI_ASK_PENDING_BASE_IDX 0
#define regDAGB1_WRCLI_GO_PENDING 0x00e1
#define regDAGB1_WRCLI_GO_PENDING_BASE_IDX 0
#define regDAGB1_WRCLI_GBLSEND_PENDING 0x00e2
#define regDAGB1_WRCLI_GBLSEND_PENDING_BASE_IDX 0
#define regDAGB1_WRCLI_TLB_PENDING 0x00e3
#define regDAGB1_WRCLI_TLB_PENDING_BASE_IDX 0
#define regDAGB1_WRCLI_OARB_PENDING 0x00e4
#define regDAGB1_WRCLI_OARB_PENDING_BASE_IDX 0
#define regDAGB1_WRCLI_OSD_PENDING 0x00e5
#define regDAGB1_WRCLI_OSD_PENDING_BASE_IDX 0
#define regDAGB1_WRCLI_DBUS_ASK_PENDING 0x00e6
#define regDAGB1_WRCLI_DBUS_ASK_PENDING_BASE_IDX 0
#define regDAGB1_WRCLI_DBUS_GO_PENDING 0x00e7
#define regDAGB1_WRCLI_DBUS_GO_PENDING_BASE_IDX 0
#define regDAGB1_DAGB_DLY 0x00e8
#define regDAGB1_DAGB_DLY_BASE_IDX 0
#define regDAGB1_CNTL_MISC 0x00e9
#define regDAGB1_CNTL_MISC_BASE_IDX 0
#define regDAGB1_CNTL_MISC2 0x00ea
#define regDAGB1_CNTL_MISC2_BASE_IDX 0
#define regDAGB1_FATAL_ERROR_CNTL 0x00eb
#define regDAGB1_FATAL_ERROR_CNTL_BASE_IDX 0
#define regDAGB1_FATAL_ERROR_CLEAR 0x00ec
#define regDAGB1_FATAL_ERROR_CLEAR_BASE_IDX 0
#define regDAGB1_FATAL_ERROR_STATUS0 0x00ed
#define regDAGB1_FATAL_ERROR_STATUS0_BASE_IDX 0
#define regDAGB1_FATAL_ERROR_STATUS1 0x00ee
#define regDAGB1_FATAL_ERROR_STATUS1_BASE_IDX 0
#define regDAGB1_FATAL_ERROR_STATUS2 0x00ef
#define regDAGB1_FATAL_ERROR_STATUS2_BASE_IDX 0
#define regDAGB1_FATAL_ERROR_STATUS3 0x00f0
#define regDAGB1_FATAL_ERROR_STATUS3_BASE_IDX 0
#define regDAGB1_FIFO_EMPTY 0x00f1
#define regDAGB1_FIFO_EMPTY_BASE_IDX 0
#define regDAGB1_FIFO_FULL 0x00f2
#define regDAGB1_FIFO_FULL_BASE_IDX 0
#define regDAGB1_WR_CREDITS_FULL 0x00f3
#define regDAGB1_WR_CREDITS_FULL_BASE_IDX 0
#define regDAGB1_RD_CREDITS_FULL 0x00f4
#define regDAGB1_RD_CREDITS_FULL_BASE_IDX 0
#define regDAGB1_PERFCOUNTER_LO 0x00f5
#define regDAGB1_PERFCOUNTER_LO_BASE_IDX 0
#define regDAGB1_PERFCOUNTER_HI 0x00f6
#define regDAGB1_PERFCOUNTER_HI_BASE_IDX 0
#define regDAGB1_PERFCOUNTER0_CFG 0x00f7
#define regDAGB1_PERFCOUNTER0_CFG_BASE_IDX 0
#define regDAGB1_PERFCOUNTER1_CFG 0x00f8
#define regDAGB1_PERFCOUNTER1_CFG_BASE_IDX 0
#define regDAGB1_PERFCOUNTER2_CFG 0x00f9
#define regDAGB1_PERFCOUNTER2_CFG_BASE_IDX 0
#define regDAGB1_PERFCOUNTER_RSLT_CNTL 0x00fa
#define regDAGB1_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0
#define regDAGB1_L1TLB_REG_RW 0x00fb
#define regDAGB1_L1TLB_REG_RW_BASE_IDX 0
#define regDAGB1_RESERVE1 0x00fc
#define regDAGB1_RESERVE1_BASE_IDX 0
#define regDAGB1_RESERVE2 0x00fd
#define regDAGB1_RESERVE2_BASE_IDX 0
#define regDAGB1_RESERVE3 0x00fe
#define regDAGB1_RESERVE3_BASE_IDX 0
#define regDAGB1_RESERVE4 0x00ff
#define regDAGB1_RESERVE4_BASE_IDX 0
// addressBlock: mmhub_dagb_dagbdec2
// base address: 0x68400
#define regDAGB2_RDCLI0 0x0100
#define regDAGB2_RDCLI0_BASE_IDX 0
#define regDAGB2_RDCLI1 0x0101
#define regDAGB2_RDCLI1_BASE_IDX 0
#define regDAGB2_RDCLI2 0x0102
#define regDAGB2_RDCLI2_BASE_IDX 0
#define regDAGB2_RDCLI3 0x0103
#define regDAGB2_RDCLI3_BASE_IDX 0
#define regDAGB2_RDCLI4 0x0104
#define regDAGB2_RDCLI4_BASE_IDX 0
#define regDAGB2_RDCLI5 0x0105
#define regDAGB2_RDCLI5_BASE_IDX 0
#define regDAGB2_RDCLI6 0x0106
#define regDAGB2_RDCLI6_BASE_IDX 0
#define regDAGB2_RDCLI7 0x0107
#define regDAGB2_RDCLI7_BASE_IDX 0
#define regDAGB2_RDCLI8 0x0108
#define regDAGB2_RDCLI8_BASE_IDX 0
#define regDAGB2_RDCLI9 0x0109
#define regDAGB2_RDCLI9_BASE_IDX 0
#define regDAGB2_RDCLI10 0x010a
#define regDAGB2_RDCLI10_BASE_IDX 0
#define regDAGB2_RDCLI11 0x010b
#define regDAGB2_RDCLI11_BASE_IDX 0
#define regDAGB2_RDCLI12 0x010c
#define regDAGB2_RDCLI12_BASE_IDX 0
#define regDAGB2_RDCLI13 0x010d
#define regDAGB2_RDCLI13_BASE_IDX 0
#define regDAGB2_RDCLI14 0x010e
#define regDAGB2_RDCLI14_BASE_IDX 0
#define regDAGB2_RDCLI15 0x010f
#define regDAGB2_RDCLI15_BASE_IDX 0
#define regDAGB2_RD_CNTL 0x0110
#define regDAGB2_RD_CNTL_BASE_IDX 0
#define regDAGB2_RD_GMI_CNTL 0x0111
#define regDAGB2_RD_GMI_CNTL_BASE_IDX 0
#define regDAGB2_RD_ADDR_DAGB 0x0112
#define regDAGB2_RD_ADDR_DAGB_BASE_IDX 0
#define regDAGB2_RD_OUTPUT_DAGB_MAX_BURST 0x0113
#define regDAGB2_RD_OUTPUT_DAGB_MAX_BURST_BASE_IDX 0
#define regDAGB2_RD_OUTPUT_DAGB_LAZY_TIMER 0x0114
#define regDAGB2_RD_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 0
#define regDAGB2_RD_CGTT_CLK_CTRL 0x0115
#define regDAGB2_RD_CGTT_CLK_CTRL_BASE_IDX 0
#define regDAGB2_L1TLB_RD_CGTT_CLK_CTRL 0x0116
#define regDAGB2_L1TLB_RD_CGTT_CLK_CTRL_BASE_IDX 0
#define regDAGB2_ATCVM_RD_CGTT_CLK_CTRL 0x0117
#define regDAGB2_ATCVM_RD_CGTT_CLK_CTRL_BASE_IDX 0
#define regDAGB2_RD_ADDR_DAGB_MAX_BURST0 0x0118
#define regDAGB2_RD_ADDR_DAGB_MAX_BURST0_BASE_IDX 0
#define regDAGB2_RD_ADDR_DAGB_LAZY_TIMER0 0x0119
#define regDAGB2_RD_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 0
#define regDAGB2_RD_ADDR_DAGB_MAX_BURST1 0x011a
#define regDAGB2_RD_ADDR_DAGB_MAX_BURST1_BASE_IDX 0
#define regDAGB2_RD_ADDR_DAGB_LAZY_TIMER1 0x011b
#define regDAGB2_RD_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 0
#define regDAGB2_RD_VC0_CNTL 0x011c
#define regDAGB2_RD_VC0_CNTL_BASE_IDX 0
#define regDAGB2_RD_VC1_CNTL 0x011d
#define regDAGB2_RD_VC1_CNTL_BASE_IDX 0
#define regDAGB2_RD_VC2_CNTL 0x011e
#define regDAGB2_RD_VC2_CNTL_BASE_IDX 0
#define regDAGB2_RD_VC3_CNTL 0x011f
#define regDAGB2_RD_VC3_CNTL_BASE_IDX 0
#define regDAGB2_RD_VC4_CNTL 0x0120
#define regDAGB2_RD_VC4_CNTL_BASE_IDX 0
#define regDAGB2_RD_VC5_CNTL 0x0121
#define regDAGB2_RD_VC5_CNTL_BASE_IDX 0
#define regDAGB2_RD_VC6_CNTL 0x0122
#define regDAGB2_RD_VC6_CNTL_BASE_IDX 0
#define regDAGB2_RD_VC7_CNTL 0x0123
#define regDAGB2_RD_VC7_CNTL_BASE_IDX 0
#define regDAGB2_RD_CNTL_MISC 0x0124
#define regDAGB2_RD_CNTL_MISC_BASE_IDX 0
#define regDAGB2_RD_TLB_CREDIT 0x0125
#define regDAGB2_RD_TLB_CREDIT_BASE_IDX 0
#define regDAGB2_RD_RDRET_CREDIT_CNTL 0x0126
#define regDAGB2_RD_RDRET_CREDIT_CNTL_BASE_IDX 0
#define regDAGB2_RD_RDRET_CREDIT_CNTL2 0x0127
#define regDAGB2_RD_RDRET_CREDIT_CNTL2_BASE_IDX 0
#define regDAGB2_RDCLI_ASK_PENDING 0x0128
#define regDAGB2_RDCLI_ASK_PENDING_BASE_IDX 0
#define regDAGB2_RDCLI_GO_PENDING 0x0129
#define regDAGB2_RDCLI_GO_PENDING_BASE_IDX 0
#define regDAGB2_RDCLI_GBLSEND_PENDING 0x012a
#define regDAGB2_RDCLI_GBLSEND_PENDING_BASE_IDX 0
#define regDAGB2_RDCLI_TLB_PENDING 0x012b
#define regDAGB2_RDCLI_TLB_PENDING_BASE_IDX 0
#define regDAGB2_RDCLI_OARB_PENDING 0x012c
#define regDAGB2_RDCLI_OARB_PENDING_BASE_IDX 0
#define regDAGB2_RDCLI_OSD_PENDING 0x012d
#define regDAGB2_RDCLI_OSD_PENDING_BASE_IDX 0
#define regDAGB2_WRCLI0 0x012e
#define regDAGB2_WRCLI0_BASE_IDX 0
#define regDAGB2_WRCLI1 0x012f
#define regDAGB2_WRCLI1_BASE_IDX 0
#define regDAGB2_WRCLI2 0x0130
#define regDAGB2_WRCLI2_BASE_IDX 0
#define regDAGB2_WRCLI3 0x0131
#define regDAGB2_WRCLI3_BASE_IDX 0
#define regDAGB2_WRCLI4 0x0132
#define regDAGB2_WRCLI4_BASE_IDX 0
#define regDAGB2_WRCLI5 0x0133
#define regDAGB2_WRCLI5_BASE_IDX 0
#define regDAGB2_WRCLI6 0x0134
#define regDAGB2_WRCLI6_BASE_IDX 0
#define regDAGB2_WRCLI7 0x0135
#define regDAGB2_WRCLI7_BASE_IDX 0
#define regDAGB2_WRCLI8 0x0136
#define regDAGB2_WRCLI8_BASE_IDX 0
#define regDAGB2_WRCLI9 0x0137
#define regDAGB2_WRCLI9_BASE_IDX 0
#define regDAGB2_WRCLI10 0x0138
#define regDAGB2_WRCLI10_BASE_IDX 0
#define regDAGB2_WRCLI11 0x0139
#define regDAGB2_WRCLI11_BASE_IDX 0
#define regDAGB2_WRCLI12 0x013a
#define regDAGB2_WRCLI12_BASE_IDX 0
#define regDAGB2_WRCLI13 0x013b
#define regDAGB2_WRCLI13_BASE_IDX 0
#define regDAGB2_WRCLI14 0x013c
#define regDAGB2_WRCLI14_BASE_IDX 0
#define regDAGB2_WRCLI15 0x013d
#define regDAGB2_WRCLI15_BASE_IDX 0
#define regDAGB2_WR_CNTL 0x013e
#define regDAGB2_WR_CNTL_BASE_IDX 0
#define regDAGB2_WR_GMI_CNTL 0x013f
#define regDAGB2_WR_GMI_CNTL_BASE_IDX 0
#define regDAGB2_WR_ADDR_DAGB 0x0140
#define regDAGB2_WR_ADDR_DAGB_BASE_IDX 0
#define regDAGB2_WR_OUTPUT_DAGB_MAX_BURST 0x0141
#define regDAGB2_WR_OUTPUT_DAGB_MAX_BURST_BASE_IDX 0
#define regDAGB2_WR_OUTPUT_DAGB_LAZY_TIMER 0x0142
#define regDAGB2_WR_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 0
#define regDAGB2_WR_CGTT_CLK_CTRL 0x0143
#define regDAGB2_WR_CGTT_CLK_CTRL_BASE_IDX 0
#define regDAGB2_L1TLB_WR_CGTT_CLK_CTRL 0x0144
#define regDAGB2_L1TLB_WR_CGTT_CLK_CTRL_BASE_IDX 0
#define regDAGB2_ATCVM_WR_CGTT_CLK_CTRL 0x0145
#define regDAGB2_ATCVM_WR_CGTT_CLK_CTRL_BASE_IDX 0
#define regDAGB2_WR_ADDR_DAGB_MAX_BURST0 0x0146
#define regDAGB2_WR_ADDR_DAGB_MAX_BURST0_BASE_IDX 0
#define regDAGB2_WR_ADDR_DAGB_LAZY_TIMER0 0x0147
#define regDAGB2_WR_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 0
#define regDAGB2_WR_ADDR_DAGB_MAX_BURST1 0x0148
#define regDAGB2_WR_ADDR_DAGB_MAX_BURST1_BASE_IDX 0
#define regDAGB2_WR_ADDR_DAGB_LAZY_TIMER1 0x0149
#define regDAGB2_WR_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 0
#define regDAGB2_WR_DATA_DAGB 0x014a
#define regDAGB2_WR_DATA_DAGB_BASE_IDX 0
#define regDAGB2_WR_DATA_DAGB_MAX_BURST0 0x014b
#define regDAGB2_WR_DATA_DAGB_MAX_BURST0_BASE_IDX 0
#define regDAGB2_WR_DATA_DAGB_LAZY_TIMER0 0x014c
#define regDAGB2_WR_DATA_DAGB_LAZY_TIMER0_BASE_IDX 0
#define regDAGB2_WR_DATA_DAGB_MAX_BURST1 0x014d
#define regDAGB2_WR_DATA_DAGB_MAX_BURST1_BASE_IDX 0
#define regDAGB2_WR_DATA_DAGB_LAZY_TIMER1 0x014e
#define regDAGB2_WR_DATA_DAGB_LAZY_TIMER1_BASE_IDX 0
#define regDAGB2_WR_VC0_CNTL 0x014f
#define regDAGB2_WR_VC0_CNTL_BASE_IDX 0
#define regDAGB2_WR_VC1_CNTL 0x0150
#define regDAGB2_WR_VC1_CNTL_BASE_IDX 0
#define regDAGB2_WR_VC2_CNTL 0x0151
#define regDAGB2_WR_VC2_CNTL_BASE_IDX 0
#define regDAGB2_WR_VC3_CNTL 0x0152
#define regDAGB2_WR_VC3_CNTL_BASE_IDX 0
#define regDAGB2_WR_VC4_CNTL 0x0153
#define regDAGB2_WR_VC4_CNTL_BASE_IDX 0
#define regDAGB2_WR_VC5_CNTL 0x0154
#define regDAGB2_WR_VC5_CNTL_BASE_IDX 0
#define regDAGB2_WR_VC6_CNTL 0x0155
#define regDAGB2_WR_VC6_CNTL_BASE_IDX 0
#define regDAGB2_WR_VC7_CNTL 0x0156
#define regDAGB2_WR_VC7_CNTL_BASE_IDX 0
#define regDAGB2_WR_CNTL_MISC 0x0157
#define regDAGB2_WR_CNTL_MISC_BASE_IDX 0
#define regDAGB2_WR_TLB_CREDIT 0x0158
#define regDAGB2_WR_TLB_CREDIT_BASE_IDX 0
#define regDAGB2_WR_DATA_CREDIT 0x0159
#define regDAGB2_WR_DATA_CREDIT_BASE_IDX 0
#define regDAGB2_WR_MISC_CREDIT 0x015a
#define regDAGB2_WR_MISC_CREDIT_BASE_IDX 0
#define regDAGB2_WR_OSD_CREDIT_CNTL1 0x015b
#define regDAGB2_WR_OSD_CREDIT_CNTL1_BASE_IDX 0
#define regDAGB2_WR_OSD_CREDIT_CNTL2 0x015c
#define regDAGB2_WR_OSD_CREDIT_CNTL2_BASE_IDX 0
#define regDAGB2_WR_ATOMIC_FIFO_CREDIT_CNTL1 0x015d
#define regDAGB2_WR_ATOMIC_FIFO_CREDIT_CNTL1_BASE_IDX 0
#define regDAGB2_WRCLI_GPU_SNOOP_OVERRIDE 0x015e
#define regDAGB2_WRCLI_GPU_SNOOP_OVERRIDE_BASE_IDX 0
#define regDAGB2_WRCLI_GPU_SNOOP_OVERRIDE_VALUE 0x015f
#define regDAGB2_WRCLI_GPU_SNOOP_OVERRIDE_VALUE_BASE_IDX 0
#define regDAGB2_WRCLI_ASK_PENDING 0x0160
#define regDAGB2_WRCLI_ASK_PENDING_BASE_IDX 0
#define regDAGB2_WRCLI_GO_PENDING 0x0161
#define regDAGB2_WRCLI_GO_PENDING_BASE_IDX 0
#define regDAGB2_WRCLI_GBLSEND_PENDING 0x0162
#define regDAGB2_WRCLI_GBLSEND_PENDING_BASE_IDX 0
#define regDAGB2_WRCLI_TLB_PENDING 0x0163
#define regDAGB2_WRCLI_TLB_PENDING_BASE_IDX 0
#define regDAGB2_WRCLI_OARB_PENDING 0x0164
#define regDAGB2_WRCLI_OARB_PENDING_BASE_IDX 0
#define regDAGB2_WRCLI_OSD_PENDING 0x0165
#define regDAGB2_WRCLI_OSD_PENDING_BASE_IDX 0
#define regDAGB2_WRCLI_DBUS_ASK_PENDING 0x0166
#define regDAGB2_WRCLI_DBUS_ASK_PENDING_BASE_IDX 0
#define regDAGB2_WRCLI_DBUS_GO_PENDING 0x0167
#define regDAGB2_WRCLI_DBUS_GO_PENDING_BASE_IDX 0
#define regDAGB2_DAGB_DLY 0x0168
#define regDAGB2_DAGB_DLY_BASE_IDX 0
#define regDAGB2_CNTL_MISC 0x0169
#define regDAGB2_CNTL_MISC_BASE_IDX 0
#define regDAGB2_CNTL_MISC2 0x016a
#define regDAGB2_CNTL_MISC2_BASE_IDX 0
#define regDAGB2_FATAL_ERROR_CNTL 0x016b
#define regDAGB2_FATAL_ERROR_CNTL_BASE_IDX 0
#define regDAGB2_FATAL_ERROR_CLEAR 0x016c
#define regDAGB2_FATAL_ERROR_CLEAR_BASE_IDX 0
#define regDAGB2_FATAL_ERROR_STATUS0 0x016d
#define regDAGB2_FATAL_ERROR_STATUS0_BASE_IDX 0
#define regDAGB2_FATAL_ERROR_STATUS1 0x016e
#define regDAGB2_FATAL_ERROR_STATUS1_BASE_IDX 0
#define regDAGB2_FATAL_ERROR_STATUS2 0x016f
#define regDAGB2_FATAL_ERROR_STATUS2_BASE_IDX 0
#define regDAGB2_FATAL_ERROR_STATUS3 0x0170
#define regDAGB2_FATAL_ERROR_STATUS3_BASE_IDX 0
#define regDAGB2_FIFO_EMPTY 0x0171
#define regDAGB2_FIFO_EMPTY_BASE_IDX 0
#define regDAGB2_FIFO_FULL 0x0172
#define regDAGB2_FIFO_FULL_BASE_IDX 0
#define regDAGB2_WR_CREDITS_FULL 0x0173
#define regDAGB2_WR_CREDITS_FULL_BASE_IDX 0
#define regDAGB2_RD_CREDITS_FULL 0x0174
#define regDAGB2_RD_CREDITS_FULL_BASE_IDX 0
#define regDAGB2_PERFCOUNTER_LO 0x0175
#define regDAGB2_PERFCOUNTER_LO_BASE_IDX 0
#define regDAGB2_PERFCOUNTER_HI 0x0176
#define regDAGB2_PERFCOUNTER_HI_BASE_IDX 0
#define regDAGB2_PERFCOUNTER0_CFG 0x0177
#define regDAGB2_PERFCOUNTER0_CFG_BASE_IDX 0
#define regDAGB2_PERFCOUNTER1_CFG 0x0178
#define regDAGB2_PERFCOUNTER1_CFG_BASE_IDX 0
#define regDAGB2_PERFCOUNTER2_CFG 0x0179
#define regDAGB2_PERFCOUNTER2_CFG_BASE_IDX 0
#define regDAGB2_PERFCOUNTER_RSLT_CNTL 0x017a
#define regDAGB2_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0
#define regDAGB2_L1TLB_REG_RW 0x017b
#define regDAGB2_L1TLB_REG_RW_BASE_IDX 0
#define regDAGB2_RESERVE1 0x017c
#define regDAGB2_RESERVE1_BASE_IDX 0
#define regDAGB2_RESERVE2 0x017d
#define regDAGB2_RESERVE2_BASE_IDX 0
#define regDAGB2_RESERVE3 0x017e
#define regDAGB2_RESERVE3_BASE_IDX 0
#define regDAGB2_RESERVE4 0x017f
#define regDAGB2_RESERVE4_BASE_IDX 0
// addressBlock: mmhub_dagb_dagbdec3
// base address: 0x68600
#define regDAGB3_RDCLI0 0x0180
#define regDAGB3_RDCLI0_BASE_IDX 0
#define regDAGB3_RDCLI1 0x0181
#define regDAGB3_RDCLI1_BASE_IDX 0
#define regDAGB3_RDCLI2 0x0182
#define regDAGB3_RDCLI2_BASE_IDX 0
#define regDAGB3_RDCLI3 0x0183
#define regDAGB3_RDCLI3_BASE_IDX 0
#define regDAGB3_RDCLI4 0x0184
#define regDAGB3_RDCLI4_BASE_IDX 0
#define regDAGB3_RDCLI5 0x0185
#define regDAGB3_RDCLI5_BASE_IDX 0
#define regDAGB3_RDCLI6 0x0186
#define regDAGB3_RDCLI6_BASE_IDX 0
#define regDAGB3_RDCLI7 0x0187
#define regDAGB3_RDCLI7_BASE_IDX 0
#define regDAGB3_RDCLI8 0x0188
#define regDAGB3_RDCLI8_BASE_IDX 0
#define regDAGB3_RDCLI9 0x0189
#define regDAGB3_RDCLI9_BASE_IDX 0
#define regDAGB3_RDCLI10 0x018a
#define regDAGB3_RDCLI10_BASE_IDX 0
#define regDAGB3_RDCLI11 0x018b
#define regDAGB3_RDCLI11_BASE_IDX 0
#define regDAGB3_RDCLI12 0x018c
#define regDAGB3_RDCLI12_BASE_IDX 0
#define regDAGB3_RDCLI13 0x018d
#define regDAGB3_RDCLI13_BASE_IDX 0
#define regDAGB3_RDCLI14 0x018e
#define regDAGB3_RDCLI14_BASE_IDX 0
#define regDAGB3_RDCLI15 0x018f
#define regDAGB3_RDCLI15_BASE_IDX 0
#define regDAGB3_RD_CNTL 0x0190
#define regDAGB3_RD_CNTL_BASE_IDX 0
#define regDAGB3_RD_GMI_CNTL 0x0191
#define regDAGB3_RD_GMI_CNTL_BASE_IDX 0
#define regDAGB3_RD_ADDR_DAGB 0x0192
#define regDAGB3_RD_ADDR_DAGB_BASE_IDX 0
#define regDAGB3_RD_OUTPUT_DAGB_MAX_BURST 0x0193
#define regDAGB3_RD_OUTPUT_DAGB_MAX_BURST_BASE_IDX 0
#define regDAGB3_RD_OUTPUT_DAGB_LAZY_TIMER 0x0194
#define regDAGB3_RD_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 0
#define regDAGB3_RD_CGTT_CLK_CTRL 0x0195
#define regDAGB3_RD_CGTT_CLK_CTRL_BASE_IDX 0
#define regDAGB3_L1TLB_RD_CGTT_CLK_CTRL 0x0196
#define regDAGB3_L1TLB_RD_CGTT_CLK_CTRL_BASE_IDX 0
#define regDAGB3_ATCVM_RD_CGTT_CLK_CTRL 0x0197
#define regDAGB3_ATCVM_RD_CGTT_CLK_CTRL_BASE_IDX 0
#define regDAGB3_RD_ADDR_DAGB_MAX_BURST0 0x0198
#define regDAGB3_RD_ADDR_DAGB_MAX_BURST0_BASE_IDX 0
#define regDAGB3_RD_ADDR_DAGB_LAZY_TIMER0 0x0199
#define regDAGB3_RD_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 0
#define regDAGB3_RD_ADDR_DAGB_MAX_BURST1 0x019a
#define regDAGB3_RD_ADDR_DAGB_MAX_BURST1_BASE_IDX 0
#define regDAGB3_RD_ADDR_DAGB_LAZY_TIMER1 0x019b
#define regDAGB3_RD_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 0
#define regDAGB3_RD_VC0_CNTL 0x019c
#define regDAGB3_RD_VC0_CNTL_BASE_IDX 0
#define regDAGB3_RD_VC1_CNTL 0x019d
#define regDAGB3_RD_VC1_CNTL_BASE_IDX 0
#define regDAGB3_RD_VC2_CNTL 0x019e
#define regDAGB3_RD_VC2_CNTL_BASE_IDX 0
#define regDAGB3_RD_VC3_CNTL 0x019f
#define regDAGB3_RD_VC3_CNTL_BASE_IDX 0
#define regDAGB3_RD_VC4_CNTL 0x01a0
#define regDAGB3_RD_VC4_CNTL_BASE_IDX 0
#define regDAGB3_RD_VC5_CNTL 0x01a1
#define regDAGB3_RD_VC5_CNTL_BASE_IDX 0
#define regDAGB3_RD_VC6_CNTL 0x01a2
#define regDAGB3_RD_VC6_CNTL_BASE_IDX 0
#define regDAGB3_RD_VC7_CNTL 0x01a3
#define regDAGB3_RD_VC7_CNTL_BASE_IDX 0
#define regDAGB3_RD_CNTL_MISC 0x01a4
#define regDAGB3_RD_CNTL_MISC_BASE_IDX 0
#define regDAGB3_RD_TLB_CREDIT 0x01a5
#define regDAGB3_RD_TLB_CREDIT_BASE_IDX 0
#define regDAGB3_RD_RDRET_CREDIT_CNTL 0x01a6
#define regDAGB3_RD_RDRET_CREDIT_CNTL_BASE_IDX 0
#define regDAGB3_RD_RDRET_CREDIT_CNTL2 0x01a7
#define regDAGB3_RD_RDRET_CREDIT_CNTL2_BASE_IDX 0
#define regDAGB3_RDCLI_ASK_PENDING 0x01a8
#define regDAGB3_RDCLI_ASK_PENDING_BASE_IDX 0
#define regDAGB3_RDCLI_GO_PENDING 0x01a9
#define regDAGB3_RDCLI_GO_PENDING_BASE_IDX 0
#define regDAGB3_RDCLI_GBLSEND_PENDING 0x01aa
#define regDAGB3_RDCLI_GBLSEND_PENDING_BASE_IDX 0
#define regDAGB3_RDCLI_TLB_PENDING 0x01ab
#define regDAGB3_RDCLI_TLB_PENDING_BASE_IDX 0
#define regDAGB3_RDCLI_OARB_PENDING 0x01ac
#define regDAGB3_RDCLI_OARB_PENDING_BASE_IDX 0
#define regDAGB3_RDCLI_OSD_PENDING 0x01ad
#define regDAGB3_RDCLI_OSD_PENDING_BASE_IDX 0
#define regDAGB3_WRCLI0 0x01ae
#define regDAGB3_WRCLI0_BASE_IDX 0
#define regDAGB3_WRCLI1 0x01af
#define regDAGB3_WRCLI1_BASE_IDX 0
#define regDAGB3_WRCLI2 0x01b0
#define regDAGB3_WRCLI2_BASE_IDX 0
#define regDAGB3_WRCLI3 0x01b1
#define regDAGB3_WRCLI3_BASE_IDX 0
#define regDAGB3_WRCLI4 0x01b2
#define regDAGB3_WRCLI4_BASE_IDX 0
#define regDAGB3_WRCLI5 0x01b3
#define regDAGB3_WRCLI5_BASE_IDX 0
#define regDAGB3_WRCLI6 0x01b4
#define regDAGB3_WRCLI6_BASE_IDX 0
#define regDAGB3_WRCLI7 0x01b5
#define regDAGB3_WRCLI7_BASE_IDX 0
#define regDAGB3_WRCLI8 0x01b6
#define regDAGB3_WRCLI8_BASE_IDX 0
#define regDAGB3_WRCLI9 0x01b7
#define regDAGB3_WRCLI9_BASE_IDX 0
#define regDAGB3_WRCLI10 0x01b8
#define regDAGB3_WRCLI10_BASE_IDX 0
#define regDAGB3_WRCLI11 0x01b9
#define regDAGB3_WRCLI11_BASE_IDX 0
#define regDAGB3_WRCLI12 0x01ba
#define regDAGB3_WRCLI12_BASE_IDX 0
#define regDAGB3_WRCLI13 0x01bb
#define regDAGB3_WRCLI13_BASE_IDX 0
#define regDAGB3_WRCLI14 0x01bc
#define regDAGB3_WRCLI14_BASE_IDX 0
#define regDAGB3_WRCLI15 0x01bd
#define regDAGB3_WRCLI15_BASE_IDX 0
#define regDAGB3_WR_CNTL 0x01be
#define regDAGB3_WR_CNTL_BASE_IDX 0
#define regDAGB3_WR_GMI_CNTL 0x01bf
#define regDAGB3_WR_GMI_CNTL_BASE_IDX 0
#define regDAGB3_WR_ADDR_DAGB 0x01c0
#define regDAGB3_WR_ADDR_DAGB_BASE_IDX 0
#define regDAGB3_WR_OUTPUT_DAGB_MAX_BURST 0x01c1
#define regDAGB3_WR_OUTPUT_DAGB_MAX_BURST_BASE_IDX 0
#define regDAGB3_WR_OUTPUT_DAGB_LAZY_TIMER 0x01c2
#define regDAGB3_WR_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 0
#define regDAGB3_WR_CGTT_CLK_CTRL 0x01c3
#define regDAGB3_WR_CGTT_CLK_CTRL_BASE_IDX 0
#define regDAGB3_L1TLB_WR_CGTT_CLK_CTRL 0x01c4
#define regDAGB3_L1TLB_WR_CGTT_CLK_CTRL_BASE_IDX 0
#define regDAGB3_ATCVM_WR_CGTT_CLK_CTRL 0x01c5
#define regDAGB3_ATCVM_WR_CGTT_CLK_CTRL_BASE_IDX 0
#define regDAGB3_WR_ADDR_DAGB_MAX_BURST0 0x01c6
#define regDAGB3_WR_ADDR_DAGB_MAX_BURST0_BASE_IDX 0
#define regDAGB3_WR_ADDR_DAGB_LAZY_TIMER0 0x01c7
#define regDAGB3_WR_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 0
#define regDAGB3_WR_ADDR_DAGB_MAX_BURST1 0x01c8
#define regDAGB3_WR_ADDR_DAGB_MAX_BURST1_BASE_IDX 0
#define regDAGB3_WR_ADDR_DAGB_LAZY_TIMER1 0x01c9
#define regDAGB3_WR_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 0
#define regDAGB3_WR_DATA_DAGB 0x01ca
#define regDAGB3_WR_DATA_DAGB_BASE_IDX 0
#define regDAGB3_WR_DATA_DAGB_MAX_BURST0 0x01cb
#define regDAGB3_WR_DATA_DAGB_MAX_BURST0_BASE_IDX 0
#define regDAGB3_WR_DATA_DAGB_LAZY_TIMER0 0x01cc
#define regDAGB3_WR_DATA_DAGB_LAZY_TIMER0_BASE_IDX 0
#define regDAGB3_WR_DATA_DAGB_MAX_BURST1 0x01cd
#define regDAGB3_WR_DATA_DAGB_MAX_BURST1_BASE_IDX 0
#define regDAGB3_WR_DATA_DAGB_LAZY_TIMER1 0x01ce
#define regDAGB3_WR_DATA_DAGB_LAZY_TIMER1_BASE_IDX 0
#define regDAGB3_WR_VC0_CNTL 0x01cf
#define regDAGB3_WR_VC0_CNTL_BASE_IDX 0
#define regDAGB3_WR_VC1_CNTL 0x01d0
#define regDAGB3_WR_VC1_CNTL_BASE_IDX 0
#define regDAGB3_WR_VC2_CNTL 0x01d1
#define regDAGB3_WR_VC2_CNTL_BASE_IDX 0
#define regDAGB3_WR_VC3_CNTL 0x01d2
#define regDAGB3_WR_VC3_CNTL_BASE_IDX 0
#define regDAGB3_WR_VC4_CNTL 0x01d3
#define regDAGB3_WR_VC4_CNTL_BASE_IDX 0
#define regDAGB3_WR_VC5_CNTL 0x01d4
#define regDAGB3_WR_VC5_CNTL_BASE_IDX 0
#define regDAGB3_WR_VC6_CNTL 0x01d5
#define regDAGB3_WR_VC6_CNTL_BASE_IDX 0
#define regDAGB3_WR_VC7_CNTL 0x01d6
#define regDAGB3_WR_VC7_CNTL_BASE_IDX 0
#define regDAGB3_WR_CNTL_MISC 0x01d7
#define regDAGB3_WR_CNTL_MISC_BASE_IDX 0
#define regDAGB3_WR_TLB_CREDIT 0x01d8
#define regDAGB3_WR_TLB_CREDIT_BASE_IDX 0
#define regDAGB3_WR_DATA_CREDIT 0x01d9
#define regDAGB3_WR_DATA_CREDIT_BASE_IDX 0
#define regDAGB3_WR_MISC_CREDIT 0x01da
#define regDAGB3_WR_MISC_CREDIT_BASE_IDX 0
#define regDAGB3_WR_OSD_CREDIT_CNTL1 0x01db
#define regDAGB3_WR_OSD_CREDIT_CNTL1_BASE_IDX 0
#define regDAGB3_WR_OSD_CREDIT_CNTL2 0x01dc
#define regDAGB3_WR_OSD_CREDIT_CNTL2_BASE_IDX 0
#define regDAGB3_WR_ATOMIC_FIFO_CREDIT_CNTL1 0x01dd
#define regDAGB3_WR_ATOMIC_FIFO_CREDIT_CNTL1_BASE_IDX 0
#define regDAGB3_WRCLI_GPU_SNOOP_OVERRIDE 0x01de
#define regDAGB3_WRCLI_GPU_SNOOP_OVERRIDE_BASE_IDX 0
#define regDAGB3_WRCLI_GPU_SNOOP_OVERRIDE_VALUE 0x01df
#define regDAGB3_WRCLI_GPU_SNOOP_OVERRIDE_VALUE_BASE_IDX 0
#define regDAGB3_WRCLI_ASK_PENDING 0x01e0
#define regDAGB3_WRCLI_ASK_PENDING_BASE_IDX 0
#define regDAGB3_WRCLI_GO_PENDING 0x01e1
#define regDAGB3_WRCLI_GO_PENDING_BASE_IDX 0
#define regDAGB3_WRCLI_GBLSEND_PENDING 0x01e2
#define regDAGB3_WRCLI_GBLSEND_PENDING_BASE_IDX 0
#define regDAGB3_WRCLI_TLB_PENDING 0x01e3
#define regDAGB3_WRCLI_TLB_PENDING_BASE_IDX 0
#define regDAGB3_WRCLI_OARB_PENDING 0x01e4
#define regDAGB3_WRCLI_OARB_PENDING_BASE_IDX 0
#define regDAGB3_WRCLI_OSD_PENDING 0x01e5
#define regDAGB3_WRCLI_OSD_PENDING_BASE_IDX 0
#define regDAGB3_WRCLI_DBUS_ASK_PENDING 0x01e6
#define regDAGB3_WRCLI_DBUS_ASK_PENDING_BASE_IDX 0
#define regDAGB3_WRCLI_DBUS_GO_PENDING 0x01e7
#define regDAGB3_WRCLI_DBUS_GO_PENDING_BASE_IDX 0
#define regDAGB3_DAGB_DLY 0x01e8
#define regDAGB3_DAGB_DLY_BASE_IDX 0
#define regDAGB3_CNTL_MISC 0x01e9
#define regDAGB3_CNTL_MISC_BASE_IDX 0
#define regDAGB3_CNTL_MISC2 0x01ea
#define regDAGB3_CNTL_MISC2_BASE_IDX 0
#define regDAGB3_FATAL_ERROR_CNTL 0x01eb
#define regDAGB3_FATAL_ERROR_CNTL_BASE_IDX 0
#define regDAGB3_FATAL_ERROR_CLEAR 0x01ec
#define regDAGB3_FATAL_ERROR_CLEAR_BASE_IDX 0
#define regDAGB3_FATAL_ERROR_STATUS0 0x01ed
#define regDAGB3_FATAL_ERROR_STATUS0_BASE_IDX 0
#define regDAGB3_FATAL_ERROR_STATUS1 0x01ee
#define regDAGB3_FATAL_ERROR_STATUS1_BASE_IDX 0
#define regDAGB3_FATAL_ERROR_STATUS2 0x01ef
#define regDAGB3_FATAL_ERROR_STATUS2_BASE_IDX 0
#define regDAGB3_FATAL_ERROR_STATUS3 0x01f0
#define regDAGB3_FATAL_ERROR_STATUS3_BASE_IDX 0
#define regDAGB3_FIFO_EMPTY 0x01f1
#define regDAGB3_FIFO_EMPTY_BASE_IDX 0
#define regDAGB3_FIFO_FULL 0x01f2
#define regDAGB3_FIFO_FULL_BASE_IDX 0
#define regDAGB3_WR_CREDITS_FULL 0x01f3
#define regDAGB3_WR_CREDITS_FULL_BASE_IDX 0
#define regDAGB3_RD_CREDITS_FULL 0x01f4
#define regDAGB3_RD_CREDITS_FULL_BASE_IDX 0
#define regDAGB3_PERFCOUNTER_LO 0x01f5
#define regDAGB3_PERFCOUNTER_LO_BASE_IDX 0
#define regDAGB3_PERFCOUNTER_HI 0x01f6
#define regDAGB3_PERFCOUNTER_HI_BASE_IDX 0
#define regDAGB3_PERFCOUNTER0_CFG 0x01f7
#define regDAGB3_PERFCOUNTER0_CFG_BASE_IDX 0
#define regDAGB3_PERFCOUNTER1_CFG 0x01f8
#define regDAGB3_PERFCOUNTER1_CFG_BASE_IDX 0
#define regDAGB3_PERFCOUNTER2_CFG 0x01f9
#define regDAGB3_PERFCOUNTER2_CFG_BASE_IDX 0
#define regDAGB3_PERFCOUNTER_RSLT_CNTL 0x01fa
#define regDAGB3_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0
#define regDAGB3_L1TLB_REG_RW 0x01fb
#define regDAGB3_L1TLB_REG_RW_BASE_IDX 0
#define regDAGB3_RESERVE1 0x01fc
#define regDAGB3_RESERVE1_BASE_IDX 0
#define regDAGB3_RESERVE2 0x01fd
#define regDAGB3_RESERVE2_BASE_IDX 0
#define regDAGB3_RESERVE3 0x01fe
#define regDAGB3_RESERVE3_BASE_IDX 0
#define regDAGB3_RESERVE4 0x01ff
#define regDAGB3_RESERVE4_BASE_IDX 0
// addressBlock: mmhub_dagb_dagbdec4
// base address: 0x68800
#define regDAGB4_RDCLI0 0x0200
#define regDAGB4_RDCLI0_BASE_IDX 0
#define regDAGB4_RDCLI1 0x0201
#define regDAGB4_RDCLI1_BASE_IDX 0
#define regDAGB4_RDCLI2 0x0202
#define regDAGB4_RDCLI2_BASE_IDX 0
#define regDAGB4_RDCLI3 0x0203
#define regDAGB4_RDCLI3_BASE_IDX 0
#define regDAGB4_RDCLI4 0x0204
#define regDAGB4_RDCLI4_BASE_IDX 0
#define regDAGB4_RDCLI5 0x0205
#define regDAGB4_RDCLI5_BASE_IDX 0
#define regDAGB4_RDCLI6 0x0206
#define regDAGB4_RDCLI6_BASE_IDX 0
#define regDAGB4_RDCLI7 0x0207
#define regDAGB4_RDCLI7_BASE_IDX 0
#define regDAGB4_RDCLI8 0x0208
#define regDAGB4_RDCLI8_BASE_IDX 0
#define regDAGB4_RDCLI9 0x0209
#define regDAGB4_RDCLI9_BASE_IDX 0
#define regDAGB4_RDCLI10 0x020a
#define regDAGB4_RDCLI10_BASE_IDX 0
#define regDAGB4_RDCLI11 0x020b
#define regDAGB4_RDCLI11_BASE_IDX 0
#define regDAGB4_RDCLI12 0x020c
#define regDAGB4_RDCLI12_BASE_IDX 0
#define regDAGB4_RDCLI13 0x020d
#define regDAGB4_RDCLI13_BASE_IDX 0
#define regDAGB4_RDCLI14 0x020e
#define regDAGB4_RDCLI14_BASE_IDX 0
#define regDAGB4_RDCLI15 0x020f
#define regDAGB4_RDCLI15_BASE_IDX 0
#define regDAGB4_RD_CNTL 0x0210
#define regDAGB4_RD_CNTL_BASE_IDX 0
#define regDAGB4_RD_GMI_CNTL 0x0211
#define regDAGB4_RD_GMI_CNTL_BASE_IDX 0
#define regDAGB4_RD_ADDR_DAGB 0x0212
#define regDAGB4_RD_ADDR_DAGB_BASE_IDX 0
#define regDAGB4_RD_OUTPUT_DAGB_MAX_BURST 0x0213
#define regDAGB4_RD_OUTPUT_DAGB_MAX_BURST_BASE_IDX 0
#define regDAGB4_RD_OUTPUT_DAGB_LAZY_TIMER 0x0214
#define regDAGB4_RD_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 0
#define regDAGB4_RD_CGTT_CLK_CTRL 0x0215
#define regDAGB4_RD_CGTT_CLK_CTRL_BASE_IDX 0
#define regDAGB4_L1TLB_RD_CGTT_CLK_CTRL 0x0216
#define regDAGB4_L1TLB_RD_CGTT_CLK_CTRL_BASE_IDX 0
#define regDAGB4_ATCVM_RD_CGTT_CLK_CTRL 0x0217
#define regDAGB4_ATCVM_RD_CGTT_CLK_CTRL_BASE_IDX 0
#define regDAGB4_RD_ADDR_DAGB_MAX_BURST0 0x0218
#define regDAGB4_RD_ADDR_DAGB_MAX_BURST0_BASE_IDX 0
#define regDAGB4_RD_ADDR_DAGB_LAZY_TIMER0 0x0219
#define regDAGB4_RD_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 0
#define regDAGB4_RD_ADDR_DAGB_MAX_BURST1 0x021a
#define regDAGB4_RD_ADDR_DAGB_MAX_BURST1_BASE_IDX 0
#define regDAGB4_RD_ADDR_DAGB_LAZY_TIMER1 0x021b
#define regDAGB4_RD_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 0
#define regDAGB4_RD_VC0_CNTL 0x021c
#define regDAGB4_RD_VC0_CNTL_BASE_IDX 0
#define regDAGB4_RD_VC1_CNTL 0x021d
#define regDAGB4_RD_VC1_CNTL_BASE_IDX 0
#define regDAGB4_RD_VC2_CNTL 0x021e
#define regDAGB4_RD_VC2_CNTL_BASE_IDX 0
#define regDAGB4_RD_VC3_CNTL 0x021f
#define regDAGB4_RD_VC3_CNTL_BASE_IDX 0
#define regDAGB4_RD_VC4_CNTL 0x0220
#define regDAGB4_RD_VC4_CNTL_BASE_IDX 0
#define regDAGB4_RD_VC5_CNTL 0x0221
#define regDAGB4_RD_VC5_CNTL_BASE_IDX 0
#define regDAGB4_RD_VC6_CNTL 0x0222
#define regDAGB4_RD_VC6_CNTL_BASE_IDX 0
#define regDAGB4_RD_VC7_CNTL 0x0223
#define regDAGB4_RD_VC7_CNTL_BASE_IDX 0
#define regDAGB4_RD_CNTL_MISC 0x0224
#define regDAGB4_RD_CNTL_MISC_BASE_IDX 0
#define regDAGB4_RD_TLB_CREDIT 0x0225
#define regDAGB4_RD_TLB_CREDIT_BASE_IDX 0
#define regDAGB4_RD_RDRET_CREDIT_CNTL 0x0226
#define regDAGB4_RD_RDRET_CREDIT_CNTL_BASE_IDX 0
#define regDAGB4_RD_RDRET_CREDIT_CNTL2 0x0227
#define regDAGB4_RD_RDRET_CREDIT_CNTL2_BASE_IDX 0
#define regDAGB4_RDCLI_ASK_PENDING 0x0228
#define regDAGB4_RDCLI_ASK_PENDING_BASE_IDX 0
#define regDAGB4_RDCLI_GO_PENDING 0x0229
#define regDAGB4_RDCLI_GO_PENDING_BASE_IDX 0
#define regDAGB4_RDCLI_GBLSEND_PENDING 0x022a
#define regDAGB4_RDCLI_GBLSEND_PENDING_BASE_IDX 0
#define regDAGB4_RDCLI_TLB_PENDING 0x022b
#define regDAGB4_RDCLI_TLB_PENDING_BASE_IDX 0
#define regDAGB4_RDCLI_OARB_PENDING 0x022c
#define regDAGB4_RDCLI_OARB_PENDING_BASE_IDX 0
#define regDAGB4_RDCLI_OSD_PENDING 0x022d
#define regDAGB4_RDCLI_OSD_PENDING_BASE_IDX 0
#define regDAGB4_WRCLI0 0x022e
#define regDAGB4_WRCLI0_BASE_IDX 0
#define regDAGB4_WRCLI1 0x022f
#define regDAGB4_WRCLI1_BASE_IDX 0
#define regDAGB4_WRCLI2 0x0230
#define regDAGB4_WRCLI2_BASE_IDX 0
#define regDAGB4_WRCLI3 0x0231
#define regDAGB4_WRCLI3_BASE_IDX 0
#define regDAGB4_WRCLI4 0x0232
#define regDAGB4_WRCLI4_BASE_IDX 0
#define regDAGB4_WRCLI5 0x0233
#define regDAGB4_WRCLI5_BASE_IDX 0
#define regDAGB4_WRCLI6 0x0234
#define regDAGB4_WRCLI6_BASE_IDX 0
#define regDAGB4_WRCLI7 0x0235
#define regDAGB4_WRCLI7_BASE_IDX 0
#define regDAGB4_WRCLI8 0x0236
#define regDAGB4_WRCLI8_BASE_IDX 0
#define regDAGB4_WRCLI9 0x0237
#define regDAGB4_WRCLI9_BASE_IDX 0
#define regDAGB4_WRCLI10 0x0238
#define regDAGB4_WRCLI10_BASE_IDX 0
#define regDAGB4_WRCLI11 0x0239
#define regDAGB4_WRCLI11_BASE_IDX 0
#define regDAGB4_WRCLI12 0x023a
#define regDAGB4_WRCLI12_BASE_IDX 0
#define regDAGB4_WRCLI13 0x023b
#define regDAGB4_WRCLI13_BASE_IDX 0
#define regDAGB4_WRCLI14 0x023c
#define regDAGB4_WRCLI14_BASE_IDX 0
#define regDAGB4_WRCLI15 0x023d
#define regDAGB4_WRCLI15_BASE_IDX 0
#define regDAGB4_WR_CNTL 0x023e
#define regDAGB4_WR_CNTL_BASE_IDX 0
#define regDAGB4_WR_GMI_CNTL 0x023f
#define regDAGB4_WR_GMI_CNTL_BASE_IDX 0
#define regDAGB4_WR_ADDR_DAGB 0x0240
#define regDAGB4_WR_ADDR_DAGB_BASE_IDX 0
#define regDAGB4_WR_OUTPUT_DAGB_MAX_BURST 0x0241
#define regDAGB4_WR_OUTPUT_DAGB_MAX_BURST_BASE_IDX 0
#define regDAGB4_WR_OUTPUT_DAGB_LAZY_TIMER 0x0242
#define regDAGB4_WR_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 0
#define regDAGB4_WR_CGTT_CLK_CTRL 0x0243
#define regDAGB4_WR_CGTT_CLK_CTRL_BASE_IDX 0
#define regDAGB4_L1TLB_WR_CGTT_CLK_CTRL 0x0244
#define regDAGB4_L1TLB_WR_CGTT_CLK_CTRL_BASE_IDX 0
#define regDAGB4_ATCVM_WR_CGTT_CLK_CTRL 0x0245
#define regDAGB4_ATCVM_WR_CGTT_CLK_CTRL_BASE_IDX 0
#define regDAGB4_WR_ADDR_DAGB_MAX_BURST0 0x0246
#define regDAGB4_WR_ADDR_DAGB_MAX_BURST0_BASE_IDX 0
#define regDAGB4_WR_ADDR_DAGB_LAZY_TIMER0 0x0247
#define regDAGB4_WR_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 0
#define regDAGB4_WR_ADDR_DAGB_MAX_BURST1 0x0248
#define regDAGB4_WR_ADDR_DAGB_MAX_BURST1_BASE_IDX 0
#define regDAGB4_WR_ADDR_DAGB_LAZY_TIMER1 0x0249
#define regDAGB4_WR_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 0
#define regDAGB4_WR_DATA_DAGB 0x024a
#define regDAGB4_WR_DATA_DAGB_BASE_IDX 0
#define regDAGB4_WR_DATA_DAGB_MAX_BURST0 0x024b
#define regDAGB4_WR_DATA_DAGB_MAX_BURST0_BASE_IDX 0
#define regDAGB4_WR_DATA_DAGB_LAZY_TIMER0 0x024c
#define regDAGB4_WR_DATA_DAGB_LAZY_TIMER0_BASE_IDX 0
#define regDAGB4_WR_DATA_DAGB_MAX_BURST1 0x024d
#define regDAGB4_WR_DATA_DAGB_MAX_BURST1_BASE_IDX 0
#define regDAGB4_WR_DATA_DAGB_LAZY_TIMER1 0x024e
#define regDAGB4_WR_DATA_DAGB_LAZY_TIMER1_BASE_IDX 0
#define regDAGB4_WR_VC0_CNTL 0x024f
#define regDAGB4_WR_VC0_CNTL_BASE_IDX 0
#define regDAGB4_WR_VC1_CNTL 0x0250
#define regDAGB4_WR_VC1_CNTL_BASE_IDX 0
#define regDAGB4_WR_VC2_CNTL 0x0251
#define regDAGB4_WR_VC2_CNTL_BASE_IDX 0
#define regDAGB4_WR_VC3_CNTL 0x0252
#define regDAGB4_WR_VC3_CNTL_BASE_IDX 0
#define regDAGB4_WR_VC4_CNTL 0x0253
#define regDAGB4_WR_VC4_CNTL_BASE_IDX 0
#define regDAGB4_WR_VC5_CNTL 0x0254
#define regDAGB4_WR_VC5_CNTL_BASE_IDX 0
#define regDAGB4_WR_VC6_CNTL 0x0255
#define regDAGB4_WR_VC6_CNTL_BASE_IDX 0
#define regDAGB4_WR_VC7_CNTL 0x0256
#define regDAGB4_WR_VC7_CNTL_BASE_IDX 0
#define regDAGB4_WR_CNTL_MISC 0x0257
#define regDAGB4_WR_CNTL_MISC_BASE_IDX 0
#define regDAGB4_WR_TLB_CREDIT 0x0258
#define regDAGB4_WR_TLB_CREDIT_BASE_IDX 0
#define regDAGB4_WR_DATA_CREDIT 0x0259
#define regDAGB4_WR_DATA_CREDIT_BASE_IDX 0
#define regDAGB4_WR_MISC_CREDIT 0x025a
#define regDAGB4_WR_MISC_CREDIT_BASE_IDX 0
#define regDAGB4_WR_OSD_CREDIT_CNTL1 0x025b
#define regDAGB4_WR_OSD_CREDIT_CNTL1_BASE_IDX 0
#define regDAGB4_WR_OSD_CREDIT_CNTL2 0x025c
#define regDAGB4_WR_OSD_CREDIT_CNTL2_BASE_IDX 0
#define regDAGB4_WR_ATOMIC_FIFO_CREDIT_CNTL1 0x025d
#define regDAGB4_WR_ATOMIC_FIFO_CREDIT_CNTL1_BASE_IDX 0
#define regDAGB4_WRCLI_GPU_SNOOP_OVERRIDE 0x025e
#define regDAGB4_WRCLI_GPU_SNOOP_OVERRIDE_BASE_IDX 0
#define regDAGB4_WRCLI_GPU_SNOOP_OVERRIDE_VALUE 0x025f
#define regDAGB4_WRCLI_GPU_SNOOP_OVERRIDE_VALUE_BASE_IDX 0
#define regDAGB4_WRCLI_ASK_PENDING 0x0260
#define regDAGB4_WRCLI_ASK_PENDING_BASE_IDX 0
#define regDAGB4_WRCLI_GO_PENDING 0x0261
#define regDAGB4_WRCLI_GO_PENDING_BASE_IDX 0
#define regDAGB4_WRCLI_GBLSEND_PENDING 0x0262
#define regDAGB4_WRCLI_GBLSEND_PENDING_BASE_IDX 0
#define regDAGB4_WRCLI_TLB_PENDING 0x0263
#define regDAGB4_WRCLI_TLB_PENDING_BASE_IDX 0
#define regDAGB4_WRCLI_OARB_PENDING 0x0264
#define regDAGB4_WRCLI_OARB_PENDING_BASE_IDX 0
#define regDAGB4_WRCLI_OSD_PENDING 0x0265
#define regDAGB4_WRCLI_OSD_PENDING_BASE_IDX 0
#define regDAGB4_WRCLI_DBUS_ASK_PENDING 0x0266
#define regDAGB4_WRCLI_DBUS_ASK_PENDING_BASE_IDX 0
#define regDAGB4_WRCLI_DBUS_GO_PENDING 0x0267
#define regDAGB4_WRCLI_DBUS_GO_PENDING_BASE_IDX 0
#define regDAGB4_DAGB_DLY 0x0268
#define regDAGB4_DAGB_DLY_BASE_IDX 0
#define regDAGB4_CNTL_MISC 0x0269
#define regDAGB4_CNTL_MISC_BASE_IDX 0
#define regDAGB4_CNTL_MISC2 0x026a
#define regDAGB4_CNTL_MISC2_BASE_IDX 0
#define regDAGB4_FATAL_ERROR_CNTL 0x026b
#define regDAGB4_FATAL_ERROR_CNTL_BASE_IDX 0
#define regDAGB4_FATAL_ERROR_CLEAR 0x026c
#define regDAGB4_FATAL_ERROR_CLEAR_BASE_IDX 0
#define regDAGB4_FATAL_ERROR_STATUS0 0x026d
#define regDAGB4_FATAL_ERROR_STATUS0_BASE_IDX 0
#define regDAGB4_FATAL_ERROR_STATUS1 0x026e
#define regDAGB4_FATAL_ERROR_STATUS1_BASE_IDX 0
#define regDAGB4_FATAL_ERROR_STATUS2 0x026f
#define regDAGB4_FATAL_ERROR_STATUS2_BASE_IDX 0
#define regDAGB4_FATAL_ERROR_STATUS3 0x0270
#define regDAGB4_FATAL_ERROR_STATUS3_BASE_IDX 0
#define regDAGB4_FIFO_EMPTY 0x0271
#define regDAGB4_FIFO_EMPTY_BASE_IDX 0
#define regDAGB4_FIFO_FULL 0x0272
#define regDAGB4_FIFO_FULL_BASE_IDX 0
#define regDAGB4_WR_CREDITS_FULL 0x0273
#define regDAGB4_WR_CREDITS_FULL_BASE_IDX 0
#define regDAGB4_RD_CREDITS_FULL 0x0274
#define regDAGB4_RD_CREDITS_FULL_BASE_IDX 0
#define regDAGB4_PERFCOUNTER_LO 0x0275
#define regDAGB4_PERFCOUNTER_LO_BASE_IDX 0
#define regDAGB4_PERFCOUNTER_HI 0x0276
#define regDAGB4_PERFCOUNTER_HI_BASE_IDX 0
#define regDAGB4_PERFCOUNTER0_CFG 0x0277
#define regDAGB4_PERFCOUNTER0_CFG_BASE_IDX 0
#define regDAGB4_PERFCOUNTER1_CFG 0x0278
#define regDAGB4_PERFCOUNTER1_CFG_BASE_IDX 0
#define regDAGB4_PERFCOUNTER2_CFG 0x0279
#define regDAGB4_PERFCOUNTER2_CFG_BASE_IDX 0
#define regDAGB4_PERFCOUNTER_RSLT_CNTL 0x027a
#define regDAGB4_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0
#define regDAGB4_L1TLB_REG_RW 0x027b
#define regDAGB4_L1TLB_REG_RW_BASE_IDX 0
#define regDAGB4_RESERVE1 0x027c
#define regDAGB4_RESERVE1_BASE_IDX 0
#define regDAGB4_RESERVE2 0x027d
#define regDAGB4_RESERVE2_BASE_IDX 0
#define regDAGB4_RESERVE3 0x027e
#define regDAGB4_RESERVE3_BASE_IDX 0
#define regDAGB4_RESERVE4 0x027f
#define regDAGB4_RESERVE4_BASE_IDX 0
// addressBlock: mmhub_dagb_dagbdec5
// base address: 0x68a00
#define regDAGB5_RDCLI0 0x0280
#define regDAGB5_RDCLI0_BASE_IDX 0
#define regDAGB5_RDCLI1 0x0281
#define regDAGB5_RDCLI1_BASE_IDX 0
#define regDAGB5_RDCLI2 0x0282
#define regDAGB5_RDCLI2_BASE_IDX 0
#define regDAGB5_RDCLI3 0x0283
#define regDAGB5_RDCLI3_BASE_IDX 0
#define regDAGB5_RDCLI4 0x0284
#define regDAGB5_RDCLI4_BASE_IDX 0
#define regDAGB5_RDCLI5 0x0285
#define regDAGB5_RDCLI5_BASE_IDX 0
#define regDAGB5_RDCLI6 0x0286
#define regDAGB5_RDCLI6_BASE_IDX 0
#define regDAGB5_RDCLI7 0x0287
#define regDAGB5_RDCLI7_BASE_IDX 0
#define regDAGB5_RDCLI8 0x0288
#define regDAGB5_RDCLI8_BASE_IDX 0
#define regDAGB5_RDCLI9 0x0289
#define regDAGB5_RDCLI9_BASE_IDX 0
#define regDAGB5_RDCLI10 0x028a
#define regDAGB5_RDCLI10_BASE_IDX 0
#define regDAGB5_RDCLI11 0x028b
#define regDAGB5_RDCLI11_BASE_IDX 0
#define regDAGB5_RDCLI12 0x028c
#define regDAGB5_RDCLI12_BASE_IDX 0
#define regDAGB5_RDCLI13 0x028d
#define regDAGB5_RDCLI13_BASE_IDX 0
#define regDAGB5_RDCLI14 0x028e
#define regDAGB5_RDCLI14_BASE_IDX 0
#define regDAGB5_RDCLI15 0x028f
#define regDAGB5_RDCLI15_BASE_IDX 0
#define regDAGB5_RD_CNTL 0x0290
#define regDAGB5_RD_CNTL_BASE_IDX 0
#define regDAGB5_RD_GMI_CNTL 0x0291
#define regDAGB5_RD_GMI_CNTL_BASE_IDX 0
#define regDAGB5_RD_ADDR_DAGB 0x0292
#define regDAGB5_RD_ADDR_DAGB_BASE_IDX 0
#define regDAGB5_RD_OUTPUT_DAGB_MAX_BURST 0x0293
#define regDAGB5_RD_OUTPUT_DAGB_MAX_BURST_BASE_IDX 0
#define regDAGB5_RD_OUTPUT_DAGB_LAZY_TIMER 0x0294
#define regDAGB5_RD_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 0
#define regDAGB5_RD_CGTT_CLK_CTRL 0x0295
#define regDAGB5_RD_CGTT_CLK_CTRL_BASE_IDX 0
#define regDAGB5_L1TLB_RD_CGTT_CLK_CTRL 0x0296
#define regDAGB5_L1TLB_RD_CGTT_CLK_CTRL_BASE_IDX 0
#define regDAGB5_ATCVM_RD_CGTT_CLK_CTRL 0x0297
#define regDAGB5_ATCVM_RD_CGTT_CLK_CTRL_BASE_IDX 0
#define regDAGB5_RD_ADDR_DAGB_MAX_BURST0 0x0298
#define regDAGB5_RD_ADDR_DAGB_MAX_BURST0_BASE_IDX 0
#define regDAGB5_RD_ADDR_DAGB_LAZY_TIMER0 0x0299
#define regDAGB5_RD_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 0
#define regDAGB5_RD_ADDR_DAGB_MAX_BURST1 0x029a
#define regDAGB5_RD_ADDR_DAGB_MAX_BURST1_BASE_IDX 0
#define regDAGB5_RD_ADDR_DAGB_LAZY_TIMER1 0x029b
#define regDAGB5_RD_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 0
#define regDAGB5_RD_VC0_CNTL 0x029c
#define regDAGB5_RD_VC0_CNTL_BASE_IDX 0
#define regDAGB5_RD_VC1_CNTL 0x029d
#define regDAGB5_RD_VC1_CNTL_BASE_IDX 0
#define regDAGB5_RD_VC2_CNTL 0x029e
#define regDAGB5_RD_VC2_CNTL_BASE_IDX 0
#define regDAGB5_RD_VC3_CNTL 0x029f
#define regDAGB5_RD_VC3_CNTL_BASE_IDX 0
#define regDAGB5_RD_VC4_CNTL 0x02a0
#define regDAGB5_RD_VC4_CNTL_BASE_IDX 0
#define regDAGB5_RD_VC5_CNTL 0x02a1
#define regDAGB5_RD_VC5_CNTL_BASE_IDX 0
#define regDAGB5_RD_VC6_CNTL 0x02a2
#define regDAGB5_RD_VC6_CNTL_BASE_IDX 0
#define regDAGB5_RD_VC7_CNTL 0x02a3
#define regDAGB5_RD_VC7_CNTL_BASE_IDX 0
#define regDAGB5_RD_CNTL_MISC 0x02a4
#define regDAGB5_RD_CNTL_MISC_BASE_IDX 0
#define regDAGB5_RD_TLB_CREDIT 0x02a5
#define regDAGB5_RD_TLB_CREDIT_BASE_IDX 0
#define regDAGB5_RD_RDRET_CREDIT_CNTL 0x02a6
#define regDAGB5_RD_RDRET_CREDIT_CNTL_BASE_IDX 0
#define regDAGB5_RD_RDRET_CREDIT_CNTL2 0x02a7
#define regDAGB5_RD_RDRET_CREDIT_CNTL2_BASE_IDX 0
#define regDAGB5_RDCLI_ASK_PENDING 0x02a8
#define regDAGB5_RDCLI_ASK_PENDING_BASE_IDX 0
#define regDAGB5_RDCLI_GO_PENDING 0x02a9
#define regDAGB5_RDCLI_GO_PENDING_BASE_IDX 0
#define regDAGB5_RDCLI_GBLSEND_PENDING 0x02aa
#define regDAGB5_RDCLI_GBLSEND_PENDING_BASE_IDX 0
#define regDAGB5_RDCLI_TLB_PENDING 0x02ab
#define regDAGB5_RDCLI_TLB_PENDING_BASE_IDX 0
#define regDAGB5_RDCLI_OARB_PENDING 0x02ac
#define regDAGB5_RDCLI_OARB_PENDING_BASE_IDX 0
#define regDAGB5_RDCLI_OSD_PENDING 0x02ad
#define regDAGB5_RDCLI_OSD_PENDING_BASE_IDX 0
#define regDAGB5_WRCLI0 0x02ae
#define regDAGB5_WRCLI0_BASE_IDX 0
#define regDAGB5_WRCLI1 0x02af
#define regDAGB5_WRCLI1_BASE_IDX 0
#define regDAGB5_WRCLI2 0x02b0
#define regDAGB5_WRCLI2_BASE_IDX 0
#define regDAGB5_WRCLI3 0x02b1
#define regDAGB5_WRCLI3_BASE_IDX 0
#define regDAGB5_WRCLI4 0x02b2
#define regDAGB5_WRCLI4_BASE_IDX 0
#define regDAGB5_WRCLI5 0x02b3
#define regDAGB5_WRCLI5_BASE_IDX 0
#define regDAGB5_WRCLI6 0x02b4
#define regDAGB5_WRCLI6_BASE_IDX 0
#define regDAGB5_WRCLI7 0x02b5
#define regDAGB5_WRCLI7_BASE_IDX 0
#define regDAGB5_WRCLI8 0x02b6
#define regDAGB5_WRCLI8_BASE_IDX 0
#define regDAGB5_WRCLI9 0x02b7
#define regDAGB5_WRCLI9_BASE_IDX 0
#define regDAGB5_WRCLI10 0x02b8
#define regDAGB5_WRCLI10_BASE_IDX 0
#define regDAGB5_WRCLI11 0x02b9
#define regDAGB5_WRCLI11_BASE_IDX 0
#define regDAGB5_WRCLI12 0x02ba
#define regDAGB5_WRCLI12_BASE_IDX 0
#define regDAGB5_WRCLI13 0x02bb
#define regDAGB5_WRCLI13_BASE_IDX 0
#define regDAGB5_WRCLI14 0x02bc
#define regDAGB5_WRCLI14_BASE_IDX 0
#define regDAGB5_WRCLI15 0x02bd
#define regDAGB5_WRCLI15_BASE_IDX 0
#define regDAGB5_WR_CNTL 0x02be
#define regDAGB5_WR_CNTL_BASE_IDX 0
#define regDAGB5_WR_GMI_CNTL 0x02bf
#define regDAGB5_WR_GMI_CNTL_BASE_IDX 0
#define regDAGB5_WR_ADDR_DAGB 0x02c0
#define regDAGB5_WR_ADDR_DAGB_BASE_IDX 0
#define regDAGB5_WR_OUTPUT_DAGB_MAX_BURST 0x02c1
#define regDAGB5_WR_OUTPUT_DAGB_MAX_BURST_BASE_IDX 0
#define regDAGB5_WR_OUTPUT_DAGB_LAZY_TIMER 0x02c2
#define regDAGB5_WR_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 0
#define regDAGB5_WR_CGTT_CLK_CTRL 0x02c3
#define regDAGB5_WR_CGTT_CLK_CTRL_BASE_IDX 0
#define regDAGB5_L1TLB_WR_CGTT_CLK_CTRL 0x02c4
#define regDAGB5_L1TLB_WR_CGTT_CLK_CTRL_BASE_IDX 0
#define regDAGB5_ATCVM_WR_CGTT_CLK_CTRL 0x02c5
#define regDAGB5_ATCVM_WR_CGTT_CLK_CTRL_BASE_IDX 0
#define regDAGB5_WR_ADDR_DAGB_MAX_BURST0 0x02c6
#define regDAGB5_WR_ADDR_DAGB_MAX_BURST0_BASE_IDX 0
#define regDAGB5_WR_ADDR_DAGB_LAZY_TIMER0 0x02c7
#define regDAGB5_WR_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 0
#define regDAGB5_WR_ADDR_DAGB_MAX_BURST1 0x02c8
#define regDAGB5_WR_ADDR_DAGB_MAX_BURST1_BASE_IDX 0
#define regDAGB5_WR_ADDR_DAGB_LAZY_TIMER1 0x02c9
#define regDAGB5_WR_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 0
#define regDAGB5_WR_DATA_DAGB 0x02ca
#define regDAGB5_WR_DATA_DAGB_BASE_IDX 0
#define regDAGB5_WR_DATA_DAGB_MAX_BURST0 0x02cb
#define regDAGB5_WR_DATA_DAGB_MAX_BURST0_BASE_IDX 0
#define regDAGB5_WR_DATA_DAGB_LAZY_TIMER0 0x02cc
#define regDAGB5_WR_DATA_DAGB_LAZY_TIMER0_BASE_IDX 0
#define regDAGB5_WR_DATA_DAGB_MAX_BURST1 0x02cd
#define regDAGB5_WR_DATA_DAGB_MAX_BURST1_BASE_IDX 0
#define regDAGB5_WR_DATA_DAGB_LAZY_TIMER1 0x02ce
#define regDAGB5_WR_DATA_DAGB_LAZY_TIMER1_BASE_IDX 0
#define regDAGB5_WR_VC0_CNTL 0x02cf
#define regDAGB5_WR_VC0_CNTL_BASE_IDX 0
#define regDAGB5_WR_VC1_CNTL 0x02d0
#define regDAGB5_WR_VC1_CNTL_BASE_IDX 0
#define regDAGB5_WR_VC2_CNTL 0x02d1
#define regDAGB5_WR_VC2_CNTL_BASE_IDX 0
#define regDAGB5_WR_VC3_CNTL 0x02d2
#define regDAGB5_WR_VC3_CNTL_BASE_IDX 0
#define regDAGB5_WR_VC4_CNTL 0x02d3
#define regDAGB5_WR_VC4_CNTL_BASE_IDX 0
#define regDAGB5_WR_VC5_CNTL 0x02d4
#define regDAGB5_WR_VC5_CNTL_BASE_IDX 0
#define regDAGB5_WR_VC6_CNTL 0x02d5
#define regDAGB5_WR_VC6_CNTL_BASE_IDX 0
#define regDAGB5_WR_VC7_CNTL 0x02d6
#define regDAGB5_WR_VC7_CNTL_BASE_IDX 0
#define regDAGB5_WR_CNTL_MISC 0x02d7
#define regDAGB5_WR_CNTL_MISC_BASE_IDX 0
#define regDAGB5_WR_TLB_CREDIT 0x02d8
#define regDAGB5_WR_TLB_CREDIT_BASE_IDX 0
#define regDAGB5_WR_DATA_CREDIT 0x02d9
#define regDAGB5_WR_DATA_CREDIT_BASE_IDX 0
#define regDAGB5_WR_MISC_CREDIT 0x02da
#define regDAGB5_WR_MISC_CREDIT_BASE_IDX 0
#define regDAGB5_WR_OSD_CREDIT_CNTL1 0x02db
#define regDAGB5_WR_OSD_CREDIT_CNTL1_BASE_IDX 0
#define regDAGB5_WR_OSD_CREDIT_CNTL2 0x02dc
#define regDAGB5_WR_OSD_CREDIT_CNTL2_BASE_IDX 0
#define regDAGB5_WR_ATOMIC_FIFO_CREDIT_CNTL1 0x02dd
#define regDAGB5_WR_ATOMIC_FIFO_CREDIT_CNTL1_BASE_IDX 0
#define regDAGB5_WRCLI_GPU_SNOOP_OVERRIDE 0x02de
#define regDAGB5_WRCLI_GPU_SNOOP_OVERRIDE_BASE_IDX 0
#define regDAGB5_WRCLI_GPU_SNOOP_OVERRIDE_VALUE 0x02df
#define regDAGB5_WRCLI_GPU_SNOOP_OVERRIDE_VALUE_BASE_IDX 0
#define regDAGB5_WRCLI_ASK_PENDING 0x02e0
#define regDAGB5_WRCLI_ASK_PENDING_BASE_IDX 0
#define regDAGB5_WRCLI_GO_PENDING 0x02e1
#define regDAGB5_WRCLI_GO_PENDING_BASE_IDX 0
#define regDAGB5_WRCLI_GBLSEND_PENDING 0x02e2
#define regDAGB5_WRCLI_GBLSEND_PENDING_BASE_IDX 0
#define regDAGB5_WRCLI_TLB_PENDING 0x02e3
#define regDAGB5_WRCLI_TLB_PENDING_BASE_IDX 0
#define regDAGB5_WRCLI_OARB_PENDING 0x02e4
#define regDAGB5_WRCLI_OARB_PENDING_BASE_IDX 0
#define regDAGB5_WRCLI_OSD_PENDING 0x02e5
#define regDAGB5_WRCLI_OSD_PENDING_BASE_IDX 0
#define regDAGB5_WRCLI_DBUS_ASK_PENDING 0x02e6
#define regDAGB5_WRCLI_DBUS_ASK_PENDING_BASE_IDX 0
#define regDAGB5_WRCLI_DBUS_GO_PENDING 0x02e7
#define regDAGB5_WRCLI_DBUS_GO_PENDING_BASE_IDX 0
#define regDAGB5_DAGB_DLY 0x02e8
#define regDAGB5_DAGB_DLY_BASE_IDX 0
#define regDAGB5_CNTL_MISC 0x02e9
#define regDAGB5_CNTL_MISC_BASE_IDX 0
#define regDAGB5_CNTL_MISC2 0x02ea
#define regDAGB5_CNTL_MISC2_BASE_IDX 0
#define regDAGB5_FATAL_ERROR_CNTL 0x02eb
#define regDAGB5_FATAL_ERROR_CNTL_BASE_IDX 0
#define regDAGB5_FATAL_ERROR_CLEAR 0x02ec
#define regDAGB5_FATAL_ERROR_CLEAR_BASE_IDX 0
#define regDAGB5_FATAL_ERROR_STATUS0 0x02ed
#define regDAGB5_FATAL_ERROR_STATUS0_BASE_IDX 0
#define regDAGB5_FATAL_ERROR_STATUS1 0x02ee
#define regDAGB5_FATAL_ERROR_STATUS1_BASE_IDX 0
#define regDAGB5_FATAL_ERROR_STATUS2 0x02ef
#define regDAGB5_FATAL_ERROR_STATUS2_BASE_IDX 0
#define regDAGB5_FATAL_ERROR_STATUS3 0x02f0
#define regDAGB5_FATAL_ERROR_STATUS3_BASE_IDX 0
#define regDAGB5_FIFO_EMPTY 0x02f1
#define regDAGB5_FIFO_EMPTY_BASE_IDX 0
#define regDAGB5_FIFO_FULL 0x02f2
#define regDAGB5_FIFO_FULL_BASE_IDX 0
#define regDAGB5_WR_CREDITS_FULL 0x02f3
#define regDAGB5_WR_CREDITS_FULL_BASE_IDX 0
#define regDAGB5_RD_CREDITS_FULL 0x02f4
#define regDAGB5_RD_CREDITS_FULL_BASE_IDX 0
#define regDAGB5_PERFCOUNTER_LO 0x02f5
#define regDAGB5_PERFCOUNTER_LO_BASE_IDX 0
#define regDAGB5_PERFCOUNTER_HI 0x02f6
#define regDAGB5_PERFCOUNTER_HI_BASE_IDX 0
#define regDAGB5_PERFCOUNTER0_CFG 0x02f7
#define regDAGB5_PERFCOUNTER0_CFG_BASE_IDX 0
#define regDAGB5_PERFCOUNTER1_CFG 0x02f8
#define regDAGB5_PERFCOUNTER1_CFG_BASE_IDX 0
#define regDAGB5_PERFCOUNTER2_CFG 0x02f9
#define regDAGB5_PERFCOUNTER2_CFG_BASE_IDX 0
#define regDAGB5_PERFCOUNTER_RSLT_CNTL 0x02fa
#define regDAGB5_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0
#define regDAGB5_L1TLB_REG_RW 0x02fb
#define regDAGB5_L1TLB_REG_RW_BASE_IDX 0
#define regDAGB5_RESERVE1 0x02fc
#define regDAGB5_RESERVE1_BASE_IDX 0
#define regDAGB5_RESERVE2 0x02fd
#define regDAGB5_RESERVE2_BASE_IDX 0
#define regDAGB5_RESERVE3 0x02fe
#define regDAGB5_RESERVE3_BASE_IDX 0
#define regDAGB5_RESERVE4 0x02ff
#define regDAGB5_RESERVE4_BASE_IDX 0
// addressBlock: mmhub_ea_mmeadec0
// base address: 0x68c00
#define regMMEA0_DRAM_RD_CLI2GRP_MAP0 0x0300
#define regMMEA0_DRAM_RD_CLI2GRP_MAP0_BASE_IDX 0
#define regMMEA0_DRAM_RD_CLI2GRP_MAP1 0x0301
#define regMMEA0_DRAM_RD_CLI2GRP_MAP1_BASE_IDX 0
#define regMMEA0_DRAM_WR_CLI2GRP_MAP0 0x0302
#define regMMEA0_DRAM_WR_CLI2GRP_MAP0_BASE_IDX 0
#define regMMEA0_DRAM_WR_CLI2GRP_MAP1 0x0303
#define regMMEA0_DRAM_WR_CLI2GRP_MAP1_BASE_IDX 0
#define regMMEA0_DRAM_RD_GRP2VC_MAP 0x0304
#define regMMEA0_DRAM_RD_GRP2VC_MAP_BASE_IDX 0
#define regMMEA0_DRAM_WR_GRP2VC_MAP 0x0305
#define regMMEA0_DRAM_WR_GRP2VC_MAP_BASE_IDX 0
#define regMMEA0_DRAM_RD_LAZY 0x0306
#define regMMEA0_DRAM_RD_LAZY_BASE_IDX 0
#define regMMEA0_DRAM_WR_LAZY 0x0307
#define regMMEA0_DRAM_WR_LAZY_BASE_IDX 0
#define regMMEA0_DRAM_RD_CAM_CNTL 0x0308
#define regMMEA0_DRAM_RD_CAM_CNTL_BASE_IDX 0
#define regMMEA0_DRAM_WR_CAM_CNTL 0x0309
#define regMMEA0_DRAM_WR_CAM_CNTL_BASE_IDX 0
#define regMMEA0_DRAM_PAGE_BURST 0x030a
#define regMMEA0_DRAM_PAGE_BURST_BASE_IDX 0
#define regMMEA0_DRAM_RD_PRI_AGE 0x030b
#define regMMEA0_DRAM_RD_PRI_AGE_BASE_IDX 0
#define regMMEA0_DRAM_WR_PRI_AGE 0x030c
#define regMMEA0_DRAM_WR_PRI_AGE_BASE_IDX 0
#define regMMEA0_DRAM_RD_PRI_QUEUING 0x030d
#define regMMEA0_DRAM_RD_PRI_QUEUING_BASE_IDX 0
#define regMMEA0_DRAM_WR_PRI_QUEUING 0x030e
#define regMMEA0_DRAM_WR_PRI_QUEUING_BASE_IDX 0
#define regMMEA0_DRAM_RD_PRI_FIXED 0x030f
#define regMMEA0_DRAM_RD_PRI_FIXED_BASE_IDX 0
#define regMMEA0_DRAM_WR_PRI_FIXED 0x0310
#define regMMEA0_DRAM_WR_PRI_FIXED_BASE_IDX 0
#define regMMEA0_DRAM_RD_PRI_URGENCY 0x0311
#define regMMEA0_DRAM_RD_PRI_URGENCY_BASE_IDX 0
#define regMMEA0_DRAM_WR_PRI_URGENCY 0x0312
#define regMMEA0_DRAM_WR_PRI_URGENCY_BASE_IDX 0
#define regMMEA0_DRAM_RD_PRI_QUANT_PRI1 0x0313
#define regMMEA0_DRAM_RD_PRI_QUANT_PRI1_BASE_IDX 0
#define regMMEA0_DRAM_RD_PRI_QUANT_PRI2 0x0314
#define regMMEA0_DRAM_RD_PRI_QUANT_PRI2_BASE_IDX 0
#define regMMEA0_DRAM_RD_PRI_QUANT_PRI3 0x0315
#define regMMEA0_DRAM_RD_PRI_QUANT_PRI3_BASE_IDX 0
#define regMMEA0_DRAM_WR_PRI_QUANT_PRI1 0x0316
#define regMMEA0_DRAM_WR_PRI_QUANT_PRI1_BASE_IDX 0
#define regMMEA0_DRAM_WR_PRI_QUANT_PRI2 0x0317
#define regMMEA0_DRAM_WR_PRI_QUANT_PRI2_BASE_IDX 0
#define regMMEA0_DRAM_WR_PRI_QUANT_PRI3 0x0318
#define regMMEA0_DRAM_WR_PRI_QUANT_PRI3_BASE_IDX 0
#define regMMEA0_GMI_RD_CLI2GRP_MAP0 0x0319
#define regMMEA0_GMI_RD_CLI2GRP_MAP0_BASE_IDX 0
#define regMMEA0_GMI_RD_CLI2GRP_MAP1 0x031a
#define regMMEA0_GMI_RD_CLI2GRP_MAP1_BASE_IDX 0
#define regMMEA0_GMI_WR_CLI2GRP_MAP0 0x031b
#define regMMEA0_GMI_WR_CLI2GRP_MAP0_BASE_IDX 0
#define regMMEA0_GMI_WR_CLI2GRP_MAP1 0x031c
#define regMMEA0_GMI_WR_CLI2GRP_MAP1_BASE_IDX 0
#define regMMEA0_GMI_RD_GRP2VC_MAP 0x031d
#define regMMEA0_GMI_RD_GRP2VC_MAP_BASE_IDX 0
#define regMMEA0_GMI_WR_GRP2VC_MAP 0x031e
#define regMMEA0_GMI_WR_GRP2VC_MAP_BASE_IDX 0
#define regMMEA0_GMI_RD_LAZY 0x031f
#define regMMEA0_GMI_RD_LAZY_BASE_IDX 0
#define regMMEA0_GMI_WR_LAZY 0x0320
#define regMMEA0_GMI_WR_LAZY_BASE_IDX 0
#define regMMEA0_GMI_RD_CAM_CNTL 0x0321
#define regMMEA0_GMI_RD_CAM_CNTL_BASE_IDX 0
#define regMMEA0_GMI_WR_CAM_CNTL 0x0322
#define regMMEA0_GMI_WR_CAM_CNTL_BASE_IDX 0
#define regMMEA0_GMI_PAGE_BURST 0x0323
#define regMMEA0_GMI_PAGE_BURST_BASE_IDX 0
#define regMMEA0_GMI_RD_PRI_AGE 0x0324
#define regMMEA0_GMI_RD_PRI_AGE_BASE_IDX 0
#define regMMEA0_GMI_WR_PRI_AGE 0x0325
#define regMMEA0_GMI_WR_PRI_AGE_BASE_IDX 0
#define regMMEA0_GMI_RD_PRI_QUEUING 0x0326
#define regMMEA0_GMI_RD_PRI_QUEUING_BASE_IDX 0
#define regMMEA0_GMI_WR_PRI_QUEUING 0x0327
#define regMMEA0_GMI_WR_PRI_QUEUING_BASE_IDX 0
#define regMMEA0_GMI_RD_PRI_FIXED 0x0328
#define regMMEA0_GMI_RD_PRI_FIXED_BASE_IDX 0
#define regMMEA0_GMI_WR_PRI_FIXED 0x0329
#define regMMEA0_GMI_WR_PRI_FIXED_BASE_IDX 0
#define regMMEA0_GMI_RD_PRI_URGENCY 0x032a
#define regMMEA0_GMI_RD_PRI_URGENCY_BASE_IDX 0
#define regMMEA0_GMI_WR_PRI_URGENCY 0x032b
#define regMMEA0_GMI_WR_PRI_URGENCY_BASE_IDX 0
#define regMMEA0_GMI_RD_PRI_URGENCY_MASKING 0x032c
#define regMMEA0_GMI_RD_PRI_URGENCY_MASKING_BASE_IDX 0
#define regMMEA0_GMI_WR_PRI_URGENCY_MASKING 0x032d
#define regMMEA0_GMI_WR_PRI_URGENCY_MASKING_BASE_IDX 0
#define regMMEA0_GMI_RD_PRI_QUANT_PRI1 0x032e
#define regMMEA0_GMI_RD_PRI_QUANT_PRI1_BASE_IDX 0
#define regMMEA0_GMI_RD_PRI_QUANT_PRI2 0x032f
#define regMMEA0_GMI_RD_PRI_QUANT_PRI2_BASE_IDX 0
#define regMMEA0_GMI_RD_PRI_QUANT_PRI3 0x0330
#define regMMEA0_GMI_RD_PRI_QUANT_PRI3_BASE_IDX 0
#define regMMEA0_GMI_WR_PRI_QUANT_PRI1 0x0331
#define regMMEA0_GMI_WR_PRI_QUANT_PRI1_BASE_IDX 0
#define regMMEA0_GMI_WR_PRI_QUANT_PRI2 0x0332
#define regMMEA0_GMI_WR_PRI_QUANT_PRI2_BASE_IDX 0
#define regMMEA0_GMI_WR_PRI_QUANT_PRI3 0x0333
#define regMMEA0_GMI_WR_PRI_QUANT_PRI3_BASE_IDX 0
#define regMMEA0_ADDRNORM_BASE_ADDR0 0x0334
#define regMMEA0_ADDRNORM_BASE_ADDR0_BASE_IDX 0
#define regMMEA0_ADDRNORM_LIMIT_ADDR0 0x0335
#define regMMEA0_ADDRNORM_LIMIT_ADDR0_BASE_IDX 0
#define regMMEA0_ADDRNORM_BASE_ADDR1 0x0336
#define regMMEA0_ADDRNORM_BASE_ADDR1_BASE_IDX 0
#define regMMEA0_ADDRNORM_LIMIT_ADDR1 0x0337
#define regMMEA0_ADDRNORM_LIMIT_ADDR1_BASE_IDX 0
#define regMMEA0_ADDRNORM_OFFSET_ADDR1 0x0338
#define regMMEA0_ADDRNORM_OFFSET_ADDR1_BASE_IDX 0
#define regMMEA0_ADDRNORM_BASE_ADDR2 0x0339
#define regMMEA0_ADDRNORM_BASE_ADDR2_BASE_IDX 0
#define regMMEA0_ADDRNORM_LIMIT_ADDR2 0x033a
#define regMMEA0_ADDRNORM_LIMIT_ADDR2_BASE_IDX 0
#define regMMEA0_ADDRNORM_BASE_ADDR3 0x033b
#define regMMEA0_ADDRNORM_BASE_ADDR3_BASE_IDX 0
#define regMMEA0_ADDRNORM_LIMIT_ADDR3 0x033c
#define regMMEA0_ADDRNORM_LIMIT_ADDR3_BASE_IDX 0
#define regMMEA0_ADDRNORM_OFFSET_ADDR3 0x033d
#define regMMEA0_ADDRNORM_OFFSET_ADDR3_BASE_IDX 0
#define regMMEA0_ADDRNORM_MEGABASE_ADDR0 0x033e
#define regMMEA0_ADDRNORM_MEGABASE_ADDR0_BASE_IDX 0
#define regMMEA0_ADDRNORM_MEGALIMIT_ADDR0 0x033f
#define regMMEA0_ADDRNORM_MEGALIMIT_ADDR0_BASE_IDX 0
#define regMMEA0_ADDRNORM_MEGABASE_ADDR1 0x0340
#define regMMEA0_ADDRNORM_MEGABASE_ADDR1_BASE_IDX 0
#define regMMEA0_ADDRNORM_MEGALIMIT_ADDR1 0x0341
#define regMMEA0_ADDRNORM_MEGALIMIT_ADDR1_BASE_IDX 0
#define regMMEA0_ADDRNORMDRAM_HOLE_CNTL 0x0343
#define regMMEA0_ADDRNORMDRAM_HOLE_CNTL_BASE_IDX 0
#define regMMEA0_ADDRNORMGMI_HOLE_CNTL 0x0344
#define regMMEA0_ADDRNORMGMI_HOLE_CNTL_BASE_IDX 0
#define regMMEA0_ADDRNORMDRAM_NP2_CHANNEL_CFG 0x0345
#define regMMEA0_ADDRNORMDRAM_NP2_CHANNEL_CFG_BASE_IDX 0
#define regMMEA0_ADDRNORMGMI_NP2_CHANNEL_CFG 0x0346
#define regMMEA0_ADDRNORMGMI_NP2_CHANNEL_CFG_BASE_IDX 0
#define regMMEA0_ADDRDEC_BANK_CFG 0x0347
#define regMMEA0_ADDRDEC_BANK_CFG_BASE_IDX 0
#define regMMEA0_ADDRDEC_MISC_CFG 0x0348
#define regMMEA0_ADDRDEC_MISC_CFG_BASE_IDX 0
#define regMMEA0_ADDRDECDRAM_HARVEST_ENABLE 0x0353
#define regMMEA0_ADDRDECDRAM_HARVEST_ENABLE_BASE_IDX 0
#define regMMEA0_ADDRDECGMI_HARVEST_ENABLE 0x035e
#define regMMEA0_ADDRDECGMI_HARVEST_ENABLE_BASE_IDX 0
#define regMMEA0_ADDRDEC0_BASE_ADDR_CS0 0x035f
#define regMMEA0_ADDRDEC0_BASE_ADDR_CS0_BASE_IDX 0
#define regMMEA0_ADDRDEC0_BASE_ADDR_CS1 0x0360
#define regMMEA0_ADDRDEC0_BASE_ADDR_CS1_BASE_IDX 0
#define regMMEA0_ADDRDEC0_BASE_ADDR_CS2 0x0361
#define regMMEA0_ADDRDEC0_BASE_ADDR_CS2_BASE_IDX 0
#define regMMEA0_ADDRDEC0_BASE_ADDR_CS3 0x0362
#define regMMEA0_ADDRDEC0_BASE_ADDR_CS3_BASE_IDX 0
#define regMMEA0_ADDRDEC0_BASE_ADDR_SECCS0 0x0363
#define regMMEA0_ADDRDEC0_BASE_ADDR_SECCS0_BASE_IDX 0
#define regMMEA0_ADDRDEC0_BASE_ADDR_SECCS1 0x0364
#define regMMEA0_ADDRDEC0_BASE_ADDR_SECCS1_BASE_IDX 0
#define regMMEA0_ADDRDEC0_BASE_ADDR_SECCS2 0x0365
#define regMMEA0_ADDRDEC0_BASE_ADDR_SECCS2_BASE_IDX 0
#define regMMEA0_ADDRDEC0_BASE_ADDR_SECCS3 0x0366
#define regMMEA0_ADDRDEC0_BASE_ADDR_SECCS3_BASE_IDX 0
#define regMMEA0_ADDRDEC0_ADDR_MASK_CS01 0x0367
#define regMMEA0_ADDRDEC0_ADDR_MASK_CS01_BASE_IDX 0
#define regMMEA0_ADDRDEC0_ADDR_MASK_CS23 0x0368
#define regMMEA0_ADDRDEC0_ADDR_MASK_CS23_BASE_IDX 0
#define regMMEA0_ADDRDEC0_ADDR_MASK_SECCS01 0x0369
#define regMMEA0_ADDRDEC0_ADDR_MASK_SECCS01_BASE_IDX 0
#define regMMEA0_ADDRDEC0_ADDR_MASK_SECCS23 0x036a
#define regMMEA0_ADDRDEC0_ADDR_MASK_SECCS23_BASE_IDX 0
#define regMMEA0_ADDRDEC0_ADDR_CFG_CS01 0x036b
#define regMMEA0_ADDRDEC0_ADDR_CFG_CS01_BASE_IDX 0
#define regMMEA0_ADDRDEC0_ADDR_CFG_CS23 0x036c
#define regMMEA0_ADDRDEC0_ADDR_CFG_CS23_BASE_IDX 0
#define regMMEA0_ADDRDEC0_ADDR_SEL_CS01 0x036d
#define regMMEA0_ADDRDEC0_ADDR_SEL_CS01_BASE_IDX 0
#define regMMEA0_ADDRDEC0_ADDR_SEL_CS23 0x036e
#define regMMEA0_ADDRDEC0_ADDR_SEL_CS23_BASE_IDX 0
#define regMMEA0_ADDRDEC0_ADDR_SEL2_CS01 0x036f
#define regMMEA0_ADDRDEC0_ADDR_SEL2_CS01_BASE_IDX 0
#define regMMEA0_ADDRDEC0_ADDR_SEL2_CS23 0x0370
#define regMMEA0_ADDRDEC0_ADDR_SEL2_CS23_BASE_IDX 0
#define regMMEA0_ADDRDEC0_COL_SEL_LO_CS01 0x0371
#define regMMEA0_ADDRDEC0_COL_SEL_LO_CS01_BASE_IDX 0
#define regMMEA0_ADDRDEC0_COL_SEL_LO_CS23 0x0372
#define regMMEA0_ADDRDEC0_COL_SEL_LO_CS23_BASE_IDX 0
#define regMMEA0_ADDRDEC0_COL_SEL_HI_CS01 0x0373
#define regMMEA0_ADDRDEC0_COL_SEL_HI_CS01_BASE_IDX 0
#define regMMEA0_ADDRDEC0_COL_SEL_HI_CS23 0x0374
#define regMMEA0_ADDRDEC0_COL_SEL_HI_CS23_BASE_IDX 0
#define regMMEA0_ADDRDEC0_RM_SEL_CS01 0x0375
#define regMMEA0_ADDRDEC0_RM_SEL_CS01_BASE_IDX 0
#define regMMEA0_ADDRDEC0_RM_SEL_CS23 0x0376
#define regMMEA0_ADDRDEC0_RM_SEL_CS23_BASE_IDX 0
#define regMMEA0_ADDRDEC0_RM_SEL_SECCS01 0x0377
#define regMMEA0_ADDRDEC0_RM_SEL_SECCS01_BASE_IDX 0
#define regMMEA0_ADDRDEC0_RM_SEL_SECCS23 0x0378
#define regMMEA0_ADDRDEC0_RM_SEL_SECCS23_BASE_IDX 0
#define regMMEA0_ADDRDEC1_BASE_ADDR_CS0 0x0379
#define regMMEA0_ADDRDEC1_BASE_ADDR_CS0_BASE_IDX 0
#define regMMEA0_ADDRDEC1_BASE_ADDR_CS1 0x037a
#define regMMEA0_ADDRDEC1_BASE_ADDR_CS1_BASE_IDX 0
#define regMMEA0_ADDRDEC1_BASE_ADDR_CS2 0x037b
#define regMMEA0_ADDRDEC1_BASE_ADDR_CS2_BASE_IDX 0
#define regMMEA0_ADDRDEC1_BASE_ADDR_CS3 0x037c
#define regMMEA0_ADDRDEC1_BASE_ADDR_CS3_BASE_IDX 0
#define regMMEA0_ADDRDEC1_BASE_ADDR_SECCS0 0x037d
#define regMMEA0_ADDRDEC1_BASE_ADDR_SECCS0_BASE_IDX 0
#define regMMEA0_ADDRDEC1_BASE_ADDR_SECCS1 0x037e
#define regMMEA0_ADDRDEC1_BASE_ADDR_SECCS1_BASE_IDX 0
#define regMMEA0_ADDRDEC1_BASE_ADDR_SECCS2 0x037f
#define regMMEA0_ADDRDEC1_BASE_ADDR_SECCS2_BASE_IDX 0
#define regMMEA0_ADDRDEC1_BASE_ADDR_SECCS3 0x0380
#define regMMEA0_ADDRDEC1_BASE_ADDR_SECCS3_BASE_IDX 0
#define regMMEA0_ADDRDEC1_ADDR_MASK_CS01 0x0381
#define regMMEA0_ADDRDEC1_ADDR_MASK_CS01_BASE_IDX 0
#define regMMEA0_ADDRDEC1_ADDR_MASK_CS23 0x0382
#define regMMEA0_ADDRDEC1_ADDR_MASK_CS23_BASE_IDX 0
#define regMMEA0_ADDRDEC1_ADDR_MASK_SECCS01 0x0383
#define regMMEA0_ADDRDEC1_ADDR_MASK_SECCS01_BASE_IDX 0
#define regMMEA0_ADDRDEC1_ADDR_MASK_SECCS23 0x0384
#define regMMEA0_ADDRDEC1_ADDR_MASK_SECCS23_BASE_IDX 0
#define regMMEA0_ADDRDEC1_ADDR_CFG_CS01 0x0385
#define regMMEA0_ADDRDEC1_ADDR_CFG_CS01_BASE_IDX 0
#define regMMEA0_ADDRDEC1_ADDR_CFG_CS23 0x0386
#define regMMEA0_ADDRDEC1_ADDR_CFG_CS23_BASE_IDX 0
#define regMMEA0_ADDRDEC1_ADDR_SEL_CS01 0x0387
#define regMMEA0_ADDRDEC1_ADDR_SEL_CS01_BASE_IDX 0
#define regMMEA0_ADDRDEC1_ADDR_SEL_CS23 0x0388
#define regMMEA0_ADDRDEC1_ADDR_SEL_CS23_BASE_IDX 0
#define regMMEA0_ADDRDEC1_ADDR_SEL2_CS01 0x0389
#define regMMEA0_ADDRDEC1_ADDR_SEL2_CS01_BASE_IDX 0
#define regMMEA0_ADDRDEC1_ADDR_SEL2_CS23 0x038a
#define regMMEA0_ADDRDEC1_ADDR_SEL2_CS23_BASE_IDX 0
#define regMMEA0_ADDRDEC1_COL_SEL_LO_CS01 0x038b
#define regMMEA0_ADDRDEC1_COL_SEL_LO_CS01_BASE_IDX 0
#define regMMEA0_ADDRDEC1_COL_SEL_LO_CS23 0x038c
#define regMMEA0_ADDRDEC1_COL_SEL_LO_CS23_BASE_IDX 0
#define regMMEA0_ADDRDEC1_COL_SEL_HI_CS01 0x038d
#define regMMEA0_ADDRDEC1_COL_SEL_HI_CS01_BASE_IDX 0
#define regMMEA0_ADDRDEC1_COL_SEL_HI_CS23 0x038e
#define regMMEA0_ADDRDEC1_COL_SEL_HI_CS23_BASE_IDX 0
#define regMMEA0_ADDRDEC1_RM_SEL_CS01 0x038f
#define regMMEA0_ADDRDEC1_RM_SEL_CS01_BASE_IDX 0
#define regMMEA0_ADDRDEC1_RM_SEL_CS23 0x0390
#define regMMEA0_ADDRDEC1_RM_SEL_CS23_BASE_IDX 0
#define regMMEA0_ADDRDEC1_RM_SEL_SECCS01 0x0391
#define regMMEA0_ADDRDEC1_RM_SEL_SECCS01_BASE_IDX 0
#define regMMEA0_ADDRDEC1_RM_SEL_SECCS23 0x0392
#define regMMEA0_ADDRDEC1_RM_SEL_SECCS23_BASE_IDX 0
#define regMMEA0_ADDRDEC2_BASE_ADDR_CS0 0x0393
#define regMMEA0_ADDRDEC2_BASE_ADDR_CS0_BASE_IDX 0
#define regMMEA0_ADDRDEC2_BASE_ADDR_CS1 0x0394
#define regMMEA0_ADDRDEC2_BASE_ADDR_CS1_BASE_IDX 0
#define regMMEA0_ADDRDEC2_BASE_ADDR_CS2 0x0395
#define regMMEA0_ADDRDEC2_BASE_ADDR_CS2_BASE_IDX 0
#define regMMEA0_ADDRDEC2_BASE_ADDR_CS3 0x0396
#define regMMEA0_ADDRDEC2_BASE_ADDR_CS3_BASE_IDX 0
#define regMMEA0_ADDRDEC2_BASE_ADDR_SECCS0 0x0397
#define regMMEA0_ADDRDEC2_BASE_ADDR_SECCS0_BASE_IDX 0
#define regMMEA0_ADDRDEC2_BASE_ADDR_SECCS1 0x0398
#define regMMEA0_ADDRDEC2_BASE_ADDR_SECCS1_BASE_IDX 0
#define regMMEA0_ADDRDEC2_BASE_ADDR_SECCS2 0x0399
#define regMMEA0_ADDRDEC2_BASE_ADDR_SECCS2_BASE_IDX 0
#define regMMEA0_ADDRDEC2_BASE_ADDR_SECCS3 0x039a
#define regMMEA0_ADDRDEC2_BASE_ADDR_SECCS3_BASE_IDX 0
#define regMMEA0_ADDRDEC2_ADDR_MASK_CS01 0x039b
#define regMMEA0_ADDRDEC2_ADDR_MASK_CS01_BASE_IDX 0
#define regMMEA0_ADDRDEC2_ADDR_MASK_CS23 0x039c
#define regMMEA0_ADDRDEC2_ADDR_MASK_CS23_BASE_IDX 0
#define regMMEA0_ADDRDEC2_ADDR_MASK_SECCS01 0x039d
#define regMMEA0_ADDRDEC2_ADDR_MASK_SECCS01_BASE_IDX 0
#define regMMEA0_ADDRDEC2_ADDR_MASK_SECCS23 0x039e
#define regMMEA0_ADDRDEC2_ADDR_MASK_SECCS23_BASE_IDX 0
#define regMMEA0_ADDRDEC2_ADDR_CFG_CS01 0x039f
#define regMMEA0_ADDRDEC2_ADDR_CFG_CS01_BASE_IDX 0
#define regMMEA0_ADDRDEC2_ADDR_CFG_CS23 0x03a0
#define regMMEA0_ADDRDEC2_ADDR_CFG_CS23_BASE_IDX 0
#define regMMEA0_ADDRDEC2_ADDR_SEL_CS01 0x03a1
#define regMMEA0_ADDRDEC2_ADDR_SEL_CS01_BASE_IDX 0
#define regMMEA0_ADDRDEC2_ADDR_SEL_CS23 0x03a2
#define regMMEA0_ADDRDEC2_ADDR_SEL_CS23_BASE_IDX 0
#define regMMEA0_ADDRDEC2_ADDR_SEL2_CS01 0x03a3
#define regMMEA0_ADDRDEC2_ADDR_SEL2_CS01_BASE_IDX 0
#define regMMEA0_ADDRDEC2_ADDR_SEL2_CS23 0x03a4
#define regMMEA0_ADDRDEC2_ADDR_SEL2_CS23_BASE_IDX 0
#define regMMEA0_ADDRDEC2_COL_SEL_LO_CS01 0x03a5
#define regMMEA0_ADDRDEC2_COL_SEL_LO_CS01_BASE_IDX 0
#define regMMEA0_ADDRDEC2_COL_SEL_LO_CS23 0x03a6
#define regMMEA0_ADDRDEC2_COL_SEL_LO_CS23_BASE_IDX 0
#define regMMEA0_ADDRDEC2_COL_SEL_HI_CS01 0x03a7
#define regMMEA0_ADDRDEC2_COL_SEL_HI_CS01_BASE_IDX 0
#define regMMEA0_ADDRDEC2_COL_SEL_HI_CS23 0x03a8
#define regMMEA0_ADDRDEC2_COL_SEL_HI_CS23_BASE_IDX 0
#define regMMEA0_ADDRDEC2_RM_SEL_CS01 0x03a9
#define regMMEA0_ADDRDEC2_RM_SEL_CS01_BASE_IDX 0
#define regMMEA0_ADDRDEC2_RM_SEL_CS23 0x03aa
#define regMMEA0_ADDRDEC2_RM_SEL_CS23_BASE_IDX 0
#define regMMEA0_ADDRDEC2_RM_SEL_SECCS01 0x03ab
#define regMMEA0_ADDRDEC2_RM_SEL_SECCS01_BASE_IDX 0
#define regMMEA0_ADDRDEC2_RM_SEL_SECCS23 0x03ac
#define regMMEA0_ADDRDEC2_RM_SEL_SECCS23_BASE_IDX 0
#define regMMEA0_ADDRNORMDRAM_GLOBAL_CNTL 0x03ad
#define regMMEA0_ADDRNORMDRAM_GLOBAL_CNTL_BASE_IDX 0
#define regMMEA0_ADDRNORMGMI_GLOBAL_CNTL 0x03ae
#define regMMEA0_ADDRNORMGMI_GLOBAL_CNTL_BASE_IDX 0
#define regMMEA0_ADDRNORM_MEGACONTROL_ADDR0 0x03d1
#define regMMEA0_ADDRNORM_MEGACONTROL_ADDR0_BASE_IDX 0
#define regMMEA0_ADDRNORM_MEGACONTROL_ADDR1 0x03d2
#define regMMEA0_ADDRNORM_MEGACONTROL_ADDR1_BASE_IDX 0
#define regMMEA0_ADDRNORMDRAM_MASKING 0x03d3
#define regMMEA0_ADDRNORMDRAM_MASKING_BASE_IDX 0
#define regMMEA0_ADDRNORMGMI_MASKING 0x03d4
#define regMMEA0_ADDRNORMGMI_MASKING_BASE_IDX 0
#define regMMEA0_IO_RD_CLI2GRP_MAP0 0x03d5
#define regMMEA0_IO_RD_CLI2GRP_MAP0_BASE_IDX 0
#define regMMEA0_IO_RD_CLI2GRP_MAP1 0x03d6
#define regMMEA0_IO_RD_CLI2GRP_MAP1_BASE_IDX 0
#define regMMEA0_IO_WR_CLI2GRP_MAP0 0x03d7
#define regMMEA0_IO_WR_CLI2GRP_MAP0_BASE_IDX 0
#define regMMEA0_IO_WR_CLI2GRP_MAP1 0x03d8
#define regMMEA0_IO_WR_CLI2GRP_MAP1_BASE_IDX 0
#define regMMEA0_IO_RD_COMBINE_FLUSH 0x03d9
#define regMMEA0_IO_RD_COMBINE_FLUSH_BASE_IDX 0
#define regMMEA0_IO_WR_COMBINE_FLUSH 0x03da
#define regMMEA0_IO_WR_COMBINE_FLUSH_BASE_IDX 0
#define regMMEA0_IO_GROUP_BURST 0x03db
#define regMMEA0_IO_GROUP_BURST_BASE_IDX 0
#define regMMEA0_IO_RD_PRI_AGE 0x03dc
#define regMMEA0_IO_RD_PRI_AGE_BASE_IDX 0
#define regMMEA0_IO_WR_PRI_AGE 0x03dd
#define regMMEA0_IO_WR_PRI_AGE_BASE_IDX 0
#define regMMEA0_IO_RD_PRI_QUEUING 0x03de
#define regMMEA0_IO_RD_PRI_QUEUING_BASE_IDX 0
#define regMMEA0_IO_WR_PRI_QUEUING 0x03df
#define regMMEA0_IO_WR_PRI_QUEUING_BASE_IDX 0
#define regMMEA0_IO_RD_PRI_FIXED 0x03e0
#define regMMEA0_IO_RD_PRI_FIXED_BASE_IDX 0
#define regMMEA0_IO_WR_PRI_FIXED 0x03e1
#define regMMEA0_IO_WR_PRI_FIXED_BASE_IDX 0
#define regMMEA0_IO_RD_PRI_URGENCY 0x03e2
#define regMMEA0_IO_RD_PRI_URGENCY_BASE_IDX 0
#define regMMEA0_IO_WR_PRI_URGENCY 0x03e3
#define regMMEA0_IO_WR_PRI_URGENCY_BASE_IDX 0
#define regMMEA0_IO_RD_PRI_URGENCY_MASKING 0x03e4
#define regMMEA0_IO_RD_PRI_URGENCY_MASKING_BASE_IDX 0
#define regMMEA0_IO_WR_PRI_URGENCY_MASKING 0x03e5
#define regMMEA0_IO_WR_PRI_URGENCY_MASKING_BASE_IDX 0
#define regMMEA0_IO_RD_PRI_QUANT_PRI1 0x03e6
#define regMMEA0_IO_RD_PRI_QUANT_PRI1_BASE_IDX 0
#define regMMEA0_IO_RD_PRI_QUANT_PRI2 0x03e7
#define regMMEA0_IO_RD_PRI_QUANT_PRI2_BASE_IDX 0
#define regMMEA0_IO_RD_PRI_QUANT_PRI3 0x03e8
#define regMMEA0_IO_RD_PRI_QUANT_PRI3_BASE_IDX 0
#define regMMEA0_IO_WR_PRI_QUANT_PRI1 0x03e9
#define regMMEA0_IO_WR_PRI_QUANT_PRI1_BASE_IDX 0
#define regMMEA0_IO_WR_PRI_QUANT_PRI2 0x03ea
#define regMMEA0_IO_WR_PRI_QUANT_PRI2_BASE_IDX 0
#define regMMEA0_IO_WR_PRI_QUANT_PRI3 0x03eb
#define regMMEA0_IO_WR_PRI_QUANT_PRI3_BASE_IDX 0
#define regMMEA0_SDP_ARB_DRAM 0x03ec
#define regMMEA0_SDP_ARB_DRAM_BASE_IDX 0
#define regMMEA0_SDP_ARB_GMI 0x03ed
#define regMMEA0_SDP_ARB_GMI_BASE_IDX 0
#define regMMEA0_SDP_ARB_FINAL 0x03ee
#define regMMEA0_SDP_ARB_FINAL_BASE_IDX 0
#define regMMEA0_SDP_DRAM_PRIORITY 0x03ef
#define regMMEA0_SDP_DRAM_PRIORITY_BASE_IDX 0
#define regMMEA0_SDP_GMI_PRIORITY 0x03f0
#define regMMEA0_SDP_GMI_PRIORITY_BASE_IDX 0
#define regMMEA0_SDP_IO_PRIORITY 0x03f1
#define regMMEA0_SDP_IO_PRIORITY_BASE_IDX 0
#define regMMEA0_SDP_CREDITS 0x03f2
#define regMMEA0_SDP_CREDITS_BASE_IDX 0
#define regMMEA0_SDP_TAG_RESERVE0 0x03f3
#define regMMEA0_SDP_TAG_RESERVE0_BASE_IDX 0
#define regMMEA0_SDP_TAG_RESERVE1 0x03f4
#define regMMEA0_SDP_TAG_RESERVE1_BASE_IDX 0
#define regMMEA0_SDP_VCC_RESERVE0 0x03f5
#define regMMEA0_SDP_VCC_RESERVE0_BASE_IDX 0
#define regMMEA0_SDP_VCC_RESERVE1 0x03f6
#define regMMEA0_SDP_VCC_RESERVE1_BASE_IDX 0
#define regMMEA0_SDP_VCD_RESERVE0 0x03f7
#define regMMEA0_SDP_VCD_RESERVE0_BASE_IDX 0
#define regMMEA0_SDP_VCD_RESERVE1 0x03f8
#define regMMEA0_SDP_VCD_RESERVE1_BASE_IDX 0
#define regMMEA0_SDP_REQ_CNTL 0x03f9
#define regMMEA0_SDP_REQ_CNTL_BASE_IDX 0
#define regMMEA0_MISC 0x03fa
#define regMMEA0_MISC_BASE_IDX 0
#define regMMEA0_LATENCY_SAMPLING 0x03fb
#define regMMEA0_LATENCY_SAMPLING_BASE_IDX 0
#define regMMEA0_PERFCOUNTER_LO 0x03fc
#define regMMEA0_PERFCOUNTER_LO_BASE_IDX 0
#define regMMEA0_PERFCOUNTER_HI 0x03fd
#define regMMEA0_PERFCOUNTER_HI_BASE_IDX 0
#define regMMEA0_PERFCOUNTER0_CFG 0x03fe
#define regMMEA0_PERFCOUNTER0_CFG_BASE_IDX 0
#define regMMEA0_PERFCOUNTER1_CFG 0x03ff
#define regMMEA0_PERFCOUNTER1_CFG_BASE_IDX 0
#define regMMEA0_PERFCOUNTER_RSLT_CNTL 0x0400
#define regMMEA0_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0
#define regMMEA0_EDC_CNT 0x0406
#define regMMEA0_EDC_CNT_BASE_IDX 0
#define regMMEA0_EDC_CNT2 0x0407
#define regMMEA0_EDC_CNT2_BASE_IDX 0
#define regMMEA0_DSM_CNTL 0x0408
#define regMMEA0_DSM_CNTL_BASE_IDX 0
#define regMMEA0_DSM_CNTLA 0x0409
#define regMMEA0_DSM_CNTLA_BASE_IDX 0
#define regMMEA0_DSM_CNTLB 0x040a
#define regMMEA0_DSM_CNTLB_BASE_IDX 0
#define regMMEA0_DSM_CNTL2 0x040b
#define regMMEA0_DSM_CNTL2_BASE_IDX 0
#define regMMEA0_DSM_CNTL2A 0x040c
#define regMMEA0_DSM_CNTL2A_BASE_IDX 0
#define regMMEA0_DSM_CNTL2B 0x040d
#define regMMEA0_DSM_CNTL2B_BASE_IDX 0
#define regMMEA0_CGTT_CLK_CTRL 0x040f
#define regMMEA0_CGTT_CLK_CTRL_BASE_IDX 0
#define regMMEA0_EDC_MODE 0x0410
#define regMMEA0_EDC_MODE_BASE_IDX 0
#define regMMEA0_ERR_STATUS 0x0411
#define regMMEA0_ERR_STATUS_BASE_IDX 0
#define regMMEA0_MISC2 0x0412
#define regMMEA0_MISC2_BASE_IDX 0
#define regMMEA0_ADDRDEC_SELECT 0x0413
#define regMMEA0_ADDRDEC_SELECT_BASE_IDX 0
#define regMMEA0_EDC_CNT3 0x0414
#define regMMEA0_EDC_CNT3_BASE_IDX 0
#define regMMEA0_MISC_AON 0x0415
#define regMMEA0_MISC_AON_BASE_IDX 0
// addressBlock: mmhub_ea_mmeadec1
// base address: 0x69100
#define regMMEA1_DRAM_RD_CLI2GRP_MAP0 0x0440
#define regMMEA1_DRAM_RD_CLI2GRP_MAP0_BASE_IDX 0
#define regMMEA1_DRAM_RD_CLI2GRP_MAP1 0x0441
#define regMMEA1_DRAM_RD_CLI2GRP_MAP1_BASE_IDX 0
#define regMMEA1_DRAM_WR_CLI2GRP_MAP0 0x0442
#define regMMEA1_DRAM_WR_CLI2GRP_MAP0_BASE_IDX 0
#define regMMEA1_DRAM_WR_CLI2GRP_MAP1 0x0443
#define regMMEA1_DRAM_WR_CLI2GRP_MAP1_BASE_IDX 0
#define regMMEA1_DRAM_RD_GRP2VC_MAP 0x0444
#define regMMEA1_DRAM_RD_GRP2VC_MAP_BASE_IDX 0
#define regMMEA1_DRAM_WR_GRP2VC_MAP 0x0445
#define regMMEA1_DRAM_WR_GRP2VC_MAP_BASE_IDX 0
#define regMMEA1_DRAM_RD_LAZY 0x0446
#define regMMEA1_DRAM_RD_LAZY_BASE_IDX 0
#define regMMEA1_DRAM_WR_LAZY 0x0447
#define regMMEA1_DRAM_WR_LAZY_BASE_IDX 0
#define regMMEA1_DRAM_RD_CAM_CNTL 0x0448
#define regMMEA1_DRAM_RD_CAM_CNTL_BASE_IDX 0
#define regMMEA1_DRAM_WR_CAM_CNTL 0x0449
#define regMMEA1_DRAM_WR_CAM_CNTL_BASE_IDX 0
#define regMMEA1_DRAM_PAGE_BURST 0x044a
#define regMMEA1_DRAM_PAGE_BURST_BASE_IDX 0
#define regMMEA1_DRAM_RD_PRI_AGE 0x044b
#define regMMEA1_DRAM_RD_PRI_AGE_BASE_IDX 0
#define regMMEA1_DRAM_WR_PRI_AGE 0x044c
#define regMMEA1_DRAM_WR_PRI_AGE_BASE_IDX 0
#define regMMEA1_DRAM_RD_PRI_QUEUING 0x044d
#define regMMEA1_DRAM_RD_PRI_QUEUING_BASE_IDX 0
#define regMMEA1_DRAM_WR_PRI_QUEUING 0x044e
#define regMMEA1_DRAM_WR_PRI_QUEUING_BASE_IDX 0
#define regMMEA1_DRAM_RD_PRI_FIXED 0x044f
#define regMMEA1_DRAM_RD_PRI_FIXED_BASE_IDX 0
#define regMMEA1_DRAM_WR_PRI_FIXED 0x0450
#define regMMEA1_DRAM_WR_PRI_FIXED_BASE_IDX 0
#define regMMEA1_DRAM_RD_PRI_URGENCY 0x0451
#define regMMEA1_DRAM_RD_PRI_URGENCY_BASE_IDX 0
#define regMMEA1_DRAM_WR_PRI_URGENCY 0x0452
#define regMMEA1_DRAM_WR_PRI_URGENCY_BASE_IDX 0
#define regMMEA1_DRAM_RD_PRI_QUANT_PRI1 0x0453
#define regMMEA1_DRAM_RD_PRI_QUANT_PRI1_BASE_IDX 0
#define regMMEA1_DRAM_RD_PRI_QUANT_PRI2 0x0454
#define regMMEA1_DRAM_RD_PRI_QUANT_PRI2_BASE_IDX 0
#define regMMEA1_DRAM_RD_PRI_QUANT_PRI3 0x0455
#define regMMEA1_DRAM_RD_PRI_QUANT_PRI3_BASE_IDX 0
#define regMMEA1_DRAM_WR_PRI_QUANT_PRI1 0x0456
#define regMMEA1_DRAM_WR_PRI_QUANT_PRI1_BASE_IDX 0
#define regMMEA1_DRAM_WR_PRI_QUANT_PRI2 0x0457
#define regMMEA1_DRAM_WR_PRI_QUANT_PRI2_BASE_IDX 0
#define regMMEA1_DRAM_WR_PRI_QUANT_PRI3 0x0458
#define regMMEA1_DRAM_WR_PRI_QUANT_PRI3_BASE_IDX 0
#define regMMEA1_GMI_RD_CLI2GRP_MAP0 0x0459
#define regMMEA1_GMI_RD_CLI2GRP_MAP0_BASE_IDX 0
#define regMMEA1_GMI_RD_CLI2GRP_MAP1 0x045a
#define regMMEA1_GMI_RD_CLI2GRP_MAP1_BASE_IDX 0
#define regMMEA1_GMI_WR_CLI2GRP_MAP0 0x045b
#define regMMEA1_GMI_WR_CLI2GRP_MAP0_BASE_IDX 0
#define regMMEA1_GMI_WR_CLI2GRP_MAP1 0x045c
#define regMMEA1_GMI_WR_CLI2GRP_MAP1_BASE_IDX 0
#define regMMEA1_GMI_RD_GRP2VC_MAP 0x045d
#define regMMEA1_GMI_RD_GRP2VC_MAP_BASE_IDX 0
#define regMMEA1_GMI_WR_GRP2VC_MAP 0x045e
#define regMMEA1_GMI_WR_GRP2VC_MAP_BASE_IDX 0
#define regMMEA1_GMI_RD_LAZY 0x045f
#define regMMEA1_GMI_RD_LAZY_BASE_IDX 0
#define regMMEA1_GMI_WR_LAZY 0x0460
#define regMMEA1_GMI_WR_LAZY_BASE_IDX 0
#define regMMEA1_GMI_RD_CAM_CNTL 0x0461
#define regMMEA1_GMI_RD_CAM_CNTL_BASE_IDX 0
#define regMMEA1_GMI_WR_CAM_CNTL 0x0462
#define regMMEA1_GMI_WR_CAM_CNTL_BASE_IDX 0
#define regMMEA1_GMI_PAGE_BURST 0x0463
#define regMMEA1_GMI_PAGE_BURST_BASE_IDX 0
#define regMMEA1_GMI_RD_PRI_AGE 0x0464
#define regMMEA1_GMI_RD_PRI_AGE_BASE_IDX 0
#define regMMEA1_GMI_WR_PRI_AGE 0x0465
#define regMMEA1_GMI_WR_PRI_AGE_BASE_IDX 0
#define regMMEA1_GMI_RD_PRI_QUEUING 0x0466
#define regMMEA1_GMI_RD_PRI_QUEUING_BASE_IDX 0
#define regMMEA1_GMI_WR_PRI_QUEUING 0x0467
#define regMMEA1_GMI_WR_PRI_QUEUING_BASE_IDX 0
#define regMMEA1_GMI_RD_PRI_FIXED 0x0468
#define regMMEA1_GMI_RD_PRI_FIXED_BASE_IDX 0
#define regMMEA1_GMI_WR_PRI_FIXED 0x0469
#define regMMEA1_GMI_WR_PRI_FIXED_BASE_IDX 0
#define regMMEA1_GMI_RD_PRI_URGENCY 0x046a
#define regMMEA1_GMI_RD_PRI_URGENCY_BASE_IDX 0
#define regMMEA1_GMI_WR_PRI_URGENCY 0x046b
#define regMMEA1_GMI_WR_PRI_URGENCY_BASE_IDX 0
#define regMMEA1_GMI_RD_PRI_URGENCY_MASKING 0x046c
#define regMMEA1_GMI_RD_PRI_URGENCY_MASKING_BASE_IDX 0
#define regMMEA1_GMI_WR_PRI_URGENCY_MASKING 0x046d
#define regMMEA1_GMI_WR_PRI_URGENCY_MASKING_BASE_IDX 0
#define regMMEA1_GMI_RD_PRI_QUANT_PRI1 0x046e
#define regMMEA1_GMI_RD_PRI_QUANT_PRI1_BASE_IDX 0
#define regMMEA1_GMI_RD_PRI_QUANT_PRI2 0x046f
#define regMMEA1_GMI_RD_PRI_QUANT_PRI2_BASE_IDX 0
#define regMMEA1_GMI_RD_PRI_QUANT_PRI3 0x0470
#define regMMEA1_GMI_RD_PRI_QUANT_PRI3_BASE_IDX 0
#define regMMEA1_GMI_WR_PRI_QUANT_PRI1 0x0471
#define regMMEA1_GMI_WR_PRI_QUANT_PRI1_BASE_IDX 0
#define regMMEA1_GMI_WR_PRI_QUANT_PRI2 0x0472
#define regMMEA1_GMI_WR_PRI_QUANT_PRI2_BASE_IDX 0
#define regMMEA1_GMI_WR_PRI_QUANT_PRI3 0x0473
#define regMMEA1_GMI_WR_PRI_QUANT_PRI3_BASE_IDX 0
#define regMMEA1_ADDRNORM_BASE_ADDR0 0x0474
#define regMMEA1_ADDRNORM_BASE_ADDR0_BASE_IDX 0
#define regMMEA1_ADDRNORM_LIMIT_ADDR0 0x0475
#define regMMEA1_ADDRNORM_LIMIT_ADDR0_BASE_IDX 0
#define regMMEA1_ADDRNORM_BASE_ADDR1 0x0476
#define regMMEA1_ADDRNORM_BASE_ADDR1_BASE_IDX 0
#define regMMEA1_ADDRNORM_LIMIT_ADDR1 0x0477
#define regMMEA1_ADDRNORM_LIMIT_ADDR1_BASE_IDX 0
#define regMMEA1_ADDRNORM_OFFSET_ADDR1 0x0478
#define regMMEA1_ADDRNORM_OFFSET_ADDR1_BASE_IDX 0
#define regMMEA1_ADDRNORM_BASE_ADDR2 0x0479
#define regMMEA1_ADDRNORM_BASE_ADDR2_BASE_IDX 0
#define regMMEA1_ADDRNORM_LIMIT_ADDR2 0x047a
#define regMMEA1_ADDRNORM_LIMIT_ADDR2_BASE_IDX 0
#define regMMEA1_ADDRNORM_BASE_ADDR3 0x047b
#define regMMEA1_ADDRNORM_BASE_ADDR3_BASE_IDX 0
#define regMMEA1_ADDRNORM_LIMIT_ADDR3 0x047c
#define regMMEA1_ADDRNORM_LIMIT_ADDR3_BASE_IDX 0
#define regMMEA1_ADDRNORM_OFFSET_ADDR3 0x047d
#define regMMEA1_ADDRNORM_OFFSET_ADDR3_BASE_IDX 0
#define regMMEA1_ADDRNORM_MEGABASE_ADDR0 0x047e
#define regMMEA1_ADDRNORM_MEGABASE_ADDR0_BASE_IDX 0
#define regMMEA1_ADDRNORM_MEGALIMIT_ADDR0 0x047f
#define regMMEA1_ADDRNORM_MEGALIMIT_ADDR0_BASE_IDX 0
#define regMMEA1_ADDRNORM_MEGABASE_ADDR1 0x0480
#define regMMEA1_ADDRNORM_MEGABASE_ADDR1_BASE_IDX 0
#define regMMEA1_ADDRNORM_MEGALIMIT_ADDR1 0x0481
#define regMMEA1_ADDRNORM_MEGALIMIT_ADDR1_BASE_IDX 0
#define regMMEA1_ADDRNORMDRAM_HOLE_CNTL 0x0483
#define regMMEA1_ADDRNORMDRAM_HOLE_CNTL_BASE_IDX 0
#define regMMEA1_ADDRNORMGMI_HOLE_CNTL 0x0484
#define regMMEA1_ADDRNORMGMI_HOLE_CNTL_BASE_IDX 0
#define regMMEA1_ADDRNORMDRAM_NP2_CHANNEL_CFG 0x0485
#define regMMEA1_ADDRNORMDRAM_NP2_CHANNEL_CFG_BASE_IDX 0
#define regMMEA1_ADDRNORMGMI_NP2_CHANNEL_CFG 0x0486
#define regMMEA1_ADDRNORMGMI_NP2_CHANNEL_CFG_BASE_IDX 0
#define regMMEA1_ADDRDEC_BANK_CFG 0x0487
#define regMMEA1_ADDRDEC_BANK_CFG_BASE_IDX 0
#define regMMEA1_ADDRDEC_MISC_CFG 0x0488
#define regMMEA1_ADDRDEC_MISC_CFG_BASE_IDX 0
#define regMMEA1_ADDRDECDRAM_HARVEST_ENABLE 0x0493
#define regMMEA1_ADDRDECDRAM_HARVEST_ENABLE_BASE_IDX 0
#define regMMEA1_ADDRDECGMI_HARVEST_ENABLE 0x049e
#define regMMEA1_ADDRDECGMI_HARVEST_ENABLE_BASE_IDX 0
#define regMMEA1_ADDRDEC0_BASE_ADDR_CS0 0x049f
#define regMMEA1_ADDRDEC0_BASE_ADDR_CS0_BASE_IDX 0
#define regMMEA1_ADDRDEC0_BASE_ADDR_CS1 0x04a0
#define regMMEA1_ADDRDEC0_BASE_ADDR_CS1_BASE_IDX 0
#define regMMEA1_ADDRDEC0_BASE_ADDR_CS2 0x04a1
#define regMMEA1_ADDRDEC0_BASE_ADDR_CS2_BASE_IDX 0
#define regMMEA1_ADDRDEC0_BASE_ADDR_CS3 0x04a2
#define regMMEA1_ADDRDEC0_BASE_ADDR_CS3_BASE_IDX 0
#define regMMEA1_ADDRDEC0_BASE_ADDR_SECCS0 0x04a3
#define regMMEA1_ADDRDEC0_BASE_ADDR_SECCS0_BASE_IDX 0
#define regMMEA1_ADDRDEC0_BASE_ADDR_SECCS1 0x04a4
#define regMMEA1_ADDRDEC0_BASE_ADDR_SECCS1_BASE_IDX 0
#define regMMEA1_ADDRDEC0_BASE_ADDR_SECCS2 0x04a5
#define regMMEA1_ADDRDEC0_BASE_ADDR_SECCS2_BASE_IDX 0
#define regMMEA1_ADDRDEC0_BASE_ADDR_SECCS3 0x04a6
#define regMMEA1_ADDRDEC0_BASE_ADDR_SECCS3_BASE_IDX 0
#define regMMEA1_ADDRDEC0_ADDR_MASK_CS01 0x04a7
#define regMMEA1_ADDRDEC0_ADDR_MASK_CS01_BASE_IDX 0
#define regMMEA1_ADDRDEC0_ADDR_MASK_CS23 0x04a8
#define regMMEA1_ADDRDEC0_ADDR_MASK_CS23_BASE_IDX 0
#define regMMEA1_ADDRDEC0_ADDR_MASK_SECCS01 0x04a9
#define regMMEA1_ADDRDEC0_ADDR_MASK_SECCS01_BASE_IDX 0
#define regMMEA1_ADDRDEC0_ADDR_MASK_SECCS23 0x04aa
#define regMMEA1_ADDRDEC0_ADDR_MASK_SECCS23_BASE_IDX 0
#define regMMEA1_ADDRDEC0_ADDR_CFG_CS01 0x04ab
#define regMMEA1_ADDRDEC0_ADDR_CFG_CS01_BASE_IDX 0
#define regMMEA1_ADDRDEC0_ADDR_CFG_CS23 0x04ac
#define regMMEA1_ADDRDEC0_ADDR_CFG_CS23_BASE_IDX 0
#define regMMEA1_ADDRDEC0_ADDR_SEL_CS01 0x04ad
#define regMMEA1_ADDRDEC0_ADDR_SEL_CS01_BASE_IDX 0
#define regMMEA1_ADDRDEC0_ADDR_SEL_CS23 0x04ae
#define regMMEA1_ADDRDEC0_ADDR_SEL_CS23_BASE_IDX 0
#define regMMEA1_ADDRDEC0_ADDR_SEL2_CS01 0x04af
#define regMMEA1_ADDRDEC0_ADDR_SEL2_CS01_BASE_IDX 0
#define regMMEA1_ADDRDEC0_ADDR_SEL2_CS23 0x04b0
#define regMMEA1_ADDRDEC0_ADDR_SEL2_CS23_BASE_IDX 0
#define regMMEA1_ADDRDEC0_COL_SEL_LO_CS01 0x04b1
#define regMMEA1_ADDRDEC0_COL_SEL_LO_CS01_BASE_IDX 0
#define regMMEA1_ADDRDEC0_COL_SEL_LO_CS23 0x04b2
#define regMMEA1_ADDRDEC0_COL_SEL_LO_CS23_BASE_IDX 0
#define regMMEA1_ADDRDEC0_COL_SEL_HI_CS01 0x04b3
#define regMMEA1_ADDRDEC0_COL_SEL_HI_CS01_BASE_IDX 0
#define regMMEA1_ADDRDEC0_COL_SEL_HI_CS23 0x04b4
#define regMMEA1_ADDRDEC0_COL_SEL_HI_CS23_BASE_IDX 0
#define regMMEA1_ADDRDEC0_RM_SEL_CS01 0x04b5
#define regMMEA1_ADDRDEC0_RM_SEL_CS01_BASE_IDX 0
#define regMMEA1_ADDRDEC0_RM_SEL_CS23 0x04b6
#define regMMEA1_ADDRDEC0_RM_SEL_CS23_BASE_IDX 0
#define regMMEA1_ADDRDEC0_RM_SEL_SECCS01 0x04b7
#define regMMEA1_ADDRDEC0_RM_SEL_SECCS01_BASE_IDX 0
#define regMMEA1_ADDRDEC0_RM_SEL_SECCS23 0x04b8
#define regMMEA1_ADDRDEC0_RM_SEL_SECCS23_BASE_IDX 0
#define regMMEA1_ADDRDEC1_BASE_ADDR_CS0 0x04b9
#define regMMEA1_ADDRDEC1_BASE_ADDR_CS0_BASE_IDX 0
#define regMMEA1_ADDRDEC1_BASE_ADDR_CS1 0x04ba
#define regMMEA1_ADDRDEC1_BASE_ADDR_CS1_BASE_IDX 0
#define regMMEA1_ADDRDEC1_BASE_ADDR_CS2 0x04bb
#define regMMEA1_ADDRDEC1_BASE_ADDR_CS2_BASE_IDX 0
#define regMMEA1_ADDRDEC1_BASE_ADDR_CS3 0x04bc
#define regMMEA1_ADDRDEC1_BASE_ADDR_CS3_BASE_IDX 0
#define regMMEA1_ADDRDEC1_BASE_ADDR_SECCS0 0x04bd
#define regMMEA1_ADDRDEC1_BASE_ADDR_SECCS0_BASE_IDX 0
#define regMMEA1_ADDRDEC1_BASE_ADDR_SECCS1 0x04be
#define regMMEA1_ADDRDEC1_BASE_ADDR_SECCS1_BASE_IDX 0
#define regMMEA1_ADDRDEC1_BASE_ADDR_SECCS2 0x04bf
#define regMMEA1_ADDRDEC1_BASE_ADDR_SECCS2_BASE_IDX 0
#define regMMEA1_ADDRDEC1_BASE_ADDR_SECCS3 0x04c0
#define regMMEA1_ADDRDEC1_BASE_ADDR_SECCS3_BASE_IDX 0
#define regMMEA1_ADDRDEC1_ADDR_MASK_CS01 0x04c1
#define regMMEA1_ADDRDEC1_ADDR_MASK_CS01_BASE_IDX 0
#define regMMEA1_ADDRDEC1_ADDR_MASK_CS23 0x04c2
#define regMMEA1_ADDRDEC1_ADDR_MASK_CS23_BASE_IDX 0
#define regMMEA1_ADDRDEC1_ADDR_MASK_SECCS01 0x04c3
#define regMMEA1_ADDRDEC1_ADDR_MASK_SECCS01_BASE_IDX 0
#define regMMEA1_ADDRDEC1_ADDR_MASK_SECCS23 0x04c4
#define regMMEA1_ADDRDEC1_ADDR_MASK_SECCS23_BASE_IDX 0
#define regMMEA1_ADDRDEC1_ADDR_CFG_CS01 0x04c5
#define regMMEA1_ADDRDEC1_ADDR_CFG_CS01_BASE_IDX 0
#define regMMEA1_ADDRDEC1_ADDR_CFG_CS23 0x04c6
#define regMMEA1_ADDRDEC1_ADDR_CFG_CS23_BASE_IDX 0
#define regMMEA1_ADDRDEC1_ADDR_SEL_CS01 0x04c7
#define regMMEA1_ADDRDEC1_ADDR_SEL_CS01_BASE_IDX 0
#define regMMEA1_ADDRDEC1_ADDR_SEL_CS23 0x04c8
#define regMMEA1_ADDRDEC1_ADDR_SEL_CS23_BASE_IDX 0
#define regMMEA1_ADDRDEC1_ADDR_SEL2_CS01 0x04c9
#define regMMEA1_ADDRDEC1_ADDR_SEL2_CS01_BASE_IDX 0
#define regMMEA1_ADDRDEC1_ADDR_SEL2_CS23 0x04ca
#define regMMEA1_ADDRDEC1_ADDR_SEL2_CS23_BASE_IDX 0
#define regMMEA1_ADDRDEC1_COL_SEL_LO_CS01 0x04cb
#define regMMEA1_ADDRDEC1_COL_SEL_LO_CS01_BASE_IDX 0
#define regMMEA1_ADDRDEC1_COL_SEL_LO_CS23 0x04cc
#define regMMEA1_ADDRDEC1_COL_SEL_LO_CS23_BASE_IDX 0
#define regMMEA1_ADDRDEC1_COL_SEL_HI_CS01 0x04cd
#define regMMEA1_ADDRDEC1_COL_SEL_HI_CS01_BASE_IDX 0
#define regMMEA1_ADDRDEC1_COL_SEL_HI_CS23 0x04ce
#define regMMEA1_ADDRDEC1_COL_SEL_HI_CS23_BASE_IDX 0
#define regMMEA1_ADDRDEC1_RM_SEL_CS01 0x04cf
#define regMMEA1_ADDRDEC1_RM_SEL_CS01_BASE_IDX 0
#define regMMEA1_ADDRDEC1_RM_SEL_CS23 0x04d0
#define regMMEA1_ADDRDEC1_RM_SEL_CS23_BASE_IDX 0
#define regMMEA1_ADDRDEC1_RM_SEL_SECCS01 0x04d1
#define regMMEA1_ADDRDEC1_RM_SEL_SECCS01_BASE_IDX 0
#define regMMEA1_ADDRDEC1_RM_SEL_SECCS23 0x04d2
#define regMMEA1_ADDRDEC1_RM_SEL_SECCS23_BASE_IDX 0
#define regMMEA1_ADDRDEC2_BASE_ADDR_CS0 0x04d3
#define regMMEA1_ADDRDEC2_BASE_ADDR_CS0_BASE_IDX 0
#define regMMEA1_ADDRDEC2_BASE_ADDR_CS1 0x04d4
#define regMMEA1_ADDRDEC2_BASE_ADDR_CS1_BASE_IDX 0
#define regMMEA1_ADDRDEC2_BASE_ADDR_CS2 0x04d5
#define regMMEA1_ADDRDEC2_BASE_ADDR_CS2_BASE_IDX 0
#define regMMEA1_ADDRDEC2_BASE_ADDR_CS3 0x04d6
#define regMMEA1_ADDRDEC2_BASE_ADDR_CS3_BASE_IDX 0
#define regMMEA1_ADDRDEC2_BASE_ADDR_SECCS0 0x04d7
#define regMMEA1_ADDRDEC2_BASE_ADDR_SECCS0_BASE_IDX 0
#define regMMEA1_ADDRDEC2_BASE_ADDR_SECCS1 0x04d8
#define regMMEA1_ADDRDEC2_BASE_ADDR_SECCS1_BASE_IDX 0
#define regMMEA1_ADDRDEC2_BASE_ADDR_SECCS2 0x04d9
#define regMMEA1_ADDRDEC2_BASE_ADDR_SECCS2_BASE_IDX 0
#define regMMEA1_ADDRDEC2_BASE_ADDR_SECCS3 0x04da
#define regMMEA1_ADDRDEC2_BASE_ADDR_SECCS3_BASE_IDX 0
#define regMMEA1_ADDRDEC2_ADDR_MASK_CS01 0x04db
#define regMMEA1_ADDRDEC2_ADDR_MASK_CS01_BASE_IDX 0
#define regMMEA1_ADDRDEC2_ADDR_MASK_CS23 0x04dc
#define regMMEA1_ADDRDEC2_ADDR_MASK_CS23_BASE_IDX 0
#define regMMEA1_ADDRDEC2_ADDR_MASK_SECCS01 0x04dd
#define regMMEA1_ADDRDEC2_ADDR_MASK_SECCS01_BASE_IDX 0
#define regMMEA1_ADDRDEC2_ADDR_MASK_SECCS23 0x04de
#define regMMEA1_ADDRDEC2_ADDR_MASK_SECCS23_BASE_IDX 0
#define regMMEA1_ADDRDEC2_ADDR_CFG_CS01 0x04df
#define regMMEA1_ADDRDEC2_ADDR_CFG_CS01_BASE_IDX 0
#define regMMEA1_ADDRDEC2_ADDR_CFG_CS23 0x04e0
#define regMMEA1_ADDRDEC2_ADDR_CFG_CS23_BASE_IDX 0
#define regMMEA1_ADDRDEC2_ADDR_SEL_CS01 0x04e1
#define regMMEA1_ADDRDEC2_ADDR_SEL_CS01_BASE_IDX 0
#define regMMEA1_ADDRDEC2_ADDR_SEL_CS23 0x04e2
#define regMMEA1_ADDRDEC2_ADDR_SEL_CS23_BASE_IDX 0
#define regMMEA1_ADDRDEC2_ADDR_SEL2_CS01 0x04e3
#define regMMEA1_ADDRDEC2_ADDR_SEL2_CS01_BASE_IDX 0
#define regMMEA1_ADDRDEC2_ADDR_SEL2_CS23 0x04e4
#define regMMEA1_ADDRDEC2_ADDR_SEL2_CS23_BASE_IDX 0
#define regMMEA1_ADDRDEC2_COL_SEL_LO_CS01 0x04e5
#define regMMEA1_ADDRDEC2_COL_SEL_LO_CS01_BASE_IDX 0
#define regMMEA1_ADDRDEC2_COL_SEL_LO_CS23 0x04e6
#define regMMEA1_ADDRDEC2_COL_SEL_LO_CS23_BASE_IDX 0
#define regMMEA1_ADDRDEC2_COL_SEL_HI_CS01 0x04e7
#define regMMEA1_ADDRDEC2_COL_SEL_HI_CS01_BASE_IDX 0
#define regMMEA1_ADDRDEC2_COL_SEL_HI_CS23 0x04e8
#define regMMEA1_ADDRDEC2_COL_SEL_HI_CS23_BASE_IDX 0
#define regMMEA1_ADDRDEC2_RM_SEL_CS01 0x04e9
#define regMMEA1_ADDRDEC2_RM_SEL_CS01_BASE_IDX 0
#define regMMEA1_ADDRDEC2_RM_SEL_CS23 0x04ea
#define regMMEA1_ADDRDEC2_RM_SEL_CS23_BASE_IDX 0
#define regMMEA1_ADDRDEC2_RM_SEL_SECCS01 0x04eb
#define regMMEA1_ADDRDEC2_RM_SEL_SECCS01_BASE_IDX 0
#define regMMEA1_ADDRDEC2_RM_SEL_SECCS23 0x04ec
#define regMMEA1_ADDRDEC2_RM_SEL_SECCS23_BASE_IDX 0
#define regMMEA1_ADDRNORMDRAM_GLOBAL_CNTL 0x04ed
#define regMMEA1_ADDRNORMDRAM_GLOBAL_CNTL_BASE_IDX 0
#define regMMEA1_ADDRNORMGMI_GLOBAL_CNTL 0x04ee
#define regMMEA1_ADDRNORMGMI_GLOBAL_CNTL_BASE_IDX 0
#define regMMEA1_ADDRNORM_MEGACONTROL_ADDR0 0x0511
#define regMMEA1_ADDRNORM_MEGACONTROL_ADDR0_BASE_IDX 0
#define regMMEA1_ADDRNORM_MEGACONTROL_ADDR1 0x0512
#define regMMEA1_ADDRNORM_MEGACONTROL_ADDR1_BASE_IDX 0
#define regMMEA1_ADDRNORMDRAM_MASKING 0x0513
#define regMMEA1_ADDRNORMDRAM_MASKING_BASE_IDX 0
#define regMMEA1_ADDRNORMGMI_MASKING 0x0514
#define regMMEA1_ADDRNORMGMI_MASKING_BASE_IDX 0
#define regMMEA1_IO_RD_CLI2GRP_MAP0 0x0515
#define regMMEA1_IO_RD_CLI2GRP_MAP0_BASE_IDX 0
#define regMMEA1_IO_RD_CLI2GRP_MAP1 0x0516
#define regMMEA1_IO_RD_CLI2GRP_MAP1_BASE_IDX 0
#define regMMEA1_IO_WR_CLI2GRP_MAP0 0x0517
#define regMMEA1_IO_WR_CLI2GRP_MAP0_BASE_IDX 0
#define regMMEA1_IO_WR_CLI2GRP_MAP1 0x0518
#define regMMEA1_IO_WR_CLI2GRP_MAP1_BASE_IDX 0
#define regMMEA1_IO_RD_COMBINE_FLUSH 0x0519
#define regMMEA1_IO_RD_COMBINE_FLUSH_BASE_IDX 0
#define regMMEA1_IO_WR_COMBINE_FLUSH 0x051a
#define regMMEA1_IO_WR_COMBINE_FLUSH_BASE_IDX 0
#define regMMEA1_IO_GROUP_BURST 0x051b
#define regMMEA1_IO_GROUP_BURST_BASE_IDX 0
#define regMMEA1_IO_RD_PRI_AGE 0x051c
#define regMMEA1_IO_RD_PRI_AGE_BASE_IDX 0
#define regMMEA1_IO_WR_PRI_AGE 0x051d
#define regMMEA1_IO_WR_PRI_AGE_BASE_IDX 0
#define regMMEA1_IO_RD_PRI_QUEUING 0x051e
#define regMMEA1_IO_RD_PRI_QUEUING_BASE_IDX 0
#define regMMEA1_IO_WR_PRI_QUEUING 0x051f
#define regMMEA1_IO_WR_PRI_QUEUING_BASE_IDX 0
#define regMMEA1_IO_RD_PRI_FIXED 0x0520
#define regMMEA1_IO_RD_PRI_FIXED_BASE_IDX 0
#define regMMEA1_IO_WR_PRI_FIXED 0x0521
#define regMMEA1_IO_WR_PRI_FIXED_BASE_IDX 0
#define regMMEA1_IO_RD_PRI_URGENCY 0x0522
#define regMMEA1_IO_RD_PRI_URGENCY_BASE_IDX 0
#define regMMEA1_IO_WR_PRI_URGENCY 0x0523
#define regMMEA1_IO_WR_PRI_URGENCY_BASE_IDX 0
#define regMMEA1_IO_RD_PRI_URGENCY_MASKING 0x0524
#define regMMEA1_IO_RD_PRI_URGENCY_MASKING_BASE_IDX 0
#define regMMEA1_IO_WR_PRI_URGENCY_MASKING 0x0525
#define regMMEA1_IO_WR_PRI_URGENCY_MASKING_BASE_IDX 0
#define regMMEA1_IO_RD_PRI_QUANT_PRI1 0x0526
#define regMMEA1_IO_RD_PRI_QUANT_PRI1_BASE_IDX 0
#define regMMEA1_IO_RD_PRI_QUANT_PRI2 0x0527
#define regMMEA1_IO_RD_PRI_QUANT_PRI2_BASE_IDX 0
#define regMMEA1_IO_RD_PRI_QUANT_PRI3 0x0528
#define regMMEA1_IO_RD_PRI_QUANT_PRI3_BASE_IDX 0
#define regMMEA1_IO_WR_PRI_QUANT_PRI1 0x0529
#define regMMEA1_IO_WR_PRI_QUANT_PRI1_BASE_IDX 0
#define regMMEA1_IO_WR_PRI_QUANT_PRI2 0x052a
#define regMMEA1_IO_WR_PRI_QUANT_PRI2_BASE_IDX 0
#define regMMEA1_IO_WR_PRI_QUANT_PRI3 0x052b
#define regMMEA1_IO_WR_PRI_QUANT_PRI3_BASE_IDX 0
#define regMMEA1_SDP_ARB_DRAM 0x052c
#define regMMEA1_SDP_ARB_DRAM_BASE_IDX 0
#define regMMEA1_SDP_ARB_GMI 0x052d
#define regMMEA1_SDP_ARB_GMI_BASE_IDX 0
#define regMMEA1_SDP_ARB_FINAL 0x052e
#define regMMEA1_SDP_ARB_FINAL_BASE_IDX 0
#define regMMEA1_SDP_DRAM_PRIORITY 0x052f
#define regMMEA1_SDP_DRAM_PRIORITY_BASE_IDX 0
#define regMMEA1_SDP_GMI_PRIORITY 0x0530
#define regMMEA1_SDP_GMI_PRIORITY_BASE_IDX 0
#define regMMEA1_SDP_IO_PRIORITY 0x0531
#define regMMEA1_SDP_IO_PRIORITY_BASE_IDX 0
#define regMMEA1_SDP_CREDITS 0x0532
#define regMMEA1_SDP_CREDITS_BASE_IDX 0
#define regMMEA1_SDP_TAG_RESERVE0 0x0533
#define regMMEA1_SDP_TAG_RESERVE0_BASE_IDX 0
#define regMMEA1_SDP_TAG_RESERVE1 0x0534
#define regMMEA1_SDP_TAG_RESERVE1_BASE_IDX 0
#define regMMEA1_SDP_VCC_RESERVE0 0x0535
#define regMMEA1_SDP_VCC_RESERVE0_BASE_IDX 0
#define regMMEA1_SDP_VCC_RESERVE1 0x0536
#define regMMEA1_SDP_VCC_RESERVE1_BASE_IDX 0
#define regMMEA1_SDP_VCD_RESERVE0 0x0537
#define regMMEA1_SDP_VCD_RESERVE0_BASE_IDX 0
#define regMMEA1_SDP_VCD_RESERVE1 0x0538
#define regMMEA1_SDP_VCD_RESERVE1_BASE_IDX 0
#define regMMEA1_SDP_REQ_CNTL 0x0539
#define regMMEA1_SDP_REQ_CNTL_BASE_IDX 0
#define regMMEA1_MISC 0x053a
#define regMMEA1_MISC_BASE_IDX 0
#define regMMEA1_LATENCY_SAMPLING 0x053b
#define regMMEA1_LATENCY_SAMPLING_BASE_IDX 0
#define regMMEA1_PERFCOUNTER_LO 0x053c
#define regMMEA1_PERFCOUNTER_LO_BASE_IDX 0
#define regMMEA1_PERFCOUNTER_HI 0x053d
#define regMMEA1_PERFCOUNTER_HI_BASE_IDX 0
#define regMMEA1_PERFCOUNTER0_CFG 0x053e
#define regMMEA1_PERFCOUNTER0_CFG_BASE_IDX 0
#define regMMEA1_PERFCOUNTER1_CFG 0x053f
#define regMMEA1_PERFCOUNTER1_CFG_BASE_IDX 0
#define regMMEA1_PERFCOUNTER_RSLT_CNTL 0x0540
#define regMMEA1_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0
#define regMMEA1_EDC_CNT 0x0546
#define regMMEA1_EDC_CNT_BASE_IDX 0
#define regMMEA1_EDC_CNT2 0x0547
#define regMMEA1_EDC_CNT2_BASE_IDX 0
#define regMMEA1_DSM_CNTL 0x0548
#define regMMEA1_DSM_CNTL_BASE_IDX 0
#define regMMEA1_DSM_CNTLA 0x0549
#define regMMEA1_DSM_CNTLA_BASE_IDX 0
#define regMMEA1_DSM_CNTLB 0x054a
#define regMMEA1_DSM_CNTLB_BASE_IDX 0
#define regMMEA1_DSM_CNTL2 0x054b
#define regMMEA1_DSM_CNTL2_BASE_IDX 0
#define regMMEA1_DSM_CNTL2A 0x054c
#define regMMEA1_DSM_CNTL2A_BASE_IDX 0
#define regMMEA1_DSM_CNTL2B 0x054d
#define regMMEA1_DSM_CNTL2B_BASE_IDX 0
#define regMMEA1_CGTT_CLK_CTRL 0x054f
#define regMMEA1_CGTT_CLK_CTRL_BASE_IDX 0
#define regMMEA1_EDC_MODE 0x0550
#define regMMEA1_EDC_MODE_BASE_IDX 0
#define regMMEA1_ERR_STATUS 0x0551
#define regMMEA1_ERR_STATUS_BASE_IDX 0
#define regMMEA1_MISC2 0x0552
#define regMMEA1_MISC2_BASE_IDX 0
#define regMMEA1_ADDRDEC_SELECT 0x0553
#define regMMEA1_ADDRDEC_SELECT_BASE_IDX 0
#define regMMEA1_EDC_CNT3 0x0554
#define regMMEA1_EDC_CNT3_BASE_IDX 0
#define regMMEA1_MISC_AON 0x0555
#define regMMEA1_MISC_AON_BASE_IDX 0
// addressBlock: mmhub_ea_mmeadec2
// base address: 0x69600
#define regMMEA2_DRAM_RD_CLI2GRP_MAP0 0x0580
#define regMMEA2_DRAM_RD_CLI2GRP_MAP0_BASE_IDX 0
#define regMMEA2_DRAM_RD_CLI2GRP_MAP1 0x0581
#define regMMEA2_DRAM_RD_CLI2GRP_MAP1_BASE_IDX 0
#define regMMEA2_DRAM_WR_CLI2GRP_MAP0 0x0582
#define regMMEA2_DRAM_WR_CLI2GRP_MAP0_BASE_IDX 0
#define regMMEA2_DRAM_WR_CLI2GRP_MAP1 0x0583
#define regMMEA2_DRAM_WR_CLI2GRP_MAP1_BASE_IDX 0
#define regMMEA2_DRAM_RD_GRP2VC_MAP 0x0584
#define regMMEA2_DRAM_RD_GRP2VC_MAP_BASE_IDX 0
#define regMMEA2_DRAM_WR_GRP2VC_MAP 0x0585
#define regMMEA2_DRAM_WR_GRP2VC_MAP_BASE_IDX 0
#define regMMEA2_DRAM_RD_LAZY 0x0586
#define regMMEA2_DRAM_RD_LAZY_BASE_IDX 0
#define regMMEA2_DRAM_WR_LAZY 0x0587
#define regMMEA2_DRAM_WR_LAZY_BASE_IDX 0
#define regMMEA2_DRAM_RD_CAM_CNTL 0x0588
#define regMMEA2_DRAM_RD_CAM_CNTL_BASE_IDX 0
#define regMMEA2_DRAM_WR_CAM_CNTL 0x0589
#define regMMEA2_DRAM_WR_CAM_CNTL_BASE_IDX 0
#define regMMEA2_DRAM_PAGE_BURST 0x058a
#define regMMEA2_DRAM_PAGE_BURST_BASE_IDX 0
#define regMMEA2_DRAM_RD_PRI_AGE 0x058b
#define regMMEA2_DRAM_RD_PRI_AGE_BASE_IDX 0
#define regMMEA2_DRAM_WR_PRI_AGE 0x058c
#define regMMEA2_DRAM_WR_PRI_AGE_BASE_IDX 0
#define regMMEA2_DRAM_RD_PRI_QUEUING 0x058d
#define regMMEA2_DRAM_RD_PRI_QUEUING_BASE_IDX 0
#define regMMEA2_DRAM_WR_PRI_QUEUING 0x058e
#define regMMEA2_DRAM_WR_PRI_QUEUING_BASE_IDX 0
#define regMMEA2_DRAM_RD_PRI_FIXED 0x058f
#define regMMEA2_DRAM_RD_PRI_FIXED_BASE_IDX 0
#define regMMEA2_DRAM_WR_PRI_FIXED 0x0590
#define regMMEA2_DRAM_WR_PRI_FIXED_BASE_IDX 0
#define regMMEA2_DRAM_RD_PRI_URGENCY 0x0591
#define regMMEA2_DRAM_RD_PRI_URGENCY_BASE_IDX 0
#define regMMEA2_DRAM_WR_PRI_URGENCY 0x0592
#define regMMEA2_DRAM_WR_PRI_URGENCY_BASE_IDX 0
#define regMMEA2_DRAM_RD_PRI_QUANT_PRI1 0x0593
#define regMMEA2_DRAM_RD_PRI_QUANT_PRI1_BASE_IDX 0
#define regMMEA2_DRAM_RD_PRI_QUANT_PRI2 0x0594
#define regMMEA2_DRAM_RD_PRI_QUANT_PRI2_BASE_IDX 0
#define regMMEA2_DRAM_RD_PRI_QUANT_PRI3 0x0595
#define regMMEA2_DRAM_RD_PRI_QUANT_PRI3_BASE_IDX 0
#define regMMEA2_DRAM_WR_PRI_QUANT_PRI1 0x0596
#define regMMEA2_DRAM_WR_PRI_QUANT_PRI1_BASE_IDX 0
#define regMMEA2_DRAM_WR_PRI_QUANT_PRI2 0x0597
#define regMMEA2_DRAM_WR_PRI_QUANT_PRI2_BASE_IDX 0
#define regMMEA2_DRAM_WR_PRI_QUANT_PRI3 0x0598
#define regMMEA2_DRAM_WR_PRI_QUANT_PRI3_BASE_IDX 0
#define regMMEA2_GMI_RD_CLI2GRP_MAP0 0x0599
#define regMMEA2_GMI_RD_CLI2GRP_MAP0_BASE_IDX 0
#define regMMEA2_GMI_RD_CLI2GRP_MAP1 0x059a
#define regMMEA2_GMI_RD_CLI2GRP_MAP1_BASE_IDX 0
#define regMMEA2_GMI_WR_CLI2GRP_MAP0 0x059b
#define regMMEA2_GMI_WR_CLI2GRP_MAP0_BASE_IDX 0
#define regMMEA2_GMI_WR_CLI2GRP_MAP1 0x059c
#define regMMEA2_GMI_WR_CLI2GRP_MAP1_BASE_IDX 0
#define regMMEA2_GMI_RD_GRP2VC_MAP 0x059d
#define regMMEA2_GMI_RD_GRP2VC_MAP_BASE_IDX 0
#define regMMEA2_GMI_WR_GRP2VC_MAP 0x059e
#define regMMEA2_GMI_WR_GRP2VC_MAP_BASE_IDX 0
#define regMMEA2_GMI_RD_LAZY 0x059f
#define regMMEA2_GMI_RD_LAZY_BASE_IDX 0
#define regMMEA2_GMI_WR_LAZY 0x05a0
#define regMMEA2_GMI_WR_LAZY_BASE_IDX 0
#define regMMEA2_GMI_RD_CAM_CNTL 0x05a1
#define regMMEA2_GMI_RD_CAM_CNTL_BASE_IDX 0
#define regMMEA2_GMI_WR_CAM_CNTL 0x05a2
#define regMMEA2_GMI_WR_CAM_CNTL_BASE_IDX 0
#define regMMEA2_GMI_PAGE_BURST 0x05a3
#define regMMEA2_GMI_PAGE_BURST_BASE_IDX 0
#define regMMEA2_GMI_RD_PRI_AGE 0x05a4
#define regMMEA2_GMI_RD_PRI_AGE_BASE_IDX 0
#define regMMEA2_GMI_WR_PRI_AGE 0x05a5
#define regMMEA2_GMI_WR_PRI_AGE_BASE_IDX 0
#define regMMEA2_GMI_RD_PRI_QUEUING 0x05a6
#define regMMEA2_GMI_RD_PRI_QUEUING_BASE_IDX 0
#define regMMEA2_GMI_WR_PRI_QUEUING 0x05a7
#define regMMEA2_GMI_WR_PRI_QUEUING_BASE_IDX 0
#define regMMEA2_GMI_RD_PRI_FIXED 0x05a8
#define regMMEA2_GMI_RD_PRI_FIXED_BASE_IDX 0
#define regMMEA2_GMI_WR_PRI_FIXED 0x05a9
#define regMMEA2_GMI_WR_PRI_FIXED_BASE_IDX 0
#define regMMEA2_GMI_RD_PRI_URGENCY 0x05aa
#define regMMEA2_GMI_RD_PRI_URGENCY_BASE_IDX 0
#define regMMEA2_GMI_WR_PRI_URGENCY 0x05ab
#define regMMEA2_GMI_WR_PRI_URGENCY_BASE_IDX 0
#define regMMEA2_GMI_RD_PRI_URGENCY_MASKING 0x05ac
#define regMMEA2_GMI_RD_PRI_URGENCY_MASKING_BASE_IDX 0
#define regMMEA2_GMI_WR_PRI_URGENCY_MASKING 0x05ad
#define regMMEA2_GMI_WR_PRI_URGENCY_MASKING_BASE_IDX 0
#define regMMEA2_GMI_RD_PRI_QUANT_PRI1 0x05ae
#define regMMEA2_GMI_RD_PRI_QUANT_PRI1_BASE_IDX 0
#define regMMEA2_GMI_RD_PRI_QUANT_PRI2 0x05af
#define regMMEA2_GMI_RD_PRI_QUANT_PRI2_BASE_IDX 0
#define regMMEA2_GMI_RD_PRI_QUANT_PRI3 0x05b0
#define regMMEA2_GMI_RD_PRI_QUANT_PRI3_BASE_IDX 0
#define regMMEA2_GMI_WR_PRI_QUANT_PRI1 0x05b1
#define regMMEA2_GMI_WR_PRI_QUANT_PRI1_BASE_IDX 0
#define regMMEA2_GMI_WR_PRI_QUANT_PRI2 0x05b2
#define regMMEA2_GMI_WR_PRI_QUANT_PRI2_BASE_IDX 0
#define regMMEA2_GMI_WR_PRI_QUANT_PRI3 0x05b3
#define regMMEA2_GMI_WR_PRI_QUANT_PRI3_BASE_IDX 0
#define regMMEA2_ADDRNORM_BASE_ADDR0 0x05b4
#define regMMEA2_ADDRNORM_BASE_ADDR0_BASE_IDX 0
#define regMMEA2_ADDRNORM_LIMIT_ADDR0 0x05b5
#define regMMEA2_ADDRNORM_LIMIT_ADDR0_BASE_IDX 0
#define regMMEA2_ADDRNORM_BASE_ADDR1 0x05b6
#define regMMEA2_ADDRNORM_BASE_ADDR1_BASE_IDX 0
#define regMMEA2_ADDRNORM_LIMIT_ADDR1 0x05b7
#define regMMEA2_ADDRNORM_LIMIT_ADDR1_BASE_IDX 0
#define regMMEA2_ADDRNORM_OFFSET_ADDR1 0x05b8
#define regMMEA2_ADDRNORM_OFFSET_ADDR1_BASE_IDX 0
#define regMMEA2_ADDRNORM_BASE_ADDR2 0x05b9
#define regMMEA2_ADDRNORM_BASE_ADDR2_BASE_IDX 0
#define regMMEA2_ADDRNORM_LIMIT_ADDR2 0x05ba
#define regMMEA2_ADDRNORM_LIMIT_ADDR2_BASE_IDX 0
#define regMMEA2_ADDRNORM_BASE_ADDR3 0x05bb
#define regMMEA2_ADDRNORM_BASE_ADDR3_BASE_IDX 0
#define regMMEA2_ADDRNORM_LIMIT_ADDR3 0x05bc
#define regMMEA2_ADDRNORM_LIMIT_ADDR3_BASE_IDX 0
#define regMMEA2_ADDRNORM_OFFSET_ADDR3 0x05bd
#define regMMEA2_ADDRNORM_OFFSET_ADDR3_BASE_IDX 0
#define regMMEA2_ADDRNORM_MEGABASE_ADDR0 0x05be
#define regMMEA2_ADDRNORM_MEGABASE_ADDR0_BASE_IDX 0
#define regMMEA2_ADDRNORM_MEGALIMIT_ADDR0 0x05bf
#define regMMEA2_ADDRNORM_MEGALIMIT_ADDR0_BASE_IDX 0
#define regMMEA2_ADDRNORM_MEGABASE_ADDR1 0x05c0
#define regMMEA2_ADDRNORM_MEGABASE_ADDR1_BASE_IDX 0
#define regMMEA2_ADDRNORM_MEGALIMIT_ADDR1 0x05c1
#define regMMEA2_ADDRNORM_MEGALIMIT_ADDR1_BASE_IDX 0
#define regMMEA2_ADDRNORMDRAM_HOLE_CNTL 0x05c3
#define regMMEA2_ADDRNORMDRAM_HOLE_CNTL_BASE_IDX 0
#define regMMEA2_ADDRNORMGMI_HOLE_CNTL 0x05c4
#define regMMEA2_ADDRNORMGMI_HOLE_CNTL_BASE_IDX 0
#define regMMEA2_ADDRNORMDRAM_NP2_CHANNEL_CFG 0x05c5
#define regMMEA2_ADDRNORMDRAM_NP2_CHANNEL_CFG_BASE_IDX 0
#define regMMEA2_ADDRNORMGMI_NP2_CHANNEL_CFG 0x05c6
#define regMMEA2_ADDRNORMGMI_NP2_CHANNEL_CFG_BASE_IDX 0
#define regMMEA2_ADDRDEC_BANK_CFG 0x05c7
#define regMMEA2_ADDRDEC_BANK_CFG_BASE_IDX 0
#define regMMEA2_ADDRDEC_MISC_CFG 0x05c8
#define regMMEA2_ADDRDEC_MISC_CFG_BASE_IDX 0
#define regMMEA2_ADDRDECDRAM_HARVEST_ENABLE 0x05d3
#define regMMEA2_ADDRDECDRAM_HARVEST_ENABLE_BASE_IDX 0
#define regMMEA2_ADDRDECGMI_HARVEST_ENABLE 0x05de
#define regMMEA2_ADDRDECGMI_HARVEST_ENABLE_BASE_IDX 0
#define regMMEA2_ADDRDEC0_BASE_ADDR_CS0 0x05df
#define regMMEA2_ADDRDEC0_BASE_ADDR_CS0_BASE_IDX 0
#define regMMEA2_ADDRDEC0_BASE_ADDR_CS1 0x05e0
#define regMMEA2_ADDRDEC0_BASE_ADDR_CS1_BASE_IDX 0
#define regMMEA2_ADDRDEC0_BASE_ADDR_CS2 0x05e1
#define regMMEA2_ADDRDEC0_BASE_ADDR_CS2_BASE_IDX 0
#define regMMEA2_ADDRDEC0_BASE_ADDR_CS3 0x05e2
#define regMMEA2_ADDRDEC0_BASE_ADDR_CS3_BASE_IDX 0
#define regMMEA2_ADDRDEC0_BASE_ADDR_SECCS0 0x05e3
#define regMMEA2_ADDRDEC0_BASE_ADDR_SECCS0_BASE_IDX 0
#define regMMEA2_ADDRDEC0_BASE_ADDR_SECCS1 0x05e4
#define regMMEA2_ADDRDEC0_BASE_ADDR_SECCS1_BASE_IDX 0
#define regMMEA2_ADDRDEC0_BASE_ADDR_SECCS2 0x05e5
#define regMMEA2_ADDRDEC0_BASE_ADDR_SECCS2_BASE_IDX 0
#define regMMEA2_ADDRDEC0_BASE_ADDR_SECCS3 0x05e6
#define regMMEA2_ADDRDEC0_BASE_ADDR_SECCS3_BASE_IDX 0
#define regMMEA2_ADDRDEC0_ADDR_MASK_CS01 0x05e7
#define regMMEA2_ADDRDEC0_ADDR_MASK_CS01_BASE_IDX 0
#define regMMEA2_ADDRDEC0_ADDR_MASK_CS23 0x05e8
#define regMMEA2_ADDRDEC0_ADDR_MASK_CS23_BASE_IDX 0
#define regMMEA2_ADDRDEC0_ADDR_MASK_SECCS01 0x05e9
#define regMMEA2_ADDRDEC0_ADDR_MASK_SECCS01_BASE_IDX 0
#define regMMEA2_ADDRDEC0_ADDR_MASK_SECCS23 0x05ea
#define regMMEA2_ADDRDEC0_ADDR_MASK_SECCS23_BASE_IDX 0
#define regMMEA2_ADDRDEC0_ADDR_CFG_CS01 0x05eb
#define regMMEA2_ADDRDEC0_ADDR_CFG_CS01_BASE_IDX 0
#define regMMEA2_ADDRDEC0_ADDR_CFG_CS23 0x05ec
#define regMMEA2_ADDRDEC0_ADDR_CFG_CS23_BASE_IDX 0
#define regMMEA2_ADDRDEC0_ADDR_SEL_CS01 0x05ed
#define regMMEA2_ADDRDEC0_ADDR_SEL_CS01_BASE_IDX 0
#define regMMEA2_ADDRDEC0_ADDR_SEL_CS23 0x05ee
#define regMMEA2_ADDRDEC0_ADDR_SEL_CS23_BASE_IDX 0
#define regMMEA2_ADDRDEC0_ADDR_SEL2_CS01 0x05ef
#define regMMEA2_ADDRDEC0_ADDR_SEL2_CS01_BASE_IDX 0
#define regMMEA2_ADDRDEC0_ADDR_SEL2_CS23 0x05f0
#define regMMEA2_ADDRDEC0_ADDR_SEL2_CS23_BASE_IDX 0
#define regMMEA2_ADDRDEC0_COL_SEL_LO_CS01 0x05f1
#define regMMEA2_ADDRDEC0_COL_SEL_LO_CS01_BASE_IDX 0
#define regMMEA2_ADDRDEC0_COL_SEL_LO_CS23 0x05f2
#define regMMEA2_ADDRDEC0_COL_SEL_LO_CS23_BASE_IDX 0
#define regMMEA2_ADDRDEC0_COL_SEL_HI_CS01 0x05f3
#define regMMEA2_ADDRDEC0_COL_SEL_HI_CS01_BASE_IDX 0
#define regMMEA2_ADDRDEC0_COL_SEL_HI_CS23 0x05f4
#define regMMEA2_ADDRDEC0_COL_SEL_HI_CS23_BASE_IDX 0
#define regMMEA2_ADDRDEC0_RM_SEL_CS01 0x05f5
#define regMMEA2_ADDRDEC0_RM_SEL_CS01_BASE_IDX 0
#define regMMEA2_ADDRDEC0_RM_SEL_CS23 0x05f6
#define regMMEA2_ADDRDEC0_RM_SEL_CS23_BASE_IDX 0
#define regMMEA2_ADDRDEC0_RM_SEL_SECCS01 0x05f7
#define regMMEA2_ADDRDEC0_RM_SEL_SECCS01_BASE_IDX 0
#define regMMEA2_ADDRDEC0_RM_SEL_SECCS23 0x05f8
#define regMMEA2_ADDRDEC0_RM_SEL_SECCS23_BASE_IDX 0
#define regMMEA2_ADDRDEC1_BASE_ADDR_CS0 0x05f9
#define regMMEA2_ADDRDEC1_BASE_ADDR_CS0_BASE_IDX 0
#define regMMEA2_ADDRDEC1_BASE_ADDR_CS1 0x05fa
#define regMMEA2_ADDRDEC1_BASE_ADDR_CS1_BASE_IDX 0
#define regMMEA2_ADDRDEC1_BASE_ADDR_CS2 0x05fb
#define regMMEA2_ADDRDEC1_BASE_ADDR_CS2_BASE_IDX 0
#define regMMEA2_ADDRDEC1_BASE_ADDR_CS3 0x05fc
#define regMMEA2_ADDRDEC1_BASE_ADDR_CS3_BASE_IDX 0
#define regMMEA2_ADDRDEC1_BASE_ADDR_SECCS0 0x05fd
#define regMMEA2_ADDRDEC1_BASE_ADDR_SECCS0_BASE_IDX 0
#define regMMEA2_ADDRDEC1_BASE_ADDR_SECCS1 0x05fe
#define regMMEA2_ADDRDEC1_BASE_ADDR_SECCS1_BASE_IDX 0
#define regMMEA2_ADDRDEC1_BASE_ADDR_SECCS2 0x05ff
#define regMMEA2_ADDRDEC1_BASE_ADDR_SECCS2_BASE_IDX 0
#define regMMEA2_ADDRDEC1_BASE_ADDR_SECCS3 0x0600
#define regMMEA2_ADDRDEC1_BASE_ADDR_SECCS3_BASE_IDX 0
#define regMMEA2_ADDRDEC1_ADDR_MASK_CS01 0x0601
#define regMMEA2_ADDRDEC1_ADDR_MASK_CS01_BASE_IDX 0
#define regMMEA2_ADDRDEC1_ADDR_MASK_CS23 0x0602
#define regMMEA2_ADDRDEC1_ADDR_MASK_CS23_BASE_IDX 0
#define regMMEA2_ADDRDEC1_ADDR_MASK_SECCS01 0x0603
#define regMMEA2_ADDRDEC1_ADDR_MASK_SECCS01_BASE_IDX 0
#define regMMEA2_ADDRDEC1_ADDR_MASK_SECCS23 0x0604
#define regMMEA2_ADDRDEC1_ADDR_MASK_SECCS23_BASE_IDX 0
#define regMMEA2_ADDRDEC1_ADDR_CFG_CS01 0x0605
#define regMMEA2_ADDRDEC1_ADDR_CFG_CS01_BASE_IDX 0
#define regMMEA2_ADDRDEC1_ADDR_CFG_CS23 0x0606
#define regMMEA2_ADDRDEC1_ADDR_CFG_CS23_BASE_IDX 0
#define regMMEA2_ADDRDEC1_ADDR_SEL_CS01 0x0607
#define regMMEA2_ADDRDEC1_ADDR_SEL_CS01_BASE_IDX 0
#define regMMEA2_ADDRDEC1_ADDR_SEL_CS23 0x0608
#define regMMEA2_ADDRDEC1_ADDR_SEL_CS23_BASE_IDX 0
#define regMMEA2_ADDRDEC1_ADDR_SEL2_CS01 0x0609
#define regMMEA2_ADDRDEC1_ADDR_SEL2_CS01_BASE_IDX 0
#define regMMEA2_ADDRDEC1_ADDR_SEL2_CS23 0x060a
#define regMMEA2_ADDRDEC1_ADDR_SEL2_CS23_BASE_IDX 0
#define regMMEA2_ADDRDEC1_COL_SEL_LO_CS01 0x060b
#define regMMEA2_ADDRDEC1_COL_SEL_LO_CS01_BASE_IDX 0
#define regMMEA2_ADDRDEC1_COL_SEL_LO_CS23 0x060c
#define regMMEA2_ADDRDEC1_COL_SEL_LO_CS23_BASE_IDX 0
#define regMMEA2_ADDRDEC1_COL_SEL_HI_CS01 0x060d
#define regMMEA2_ADDRDEC1_COL_SEL_HI_CS01_BASE_IDX 0
#define regMMEA2_ADDRDEC1_COL_SEL_HI_CS23 0x060e
#define regMMEA2_ADDRDEC1_COL_SEL_HI_CS23_BASE_IDX 0
#define regMMEA2_ADDRDEC1_RM_SEL_CS01 0x060f
#define regMMEA2_ADDRDEC1_RM_SEL_CS01_BASE_IDX 0
#define regMMEA2_ADDRDEC1_RM_SEL_CS23 0x0610
#define regMMEA2_ADDRDEC1_RM_SEL_CS23_BASE_IDX 0
#define regMMEA2_ADDRDEC1_RM_SEL_SECCS01 0x0611
#define regMMEA2_ADDRDEC1_RM_SEL_SECCS01_BASE_IDX 0
#define regMMEA2_ADDRDEC1_RM_SEL_SECCS23 0x0612
#define regMMEA2_ADDRDEC1_RM_SEL_SECCS23_BASE_IDX 0
#define regMMEA2_ADDRDEC2_BASE_ADDR_CS0 0x0613
#define regMMEA2_ADDRDEC2_BASE_ADDR_CS0_BASE_IDX 0
#define regMMEA2_ADDRDEC2_BASE_ADDR_CS1 0x0614
#define regMMEA2_ADDRDEC2_BASE_ADDR_CS1_BASE_IDX 0
#define regMMEA2_ADDRDEC2_BASE_ADDR_CS2 0x0615
#define regMMEA2_ADDRDEC2_BASE_ADDR_CS2_BASE_IDX 0
#define regMMEA2_ADDRDEC2_BASE_ADDR_CS3 0x0616
#define regMMEA2_ADDRDEC2_BASE_ADDR_CS3_BASE_IDX 0
#define regMMEA2_ADDRDEC2_BASE_ADDR_SECCS0 0x0617
#define regMMEA2_ADDRDEC2_BASE_ADDR_SECCS0_BASE_IDX 0
#define regMMEA2_ADDRDEC2_BASE_ADDR_SECCS1 0x0618
#define regMMEA2_ADDRDEC2_BASE_ADDR_SECCS1_BASE_IDX 0
#define regMMEA2_ADDRDEC2_BASE_ADDR_SECCS2 0x0619
#define regMMEA2_ADDRDEC2_BASE_ADDR_SECCS2_BASE_IDX 0
#define regMMEA2_ADDRDEC2_BASE_ADDR_SECCS3 0x061a
#define regMMEA2_ADDRDEC2_BASE_ADDR_SECCS3_BASE_IDX 0
#define regMMEA2_ADDRDEC2_ADDR_MASK_CS01 0x061b
#define regMMEA2_ADDRDEC2_ADDR_MASK_CS01_BASE_IDX 0
#define regMMEA2_ADDRDEC2_ADDR_MASK_CS23 0x061c
#define regMMEA2_ADDRDEC2_ADDR_MASK_CS23_BASE_IDX 0
#define regMMEA2_ADDRDEC2_ADDR_MASK_SECCS01 0x061d
#define regMMEA2_ADDRDEC2_ADDR_MASK_SECCS01_BASE_IDX 0
#define regMMEA2_ADDRDEC2_ADDR_MASK_SECCS23 0x061e
#define regMMEA2_ADDRDEC2_ADDR_MASK_SECCS23_BASE_IDX 0
#define regMMEA2_ADDRDEC2_ADDR_CFG_CS01 0x061f
#define regMMEA2_ADDRDEC2_ADDR_CFG_CS01_BASE_IDX 0
#define regMMEA2_ADDRDEC2_ADDR_CFG_CS23 0x0620
#define regMMEA2_ADDRDEC2_ADDR_CFG_CS23_BASE_IDX 0
#define regMMEA2_ADDRDEC2_ADDR_SEL_CS01 0x0621
#define regMMEA2_ADDRDEC2_ADDR_SEL_CS01_BASE_IDX 0
#define regMMEA2_ADDRDEC2_ADDR_SEL_CS23 0x0622
#define regMMEA2_ADDRDEC2_ADDR_SEL_CS23_BASE_IDX 0
#define regMMEA2_ADDRDEC2_ADDR_SEL2_CS01 0x0623
#define regMMEA2_ADDRDEC2_ADDR_SEL2_CS01_BASE_IDX 0
#define regMMEA2_ADDRDEC2_ADDR_SEL2_CS23 0x0624
#define regMMEA2_ADDRDEC2_ADDR_SEL2_CS23_BASE_IDX 0
#define regMMEA2_ADDRDEC2_COL_SEL_LO_CS01 0x0625
#define regMMEA2_ADDRDEC2_COL_SEL_LO_CS01_BASE_IDX 0
#define regMMEA2_ADDRDEC2_COL_SEL_LO_CS23 0x0626
#define regMMEA2_ADDRDEC2_COL_SEL_LO_CS23_BASE_IDX 0
#define regMMEA2_ADDRDEC2_COL_SEL_HI_CS01 0x0627
#define regMMEA2_ADDRDEC2_COL_SEL_HI_CS01_BASE_IDX 0
#define regMMEA2_ADDRDEC2_COL_SEL_HI_CS23 0x0628
#define regMMEA2_ADDRDEC2_COL_SEL_HI_CS23_BASE_IDX 0
#define regMMEA2_ADDRDEC2_RM_SEL_CS01 0x0629
#define regMMEA2_ADDRDEC2_RM_SEL_CS01_BASE_IDX 0
#define regMMEA2_ADDRDEC2_RM_SEL_CS23 0x062a
#define regMMEA2_ADDRDEC2_RM_SEL_CS23_BASE_IDX 0
#define regMMEA2_ADDRDEC2_RM_SEL_SECCS01 0x062b
#define regMMEA2_ADDRDEC2_RM_SEL_SECCS01_BASE_IDX 0
#define regMMEA2_ADDRDEC2_RM_SEL_SECCS23 0x062c
#define regMMEA2_ADDRDEC2_RM_SEL_SECCS23_BASE_IDX 0
#define regMMEA2_ADDRNORMDRAM_GLOBAL_CNTL 0x062d
#define regMMEA2_ADDRNORMDRAM_GLOBAL_CNTL_BASE_IDX 0
#define regMMEA2_ADDRNORMGMI_GLOBAL_CNTL 0x062e
#define regMMEA2_ADDRNORMGMI_GLOBAL_CNTL_BASE_IDX 0
#define regMMEA2_ADDRNORM_MEGACONTROL_ADDR0 0x0651
#define regMMEA2_ADDRNORM_MEGACONTROL_ADDR0_BASE_IDX 0
#define regMMEA2_ADDRNORM_MEGACONTROL_ADDR1 0x0652
#define regMMEA2_ADDRNORM_MEGACONTROL_ADDR1_BASE_IDX 0
#define regMMEA2_ADDRNORMDRAM_MASKING 0x0653
#define regMMEA2_ADDRNORMDRAM_MASKING_BASE_IDX 0
#define regMMEA2_ADDRNORMGMI_MASKING 0x0654
#define regMMEA2_ADDRNORMGMI_MASKING_BASE_IDX 0
#define regMMEA2_IO_RD_CLI2GRP_MAP0 0x0655
#define regMMEA2_IO_RD_CLI2GRP_MAP0_BASE_IDX 0
#define regMMEA2_IO_RD_CLI2GRP_MAP1 0x0656
#define regMMEA2_IO_RD_CLI2GRP_MAP1_BASE_IDX 0
#define regMMEA2_IO_WR_CLI2GRP_MAP0 0x0657
#define regMMEA2_IO_WR_CLI2GRP_MAP0_BASE_IDX 0
#define regMMEA2_IO_WR_CLI2GRP_MAP1 0x0658
#define regMMEA2_IO_WR_CLI2GRP_MAP1_BASE_IDX 0
#define regMMEA2_IO_RD_COMBINE_FLUSH 0x0659
#define regMMEA2_IO_RD_COMBINE_FLUSH_BASE_IDX 0
#define regMMEA2_IO_WR_COMBINE_FLUSH 0x065a
#define regMMEA2_IO_WR_COMBINE_FLUSH_BASE_IDX 0
#define regMMEA2_IO_GROUP_BURST 0x065b
#define regMMEA2_IO_GROUP_BURST_BASE_IDX 0
#define regMMEA2_IO_RD_PRI_AGE 0x065c
#define regMMEA2_IO_RD_PRI_AGE_BASE_IDX 0
#define regMMEA2_IO_WR_PRI_AGE 0x065d
#define regMMEA2_IO_WR_PRI_AGE_BASE_IDX 0
#define regMMEA2_IO_RD_PRI_QUEUING 0x065e
#define regMMEA2_IO_RD_PRI_QUEUING_BASE_IDX 0
#define regMMEA2_IO_WR_PRI_QUEUING 0x065f
#define regMMEA2_IO_WR_PRI_QUEUING_BASE_IDX 0
#define regMMEA2_IO_RD_PRI_FIXED 0x0660
#define regMMEA2_IO_RD_PRI_FIXED_BASE_IDX 0
#define regMMEA2_IO_WR_PRI_FIXED 0x0661
#define regMMEA2_IO_WR_PRI_FIXED_BASE_IDX 0
#define regMMEA2_IO_RD_PRI_URGENCY 0x0662
#define regMMEA2_IO_RD_PRI_URGENCY_BASE_IDX 0
#define regMMEA2_IO_WR_PRI_URGENCY 0x0663
#define regMMEA2_IO_WR_PRI_URGENCY_BASE_IDX 0
#define regMMEA2_IO_RD_PRI_URGENCY_MASKING 0x0664
#define regMMEA2_IO_RD_PRI_URGENCY_MASKING_BASE_IDX 0
#define regMMEA2_IO_WR_PRI_URGENCY_MASKING 0x0665
#define regMMEA2_IO_WR_PRI_URGENCY_MASKING_BASE_IDX 0
#define regMMEA2_IO_RD_PRI_QUANT_PRI1 0x0666
#define regMMEA2_IO_RD_PRI_QUANT_PRI1_BASE_IDX 0
#define regMMEA2_IO_RD_PRI_QUANT_PRI2 0x0667
#define regMMEA2_IO_RD_PRI_QUANT_PRI2_BASE_IDX 0
#define regMMEA2_IO_RD_PRI_QUANT_PRI3 0x0668
#define regMMEA2_IO_RD_PRI_QUANT_PRI3_BASE_IDX 0
#define regMMEA2_IO_WR_PRI_QUANT_PRI1 0x0669
#define regMMEA2_IO_WR_PRI_QUANT_PRI1_BASE_IDX 0
#define regMMEA2_IO_WR_PRI_QUANT_PRI2 0x066a
#define regMMEA2_IO_WR_PRI_QUANT_PRI2_BASE_IDX 0
#define regMMEA2_IO_WR_PRI_QUANT_PRI3 0x066b
#define regMMEA2_IO_WR_PRI_QUANT_PRI3_BASE_IDX 0
#define regMMEA2_SDP_ARB_DRAM 0x066c
#define regMMEA2_SDP_ARB_DRAM_BASE_IDX 0
#define regMMEA2_SDP_ARB_GMI 0x066d
#define regMMEA2_SDP_ARB_GMI_BASE_IDX 0
#define regMMEA2_SDP_ARB_FINAL 0x066e
#define regMMEA2_SDP_ARB_FINAL_BASE_IDX 0
#define regMMEA2_SDP_DRAM_PRIORITY 0x066f
#define regMMEA2_SDP_DRAM_PRIORITY_BASE_IDX 0
#define regMMEA2_SDP_GMI_PRIORITY 0x0670
#define regMMEA2_SDP_GMI_PRIORITY_BASE_IDX 0
#define regMMEA2_SDP_IO_PRIORITY 0x0671
#define regMMEA2_SDP_IO_PRIORITY_BASE_IDX 0
#define regMMEA2_SDP_CREDITS 0x0672
#define regMMEA2_SDP_CREDITS_BASE_IDX 0
#define regMMEA2_SDP_TAG_RESERVE0 0x0673
#define regMMEA2_SDP_TAG_RESERVE0_BASE_IDX 0
#define regMMEA2_SDP_TAG_RESERVE1 0x0674
#define regMMEA2_SDP_TAG_RESERVE1_BASE_IDX 0
#define regMMEA2_SDP_VCC_RESERVE0 0x0675
#define regMMEA2_SDP_VCC_RESERVE0_BASE_IDX 0
#define regMMEA2_SDP_VCC_RESERVE1 0x0676
#define regMMEA2_SDP_VCC_RESERVE1_BASE_IDX 0
#define regMMEA2_SDP_VCD_RESERVE0 0x0677
#define regMMEA2_SDP_VCD_RESERVE0_BASE_IDX 0
#define regMMEA2_SDP_VCD_RESERVE1 0x0678
#define regMMEA2_SDP_VCD_RESERVE1_BASE_IDX 0
#define regMMEA2_SDP_REQ_CNTL 0x0679
#define regMMEA2_SDP_REQ_CNTL_BASE_IDX 0
#define regMMEA2_MISC 0x067a
#define regMMEA2_MISC_BASE_IDX 0
#define regMMEA2_LATENCY_SAMPLING 0x067b
#define regMMEA2_LATENCY_SAMPLING_BASE_IDX 0
#define regMMEA2_PERFCOUNTER_LO 0x067c
#define regMMEA2_PERFCOUNTER_LO_BASE_IDX 0
#define regMMEA2_PERFCOUNTER_HI 0x067d
#define regMMEA2_PERFCOUNTER_HI_BASE_IDX 0
#define regMMEA2_PERFCOUNTER0_CFG 0x067e
#define regMMEA2_PERFCOUNTER0_CFG_BASE_IDX 0
#define regMMEA2_PERFCOUNTER1_CFG 0x067f
#define regMMEA2_PERFCOUNTER1_CFG_BASE_IDX 0
#define regMMEA2_PERFCOUNTER_RSLT_CNTL 0x0680
#define regMMEA2_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0
#define regMMEA2_EDC_CNT 0x0686
#define regMMEA2_EDC_CNT_BASE_IDX 0
#define regMMEA2_EDC_CNT2 0x0687
#define regMMEA2_EDC_CNT2_BASE_IDX 0
#define regMMEA2_DSM_CNTL 0x0688
#define regMMEA2_DSM_CNTL_BASE_IDX 0
#define regMMEA2_DSM_CNTLA 0x0689
#define regMMEA2_DSM_CNTLA_BASE_IDX 0
#define regMMEA2_DSM_CNTLB 0x068a
#define regMMEA2_DSM_CNTLB_BASE_IDX 0
#define regMMEA2_DSM_CNTL2 0x068b
#define regMMEA2_DSM_CNTL2_BASE_IDX 0
#define regMMEA2_DSM_CNTL2A 0x068c
#define regMMEA2_DSM_CNTL2A_BASE_IDX 0
#define regMMEA2_DSM_CNTL2B 0x068d
#define regMMEA2_DSM_CNTL2B_BASE_IDX 0
#define regMMEA2_CGTT_CLK_CTRL 0x068f
#define regMMEA2_CGTT_CLK_CTRL_BASE_IDX 0
#define regMMEA2_EDC_MODE 0x0690
#define regMMEA2_EDC_MODE_BASE_IDX 0
#define regMMEA2_ERR_STATUS 0x0691
#define regMMEA2_ERR_STATUS_BASE_IDX 0
#define regMMEA2_MISC2 0x0692
#define regMMEA2_MISC2_BASE_IDX 0
#define regMMEA2_ADDRDEC_SELECT 0x0693
#define regMMEA2_ADDRDEC_SELECT_BASE_IDX 0
#define regMMEA2_EDC_CNT3 0x0694
#define regMMEA2_EDC_CNT3_BASE_IDX 0
#define regMMEA2_MISC_AON 0x0695
#define regMMEA2_MISC_AON_BASE_IDX 0
// addressBlock: mmhub_ea_mmeadec3
// base address: 0x69b00
#define regMMEA3_DRAM_RD_CLI2GRP_MAP0 0x06c0
#define regMMEA3_DRAM_RD_CLI2GRP_MAP0_BASE_IDX 0
#define regMMEA3_DRAM_RD_CLI2GRP_MAP1 0x06c1
#define regMMEA3_DRAM_RD_CLI2GRP_MAP1_BASE_IDX 0
#define regMMEA3_DRAM_WR_CLI2GRP_MAP0 0x06c2
#define regMMEA3_DRAM_WR_CLI2GRP_MAP0_BASE_IDX 0
#define regMMEA3_DRAM_WR_CLI2GRP_MAP1 0x06c3
#define regMMEA3_DRAM_WR_CLI2GRP_MAP1_BASE_IDX 0
#define regMMEA3_DRAM_RD_GRP2VC_MAP 0x06c4
#define regMMEA3_DRAM_RD_GRP2VC_MAP_BASE_IDX 0
#define regMMEA3_DRAM_WR_GRP2VC_MAP 0x06c5
#define regMMEA3_DRAM_WR_GRP2VC_MAP_BASE_IDX 0
#define regMMEA3_DRAM_RD_LAZY 0x06c6
#define regMMEA3_DRAM_RD_LAZY_BASE_IDX 0
#define regMMEA3_DRAM_WR_LAZY 0x06c7
#define regMMEA3_DRAM_WR_LAZY_BASE_IDX 0
#define regMMEA3_DRAM_RD_CAM_CNTL 0x06c8
#define regMMEA3_DRAM_RD_CAM_CNTL_BASE_IDX 0
#define regMMEA3_DRAM_WR_CAM_CNTL 0x06c9
#define regMMEA3_DRAM_WR_CAM_CNTL_BASE_IDX 0
#define regMMEA3_DRAM_PAGE_BURST 0x06ca
#define regMMEA3_DRAM_PAGE_BURST_BASE_IDX 0
#define regMMEA3_DRAM_RD_PRI_AGE 0x06cb
#define regMMEA3_DRAM_RD_PRI_AGE_BASE_IDX 0
#define regMMEA3_DRAM_WR_PRI_AGE 0x06cc
#define regMMEA3_DRAM_WR_PRI_AGE_BASE_IDX 0
#define regMMEA3_DRAM_RD_PRI_QUEUING 0x06cd
#define regMMEA3_DRAM_RD_PRI_QUEUING_BASE_IDX 0
#define regMMEA3_DRAM_WR_PRI_QUEUING 0x06ce
#define regMMEA3_DRAM_WR_PRI_QUEUING_BASE_IDX 0
#define regMMEA3_DRAM_RD_PRI_FIXED 0x06cf
#define regMMEA3_DRAM_RD_PRI_FIXED_BASE_IDX 0
#define regMMEA3_DRAM_WR_PRI_FIXED 0x06d0
#define regMMEA3_DRAM_WR_PRI_FIXED_BASE_IDX 0
#define regMMEA3_DRAM_RD_PRI_URGENCY 0x06d1
#define regMMEA3_DRAM_RD_PRI_URGENCY_BASE_IDX 0
#define regMMEA3_DRAM_WR_PRI_URGENCY 0x06d2
#define regMMEA3_DRAM_WR_PRI_URGENCY_BASE_IDX 0
#define regMMEA3_DRAM_RD_PRI_QUANT_PRI1 0x06d3
#define regMMEA3_DRAM_RD_PRI_QUANT_PRI1_BASE_IDX 0
#define regMMEA3_DRAM_RD_PRI_QUANT_PRI2 0x06d4
#define regMMEA3_DRAM_RD_PRI_QUANT_PRI2_BASE_IDX 0
#define regMMEA3_DRAM_RD_PRI_QUANT_PRI3 0x06d5
#define regMMEA3_DRAM_RD_PRI_QUANT_PRI3_BASE_IDX 0
#define regMMEA3_DRAM_WR_PRI_QUANT_PRI1 0x06d6
#define regMMEA3_DRAM_WR_PRI_QUANT_PRI1_BASE_IDX 0
#define regMMEA3_DRAM_WR_PRI_QUANT_PRI2 0x06d7
#define regMMEA3_DRAM_WR_PRI_QUANT_PRI2_BASE_IDX 0
#define regMMEA3_DRAM_WR_PRI_QUANT_PRI3 0x06d8
#define regMMEA3_DRAM_WR_PRI_QUANT_PRI3_BASE_IDX 0
#define regMMEA3_GMI_RD_CLI2GRP_MAP0 0x06d9
#define regMMEA3_GMI_RD_CLI2GRP_MAP0_BASE_IDX 0
#define regMMEA3_GMI_RD_CLI2GRP_MAP1 0x06da
#define regMMEA3_GMI_RD_CLI2GRP_MAP1_BASE_IDX 0
#define regMMEA3_GMI_WR_CLI2GRP_MAP0 0x06db
#define regMMEA3_GMI_WR_CLI2GRP_MAP0_BASE_IDX 0
#define regMMEA3_GMI_WR_CLI2GRP_MAP1 0x06dc
#define regMMEA3_GMI_WR_CLI2GRP_MAP1_BASE_IDX 0
#define regMMEA3_GMI_RD_GRP2VC_MAP 0x06dd
#define regMMEA3_GMI_RD_GRP2VC_MAP_BASE_IDX 0
#define regMMEA3_GMI_WR_GRP2VC_MAP 0x06de
#define regMMEA3_GMI_WR_GRP2VC_MAP_BASE_IDX 0
#define regMMEA3_GMI_RD_LAZY 0x06df
#define regMMEA3_GMI_RD_LAZY_BASE_IDX 0
#define regMMEA3_GMI_WR_LAZY 0x06e0
#define regMMEA3_GMI_WR_LAZY_BASE_IDX 0
#define regMMEA3_GMI_RD_CAM_CNTL 0x06e1
#define regMMEA3_GMI_RD_CAM_CNTL_BASE_IDX 0
#define regMMEA3_GMI_WR_CAM_CNTL 0x06e2
#define regMMEA3_GMI_WR_CAM_CNTL_BASE_IDX 0
#define regMMEA3_GMI_PAGE_BURST 0x06e3
#define regMMEA3_GMI_PAGE_BURST_BASE_IDX 0
#define regMMEA3_GMI_RD_PRI_AGE 0x06e4
#define regMMEA3_GMI_RD_PRI_AGE_BASE_IDX 0
#define regMMEA3_GMI_WR_PRI_AGE 0x06e5
#define regMMEA3_GMI_WR_PRI_AGE_BASE_IDX 0
#define regMMEA3_GMI_RD_PRI_QUEUING 0x06e6
#define regMMEA3_GMI_RD_PRI_QUEUING_BASE_IDX 0
#define regMMEA3_GMI_WR_PRI_QUEUING 0x06e7
#define regMMEA3_GMI_WR_PRI_QUEUING_BASE_IDX 0
#define regMMEA3_GMI_RD_PRI_FIXED 0x06e8
#define regMMEA3_GMI_RD_PRI_FIXED_BASE_IDX 0
#define regMMEA3_GMI_WR_PRI_FIXED 0x06e9
#define regMMEA3_GMI_WR_PRI_FIXED_BASE_IDX 0
#define regMMEA3_GMI_RD_PRI_URGENCY 0x06ea
#define regMMEA3_GMI_RD_PRI_URGENCY_BASE_IDX 0
#define regMMEA3_GMI_WR_PRI_URGENCY 0x06eb
#define regMMEA3_GMI_WR_PRI_URGENCY_BASE_IDX 0
#define regMMEA3_GMI_RD_PRI_URGENCY_MASKING 0x06ec
#define regMMEA3_GMI_RD_PRI_URGENCY_MASKING_BASE_IDX 0
#define regMMEA3_GMI_WR_PRI_URGENCY_MASKING 0x06ed
#define regMMEA3_GMI_WR_PRI_URGENCY_MASKING_BASE_IDX 0
#define regMMEA3_GMI_RD_PRI_QUANT_PRI1 0x06ee
#define regMMEA3_GMI_RD_PRI_QUANT_PRI1_BASE_IDX 0
#define regMMEA3_GMI_RD_PRI_QUANT_PRI2 0x06ef
#define regMMEA3_GMI_RD_PRI_QUANT_PRI2_BASE_IDX 0
#define regMMEA3_GMI_RD_PRI_QUANT_PRI3 0x06f0
#define regMMEA3_GMI_RD_PRI_QUANT_PRI3_BASE_IDX 0
#define regMMEA3_GMI_WR_PRI_QUANT_PRI1 0x06f1
#define regMMEA3_GMI_WR_PRI_QUANT_PRI1_BASE_IDX 0
#define regMMEA3_GMI_WR_PRI_QUANT_PRI2 0x06f2
#define regMMEA3_GMI_WR_PRI_QUANT_PRI2_BASE_IDX 0
#define regMMEA3_GMI_WR_PRI_QUANT_PRI3 0x06f3
#define regMMEA3_GMI_WR_PRI_QUANT_PRI3_BASE_IDX 0
#define regMMEA3_ADDRNORM_BASE_ADDR0 0x06f4
#define regMMEA3_ADDRNORM_BASE_ADDR0_BASE_IDX 0
#define regMMEA3_ADDRNORM_LIMIT_ADDR0 0x06f5
#define regMMEA3_ADDRNORM_LIMIT_ADDR0_BASE_IDX 0
#define regMMEA3_ADDRNORM_BASE_ADDR1 0x06f6
#define regMMEA3_ADDRNORM_BASE_ADDR1_BASE_IDX 0
#define regMMEA3_ADDRNORM_LIMIT_ADDR1 0x06f7
#define regMMEA3_ADDRNORM_LIMIT_ADDR1_BASE_IDX 0
#define regMMEA3_ADDRNORM_OFFSET_ADDR1 0x06f8
#define regMMEA3_ADDRNORM_OFFSET_ADDR1_BASE_IDX 0
#define regMMEA3_ADDRNORM_BASE_ADDR2 0x06f9
#define regMMEA3_ADDRNORM_BASE_ADDR2_BASE_IDX 0
#define regMMEA3_ADDRNORM_LIMIT_ADDR2 0x06fa
#define regMMEA3_ADDRNORM_LIMIT_ADDR2_BASE_IDX 0
#define regMMEA3_ADDRNORM_BASE_ADDR3 0x06fb
#define regMMEA3_ADDRNORM_BASE_ADDR3_BASE_IDX 0
#define regMMEA3_ADDRNORM_LIMIT_ADDR3 0x06fc
#define regMMEA3_ADDRNORM_LIMIT_ADDR3_BASE_IDX 0
#define regMMEA3_ADDRNORM_OFFSET_ADDR3 0x06fd
#define regMMEA3_ADDRNORM_OFFSET_ADDR3_BASE_IDX 0
#define regMMEA3_ADDRNORM_MEGABASE_ADDR0 0x06fe
#define regMMEA3_ADDRNORM_MEGABASE_ADDR0_BASE_IDX 0
#define regMMEA3_ADDRNORM_MEGALIMIT_ADDR0 0x06ff
#define regMMEA3_ADDRNORM_MEGALIMIT_ADDR0_BASE_IDX 0
#define regMMEA3_ADDRNORM_MEGABASE_ADDR1 0x0700
#define regMMEA3_ADDRNORM_MEGABASE_ADDR1_BASE_IDX 0
#define regMMEA3_ADDRNORM_MEGALIMIT_ADDR1 0x0701
#define regMMEA3_ADDRNORM_MEGALIMIT_ADDR1_BASE_IDX 0
#define regMMEA3_ADDRNORMDRAM_HOLE_CNTL 0x0703
#define regMMEA3_ADDRNORMDRAM_HOLE_CNTL_BASE_IDX 0
#define regMMEA3_ADDRNORMGMI_HOLE_CNTL 0x0704
#define regMMEA3_ADDRNORMGMI_HOLE_CNTL_BASE_IDX 0
#define regMMEA3_ADDRNORMDRAM_NP2_CHANNEL_CFG 0x0705
#define regMMEA3_ADDRNORMDRAM_NP2_CHANNEL_CFG_BASE_IDX 0
#define regMMEA3_ADDRNORMGMI_NP2_CHANNEL_CFG 0x0706
#define regMMEA3_ADDRNORMGMI_NP2_CHANNEL_CFG_BASE_IDX 0
#define regMMEA3_ADDRDEC_BANK_CFG 0x0707
#define regMMEA3_ADDRDEC_BANK_CFG_BASE_IDX 0
#define regMMEA3_ADDRDEC_MISC_CFG 0x0708
#define regMMEA3_ADDRDEC_MISC_CFG_BASE_IDX 0
#define regMMEA3_ADDRDECDRAM_HARVEST_ENABLE 0x0713
#define regMMEA3_ADDRDECDRAM_HARVEST_ENABLE_BASE_IDX 0
#define regMMEA3_ADDRDECGMI_HARVEST_ENABLE 0x071e
#define regMMEA3_ADDRDECGMI_HARVEST_ENABLE_BASE_IDX 0
#define regMMEA3_ADDRDEC0_BASE_ADDR_CS0 0x071f
#define regMMEA3_ADDRDEC0_BASE_ADDR_CS0_BASE_IDX 0
#define regMMEA3_ADDRDEC0_BASE_ADDR_CS1 0x0720
#define regMMEA3_ADDRDEC0_BASE_ADDR_CS1_BASE_IDX 0
#define regMMEA3_ADDRDEC0_BASE_ADDR_CS2 0x0721
#define regMMEA3_ADDRDEC0_BASE_ADDR_CS2_BASE_IDX 0
#define regMMEA3_ADDRDEC0_BASE_ADDR_CS3 0x0722
#define regMMEA3_ADDRDEC0_BASE_ADDR_CS3_BASE_IDX 0
#define regMMEA3_ADDRDEC0_BASE_ADDR_SECCS0 0x0723
#define regMMEA3_ADDRDEC0_BASE_ADDR_SECCS0_BASE_IDX 0
#define regMMEA3_ADDRDEC0_BASE_ADDR_SECCS1 0x0724
#define regMMEA3_ADDRDEC0_BASE_ADDR_SECCS1_BASE_IDX 0
#define regMMEA3_ADDRDEC0_BASE_ADDR_SECCS2 0x0725
#define regMMEA3_ADDRDEC0_BASE_ADDR_SECCS2_BASE_IDX 0
#define regMMEA3_ADDRDEC0_BASE_ADDR_SECCS3 0x0726
#define regMMEA3_ADDRDEC0_BASE_ADDR_SECCS3_BASE_IDX 0
#define regMMEA3_ADDRDEC0_ADDR_MASK_CS01 0x0727
#define regMMEA3_ADDRDEC0_ADDR_MASK_CS01_BASE_IDX 0
#define regMMEA3_ADDRDEC0_ADDR_MASK_CS23 0x0728
#define regMMEA3_ADDRDEC0_ADDR_MASK_CS23_BASE_IDX 0
#define regMMEA3_ADDRDEC0_ADDR_MASK_SECCS01 0x0729
#define regMMEA3_ADDRDEC0_ADDR_MASK_SECCS01_BASE_IDX 0
#define regMMEA3_ADDRDEC0_ADDR_MASK_SECCS23 0x072a
#define regMMEA3_ADDRDEC0_ADDR_MASK_SECCS23_BASE_IDX 0
#define regMMEA3_ADDRDEC0_ADDR_CFG_CS01 0x072b
#define regMMEA3_ADDRDEC0_ADDR_CFG_CS01_BASE_IDX 0
#define regMMEA3_ADDRDEC0_ADDR_CFG_CS23 0x072c
#define regMMEA3_ADDRDEC0_ADDR_CFG_CS23_BASE_IDX 0
#define regMMEA3_ADDRDEC0_ADDR_SEL_CS01 0x072d
#define regMMEA3_ADDRDEC0_ADDR_SEL_CS01_BASE_IDX 0
#define regMMEA3_ADDRDEC0_ADDR_SEL_CS23 0x072e
#define regMMEA3_ADDRDEC0_ADDR_SEL_CS23_BASE_IDX 0
#define regMMEA3_ADDRDEC0_ADDR_SEL2_CS01 0x072f
#define regMMEA3_ADDRDEC0_ADDR_SEL2_CS01_BASE_IDX 0
#define regMMEA3_ADDRDEC0_ADDR_SEL2_CS23 0x0730
#define regMMEA3_ADDRDEC0_ADDR_SEL2_CS23_BASE_IDX 0
#define regMMEA3_ADDRDEC0_COL_SEL_LO_CS01 0x0731
#define regMMEA3_ADDRDEC0_COL_SEL_LO_CS01_BASE_IDX 0
#define regMMEA3_ADDRDEC0_COL_SEL_LO_CS23 0x0732
#define regMMEA3_ADDRDEC0_COL_SEL_LO_CS23_BASE_IDX 0
#define regMMEA3_ADDRDEC0_COL_SEL_HI_CS01 0x0733
#define regMMEA3_ADDRDEC0_COL_SEL_HI_CS01_BASE_IDX 0
#define regMMEA3_ADDRDEC0_COL_SEL_HI_CS23 0x0734
#define regMMEA3_ADDRDEC0_COL_SEL_HI_CS23_BASE_IDX 0
#define regMMEA3_ADDRDEC0_RM_SEL_CS01 0x0735
#define regMMEA3_ADDRDEC0_RM_SEL_CS01_BASE_IDX 0
#define regMMEA3_ADDRDEC0_RM_SEL_CS23 0x0736
#define regMMEA3_ADDRDEC0_RM_SEL_CS23_BASE_IDX 0
#define regMMEA3_ADDRDEC0_RM_SEL_SECCS01 0x0737
#define regMMEA3_ADDRDEC0_RM_SEL_SECCS01_BASE_IDX 0
#define regMMEA3_ADDRDEC0_RM_SEL_SECCS23 0x0738
#define regMMEA3_ADDRDEC0_RM_SEL_SECCS23_BASE_IDX 0
#define regMMEA3_ADDRDEC1_BASE_ADDR_CS0 0x0739
#define regMMEA3_ADDRDEC1_BASE_ADDR_CS0_BASE_IDX 0
#define regMMEA3_ADDRDEC1_BASE_ADDR_CS1 0x073a
#define regMMEA3_ADDRDEC1_BASE_ADDR_CS1_BASE_IDX 0
#define regMMEA3_ADDRDEC1_BASE_ADDR_CS2 0x073b
#define regMMEA3_ADDRDEC1_BASE_ADDR_CS2_BASE_IDX 0
#define regMMEA3_ADDRDEC1_BASE_ADDR_CS3 0x073c
#define regMMEA3_ADDRDEC1_BASE_ADDR_CS3_BASE_IDX 0
#define regMMEA3_ADDRDEC1_BASE_ADDR_SECCS0 0x073d
#define regMMEA3_ADDRDEC1_BASE_ADDR_SECCS0_BASE_IDX 0
#define regMMEA3_ADDRDEC1_BASE_ADDR_SECCS1 0x073e
#define regMMEA3_ADDRDEC1_BASE_ADDR_SECCS1_BASE_IDX 0
#define regMMEA3_ADDRDEC1_BASE_ADDR_SECCS2 0x073f
#define regMMEA3_ADDRDEC1_BASE_ADDR_SECCS2_BASE_IDX 0
#define regMMEA3_ADDRDEC1_BASE_ADDR_SECCS3 0x0740
#define regMMEA3_ADDRDEC1_BASE_ADDR_SECCS3_BASE_IDX 0
#define regMMEA3_ADDRDEC1_ADDR_MASK_CS01 0x0741
#define regMMEA3_ADDRDEC1_ADDR_MASK_CS01_BASE_IDX 0
#define regMMEA3_ADDRDEC1_ADDR_MASK_CS23 0x0742
#define regMMEA3_ADDRDEC1_ADDR_MASK_CS23_BASE_IDX 0
#define regMMEA3_ADDRDEC1_ADDR_MASK_SECCS01 0x0743
#define regMMEA3_ADDRDEC1_ADDR_MASK_SECCS01_BASE_IDX 0
#define regMMEA3_ADDRDEC1_ADDR_MASK_SECCS23 0x0744
#define regMMEA3_ADDRDEC1_ADDR_MASK_SECCS23_BASE_IDX 0
#define regMMEA3_ADDRDEC1_ADDR_CFG_CS01 0x0745
#define regMMEA3_ADDRDEC1_ADDR_CFG_CS01_BASE_IDX 0
#define regMMEA3_ADDRDEC1_ADDR_CFG_CS23 0x0746
#define regMMEA3_ADDRDEC1_ADDR_CFG_CS23_BASE_IDX 0
#define regMMEA3_ADDRDEC1_ADDR_SEL_CS01 0x0747
#define regMMEA3_ADDRDEC1_ADDR_SEL_CS01_BASE_IDX 0
#define regMMEA3_ADDRDEC1_ADDR_SEL_CS23 0x0748
#define regMMEA3_ADDRDEC1_ADDR_SEL_CS23_BASE_IDX 0
#define regMMEA3_ADDRDEC1_ADDR_SEL2_CS01 0x0749
#define regMMEA3_ADDRDEC1_ADDR_SEL2_CS01_BASE_IDX 0
#define regMMEA3_ADDRDEC1_ADDR_SEL2_CS23 0x074a
#define regMMEA3_ADDRDEC1_ADDR_SEL2_CS23_BASE_IDX 0
#define regMMEA3_ADDRDEC1_COL_SEL_LO_CS01 0x074b
#define regMMEA3_ADDRDEC1_COL_SEL_LO_CS01_BASE_IDX 0
#define regMMEA3_ADDRDEC1_COL_SEL_LO_CS23 0x074c
#define regMMEA3_ADDRDEC1_COL_SEL_LO_CS23_BASE_IDX 0
#define regMMEA3_ADDRDEC1_COL_SEL_HI_CS01 0x074d
#define regMMEA3_ADDRDEC1_COL_SEL_HI_CS01_BASE_IDX 0
#define regMMEA3_ADDRDEC1_COL_SEL_HI_CS23 0x074e
#define regMMEA3_ADDRDEC1_COL_SEL_HI_CS23_BASE_IDX 0
#define regMMEA3_ADDRDEC1_RM_SEL_CS01 0x074f
#define regMMEA3_ADDRDEC1_RM_SEL_CS01_BASE_IDX 0
#define regMMEA3_ADDRDEC1_RM_SEL_CS23 0x0750
#define regMMEA3_ADDRDEC1_RM_SEL_CS23_BASE_IDX 0
#define regMMEA3_ADDRDEC1_RM_SEL_SECCS01 0x0751
#define regMMEA3_ADDRDEC1_RM_SEL_SECCS01_BASE_IDX 0
#define regMMEA3_ADDRDEC1_RM_SEL_SECCS23 0x0752
#define regMMEA3_ADDRDEC1_RM_SEL_SECCS23_BASE_IDX 0
#define regMMEA3_ADDRDEC2_BASE_ADDR_CS0 0x0753
#define regMMEA3_ADDRDEC2_BASE_ADDR_CS0_BASE_IDX 0
#define regMMEA3_ADDRDEC2_BASE_ADDR_CS1 0x0754
#define regMMEA3_ADDRDEC2_BASE_ADDR_CS1_BASE_IDX 0
#define regMMEA3_ADDRDEC2_BASE_ADDR_CS2 0x0755
#define regMMEA3_ADDRDEC2_BASE_ADDR_CS2_BASE_IDX 0
#define regMMEA3_ADDRDEC2_BASE_ADDR_CS3 0x0756
#define regMMEA3_ADDRDEC2_BASE_ADDR_CS3_BASE_IDX 0
#define regMMEA3_ADDRDEC2_BASE_ADDR_SECCS0 0x0757
#define regMMEA3_ADDRDEC2_BASE_ADDR_SECCS0_BASE_IDX 0
#define regMMEA3_ADDRDEC2_BASE_ADDR_SECCS1 0x0758
#define regMMEA3_ADDRDEC2_BASE_ADDR_SECCS1_BASE_IDX 0
#define regMMEA3_ADDRDEC2_BASE_ADDR_SECCS2 0x0759
#define regMMEA3_ADDRDEC2_BASE_ADDR_SECCS2_BASE_IDX 0
#define regMMEA3_ADDRDEC2_BASE_ADDR_SECCS3 0x075a
#define regMMEA3_ADDRDEC2_BASE_ADDR_SECCS3_BASE_IDX 0
#define regMMEA3_ADDRDEC2_ADDR_MASK_CS01 0x075b
#define regMMEA3_ADDRDEC2_ADDR_MASK_CS01_BASE_IDX 0
#define regMMEA3_ADDRDEC2_ADDR_MASK_CS23 0x075c
#define regMMEA3_ADDRDEC2_ADDR_MASK_CS23_BASE_IDX 0
#define regMMEA3_ADDRDEC2_ADDR_MASK_SECCS01 0x075d
#define regMMEA3_ADDRDEC2_ADDR_MASK_SECCS01_BASE_IDX 0
#define regMMEA3_ADDRDEC2_ADDR_MASK_SECCS23 0x075e
#define regMMEA3_ADDRDEC2_ADDR_MASK_SECCS23_BASE_IDX 0
#define regMMEA3_ADDRDEC2_ADDR_CFG_CS01 0x075f
#define regMMEA3_ADDRDEC2_ADDR_CFG_CS01_BASE_IDX 0
#define regMMEA3_ADDRDEC2_ADDR_CFG_CS23 0x0760
#define regMMEA3_ADDRDEC2_ADDR_CFG_CS23_BASE_IDX 0
#define regMMEA3_ADDRDEC2_ADDR_SEL_CS01 0x0761
#define regMMEA3_ADDRDEC2_ADDR_SEL_CS01_BASE_IDX 0
#define regMMEA3_ADDRDEC2_ADDR_SEL_CS23 0x0762
#define regMMEA3_ADDRDEC2_ADDR_SEL_CS23_BASE_IDX 0
#define regMMEA3_ADDRDEC2_ADDR_SEL2_CS01 0x0763
#define regMMEA3_ADDRDEC2_ADDR_SEL2_CS01_BASE_IDX 0
#define regMMEA3_ADDRDEC2_ADDR_SEL2_CS23 0x0764
#define regMMEA3_ADDRDEC2_ADDR_SEL2_CS23_BASE_IDX 0
#define regMMEA3_ADDRDEC2_COL_SEL_LO_CS01 0x0765
#define regMMEA3_ADDRDEC2_COL_SEL_LO_CS01_BASE_IDX 0
#define regMMEA3_ADDRDEC2_COL_SEL_LO_CS23 0x0766
#define regMMEA3_ADDRDEC2_COL_SEL_LO_CS23_BASE_IDX 0
#define regMMEA3_ADDRDEC2_COL_SEL_HI_CS01 0x0767
#define regMMEA3_ADDRDEC2_COL_SEL_HI_CS01_BASE_IDX 0
#define regMMEA3_ADDRDEC2_COL_SEL_HI_CS23 0x0768
#define regMMEA3_ADDRDEC2_COL_SEL_HI_CS23_BASE_IDX 0
#define regMMEA3_ADDRDEC2_RM_SEL_CS01 0x0769
#define regMMEA3_ADDRDEC2_RM_SEL_CS01_BASE_IDX 0
#define regMMEA3_ADDRDEC2_RM_SEL_CS23 0x076a
#define regMMEA3_ADDRDEC2_RM_SEL_CS23_BASE_IDX 0
#define regMMEA3_ADDRDEC2_RM_SEL_SECCS01 0x076b
#define regMMEA3_ADDRDEC2_RM_SEL_SECCS01_BASE_IDX 0
#define regMMEA3_ADDRDEC2_RM_SEL_SECCS23 0x076c
#define regMMEA3_ADDRDEC2_RM_SEL_SECCS23_BASE_IDX 0
#define regMMEA3_ADDRNORMDRAM_GLOBAL_CNTL 0x076d
#define regMMEA3_ADDRNORMDRAM_GLOBAL_CNTL_BASE_IDX 0
#define regMMEA3_ADDRNORMGMI_GLOBAL_CNTL 0x076e
#define regMMEA3_ADDRNORMGMI_GLOBAL_CNTL_BASE_IDX 0
#define regMMEA3_ADDRNORM_MEGACONTROL_ADDR0 0x0791
#define regMMEA3_ADDRNORM_MEGACONTROL_ADDR0_BASE_IDX 0
#define regMMEA3_ADDRNORM_MEGACONTROL_ADDR1 0x0792
#define regMMEA3_ADDRNORM_MEGACONTROL_ADDR1_BASE_IDX 0
#define regMMEA3_ADDRNORMDRAM_MASKING 0x0793
#define regMMEA3_ADDRNORMDRAM_MASKING_BASE_IDX 0
#define regMMEA3_ADDRNORMGMI_MASKING 0x0794
#define regMMEA3_ADDRNORMGMI_MASKING_BASE_IDX 0
#define regMMEA3_IO_RD_CLI2GRP_MAP0 0x0795
#define regMMEA3_IO_RD_CLI2GRP_MAP0_BASE_IDX 0
#define regMMEA3_IO_RD_CLI2GRP_MAP1 0x0796
#define regMMEA3_IO_RD_CLI2GRP_MAP1_BASE_IDX 0
#define regMMEA3_IO_WR_CLI2GRP_MAP0 0x0797
#define regMMEA3_IO_WR_CLI2GRP_MAP0_BASE_IDX 0
#define regMMEA3_IO_WR_CLI2GRP_MAP1 0x0798
#define regMMEA3_IO_WR_CLI2GRP_MAP1_BASE_IDX 0
#define regMMEA3_IO_RD_COMBINE_FLUSH 0x0799
#define regMMEA3_IO_RD_COMBINE_FLUSH_BASE_IDX 0
#define regMMEA3_IO_WR_COMBINE_FLUSH 0x079a
#define regMMEA3_IO_WR_COMBINE_FLUSH_BASE_IDX 0
#define regMMEA3_IO_GROUP_BURST 0x079b
#define regMMEA3_IO_GROUP_BURST_BASE_IDX 0
#define regMMEA3_IO_RD_PRI_AGE 0x079c
#define regMMEA3_IO_RD_PRI_AGE_BASE_IDX 0
#define regMMEA3_IO_WR_PRI_AGE 0x079d
#define regMMEA3_IO_WR_PRI_AGE_BASE_IDX 0
#define regMMEA3_IO_RD_PRI_QUEUING 0x079e
#define regMMEA3_IO_RD_PRI_QUEUING_BASE_IDX 0
#define regMMEA3_IO_WR_PRI_QUEUING 0x079f
#define regMMEA3_IO_WR_PRI_QUEUING_BASE_IDX 0
#define regMMEA3_IO_RD_PRI_FIXED 0x07a0
#define regMMEA3_IO_RD_PRI_FIXED_BASE_IDX 0
#define regMMEA3_IO_WR_PRI_FIXED 0x07a1
#define regMMEA3_IO_WR_PRI_FIXED_BASE_IDX 0
#define regMMEA3_IO_RD_PRI_URGENCY 0x07a2
#define regMMEA3_IO_RD_PRI_URGENCY_BASE_IDX 0
#define regMMEA3_IO_WR_PRI_URGENCY 0x07a3
#define regMMEA3_IO_WR_PRI_URGENCY_BASE_IDX 0
#define regMMEA3_IO_RD_PRI_URGENCY_MASKING 0x07a4
#define regMMEA3_IO_RD_PRI_URGENCY_MASKING_BASE_IDX 0
#define regMMEA3_IO_WR_PRI_URGENCY_MASKING 0x07a5
#define regMMEA3_IO_WR_PRI_URGENCY_MASKING_BASE_IDX 0
#define regMMEA3_IO_RD_PRI_QUANT_PRI1 0x07a6
#define regMMEA3_IO_RD_PRI_QUANT_PRI1_BASE_IDX 0
#define regMMEA3_IO_RD_PRI_QUANT_PRI2 0x07a7
#define regMMEA3_IO_RD_PRI_QUANT_PRI2_BASE_IDX 0
#define regMMEA3_IO_RD_PRI_QUANT_PRI3 0x07a8
#define regMMEA3_IO_RD_PRI_QUANT_PRI3_BASE_IDX 0
#define regMMEA3_IO_WR_PRI_QUANT_PRI1 0x07a9
#define regMMEA3_IO_WR_PRI_QUANT_PRI1_BASE_IDX 0
#define regMMEA3_IO_WR_PRI_QUANT_PRI2 0x07aa
#define regMMEA3_IO_WR_PRI_QUANT_PRI2_BASE_IDX 0
#define regMMEA3_IO_WR_PRI_QUANT_PRI3 0x07ab
#define regMMEA3_IO_WR_PRI_QUANT_PRI3_BASE_IDX 0
#define regMMEA3_SDP_ARB_DRAM 0x07ac
#define regMMEA3_SDP_ARB_DRAM_BASE_IDX 0
#define regMMEA3_SDP_ARB_GMI 0x07ad
#define regMMEA3_SDP_ARB_GMI_BASE_IDX 0
#define regMMEA3_SDP_ARB_FINAL 0x07ae
#define regMMEA3_SDP_ARB_FINAL_BASE_IDX 0
#define regMMEA3_SDP_DRAM_PRIORITY 0x07af
#define regMMEA3_SDP_DRAM_PRIORITY_BASE_IDX 0
#define regMMEA3_SDP_GMI_PRIORITY 0x07b0
#define regMMEA3_SDP_GMI_PRIORITY_BASE_IDX 0
#define regMMEA3_SDP_IO_PRIORITY 0x07b1
#define regMMEA3_SDP_IO_PRIORITY_BASE_IDX 0
#define regMMEA3_SDP_CREDITS 0x07b2
#define regMMEA3_SDP_CREDITS_BASE_IDX 0
#define regMMEA3_SDP_TAG_RESERVE0 0x07b3
#define regMMEA3_SDP_TAG_RESERVE0_BASE_IDX 0
#define regMMEA3_SDP_TAG_RESERVE1 0x07b4
#define regMMEA3_SDP_TAG_RESERVE1_BASE_IDX 0
#define regMMEA3_SDP_VCC_RESERVE0 0x07b5
#define regMMEA3_SDP_VCC_RESERVE0_BASE_IDX 0
#define regMMEA3_SDP_VCC_RESERVE1 0x07b6
#define regMMEA3_SDP_VCC_RESERVE1_BASE_IDX 0
#define regMMEA3_SDP_VCD_RESERVE0 0x07b7
#define regMMEA3_SDP_VCD_RESERVE0_BASE_IDX 0
#define regMMEA3_SDP_VCD_RESERVE1 0x07b8
#define regMMEA3_SDP_VCD_RESERVE1_BASE_IDX 0
#define regMMEA3_SDP_REQ_CNTL 0x07b9
#define regMMEA3_SDP_REQ_CNTL_BASE_IDX 0
#define regMMEA3_MISC 0x07ba
#define regMMEA3_MISC_BASE_IDX 0
#define regMMEA3_LATENCY_SAMPLING 0x07bb
#define regMMEA3_LATENCY_SAMPLING_BASE_IDX 0
#define regMMEA3_PERFCOUNTER_LO 0x07bc
#define regMMEA3_PERFCOUNTER_LO_BASE_IDX 0
#define regMMEA3_PERFCOUNTER_HI 0x07bd
#define regMMEA3_PERFCOUNTER_HI_BASE_IDX 0
#define regMMEA3_PERFCOUNTER0_CFG 0x07be
#define regMMEA3_PERFCOUNTER0_CFG_BASE_IDX 0
#define regMMEA3_PERFCOUNTER1_CFG 0x07bf
#define regMMEA3_PERFCOUNTER1_CFG_BASE_IDX 0
#define regMMEA3_PERFCOUNTER_RSLT_CNTL 0x07c0
#define regMMEA3_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0
#define regMMEA3_EDC_CNT 0x07c6
#define regMMEA3_EDC_CNT_BASE_IDX 0
#define regMMEA3_EDC_CNT2 0x07c7
#define regMMEA3_EDC_CNT2_BASE_IDX 0
#define regMMEA3_DSM_CNTL 0x07c8
#define regMMEA3_DSM_CNTL_BASE_IDX 0
#define regMMEA3_DSM_CNTLA 0x07c9
#define regMMEA3_DSM_CNTLA_BASE_IDX 0
#define regMMEA3_DSM_CNTLB 0x07ca
#define regMMEA3_DSM_CNTLB_BASE_IDX 0
#define regMMEA3_DSM_CNTL2 0x07cb
#define regMMEA3_DSM_CNTL2_BASE_IDX 0
#define regMMEA3_DSM_CNTL2A 0x07cc
#define regMMEA3_DSM_CNTL2A_BASE_IDX 0
#define regMMEA3_DSM_CNTL2B 0x07cd
#define regMMEA3_DSM_CNTL2B_BASE_IDX 0
#define regMMEA3_CGTT_CLK_CTRL 0x07cf
#define regMMEA3_CGTT_CLK_CTRL_BASE_IDX 0
#define regMMEA3_EDC_MODE 0x07d0
#define regMMEA3_EDC_MODE_BASE_IDX 0
#define regMMEA3_ERR_STATUS 0x07d1
#define regMMEA3_ERR_STATUS_BASE_IDX 0
#define regMMEA3_MISC2 0x07d2
#define regMMEA3_MISC2_BASE_IDX 0
#define regMMEA3_ADDRDEC_SELECT 0x07d3
#define regMMEA3_ADDRDEC_SELECT_BASE_IDX 0
#define regMMEA3_EDC_CNT3 0x07d4
#define regMMEA3_EDC_CNT3_BASE_IDX 0
#define regMMEA3_MISC_AON 0x07d5
#define regMMEA3_MISC_AON_BASE_IDX 0
// addressBlock: mmhub_ea_mmeadec4
// base address: 0x6a000
#define regMMEA4_DRAM_RD_CLI2GRP_MAP0 0x0800
#define regMMEA4_DRAM_RD_CLI2GRP_MAP0_BASE_IDX 0
#define regMMEA4_DRAM_RD_CLI2GRP_MAP1 0x0801
#define regMMEA4_DRAM_RD_CLI2GRP_MAP1_BASE_IDX 0
#define regMMEA4_DRAM_WR_CLI2GRP_MAP0 0x0802
#define regMMEA4_DRAM_WR_CLI2GRP_MAP0_BASE_IDX 0
#define regMMEA4_DRAM_WR_CLI2GRP_MAP1 0x0803
#define regMMEA4_DRAM_WR_CLI2GRP_MAP1_BASE_IDX 0
#define regMMEA4_DRAM_RD_GRP2VC_MAP 0x0804
#define regMMEA4_DRAM_RD_GRP2VC_MAP_BASE_IDX 0
#define regMMEA4_DRAM_WR_GRP2VC_MAP 0x0805
#define regMMEA4_DRAM_WR_GRP2VC_MAP_BASE_IDX 0
#define regMMEA4_DRAM_RD_LAZY 0x0806
#define regMMEA4_DRAM_RD_LAZY_BASE_IDX 0
#define regMMEA4_DRAM_WR_LAZY 0x0807
#define regMMEA4_DRAM_WR_LAZY_BASE_IDX 0
#define regMMEA4_DRAM_RD_CAM_CNTL 0x0808
#define regMMEA4_DRAM_RD_CAM_CNTL_BASE_IDX 0
#define regMMEA4_DRAM_WR_CAM_CNTL 0x0809
#define regMMEA4_DRAM_WR_CAM_CNTL_BASE_IDX 0
#define regMMEA4_DRAM_PAGE_BURST 0x080a
#define regMMEA4_DRAM_PAGE_BURST_BASE_IDX 0
#define regMMEA4_DRAM_RD_PRI_AGE 0x080b
#define regMMEA4_DRAM_RD_PRI_AGE_BASE_IDX 0
#define regMMEA4_DRAM_WR_PRI_AGE 0x080c
#define regMMEA4_DRAM_WR_PRI_AGE_BASE_IDX 0
#define regMMEA4_DRAM_RD_PRI_QUEUING 0x080d
#define regMMEA4_DRAM_RD_PRI_QUEUING_BASE_IDX 0
#define regMMEA4_DRAM_WR_PRI_QUEUING 0x080e
#define regMMEA4_DRAM_WR_PRI_QUEUING_BASE_IDX 0
#define regMMEA4_DRAM_RD_PRI_FIXED 0x080f
#define regMMEA4_DRAM_RD_PRI_FIXED_BASE_IDX 0
#define regMMEA4_DRAM_WR_PRI_FIXED 0x0810
#define regMMEA4_DRAM_WR_PRI_FIXED_BASE_IDX 0
#define regMMEA4_DRAM_RD_PRI_URGENCY 0x0811
#define regMMEA4_DRAM_RD_PRI_URGENCY_BASE_IDX 0
#define regMMEA4_DRAM_WR_PRI_URGENCY 0x0812
#define regMMEA4_DRAM_WR_PRI_URGENCY_BASE_IDX 0
#define regMMEA4_DRAM_RD_PRI_QUANT_PRI1 0x0813
#define regMMEA4_DRAM_RD_PRI_QUANT_PRI1_BASE_IDX 0
#define regMMEA4_DRAM_RD_PRI_QUANT_PRI2 0x0814
#define regMMEA4_DRAM_RD_PRI_QUANT_PRI2_BASE_IDX 0
#define regMMEA4_DRAM_RD_PRI_QUANT_PRI3 0x0815
#define regMMEA4_DRAM_RD_PRI_QUANT_PRI3_BASE_IDX 0
#define regMMEA4_DRAM_WR_PRI_QUANT_PRI1 0x0816
#define regMMEA4_DRAM_WR_PRI_QUANT_PRI1_BASE_IDX 0
#define regMMEA4_DRAM_WR_PRI_QUANT_PRI2 0x0817
#define regMMEA4_DRAM_WR_PRI_QUANT_PRI2_BASE_IDX 0
#define regMMEA4_DRAM_WR_PRI_QUANT_PRI3 0x0818
#define regMMEA4_DRAM_WR_PRI_QUANT_PRI3_BASE_IDX 0
#define regMMEA4_GMI_RD_CLI2GRP_MAP0 0x0819
#define regMMEA4_GMI_RD_CLI2GRP_MAP0_BASE_IDX 0
#define regMMEA4_GMI_RD_CLI2GRP_MAP1 0x081a
#define regMMEA4_GMI_RD_CLI2GRP_MAP1_BASE_IDX 0
#define regMMEA4_GMI_WR_CLI2GRP_MAP0 0x081b
#define regMMEA4_GMI_WR_CLI2GRP_MAP0_BASE_IDX 0
#define regMMEA4_GMI_WR_CLI2GRP_MAP1 0x081c
#define regMMEA4_GMI_WR_CLI2GRP_MAP1_BASE_IDX 0
#define regMMEA4_GMI_RD_GRP2VC_MAP 0x081d
#define regMMEA4_GMI_RD_GRP2VC_MAP_BASE_IDX 0
#define regMMEA4_GMI_WR_GRP2VC_MAP 0x081e
#define regMMEA4_GMI_WR_GRP2VC_MAP_BASE_IDX 0
#define regMMEA4_GMI_RD_LAZY 0x081f
#define regMMEA4_GMI_RD_LAZY_BASE_IDX 0
#define regMMEA4_GMI_WR_LAZY 0x0820
#define regMMEA4_GMI_WR_LAZY_BASE_IDX 0
#define regMMEA4_GMI_RD_CAM_CNTL 0x0821
#define regMMEA4_GMI_RD_CAM_CNTL_BASE_IDX 0
#define regMMEA4_GMI_WR_CAM_CNTL 0x0822
#define regMMEA4_GMI_WR_CAM_CNTL_BASE_IDX 0
#define regMMEA4_GMI_PAGE_BURST 0x0823
#define regMMEA4_GMI_PAGE_BURST_BASE_IDX 0
#define regMMEA4_GMI_RD_PRI_AGE 0x0824
#define regMMEA4_GMI_RD_PRI_AGE_BASE_IDX 0
#define regMMEA4_GMI_WR_PRI_AGE 0x0825
#define regMMEA4_GMI_WR_PRI_AGE_BASE_IDX 0
#define regMMEA4_GMI_RD_PRI_QUEUING 0x0826
#define regMMEA4_GMI_RD_PRI_QUEUING_BASE_IDX 0
#define regMMEA4_GMI_WR_PRI_QUEUING 0x0827
#define regMMEA4_GMI_WR_PRI_QUEUING_BASE_IDX 0
#define regMMEA4_GMI_RD_PRI_FIXED 0x0828
#define regMMEA4_GMI_RD_PRI_FIXED_BASE_IDX 0
#define regMMEA4_GMI_WR_PRI_FIXED 0x0829
#define regMMEA4_GMI_WR_PRI_FIXED_BASE_IDX 0
#define regMMEA4_GMI_RD_PRI_URGENCY 0x082a
#define regMMEA4_GMI_RD_PRI_URGENCY_BASE_IDX 0
#define regMMEA4_GMI_WR_PRI_URGENCY 0x082b
#define regMMEA4_GMI_WR_PRI_URGENCY_BASE_IDX 0
#define regMMEA4_GMI_RD_PRI_URGENCY_MASKING 0x082c
#define regMMEA4_GMI_RD_PRI_URGENCY_MASKING_BASE_IDX 0
#define regMMEA4_GMI_WR_PRI_URGENCY_MASKING 0x082d
#define regMMEA4_GMI_WR_PRI_URGENCY_MASKING_BASE_IDX 0
#define regMMEA4_GMI_RD_PRI_QUANT_PRI1 0x082e
#define regMMEA4_GMI_RD_PRI_QUANT_PRI1_BASE_IDX 0
#define regMMEA4_GMI_RD_PRI_QUANT_PRI2 0x082f
#define regMMEA4_GMI_RD_PRI_QUANT_PRI2_BASE_IDX 0
#define regMMEA4_GMI_RD_PRI_QUANT_PRI3 0x0830
#define regMMEA4_GMI_RD_PRI_QUANT_PRI3_BASE_IDX 0
#define regMMEA4_GMI_WR_PRI_QUANT_PRI1 0x0831
#define regMMEA4_GMI_WR_PRI_QUANT_PRI1_BASE_IDX 0
#define regMMEA4_GMI_WR_PRI_QUANT_PRI2 0x0832
#define regMMEA4_GMI_WR_PRI_QUANT_PRI2_BASE_IDX 0
#define regMMEA4_GMI_WR_PRI_QUANT_PRI3 0x0833
#define regMMEA4_GMI_WR_PRI_QUANT_PRI3_BASE_IDX 0
#define regMMEA4_ADDRNORM_BASE_ADDR0 0x0834
#define regMMEA4_ADDRNORM_BASE_ADDR0_BASE_IDX 0
#define regMMEA4_ADDRNORM_LIMIT_ADDR0 0x0835
#define regMMEA4_ADDRNORM_LIMIT_ADDR0_BASE_IDX 0
#define regMMEA4_ADDRNORM_BASE_ADDR1 0x0836
#define regMMEA4_ADDRNORM_BASE_ADDR1_BASE_IDX 0
#define regMMEA4_ADDRNORM_LIMIT_ADDR1 0x0837
#define regMMEA4_ADDRNORM_LIMIT_ADDR1_BASE_IDX 0
#define regMMEA4_ADDRNORM_OFFSET_ADDR1 0x0838
#define regMMEA4_ADDRNORM_OFFSET_ADDR1_BASE_IDX 0
#define regMMEA4_ADDRNORM_BASE_ADDR2 0x0839
#define regMMEA4_ADDRNORM_BASE_ADDR2_BASE_IDX 0
#define regMMEA4_ADDRNORM_LIMIT_ADDR2 0x083a
#define regMMEA4_ADDRNORM_LIMIT_ADDR2_BASE_IDX 0
#define regMMEA4_ADDRNORM_BASE_ADDR3 0x083b
#define regMMEA4_ADDRNORM_BASE_ADDR3_BASE_IDX 0
#define regMMEA4_ADDRNORM_LIMIT_ADDR3 0x083c
#define regMMEA4_ADDRNORM_LIMIT_ADDR3_BASE_IDX 0
#define regMMEA4_ADDRNORM_OFFSET_ADDR3 0x083d
#define regMMEA4_ADDRNORM_OFFSET_ADDR3_BASE_IDX 0
#define regMMEA4_ADDRNORM_MEGABASE_ADDR0 0x083e
#define regMMEA4_ADDRNORM_MEGABASE_ADDR0_BASE_IDX 0
#define regMMEA4_ADDRNORM_MEGALIMIT_ADDR0 0x083f
#define regMMEA4_ADDRNORM_MEGALIMIT_ADDR0_BASE_IDX 0
#define regMMEA4_ADDRNORM_MEGABASE_ADDR1 0x0840
#define regMMEA4_ADDRNORM_MEGABASE_ADDR1_BASE_IDX 0
#define regMMEA4_ADDRNORM_MEGALIMIT_ADDR1 0x0841
#define regMMEA4_ADDRNORM_MEGALIMIT_ADDR1_BASE_IDX 0
#define regMMEA4_ADDRNORMDRAM_HOLE_CNTL 0x0843
#define regMMEA4_ADDRNORMDRAM_HOLE_CNTL_BASE_IDX 0
#define regMMEA4_ADDRNORMGMI_HOLE_CNTL 0x0844
#define regMMEA4_ADDRNORMGMI_HOLE_CNTL_BASE_IDX 0
#define regMMEA4_ADDRNORMDRAM_NP2_CHANNEL_CFG 0x0845
#define regMMEA4_ADDRNORMDRAM_NP2_CHANNEL_CFG_BASE_IDX 0
#define regMMEA4_ADDRNORMGMI_NP2_CHANNEL_CFG 0x0846
#define regMMEA4_ADDRNORMGMI_NP2_CHANNEL_CFG_BASE_IDX 0
#define regMMEA4_ADDRDEC_BANK_CFG 0x0847
#define regMMEA4_ADDRDEC_BANK_CFG_BASE_IDX 0
#define regMMEA4_ADDRDEC_MISC_CFG 0x0848
#define regMMEA4_ADDRDEC_MISC_CFG_BASE_IDX 0
#define regMMEA4_ADDRDECDRAM_HARVEST_ENABLE 0x0853
#define regMMEA4_ADDRDECDRAM_HARVEST_ENABLE_BASE_IDX 0
#define regMMEA4_ADDRDECGMI_HARVEST_ENABLE 0x085e
#define regMMEA4_ADDRDECGMI_HARVEST_ENABLE_BASE_IDX 0
#define regMMEA4_ADDRDEC0_BASE_ADDR_CS0 0x085f
#define regMMEA4_ADDRDEC0_BASE_ADDR_CS0_BASE_IDX 0
#define regMMEA4_ADDRDEC0_BASE_ADDR_CS1 0x0860
#define regMMEA4_ADDRDEC0_BASE_ADDR_CS1_BASE_IDX 0
#define regMMEA4_ADDRDEC0_BASE_ADDR_CS2 0x0861
#define regMMEA4_ADDRDEC0_BASE_ADDR_CS2_BASE_IDX 0
#define regMMEA4_ADDRDEC0_BASE_ADDR_CS3 0x0862
#define regMMEA4_ADDRDEC0_BASE_ADDR_CS3_BASE_IDX 0
#define regMMEA4_ADDRDEC0_BASE_ADDR_SECCS0 0x0863
#define regMMEA4_ADDRDEC0_BASE_ADDR_SECCS0_BASE_IDX 0
#define regMMEA4_ADDRDEC0_BASE_ADDR_SECCS1 0x0864
#define regMMEA4_ADDRDEC0_BASE_ADDR_SECCS1_BASE_IDX 0
#define regMMEA4_ADDRDEC0_BASE_ADDR_SECCS2 0x0865
#define regMMEA4_ADDRDEC0_BASE_ADDR_SECCS2_BASE_IDX 0
#define regMMEA4_ADDRDEC0_BASE_ADDR_SECCS3 0x0866
#define regMMEA4_ADDRDEC0_BASE_ADDR_SECCS3_BASE_IDX 0
#define regMMEA4_ADDRDEC0_ADDR_MASK_CS01 0x0867
#define regMMEA4_ADDRDEC0_ADDR_MASK_CS01_BASE_IDX 0
#define regMMEA4_ADDRDEC0_ADDR_MASK_CS23 0x0868
#define regMMEA4_ADDRDEC0_ADDR_MASK_CS23_BASE_IDX 0
#define regMMEA4_ADDRDEC0_ADDR_MASK_SECCS01 0x0869
#define regMMEA4_ADDRDEC0_ADDR_MASK_SECCS01_BASE_IDX 0
#define regMMEA4_ADDRDEC0_ADDR_MASK_SECCS23 0x086a
#define regMMEA4_ADDRDEC0_ADDR_MASK_SECCS23_BASE_IDX 0
#define regMMEA4_ADDRDEC0_ADDR_CFG_CS01 0x086b
#define regMMEA4_ADDRDEC0_ADDR_CFG_CS01_BASE_IDX 0
#define regMMEA4_ADDRDEC0_ADDR_CFG_CS23 0x086c
#define regMMEA4_ADDRDEC0_ADDR_CFG_CS23_BASE_IDX 0
#define regMMEA4_ADDRDEC0_ADDR_SEL_CS01 0x086d
#define regMMEA4_ADDRDEC0_ADDR_SEL_CS01_BASE_IDX 0
#define regMMEA4_ADDRDEC0_ADDR_SEL_CS23 0x086e
#define regMMEA4_ADDRDEC0_ADDR_SEL_CS23_BASE_IDX 0
#define regMMEA4_ADDRDEC0_ADDR_SEL2_CS01 0x086f
#define regMMEA4_ADDRDEC0_ADDR_SEL2_CS01_BASE_IDX 0
#define regMMEA4_ADDRDEC0_ADDR_SEL2_CS23 0x0870
#define regMMEA4_ADDRDEC0_ADDR_SEL2_CS23_BASE_IDX 0
#define regMMEA4_ADDRDEC0_COL_SEL_LO_CS01 0x0871
#define regMMEA4_ADDRDEC0_COL_SEL_LO_CS01_BASE_IDX 0
#define regMMEA4_ADDRDEC0_COL_SEL_LO_CS23 0x0872
#define regMMEA4_ADDRDEC0_COL_SEL_LO_CS23_BASE_IDX 0
#define regMMEA4_ADDRDEC0_COL_SEL_HI_CS01 0x0873
#define regMMEA4_ADDRDEC0_COL_SEL_HI_CS01_BASE_IDX 0
#define regMMEA4_ADDRDEC0_COL_SEL_HI_CS23 0x0874
#define regMMEA4_ADDRDEC0_COL_SEL_HI_CS23_BASE_IDX 0
#define regMMEA4_ADDRDEC0_RM_SEL_CS01 0x0875
#define regMMEA4_ADDRDEC0_RM_SEL_CS01_BASE_IDX 0
#define regMMEA4_ADDRDEC0_RM_SEL_CS23 0x0876
#define regMMEA4_ADDRDEC0_RM_SEL_CS23_BASE_IDX 0
#define regMMEA4_ADDRDEC0_RM_SEL_SECCS01 0x0877
#define regMMEA4_ADDRDEC0_RM_SEL_SECCS01_BASE_IDX 0
#define regMMEA4_ADDRDEC0_RM_SEL_SECCS23 0x0878
#define regMMEA4_ADDRDEC0_RM_SEL_SECCS23_BASE_IDX 0
#define regMMEA4_ADDRDEC1_BASE_ADDR_CS0 0x0879
#define regMMEA4_ADDRDEC1_BASE_ADDR_CS0_BASE_IDX 0
#define regMMEA4_ADDRDEC1_BASE_ADDR_CS1 0x087a
#define regMMEA4_ADDRDEC1_BASE_ADDR_CS1_BASE_IDX 0
#define regMMEA4_ADDRDEC1_BASE_ADDR_CS2 0x087b
#define regMMEA4_ADDRDEC1_BASE_ADDR_CS2_BASE_IDX 0
#define regMMEA4_ADDRDEC1_BASE_ADDR_CS3 0x087c
#define regMMEA4_ADDRDEC1_BASE_ADDR_CS3_BASE_IDX 0
#define regMMEA4_ADDRDEC1_BASE_ADDR_SECCS0 0x087d
#define regMMEA4_ADDRDEC1_BASE_ADDR_SECCS0_BASE_IDX 0
#define regMMEA4_ADDRDEC1_BASE_ADDR_SECCS1 0x087e
#define regMMEA4_ADDRDEC1_BASE_ADDR_SECCS1_BASE_IDX 0
#define regMMEA4_ADDRDEC1_BASE_ADDR_SECCS2 0x087f
#define regMMEA4_ADDRDEC1_BASE_ADDR_SECCS2_BASE_IDX 0
#define regMMEA4_ADDRDEC1_BASE_ADDR_SECCS3 0x0880
#define regMMEA4_ADDRDEC1_BASE_ADDR_SECCS3_BASE_IDX 0
#define regMMEA4_ADDRDEC1_ADDR_MASK_CS01 0x0881
#define regMMEA4_ADDRDEC1_ADDR_MASK_CS01_BASE_IDX 0
#define regMMEA4_ADDRDEC1_ADDR_MASK_CS23 0x0882
#define regMMEA4_ADDRDEC1_ADDR_MASK_CS23_BASE_IDX 0
#define regMMEA4_ADDRDEC1_ADDR_MASK_SECCS01 0x0883
#define regMMEA4_ADDRDEC1_ADDR_MASK_SECCS01_BASE_IDX 0
#define regMMEA4_ADDRDEC1_ADDR_MASK_SECCS23 0x0884
#define regMMEA4_ADDRDEC1_ADDR_MASK_SECCS23_BASE_IDX 0
#define regMMEA4_ADDRDEC1_ADDR_CFG_CS01 0x0885
#define regMMEA4_ADDRDEC1_ADDR_CFG_CS01_BASE_IDX 0
#define regMMEA4_ADDRDEC1_ADDR_CFG_CS23 0x0886
#define regMMEA4_ADDRDEC1_ADDR_CFG_CS23_BASE_IDX 0
#define regMMEA4_ADDRDEC1_ADDR_SEL_CS01 0x0887
#define regMMEA4_ADDRDEC1_ADDR_SEL_CS01_BASE_IDX 0
#define regMMEA4_ADDRDEC1_ADDR_SEL_CS23 0x0888
#define regMMEA4_ADDRDEC1_ADDR_SEL_CS23_BASE_IDX 0
#define regMMEA4_ADDRDEC1_ADDR_SEL2_CS01 0x0889
#define regMMEA4_ADDRDEC1_ADDR_SEL2_CS01_BASE_IDX 0
#define regMMEA4_ADDRDEC1_ADDR_SEL2_CS23 0x088a
#define regMMEA4_ADDRDEC1_ADDR_SEL2_CS23_BASE_IDX 0
#define regMMEA4_ADDRDEC1_COL_SEL_LO_CS01 0x088b
#define regMMEA4_ADDRDEC1_COL_SEL_LO_CS01_BASE_IDX 0
#define regMMEA4_ADDRDEC1_COL_SEL_LO_CS23 0x088c
#define regMMEA4_ADDRDEC1_COL_SEL_LO_CS23_BASE_IDX 0
#define regMMEA4_ADDRDEC1_COL_SEL_HI_CS01 0x088d
#define regMMEA4_ADDRDEC1_COL_SEL_HI_CS01_BASE_IDX 0
#define regMMEA4_ADDRDEC1_COL_SEL_HI_CS23 0x088e
#define regMMEA4_ADDRDEC1_COL_SEL_HI_CS23_BASE_IDX 0
#define regMMEA4_ADDRDEC1_RM_SEL_CS01 0x088f
#define regMMEA4_ADDRDEC1_RM_SEL_CS01_BASE_IDX 0
#define regMMEA4_ADDRDEC1_RM_SEL_CS23 0x0890
#define regMMEA4_ADDRDEC1_RM_SEL_CS23_BASE_IDX 0
#define regMMEA4_ADDRDEC1_RM_SEL_SECCS01 0x0891
#define regMMEA4_ADDRDEC1_RM_SEL_SECCS01_BASE_IDX 0
#define regMMEA4_ADDRDEC1_RM_SEL_SECCS23 0x0892
#define regMMEA4_ADDRDEC1_RM_SEL_SECCS23_BASE_IDX 0
#define regMMEA4_ADDRDEC2_BASE_ADDR_CS0 0x0893
#define regMMEA4_ADDRDEC2_BASE_ADDR_CS0_BASE_IDX 0
#define regMMEA4_ADDRDEC2_BASE_ADDR_CS1 0x0894
#define regMMEA4_ADDRDEC2_BASE_ADDR_CS1_BASE_IDX 0
#define regMMEA4_ADDRDEC2_BASE_ADDR_CS2 0x0895
#define regMMEA4_ADDRDEC2_BASE_ADDR_CS2_BASE_IDX 0
#define regMMEA4_ADDRDEC2_BASE_ADDR_CS3 0x0896
#define regMMEA4_ADDRDEC2_BASE_ADDR_CS3_BASE_IDX 0
#define regMMEA4_ADDRDEC2_BASE_ADDR_SECCS0 0x0897
#define regMMEA4_ADDRDEC2_BASE_ADDR_SECCS0_BASE_IDX 0
#define regMMEA4_ADDRDEC2_BASE_ADDR_SECCS1 0x0898
#define regMMEA4_ADDRDEC2_BASE_ADDR_SECCS1_BASE_IDX 0
#define regMMEA4_ADDRDEC2_BASE_ADDR_SECCS2 0x0899
#define regMMEA4_ADDRDEC2_BASE_ADDR_SECCS2_BASE_IDX 0
#define regMMEA4_ADDRDEC2_BASE_ADDR_SECCS3 0x089a
#define regMMEA4_ADDRDEC2_BASE_ADDR_SECCS3_BASE_IDX 0
#define regMMEA4_ADDRDEC2_ADDR_MASK_CS01 0x089b
#define regMMEA4_ADDRDEC2_ADDR_MASK_CS01_BASE_IDX 0
#define regMMEA4_ADDRDEC2_ADDR_MASK_CS23 0x089c
#define regMMEA4_ADDRDEC2_ADDR_MASK_CS23_BASE_IDX 0
#define regMMEA4_ADDRDEC2_ADDR_MASK_SECCS01 0x089d
#define regMMEA4_ADDRDEC2_ADDR_MASK_SECCS01_BASE_IDX 0
#define regMMEA4_ADDRDEC2_ADDR_MASK_SECCS23 0x089e
#define regMMEA4_ADDRDEC2_ADDR_MASK_SECCS23_BASE_IDX 0
#define regMMEA4_ADDRDEC2_ADDR_CFG_CS01 0x089f
#define regMMEA4_ADDRDEC2_ADDR_CFG_CS01_BASE_IDX 0
#define regMMEA4_ADDRDEC2_ADDR_CFG_CS23 0x08a0
#define regMMEA4_ADDRDEC2_ADDR_CFG_CS23_BASE_IDX 0
#define regMMEA4_ADDRDEC2_ADDR_SEL_CS01 0x08a1
#define regMMEA4_ADDRDEC2_ADDR_SEL_CS01_BASE_IDX 0
#define regMMEA4_ADDRDEC2_ADDR_SEL_CS23 0x08a2
#define regMMEA4_ADDRDEC2_ADDR_SEL_CS23_BASE_IDX 0
#define regMMEA4_ADDRDEC2_ADDR_SEL2_CS01 0x08a3
#define regMMEA4_ADDRDEC2_ADDR_SEL2_CS01_BASE_IDX 0
#define regMMEA4_ADDRDEC2_ADDR_SEL2_CS23 0x08a4
#define regMMEA4_ADDRDEC2_ADDR_SEL2_CS23_BASE_IDX 0
#define regMMEA4_ADDRDEC2_COL_SEL_LO_CS01 0x08a5
#define regMMEA4_ADDRDEC2_COL_SEL_LO_CS01_BASE_IDX 0
#define regMMEA4_ADDRDEC2_COL_SEL_LO_CS23 0x08a6
#define regMMEA4_ADDRDEC2_COL_SEL_LO_CS23_BASE_IDX 0
#define regMMEA4_ADDRDEC2_COL_SEL_HI_CS01 0x08a7
#define regMMEA4_ADDRDEC2_COL_SEL_HI_CS01_BASE_IDX 0
#define regMMEA4_ADDRDEC2_COL_SEL_HI_CS23 0x08a8
#define regMMEA4_ADDRDEC2_COL_SEL_HI_CS23_BASE_IDX 0
#define regMMEA4_ADDRDEC2_RM_SEL_CS01 0x08a9
#define regMMEA4_ADDRDEC2_RM_SEL_CS01_BASE_IDX 0
#define regMMEA4_ADDRDEC2_RM_SEL_CS23 0x08aa
#define regMMEA4_ADDRDEC2_RM_SEL_CS23_BASE_IDX 0
#define regMMEA4_ADDRDEC2_RM_SEL_SECCS01 0x08ab
#define regMMEA4_ADDRDEC2_RM_SEL_SECCS01_BASE_IDX 0
#define regMMEA4_ADDRDEC2_RM_SEL_SECCS23 0x08ac
#define regMMEA4_ADDRDEC2_RM_SEL_SECCS23_BASE_IDX 0
#define regMMEA4_ADDRNORMDRAM_GLOBAL_CNTL 0x08ad
#define regMMEA4_ADDRNORMDRAM_GLOBAL_CNTL_BASE_IDX 0
#define regMMEA4_ADDRNORMGMI_GLOBAL_CNTL 0x08ae
#define regMMEA4_ADDRNORMGMI_GLOBAL_CNTL_BASE_IDX 0
#define regMMEA4_ADDRNORM_MEGACONTROL_ADDR0 0x08d1
#define regMMEA4_ADDRNORM_MEGACONTROL_ADDR0_BASE_IDX 0
#define regMMEA4_ADDRNORM_MEGACONTROL_ADDR1 0x08d2
#define regMMEA4_ADDRNORM_MEGACONTROL_ADDR1_BASE_IDX 0
#define regMMEA4_ADDRNORMDRAM_MASKING 0x08d3
#define regMMEA4_ADDRNORMDRAM_MASKING_BASE_IDX 0
#define regMMEA4_ADDRNORMGMI_MASKING 0x08d4
#define regMMEA4_ADDRNORMGMI_MASKING_BASE_IDX 0
#define regMMEA4_IO_RD_CLI2GRP_MAP0 0x08d5
#define regMMEA4_IO_RD_CLI2GRP_MAP0_BASE_IDX 0
#define regMMEA4_IO_RD_CLI2GRP_MAP1 0x08d6
#define regMMEA4_IO_RD_CLI2GRP_MAP1_BASE_IDX 0
#define regMMEA4_IO_WR_CLI2GRP_MAP0 0x08d7
#define regMMEA4_IO_WR_CLI2GRP_MAP0_BASE_IDX 0
#define regMMEA4_IO_WR_CLI2GRP_MAP1 0x08d8
#define regMMEA4_IO_WR_CLI2GRP_MAP1_BASE_IDX 0
#define regMMEA4_IO_RD_COMBINE_FLUSH 0x08d9
#define regMMEA4_IO_RD_COMBINE_FLUSH_BASE_IDX 0
#define regMMEA4_IO_WR_COMBINE_FLUSH 0x08da
#define regMMEA4_IO_WR_COMBINE_FLUSH_BASE_IDX 0
#define regMMEA4_IO_GROUP_BURST 0x08db
#define regMMEA4_IO_GROUP_BURST_BASE_IDX 0
#define regMMEA4_IO_RD_PRI_AGE 0x08dc
#define regMMEA4_IO_RD_PRI_AGE_BASE_IDX 0
#define regMMEA4_IO_WR_PRI_AGE 0x08dd
#define regMMEA4_IO_WR_PRI_AGE_BASE_IDX 0
#define regMMEA4_IO_RD_PRI_QUEUING 0x08de
#define regMMEA4_IO_RD_PRI_QUEUING_BASE_IDX 0
#define regMMEA4_IO_WR_PRI_QUEUING 0x08df
#define regMMEA4_IO_WR_PRI_QUEUING_BASE_IDX 0
#define regMMEA4_IO_RD_PRI_FIXED 0x08e0
#define regMMEA4_IO_RD_PRI_FIXED_BASE_IDX 0
#define regMMEA4_IO_WR_PRI_FIXED 0x08e1
#define regMMEA4_IO_WR_PRI_FIXED_BASE_IDX 0
#define regMMEA4_IO_RD_PRI_URGENCY 0x08e2
#define regMMEA4_IO_RD_PRI_URGENCY_BASE_IDX 0
#define regMMEA4_IO_WR_PRI_URGENCY 0x08e3
#define regMMEA4_IO_WR_PRI_URGENCY_BASE_IDX 0
#define regMMEA4_IO_RD_PRI_URGENCY_MASKING 0x08e4
#define regMMEA4_IO_RD_PRI_URGENCY_MASKING_BASE_IDX 0
#define regMMEA4_IO_WR_PRI_URGENCY_MASKING 0x08e5
#define regMMEA4_IO_WR_PRI_URGENCY_MASKING_BASE_IDX 0
#define regMMEA4_IO_RD_PRI_QUANT_PRI1 0x08e6
#define regMMEA4_IO_RD_PRI_QUANT_PRI1_BASE_IDX 0
#define regMMEA4_IO_RD_PRI_QUANT_PRI2 0x08e7
#define regMMEA4_IO_RD_PRI_QUANT_PRI2_BASE_IDX 0
#define regMMEA4_IO_RD_PRI_QUANT_PRI3 0x08e8
#define regMMEA4_IO_RD_PRI_QUANT_PRI3_BASE_IDX 0
#define regMMEA4_IO_WR_PRI_QUANT_PRI1 0x08e9
#define regMMEA4_IO_WR_PRI_QUANT_PRI1_BASE_IDX 0
#define regMMEA4_IO_WR_PRI_QUANT_PRI2 0x08ea
#define regMMEA4_IO_WR_PRI_QUANT_PRI2_BASE_IDX 0
#define regMMEA4_IO_WR_PRI_QUANT_PRI3 0x08eb
#define regMMEA4_IO_WR_PRI_QUANT_PRI3_BASE_IDX 0
#define regMMEA4_SDP_ARB_DRAM 0x08ec
#define regMMEA4_SDP_ARB_DRAM_BASE_IDX 0
#define regMMEA4_SDP_ARB_GMI 0x08ed
#define regMMEA4_SDP_ARB_GMI_BASE_IDX 0
#define regMMEA4_SDP_ARB_FINAL 0x08ee
#define regMMEA4_SDP_ARB_FINAL_BASE_IDX 0
#define regMMEA4_SDP_DRAM_PRIORITY 0x08ef
#define regMMEA4_SDP_DRAM_PRIORITY_BASE_IDX 0
#define regMMEA4_SDP_GMI_PRIORITY 0x08f0
#define regMMEA4_SDP_GMI_PRIORITY_BASE_IDX 0
#define regMMEA4_SDP_IO_PRIORITY 0x08f1
#define regMMEA4_SDP_IO_PRIORITY_BASE_IDX 0
#define regMMEA4_SDP_CREDITS 0x08f2
#define regMMEA4_SDP_CREDITS_BASE_IDX 0
#define regMMEA4_SDP_TAG_RESERVE0 0x08f3
#define regMMEA4_SDP_TAG_RESERVE0_BASE_IDX 0
#define regMMEA4_SDP_TAG_RESERVE1 0x08f4
#define regMMEA4_SDP_TAG_RESERVE1_BASE_IDX 0
#define regMMEA4_SDP_VCC_RESERVE0 0x08f5
#define regMMEA4_SDP_VCC_RESERVE0_BASE_IDX 0
#define regMMEA4_SDP_VCC_RESERVE1 0x08f6
#define regMMEA4_SDP_VCC_RESERVE1_BASE_IDX 0
#define regMMEA4_SDP_VCD_RESERVE0 0x08f7
#define regMMEA4_SDP_VCD_RESERVE0_BASE_IDX 0
#define regMMEA4_SDP_VCD_RESERVE1 0x08f8
#define regMMEA4_SDP_VCD_RESERVE1_BASE_IDX 0
#define regMMEA4_SDP_REQ_CNTL 0x08f9
#define regMMEA4_SDP_REQ_CNTL_BASE_IDX 0
#define regMMEA4_MISC 0x08fa
#define regMMEA4_MISC_BASE_IDX 0
#define regMMEA4_LATENCY_SAMPLING 0x08fb
#define regMMEA4_LATENCY_SAMPLING_BASE_IDX 0
#define regMMEA4_PERFCOUNTER_LO 0x08fc
#define regMMEA4_PERFCOUNTER_LO_BASE_IDX 0
#define regMMEA4_PERFCOUNTER_HI 0x08fd
#define regMMEA4_PERFCOUNTER_HI_BASE_IDX 0
#define regMMEA4_PERFCOUNTER0_CFG 0x08fe
#define regMMEA4_PERFCOUNTER0_CFG_BASE_IDX 0
#define regMMEA4_PERFCOUNTER1_CFG 0x08ff
#define regMMEA4_PERFCOUNTER1_CFG_BASE_IDX 0
#define regMMEA4_PERFCOUNTER_RSLT_CNTL 0x0900
#define regMMEA4_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0
#define regMMEA4_EDC_CNT 0x0906
#define regMMEA4_EDC_CNT_BASE_IDX 0
#define regMMEA4_EDC_CNT2 0x0907
#define regMMEA4_EDC_CNT2_BASE_IDX 0
#define regMMEA4_DSM_CNTL 0x0908
#define regMMEA4_DSM_CNTL_BASE_IDX 0
#define regMMEA4_DSM_CNTLA 0x0909
#define regMMEA4_DSM_CNTLA_BASE_IDX 0
#define regMMEA4_DSM_CNTLB 0x090a
#define regMMEA4_DSM_CNTLB_BASE_IDX 0
#define regMMEA4_DSM_CNTL2 0x090b
#define regMMEA4_DSM_CNTL2_BASE_IDX 0
#define regMMEA4_DSM_CNTL2A 0x090c
#define regMMEA4_DSM_CNTL2A_BASE_IDX 0
#define regMMEA4_DSM_CNTL2B 0x090d
#define regMMEA4_DSM_CNTL2B_BASE_IDX 0
#define regMMEA4_CGTT_CLK_CTRL 0x090f
#define regMMEA4_CGTT_CLK_CTRL_BASE_IDX 0
#define regMMEA4_EDC_MODE 0x0910
#define regMMEA4_EDC_MODE_BASE_IDX 0
#define regMMEA4_ERR_STATUS 0x0911
#define regMMEA4_ERR_STATUS_BASE_IDX 0
#define regMMEA4_MISC2 0x0912
#define regMMEA4_MISC2_BASE_IDX 0
#define regMMEA4_ADDRDEC_SELECT 0x0913
#define regMMEA4_ADDRDEC_SELECT_BASE_IDX 0
#define regMMEA4_EDC_CNT3 0x0914
#define regMMEA4_EDC_CNT3_BASE_IDX 0
#define regMMEA4_MISC_AON 0x0915
#define regMMEA4_MISC_AON_BASE_IDX 0
// addressBlock: mmhub_ea_mmeadec5
// base address: 0x6a500
#define regMMEA5_DRAM_RD_CLI2GRP_MAP0 0x0940
#define regMMEA5_DRAM_RD_CLI2GRP_MAP0_BASE_IDX 0
#define regMMEA5_DRAM_RD_CLI2GRP_MAP1 0x0941
#define regMMEA5_DRAM_RD_CLI2GRP_MAP1_BASE_IDX 0
#define regMMEA5_DRAM_WR_CLI2GRP_MAP0 0x0942
#define regMMEA5_DRAM_WR_CLI2GRP_MAP0_BASE_IDX 0
#define regMMEA5_DRAM_WR_CLI2GRP_MAP1 0x0943
#define regMMEA5_DRAM_WR_CLI2GRP_MAP1_BASE_IDX 0
#define regMMEA5_DRAM_RD_GRP2VC_MAP 0x0944
#define regMMEA5_DRAM_RD_GRP2VC_MAP_BASE_IDX 0
#define regMMEA5_DRAM_WR_GRP2VC_MAP 0x0945
#define regMMEA5_DRAM_WR_GRP2VC_MAP_BASE_IDX 0
#define regMMEA5_DRAM_RD_LAZY 0x0946
#define regMMEA5_DRAM_RD_LAZY_BASE_IDX 0
#define regMMEA5_DRAM_WR_LAZY 0x0947
#define regMMEA5_DRAM_WR_LAZY_BASE_IDX 0
#define regMMEA5_DRAM_RD_CAM_CNTL 0x0948
#define regMMEA5_DRAM_RD_CAM_CNTL_BASE_IDX 0
#define regMMEA5_DRAM_WR_CAM_CNTL 0x0949
#define regMMEA5_DRAM_WR_CAM_CNTL_BASE_IDX 0
#define regMMEA5_DRAM_PAGE_BURST 0x094a
#define regMMEA5_DRAM_PAGE_BURST_BASE_IDX 0
#define regMMEA5_DRAM_RD_PRI_AGE 0x094b
#define regMMEA5_DRAM_RD_PRI_AGE_BASE_IDX 0
#define regMMEA5_DRAM_WR_PRI_AGE 0x094c
#define regMMEA5_DRAM_WR_PRI_AGE_BASE_IDX 0
#define regMMEA5_DRAM_RD_PRI_QUEUING 0x094d
#define regMMEA5_DRAM_RD_PRI_QUEUING_BASE_IDX 0
#define regMMEA5_DRAM_WR_PRI_QUEUING 0x094e
#define regMMEA5_DRAM_WR_PRI_QUEUING_BASE_IDX 0
#define regMMEA5_DRAM_RD_PRI_FIXED 0x094f
#define regMMEA5_DRAM_RD_PRI_FIXED_BASE_IDX 0
#define regMMEA5_DRAM_WR_PRI_FIXED 0x0950
#define regMMEA5_DRAM_WR_PRI_FIXED_BASE_IDX 0
#define regMMEA5_DRAM_RD_PRI_URGENCY 0x0951
#define regMMEA5_DRAM_RD_PRI_URGENCY_BASE_IDX 0
#define regMMEA5_DRAM_WR_PRI_URGENCY 0x0952
#define regMMEA5_DRAM_WR_PRI_URGENCY_BASE_IDX 0
#define regMMEA5_DRAM_RD_PRI_QUANT_PRI1 0x0953
#define regMMEA5_DRAM_RD_PRI_QUANT_PRI1_BASE_IDX 0
#define regMMEA5_DRAM_RD_PRI_QUANT_PRI2 0x0954
#define regMMEA5_DRAM_RD_PRI_QUANT_PRI2_BASE_IDX 0
#define regMMEA5_DRAM_RD_PRI_QUANT_PRI3 0x0955
#define regMMEA5_DRAM_RD_PRI_QUANT_PRI3_BASE_IDX 0
#define regMMEA5_DRAM_WR_PRI_QUANT_PRI1 0x0956
#define regMMEA5_DRAM_WR_PRI_QUANT_PRI1_BASE_IDX 0
#define regMMEA5_DRAM_WR_PRI_QUANT_PRI2 0x0957
#define regMMEA5_DRAM_WR_PRI_QUANT_PRI2_BASE_IDX 0
#define regMMEA5_DRAM_WR_PRI_QUANT_PRI3 0x0958
#define regMMEA5_DRAM_WR_PRI_QUANT_PRI3_BASE_IDX 0
#define regMMEA5_GMI_RD_CLI2GRP_MAP0 0x0959
#define regMMEA5_GMI_RD_CLI2GRP_MAP0_BASE_IDX 0
#define regMMEA5_GMI_RD_CLI2GRP_MAP1 0x095a
#define regMMEA5_GMI_RD_CLI2GRP_MAP1_BASE_IDX 0
#define regMMEA5_GMI_WR_CLI2GRP_MAP0 0x095b
#define regMMEA5_GMI_WR_CLI2GRP_MAP0_BASE_IDX 0
#define regMMEA5_GMI_WR_CLI2GRP_MAP1 0x095c
#define regMMEA5_GMI_WR_CLI2GRP_MAP1_BASE_IDX 0
#define regMMEA5_GMI_RD_GRP2VC_MAP 0x095d
#define regMMEA5_GMI_RD_GRP2VC_MAP_BASE_IDX 0
#define regMMEA5_GMI_WR_GRP2VC_MAP 0x095e
#define regMMEA5_GMI_WR_GRP2VC_MAP_BASE_IDX 0
#define regMMEA5_GMI_RD_LAZY 0x095f
#define regMMEA5_GMI_RD_LAZY_BASE_IDX 0
#define regMMEA5_GMI_WR_LAZY 0x0960
#define regMMEA5_GMI_WR_LAZY_BASE_IDX 0
#define regMMEA5_GMI_RD_CAM_CNTL 0x0961
#define regMMEA5_GMI_RD_CAM_CNTL_BASE_IDX 0
#define regMMEA5_GMI_WR_CAM_CNTL 0x0962
#define regMMEA5_GMI_WR_CAM_CNTL_BASE_IDX 0
#define regMMEA5_GMI_PAGE_BURST 0x0963
#define regMMEA5_GMI_PAGE_BURST_BASE_IDX 0
#define regMMEA5_GMI_RD_PRI_AGE 0x0964
#define regMMEA5_GMI_RD_PRI_AGE_BASE_IDX 0
#define regMMEA5_GMI_WR_PRI_AGE 0x0965
#define regMMEA5_GMI_WR_PRI_AGE_BASE_IDX 0
#define regMMEA5_GMI_RD_PRI_QUEUING 0x0966
#define regMMEA5_GMI_RD_PRI_QUEUING_BASE_IDX 0
#define regMMEA5_GMI_WR_PRI_QUEUING 0x0967
#define regMMEA5_GMI_WR_PRI_QUEUING_BASE_IDX 0
#define regMMEA5_GMI_RD_PRI_FIXED 0x0968
#define regMMEA5_GMI_RD_PRI_FIXED_BASE_IDX 0
#define regMMEA5_GMI_WR_PRI_FIXED 0x0969
#define regMMEA5_GMI_WR_PRI_FIXED_BASE_IDX 0
#define regMMEA5_GMI_RD_PRI_URGENCY 0x096a
#define regMMEA5_GMI_RD_PRI_URGENCY_BASE_IDX 0
#define regMMEA5_GMI_WR_PRI_URGENCY 0x096b
#define regMMEA5_GMI_WR_PRI_URGENCY_BASE_IDX 0
#define regMMEA5_GMI_RD_PRI_URGENCY_MASKING 0x096c
#define regMMEA5_GMI_RD_PRI_URGENCY_MASKING_BASE_IDX 0
#define regMMEA5_GMI_WR_PRI_URGENCY_MASKING 0x096d
#define regMMEA5_GMI_WR_PRI_URGENCY_MASKING_BASE_IDX 0
#define regMMEA5_GMI_RD_PRI_QUANT_PRI1 0x096e
#define regMMEA5_GMI_RD_PRI_QUANT_PRI1_BASE_IDX 0
#define regMMEA5_GMI_RD_PRI_QUANT_PRI2 0x096f
#define regMMEA5_GMI_RD_PRI_QUANT_PRI2_BASE_IDX 0
#define regMMEA5_GMI_RD_PRI_QUANT_PRI3 0x0970
#define regMMEA5_GMI_RD_PRI_QUANT_PRI3_BASE_IDX 0
#define regMMEA5_GMI_WR_PRI_QUANT_PRI1 0x0971
#define regMMEA5_GMI_WR_PRI_QUANT_PRI1_BASE_IDX 0
#define regMMEA5_GMI_WR_PRI_QUANT_PRI2 0x0972
#define regMMEA5_GMI_WR_PRI_QUANT_PRI2_BASE_IDX 0
#define regMMEA5_GMI_WR_PRI_QUANT_PRI3 0x0973
#define regMMEA5_GMI_WR_PRI_QUANT_PRI3_BASE_IDX 0
#define regMMEA5_ADDRNORM_BASE_ADDR0 0x0974
#define regMMEA5_ADDRNORM_BASE_ADDR0_BASE_IDX 0
#define regMMEA5_ADDRNORM_LIMIT_ADDR0 0x0975
#define regMMEA5_ADDRNORM_LIMIT_ADDR0_BASE_IDX 0
#define regMMEA5_ADDRNORM_BASE_ADDR1 0x0976
#define regMMEA5_ADDRNORM_BASE_ADDR1_BASE_IDX 0
#define regMMEA5_ADDRNORM_LIMIT_ADDR1 0x0977
#define regMMEA5_ADDRNORM_LIMIT_ADDR1_BASE_IDX 0
#define regMMEA5_ADDRNORM_OFFSET_ADDR1 0x0978
#define regMMEA5_ADDRNORM_OFFSET_ADDR1_BASE_IDX 0
#define regMMEA5_ADDRNORM_BASE_ADDR2 0x0979
#define regMMEA5_ADDRNORM_BASE_ADDR2_BASE_IDX 0
#define regMMEA5_ADDRNORM_LIMIT_ADDR2 0x097a
#define regMMEA5_ADDRNORM_LIMIT_ADDR2_BASE_IDX 0
#define regMMEA5_ADDRNORM_BASE_ADDR3 0x097b
#define regMMEA5_ADDRNORM_BASE_ADDR3_BASE_IDX 0
#define regMMEA5_ADDRNORM_LIMIT_ADDR3 0x097c
#define regMMEA5_ADDRNORM_LIMIT_ADDR3_BASE_IDX 0
#define regMMEA5_ADDRNORM_OFFSET_ADDR3 0x097d
#define regMMEA5_ADDRNORM_OFFSET_ADDR3_BASE_IDX 0
#define regMMEA5_ADDRNORM_MEGABASE_ADDR0 0x097e
#define regMMEA5_ADDRNORM_MEGABASE_ADDR0_BASE_IDX 0
#define regMMEA5_ADDRNORM_MEGALIMIT_ADDR0 0x097f
#define regMMEA5_ADDRNORM_MEGALIMIT_ADDR0_BASE_IDX 0
#define regMMEA5_ADDRNORM_MEGABASE_ADDR1 0x0980
#define regMMEA5_ADDRNORM_MEGABASE_ADDR1_BASE_IDX 0
#define regMMEA5_ADDRNORM_MEGALIMIT_ADDR1 0x0981
#define regMMEA5_ADDRNORM_MEGALIMIT_ADDR1_BASE_IDX 0
#define regMMEA5_ADDRNORMDRAM_HOLE_CNTL 0x0983
#define regMMEA5_ADDRNORMDRAM_HOLE_CNTL_BASE_IDX 0
#define regMMEA5_ADDRNORMGMI_HOLE_CNTL 0x0984
#define regMMEA5_ADDRNORMGMI_HOLE_CNTL_BASE_IDX 0
#define regMMEA5_ADDRNORMDRAM_NP2_CHANNEL_CFG 0x0985
#define regMMEA5_ADDRNORMDRAM_NP2_CHANNEL_CFG_BASE_IDX 0
#define regMMEA5_ADDRNORMGMI_NP2_CHANNEL_CFG 0x0986
#define regMMEA5_ADDRNORMGMI_NP2_CHANNEL_CFG_BASE_IDX 0
#define regMMEA5_ADDRDEC_BANK_CFG 0x0987
#define regMMEA5_ADDRDEC_BANK_CFG_BASE_IDX 0
#define regMMEA5_ADDRDEC_MISC_CFG 0x0988
#define regMMEA5_ADDRDEC_MISC_CFG_BASE_IDX 0
#define regMMEA5_ADDRDECDRAM_HARVEST_ENABLE 0x0993
#define regMMEA5_ADDRDECDRAM_HARVEST_ENABLE_BASE_IDX 0
#define regMMEA5_ADDRDECGMI_HARVEST_ENABLE 0x099e
#define regMMEA5_ADDRDECGMI_HARVEST_ENABLE_BASE_IDX 0
#define regMMEA5_ADDRDEC0_BASE_ADDR_CS0 0x099f
#define regMMEA5_ADDRDEC0_BASE_ADDR_CS0_BASE_IDX 0
#define regMMEA5_ADDRDEC0_BASE_ADDR_CS1 0x09a0
#define regMMEA5_ADDRDEC0_BASE_ADDR_CS1_BASE_IDX 0
#define regMMEA5_ADDRDEC0_BASE_ADDR_CS2 0x09a1
#define regMMEA5_ADDRDEC0_BASE_ADDR_CS2_BASE_IDX 0
#define regMMEA5_ADDRDEC0_BASE_ADDR_CS3 0x09a2
#define regMMEA5_ADDRDEC0_BASE_ADDR_CS3_BASE_IDX 0
#define regMMEA5_ADDRDEC0_BASE_ADDR_SECCS0 0x09a3
#define regMMEA5_ADDRDEC0_BASE_ADDR_SECCS0_BASE_IDX 0
#define regMMEA5_ADDRDEC0_BASE_ADDR_SECCS1 0x09a4
#define regMMEA5_ADDRDEC0_BASE_ADDR_SECCS1_BASE_IDX 0
#define regMMEA5_ADDRDEC0_BASE_ADDR_SECCS2 0x09a5
#define regMMEA5_ADDRDEC0_BASE_ADDR_SECCS2_BASE_IDX 0
#define regMMEA5_ADDRDEC0_BASE_ADDR_SECCS3 0x09a6
#define regMMEA5_ADDRDEC0_BASE_ADDR_SECCS3_BASE_IDX 0
#define regMMEA5_ADDRDEC0_ADDR_MASK_CS01 0x09a7
#define regMMEA5_ADDRDEC0_ADDR_MASK_CS01_BASE_IDX 0
#define regMMEA5_ADDRDEC0_ADDR_MASK_CS23 0x09a8
#define regMMEA5_ADDRDEC0_ADDR_MASK_CS23_BASE_IDX 0
#define regMMEA5_ADDRDEC0_ADDR_MASK_SECCS01 0x09a9
#define regMMEA5_ADDRDEC0_ADDR_MASK_SECCS01_BASE_IDX 0
#define regMMEA5_ADDRDEC0_ADDR_MASK_SECCS23 0x09aa
#define regMMEA5_ADDRDEC0_ADDR_MASK_SECCS23_BASE_IDX 0
#define regMMEA5_ADDRDEC0_ADDR_CFG_CS01 0x09ab
#define regMMEA5_ADDRDEC0_ADDR_CFG_CS01_BASE_IDX 0
#define regMMEA5_ADDRDEC0_ADDR_CFG_CS23 0x09ac
#define regMMEA5_ADDRDEC0_ADDR_CFG_CS23_BASE_IDX 0
#define regMMEA5_ADDRDEC0_ADDR_SEL_CS01 0x09ad
#define regMMEA5_ADDRDEC0_ADDR_SEL_CS01_BASE_IDX 0
#define regMMEA5_ADDRDEC0_ADDR_SEL_CS23 0x09ae
#define regMMEA5_ADDRDEC0_ADDR_SEL_CS23_BASE_IDX 0
#define regMMEA5_ADDRDEC0_ADDR_SEL2_CS01 0x09af
#define regMMEA5_ADDRDEC0_ADDR_SEL2_CS01_BASE_IDX 0
#define regMMEA5_ADDRDEC0_ADDR_SEL2_CS23 0x09b0
#define regMMEA5_ADDRDEC0_ADDR_SEL2_CS23_BASE_IDX 0
#define regMMEA5_ADDRDEC0_COL_SEL_LO_CS01 0x09b1
#define regMMEA5_ADDRDEC0_COL_SEL_LO_CS01_BASE_IDX 0
#define regMMEA5_ADDRDEC0_COL_SEL_LO_CS23 0x09b2
#define regMMEA5_ADDRDEC0_COL_SEL_LO_CS23_BASE_IDX 0
#define regMMEA5_ADDRDEC0_COL_SEL_HI_CS01 0x09b3
#define regMMEA5_ADDRDEC0_COL_SEL_HI_CS01_BASE_IDX 0
#define regMMEA5_ADDRDEC0_COL_SEL_HI_CS23 0x09b4
#define regMMEA5_ADDRDEC0_COL_SEL_HI_CS23_BASE_IDX 0
#define regMMEA5_ADDRDEC0_RM_SEL_CS01 0x09b5
#define regMMEA5_ADDRDEC0_RM_SEL_CS01_BASE_IDX 0
#define regMMEA5_ADDRDEC0_RM_SEL_CS23 0x09b6
#define regMMEA5_ADDRDEC0_RM_SEL_CS23_BASE_IDX 0
#define regMMEA5_ADDRDEC0_RM_SEL_SECCS01 0x09b7
#define regMMEA5_ADDRDEC0_RM_SEL_SECCS01_BASE_IDX 0
#define regMMEA5_ADDRDEC0_RM_SEL_SECCS23 0x09b8
#define regMMEA5_ADDRDEC0_RM_SEL_SECCS23_BASE_IDX 0
#define regMMEA5_ADDRDEC1_BASE_ADDR_CS0 0x09b9
#define regMMEA5_ADDRDEC1_BASE_ADDR_CS0_BASE_IDX 0
#define regMMEA5_ADDRDEC1_BASE_ADDR_CS1 0x09ba
#define regMMEA5_ADDRDEC1_BASE_ADDR_CS1_BASE_IDX 0
#define regMMEA5_ADDRDEC1_BASE_ADDR_CS2 0x09bb
#define regMMEA5_ADDRDEC1_BASE_ADDR_CS2_BASE_IDX 0
#define regMMEA5_ADDRDEC1_BASE_ADDR_CS3 0x09bc
#define regMMEA5_ADDRDEC1_BASE_ADDR_CS3_BASE_IDX 0
#define regMMEA5_ADDRDEC1_BASE_ADDR_SECCS0 0x09bd
#define regMMEA5_ADDRDEC1_BASE_ADDR_SECCS0_BASE_IDX 0
#define regMMEA5_ADDRDEC1_BASE_ADDR_SECCS1 0x09be
#define regMMEA5_ADDRDEC1_BASE_ADDR_SECCS1_BASE_IDX 0
#define regMMEA5_ADDRDEC1_BASE_ADDR_SECCS2 0x09bf
#define regMMEA5_ADDRDEC1_BASE_ADDR_SECCS2_BASE_IDX 0
#define regMMEA5_ADDRDEC1_BASE_ADDR_SECCS3 0x09c0
#define regMMEA5_ADDRDEC1_BASE_ADDR_SECCS3_BASE_IDX 0
#define regMMEA5_ADDRDEC1_ADDR_MASK_CS01 0x09c1
#define regMMEA5_ADDRDEC1_ADDR_MASK_CS01_BASE_IDX 0
#define regMMEA5_ADDRDEC1_ADDR_MASK_CS23 0x09c2
#define regMMEA5_ADDRDEC1_ADDR_MASK_CS23_BASE_IDX 0
#define regMMEA5_ADDRDEC1_ADDR_MASK_SECCS01 0x09c3
#define regMMEA5_ADDRDEC1_ADDR_MASK_SECCS01_BASE_IDX 0
#define regMMEA5_ADDRDEC1_ADDR_MASK_SECCS23 0x09c4
#define regMMEA5_ADDRDEC1_ADDR_MASK_SECCS23_BASE_IDX 0
#define regMMEA5_ADDRDEC1_ADDR_CFG_CS01 0x09c5
#define regMMEA5_ADDRDEC1_ADDR_CFG_CS01_BASE_IDX 0
#define regMMEA5_ADDRDEC1_ADDR_CFG_CS23 0x09c6
#define regMMEA5_ADDRDEC1_ADDR_CFG_CS23_BASE_IDX 0
#define regMMEA5_ADDRDEC1_ADDR_SEL_CS01 0x09c7
#define regMMEA5_ADDRDEC1_ADDR_SEL_CS01_BASE_IDX 0
#define regMMEA5_ADDRDEC1_ADDR_SEL_CS23 0x09c8
#define regMMEA5_ADDRDEC1_ADDR_SEL_CS23_BASE_IDX 0
#define regMMEA5_ADDRDEC1_ADDR_SEL2_CS01 0x09c9
#define regMMEA5_ADDRDEC1_ADDR_SEL2_CS01_BASE_IDX 0
#define regMMEA5_ADDRDEC1_ADDR_SEL2_CS23 0x09ca
#define regMMEA5_ADDRDEC1_ADDR_SEL2_CS23_BASE_IDX 0
#define regMMEA5_ADDRDEC1_COL_SEL_LO_CS01 0x09cb
#define regMMEA5_ADDRDEC1_COL_SEL_LO_CS01_BASE_IDX 0
#define regMMEA5_ADDRDEC1_COL_SEL_LO_CS23 0x09cc
#define regMMEA5_ADDRDEC1_COL_SEL_LO_CS23_BASE_IDX 0
#define regMMEA5_ADDRDEC1_COL_SEL_HI_CS01 0x09cd
#define regMMEA5_ADDRDEC1_COL_SEL_HI_CS01_BASE_IDX 0
#define regMMEA5_ADDRDEC1_COL_SEL_HI_CS23 0x09ce
#define regMMEA5_ADDRDEC1_COL_SEL_HI_CS23_BASE_IDX 0
#define regMMEA5_ADDRDEC1_RM_SEL_CS01 0x09cf
#define regMMEA5_ADDRDEC1_RM_SEL_CS01_BASE_IDX 0
#define regMMEA5_ADDRDEC1_RM_SEL_CS23 0x09d0
#define regMMEA5_ADDRDEC1_RM_SEL_CS23_BASE_IDX 0
#define regMMEA5_ADDRDEC1_RM_SEL_SECCS01 0x09d1
#define regMMEA5_ADDRDEC1_RM_SEL_SECCS01_BASE_IDX 0
#define regMMEA5_ADDRDEC1_RM_SEL_SECCS23 0x09d2
#define regMMEA5_ADDRDEC1_RM_SEL_SECCS23_BASE_IDX 0
#define regMMEA5_ADDRDEC2_BASE_ADDR_CS0 0x09d3
#define regMMEA5_ADDRDEC2_BASE_ADDR_CS0_BASE_IDX 0
#define regMMEA5_ADDRDEC2_BASE_ADDR_CS1 0x09d4
#define regMMEA5_ADDRDEC2_BASE_ADDR_CS1_BASE_IDX 0
#define regMMEA5_ADDRDEC2_BASE_ADDR_CS2 0x09d5
#define regMMEA5_ADDRDEC2_BASE_ADDR_CS2_BASE_IDX 0
#define regMMEA5_ADDRDEC2_BASE_ADDR_CS3 0x09d6
#define regMMEA5_ADDRDEC2_BASE_ADDR_CS3_BASE_IDX 0
#define regMMEA5_ADDRDEC2_BASE_ADDR_SECCS0 0x09d7
#define regMMEA5_ADDRDEC2_BASE_ADDR_SECCS0_BASE_IDX 0
#define regMMEA5_ADDRDEC2_BASE_ADDR_SECCS1 0x09d8
#define regMMEA5_ADDRDEC2_BASE_ADDR_SECCS1_BASE_IDX 0
#define regMMEA5_ADDRDEC2_BASE_ADDR_SECCS2 0x09d9
#define regMMEA5_ADDRDEC2_BASE_ADDR_SECCS2_BASE_IDX 0
#define regMMEA5_ADDRDEC2_BASE_ADDR_SECCS3 0x09da
#define regMMEA5_ADDRDEC2_BASE_ADDR_SECCS3_BASE_IDX 0
#define regMMEA5_ADDRDEC2_ADDR_MASK_CS01 0x09db
#define regMMEA5_ADDRDEC2_ADDR_MASK_CS01_BASE_IDX 0
#define regMMEA5_ADDRDEC2_ADDR_MASK_CS23 0x09dc
#define regMMEA5_ADDRDEC2_ADDR_MASK_CS23_BASE_IDX 0
#define regMMEA5_ADDRDEC2_ADDR_MASK_SECCS01 0x09dd
#define regMMEA5_ADDRDEC2_ADDR_MASK_SECCS01_BASE_IDX 0
#define regMMEA5_ADDRDEC2_ADDR_MASK_SECCS23 0x09de
#define regMMEA5_ADDRDEC2_ADDR_MASK_SECCS23_BASE_IDX 0
#define regMMEA5_ADDRDEC2_ADDR_CFG_CS01 0x09df
#define regMMEA5_ADDRDEC2_ADDR_CFG_CS01_BASE_IDX 0
#define regMMEA5_ADDRDEC2_ADDR_CFG_CS23 0x09e0
#define regMMEA5_ADDRDEC2_ADDR_CFG_CS23_BASE_IDX 0
#define regMMEA5_ADDRDEC2_ADDR_SEL_CS01 0x09e1
#define regMMEA5_ADDRDEC2_ADDR_SEL_CS01_BASE_IDX 0
#define regMMEA5_ADDRDEC2_ADDR_SEL_CS23 0x09e2
#define regMMEA5_ADDRDEC2_ADDR_SEL_CS23_BASE_IDX 0
#define regMMEA5_ADDRDEC2_ADDR_SEL2_CS01 0x09e3
#define regMMEA5_ADDRDEC2_ADDR_SEL2_CS01_BASE_IDX 0
#define regMMEA5_ADDRDEC2_ADDR_SEL2_CS23 0x09e4
#define regMMEA5_ADDRDEC2_ADDR_SEL2_CS23_BASE_IDX 0
#define regMMEA5_ADDRDEC2_COL_SEL_LO_CS01 0x09e5
#define regMMEA5_ADDRDEC2_COL_SEL_LO_CS01_BASE_IDX 0
#define regMMEA5_ADDRDEC2_COL_SEL_LO_CS23 0x09e6
#define regMMEA5_ADDRDEC2_COL_SEL_LO_CS23_BASE_IDX 0
#define regMMEA5_ADDRDEC2_COL_SEL_HI_CS01 0x09e7
#define regMMEA5_ADDRDEC2_COL_SEL_HI_CS01_BASE_IDX 0
#define regMMEA5_ADDRDEC2_COL_SEL_HI_CS23 0x09e8
#define regMMEA5_ADDRDEC2_COL_SEL_HI_CS23_BASE_IDX 0
#define regMMEA5_ADDRDEC2_RM_SEL_CS01 0x09e9
#define regMMEA5_ADDRDEC2_RM_SEL_CS01_BASE_IDX 0
#define regMMEA5_ADDRDEC2_RM_SEL_CS23 0x09ea
#define regMMEA5_ADDRDEC2_RM_SEL_CS23_BASE_IDX 0
#define regMMEA5_ADDRDEC2_RM_SEL_SECCS01 0x09eb
#define regMMEA5_ADDRDEC2_RM_SEL_SECCS01_BASE_IDX 0
#define regMMEA5_ADDRDEC2_RM_SEL_SECCS23 0x09ec
#define regMMEA5_ADDRDEC2_RM_SEL_SECCS23_BASE_IDX 0
#define regMMEA5_ADDRNORMDRAM_GLOBAL_CNTL 0x09ed
#define regMMEA5_ADDRNORMDRAM_GLOBAL_CNTL_BASE_IDX 0
#define regMMEA5_ADDRNORMGMI_GLOBAL_CNTL 0x09ee
#define regMMEA5_ADDRNORMGMI_GLOBAL_CNTL_BASE_IDX 0
#define regMMEA5_ADDRNORM_MEGACONTROL_ADDR0 0x0a11
#define regMMEA5_ADDRNORM_MEGACONTROL_ADDR0_BASE_IDX 0
#define regMMEA5_ADDRNORM_MEGACONTROL_ADDR1 0x0a12
#define regMMEA5_ADDRNORM_MEGACONTROL_ADDR1_BASE_IDX 0
#define regMMEA5_ADDRNORMDRAM_MASKING 0x0a13
#define regMMEA5_ADDRNORMDRAM_MASKING_BASE_IDX 0
#define regMMEA5_ADDRNORMGMI_MASKING 0x0a14
#define regMMEA5_ADDRNORMGMI_MASKING_BASE_IDX 0
#define regMMEA5_IO_RD_CLI2GRP_MAP0 0x0a15
#define regMMEA5_IO_RD_CLI2GRP_MAP0_BASE_IDX 0
#define regMMEA5_IO_RD_CLI2GRP_MAP1 0x0a16
#define regMMEA5_IO_RD_CLI2GRP_MAP1_BASE_IDX 0
#define regMMEA5_IO_WR_CLI2GRP_MAP0 0x0a17
#define regMMEA5_IO_WR_CLI2GRP_MAP0_BASE_IDX 0
#define regMMEA5_IO_WR_CLI2GRP_MAP1 0x0a18
#define regMMEA5_IO_WR_CLI2GRP_MAP1_BASE_IDX 0
#define regMMEA5_IO_RD_COMBINE_FLUSH 0x0a19
#define regMMEA5_IO_RD_COMBINE_FLUSH_BASE_IDX 0
#define regMMEA5_IO_WR_COMBINE_FLUSH 0x0a1a
#define regMMEA5_IO_WR_COMBINE_FLUSH_BASE_IDX 0
#define regMMEA5_IO_GROUP_BURST 0x0a1b
#define regMMEA5_IO_GROUP_BURST_BASE_IDX 0
#define regMMEA5_IO_RD_PRI_AGE 0x0a1c
#define regMMEA5_IO_RD_PRI_AGE_BASE_IDX 0
#define regMMEA5_IO_WR_PRI_AGE 0x0a1d
#define regMMEA5_IO_WR_PRI_AGE_BASE_IDX 0
#define regMMEA5_IO_RD_PRI_QUEUING 0x0a1e
#define regMMEA5_IO_RD_PRI_QUEUING_BASE_IDX 0
#define regMMEA5_IO_WR_PRI_QUEUING 0x0a1f
#define regMMEA5_IO_WR_PRI_QUEUING_BASE_IDX 0
#define regMMEA5_IO_RD_PRI_FIXED 0x0a20
#define regMMEA5_IO_RD_PRI_FIXED_BASE_IDX 0
#define regMMEA5_IO_WR_PRI_FIXED 0x0a21
#define regMMEA5_IO_WR_PRI_FIXED_BASE_IDX 0
#define regMMEA5_IO_RD_PRI_URGENCY 0x0a22
#define regMMEA5_IO_RD_PRI_URGENCY_BASE_IDX 0
#define regMMEA5_IO_WR_PRI_URGENCY 0x0a23
#define regMMEA5_IO_WR_PRI_URGENCY_BASE_IDX 0
#define regMMEA5_IO_RD_PRI_URGENCY_MASKING 0x0a24
#define regMMEA5_IO_RD_PRI_URGENCY_MASKING_BASE_IDX 0
#define regMMEA5_IO_WR_PRI_URGENCY_MASKING 0x0a25
#define regMMEA5_IO_WR_PRI_URGENCY_MASKING_BASE_IDX 0
#define regMMEA5_IO_RD_PRI_QUANT_PRI1 0x0a26
#define regMMEA5_IO_RD_PRI_QUANT_PRI1_BASE_IDX 0
#define regMMEA5_IO_RD_PRI_QUANT_PRI2 0x0a27
#define regMMEA5_IO_RD_PRI_QUANT_PRI2_BASE_IDX 0
#define regMMEA5_IO_RD_PRI_QUANT_PRI3 0x0a28
#define regMMEA5_IO_RD_PRI_QUANT_PRI3_BASE_IDX 0
#define regMMEA5_IO_WR_PRI_QUANT_PRI1 0x0a29
#define regMMEA5_IO_WR_PRI_QUANT_PRI1_BASE_IDX 0
#define regMMEA5_IO_WR_PRI_QUANT_PRI2 0x0a2a
#define regMMEA5_IO_WR_PRI_QUANT_PRI2_BASE_IDX 0
#define regMMEA5_IO_WR_PRI_QUANT_PRI3 0x0a2b
#define regMMEA5_IO_WR_PRI_QUANT_PRI3_BASE_IDX 0
#define regMMEA5_SDP_ARB_DRAM 0x0a2c
#define regMMEA5_SDP_ARB_DRAM_BASE_IDX 0
#define regMMEA5_SDP_ARB_GMI 0x0a2d
#define regMMEA5_SDP_ARB_GMI_BASE_IDX 0
#define regMMEA5_SDP_ARB_FINAL 0x0a2e
#define regMMEA5_SDP_ARB_FINAL_BASE_IDX 0
#define regMMEA5_SDP_DRAM_PRIORITY 0x0a2f
#define regMMEA5_SDP_DRAM_PRIORITY_BASE_IDX 0
#define regMMEA5_SDP_GMI_PRIORITY 0x0a30
#define regMMEA5_SDP_GMI_PRIORITY_BASE_IDX 0
#define regMMEA5_SDP_IO_PRIORITY 0x0a31
#define regMMEA5_SDP_IO_PRIORITY_BASE_IDX 0
#define regMMEA5_SDP_CREDITS 0x0a32
#define regMMEA5_SDP_CREDITS_BASE_IDX 0
#define regMMEA5_SDP_TAG_RESERVE0 0x0a33
#define regMMEA5_SDP_TAG_RESERVE0_BASE_IDX 0
#define regMMEA5_SDP_TAG_RESERVE1 0x0a34
#define regMMEA5_SDP_TAG_RESERVE1_BASE_IDX 0
#define regMMEA5_SDP_VCC_RESERVE0 0x0a35
#define regMMEA5_SDP_VCC_RESERVE0_BASE_IDX 0
#define regMMEA5_SDP_VCC_RESERVE1 0x0a36
#define regMMEA5_SDP_VCC_RESERVE1_BASE_IDX 0
#define regMMEA5_SDP_VCD_RESERVE0 0x0a37
#define regMMEA5_SDP_VCD_RESERVE0_BASE_IDX 0
#define regMMEA5_SDP_VCD_RESERVE1 0x0a38
#define regMMEA5_SDP_VCD_RESERVE1_BASE_IDX 0
#define regMMEA5_SDP_REQ_CNTL 0x0a39
#define regMMEA5_SDP_REQ_CNTL_BASE_IDX 0
#define regMMEA5_MISC 0x0a3a
#define regMMEA5_MISC_BASE_IDX 0
#define regMMEA5_LATENCY_SAMPLING 0x0a3b
#define regMMEA5_LATENCY_SAMPLING_BASE_IDX 0
#define regMMEA5_PERFCOUNTER_LO 0x0a3c
#define regMMEA5_PERFCOUNTER_LO_BASE_IDX 0
#define regMMEA5_PERFCOUNTER_HI 0x0a3d
#define regMMEA5_PERFCOUNTER_HI_BASE_IDX 0
#define regMMEA5_PERFCOUNTER0_CFG 0x0a3e
#define regMMEA5_PERFCOUNTER0_CFG_BASE_IDX 0
#define regMMEA5_PERFCOUNTER1_CFG 0x0a3f
#define regMMEA5_PERFCOUNTER1_CFG_BASE_IDX 0
#define regMMEA5_PERFCOUNTER_RSLT_CNTL 0x0a40
#define regMMEA5_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0
#define regMMEA5_EDC_CNT 0x0a46
#define regMMEA5_EDC_CNT_BASE_IDX 0
#define regMMEA5_EDC_CNT2 0x0a47
#define regMMEA5_EDC_CNT2_BASE_IDX 0
#define regMMEA5_DSM_CNTL 0x0a48
#define regMMEA5_DSM_CNTL_BASE_IDX 0
#define regMMEA5_DSM_CNTLA 0x0a49
#define regMMEA5_DSM_CNTLA_BASE_IDX 0
#define regMMEA5_DSM_CNTLB 0x0a4a
#define regMMEA5_DSM_CNTLB_BASE_IDX 0
#define regMMEA5_DSM_CNTL2 0x0a4b
#define regMMEA5_DSM_CNTL2_BASE_IDX 0
#define regMMEA5_DSM_CNTL2A 0x0a4c
#define regMMEA5_DSM_CNTL2A_BASE_IDX 0
#define regMMEA5_DSM_CNTL2B 0x0a4d
#define regMMEA5_DSM_CNTL2B_BASE_IDX 0
#define regMMEA5_CGTT_CLK_CTRL 0x0a4f
#define regMMEA5_CGTT_CLK_CTRL_BASE_IDX 0
#define regMMEA5_EDC_MODE 0x0a50
#define regMMEA5_EDC_MODE_BASE_IDX 0
#define regMMEA5_ERR_STATUS 0x0a51
#define regMMEA5_ERR_STATUS_BASE_IDX 0
#define regMMEA5_MISC2 0x0a52
#define regMMEA5_MISC2_BASE_IDX 0
#define regMMEA5_ADDRDEC_SELECT 0x0a53
#define regMMEA5_ADDRDEC_SELECT_BASE_IDX 0
#define regMMEA5_EDC_CNT3 0x0a54
#define regMMEA5_EDC_CNT3_BASE_IDX 0
#define regMMEA5_MISC_AON 0x0a55
#define regMMEA5_MISC_AON_BASE_IDX 0
// addressBlock: mmhub_l1tlb_vml1dec
// base address: 0x6ac00
#define regMC_VM_MX_L1_TLB0_STATUS 0x0b08
#define regMC_VM_MX_L1_TLB0_STATUS_BASE_IDX 0
#define regMC_VM_MX_L1_TLB1_STATUS 0x0b09
#define regMC_VM_MX_L1_TLB1_STATUS_BASE_IDX 0
#define regMC_VM_MX_L1_TLB2_STATUS 0x0b0a
#define regMC_VM_MX_L1_TLB2_STATUS_BASE_IDX 0
#define regMC_VM_MX_L1_TLB3_STATUS 0x0b0b
#define regMC_VM_MX_L1_TLB3_STATUS_BASE_IDX 0
#define regMC_VM_MX_L1_TLB4_STATUS 0x0b0c
#define regMC_VM_MX_L1_TLB4_STATUS_BASE_IDX 0
#define regMC_VM_MX_L1_TLB5_STATUS 0x0b0d
#define regMC_VM_MX_L1_TLB5_STATUS_BASE_IDX 0
#define regMC_VM_MX_L1_TLB6_STATUS 0x0b0e
#define regMC_VM_MX_L1_TLB6_STATUS_BASE_IDX 0
#define regMC_VM_MX_L1_TLB7_STATUS 0x0b0f
#define regMC_VM_MX_L1_TLB7_STATUS_BASE_IDX 0
// addressBlock: mmhub_l1tlb_vml1pldec
// base address: 0x6ac80
#define regMC_VM_MX_L1_PERFCOUNTER0_CFG 0x0b20
#define regMC_VM_MX_L1_PERFCOUNTER0_CFG_BASE_IDX 0
#define regMC_VM_MX_L1_PERFCOUNTER1_CFG 0x0b21
#define regMC_VM_MX_L1_PERFCOUNTER1_CFG_BASE_IDX 0
#define regMC_VM_MX_L1_PERFCOUNTER2_CFG 0x0b22
#define regMC_VM_MX_L1_PERFCOUNTER2_CFG_BASE_IDX 0
#define regMC_VM_MX_L1_PERFCOUNTER3_CFG 0x0b23
#define regMC_VM_MX_L1_PERFCOUNTER3_CFG_BASE_IDX 0
#define regMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL 0x0b24
#define regMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0
// addressBlock: mmhub_l1tlb_vml1prdec
// base address: 0x6acc0
#define regMC_VM_MX_L1_PERFCOUNTER_LO 0x0b30
#define regMC_VM_MX_L1_PERFCOUNTER_LO_BASE_IDX 0
#define regMC_VM_MX_L1_PERFCOUNTER_HI 0x0b31
#define regMC_VM_MX_L1_PERFCOUNTER_HI_BASE_IDX 0
// addressBlock: mmhub_pctldec0
// base address: 0x6aa00
#define regPCTL0_CTRL 0x0a80
#define regPCTL0_CTRL_BASE_IDX 0
#define regPCTL0_MMHUB_DEEPSLEEP_IB 0x0a81
#define regPCTL0_MMHUB_DEEPSLEEP_IB_BASE_IDX 0
#define regPCTL0_MMHUB_DEEPSLEEP_OVERRIDE 0x0a82
#define regPCTL0_MMHUB_DEEPSLEEP_OVERRIDE_BASE_IDX 0
#define regPCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB 0x0a83
#define regPCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB_BASE_IDX 0
#define regPCTL0_PG_IGNORE_DEEPSLEEP 0x0a84
#define regPCTL0_PG_IGNORE_DEEPSLEEP_BASE_IDX 0
#define regPCTL0_PG_IGNORE_DEEPSLEEP_IB 0x0a85
#define regPCTL0_PG_IGNORE_DEEPSLEEP_IB_BASE_IDX 0
#define regPCTL0_SLICE0_CFG_DAGB_BUSY 0x0a86
#define regPCTL0_SLICE0_CFG_DAGB_BUSY_BASE_IDX 0
#define regPCTL0_SLICE0_CFG_DS_ALLOW 0x0a87
#define regPCTL0_SLICE0_CFG_DS_ALLOW_BASE_IDX 0
#define regPCTL0_SLICE0_CFG_DS_ALLOW_IB 0x0a88
#define regPCTL0_SLICE0_CFG_DS_ALLOW_IB_BASE_IDX 0
#define regPCTL0_SLICE1_CFG_DAGB_BUSY 0x0a89
#define regPCTL0_SLICE1_CFG_DAGB_BUSY_BASE_IDX 0
#define regPCTL0_SLICE1_CFG_DS_ALLOW 0x0a8a
#define regPCTL0_SLICE1_CFG_DS_ALLOW_BASE_IDX 0
#define regPCTL0_SLICE1_CFG_DS_ALLOW_IB 0x0a8b
#define regPCTL0_SLICE1_CFG_DS_ALLOW_IB_BASE_IDX 0
#define regPCTL0_SLICE2_CFG_DAGB_BUSY 0x0a8c
#define regPCTL0_SLICE2_CFG_DAGB_BUSY_BASE_IDX 0
#define regPCTL0_SLICE2_CFG_DS_ALLOW 0x0a8d
#define regPCTL0_SLICE2_CFG_DS_ALLOW_BASE_IDX 0
#define regPCTL0_SLICE2_CFG_DS_ALLOW_IB 0x0a8e
#define regPCTL0_SLICE2_CFG_DS_ALLOW_IB_BASE_IDX 0
#define regPCTL0_SLICE3_CFG_DAGB_BUSY 0x0a8f
#define regPCTL0_SLICE3_CFG_DAGB_BUSY_BASE_IDX 0
#define regPCTL0_SLICE3_CFG_DS_ALLOW 0x0a90
#define regPCTL0_SLICE3_CFG_DS_ALLOW_BASE_IDX 0
#define regPCTL0_SLICE3_CFG_DS_ALLOW_IB 0x0a91
#define regPCTL0_SLICE3_CFG_DS_ALLOW_IB_BASE_IDX 0
#define regPCTL0_SLICE4_CFG_DAGB_BUSY 0x0a92
#define regPCTL0_SLICE4_CFG_DAGB_BUSY_BASE_IDX 0
#define regPCTL0_SLICE4_CFG_DS_ALLOW 0x0a93
#define regPCTL0_SLICE4_CFG_DS_ALLOW_BASE_IDX 0
#define regPCTL0_SLICE4_CFG_DS_ALLOW_IB 0x0a94
#define regPCTL0_SLICE4_CFG_DS_ALLOW_IB_BASE_IDX 0
#define regPCTL0_SLICE5_CFG_DAGB_BUSY 0x0a95
#define regPCTL0_SLICE5_CFG_DAGB_BUSY_BASE_IDX 0
#define regPCTL0_SLICE5_CFG_DS_ALLOW 0x0a96
#define regPCTL0_SLICE5_CFG_DS_ALLOW_BASE_IDX 0
#define regPCTL0_SLICE5_CFG_DS_ALLOW_IB 0x0a97
#define regPCTL0_SLICE5_CFG_DS_ALLOW_IB_BASE_IDX 0
#define regPCTL0_UTCL2_MISC 0x0a98
#define regPCTL0_UTCL2_MISC_BASE_IDX 0
#define regPCTL0_SLICE0_MISC 0x0a99
#define regPCTL0_SLICE0_MISC_BASE_IDX 0
#define regPCTL0_SLICE1_MISC 0x0a9a
#define regPCTL0_SLICE1_MISC_BASE_IDX 0
#define regPCTL0_SLICE2_MISC 0x0a9b
#define regPCTL0_SLICE2_MISC_BASE_IDX 0
#define regPCTL0_SLICE3_MISC 0x0a9c
#define regPCTL0_SLICE3_MISC_BASE_IDX 0
#define regPCTL0_SLICE4_MISC 0x0a9d
#define regPCTL0_SLICE4_MISC_BASE_IDX 0
#define regPCTL0_SLICE5_MISC 0x0a9e
#define regPCTL0_SLICE5_MISC_BASE_IDX 0
// addressBlock: mmhub_utcl2_atcl2dec
// base address: 0x6ad00
#define regATC_L2_CNTL 0x0b40
#define regATC_L2_CNTL_BASE_IDX 0
#define regATC_L2_CNTL2 0x0b41
#define regATC_L2_CNTL2_BASE_IDX 0
#define regATC_L2_CACHE_DATA0 0x0b44
#define regATC_L2_CACHE_DATA0_BASE_IDX 0
#define regATC_L2_CACHE_DATA1 0x0b45
#define regATC_L2_CACHE_DATA1_BASE_IDX 0
#define regATC_L2_CACHE_DATA2 0x0b46
#define regATC_L2_CACHE_DATA2_BASE_IDX 0
#define regATC_L2_CACHE_DATA3 0x0b47
#define regATC_L2_CACHE_DATA3_BASE_IDX 0
#define regATC_L2_CNTL3 0x0b48
#define regATC_L2_CNTL3_BASE_IDX 0
#define regATC_L2_STATUS 0x0b49
#define regATC_L2_STATUS_BASE_IDX 0
#define regATC_L2_STATUS2 0x0b4a
#define regATC_L2_STATUS2_BASE_IDX 0
#define regATC_L2_MISC_CG 0x0b4b
#define regATC_L2_MISC_CG_BASE_IDX 0
#define regATC_L2_MEM_POWER_LS 0x0b4c
#define regATC_L2_MEM_POWER_LS_BASE_IDX 0
#define regATC_L2_CGTT_CLK_CTRL 0x0b4d
#define regATC_L2_CGTT_CLK_CTRL_BASE_IDX 0
#define regATC_L2_CACHE_4K_DSM_INDEX 0x0b4e
#define regATC_L2_CACHE_4K_DSM_INDEX_BASE_IDX 0
#define regATC_L2_CACHE_32K_DSM_INDEX 0x0b4f
#define regATC_L2_CACHE_32K_DSM_INDEX_BASE_IDX 0
#define regATC_L2_CACHE_2M_DSM_INDEX 0x0b50
#define regATC_L2_CACHE_2M_DSM_INDEX_BASE_IDX 0
#define regATC_L2_CACHE_4K_DSM_CNTL 0x0b51
#define regATC_L2_CACHE_4K_DSM_CNTL_BASE_IDX 0
#define regATC_L2_CACHE_32K_DSM_CNTL 0x0b52
#define regATC_L2_CACHE_32K_DSM_CNTL_BASE_IDX 0
#define regATC_L2_CACHE_2M_DSM_CNTL 0x0b53
#define regATC_L2_CACHE_2M_DSM_CNTL_BASE_IDX 0
#define regATC_L2_CNTL4 0x0b54
#define regATC_L2_CNTL4_BASE_IDX 0
#define regATC_L2_MM_GROUP_RT_CLASSES 0x0b55
#define regATC_L2_MM_GROUP_RT_CLASSES_BASE_IDX 0
// addressBlock: mmhub_utcl2_atcl2pfcntldec
// base address: 0x6b4d0
#define regATC_L2_PERFCOUNTER0_CFG 0x0d34
#define regATC_L2_PERFCOUNTER0_CFG_BASE_IDX 0
#define regATC_L2_PERFCOUNTER1_CFG 0x0d35
#define regATC_L2_PERFCOUNTER1_CFG_BASE_IDX 0
#define regATC_L2_PERFCOUNTER_RSLT_CNTL 0x0d36
#define regATC_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0
// addressBlock: mmhub_utcl2_atcl2pfcntrdec
// base address: 0x6b4c0
#define regATC_L2_PERFCOUNTER_LO 0x0d30
#define regATC_L2_PERFCOUNTER_LO_BASE_IDX 0
#define regATC_L2_PERFCOUNTER_HI 0x0d31
#define regATC_L2_PERFCOUNTER_HI_BASE_IDX 0
// addressBlock: mmhub_utcl2_l2tlbdec
// base address: 0x6b580
#define regL2TLB_TLB0_STATUS 0x0d61
#define regL2TLB_TLB0_STATUS_BASE_IDX 0
#define regUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO 0x0d63
#define regUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO_BASE_IDX 0
#define regUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI 0x0d64
#define regUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI_BASE_IDX 0
#define regUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO 0x0d65
#define regUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO_BASE_IDX 0
#define regUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI 0x0d66
#define regUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI_BASE_IDX 0
// addressBlock: mmhub_utcl2_l2tlbpldec
// base address: 0x6b5a0
#define regL2TLB_PERFCOUNTER0_CFG 0x0d68
#define regL2TLB_PERFCOUNTER0_CFG_BASE_IDX 0
#define regL2TLB_PERFCOUNTER1_CFG 0x0d69
#define regL2TLB_PERFCOUNTER1_CFG_BASE_IDX 0
#define regL2TLB_PERFCOUNTER2_CFG 0x0d6a
#define regL2TLB_PERFCOUNTER2_CFG_BASE_IDX 0
#define regL2TLB_PERFCOUNTER3_CFG 0x0d6b
#define regL2TLB_PERFCOUNTER3_CFG_BASE_IDX 0
#define regL2TLB_PERFCOUNTER_RSLT_CNTL 0x0d6c
#define regL2TLB_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0
// addressBlock: mmhub_utcl2_l2tlbprdec
// base address: 0x6b5c0
#define regL2TLB_PERFCOUNTER_LO 0x0d70
#define regL2TLB_PERFCOUNTER_LO_BASE_IDX 0
#define regL2TLB_PERFCOUNTER_HI 0x0d71
#define regL2TLB_PERFCOUNTER_HI_BASE_IDX 0
// addressBlock: mmhub_utcl2_vml2pfdec
// base address: 0x6ae00
#define regVM_L2_CNTL 0x0b80
#define regVM_L2_CNTL_BASE_IDX 0
#define regVM_L2_CNTL2 0x0b81
#define regVM_L2_CNTL2_BASE_IDX 0
#define regVM_L2_CNTL3 0x0b82
#define regVM_L2_CNTL3_BASE_IDX 0
#define regVM_L2_STATUS 0x0b83
#define regVM_L2_STATUS_BASE_IDX 0
#define regVM_DUMMY_PAGE_FAULT_CNTL 0x0b84
#define regVM_DUMMY_PAGE_FAULT_CNTL_BASE_IDX 0
#define regVM_DUMMY_PAGE_FAULT_ADDR_LO32 0x0b85
#define regVM_DUMMY_PAGE_FAULT_ADDR_LO32_BASE_IDX 0
#define regVM_DUMMY_PAGE_FAULT_ADDR_HI32 0x0b86
#define regVM_DUMMY_PAGE_FAULT_ADDR_HI32_BASE_IDX 0
#define regVM_L2_PROTECTION_FAULT_CNTL 0x0b87
#define regVM_L2_PROTECTION_FAULT_CNTL_BASE_IDX 0
#define regVM_L2_PROTECTION_FAULT_CNTL2 0x0b88
#define regVM_L2_PROTECTION_FAULT_CNTL2_BASE_IDX 0
#define regVM_L2_PROTECTION_FAULT_MM_CNTL3 0x0b89
#define regVM_L2_PROTECTION_FAULT_MM_CNTL3_BASE_IDX 0
#define regVM_L2_PROTECTION_FAULT_MM_CNTL4 0x0b8a
#define regVM_L2_PROTECTION_FAULT_MM_CNTL4_BASE_IDX 0
#define regVM_L2_PROTECTION_FAULT_STATUS 0x0b8b
#define regVM_L2_PROTECTION_FAULT_STATUS_BASE_IDX 0
#define regVM_L2_PROTECTION_FAULT_ADDR_LO32 0x0b8c
#define regVM_L2_PROTECTION_FAULT_ADDR_LO32_BASE_IDX 0
#define regVM_L2_PROTECTION_FAULT_ADDR_HI32 0x0b8d
#define regVM_L2_PROTECTION_FAULT_ADDR_HI32_BASE_IDX 0
#define regVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32 0x0b8e
#define regVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32_BASE_IDX 0
#define regVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32 0x0b8f
#define regVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32_BASE_IDX 0
#define regVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32 0x0b91
#define regVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32_BASE_IDX 0
#define regVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32 0x0b92
#define regVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32_BASE_IDX 0
#define regVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32 0x0b93
#define regVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32_BASE_IDX 0
#define regVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32 0x0b94
#define regVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32_BASE_IDX 0
#define regVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32 0x0b95
#define regVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32_BASE_IDX 0
#define regVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32 0x0b96
#define regVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32_BASE_IDX 0
#define regVM_L2_CNTL4 0x0b97
#define regVM_L2_CNTL4_BASE_IDX 0
#define regVM_L2_MM_GROUP_RT_CLASSES 0x0b98
#define regVM_L2_MM_GROUP_RT_CLASSES_BASE_IDX 0
#define regVM_L2_BANK_SELECT_RESERVED_CID 0x0b99
#define regVM_L2_BANK_SELECT_RESERVED_CID_BASE_IDX 0
#define regVM_L2_BANK_SELECT_RESERVED_CID2 0x0b9a
#define regVM_L2_BANK_SELECT_RESERVED_CID2_BASE_IDX 0
#define regVM_L2_CACHE_PARITY_CNTL 0x0b9b
#define regVM_L2_CACHE_PARITY_CNTL_BASE_IDX 0
#define regVM_L2_CGTT_CLK_CTRL 0x0b9e
#define regVM_L2_CGTT_CLK_CTRL_BASE_IDX 0
#define regVM_L2_CGTT_BUSY_CTRL 0x0b9f
#define regVM_L2_CGTT_BUSY_CTRL_BASE_IDX 0
#define regVML2_MEM_ECC_INDEX 0x0ba1
#define regVML2_MEM_ECC_INDEX_BASE_IDX 0
#define regVML2_WALKER_MEM_ECC_INDEX 0x0ba2
#define regVML2_WALKER_MEM_ECC_INDEX_BASE_IDX 0
#define regUTCL2_MEM_ECC_INDEX 0x0ba3
#define regUTCL2_MEM_ECC_INDEX_BASE_IDX 0
#define regVML2_MEM_ECC_CNTL 0x0ba4
#define regVML2_MEM_ECC_CNTL_BASE_IDX 0
#define regVML2_WALKER_MEM_ECC_CNTL 0x0ba5
#define regVML2_WALKER_MEM_ECC_CNTL_BASE_IDX 0
#define regUTCL2_MEM_ECC_CNTL 0x0ba6
#define regUTCL2_MEM_ECC_CNTL_BASE_IDX 0
#define regVML2_MEM_ECC_STATUS 0x0ba7
#define regVML2_MEM_ECC_STATUS_BASE_IDX 0
#define regVML2_WALKER_MEM_ECC_STATUS 0x0ba8
#define regVML2_WALKER_MEM_ECC_STATUS_BASE_IDX 0
#define regUTCL2_MEM_ECC_STATUS 0x0ba9
#define regUTCL2_MEM_ECC_STATUS_BASE_IDX 0
#define regUTCL2_EDC_MODE 0x0baa
#define regUTCL2_EDC_MODE_BASE_IDX 0
#define regUTCL2_EDC_CONFIG 0x0bab
#define regUTCL2_EDC_CONFIG_BASE_IDX 0
// addressBlock: mmhub_utcl2_vml2pldec
// base address: 0x6b500
#define regMC_VM_L2_PERFCOUNTER0_CFG 0x0d40
#define regMC_VM_L2_PERFCOUNTER0_CFG_BASE_IDX 0
#define regMC_VM_L2_PERFCOUNTER1_CFG 0x0d41
#define regMC_VM_L2_PERFCOUNTER1_CFG_BASE_IDX 0
#define regMC_VM_L2_PERFCOUNTER2_CFG 0x0d42
#define regMC_VM_L2_PERFCOUNTER2_CFG_BASE_IDX 0
#define regMC_VM_L2_PERFCOUNTER3_CFG 0x0d43
#define regMC_VM_L2_PERFCOUNTER3_CFG_BASE_IDX 0
#define regMC_VM_L2_PERFCOUNTER4_CFG 0x0d44
#define regMC_VM_L2_PERFCOUNTER4_CFG_BASE_IDX 0
#define regMC_VM_L2_PERFCOUNTER5_CFG 0x0d45
#define regMC_VM_L2_PERFCOUNTER5_CFG_BASE_IDX 0
#define regMC_VM_L2_PERFCOUNTER6_CFG 0x0d46
#define regMC_VM_L2_PERFCOUNTER6_CFG_BASE_IDX 0
#define regMC_VM_L2_PERFCOUNTER7_CFG 0x0d47
#define regMC_VM_L2_PERFCOUNTER7_CFG_BASE_IDX 0
#define regMC_VM_L2_PERFCOUNTER_RSLT_CNTL 0x0d48
#define regMC_VM_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0
// addressBlock: mmhub_utcl2_vml2prdec
// base address: 0x6b540
#define regMC_VM_L2_PERFCOUNTER_LO 0x0d50
#define regMC_VM_L2_PERFCOUNTER_LO_BASE_IDX 0
#define regMC_VM_L2_PERFCOUNTER_HI 0x0d51
#define regMC_VM_L2_PERFCOUNTER_HI_BASE_IDX 0
// addressBlock: mmhub_utcl2_vml2vcdec
// base address: 0x6af00
#define regVM_CONTEXT0_CNTL 0x0bc0
#define regVM_CONTEXT0_CNTL_BASE_IDX 0
#define regVM_CONTEXT1_CNTL 0x0bc1
#define regVM_CONTEXT1_CNTL_BASE_IDX 0
#define regVM_CONTEXT2_CNTL 0x0bc2
#define regVM_CONTEXT2_CNTL_BASE_IDX 0
#define regVM_CONTEXT3_CNTL 0x0bc3
#define regVM_CONTEXT3_CNTL_BASE_IDX 0
#define regVM_CONTEXT4_CNTL 0x0bc4
#define regVM_CONTEXT4_CNTL_BASE_IDX 0
#define regVM_CONTEXT5_CNTL 0x0bc5
#define regVM_CONTEXT5_CNTL_BASE_IDX 0
#define regVM_CONTEXT6_CNTL 0x0bc6
#define regVM_CONTEXT6_CNTL_BASE_IDX 0
#define regVM_CONTEXT7_CNTL 0x0bc7
#define regVM_CONTEXT7_CNTL_BASE_IDX 0
#define regVM_CONTEXT8_CNTL 0x0bc8
#define regVM_CONTEXT8_CNTL_BASE_IDX 0
#define regVM_CONTEXT9_CNTL 0x0bc9
#define regVM_CONTEXT9_CNTL_BASE_IDX 0
#define regVM_CONTEXT10_CNTL 0x0bca
#define regVM_CONTEXT10_CNTL_BASE_IDX 0
#define regVM_CONTEXT11_CNTL 0x0bcb
#define regVM_CONTEXT11_CNTL_BASE_IDX 0
#define regVM_CONTEXT12_CNTL 0x0bcc
#define regVM_CONTEXT12_CNTL_BASE_IDX 0
#define regVM_CONTEXT13_CNTL 0x0bcd
#define regVM_CONTEXT13_CNTL_BASE_IDX 0
#define regVM_CONTEXT14_CNTL 0x0bce
#define regVM_CONTEXT14_CNTL_BASE_IDX 0
#define regVM_CONTEXT15_CNTL 0x0bcf
#define regVM_CONTEXT15_CNTL_BASE_IDX 0
#define regVM_CONTEXTS_DISABLE 0x0bd0
#define regVM_CONTEXTS_DISABLE_BASE_IDX 0
#define regVM_INVALIDATE_ENG0_SEM 0x0bd1
#define regVM_INVALIDATE_ENG0_SEM_BASE_IDX 0
#define regVM_INVALIDATE_ENG1_SEM 0x0bd2
#define regVM_INVALIDATE_ENG1_SEM_BASE_IDX 0
#define regVM_INVALIDATE_ENG2_SEM 0x0bd3
#define regVM_INVALIDATE_ENG2_SEM_BASE_IDX 0
#define regVM_INVALIDATE_ENG3_SEM 0x0bd4
#define regVM_INVALIDATE_ENG3_SEM_BASE_IDX 0
#define regVM_INVALIDATE_ENG4_SEM 0x0bd5
#define regVM_INVALIDATE_ENG4_SEM_BASE_IDX 0
#define regVM_INVALIDATE_ENG5_SEM 0x0bd6
#define regVM_INVALIDATE_ENG5_SEM_BASE_IDX 0
#define regVM_INVALIDATE_ENG6_SEM 0x0bd7
#define regVM_INVALIDATE_ENG6_SEM_BASE_IDX 0
#define regVM_INVALIDATE_ENG7_SEM 0x0bd8
#define regVM_INVALIDATE_ENG7_SEM_BASE_IDX 0
#define regVM_INVALIDATE_ENG8_SEM 0x0bd9
#define regVM_INVALIDATE_ENG8_SEM_BASE_IDX 0
#define regVM_INVALIDATE_ENG9_SEM 0x0bda
#define regVM_INVALIDATE_ENG9_SEM_BASE_IDX 0
#define regVM_INVALIDATE_ENG10_SEM 0x0bdb
#define regVM_INVALIDATE_ENG10_SEM_BASE_IDX 0
#define regVM_INVALIDATE_ENG11_SEM 0x0bdc
#define regVM_INVALIDATE_ENG11_SEM_BASE_IDX 0
#define regVM_INVALIDATE_ENG12_SEM 0x0bdd
#define regVM_INVALIDATE_ENG12_SEM_BASE_IDX 0
#define regVM_INVALIDATE_ENG13_SEM 0x0bde
#define regVM_INVALIDATE_ENG13_SEM_BASE_IDX 0
#define regVM_INVALIDATE_ENG14_SEM 0x0bdf
#define regVM_INVALIDATE_ENG14_SEM_BASE_IDX 0
#define regVM_INVALIDATE_ENG15_SEM 0x0be0
#define regVM_INVALIDATE_ENG15_SEM_BASE_IDX 0
#define regVM_INVALIDATE_ENG16_SEM 0x0be1
#define regVM_INVALIDATE_ENG16_SEM_BASE_IDX 0
#define regVM_INVALIDATE_ENG17_SEM 0x0be2
#define regVM_INVALIDATE_ENG17_SEM_BASE_IDX 0
#define regVM_INVALIDATE_ENG0_REQ 0x0be3
#define regVM_INVALIDATE_ENG0_REQ_BASE_IDX 0
#define regVM_INVALIDATE_ENG1_REQ 0x0be4
#define regVM_INVALIDATE_ENG1_REQ_BASE_IDX 0
#define regVM_INVALIDATE_ENG2_REQ 0x0be5
#define regVM_INVALIDATE_ENG2_REQ_BASE_IDX 0
#define regVM_INVALIDATE_ENG3_REQ 0x0be6
#define regVM_INVALIDATE_ENG3_REQ_BASE_IDX 0
#define regVM_INVALIDATE_ENG4_REQ 0x0be7
#define regVM_INVALIDATE_ENG4_REQ_BASE_IDX 0
#define regVM_INVALIDATE_ENG5_REQ 0x0be8
#define regVM_INVALIDATE_ENG5_REQ_BASE_IDX 0
#define regVM_INVALIDATE_ENG6_REQ 0x0be9
#define regVM_INVALIDATE_ENG6_REQ_BASE_IDX 0
#define regVM_INVALIDATE_ENG7_REQ 0x0bea
#define regVM_INVALIDATE_ENG7_REQ_BASE_IDX 0
#define regVM_INVALIDATE_ENG8_REQ 0x0beb
#define regVM_INVALIDATE_ENG8_REQ_BASE_IDX 0
#define regVM_INVALIDATE_ENG9_REQ 0x0bec
#define regVM_INVALIDATE_ENG9_REQ_BASE_IDX 0
#define regVM_INVALIDATE_ENG10_REQ 0x0bed
#define regVM_INVALIDATE_ENG10_REQ_BASE_IDX 0
#define regVM_INVALIDATE_ENG11_REQ 0x0bee
#define regVM_INVALIDATE_ENG11_REQ_BASE_IDX 0
#define regVM_INVALIDATE_ENG12_REQ 0x0bef
#define regVM_INVALIDATE_ENG12_REQ_BASE_IDX 0
#define regVM_INVALIDATE_ENG13_REQ 0x0bf0
#define regVM_INVALIDATE_ENG13_REQ_BASE_IDX 0
#define regVM_INVALIDATE_ENG14_REQ 0x0bf1
#define regVM_INVALIDATE_ENG14_REQ_BASE_IDX 0
#define regVM_INVALIDATE_ENG15_REQ 0x0bf2
#define regVM_INVALIDATE_ENG15_REQ_BASE_IDX 0
#define regVM_INVALIDATE_ENG16_REQ 0x0bf3
#define regVM_INVALIDATE_ENG16_REQ_BASE_IDX 0
#define regVM_INVALIDATE_ENG17_REQ 0x0bf4
#define regVM_INVALIDATE_ENG17_REQ_BASE_IDX 0
#define regVM_INVALIDATE_ENG0_ACK 0x0bf5
#define regVM_INVALIDATE_ENG0_ACK_BASE_IDX 0
#define regVM_INVALIDATE_ENG1_ACK 0x0bf6
#define regVM_INVALIDATE_ENG1_ACK_BASE_IDX 0
#define regVM_INVALIDATE_ENG2_ACK 0x0bf7
#define regVM_INVALIDATE_ENG2_ACK_BASE_IDX 0
#define regVM_INVALIDATE_ENG3_ACK 0x0bf8
#define regVM_INVALIDATE_ENG3_ACK_BASE_IDX 0
#define regVM_INVALIDATE_ENG4_ACK 0x0bf9
#define regVM_INVALIDATE_ENG4_ACK_BASE_IDX 0
#define regVM_INVALIDATE_ENG5_ACK 0x0bfa
#define regVM_INVALIDATE_ENG5_ACK_BASE_IDX 0
#define regVM_INVALIDATE_ENG6_ACK 0x0bfb
#define regVM_INVALIDATE_ENG6_ACK_BASE_IDX 0
#define regVM_INVALIDATE_ENG7_ACK 0x0bfc
#define regVM_INVALIDATE_ENG7_ACK_BASE_IDX 0
#define regVM_INVALIDATE_ENG8_ACK 0x0bfd
#define regVM_INVALIDATE_ENG8_ACK_BASE_IDX 0
#define regVM_INVALIDATE_ENG9_ACK 0x0bfe
#define regVM_INVALIDATE_ENG9_ACK_BASE_IDX 0
#define regVM_INVALIDATE_ENG10_ACK 0x0bff
#define regVM_INVALIDATE_ENG10_ACK_BASE_IDX 0
#define regVM_INVALIDATE_ENG11_ACK 0x0c00
#define regVM_INVALIDATE_ENG11_ACK_BASE_IDX 0
#define regVM_INVALIDATE_ENG12_ACK 0x0c01
#define regVM_INVALIDATE_ENG12_ACK_BASE_IDX 0
#define regVM_INVALIDATE_ENG13_ACK 0x0c02
#define regVM_INVALIDATE_ENG13_ACK_BASE_IDX 0
#define regVM_INVALIDATE_ENG14_ACK 0x0c03
#define regVM_INVALIDATE_ENG14_ACK_BASE_IDX 0
#define regVM_INVALIDATE_ENG15_ACK 0x0c04
#define regVM_INVALIDATE_ENG15_ACK_BASE_IDX 0
#define regVM_INVALIDATE_ENG16_ACK 0x0c05
#define regVM_INVALIDATE_ENG16_ACK_BASE_IDX 0
#define regVM_INVALIDATE_ENG17_ACK 0x0c06
#define regVM_INVALIDATE_ENG17_ACK_BASE_IDX 0
#define regVM_INVALIDATE_ENG0_ADDR_RANGE_LO32 0x0c07
#define regVM_INVALIDATE_ENG0_ADDR_RANGE_LO32_BASE_IDX 0
#define regVM_INVALIDATE_ENG0_ADDR_RANGE_HI32 0x0c08
#define regVM_INVALIDATE_ENG0_ADDR_RANGE_HI32_BASE_IDX 0
#define regVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 0x0c09
#define regVM_INVALIDATE_ENG1_ADDR_RANGE_LO32_BASE_IDX 0
#define regVM_INVALIDATE_ENG1_ADDR_RANGE_HI32 0x0c0a
#define regVM_INVALIDATE_ENG1_ADDR_RANGE_HI32_BASE_IDX 0
#define regVM_INVALIDATE_ENG2_ADDR_RANGE_LO32 0x0c0b
#define regVM_INVALIDATE_ENG2_ADDR_RANGE_LO32_BASE_IDX 0
#define regVM_INVALIDATE_ENG2_ADDR_RANGE_HI32 0x0c0c
#define regVM_INVALIDATE_ENG2_ADDR_RANGE_HI32_BASE_IDX 0
#define regVM_INVALIDATE_ENG3_ADDR_RANGE_LO32 0x0c0d
#define regVM_INVALIDATE_ENG3_ADDR_RANGE_LO32_BASE_IDX 0
#define regVM_INVALIDATE_ENG3_ADDR_RANGE_HI32 0x0c0e
#define regVM_INVALIDATE_ENG3_ADDR_RANGE_HI32_BASE_IDX 0
#define regVM_INVALIDATE_ENG4_ADDR_RANGE_LO32 0x0c0f
#define regVM_INVALIDATE_ENG4_ADDR_RANGE_LO32_BASE_IDX 0
#define regVM_INVALIDATE_ENG4_ADDR_RANGE_HI32 0x0c10
#define regVM_INVALIDATE_ENG4_ADDR_RANGE_HI32_BASE_IDX 0
#define regVM_INVALIDATE_ENG5_ADDR_RANGE_LO32 0x0c11
#define regVM_INVALIDATE_ENG5_ADDR_RANGE_LO32_BASE_IDX 0
#define regVM_INVALIDATE_ENG5_ADDR_RANGE_HI32 0x0c12
#define regVM_INVALIDATE_ENG5_ADDR_RANGE_HI32_BASE_IDX 0
#define regVM_INVALIDATE_ENG6_ADDR_RANGE_LO32 0x0c13
#define regVM_INVALIDATE_ENG6_ADDR_RANGE_LO32_BASE_IDX 0
#define regVM_INVALIDATE_ENG6_ADDR_RANGE_HI32 0x0c14
#define regVM_INVALIDATE_ENG6_ADDR_RANGE_HI32_BASE_IDX 0
#define regVM_INVALIDATE_ENG7_ADDR_RANGE_LO32 0x0c15
#define regVM_INVALIDATE_ENG7_ADDR_RANGE_LO32_BASE_IDX 0
#define regVM_INVALIDATE_ENG7_ADDR_RANGE_HI32 0x0c16
#define regVM_INVALIDATE_ENG7_ADDR_RANGE_HI32_BASE_IDX 0
#define regVM_INVALIDATE_ENG8_ADDR_RANGE_LO32 0x0c17
#define regVM_INVALIDATE_ENG8_ADDR_RANGE_LO32_BASE_IDX 0
#define regVM_INVALIDATE_ENG8_ADDR_RANGE_HI32 0x0c18
#define regVM_INVALIDATE_ENG8_ADDR_RANGE_HI32_BASE_IDX 0
#define regVM_INVALIDATE_ENG9_ADDR_RANGE_LO32 0x0c19
#define regVM_INVALIDATE_ENG9_ADDR_RANGE_LO32_BASE_IDX 0
#define regVM_INVALIDATE_ENG9_ADDR_RANGE_HI32 0x0c1a
#define regVM_INVALIDATE_ENG9_ADDR_RANGE_HI32_BASE_IDX 0
#define regVM_INVALIDATE_ENG10_ADDR_RANGE_LO32 0x0c1b
#define regVM_INVALIDATE_ENG10_ADDR_RANGE_LO32_BASE_IDX 0
#define regVM_INVALIDATE_ENG10_ADDR_RANGE_HI32 0x0c1c
#define regVM_INVALIDATE_ENG10_ADDR_RANGE_HI32_BASE_IDX 0
#define regVM_INVALIDATE_ENG11_ADDR_RANGE_LO32 0x0c1d
#define regVM_INVALIDATE_ENG11_ADDR_RANGE_LO32_BASE_IDX 0
#define regVM_INVALIDATE_ENG11_ADDR_RANGE_HI32 0x0c1e
#define regVM_INVALIDATE_ENG11_ADDR_RANGE_HI32_BASE_IDX 0
#define regVM_INVALIDATE_ENG12_ADDR_RANGE_LO32 0x0c1f
#define regVM_INVALIDATE_ENG12_ADDR_RANGE_LO32_BASE_IDX 0
#define regVM_INVALIDATE_ENG12_ADDR_RANGE_HI32 0x0c20
#define regVM_INVALIDATE_ENG12_ADDR_RANGE_HI32_BASE_IDX 0
#define regVM_INVALIDATE_ENG13_ADDR_RANGE_LO32 0x0c21
#define regVM_INVALIDATE_ENG13_ADDR_RANGE_LO32_BASE_IDX 0
#define regVM_INVALIDATE_ENG13_ADDR_RANGE_HI32 0x0c22
#define regVM_INVALIDATE_ENG13_ADDR_RANGE_HI32_BASE_IDX 0
#define regVM_INVALIDATE_ENG14_ADDR_RANGE_LO32 0x0c23
#define regVM_INVALIDATE_ENG14_ADDR_RANGE_LO32_BASE_IDX 0
#define regVM_INVALIDATE_ENG14_ADDR_RANGE_HI32 0x0c24
#define regVM_INVALIDATE_ENG14_ADDR_RANGE_HI32_BASE_IDX 0
#define regVM_INVALIDATE_ENG15_ADDR_RANGE_LO32 0x0c25
#define regVM_INVALIDATE_ENG15_ADDR_RANGE_LO32_BASE_IDX 0
#define regVM_INVALIDATE_ENG15_ADDR_RANGE_HI32 0x0c26
#define regVM_INVALIDATE_ENG15_ADDR_RANGE_HI32_BASE_IDX 0
#define regVM_INVALIDATE_ENG16_ADDR_RANGE_LO32 0x0c27
#define regVM_INVALIDATE_ENG16_ADDR_RANGE_LO32_BASE_IDX 0
#define regVM_INVALIDATE_ENG16_ADDR_RANGE_HI32 0x0c28
#define regVM_INVALIDATE_ENG16_ADDR_RANGE_HI32_BASE_IDX 0
#define regVM_INVALIDATE_ENG17_ADDR_RANGE_LO32 0x0c29
#define regVM_INVALIDATE_ENG17_ADDR_RANGE_LO32_BASE_IDX 0
#define regVM_INVALIDATE_ENG17_ADDR_RANGE_HI32 0x0c2a
#define regVM_INVALIDATE_ENG17_ADDR_RANGE_HI32_BASE_IDX 0
#define regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 0x0c2b
#define regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
#define regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 0x0c2c
#define regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
#define regVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 0x0c2d
#define regVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
#define regVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 0x0c2e
#define regVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
#define regVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 0x0c2f
#define regVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
#define regVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 0x0c30
#define regVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
#define regVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 0x0c31
#define regVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
#define regVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 0x0c32
#define regVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
#define regVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 0x0c33
#define regVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
#define regVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 0x0c34
#define regVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
#define regVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 0x0c35
#define regVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
#define regVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 0x0c36
#define regVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
#define regVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 0x0c37
#define regVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
#define regVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 0x0c38
#define regVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
#define regVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 0x0c39
#define regVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
#define regVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 0x0c3a
#define regVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
#define regVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 0x0c3b
#define regVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
#define regVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 0x0c3c
#define regVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
#define regVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 0x0c3d
#define regVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
#define regVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 0x0c3e
#define regVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
#define regVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 0x0c3f
#define regVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
#define regVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 0x0c40
#define regVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
#define regVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 0x0c41
#define regVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
#define regVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 0x0c42
#define regVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
#define regVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 0x0c43
#define regVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
#define regVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 0x0c44
#define regVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
#define regVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 0x0c45
#define regVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
#define regVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 0x0c46
#define regVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
#define regVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 0x0c47
#define regVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
#define regVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 0x0c48
#define regVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
#define regVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 0x0c49
#define regVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
#define regVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 0x0c4a
#define regVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
#define regVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 0x0c4b
#define regVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
#define regVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 0x0c4c
#define regVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
#define regVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 0x0c4d
#define regVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
#define regVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 0x0c4e
#define regVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
#define regVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 0x0c4f
#define regVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
#define regVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 0x0c50
#define regVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
#define regVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 0x0c51
#define regVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
#define regVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 0x0c52
#define regVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
#define regVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 0x0c53
#define regVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
#define regVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 0x0c54
#define regVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
#define regVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 0x0c55
#define regVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
#define regVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 0x0c56
#define regVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
#define regVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 0x0c57
#define regVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
#define regVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 0x0c58
#define regVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
#define regVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 0x0c59
#define regVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
#define regVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 0x0c5a
#define regVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
#define regVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 0x0c5b
#define regVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
#define regVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 0x0c5c
#define regVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
#define regVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 0x0c5d
#define regVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
#define regVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 0x0c5e
#define regVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
#define regVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 0x0c5f
#define regVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
#define regVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 0x0c60
#define regVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
#define regVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 0x0c61
#define regVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
#define regVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 0x0c62
#define regVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
#define regVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 0x0c63
#define regVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
#define regVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 0x0c64
#define regVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
#define regVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 0x0c65
#define regVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
#define regVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 0x0c66
#define regVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
#define regVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 0x0c67
#define regVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
#define regVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 0x0c68
#define regVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
#define regVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 0x0c69
#define regVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
#define regVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 0x0c6a
#define regVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
#define regVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 0x0c6b
#define regVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
#define regVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 0x0c6c
#define regVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
#define regVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 0x0c6d
#define regVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
#define regVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 0x0c6e
#define regVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
#define regVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 0x0c6f
#define regVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
#define regVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 0x0c70
#define regVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
#define regVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 0x0c71
#define regVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
#define regVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 0x0c72
#define regVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
#define regVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 0x0c73
#define regVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
#define regVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 0x0c74
#define regVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
#define regVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 0x0c75
#define regVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
#define regVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 0x0c76
#define regVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
#define regVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 0x0c77
#define regVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
#define regVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 0x0c78
#define regVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
#define regVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 0x0c79
#define regVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
#define regVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 0x0c7a
#define regVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
#define regVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 0x0c7b
#define regVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
#define regVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 0x0c7c
#define regVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
#define regVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 0x0c7d
#define regVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
#define regVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 0x0c7e
#define regVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
#define regVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 0x0c7f
#define regVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
#define regVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 0x0c80
#define regVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
#define regVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 0x0c81
#define regVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
#define regVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 0x0c82
#define regVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
#define regVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 0x0c83
#define regVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
#define regVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 0x0c84
#define regVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
#define regVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 0x0c85
#define regVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
#define regVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 0x0c86
#define regVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
#define regVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 0x0c87
#define regVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
#define regVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 0x0c88
#define regVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
#define regVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 0x0c89
#define regVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
#define regVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 0x0c8a
#define regVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
// addressBlock: mmhub_utcl2_vmsharedhvdec
// base address: 0x6b380
#define regMC_VM_FB_SIZE_OFFSET_VF0 0x0ce0
#define regMC_VM_FB_SIZE_OFFSET_VF0_BASE_IDX 0
#define regMC_VM_FB_SIZE_OFFSET_VF1 0x0ce1
#define regMC_VM_FB_SIZE_OFFSET_VF1_BASE_IDX 0
#define regMC_VM_FB_SIZE_OFFSET_VF2 0x0ce2
#define regMC_VM_FB_SIZE_OFFSET_VF2_BASE_IDX 0
#define regMC_VM_FB_SIZE_OFFSET_VF3 0x0ce3
#define regMC_VM_FB_SIZE_OFFSET_VF3_BASE_IDX 0
#define regMC_VM_FB_SIZE_OFFSET_VF4 0x0ce4
#define regMC_VM_FB_SIZE_OFFSET_VF4_BASE_IDX 0
#define regMC_VM_FB_SIZE_OFFSET_VF5 0x0ce5
#define regMC_VM_FB_SIZE_OFFSET_VF5_BASE_IDX 0
#define regMC_VM_FB_SIZE_OFFSET_VF6 0x0ce6
#define regMC_VM_FB_SIZE_OFFSET_VF6_BASE_IDX 0
#define regMC_VM_FB_SIZE_OFFSET_VF7 0x0ce7
#define regMC_VM_FB_SIZE_OFFSET_VF7_BASE_IDX 0
#define regMC_VM_FB_SIZE_OFFSET_VF8 0x0ce8
#define regMC_VM_FB_SIZE_OFFSET_VF8_BASE_IDX 0
#define regMC_VM_FB_SIZE_OFFSET_VF9 0x0ce9
#define regMC_VM_FB_SIZE_OFFSET_VF9_BASE_IDX 0
#define regMC_VM_FB_SIZE_OFFSET_VF10 0x0cea
#define regMC_VM_FB_SIZE_OFFSET_VF10_BASE_IDX 0
#define regMC_VM_FB_SIZE_OFFSET_VF11 0x0ceb
#define regMC_VM_FB_SIZE_OFFSET_VF11_BASE_IDX 0
#define regMC_VM_FB_SIZE_OFFSET_VF12 0x0cec
#define regMC_VM_FB_SIZE_OFFSET_VF12_BASE_IDX 0
#define regMC_VM_FB_SIZE_OFFSET_VF13 0x0ced
#define regMC_VM_FB_SIZE_OFFSET_VF13_BASE_IDX 0
#define regMC_VM_FB_SIZE_OFFSET_VF14 0x0cee
#define regMC_VM_FB_SIZE_OFFSET_VF14_BASE_IDX 0
#define regMC_VM_FB_SIZE_OFFSET_VF15 0x0cef
#define regMC_VM_FB_SIZE_OFFSET_VF15_BASE_IDX 0
#define regMC_VM_MARC_BASE_LO_0 0x0cf1
#define regMC_VM_MARC_BASE_LO_0_BASE_IDX 0
#define regMC_VM_MARC_BASE_LO_1 0x0cf2
#define regMC_VM_MARC_BASE_LO_1_BASE_IDX 0
#define regMC_VM_MARC_BASE_LO_2 0x0cf3
#define regMC_VM_MARC_BASE_LO_2_BASE_IDX 0
#define regMC_VM_MARC_BASE_LO_3 0x0cf4
#define regMC_VM_MARC_BASE_LO_3_BASE_IDX 0
#define regMC_VM_MARC_BASE_HI_0 0x0cf5
#define regMC_VM_MARC_BASE_HI_0_BASE_IDX 0
#define regMC_VM_MARC_BASE_HI_1 0x0cf6
#define regMC_VM_MARC_BASE_HI_1_BASE_IDX 0
#define regMC_VM_MARC_BASE_HI_2 0x0cf7
#define regMC_VM_MARC_BASE_HI_2_BASE_IDX 0
#define regMC_VM_MARC_BASE_HI_3 0x0cf8
#define regMC_VM_MARC_BASE_HI_3_BASE_IDX 0
#define regMC_VM_MARC_RELOC_LO_0 0x0cf9
#define regMC_VM_MARC_RELOC_LO_0_BASE_IDX 0
#define regMC_VM_MARC_RELOC_LO_1 0x0cfa
#define regMC_VM_MARC_RELOC_LO_1_BASE_IDX 0
#define regMC_VM_MARC_RELOC_LO_2 0x0cfb
#define regMC_VM_MARC_RELOC_LO_2_BASE_IDX 0
#define regMC_VM_MARC_RELOC_LO_3 0x0cfc
#define regMC_VM_MARC_RELOC_LO_3_BASE_IDX 0
#define regMC_VM_MARC_RELOC_HI_0 0x0cfd
#define regMC_VM_MARC_RELOC_HI_0_BASE_IDX 0
#define regMC_VM_MARC_RELOC_HI_1 0x0cfe
#define regMC_VM_MARC_RELOC_HI_1_BASE_IDX 0
#define regMC_VM_MARC_RELOC_HI_2 0x0cff
#define regMC_VM_MARC_RELOC_HI_2_BASE_IDX 0
#define regMC_VM_MARC_RELOC_HI_3 0x0d00
#define regMC_VM_MARC_RELOC_HI_3_BASE_IDX 0
#define regMC_VM_MARC_LEN_LO_0 0x0d01
#define regMC_VM_MARC_LEN_LO_0_BASE_IDX 0
#define regMC_VM_MARC_LEN_LO_1 0x0d02
#define regMC_VM_MARC_LEN_LO_1_BASE_IDX 0
#define regMC_VM_MARC_LEN_LO_2 0x0d03
#define regMC_VM_MARC_LEN_LO_2_BASE_IDX 0
#define regMC_VM_MARC_LEN_LO_3 0x0d04
#define regMC_VM_MARC_LEN_LO_3_BASE_IDX 0
#define regMC_VM_MARC_LEN_HI_0 0x0d05
#define regMC_VM_MARC_LEN_HI_0_BASE_IDX 0
#define regMC_VM_MARC_LEN_HI_1 0x0d06
#define regMC_VM_MARC_LEN_HI_1_BASE_IDX 0
#define regMC_VM_MARC_LEN_HI_2 0x0d07
#define regMC_VM_MARC_LEN_HI_2_BASE_IDX 0
#define regMC_VM_MARC_LEN_HI_3 0x0d08
#define regMC_VM_MARC_LEN_HI_3_BASE_IDX 0
#define regVM_PCIE_ATS_CNTL 0x0d0b
#define regVM_PCIE_ATS_CNTL_BASE_IDX 0
#define regVM_PCIE_ATS_CNTL_VF_0 0x0d0c
#define regVM_PCIE_ATS_CNTL_VF_0_BASE_IDX 0
#define regVM_PCIE_ATS_CNTL_VF_1 0x0d0d
#define regVM_PCIE_ATS_CNTL_VF_1_BASE_IDX 0
#define regVM_PCIE_ATS_CNTL_VF_2 0x0d0e
#define regVM_PCIE_ATS_CNTL_VF_2_BASE_IDX 0
#define regVM_PCIE_ATS_CNTL_VF_3 0x0d0f
#define regVM_PCIE_ATS_CNTL_VF_3_BASE_IDX 0
#define regVM_PCIE_ATS_CNTL_VF_4 0x0d10
#define regVM_PCIE_ATS_CNTL_VF_4_BASE_IDX 0
#define regVM_PCIE_ATS_CNTL_VF_5 0x0d11
#define regVM_PCIE_ATS_CNTL_VF_5_BASE_IDX 0
#define regVM_PCIE_ATS_CNTL_VF_6 0x0d12
#define regVM_PCIE_ATS_CNTL_VF_6_BASE_IDX 0
#define regVM_PCIE_ATS_CNTL_VF_7 0x0d13
#define regVM_PCIE_ATS_CNTL_VF_7_BASE_IDX 0
#define regVM_PCIE_ATS_CNTL_VF_8 0x0d14
#define regVM_PCIE_ATS_CNTL_VF_8_BASE_IDX 0
#define regVM_PCIE_ATS_CNTL_VF_9 0x0d15
#define regVM_PCIE_ATS_CNTL_VF_9_BASE_IDX 0
#define regVM_PCIE_ATS_CNTL_VF_10 0x0d16
#define regVM_PCIE_ATS_CNTL_VF_10_BASE_IDX 0
#define regVM_PCIE_ATS_CNTL_VF_11 0x0d17
#define regVM_PCIE_ATS_CNTL_VF_11_BASE_IDX 0
#define regVM_PCIE_ATS_CNTL_VF_12 0x0d18
#define regVM_PCIE_ATS_CNTL_VF_12_BASE_IDX 0
#define regVM_PCIE_ATS_CNTL_VF_13 0x0d19
#define regVM_PCIE_ATS_CNTL_VF_13_BASE_IDX 0
#define regVM_PCIE_ATS_CNTL_VF_14 0x0d1a
#define regVM_PCIE_ATS_CNTL_VF_14_BASE_IDX 0
#define regVM_PCIE_ATS_CNTL_VF_15 0x0d1b
#define regVM_PCIE_ATS_CNTL_VF_15_BASE_IDX 0
#define regMC_SHARED_ACTIVE_FCN_ID 0x0d1c
#define regMC_SHARED_ACTIVE_FCN_ID_BASE_IDX 0
#define regMC_VM_XGMI_GPUIOV_ENABLE 0x0d1d
#define regMC_VM_XGMI_GPUIOV_ENABLE_BASE_IDX 0
// addressBlock: mmhub_utcl2_vmsharedpfdec
// base address: 0x6b290
#define regMC_VM_FB_OFFSET 0x0cab
#define regMC_VM_FB_OFFSET_BASE_IDX 0
#define regMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB 0x0cac
#define regMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_BASE_IDX 0
#define regMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB 0x0cad
#define regMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_BASE_IDX 0
#define regMC_VM_STEERING 0x0cae
#define regMC_VM_STEERING_BASE_IDX 0
#define regMC_SHARED_VIRT_RESET_REQ 0x0caf
#define regMC_SHARED_VIRT_RESET_REQ_BASE_IDX 0
#define regMC_MEM_POWER_LS 0x0cb0
#define regMC_MEM_POWER_LS_BASE_IDX 0
#define regMC_VM_CACHEABLE_DRAM_ADDRESS_START 0x0cb1
#define regMC_VM_CACHEABLE_DRAM_ADDRESS_START_BASE_IDX 0
#define regMC_VM_CACHEABLE_DRAM_ADDRESS_END 0x0cb2
#define regMC_VM_CACHEABLE_DRAM_ADDRESS_END_BASE_IDX 0
#define regMC_VM_APT_CNTL 0x0cb3
#define regMC_VM_APT_CNTL_BASE_IDX 0
#define regMC_VM_LOCAL_HBM_ADDRESS_START 0x0cb4
#define regMC_VM_LOCAL_HBM_ADDRESS_START_BASE_IDX 0
#define regMC_VM_LOCAL_HBM_ADDRESS_END 0x0cb5
#define regMC_VM_LOCAL_HBM_ADDRESS_END_BASE_IDX 0
#define regMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL 0x0cb6
#define regMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL_BASE_IDX 0
#define regUTCL2_CGTT_CLK_CTRL 0x0cb7
#define regUTCL2_CGTT_CLK_CTRL_BASE_IDX 0
#define regMC_VM_XGMI_LFB_CNTL 0x0cb8
#define regMC_VM_XGMI_LFB_CNTL_BASE_IDX 0
#define regMC_VM_XGMI_LFB_SIZE 0x0cb9
#define regMC_VM_XGMI_LFB_SIZE_BASE_IDX 0
#define regMC_VM_CACHEABLE_DRAM_CNTL 0x0cba
#define regMC_VM_CACHEABLE_DRAM_CNTL_BASE_IDX 0
#define regMC_VM_HOST_MAPPING 0x0cbb
#define regMC_VM_HOST_MAPPING_BASE_IDX 0
// addressBlock: mmhub_utcl2_vmsharedvcdec
// base address: 0x6b300
#define regMC_VM_FB_LOCATION_BASE 0x0cc0
#define regMC_VM_FB_LOCATION_BASE_BASE_IDX 0
#define regMC_VM_FB_LOCATION_TOP 0x0cc1
#define regMC_VM_FB_LOCATION_TOP_BASE_IDX 0
#define regMC_VM_AGP_TOP 0x0cc2
#define regMC_VM_AGP_TOP_BASE_IDX 0
#define regMC_VM_AGP_BOT 0x0cc3
#define regMC_VM_AGP_BOT_BASE_IDX 0
#define regMC_VM_AGP_BASE 0x0cc4
#define regMC_VM_AGP_BASE_BASE_IDX 0
#define regMC_VM_SYSTEM_APERTURE_LOW_ADDR 0x0cc5
#define regMC_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 0
#define regMC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x0cc6
#define regMC_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 0
#define regMC_VM_MX_L1_TLB_CNTL 0x0cc7
#define regMC_VM_MX_L1_TLB_CNTL_BASE_IDX 0
#endif
Codebase Browser
linux