linux/tools/perf/pmu-events/arch/test/test_soc/cpu/other.json

[
    {
        "EventCode": "0x6",
        "Counter": "0,1",
        "UMask": "0x80",
        "EventName": "SEGMENT_REG_LOADS.ANY",
        "SampleAfterValue": "200000",
        "BriefDescription": "Number of segment register loads."
    },
    {
        "EventCode": "0x9",
        "Counter": "0,1",
        "UMask": "0x20",
        "EventName": "DISPATCH_BLOCKED.ANY",
        "SampleAfterValue": "200000",
        "BriefDescription": "Memory cluster signals to block micro-op dispatch for any reason"
    },
    {
        "EventCode": "0x3A",
        "Counter": "0,1",
        "UMask": "0x0",
        "EventName": "EIST_TRANS",
        "SampleAfterValue": "200000",
        "BriefDescription": "Number of Enhanced Intel SpeedStep(R) Technology (EIST) transitions"
    }
]