[
{
"BriefDescription": "Counts the number of read requests and streaming stores that hit in MCDRAM cache and the data in MCDRAM is clean with respect to DDR. This event is only valid in cache and hybrid memory mode.",
"Counter": "0,1,2,3",
"EventCode": "0x02",
"EventName": "UNC_E_EDC_ACCESS.HIT_CLEAN",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "EDC_UCLK"
},
{
"BriefDescription": "Counts the number of read requests and streaming stores that hit in MCDRAM cache and the data in MCDRAM is dirty with respect to DDR. This event is only valid in cache and hybrid memory mode.",
"Counter": "0,1,2,3",
"EventCode": "0x02",
"EventName": "UNC_E_EDC_ACCESS.HIT_DIRTY",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "EDC_UCLK"
},
{
"BriefDescription": "Counts the number of read requests and streaming stores that miss in MCDRAM cache and the data evicted from the MCDRAM is clean with respect to DDR. This event is only valid in cache and hybrid memory mode.",
"Counter": "0,1,2,3",
"EventCode": "0x02",
"EventName": "UNC_E_EDC_ACCESS.MISS_CLEAN",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "EDC_UCLK"
},
{
"BriefDescription": "Counts the number of read requests and streaming stores that miss in MCDRAM cache and the data evicted from the MCDRAM is dirty with respect to DDR. This event is only valid in cache and hybrid memory mode.",
"Counter": "0,1,2,3",
"EventCode": "0x02",
"EventName": "UNC_E_EDC_ACCESS.MISS_DIRTY",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "EDC_UCLK"
},
{
"BriefDescription": "Number of EDC Hits or Misses. Miss I",
"Counter": "0,1,2,3",
"EventCode": "0x02",
"EventName": "UNC_E_EDC_ACCESS.MISS_INVALID",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "EDC_UCLK"
},
{
"BriefDescription": "ECLK count",
"Counter": "0,1,2,3",
"EventName": "UNC_E_E_CLOCKTICKS",
"PerPkg": "1",
"Unit": "EDC_ECLK"
},
{
"BriefDescription": "Counts the number of read requests received by the MCDRAM controller. This event is valid in all three memory modes: flat, cache and hybrid. In cache and hybrid memory mode, this event counts all read requests as well as streaming stores that hit or miss in the MCDRAM cache.",
"Counter": "0,1,2,3",
"EventCode": "0x01",
"EventName": "UNC_E_RPQ_INSERTS",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "EDC_ECLK"
},
{
"BriefDescription": "UCLK count",
"Counter": "0,1,2,3",
"EventName": "UNC_E_U_CLOCKTICKS",
"PerPkg": "1",
"Unit": "EDC_UCLK"
},
{
"BriefDescription": "Counts the number of write requests received by the MCDRAM controller. This event is valid in all three memory modes: flat, cache and hybrid. In cache and hybrid memory mode, this event counts all streaming stores, writebacks and, read requests that miss in MCDRAM cache.",
"Counter": "0,1,2,3",
"EventCode": "0x02",
"EventName": "UNC_E_WPQ_INSERTS",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "EDC_ECLK"
},
{
"BriefDescription": "CAS All",
"Counter": "0,1,2,3",
"EventCode": "0x03",
"EventName": "UNC_M_CAS_COUNT.ALL",
"PerPkg": "1",
"UMask": "0x3",
"Unit": "iMC_DCLK"
},
{
"BriefDescription": "CAS Reads",
"Counter": "0,1,2,3",
"EventCode": "0x03",
"EventName": "UNC_M_CAS_COUNT.RD",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "iMC_DCLK"
},
{
"BriefDescription": "CAS Writes",
"Counter": "0,1,2,3",
"EventCode": "0x03",
"EventName": "UNC_M_CAS_COUNT.WR",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "iMC_DCLK"
},
{
"BriefDescription": "DCLK count",
"Counter": "0,1,2,3",
"EventName": "UNC_M_D_CLOCKTICKS",
"PerPkg": "1",
"Unit": "iMC_DCLK"
},
{
"BriefDescription": "UCLK count",
"Counter": "0,1,2,3",
"EventName": "UNC_M_U_CLOCKTICKS",
"PerPkg": "1",
"Unit": "iMC_UCLK"
}
]
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