[
{
"BriefDescription": "Total Write Cache Occupancy : Any Source",
"Counter": "0,1",
"EventCode": "0x0F",
"EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.ANY",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Total Write Cache Occupancy : Any Source : Accumulates the number of reads and writes that are outstanding in the uncore in each cycle. This is effectively the sum of the READ_OCCUPANCY and WRITE_OCCUPANCY events. : Tracks all requests from any source port.",
"UMask": "0x1",
"Unit": "IRP"
},
{
"BriefDescription": "Total Write Cache Occupancy : Snoops",
"Counter": "0,1",
"EventCode": "0x0F",
"EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.IV_Q",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Total Write Cache Occupancy : Snoops : Accumulates the number of reads and writes that are outstanding in the uncore in each cycle. This is effectively the sum of the READ_OCCUPANCY and WRITE_OCCUPANCY events.",
"UMask": "0x2",
"Unit": "IRP"
},
{
"BriefDescription": "Total IRP occupancy of inbound read and write requests to coherent memory.",
"Counter": "0,1",
"EventCode": "0x0f",
"EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.MEM",
"PerPkg": "1",
"PublicDescription": "Total IRP occupancy of inbound read and write requests to coherent memory. This is effectively the sum of read occupancy and write occupancy.",
"UMask": "0x4",
"Unit": "IRP"
},
{
"BriefDescription": "Clockticks of the IO coherency tracker (IRP)",
"Counter": "0,1",
"EventCode": "0x01",
"EventName": "UNC_I_CLOCKTICKS",
"PerPkg": "1",
"Unit": "IRP"
},
{
"BriefDescription": "Coherent Ops : CLFlush",
"Counter": "0,1",
"EventCode": "0x10",
"EventName": "UNC_I_COHERENT_OPS.CLFLUSH",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Coherent Ops : CLFlush : Counts the number of coherency related operations serviced by the IRP",
"UMask": "0x80",
"Unit": "IRP"
},
{
"BriefDescription": "PCIITOM request issued by the IRP unit to the mesh with the intention of writing a full cacheline.",
"Counter": "0,1",
"EventCode": "0x10",
"EventName": "UNC_I_COHERENT_OPS.PCITOM",
"PerPkg": "1",
"PublicDescription": "PCIITOM request issued by the IRP unit to the mesh with the intention of writing a full cacheline to coherent memory, without a RFO. PCIITOM is a speculative Invalidate to Modified command that requests ownership of the cacheline and does not move data from the mesh to IRP cache.",
"UMask": "0x10",
"Unit": "IRP"
},
{
"BriefDescription": "RFO request issued by the IRP unit to the mesh with the intention of writing a partial cacheline.",
"Counter": "0,1",
"EventCode": "0x10",
"EventName": "UNC_I_COHERENT_OPS.RFO",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "RFO request issued by the IRP unit to the mesh with the intention of writing a partial cacheline to coherent memory. RFO is a Read For Ownership command that requests ownership of the cacheline and moves data from the mesh to IRP cache.",
"UMask": "0x8",
"Unit": "IRP"
},
{
"BriefDescription": "Coherent Ops : WbMtoI",
"Counter": "0,1",
"EventCode": "0x10",
"EventName": "UNC_I_COHERENT_OPS.WBMTOI",
"PerPkg": "1",
"PublicDescription": "Coherent Ops : WbMtoI : Counts the number of coherency related operations serviced by the IRP",
"UMask": "0x40",
"Unit": "IRP"
},
{
"BriefDescription": "FAF RF full",
"Counter": "0,1",
"EventCode": "0x17",
"EventName": "UNC_I_FAF_FULL",
"PerPkg": "1",
"Unit": "IRP"
},
{
"BriefDescription": "Inbound read requests received by the IRP and inserted into the FAF queue.",
"Counter": "0,1",
"EventCode": "0x18",
"EventName": "UNC_I_FAF_INSERTS",
"PerPkg": "1",
"PublicDescription": "Inbound read requests to coherent memory, received by the IRP and inserted into the Fire and Forget queue (FAF), a queue used for processing inbound reads in the IRP.",
"Unit": "IRP"
},
{
"BriefDescription": "Occupancy of the IRP FAF queue.",
"Counter": "0,1",
"EventCode": "0x19",
"EventName": "UNC_I_FAF_OCCUPANCY",
"PerPkg": "1",
"PublicDescription": "Occupancy of the IRP Fire and Forget (FAF) queue, a queue used for processing inbound reads in the IRP.",
"Unit": "IRP"
},
{
"BriefDescription": "FAF allocation -- sent to ADQ",
"Counter": "0,1",
"EventCode": "0x16",
"EventName": "UNC_I_FAF_TRANSACTIONS",
"PerPkg": "1",
"Unit": "IRP"
},
{
"BriefDescription": ": All Inserts Outbound (BL, AK, Snoops)",
"Counter": "0,1",
"EventCode": "0x20",
"EventName": "UNC_I_IRP_ALL.EVICTS",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "IRP"
},
{
"BriefDescription": ": All Inserts Inbound (p2p + faf + cset)",
"Counter": "0,1",
"EventCode": "0x20",
"EventName": "UNC_I_IRP_ALL.INBOUND_INSERTS",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "IRP"
},
{
"BriefDescription": ": All Inserts Outbound (BL, AK, Snoops)",
"Counter": "0,1",
"EventCode": "0x20",
"EventName": "UNC_I_IRP_ALL.OUTBOUND_INSERTS",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "IRP"
},
{
"BriefDescription": "Counts Timeouts - Set 0 : Cache Inserts of Atomic Transactions as Secondary",
"Counter": "0,1",
"EventCode": "0x1E",
"EventName": "UNC_I_MISC0.2ND_ATOMIC_INSERT",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "IRP"
},
{
"BriefDescription": "Counts Timeouts - Set 0 : Cache Inserts of Read Transactions as Secondary",
"Counter": "0,1",
"EventCode": "0x1e",
"EventName": "UNC_I_MISC0.2ND_RD_INSERT",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "IRP"
},
{
"BriefDescription": "Counts Timeouts - Set 0 : Cache Inserts of Write Transactions as Secondary",
"Counter": "0,1",
"EventCode": "0x1e",
"EventName": "UNC_I_MISC0.2ND_WR_INSERT",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "IRP"
},
{
"BriefDescription": "Counts Timeouts - Set 0 : Fastpath Rejects",
"Counter": "0,1",
"EventCode": "0x1E",
"EventName": "UNC_I_MISC0.FAST_REJ",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "IRP"
},
{
"BriefDescription": "Counts Timeouts - Set 0 : Fastpath Requests",
"Counter": "0,1",
"EventCode": "0x1e",
"EventName": "UNC_I_MISC0.FAST_REQ",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "IRP"
},
{
"BriefDescription": "Counts Timeouts - Set 0 : Fastpath Transfers From Primary to Secondary",
"Counter": "0,1",
"EventCode": "0x1E",
"EventName": "UNC_I_MISC0.FAST_XFER",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "IRP"
},
{
"BriefDescription": "Counts Timeouts - Set 0 : Prefetch Ack Hints From Primary to Secondary",
"Counter": "0,1",
"EventCode": "0x1E",
"EventName": "UNC_I_MISC0.PF_ACK_HINT",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x40",
"Unit": "IRP"
},
{
"BriefDescription": "Counts Timeouts - Set 0 : Slow path fwpf didn't find prefetch",
"Counter": "0,1",
"EventCode": "0x1E",
"EventName": "UNC_I_MISC0.SLOWPATH_FWPF_NO_PRF",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x80",
"Unit": "IRP"
},
{
"BriefDescription": "Misc Events - Set 1 : Lost Forward",
"Counter": "0,1",
"EventCode": "0x1F",
"EventName": "UNC_I_MISC1.LOST_FWD",
"PerPkg": "1",
"PublicDescription": "Misc Events - Set 1 : Lost Forward : Snoop pulled away ownership before a write was committed",
"UMask": "0x10",
"Unit": "IRP"
},
{
"BriefDescription": "Misc Events - Set 1 : Received Invalid",
"Counter": "0,1",
"EventCode": "0x1F",
"EventName": "UNC_I_MISC1.SEC_RCVD_INVLD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Misc Events - Set 1 : Received Invalid : Secondary received a transfer that did not have sufficient MESI state",
"UMask": "0x20",
"Unit": "IRP"
},
{
"BriefDescription": "Misc Events - Set 1 : Received Valid",
"Counter": "0,1",
"EventCode": "0x1F",
"EventName": "UNC_I_MISC1.SEC_RCVD_VLD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Misc Events - Set 1 : Received Valid : Secondary received a transfer that did have sufficient MESI state",
"UMask": "0x40",
"Unit": "IRP"
},
{
"BriefDescription": "Misc Events - Set 1 : Slow Transfer of E Line",
"Counter": "0,1",
"EventCode": "0x1f",
"EventName": "UNC_I_MISC1.SLOW_E",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Misc Events - Set 1 : Slow Transfer of E Line : Secondary received a transfer that did have sufficient MESI state",
"UMask": "0x4",
"Unit": "IRP"
},
{
"BriefDescription": "Misc Events - Set 1 : Slow Transfer of I Line",
"Counter": "0,1",
"EventCode": "0x1f",
"EventName": "UNC_I_MISC1.SLOW_I",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Misc Events - Set 1 : Slow Transfer of I Line : Snoop took cacheline ownership before write from data was committed.",
"UMask": "0x1",
"Unit": "IRP"
},
{
"BriefDescription": "Misc Events - Set 1 : Slow Transfer of M Line",
"Counter": "0,1",
"EventCode": "0x1f",
"EventName": "UNC_I_MISC1.SLOW_M",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Misc Events - Set 1 : Slow Transfer of M Line : Snoop took cacheline ownership before write from data was committed.",
"UMask": "0x8",
"Unit": "IRP"
},
{
"BriefDescription": "Misc Events - Set 1 : Slow Transfer of S Line",
"Counter": "0,1",
"EventCode": "0x1f",
"EventName": "UNC_I_MISC1.SLOW_S",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Misc Events - Set 1 : Slow Transfer of S Line : Secondary received a transfer that did not have sufficient MESI state",
"UMask": "0x2",
"Unit": "IRP"
},
{
"BriefDescription": "P2P Requests",
"Counter": "0,1",
"EventCode": "0x14",
"EventName": "UNC_I_P2P_INSERTS",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "P2P Requests : P2P requests from the ITC",
"Unit": "IRP"
},
{
"BriefDescription": "P2P Occupancy",
"Counter": "0,1",
"EventCode": "0x15",
"EventName": "UNC_I_P2P_OCCUPANCY",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "P2P Occupancy : P2P B & S Queue Occupancy",
"Unit": "IRP"
},
{
"BriefDescription": "P2P Transactions : P2P completions",
"Counter": "0,1",
"EventCode": "0x13",
"EventName": "UNC_I_P2P_TRANSACTIONS.CMPL",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "IRP"
},
{
"BriefDescription": "P2P Transactions : match if local only",
"Counter": "0,1",
"EventCode": "0x13",
"EventName": "UNC_I_P2P_TRANSACTIONS.LOC",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x40",
"Unit": "IRP"
},
{
"BriefDescription": "P2P Transactions : match if local and target matches",
"Counter": "0,1",
"EventCode": "0x13",
"EventName": "UNC_I_P2P_TRANSACTIONS.LOC_AND_TGT_MATCH",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x80",
"Unit": "IRP"
},
{
"BriefDescription": "P2P Transactions : P2P Message",
"Counter": "0,1",
"EventCode": "0x13",
"EventName": "UNC_I_P2P_TRANSACTIONS.MSG",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "IRP"
},
{
"BriefDescription": "P2P Transactions : P2P reads",
"Counter": "0,1",
"EventCode": "0x13",
"EventName": "UNC_I_P2P_TRANSACTIONS.RD",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "IRP"
},
{
"BriefDescription": "P2P Transactions : Match if remote only",
"Counter": "0,1",
"EventCode": "0x13",
"EventName": "UNC_I_P2P_TRANSACTIONS.REM",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "IRP"
},
{
"BriefDescription": "P2P Transactions : match if remote and target matches",
"Counter": "0,1",
"EventCode": "0x13",
"EventName": "UNC_I_P2P_TRANSACTIONS.REM_AND_TGT_MATCH",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "IRP"
},
{
"BriefDescription": "P2P Transactions : P2P Writes",
"Counter": "0,1",
"EventCode": "0x13",
"EventName": "UNC_I_P2P_TRANSACTIONS.WR",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "IRP"
},
{
"BriefDescription": "Responses to snoops of any type that hit M, E, S or I line in the IIO",
"Counter": "0,1",
"EventCode": "0x12",
"EventName": "UNC_I_SNOOP_RESP.ALL_HIT",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Responses to snoops of any type (code, data, invalidate) that hit M, E, S or I line in the IIO",
"UMask": "0x7e",
"Unit": "IRP"
},
{
"BriefDescription": "Responses to snoops of any type that hit E or S line in the IIO cache",
"Counter": "0,1",
"EventCode": "0x12",
"EventName": "UNC_I_SNOOP_RESP.ALL_HIT_ES",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Responses to snoops of any type (code, data, invalidate) that hit E or S line in the IIO cache",
"UMask": "0x74",
"Unit": "IRP"
},
{
"BriefDescription": "Responses to snoops of any type that hit I line in the IIO cache",
"Counter": "0,1",
"EventCode": "0x12",
"EventName": "UNC_I_SNOOP_RESP.ALL_HIT_I",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Responses to snoops of any type (code, data, invalidate) that hit I line in the IIO cache",
"UMask": "0x72",
"Unit": "IRP"
},
{
"BriefDescription": "Responses to snoops of any type that hit M line in the IIO cache",
"Counter": "0,1",
"EventCode": "0x12",
"EventName": "UNC_I_SNOOP_RESP.ALL_HIT_M",
"PerPkg": "1",
"PublicDescription": "Responses to snoops of any type (code, data, invalidate) that hit M line in the IIO cache",
"UMask": "0x78",
"Unit": "IRP"
},
{
"BriefDescription": "Responses to snoops of any type that miss the IIO cache",
"Counter": "0,1",
"EventCode": "0x12",
"EventName": "UNC_I_SNOOP_RESP.ALL_MISS",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Responses to snoops of any type (code, data, invalidate) that miss the IIO cache",
"UMask": "0x71",
"Unit": "IRP"
},
{
"BriefDescription": "Snoop Responses : Hit E or S",
"Counter": "0,1",
"EventCode": "0x12",
"EventName": "UNC_I_SNOOP_RESP.HIT_ES",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "IRP"
},
{
"BriefDescription": "Snoop Responses : Hit I",
"Counter": "0,1",
"EventCode": "0x12",
"EventName": "UNC_I_SNOOP_RESP.HIT_I",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "IRP"
},
{
"BriefDescription": "Snoop Responses : Hit M",
"Counter": "0,1",
"EventCode": "0x12",
"EventName": "UNC_I_SNOOP_RESP.HIT_M",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "IRP"
},
{
"BriefDescription": "Snoop Responses : Miss",
"Counter": "0,1",
"EventCode": "0x12",
"EventName": "UNC_I_SNOOP_RESP.MISS",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "IRP"
},
{
"BriefDescription": "Snoop Responses : SnpCode",
"Counter": "0,1",
"EventCode": "0x12",
"EventName": "UNC_I_SNOOP_RESP.SNPCODE",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "IRP"
},
{
"BriefDescription": "Snoop Responses : SnpData",
"Counter": "0,1",
"EventCode": "0x12",
"EventName": "UNC_I_SNOOP_RESP.SNPDATA",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "IRP"
},
{
"BriefDescription": "Snoop Responses : SnpInv",
"Counter": "0,1",
"EventCode": "0x12",
"EventName": "UNC_I_SNOOP_RESP.SNPINV",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x40",
"Unit": "IRP"
},
{
"BriefDescription": "Inbound Transaction Count : Atomic",
"Counter": "0,1",
"EventCode": "0x11",
"EventName": "UNC_I_TRANSACTIONS.ATOMIC",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Inbound Transaction Count : Atomic : Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID. : Tracks the number of atomic transactions",
"UMask": "0x10",
"Unit": "IRP"
},
{
"BriefDescription": "Inbound Transaction Count : Other",
"Counter": "0,1",
"EventCode": "0x11",
"EventName": "UNC_I_TRANSACTIONS.OTHER",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Inbound Transaction Count : Other : Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID. : Tracks the number of 'other' kinds of transactions.",
"UMask": "0x20",
"Unit": "IRP"
},
{
"BriefDescription": "Inbound Transaction Count : Writes",
"Counter": "0,1",
"EventCode": "0x11",
"EventName": "UNC_I_TRANSACTIONS.WRITES",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Inbound Transaction Count : Writes : Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID. : Tracks only write requests. Each write request should have a prefetch, so there is no need to explicitly track these requests. For writes that are tickled and have to retry, the counter will be incremented for each retry.",
"UMask": "0x2",
"Unit": "IRP"
},
{
"BriefDescription": "Inbound write (fast path) requests received by the IRP.",
"Counter": "0,1",
"EventCode": "0x11",
"EventName": "UNC_I_TRANSACTIONS.WR_PREF",
"PerPkg": "1",
"PublicDescription": "Inbound write (fast path) requests to coherent memory, received by the IRP resulting in write ownership requests issued by IRP to the mesh.",
"UMask": "0x8",
"Unit": "IRP"
},
{
"BriefDescription": "AK Egress Allocations",
"Counter": "0,1",
"EventCode": "0x0B",
"EventName": "UNC_I_TxC_AK_INSERTS",
"Experimental": "1",
"PerPkg": "1",
"Unit": "IRP"
},
{
"BriefDescription": "BL DRS Egress Cycles Full",
"Counter": "0,1",
"EventCode": "0x05",
"EventName": "UNC_I_TxC_BL_DRS_CYCLES_FULL",
"Experimental": "1",
"PerPkg": "1",
"Unit": "IRP"
},
{
"BriefDescription": "BL DRS Egress Inserts",
"Counter": "0,1",
"EventCode": "0x02",
"EventName": "UNC_I_TxC_BL_DRS_INSERTS",
"Experimental": "1",
"PerPkg": "1",
"Unit": "IRP"
},
{
"BriefDescription": "BL DRS Egress Occupancy",
"Counter": "0,1",
"EventCode": "0x08",
"EventName": "UNC_I_TxC_BL_DRS_OCCUPANCY",
"Experimental": "1",
"PerPkg": "1",
"Unit": "IRP"
},
{
"BriefDescription": "BL NCB Egress Cycles Full",
"Counter": "0,1",
"EventCode": "0x06",
"EventName": "UNC_I_TxC_BL_NCB_CYCLES_FULL",
"Experimental": "1",
"PerPkg": "1",
"Unit": "IRP"
},
{
"BriefDescription": "BL NCB Egress Inserts",
"Counter": "0,1",
"EventCode": "0x03",
"EventName": "UNC_I_TxC_BL_NCB_INSERTS",
"Experimental": "1",
"PerPkg": "1",
"Unit": "IRP"
},
{
"BriefDescription": "BL NCB Egress Occupancy",
"Counter": "0,1",
"EventCode": "0x09",
"EventName": "UNC_I_TxC_BL_NCB_OCCUPANCY",
"Experimental": "1",
"PerPkg": "1",
"Unit": "IRP"
},
{
"BriefDescription": "BL NCS Egress Cycles Full",
"Counter": "0,1",
"EventCode": "0x07",
"EventName": "UNC_I_TxC_BL_NCS_CYCLES_FULL",
"Experimental": "1",
"PerPkg": "1",
"Unit": "IRP"
},
{
"BriefDescription": "BL NCS Egress Inserts",
"Counter": "0,1",
"EventCode": "0x04",
"EventName": "UNC_I_TxC_BL_NCS_INSERTS",
"Experimental": "1",
"PerPkg": "1",
"Unit": "IRP"
},
{
"BriefDescription": "BL NCS Egress Occupancy",
"Counter": "0,1",
"EventCode": "0x0A",
"EventName": "UNC_I_TxC_BL_NCS_OCCUPANCY",
"Experimental": "1",
"PerPkg": "1",
"Unit": "IRP"
},
{
"BriefDescription": "UNC_I_TxR2_AD01_STALL_CREDIT_CYCLES",
"Counter": "0,1",
"EventCode": "0x1C",
"EventName": "UNC_I_TxR2_AD01_STALL_CREDIT_CYCLES",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": ": Counts the number times when it is not possible to issue a request to the M2PCIe because there are no Egress Credits available on AD0, A1 or AD0&AD1 both. Stalls on both AD0 and AD1 will count as 2",
"Unit": "IRP"
},
{
"BriefDescription": "No AD0 Egress Credits Stalls",
"Counter": "0,1",
"EventCode": "0x1A",
"EventName": "UNC_I_TxR2_AD0_STALL_CREDIT_CYCLES",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "No AD0 Egress Credits Stalls : Counts the number times when it is not possible to issue a request to the M2PCIe because there are no AD0 Egress Credits available.",
"Unit": "IRP"
},
{
"BriefDescription": "No AD1 Egress Credits Stalls",
"Counter": "0,1",
"EventCode": "0x1B",
"EventName": "UNC_I_TxR2_AD1_STALL_CREDIT_CYCLES",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "No AD1 Egress Credits Stalls : Counts the number times when it is not possible to issue a request to the M2PCIe because there are no AD1 Egress Credits available.",
"Unit": "IRP"
},
{
"BriefDescription": "No BL Egress Credit Stalls",
"Counter": "0,1",
"EventCode": "0x1D",
"EventName": "UNC_I_TxR2_BL_STALL_CREDIT_CYCLES",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "No BL Egress Credit Stalls : Counts the number times when it is not possible to issue data to the R2PCIe because there are no BL Egress Credits available.",
"Unit": "IRP"
},
{
"BriefDescription": "Outbound Read Requests",
"Counter": "0,1",
"EventCode": "0x0D",
"EventName": "UNC_I_TxS_DATA_INSERTS_NCB",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Outbound Read Requests : Counts the number of requests issued to the switch (towards the devices).",
"Unit": "IRP"
},
{
"BriefDescription": "Outbound Read Requests",
"Counter": "0,1",
"EventCode": "0x0E",
"EventName": "UNC_I_TxS_DATA_INSERTS_NCS",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Outbound Read Requests : Counts the number of requests issued to the switch (towards the devices).",
"Unit": "IRP"
},
{
"BriefDescription": "Outbound Request Queue Occupancy",
"Counter": "0,1",
"EventCode": "0x0C",
"EventName": "UNC_I_TxS_REQUEST_OCCUPANCY",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Outbound Request Queue Occupancy : Accumulates the number of outstanding outbound requests from the IRP to the switch (towards the devices). This can be used in conjunction with the allocations event in order to calculate average latency of outbound requests.",
"Unit": "IRP"
},
{
"BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 0",
"Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR0",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 0 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 1",
"Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR1",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 1 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 2",
"Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR2",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 2 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x4",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 3",
"Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR3",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 3 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x8",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 4",
"Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR4",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 4 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x10",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 5",
"Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR5",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 5 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x20",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 6",
"Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR6",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 6 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x40",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 7",
"Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR7",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 7 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x80",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 10",
"Counter": "0,1,2,3",
"EventCode": "0x81",
"EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED1.TGR10",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 10 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x4",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 8",
"Counter": "0,1,2,3",
"EventCode": "0x81",
"EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED1.TGR8",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 8 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 9",
"Counter": "0,1,2,3",
"EventCode": "0x81",
"EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED1.TGR9",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 9 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 0",
"Counter": "0,1,2,3",
"EventCode": "0x82",
"EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR0",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 0 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 1",
"Counter": "0,1,2,3",
"EventCode": "0x82",
"EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR1",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 1 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 2",
"Counter": "0,1,2,3",
"EventCode": "0x82",
"EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR2",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 2 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
"UMask": "0x4",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 3",
"Counter": "0,1,2,3",
"EventCode": "0x82",
"EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR3",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 3 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
"UMask": "0x8",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 4",
"Counter": "0,1,2,3",
"EventCode": "0x82",
"EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR4",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 4 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
"UMask": "0x10",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 5",
"Counter": "0,1,2,3",
"EventCode": "0x82",
"EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR5",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 5 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
"UMask": "0x20",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 6",
"Counter": "0,1,2,3",
"EventCode": "0x82",
"EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR6",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 6 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
"UMask": "0x40",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 7",
"Counter": "0,1,2,3",
"EventCode": "0x82",
"EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR7",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 7 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
"UMask": "0x80",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 10",
"Counter": "0,1,2,3",
"EventCode": "0x83",
"EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY1.TGR10",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 10 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
"UMask": "0x4",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 8",
"Counter": "0,1,2,3",
"EventCode": "0x83",
"EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY1.TGR8",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 8 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 9",
"Counter": "0,1,2,3",
"EventCode": "0x83",
"EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY1.TGR9",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 9 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 0",
"Counter": "0,1,2,3",
"EventCode": "0x88",
"EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR0",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 0 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 1",
"Counter": "0,1,2,3",
"EventCode": "0x88",
"EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR1",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 1 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 2",
"Counter": "0,1,2,3",
"EventCode": "0x88",
"EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR2",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 2 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x4",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 3",
"Counter": "0,1,2,3",
"EventCode": "0x88",
"EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR3",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 3 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x8",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 4",
"Counter": "0,1,2,3",
"EventCode": "0x88",
"EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR4",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 4 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x10",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 5",
"Counter": "0,1,2,3",
"EventCode": "0x88",
"EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR5",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 5 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x20",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 6",
"Counter": "0,1,2,3",
"EventCode": "0x88",
"EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR6",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 6 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x40",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 7",
"Counter": "0,1,2,3",
"EventCode": "0x88",
"EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR7",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 7 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x80",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 10",
"Counter": "0,1,2,3",
"EventCode": "0x89",
"EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED1.TGR10",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 10 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x4",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 8",
"Counter": "0,1,2,3",
"EventCode": "0x89",
"EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED1.TGR8",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 8 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 9",
"Counter": "0,1,2,3",
"EventCode": "0x89",
"EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED1.TGR9",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 9 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 0",
"Counter": "0,1,2,3",
"EventCode": "0x8A",
"EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR0",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 0 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 1",
"Counter": "0,1,2,3",
"EventCode": "0x8A",
"EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR1",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 1 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 2",
"Counter": "0,1,2,3",
"EventCode": "0x8A",
"EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR2",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 2 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
"UMask": "0x4",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 3",
"Counter": "0,1,2,3",
"EventCode": "0x8A",
"EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR3",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 3 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
"UMask": "0x8",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 4",
"Counter": "0,1,2,3",
"EventCode": "0x8A",
"EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR4",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 4 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
"UMask": "0x10",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 5",
"Counter": "0,1,2,3",
"EventCode": "0x8A",
"EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR5",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 5 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
"UMask": "0x20",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 6",
"Counter": "0,1,2,3",
"EventCode": "0x8A",
"EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR6",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 6 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
"UMask": "0x40",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 7",
"Counter": "0,1,2,3",
"EventCode": "0x8A",
"EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR7",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 7 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
"UMask": "0x80",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 10",
"Counter": "0,1,2,3",
"EventCode": "0x8B",
"EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY1.TGR10",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 10 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
"UMask": "0x4",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 8",
"Counter": "0,1,2,3",
"EventCode": "0x8B",
"EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY1.TGR8",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 8 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 9",
"Counter": "0,1,2,3",
"EventCode": "0x8B",
"EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY1.TGR9",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 9 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 0",
"Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR0",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 0 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 1",
"Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR1",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 1 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 2",
"Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR2",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 2 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x4",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 3",
"Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR3",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 3 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x8",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 4",
"Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR4",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 4 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x10",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 5",
"Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR5",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 5 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x20",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 6",
"Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR6",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 6 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x40",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 7",
"Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR7",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 7 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x80",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 10",
"Counter": "0,1,2,3",
"EventCode": "0x85",
"EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED1.TGR10",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 10 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x4",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 8",
"Counter": "0,1,2,3",
"EventCode": "0x85",
"EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED1.TGR8",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 8 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 9",
"Counter": "0,1,2,3",
"EventCode": "0x85",
"EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED1.TGR9",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 9 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 0",
"Counter": "0,1,2,3",
"EventCode": "0x86",
"EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR0",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 0 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 1",
"Counter": "0,1,2,3",
"EventCode": "0x86",
"EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR1",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 1 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 2",
"Counter": "0,1,2,3",
"EventCode": "0x86",
"EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR2",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 2 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
"UMask": "0x4",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 3",
"Counter": "0,1,2,3",
"EventCode": "0x86",
"EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR3",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 3 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
"UMask": "0x8",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 4",
"Counter": "0,1,2,3",
"EventCode": "0x86",
"EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR4",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 4 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
"UMask": "0x10",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 5",
"Counter": "0,1,2,3",
"EventCode": "0x86",
"EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR5",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 5 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
"UMask": "0x20",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 6",
"Counter": "0,1,2,3",
"EventCode": "0x86",
"EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR6",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 6 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
"UMask": "0x40",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 7",
"Counter": "0,1,2,3",
"EventCode": "0x86",
"EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR7",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 7 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
"UMask": "0x80",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 10",
"Counter": "0,1,2,3",
"EventCode": "0x87",
"EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY1.TGR10",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 10 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
"UMask": "0x4",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 8",
"Counter": "0,1,2,3",
"EventCode": "0x87",
"EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY1.TGR8",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 8 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 9",
"Counter": "0,1,2,3",
"EventCode": "0x87",
"EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY1.TGR9",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 9 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 0",
"Counter": "0,1,2,3",
"EventCode": "0x8C",
"EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR0",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 0 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 1",
"Counter": "0,1,2,3",
"EventCode": "0x8C",
"EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR1",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 1 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 2",
"Counter": "0,1,2,3",
"EventCode": "0x8C",
"EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR2",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 2 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x4",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 3",
"Counter": "0,1,2,3",
"EventCode": "0x8C",
"EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR3",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 3 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x8",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4",
"Counter": "0,1,2,3",
"EventCode": "0x8C",
"EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR4",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x10",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5",
"Counter": "0,1,2,3",
"EventCode": "0x8C",
"EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR5",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x20",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4",
"Counter": "0,1,2,3",
"EventCode": "0x8C",
"EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR6",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x40",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5",
"Counter": "0,1,2,3",
"EventCode": "0x8C",
"EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR7",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x80",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 10",
"Counter": "0,1,2,3",
"EventCode": "0x8D",
"EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED1.TGR10",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 10 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x4",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 8",
"Counter": "0,1,2,3",
"EventCode": "0x8D",
"EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED1.TGR8",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 8 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 9",
"Counter": "0,1,2,3",
"EventCode": "0x8D",
"EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED1.TGR9",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 9 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 0",
"Counter": "0,1,2,3",
"EventCode": "0x8E",
"EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR0",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 0 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 1",
"Counter": "0,1,2,3",
"EventCode": "0x8E",
"EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR1",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 1 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 2",
"Counter": "0,1,2,3",
"EventCode": "0x8E",
"EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR2",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 2 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
"UMask": "0x4",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 3",
"Counter": "0,1,2,3",
"EventCode": "0x8E",
"EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR3",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 3 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
"UMask": "0x8",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 4",
"Counter": "0,1,2,3",
"EventCode": "0x8E",
"EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR4",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 4 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
"UMask": "0x10",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 5",
"Counter": "0,1,2,3",
"EventCode": "0x8E",
"EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR5",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 5 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
"UMask": "0x20",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 6",
"Counter": "0,1,2,3",
"EventCode": "0x8E",
"EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR6",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 6 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
"UMask": "0x40",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 7",
"Counter": "0,1,2,3",
"EventCode": "0x8E",
"EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR7",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 7 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
"UMask": "0x80",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 10",
"Counter": "0,1,2,3",
"EventCode": "0x8F",
"EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY1.TGR10",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 10 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
"UMask": "0x4",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 8",
"Counter": "0,1,2,3",
"EventCode": "0x8F",
"EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY1.TGR8",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 8 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 9",
"Counter": "0,1,2,3",
"EventCode": "0x8F",
"EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY1.TGR9",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 9 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "M2M to iMC Bypass : Not Taken",
"Counter": "0,1,2,3",
"EventCode": "0x22",
"EventName": "UNC_M2M_BYPASS_M2M_EGRESS.NOT_TAKEN",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "M2M to iMC Bypass : Taken",
"Counter": "0,1,2,3",
"EventCode": "0x22",
"EventName": "UNC_M2M_BYPASS_M2M_EGRESS.TAKEN",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "M2M to iMC Bypass : Not Taken",
"Counter": "0,1,2,3",
"EventCode": "0x21",
"EventName": "UNC_M2M_BYPASS_M2M_INGRESS.NOT_TAKEN",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "M2M to iMC Bypass : Taken",
"Counter": "0,1,2,3",
"EventCode": "0x21",
"EventName": "UNC_M2M_BYPASS_M2M_INGRESS.TAKEN",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "Clockticks of the mesh to memory (M2M)",
"Counter": "0,1,2,3",
"EventName": "UNC_M2M_CLOCKTICKS",
"PerPkg": "1",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Clockticks",
"Counter": "0,1,2,3",
"EventCode": "0xc0",
"EventName": "UNC_M2M_CMS_CLOCKTICKS",
"PerPkg": "1",
"Unit": "M2M"
},
{
"BriefDescription": "Cycles when direct to core mode, which bypasses the CHA, was disabled",
"Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "UNC_M2M_DIRECT2CORE_NOT_TAKEN_DIRSTATE",
"Experimental": "1",
"PerPkg": "1",
"Unit": "M2M"
},
{
"BriefDescription": "UNC_M2M_DIRECT2CORE_NOT_TAKEN_NOTFORKED",
"Counter": "0,1,2,3",
"EventCode": "0x60",
"EventName": "UNC_M2M_DIRECT2CORE_NOT_TAKEN_NOTFORKED",
"Experimental": "1",
"PerPkg": "1",
"Unit": "M2M"
},
{
"BriefDescription": "Number of reads in which direct to core transaction was overridden",
"Counter": "0,1,2,3",
"EventCode": "0x25",
"EventName": "UNC_M2M_DIRECT2CORE_TXN_OVERRIDE",
"Experimental": "1",
"PerPkg": "1",
"Unit": "M2M"
},
{
"BriefDescription": "Number of reads in which direct to Intel UPI transactions were overridden",
"Counter": "0,1,2,3",
"EventCode": "0x28",
"EventName": "UNC_M2M_DIRECT2UPI_NOT_TAKEN_CREDITS",
"Experimental": "1",
"PerPkg": "1",
"Unit": "M2M"
},
{
"BriefDescription": "Cycles when Direct2UPI was Disabled",
"Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "UNC_M2M_DIRECT2UPI_NOT_TAKEN_DIRSTATE",
"Experimental": "1",
"PerPkg": "1",
"Unit": "M2M"
},
{
"BriefDescription": "Number of reads that a message sent direct2 Intel UPI was overridden",
"Counter": "0,1,2,3",
"EventCode": "0x29",
"EventName": "UNC_M2M_DIRECT2UPI_TXN_OVERRIDE",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Clockticks of the mesh to PCI (M2P)",
"Unit": "M2M"
},
{
"BriefDescription": "Directory Hit : On NonDirty Line in A State",
"Counter": "0,1,2,3",
"EventCode": "0x2A",
"EventName": "UNC_M2M_DIRECTORY_HIT.CLEAN_A",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x80",
"Unit": "M2M"
},
{
"BriefDescription": "Directory Hit : On NonDirty Line in I State",
"Counter": "0,1,2,3",
"EventCode": "0x2A",
"EventName": "UNC_M2M_DIRECTORY_HIT.CLEAN_I",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "M2M"
},
{
"BriefDescription": "Directory Hit : On NonDirty Line in L State",
"Counter": "0,1,2,3",
"EventCode": "0x2A",
"EventName": "UNC_M2M_DIRECTORY_HIT.CLEAN_P",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x40",
"Unit": "M2M"
},
{
"BriefDescription": "Directory Hit : On NonDirty Line in S State",
"Counter": "0,1,2,3",
"EventCode": "0x2A",
"EventName": "UNC_M2M_DIRECTORY_HIT.CLEAN_S",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "M2M"
},
{
"BriefDescription": "Directory Hit : On Dirty Line in A State",
"Counter": "0,1,2,3",
"EventCode": "0x2A",
"EventName": "UNC_M2M_DIRECTORY_HIT.DIRTY_A",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "M2M"
},
{
"BriefDescription": "Directory Hit : On Dirty Line in I State",
"Counter": "0,1,2,3",
"EventCode": "0x2A",
"EventName": "UNC_M2M_DIRECTORY_HIT.DIRTY_I",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "Directory Hit : On Dirty Line in L State",
"Counter": "0,1,2,3",
"EventCode": "0x2A",
"EventName": "UNC_M2M_DIRECTORY_HIT.DIRTY_P",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "M2M"
},
{
"BriefDescription": "Directory Hit : On Dirty Line in S State",
"Counter": "0,1,2,3",
"EventCode": "0x2A",
"EventName": "UNC_M2M_DIRECTORY_HIT.DIRTY_S",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "Multi-socket cacheline Directory Lookups : Found in any state",
"Counter": "0,1,2,3",
"EventCode": "0x2D",
"EventName": "UNC_M2M_DIRECTORY_LOOKUP.ANY",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "Multi-socket cacheline Directory Lookups : Found in A state",
"Counter": "0,1,2,3",
"EventCode": "0x2D",
"EventName": "UNC_M2M_DIRECTORY_LOOKUP.STATE_A",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "M2M"
},
{
"BriefDescription": "Multi-socket cacheline Directory Lookups : Found in I state",
"Counter": "0,1,2,3",
"EventCode": "0x2D",
"EventName": "UNC_M2M_DIRECTORY_LOOKUP.STATE_I",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "Multi-socket cacheline Directory Lookups : Found in S state",
"Counter": "0,1,2,3",
"EventCode": "0x2D",
"EventName": "UNC_M2M_DIRECTORY_LOOKUP.STATE_S",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "M2M"
},
{
"BriefDescription": "Directory Miss : On NonDirty Line in A State",
"Counter": "0,1,2,3",
"EventCode": "0x2B",
"EventName": "UNC_M2M_DIRECTORY_MISS.CLEAN_A",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x80",
"Unit": "M2M"
},
{
"BriefDescription": "Directory Miss : On NonDirty Line in I State",
"Counter": "0,1,2,3",
"EventCode": "0x2B",
"EventName": "UNC_M2M_DIRECTORY_MISS.CLEAN_I",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "M2M"
},
{
"BriefDescription": "Directory Miss : On NonDirty Line in L State",
"Counter": "0,1,2,3",
"EventCode": "0x2B",
"EventName": "UNC_M2M_DIRECTORY_MISS.CLEAN_P",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x40",
"Unit": "M2M"
},
{
"BriefDescription": "Directory Miss : On NonDirty Line in S State",
"Counter": "0,1,2,3",
"EventCode": "0x2B",
"EventName": "UNC_M2M_DIRECTORY_MISS.CLEAN_S",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "M2M"
},
{
"BriefDescription": "Directory Miss : On Dirty Line in A State",
"Counter": "0,1,2,3",
"EventCode": "0x2B",
"EventName": "UNC_M2M_DIRECTORY_MISS.DIRTY_A",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "M2M"
},
{
"BriefDescription": "Directory Miss : On Dirty Line in I State",
"Counter": "0,1,2,3",
"EventCode": "0x2B",
"EventName": "UNC_M2M_DIRECTORY_MISS.DIRTY_I",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "Directory Miss : On Dirty Line in L State",
"Counter": "0,1,2,3",
"EventCode": "0x2B",
"EventName": "UNC_M2M_DIRECTORY_MISS.DIRTY_P",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "M2M"
},
{
"BriefDescription": "Directory Miss : On Dirty Line in S State",
"Counter": "0,1,2,3",
"EventCode": "0x2B",
"EventName": "UNC_M2M_DIRECTORY_MISS.DIRTY_S",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "Multi-socket cacheline Directory Updates : From/to any state. Note: event counts are incorrect in 2LM mode.",
"Counter": "0,1,2,3",
"EventCode": "0x2e",
"EventName": "UNC_M2M_DIRECTORY_UPDATE.ANY",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "Distress signal asserted : DPT Local",
"Counter": "0,1,2,3",
"EventCode": "0xAF",
"EventName": "UNC_M2M_DISTRESS_ASSERTED.DPT_LOCAL",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Distress signal asserted : DPT Local : Counts the number of cycles either the local or incoming distress signals are asserted. : Dynamic Prefetch Throttle triggered by this tile",
"UMask": "0x4",
"Unit": "M2M"
},
{
"BriefDescription": "Distress signal asserted : DPT Remote",
"Counter": "0,1,2,3",
"EventCode": "0xAF",
"EventName": "UNC_M2M_DISTRESS_ASSERTED.DPT_NONLOCAL",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Distress signal asserted : DPT Remote : Counts the number of cycles either the local or incoming distress signals are asserted. : Dynamic Prefetch Throttle received by this tile",
"UMask": "0x8",
"Unit": "M2M"
},
{
"BriefDescription": "Distress signal asserted : DPT Stalled - IV",
"Counter": "0,1,2,3",
"EventCode": "0xAF",
"EventName": "UNC_M2M_DISTRESS_ASSERTED.DPT_STALL_IV",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Distress signal asserted : DPT Stalled - IV : Counts the number of cycles either the local or incoming distress signals are asserted. : DPT occurred while regular IVs were received, causing DPT to be stalled",
"UMask": "0x40",
"Unit": "M2M"
},
{
"BriefDescription": "Distress signal asserted : DPT Stalled - No Credit",
"Counter": "0,1,2,3",
"EventCode": "0xAF",
"EventName": "UNC_M2M_DISTRESS_ASSERTED.DPT_STALL_NOCRD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Distress signal asserted : DPT Stalled - No Credit : Counts the number of cycles either the local or incoming distress signals are asserted. : DPT occurred while credit not available causing DPT to be stalled",
"UMask": "0x80",
"Unit": "M2M"
},
{
"BriefDescription": "Distress signal asserted : Horizontal",
"Counter": "0,1,2,3",
"EventCode": "0xAF",
"EventName": "UNC_M2M_DISTRESS_ASSERTED.HORZ",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Distress signal asserted : Horizontal : Counts the number of cycles either the local or incoming distress signals are asserted. : If TGR egress is full, then agents will throttle outgoing AD IDI transactions",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "Distress signal asserted : PMM Local",
"Counter": "0,1,2,3",
"EventCode": "0xAF",
"EventName": "UNC_M2M_DISTRESS_ASSERTED.PMM_LOCAL",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Distress signal asserted : PMM Local : Counts the number of cycles either the local or incoming distress signals are asserted. : If the CHA TOR has too many PMM transactions, this signal will throttle outgoing MS2IDI traffic",
"UMask": "0x10",
"Unit": "M2M"
},
{
"BriefDescription": "Distress signal asserted : PMM Remote",
"Counter": "0,1,2,3",
"EventCode": "0xAF",
"EventName": "UNC_M2M_DISTRESS_ASSERTED.PMM_NONLOCAL",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Distress signal asserted : PMM Remote : Counts the number of cycles either the local or incoming distress signals are asserted. : If another CHA TOR has too many PMM transactions, this signal will throttle outgoing MS2IDI traffic",
"UMask": "0x20",
"Unit": "M2M"
},
{
"BriefDescription": "Distress signal asserted : Vertical",
"Counter": "0,1,2,3",
"EventCode": "0xAF",
"EventName": "UNC_M2M_DISTRESS_ASSERTED.VERT",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Distress signal asserted : Vertical : Counts the number of cycles either the local or incoming distress signals are asserted. : If IRQ egress is full, then agents will throttle outgoing AD IDI transactions",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "UNC_M2M_DISTRESS_PMM",
"Counter": "0,1,2,3",
"EventCode": "0xF2",
"EventName": "UNC_M2M_DISTRESS_PMM",
"Experimental": "1",
"PerPkg": "1",
"Unit": "M2M"
},
{
"BriefDescription": "UNC_M2M_DISTRESS_PMM_MEMMODE",
"Counter": "0,1,2,3",
"EventCode": "0xF1",
"EventName": "UNC_M2M_DISTRESS_PMM_MEMMODE",
"Experimental": "1",
"PerPkg": "1",
"Unit": "M2M"
},
{
"BriefDescription": "Egress Blocking due to Ordering requirements : Down",
"Counter": "0,1,2,3",
"EventCode": "0xBA",
"EventName": "UNC_M2M_EGRESS_ORDERING.IV_SNOOPGO_DN",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Egress Blocking due to Ordering requirements : Down : Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements",
"UMask": "0x4",
"Unit": "M2M"
},
{
"BriefDescription": "Egress Blocking due to Ordering requirements : Up",
"Counter": "0,1,2,3",
"EventCode": "0xBA",
"EventName": "UNC_M2M_EGRESS_ORDERING.IV_SNOOPGO_UP",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Egress Blocking due to Ordering requirements : Up : Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "Horizontal AD Ring In Use : Left and Even",
"Counter": "0,1,2,3",
"EventCode": "0xB6",
"EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.LEFT_EVEN",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Horizontal AD Ring In Use : Left and Even : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "Horizontal AD Ring In Use : Left and Odd",
"Counter": "0,1,2,3",
"EventCode": "0xB6",
"EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.LEFT_ODD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Horizontal AD Ring In Use : Left and Odd : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "Horizontal AD Ring In Use : Right and Even",
"Counter": "0,1,2,3",
"EventCode": "0xB6",
"EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.RIGHT_EVEN",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Horizontal AD Ring In Use : Right and Even : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x4",
"Unit": "M2M"
},
{
"BriefDescription": "Horizontal AD Ring In Use : Right and Odd",
"Counter": "0,1,2,3",
"EventCode": "0xB6",
"EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.RIGHT_ODD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Horizontal AD Ring In Use : Right and Odd : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x8",
"Unit": "M2M"
},
{
"BriefDescription": "Horizontal AK Ring In Use : Left and Even",
"Counter": "0,1,2,3",
"EventCode": "0xBB",
"EventName": "UNC_M2M_HORZ_RING_AKC_IN_USE.LEFT_EVEN",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Horizontal AK Ring In Use : Left and Even : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "Horizontal AK Ring In Use : Left and Odd",
"Counter": "0,1,2,3",
"EventCode": "0xBB",
"EventName": "UNC_M2M_HORZ_RING_AKC_IN_USE.LEFT_ODD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Horizontal AK Ring In Use : Left and Odd : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "Horizontal AK Ring In Use : Right and Even",
"Counter": "0,1,2,3",
"EventCode": "0xBB",
"EventName": "UNC_M2M_HORZ_RING_AKC_IN_USE.RIGHT_EVEN",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Horizontal AK Ring In Use : Right and Even : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x4",
"Unit": "M2M"
},
{
"BriefDescription": "Horizontal AK Ring In Use : Right and Odd",
"Counter": "0,1,2,3",
"EventCode": "0xBB",
"EventName": "UNC_M2M_HORZ_RING_AKC_IN_USE.RIGHT_ODD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Horizontal AK Ring In Use : Right and Odd : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x8",
"Unit": "M2M"
},
{
"BriefDescription": "Horizontal AK Ring In Use : Left and Even",
"Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.LEFT_EVEN",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Horizontal AK Ring In Use : Left and Even : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "Horizontal AK Ring In Use : Left and Odd",
"Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.LEFT_ODD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Horizontal AK Ring In Use : Left and Odd : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "Horizontal AK Ring In Use : Right and Even",
"Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.RIGHT_EVEN",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Horizontal AK Ring In Use : Right and Even : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x4",
"Unit": "M2M"
},
{
"BriefDescription": "Horizontal AK Ring In Use : Right and Odd",
"Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.RIGHT_ODD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Horizontal AK Ring In Use : Right and Odd : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x8",
"Unit": "M2M"
},
{
"BriefDescription": "Horizontal BL Ring in Use : Left and Even",
"Counter": "0,1,2,3",
"EventCode": "0xB8",
"EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.LEFT_EVEN",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Horizontal BL Ring in Use : Left and Even : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "Horizontal BL Ring in Use : Left and Odd",
"Counter": "0,1,2,3",
"EventCode": "0xB8",
"EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.LEFT_ODD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Horizontal BL Ring in Use : Left and Odd : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "Horizontal BL Ring in Use : Right and Even",
"Counter": "0,1,2,3",
"EventCode": "0xB8",
"EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.RIGHT_EVEN",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Horizontal BL Ring in Use : Right and Even : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x4",
"Unit": "M2M"
},
{
"BriefDescription": "Horizontal BL Ring in Use : Right and Odd",
"Counter": "0,1,2,3",
"EventCode": "0xB8",
"EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.RIGHT_ODD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Horizontal BL Ring in Use : Right and Odd : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x8",
"Unit": "M2M"
},
{
"BriefDescription": "Horizontal IV Ring in Use : Left",
"Counter": "0,1,2,3",
"EventCode": "0xB9",
"EventName": "UNC_M2M_HORZ_RING_IV_IN_USE.LEFT",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Horizontal IV Ring in Use : Left : Counts the number of cycles that the Horizontal IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "Horizontal IV Ring in Use : Right",
"Counter": "0,1,2,3",
"EventCode": "0xB9",
"EventName": "UNC_M2M_HORZ_RING_IV_IN_USE.RIGHT",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Horizontal IV Ring in Use : Right : Counts the number of cycles that the Horizontal IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.",
"UMask": "0x4",
"Unit": "M2M"
},
{
"BriefDescription": "M2M Reads Issued to iMC : All, regardless of priority. - All Channels",
"Counter": "0,1,2,3",
"EventCode": "0x37",
"EventName": "UNC_M2M_IMC_READS.ALL",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x704",
"Unit": "M2M"
},
{
"BriefDescription": "M2M Reads Issued to iMC : All, regardless of priority. - Ch0",
"Counter": "0,1,2,3",
"EventCode": "0x37",
"EventName": "UNC_M2M_IMC_READS.CH0_ALL",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x104",
"Unit": "M2M"
},
{
"BriefDescription": "M2M Reads Issued to iMC : From TGR - Ch0",
"Counter": "0,1,2,3",
"EventCode": "0x37",
"EventName": "UNC_M2M_IMC_READS.CH0_FROM_TGR",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x140",
"Unit": "M2M"
},
{
"BriefDescription": "M2M Reads Issued to iMC : Critical Priority - Ch0",
"Counter": "0,1,2,3",
"EventCode": "0x37",
"EventName": "UNC_M2M_IMC_READS.CH0_ISOCH",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x102",
"Unit": "M2M"
},
{
"BriefDescription": "M2M Reads Issued to iMC : Normal Priority - Ch0",
"Counter": "0,1,2,3",
"EventCode": "0x37",
"EventName": "UNC_M2M_IMC_READS.CH0_NORMAL",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x101",
"Unit": "M2M"
},
{
"BriefDescription": "M2M Reads Issued to iMC : DDR, acting as Cache - Ch0",
"Counter": "0,1,2,3",
"EventCode": "0x37",
"EventName": "UNC_M2M_IMC_READS.CH0_TO_DDR_AS_CACHE",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x110",
"Unit": "M2M"
},
{
"BriefDescription": "M2M Reads Issued to iMC : DDR - Ch0",
"Counter": "0,1,2,3",
"EventCode": "0x37",
"EventName": "UNC_M2M_IMC_READS.CH0_TO_DDR_AS_MEM",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x108",
"Unit": "M2M"
},
{
"BriefDescription": "M2M Reads Issued to iMC : PMM - Ch0",
"Counter": "0,1,2,3",
"EventCode": "0x37",
"EventName": "UNC_M2M_IMC_READS.CH0_TO_PMM",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "M2M Reads Issued to iMC : PMM - Ch0 : Counts all PMM dimm read requests(full line) sent from M2M to iMC",
"UMask": "0x120",
"Unit": "M2M"
},
{
"BriefDescription": "M2M Reads Issued to iMC : All, regardless of priority. - Ch1",
"Counter": "0,1,2,3",
"EventCode": "0x37",
"EventName": "UNC_M2M_IMC_READS.CH1_ALL",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x204",
"Unit": "M2M"
},
{
"BriefDescription": "M2M Reads Issued to iMC : From TGR - Ch1",
"Counter": "0,1,2,3",
"EventCode": "0x37",
"EventName": "UNC_M2M_IMC_READS.CH1_FROM_TGR",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x240",
"Unit": "M2M"
},
{
"BriefDescription": "M2M Reads Issued to iMC : Critical Priority - Ch1",
"Counter": "0,1,2,3",
"EventCode": "0x37",
"EventName": "UNC_M2M_IMC_READS.CH1_ISOCH",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x202",
"Unit": "M2M"
},
{
"BriefDescription": "M2M Reads Issued to iMC : Normal Priority - Ch1",
"Counter": "0,1,2,3",
"EventCode": "0x37",
"EventName": "UNC_M2M_IMC_READS.CH1_NORMAL",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x201",
"Unit": "M2M"
},
{
"BriefDescription": "M2M Reads Issued to iMC : DDR, acting as Cache - Ch1",
"Counter": "0,1,2,3",
"EventCode": "0x37",
"EventName": "UNC_M2M_IMC_READS.CH1_TO_DDR_AS_CACHE",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x210",
"Unit": "M2M"
},
{
"BriefDescription": "M2M Reads Issued to iMC : DDR - Ch1",
"Counter": "0,1,2,3",
"EventCode": "0x37",
"EventName": "UNC_M2M_IMC_READS.CH1_TO_DDR_AS_MEM",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x208",
"Unit": "M2M"
},
{
"BriefDescription": "M2M Reads Issued to iMC : PMM - Ch1",
"Counter": "0,1,2,3",
"EventCode": "0x37",
"EventName": "UNC_M2M_IMC_READS.CH1_TO_PMM",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "M2M Reads Issued to iMC : PMM - Ch1 : Counts all PMM dimm read requests(full line) sent from M2M to iMC",
"UMask": "0x220",
"Unit": "M2M"
},
{
"BriefDescription": "M2M Reads Issued to iMC : From TGR - Ch2",
"Counter": "0,1,2,3",
"EventCode": "0x37",
"EventName": "UNC_M2M_IMC_READS.CH2_FROM_TGR",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x440",
"Unit": "M2M"
},
{
"BriefDescription": "M2M Reads Issued to iMC : From TGR - All Channels",
"Counter": "0,1,2,3",
"EventCode": "0x37",
"EventName": "UNC_M2M_IMC_READS.FROM_TGR",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x740",
"Unit": "M2M"
},
{
"BriefDescription": "M2M Reads Issued to iMC : Critical Priority - All Channels",
"Counter": "0,1,2,3",
"EventCode": "0x37",
"EventName": "UNC_M2M_IMC_READS.ISOCH",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x702",
"Unit": "M2M"
},
{
"BriefDescription": "M2M Reads Issued to iMC : Normal Priority - All Channels",
"Counter": "0,1,2,3",
"EventCode": "0x37",
"EventName": "UNC_M2M_IMC_READS.NORMAL",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x701",
"Unit": "M2M"
},
{
"BriefDescription": "M2M Reads Issued to iMC : DDR, acting as Cache - All Channels",
"Counter": "0,1,2,3",
"EventCode": "0x37",
"EventName": "UNC_M2M_IMC_READS.TO_DDR_AS_CACHE",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x710",
"Unit": "M2M"
},
{
"BriefDescription": "M2M Reads Issued to iMC : DDR - All Channels",
"Counter": "0,1,2,3",
"EventCode": "0x37",
"EventName": "UNC_M2M_IMC_READS.TO_DDR_AS_MEM",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x708",
"Unit": "M2M"
},
{
"BriefDescription": "M2M Reads Issued to iMC : PMM - All Channels",
"Counter": "0,1,2,3",
"EventCode": "0x37",
"EventName": "UNC_M2M_IMC_READS.TO_PMM",
"PerPkg": "1",
"UMask": "0x720",
"Unit": "M2M"
},
{
"BriefDescription": "M2M Writes Issued to iMC : All Writes - All Channels",
"Counter": "0,1,2,3",
"EventCode": "0x38",
"EventName": "UNC_M2M_IMC_WRITES.ALL",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x1c10",
"Unit": "M2M"
},
{
"BriefDescription": "M2M Writes Issued to iMC : All Writes - Ch0",
"Counter": "0,1,2,3",
"EventCode": "0x38",
"EventName": "UNC_M2M_IMC_WRITES.CH0_ALL",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x410",
"Unit": "M2M"
},
{
"BriefDescription": "M2M Writes Issued to iMC : From TGR - Ch0",
"Counter": "0,1,2,3",
"EventCode": "0x38",
"EventName": "UNC_M2M_IMC_WRITES.CH0_FROM_TGR",
"Experimental": "1",
"PerPkg": "1",
"Unit": "M2M"
},
{
"BriefDescription": "M2M Writes Issued to iMC : Full Line Non-ISOCH - Ch0",
"Counter": "0,1,2,3",
"EventCode": "0x38",
"EventName": "UNC_M2M_IMC_WRITES.CH0_FULL",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x401",
"Unit": "M2M"
},
{
"BriefDescription": "M2M Writes Issued to iMC : ISOCH Full Line - Ch0",
"Counter": "0,1,2,3",
"EventCode": "0x38",
"EventName": "UNC_M2M_IMC_WRITES.CH0_FULL_ISOCH",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x404",
"Unit": "M2M"
},
{
"BriefDescription": "M2M Writes Issued to iMC : Non-Inclusive - Ch0",
"Counter": "0,1,2,3",
"EventCode": "0x38",
"EventName": "UNC_M2M_IMC_WRITES.CH0_NI",
"Experimental": "1",
"PerPkg": "1",
"Unit": "M2M"
},
{
"BriefDescription": "M2M Writes Issued to iMC : Non-Inclusive Miss - Ch0",
"Counter": "0,1,2,3",
"EventCode": "0x38",
"EventName": "UNC_M2M_IMC_WRITES.CH0_NI_MISS",
"Experimental": "1",
"PerPkg": "1",
"Unit": "M2M"
},
{
"BriefDescription": "M2M Writes Issued to iMC : Partial Non-ISOCH - Ch0",
"Counter": "0,1,2,3",
"EventCode": "0x38",
"EventName": "UNC_M2M_IMC_WRITES.CH0_PARTIAL",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x402",
"Unit": "M2M"
},
{
"BriefDescription": "M2M Writes Issued to iMC : ISOCH Partial - Ch0",
"Counter": "0,1,2,3",
"EventCode": "0x38",
"EventName": "UNC_M2M_IMC_WRITES.CH0_PARTIAL_ISOCH",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x408",
"Unit": "M2M"
},
{
"BriefDescription": "M2M Writes Issued to iMC : DDR, acting as Cache - Ch0",
"Counter": "0,1,2,3",
"EventCode": "0x38",
"EventName": "UNC_M2M_IMC_WRITES.CH0_TO_DDR_AS_CACHE",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x440",
"Unit": "M2M"
},
{
"BriefDescription": "M2M Writes Issued to iMC : DDR - Ch0",
"Counter": "0,1,2,3",
"EventCode": "0x38",
"EventName": "UNC_M2M_IMC_WRITES.CH0_TO_DDR_AS_MEM",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x420",
"Unit": "M2M"
},
{
"BriefDescription": "M2M Writes Issued to iMC : PMM - Ch0",
"Counter": "0,1,2,3",
"EventCode": "0x38",
"EventName": "UNC_M2M_IMC_WRITES.CH0_TO_PMM",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "M2M Writes Issued to iMC : PMM - Ch0 : Counts all PMM dimm writes requests(full line and partial) sent from M2M to iMC",
"UMask": "0x480",
"Unit": "M2M"
},
{
"BriefDescription": "M2M Writes Issued to iMC : All Writes - Ch1",
"Counter": "0,1,2,3",
"EventCode": "0x38",
"EventName": "UNC_M2M_IMC_WRITES.CH1_ALL",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x810",
"Unit": "M2M"
},
{
"BriefDescription": "M2M Writes Issued to iMC : From TGR - Ch1",
"Counter": "0,1,2,3",
"EventCode": "0x38",
"EventName": "UNC_M2M_IMC_WRITES.CH1_FROM_TGR",
"Experimental": "1",
"PerPkg": "1",
"Unit": "M2M"
},
{
"BriefDescription": "M2M Writes Issued to iMC : Full Line Non-ISOCH - Ch1",
"Counter": "0,1,2,3",
"EventCode": "0x38",
"EventName": "UNC_M2M_IMC_WRITES.CH1_FULL",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x801",
"Unit": "M2M"
},
{
"BriefDescription": "M2M Writes Issued to iMC : ISOCH Full Line - Ch1",
"Counter": "0,1,2,3",
"EventCode": "0x38",
"EventName": "UNC_M2M_IMC_WRITES.CH1_FULL_ISOCH",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x804",
"Unit": "M2M"
},
{
"BriefDescription": "M2M Writes Issued to iMC : Non-Inclusive - Ch1",
"Counter": "0,1,2,3",
"EventCode": "0x38",
"EventName": "UNC_M2M_IMC_WRITES.CH1_NI",
"Experimental": "1",
"PerPkg": "1",
"Unit": "M2M"
},
{
"BriefDescription": "M2M Writes Issued to iMC : Non-Inclusive Miss - Ch1",
"Counter": "0,1,2,3",
"EventCode": "0x38",
"EventName": "UNC_M2M_IMC_WRITES.CH1_NI_MISS",
"Experimental": "1",
"PerPkg": "1",
"Unit": "M2M"
},
{
"BriefDescription": "M2M Writes Issued to iMC : Partial Non-ISOCH - Ch1",
"Counter": "0,1,2,3",
"EventCode": "0x38",
"EventName": "UNC_M2M_IMC_WRITES.CH1_PARTIAL",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x802",
"Unit": "M2M"
},
{
"BriefDescription": "M2M Writes Issued to iMC : ISOCH Partial - Ch1",
"Counter": "0,1,2,3",
"EventCode": "0x38",
"EventName": "UNC_M2M_IMC_WRITES.CH1_PARTIAL_ISOCH",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x808",
"Unit": "M2M"
},
{
"BriefDescription": "M2M Writes Issued to iMC : DDR, acting as Cache - Ch1",
"Counter": "0,1,2,3",
"EventCode": "0x38",
"EventName": "UNC_M2M_IMC_WRITES.CH1_TO_DDR_AS_CACHE",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x840",
"Unit": "M2M"
},
{
"BriefDescription": "M2M Writes Issued to iMC : DDR - Ch1",
"Counter": "0,1,2,3",
"EventCode": "0x38",
"EventName": "UNC_M2M_IMC_WRITES.CH1_TO_DDR_AS_MEM",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x820",
"Unit": "M2M"
},
{
"BriefDescription": "M2M Writes Issued to iMC : PMM - Ch1",
"Counter": "0,1,2,3",
"EventCode": "0x38",
"EventName": "UNC_M2M_IMC_WRITES.CH1_TO_PMM",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "M2M Writes Issued to iMC : PMM - Ch1 : Counts all PMM dimm writes requests(full line and partial) sent from M2M to iMC",
"UMask": "0x880",
"Unit": "M2M"
},
{
"BriefDescription": "M2M Writes Issued to iMC : From TGR - All Channels",
"Counter": "0,1,2,3",
"EventCode": "0x38",
"EventName": "UNC_M2M_IMC_WRITES.FROM_TGR",
"Experimental": "1",
"PerPkg": "1",
"Unit": "M2M"
},
{
"BriefDescription": "M2M Writes Issued to iMC : Full Line Non-ISOCH - All Channels",
"Counter": "0,1,2,3",
"EventCode": "0x38",
"EventName": "UNC_M2M_IMC_WRITES.FULL",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x1c01",
"Unit": "M2M"
},
{
"BriefDescription": "M2M Writes Issued to iMC : ISOCH Full Line - All Channels",
"Counter": "0,1,2,3",
"EventCode": "0x38",
"EventName": "UNC_M2M_IMC_WRITES.FULL_ISOCH",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x1c04",
"Unit": "M2M"
},
{
"BriefDescription": "M2M Writes Issued to iMC : Non-Inclusive - All Channels",
"Counter": "0,1,2,3",
"EventCode": "0x38",
"EventName": "UNC_M2M_IMC_WRITES.NI",
"Experimental": "1",
"PerPkg": "1",
"Unit": "M2M"
},
{
"BriefDescription": "M2M Writes Issued to iMC : Non-Inclusive Miss - All Channels",
"Counter": "0,1,2,3",
"EventCode": "0x38",
"EventName": "UNC_M2M_IMC_WRITES.NI_MISS",
"Experimental": "1",
"PerPkg": "1",
"Unit": "M2M"
},
{
"BriefDescription": "M2M Writes Issued to iMC : Partial Non-ISOCH - All Channels",
"Counter": "0,1,2,3",
"EventCode": "0x38",
"EventName": "UNC_M2M_IMC_WRITES.PARTIAL",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x1c02",
"Unit": "M2M"
},
{
"BriefDescription": "M2M Writes Issued to iMC : ISOCH Partial - All Channels",
"Counter": "0,1,2,3",
"EventCode": "0x38",
"EventName": "UNC_M2M_IMC_WRITES.PARTIAL_ISOCH",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x1c08",
"Unit": "M2M"
},
{
"BriefDescription": "M2M Writes Issued to iMC : DDR, acting as Cache - All Channels",
"Counter": "0,1,2,3",
"EventCode": "0x38",
"EventName": "UNC_M2M_IMC_WRITES.TO_DDR_AS_CACHE",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x1c40",
"Unit": "M2M"
},
{
"BriefDescription": "M2M Writes Issued to iMC : DDR - All Channels",
"Counter": "0,1,2,3",
"EventCode": "0x38",
"EventName": "UNC_M2M_IMC_WRITES.TO_DDR_AS_MEM",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x1c20",
"Unit": "M2M"
},
{
"BriefDescription": "M2M Writes Issued to iMC : PMM - All Channels",
"Counter": "0,1,2,3",
"EventCode": "0x38",
"EventName": "UNC_M2M_IMC_WRITES.TO_PMM",
"PerPkg": "1",
"UMask": "0x1c80",
"Unit": "M2M"
},
{
"BriefDescription": "Write Tracker Inserts",
"Counter": "0,1,2,3",
"EventCode": "0x64",
"EventName": "UNC_M2M_MIRR_WRQ_INSERTS",
"Experimental": "1",
"PerPkg": "1",
"Unit": "M2M"
},
{
"BriefDescription": "Write Tracker Occupancy",
"Counter": "0,1,2,3",
"EventCode": "0x65",
"EventName": "UNC_M2M_MIRR_WRQ_OCCUPANCY",
"Experimental": "1",
"PerPkg": "1",
"Unit": "M2M"
},
{
"BriefDescription": "Miscellaneous Events (mostly from MS2IDI) : Number of cycles MBE is high for MS2IDI0",
"Counter": "0,1,2,3",
"EventCode": "0xE6",
"EventName": "UNC_M2M_MISC_EXTERNAL.MBE_INST0",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "Miscellaneous Events (mostly from MS2IDI) : Number of cycles MBE is high for MS2IDI1",
"Counter": "0,1,2,3",
"EventCode": "0xE6",
"EventName": "UNC_M2M_MISC_EXTERNAL.MBE_INST1",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "Number Packet Header Matches : MC Match",
"Counter": "0,1,2,3",
"EventCode": "0x4C",
"EventName": "UNC_M2M_PKT_MATCH.MC",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "Number Packet Header Matches : Mesh Match",
"Counter": "0,1,2,3",
"EventCode": "0x4C",
"EventName": "UNC_M2M_PKT_MATCH.MESH",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "UNC_M2M_PREFCAM_CIS_DROPS",
"Counter": "0,1,2,3",
"EventCode": "0x73",
"EventName": "UNC_M2M_PREFCAM_CIS_DROPS",
"Experimental": "1",
"PerPkg": "1",
"Unit": "M2M"
},
{
"BriefDescription": "Prefetch CAM Cycles Full : All Channels",
"Counter": "0,1,2,3",
"EventCode": "0x6B",
"EventName": "UNC_M2M_PREFCAM_CYCLES_FULL.ALLCH",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x7",
"Unit": "M2M"
},
{
"BriefDescription": "Prefetch CAM Cycles Full : Channel 0",
"Counter": "0,1,2,3",
"EventCode": "0x6B",
"EventName": "UNC_M2M_PREFCAM_CYCLES_FULL.CH0",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "Prefetch CAM Cycles Full : Channel 1",
"Counter": "0,1,2,3",
"EventCode": "0x6B",
"EventName": "UNC_M2M_PREFCAM_CYCLES_FULL.CH1",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "Prefetch CAM Cycles Full : Channel 2",
"Counter": "0,1,2,3",
"EventCode": "0x6B",
"EventName": "UNC_M2M_PREFCAM_CYCLES_FULL.CH2",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "M2M"
},
{
"BriefDescription": "Prefetch CAM Cycles Not Empty : All Channels",
"Counter": "0,1,2,3",
"EventCode": "0x6C",
"EventName": "UNC_M2M_PREFCAM_CYCLES_NE.ALLCH",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x7",
"Unit": "M2M"
},
{
"BriefDescription": "Prefetch CAM Cycles Not Empty : Channel 0",
"Counter": "0,1,2,3",
"EventCode": "0x6C",
"EventName": "UNC_M2M_PREFCAM_CYCLES_NE.CH0",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "Prefetch CAM Cycles Not Empty : Channel 1",
"Counter": "0,1,2,3",
"EventCode": "0x6C",
"EventName": "UNC_M2M_PREFCAM_CYCLES_NE.CH1",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "Prefetch CAM Cycles Not Empty : Channel 2",
"Counter": "0,1,2,3",
"EventCode": "0x6C",
"EventName": "UNC_M2M_PREFCAM_CYCLES_NE.CH2",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "M2M"
},
{
"BriefDescription": "Prefetch CAM Deallocs",
"Counter": "0,1,2,3",
"EventCode": "0x6E",
"EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH0_HITA0_INVAL",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "Prefetch CAM Deallocs",
"Counter": "0,1,2,3",
"EventCode": "0x6E",
"EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH0_HITA1_INVAL",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "Prefetch CAM Deallocs",
"Counter": "0,1,2,3",
"EventCode": "0x6E",
"EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH0_MISS_INVAL",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "M2M"
},
{
"BriefDescription": "Prefetch CAM Deallocs",
"Counter": "0,1,2,3",
"EventCode": "0x6E",
"EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH0_RSP_PDRESET",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "M2M"
},
{
"BriefDescription": "Prefetch CAM Deallocs",
"Counter": "0,1,2,3",
"EventCode": "0x6E",
"EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH1_HITA0_INVAL",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "M2M"
},
{
"BriefDescription": "Prefetch CAM Deallocs",
"Counter": "0,1,2,3",
"EventCode": "0x6E",
"EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH1_HITA1_INVAL",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "M2M"
},
{
"BriefDescription": "Prefetch CAM Deallocs",
"Counter": "0,1,2,3",
"EventCode": "0x6E",
"EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH1_MISS_INVAL",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x40",
"Unit": "M2M"
},
{
"BriefDescription": "Prefetch CAM Deallocs",
"Counter": "0,1,2,3",
"EventCode": "0x6E",
"EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH1_RSP_PDRESET",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x80",
"Unit": "M2M"
},
{
"BriefDescription": "Prefetch CAM Deallocs",
"Counter": "0,1,2,3",
"EventCode": "0x6E",
"EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH2_HITA0_INVAL",
"Experimental": "1",
"PerPkg": "1",
"Unit": "M2M"
},
{
"BriefDescription": "Prefetch CAM Deallocs",
"Counter": "0,1,2,3",
"EventCode": "0x6E",
"EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH2_HITA1_INVAL",
"Experimental": "1",
"PerPkg": "1",
"Unit": "M2M"
},
{
"BriefDescription": "Prefetch CAM Deallocs",
"Counter": "0,1,2,3",
"EventCode": "0x6E",
"EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH2_MISS_INVAL",
"Experimental": "1",
"PerPkg": "1",
"Unit": "M2M"
},
{
"BriefDescription": "Prefetch CAM Deallocs",
"Counter": "0,1,2,3",
"EventCode": "0x6E",
"EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH2_RSP_PDRESET",
"Experimental": "1",
"PerPkg": "1",
"Unit": "M2M"
},
{
"BriefDescription": "Data Prefetches Dropped : UPI - Ch 0",
"Counter": "0,1,2,3",
"EventCode": "0x6F",
"EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.CH0_UPI",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "Data Prefetches Dropped : XPT - Ch 0",
"Counter": "0,1,2,3",
"EventCode": "0x6F",
"EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.CH0_XPT",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "Data Prefetches Dropped : UPI - Ch 1",
"Counter": "0,1,2,3",
"EventCode": "0x6F",
"EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.CH1_UPI",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "M2M"
},
{
"BriefDescription": "Data Prefetches Dropped : XPT - Ch 1",
"Counter": "0,1,2,3",
"EventCode": "0x6F",
"EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.CH1_XPT",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "M2M"
},
{
"BriefDescription": "Data Prefetches Dropped : UPI - Ch 2",
"Counter": "0,1,2,3",
"EventCode": "0x6F",
"EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.CH2_UPI",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "M2M"
},
{
"BriefDescription": "Data Prefetches Dropped : XPT - Ch 2",
"Counter": "0,1,2,3",
"EventCode": "0x6F",
"EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.CH2_XPT",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "M2M"
},
{
"BriefDescription": "Data Prefetches Dropped : UPI - All Channels",
"Counter": "0,1,2,3",
"EventCode": "0x6f",
"EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.UPI_ALLCH",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x2a",
"Unit": "M2M"
},
{
"BriefDescription": "Data Prefetches Dropped : XPT - All Channels",
"Counter": "0,1,2,3",
"EventCode": "0x6f",
"EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.XPT_ALLCH",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x15",
"Unit": "M2M"
},
{
"BriefDescription": "Demands Merged with CAMed Prefetches : XPT & UPI- Ch 0",
"Counter": "0,1,2,3",
"EventCode": "0x74",
"EventName": "UNC_M2M_PREFCAM_DEMAND_MERGE.CH0_XPTUPI",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Demands Merged with CAMed Prefetches : XPT & UPI - Ch 0",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "Demands Merged with CAMed Prefetches : XPT & UPI - Ch 1",
"Counter": "0,1,2,3",
"EventCode": "0x74",
"EventName": "UNC_M2M_PREFCAM_DEMAND_MERGE.CH1_XPTUPI",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Demands Merged with CAMed Prefetches : XPT & UPI- Ch 1",
"UMask": "0x4",
"Unit": "M2M"
},
{
"BriefDescription": "Demands Merged with CAMed Prefetches : XPT & UPI- Ch 2",
"Counter": "0,1,2,3",
"EventCode": "0x74",
"EventName": "UNC_M2M_PREFCAM_DEMAND_MERGE.CH2_XPTUPI",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Demands Merged with CAMed Prefetches : XPT & UPI - Ch 2",
"UMask": "0x10",
"Unit": "M2M"
},
{
"BriefDescription": "Demands Merged with CAMed Prefetches : XPT & UPI- All Channels",
"Counter": "0,1,2,3",
"EventCode": "0x74",
"EventName": "UNC_M2M_PREFCAM_DEMAND_MERGE.XPTUPI_ALLCH",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Demands Merged with CAMed Prefetches : XPT & UPI - All Channels",
"UMask": "0x15",
"Unit": "M2M"
},
{
"BriefDescription": "Demands Not Merged with CAMed Prefetches : XPT & UPI - Ch 0",
"Counter": "0,1,2,3",
"EventCode": "0x75",
"EventName": "UNC_M2M_PREFCAM_DEMAND_NO_MERGE.CH0_XPTUPI",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Demands Not Merged with CAMed Prefetches : XPT & UPI- Ch 0",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "Demands Not Merged with CAMed Prefetches : XPT & UPI - Ch 1",
"Counter": "0,1,2,3",
"EventCode": "0x75",
"EventName": "UNC_M2M_PREFCAM_DEMAND_NO_MERGE.CH1_XPTUPI",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Demands Not Merged with CAMed Prefetches : XPT & UPI- Ch 1",
"UMask": "0x4",
"Unit": "M2M"
},
{
"BriefDescription": "Demands Not Merged with CAMed Prefetches : XPT & UPI - Ch 2",
"Counter": "0,1,2,3",
"EventCode": "0x75",
"EventName": "UNC_M2M_PREFCAM_DEMAND_NO_MERGE.CH2_XPTUPI",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "M2M"
},
{
"BriefDescription": "Demands Not Merged with CAMed Prefetches : XPT & UPI - All Channels",
"Counter": "0,1,2,3",
"EventCode": "0x75",
"EventName": "UNC_M2M_PREFCAM_DEMAND_NO_MERGE.XPTUPI_ALLCH",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x15",
"Unit": "M2M"
},
{
"BriefDescription": "Data Prefetches Dropped Ch0 - Reasons",
"Counter": "0,1,2,3",
"EventCode": "0x70",
"EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.ERRORBLK_RxC",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "M2M"
},
{
"BriefDescription": "Data Prefetches Dropped Ch0 - Reasons",
"Counter": "0,1,2,3",
"EventCode": "0x70",
"EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.NOT_PF_SAD_REGION",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "Data Prefetches Dropped Ch0 - Reasons",
"Counter": "0,1,2,3",
"EventCode": "0x70",
"EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.PF_AD_CRD",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "M2M"
},
{
"BriefDescription": "Data Prefetches Dropped Ch0 - Reasons",
"Counter": "0,1,2,3",
"EventCode": "0x70",
"EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.PF_CAM_FULL",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x40",
"Unit": "M2M"
},
{
"BriefDescription": "Data Prefetches Dropped Ch0 - Reasons",
"Counter": "0,1,2,3",
"EventCode": "0x70",
"EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.PF_CAM_HIT",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "M2M"
},
{
"BriefDescription": "Data Prefetches Dropped Ch0 - Reasons",
"Counter": "0,1,2,3",
"EventCode": "0x70",
"EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.PF_SECURE_DROP",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "Data Prefetches Dropped Ch0 - Reasons",
"Counter": "0,1,2,3",
"EventCode": "0x70",
"EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.RPQ_PROXY",
"Experimental": "1",
"PerPkg": "1",
"Unit": "M2M"
},
{
"BriefDescription": "Data Prefetches Dropped Ch0 - Reasons",
"Counter": "0,1,2,3",
"EventCode": "0x70",
"EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.STOP_B2B",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "M2M"
},
{
"BriefDescription": "Data Prefetches Dropped Ch0 - Reasons",
"Counter": "0,1,2,3",
"EventCode": "0x70",
"EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.UPI_THRESH",
"Experimental": "1",
"PerPkg": "1",
"Unit": "M2M"
},
{
"BriefDescription": "Data Prefetches Dropped Ch0 - Reasons",
"Counter": "0,1,2,3",
"EventCode": "0x70",
"EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.WPQ_PROXY",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x80",
"Unit": "M2M"
},
{
"BriefDescription": "Data Prefetches Dropped Ch0 - Reasons",
"Counter": "0,1,2,3",
"EventCode": "0x70",
"EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.XPT_THRESH",
"Experimental": "1",
"PerPkg": "1",
"Unit": "M2M"
},
{
"BriefDescription": "Data Prefetches Dropped Ch1 - Reasons",
"Counter": "0,1,2,3",
"EventCode": "0x71",
"EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.ERRORBLK_RxC",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "M2M"
},
{
"BriefDescription": "Data Prefetches Dropped Ch1 - Reasons",
"Counter": "0,1,2,3",
"EventCode": "0x71",
"EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.NOT_PF_SAD_REGION",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "Data Prefetches Dropped Ch1 - Reasons",
"Counter": "0,1,2,3",
"EventCode": "0x71",
"EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.PF_AD_CRD",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "M2M"
},
{
"BriefDescription": "Data Prefetches Dropped Ch1 - Reasons",
"Counter": "0,1,2,3",
"EventCode": "0x71",
"EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.PF_CAM_FULL",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x40",
"Unit": "M2M"
},
{
"BriefDescription": "Data Prefetches Dropped Ch1 - Reasons",
"Counter": "0,1,2,3",
"EventCode": "0x71",
"EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.PF_CAM_HIT",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "M2M"
},
{
"BriefDescription": "Data Prefetches Dropped Ch1 - Reasons",
"Counter": "0,1,2,3",
"EventCode": "0x71",
"EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.PF_SECURE_DROP",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "Data Prefetches Dropped Ch1 - Reasons",
"Counter": "0,1,2,3",
"EventCode": "0x71",
"EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.RPQ_PROXY",
"Experimental": "1",
"PerPkg": "1",
"Unit": "M2M"
},
{
"BriefDescription": "Data Prefetches Dropped Ch1 - Reasons",
"Counter": "0,1,2,3",
"EventCode": "0x71",
"EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.STOP_B2B",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "M2M"
},
{
"BriefDescription": "Data Prefetches Dropped Ch1 - Reasons",
"Counter": "0,1,2,3",
"EventCode": "0x71",
"EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.UPI_THRESH",
"Experimental": "1",
"PerPkg": "1",
"Unit": "M2M"
},
{
"BriefDescription": "Data Prefetches Dropped Ch1 - Reasons",
"Counter": "0,1,2,3",
"EventCode": "0x71",
"EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.WPQ_PROXY",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x80",
"Unit": "M2M"
},
{
"BriefDescription": "Data Prefetches Dropped Ch1 - Reasons",
"Counter": "0,1,2,3",
"EventCode": "0x71",
"EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.XPT_THRESH",
"Experimental": "1",
"PerPkg": "1",
"Unit": "M2M"
},
{
"BriefDescription": "Data Prefetches Dropped Ch2 - Reasons",
"Counter": "0,1,2,3",
"EventCode": "0x72",
"EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH2.ERRORBLK_RxC",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "M2M"
},
{
"BriefDescription": "Data Prefetches Dropped Ch2 - Reasons",
"Counter": "0,1,2,3",
"EventCode": "0x72",
"EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH2.NOT_PF_SAD_REGION",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "Data Prefetches Dropped Ch2 - Reasons",
"Counter": "0,1,2,3",
"EventCode": "0x72",
"EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH2.PF_AD_CRD",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "M2M"
},
{
"BriefDescription": "Data Prefetches Dropped Ch2 - Reasons",
"Counter": "0,1,2,3",
"EventCode": "0x72",
"EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH2.PF_CAM_FULL",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x40",
"Unit": "M2M"
},
{
"BriefDescription": "Data Prefetches Dropped Ch2 - Reasons",
"Counter": "0,1,2,3",
"EventCode": "0x72",
"EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH2.PF_CAM_HIT",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "M2M"
},
{
"BriefDescription": "Data Prefetches Dropped Ch2 - Reasons",
"Counter": "0,1,2,3",
"EventCode": "0x72",
"EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH2.PF_SECURE_DROP",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "Data Prefetches Dropped Ch2 - Reasons",
"Counter": "0,1,2,3",
"EventCode": "0x72",
"EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH2.RPQ_PROXY",
"Experimental": "1",
"PerPkg": "1",
"Unit": "M2M"
},
{
"BriefDescription": "Data Prefetches Dropped Ch2 - Reasons",
"Counter": "0,1,2,3",
"EventCode": "0x72",
"EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH2.STOP_B2B",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "M2M"
},
{
"BriefDescription": "Data Prefetches Dropped Ch2 - Reasons",
"Counter": "0,1,2,3",
"EventCode": "0x72",
"EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH2.UPI_THRESH",
"Experimental": "1",
"PerPkg": "1",
"Unit": "M2M"
},
{
"BriefDescription": "Data Prefetches Dropped Ch2 - Reasons",
"Counter": "0,1,2,3",
"EventCode": "0x72",
"EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH2.WPQ_PROXY",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x80",
"Unit": "M2M"
},
{
"BriefDescription": "Data Prefetches Dropped Ch2 - Reasons",
"Counter": "0,1,2,3",
"EventCode": "0x72",
"EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH2.XPT_THRESH",
"Experimental": "1",
"PerPkg": "1",
"Unit": "M2M"
},
{
"BriefDescription": "Prefetch CAM Inserts : UPI - Ch 0",
"Counter": "0,1,2,3",
"EventCode": "0x6D",
"EventName": "UNC_M2M_PREFCAM_INSERTS.CH0_UPI",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "Prefetch CAM Inserts : XPT - Ch 0",
"Counter": "0,1,2,3",
"EventCode": "0x6D",
"EventName": "UNC_M2M_PREFCAM_INSERTS.CH0_XPT",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "Prefetch CAM Inserts : UPI - Ch 1",
"Counter": "0,1,2,3",
"EventCode": "0x6D",
"EventName": "UNC_M2M_PREFCAM_INSERTS.CH1_UPI",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "M2M"
},
{
"BriefDescription": "Prefetch CAM Inserts : XPT - Ch 1",
"Counter": "0,1,2,3",
"EventCode": "0x6D",
"EventName": "UNC_M2M_PREFCAM_INSERTS.CH1_XPT",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "M2M"
},
{
"BriefDescription": "Prefetch CAM Inserts : UPI - Ch 2",
"Counter": "0,1,2,3",
"EventCode": "0x6D",
"EventName": "UNC_M2M_PREFCAM_INSERTS.CH2_UPI",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "M2M"
},
{
"BriefDescription": "Prefetch CAM Inserts : XPT - Ch 2",
"Counter": "0,1,2,3",
"EventCode": "0x6D",
"EventName": "UNC_M2M_PREFCAM_INSERTS.CH2_XPT",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "M2M"
},
{
"BriefDescription": "Prefetch CAM Inserts : UPI - All Channels",
"Counter": "0,1,2,3",
"EventCode": "0x6d",
"EventName": "UNC_M2M_PREFCAM_INSERTS.UPI_ALLCH",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x2a",
"Unit": "M2M"
},
{
"BriefDescription": "Prefetch CAM Inserts : XPT - All Channels",
"Counter": "0,1,2,3",
"EventCode": "0x6D",
"EventName": "UNC_M2M_PREFCAM_INSERTS.XPT_ALLCH",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x15",
"Unit": "M2M"
},
{
"BriefDescription": "Prefetch CAM Occupancy : All Channels",
"Counter": "0,1,2,3",
"EventCode": "0x6A",
"EventName": "UNC_M2M_PREFCAM_OCCUPANCY.ALLCH",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x7",
"Unit": "M2M"
},
{
"BriefDescription": "Prefetch CAM Occupancy : Channel 0",
"Counter": "0,1,2,3",
"EventCode": "0x6A",
"EventName": "UNC_M2M_PREFCAM_OCCUPANCY.CH0",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "Prefetch CAM Occupancy : Channel 1",
"Counter": "0,1,2,3",
"EventCode": "0x6A",
"EventName": "UNC_M2M_PREFCAM_OCCUPANCY.CH1",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "Prefetch CAM Occupancy : Channel 2",
"Counter": "0,1,2,3",
"EventCode": "0x6A",
"EventName": "UNC_M2M_PREFCAM_OCCUPANCY.CH2",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "M2M"
},
{
"BriefDescription": ": All Channels",
"Counter": "0,1,2,3",
"EventCode": "0x76",
"EventName": "UNC_M2M_PREFCAM_RESP_MISS.ALLCH",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x7",
"Unit": "M2M"
},
{
"BriefDescription": ": Channel 0",
"Counter": "0,1,2,3",
"EventCode": "0x76",
"EventName": "UNC_M2M_PREFCAM_RESP_MISS.CH0",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": ": Channel 1",
"Counter": "0,1,2,3",
"EventCode": "0x76",
"EventName": "UNC_M2M_PREFCAM_RESP_MISS.CH1",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": ": Channel 2",
"Counter": "0,1,2,3",
"EventCode": "0x76",
"EventName": "UNC_M2M_PREFCAM_RESP_MISS.CH2",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "M2M"
},
{
"BriefDescription": "UNC_M2M_PREFCAM_RxC_CYCLES_NE",
"Counter": "0,1,2,3",
"EventCode": "0x79",
"EventName": "UNC_M2M_PREFCAM_RxC_CYCLES_NE",
"Experimental": "1",
"PerPkg": "1",
"Unit": "M2M"
},
{
"BriefDescription": "UNC_M2M_PREFCAM_RxC_DEALLOCS.1LM_POSTED",
"Counter": "0,1,2,3",
"EventCode": "0x7A",
"EventName": "UNC_M2M_PREFCAM_RxC_DEALLOCS.1LM_POSTED",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "UNC_M2M_PREFCAM_RxC_DEALLOCS.CIS",
"Counter": "0,1,2,3",
"EventCode": "0x7A",
"EventName": "UNC_M2M_PREFCAM_RxC_DEALLOCS.CIS",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "M2M"
},
{
"BriefDescription": "UNC_M2M_PREFCAM_RxC_DEALLOCS.PMM_MEMMODE_ACCEPT",
"Counter": "0,1,2,3",
"EventCode": "0x7A",
"EventName": "UNC_M2M_PREFCAM_RxC_DEALLOCS.PMM_MEMMODE_ACCEPT",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "M2M"
},
{
"BriefDescription": "UNC_M2M_PREFCAM_RxC_DEALLOCS.SQUASHED",
"Counter": "0,1,2,3",
"EventCode": "0x7A",
"EventName": "UNC_M2M_PREFCAM_RxC_DEALLOCS.SQUASHED",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "UNC_M2M_PREFCAM_RxC_INSERTS",
"Counter": "0,1,2,3",
"EventCode": "0x78",
"EventName": "UNC_M2M_PREFCAM_RxC_INSERTS",
"Experimental": "1",
"PerPkg": "1",
"Unit": "M2M"
},
{
"BriefDescription": "UNC_M2M_PREFCAM_RxC_OCCUPANCY",
"Counter": "0,1,2,3",
"EventCode": "0x77",
"EventName": "UNC_M2M_PREFCAM_RxC_OCCUPANCY",
"Experimental": "1",
"PerPkg": "1",
"Unit": "M2M"
},
{
"BriefDescription": "Messages that bounced on the Horizontal Ring. : AD",
"Counter": "0,1,2,3",
"EventCode": "0xAC",
"EventName": "UNC_M2M_RING_BOUNCES_HORZ.AD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Messages that bounced on the Horizontal Ring. : AD : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "Messages that bounced on the Horizontal Ring. : AK",
"Counter": "0,1,2,3",
"EventCode": "0xAC",
"EventName": "UNC_M2M_RING_BOUNCES_HORZ.AK",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Messages that bounced on the Horizontal Ring. : AK : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "Messages that bounced on the Horizontal Ring. : BL",
"Counter": "0,1,2,3",
"EventCode": "0xAC",
"EventName": "UNC_M2M_RING_BOUNCES_HORZ.BL",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Messages that bounced on the Horizontal Ring. : BL : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.",
"UMask": "0x4",
"Unit": "M2M"
},
{
"BriefDescription": "Messages that bounced on the Horizontal Ring. : IV",
"Counter": "0,1,2,3",
"EventCode": "0xAC",
"EventName": "UNC_M2M_RING_BOUNCES_HORZ.IV",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Messages that bounced on the Horizontal Ring. : IV : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.",
"UMask": "0x8",
"Unit": "M2M"
},
{
"BriefDescription": "Messages that bounced on the Vertical Ring. : AD",
"Counter": "0,1,2,3",
"EventCode": "0xAA",
"EventName": "UNC_M2M_RING_BOUNCES_VERT.AD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Messages that bounced on the Vertical Ring. : AD : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "Messages that bounced on the Vertical Ring. : Acknowledgements to core",
"Counter": "0,1,2,3",
"EventCode": "0xAA",
"EventName": "UNC_M2M_RING_BOUNCES_VERT.AK",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Messages that bounced on the Vertical Ring. : Acknowledgements to core : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "Messages that bounced on the Vertical Ring.",
"Counter": "0,1,2,3",
"EventCode": "0xAA",
"EventName": "UNC_M2M_RING_BOUNCES_VERT.AKC",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Messages that bounced on the Vertical Ring. : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
"UMask": "0x10",
"Unit": "M2M"
},
{
"BriefDescription": "Messages that bounced on the Vertical Ring. : Data Responses to core",
"Counter": "0,1,2,3",
"EventCode": "0xAA",
"EventName": "UNC_M2M_RING_BOUNCES_VERT.BL",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Messages that bounced on the Vertical Ring. : Data Responses to core : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
"UMask": "0x4",
"Unit": "M2M"
},
{
"BriefDescription": "Messages that bounced on the Vertical Ring. : Snoops of processor's cache.",
"Counter": "0,1,2,3",
"EventCode": "0xAA",
"EventName": "UNC_M2M_RING_BOUNCES_VERT.IV",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Messages that bounced on the Vertical Ring. : Snoops of processor's cache. : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
"UMask": "0x8",
"Unit": "M2M"
},
{
"BriefDescription": "Sink Starvation on Horizontal Ring : AD",
"Counter": "0,1,2,3",
"EventCode": "0xAD",
"EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.AD",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "Sink Starvation on Horizontal Ring : AK",
"Counter": "0,1,2,3",
"EventCode": "0xAD",
"EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.AK",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "Sink Starvation on Horizontal Ring : Acknowledgements to Agent 1",
"Counter": "0,1,2,3",
"EventCode": "0xAD",
"EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.AK_AG1",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "M2M"
},
{
"BriefDescription": "Sink Starvation on Horizontal Ring : BL",
"Counter": "0,1,2,3",
"EventCode": "0xAD",
"EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.BL",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "M2M"
},
{
"BriefDescription": "Sink Starvation on Horizontal Ring : IV",
"Counter": "0,1,2,3",
"EventCode": "0xAD",
"EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.IV",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "M2M"
},
{
"BriefDescription": "Sink Starvation on Vertical Ring : AD",
"Counter": "0,1,2,3",
"EventCode": "0xAB",
"EventName": "UNC_M2M_RING_SINK_STARVED_VERT.AD",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "Sink Starvation on Vertical Ring : Acknowledgements to core",
"Counter": "0,1,2,3",
"EventCode": "0xAB",
"EventName": "UNC_M2M_RING_SINK_STARVED_VERT.AK",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "Sink Starvation on Vertical Ring",
"Counter": "0,1,2,3",
"EventCode": "0xAB",
"EventName": "UNC_M2M_RING_SINK_STARVED_VERT.AKC",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "M2M"
},
{
"BriefDescription": "Sink Starvation on Vertical Ring : Data Responses to core",
"Counter": "0,1,2,3",
"EventCode": "0xAB",
"EventName": "UNC_M2M_RING_SINK_STARVED_VERT.BL",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "M2M"
},
{
"BriefDescription": "Sink Starvation on Vertical Ring : Snoops of processor's cache.",
"Counter": "0,1,2,3",
"EventCode": "0xAB",
"EventName": "UNC_M2M_RING_SINK_STARVED_VERT.IV",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "M2M"
},
{
"BriefDescription": "Source Throttle",
"Counter": "0,1,2,3",
"EventCode": "0xae",
"EventName": "UNC_M2M_RING_SRC_THRTL",
"Experimental": "1",
"PerPkg": "1",
"Unit": "M2M"
},
{
"BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Regular : Channel 0",
"Counter": "0,1,2,3",
"EventCode": "0x43",
"EventName": "UNC_M2M_RPQ_NO_REG_CRD.CH0",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Regular : Channel 1",
"Counter": "0,1,2,3",
"EventCode": "0x43",
"EventName": "UNC_M2M_RPQ_NO_REG_CRD.CH1",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Regular : Channel 2",
"Counter": "0,1,2,3",
"EventCode": "0x43",
"EventName": "UNC_M2M_RPQ_NO_REG_CRD.CH2",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "M2M"
},
{
"BriefDescription": "M2M->iMC RPQ Cycles w/Credits - PMM : Channel 0",
"Counter": "0,1,2,3",
"EventCode": "0x4F",
"EventName": "UNC_M2M_RPQ_NO_REG_CRD_PMM.CHN0",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "M2M->iMC RPQ Cycles w/Credits - PMM : Channel 1",
"Counter": "0,1,2,3",
"EventCode": "0x4F",
"EventName": "UNC_M2M_RPQ_NO_REG_CRD_PMM.CHN1",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "M2M->iMC RPQ Cycles w/Credits - PMM : Channel 2",
"Counter": "0,1,2,3",
"EventCode": "0x4F",
"EventName": "UNC_M2M_RPQ_NO_REG_CRD_PMM.CHN2",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "M2M"
},
{
"BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Special : Channel 0",
"Counter": "0,1,2,3",
"EventCode": "0x44",
"EventName": "UNC_M2M_RPQ_NO_SPEC_CRD.CH0",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Special : Channel 1",
"Counter": "0,1,2,3",
"EventCode": "0x44",
"EventName": "UNC_M2M_RPQ_NO_SPEC_CRD.CH1",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Special : Channel 2",
"Counter": "0,1,2,3",
"EventCode": "0x44",
"EventName": "UNC_M2M_RPQ_NO_SPEC_CRD.CH2",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "M2M"
},
{
"BriefDescription": "AD Ingress (from CMS) Full",
"Counter": "0,1,2,3",
"EventCode": "0x04",
"EventName": "UNC_M2M_RxC_AD_CYCLES_FULL",
"Experimental": "1",
"PerPkg": "1",
"Unit": "M2M"
},
{
"BriefDescription": "AD Ingress (from CMS) Not Empty",
"Counter": "0,1,2,3",
"EventCode": "0x03",
"EventName": "UNC_M2M_RxC_AD_CYCLES_NE",
"Experimental": "1",
"PerPkg": "1",
"Unit": "M2M"
},
{
"BriefDescription": "AD Ingress (from CMS) Allocations",
"Counter": "0,1,2,3",
"EventCode": "0x01",
"EventName": "UNC_M2M_RxC_AD_INSERTS",
"Experimental": "1",
"PerPkg": "1",
"Unit": "M2M"
},
{
"BriefDescription": "AD Ingress (from CMS) Occupancy",
"Counter": "0,1,2,3",
"EventCode": "0x02",
"EventName": "UNC_M2M_RxC_AD_OCCUPANCY",
"Experimental": "1",
"PerPkg": "1",
"Unit": "M2M"
},
{
"BriefDescription": "AD Ingress (from CMS) Occupancy - Prefetches",
"Counter": "0,1,2,3",
"EventCode": "0x77",
"EventName": "UNC_M2M_RxC_AD_PREF_OCCUPANCY",
"Experimental": "1",
"PerPkg": "1",
"Unit": "M2M"
},
{
"BriefDescription": "AK Egress (to CMS) Allocations",
"Counter": "0,1,2,3",
"EventCode": "0x5C",
"EventName": "UNC_M2M_RxC_AK_WR_CMP",
"Experimental": "1",
"PerPkg": "1",
"Unit": "M2M"
},
{
"BriefDescription": "BL Ingress (from CMS) Full",
"Counter": "0,1,2,3",
"EventCode": "0x08",
"EventName": "UNC_M2M_RxC_BL_CYCLES_FULL",
"Experimental": "1",
"PerPkg": "1",
"Unit": "M2M"
},
{
"BriefDescription": "BL Ingress (from CMS) Not Empty",
"Counter": "0,1,2,3",
"EventCode": "0x07",
"EventName": "UNC_M2M_RxC_BL_CYCLES_NE",
"Experimental": "1",
"PerPkg": "1",
"Unit": "M2M"
},
{
"BriefDescription": "BL Ingress (from CMS) Allocations",
"Counter": "0,1,2,3",
"EventCode": "0x05",
"EventName": "UNC_M2M_RxC_BL_INSERTS",
"Experimental": "1",
"PerPkg": "1",
"Unit": "M2M"
},
{
"BriefDescription": "BL Ingress (from CMS) Occupancy",
"Counter": "0,1,2,3",
"EventCode": "0x06",
"EventName": "UNC_M2M_RxC_BL_OCCUPANCY",
"Experimental": "1",
"PerPkg": "1",
"Unit": "M2M"
},
{
"BriefDescription": "Transgress Injection Starvation : AD - All",
"Counter": "0,1,2,3",
"EventCode": "0xE5",
"EventName": "UNC_M2M_RxR_BUSY_STARVED.AD_ALL",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Injection Starvation : AD - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority : All == Credited + Uncredited",
"UMask": "0x11",
"Unit": "M2M"
},
{
"BriefDescription": "Transgress Injection Starvation : AD - Credited",
"Counter": "0,1,2,3",
"EventCode": "0xE5",
"EventName": "UNC_M2M_RxR_BUSY_STARVED.AD_CRD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Injection Starvation : AD - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority",
"UMask": "0x10",
"Unit": "M2M"
},
{
"BriefDescription": "Transgress Injection Starvation : AD - Uncredited",
"Counter": "0,1,2,3",
"EventCode": "0xE5",
"EventName": "UNC_M2M_RxR_BUSY_STARVED.AD_UNCRD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Injection Starvation : AD - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "Transgress Injection Starvation : BL - All",
"Counter": "0,1,2,3",
"EventCode": "0xE5",
"EventName": "UNC_M2M_RxR_BUSY_STARVED.BL_ALL",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Injection Starvation : BL - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority : All == Credited + Uncredited",
"UMask": "0x44",
"Unit": "M2M"
},
{
"BriefDescription": "Transgress Injection Starvation : BL - Credited",
"Counter": "0,1,2,3",
"EventCode": "0xE5",
"EventName": "UNC_M2M_RxR_BUSY_STARVED.BL_CRD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Injection Starvation : BL - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority",
"UMask": "0x40",
"Unit": "M2M"
},
{
"BriefDescription": "Transgress Injection Starvation : BL - Uncredited",
"Counter": "0,1,2,3",
"EventCode": "0xE5",
"EventName": "UNC_M2M_RxR_BUSY_STARVED.BL_UNCRD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Injection Starvation : BL - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority",
"UMask": "0x4",
"Unit": "M2M"
},
{
"BriefDescription": "Transgress Ingress Bypass : AD - All",
"Counter": "0,1,2,3",
"EventCode": "0xE2",
"EventName": "UNC_M2M_RxR_BYPASS.AD_ALL",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Ingress Bypass : AD - All : Number of packets bypassing the CMS Ingress : All == Credited + Uncredited",
"UMask": "0x11",
"Unit": "M2M"
},
{
"BriefDescription": "Transgress Ingress Bypass : AD - Credited",
"Counter": "0,1,2,3",
"EventCode": "0xE2",
"EventName": "UNC_M2M_RxR_BYPASS.AD_CRD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Ingress Bypass : AD - Credited : Number of packets bypassing the CMS Ingress",
"UMask": "0x10",
"Unit": "M2M"
},
{
"BriefDescription": "Transgress Ingress Bypass : AD - Uncredited",
"Counter": "0,1,2,3",
"EventCode": "0xE2",
"EventName": "UNC_M2M_RxR_BYPASS.AD_UNCRD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Ingress Bypass : AD - Uncredited : Number of packets bypassing the CMS Ingress",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "Transgress Ingress Bypass : AK",
"Counter": "0,1,2,3",
"EventCode": "0xE2",
"EventName": "UNC_M2M_RxR_BYPASS.AK",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Ingress Bypass : AK : Number of packets bypassing the CMS Ingress",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "Transgress Ingress Bypass : AKC - Uncredited",
"Counter": "0,1,2,3",
"EventCode": "0xE2",
"EventName": "UNC_M2M_RxR_BYPASS.AKC_UNCRD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Ingress Bypass : AKC - Uncredited : Number of packets bypassing the CMS Ingress",
"UMask": "0x80",
"Unit": "M2M"
},
{
"BriefDescription": "Transgress Ingress Bypass : BL - All",
"Counter": "0,1,2,3",
"EventCode": "0xE2",
"EventName": "UNC_M2M_RxR_BYPASS.BL_ALL",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Ingress Bypass : BL - All : Number of packets bypassing the CMS Ingress : All == Credited + Uncredited",
"UMask": "0x44",
"Unit": "M2M"
},
{
"BriefDescription": "Transgress Ingress Bypass : BL - Credited",
"Counter": "0,1,2,3",
"EventCode": "0xE2",
"EventName": "UNC_M2M_RxR_BYPASS.BL_CRD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Ingress Bypass : BL - Credited : Number of packets bypassing the CMS Ingress",
"UMask": "0x40",
"Unit": "M2M"
},
{
"BriefDescription": "Transgress Ingress Bypass : BL - Uncredited",
"Counter": "0,1,2,3",
"EventCode": "0xE2",
"EventName": "UNC_M2M_RxR_BYPASS.BL_UNCRD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Ingress Bypass : BL - Uncredited : Number of packets bypassing the CMS Ingress",
"UMask": "0x4",
"Unit": "M2M"
},
{
"BriefDescription": "Transgress Ingress Bypass : IV",
"Counter": "0,1,2,3",
"EventCode": "0xE2",
"EventName": "UNC_M2M_RxR_BYPASS.IV",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Ingress Bypass : IV : Number of packets bypassing the CMS Ingress",
"UMask": "0x8",
"Unit": "M2M"
},
{
"BriefDescription": "Transgress Injection Starvation : AD - All",
"Counter": "0,1,2,3",
"EventCode": "0xE3",
"EventName": "UNC_M2M_RxR_CRD_STARVED.AD_ALL",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Injection Starvation : AD - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit. : All == Credited + Uncredited",
"UMask": "0x11",
"Unit": "M2M"
},
{
"BriefDescription": "Transgress Injection Starvation : AD - Credited",
"Counter": "0,1,2,3",
"EventCode": "0xE3",
"EventName": "UNC_M2M_RxR_CRD_STARVED.AD_CRD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Injection Starvation : AD - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
"UMask": "0x10",
"Unit": "M2M"
},
{
"BriefDescription": "Transgress Injection Starvation : AD - Uncredited",
"Counter": "0,1,2,3",
"EventCode": "0xE3",
"EventName": "UNC_M2M_RxR_CRD_STARVED.AD_UNCRD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Injection Starvation : AD - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "Transgress Injection Starvation : AK",
"Counter": "0,1,2,3",
"EventCode": "0xE3",
"EventName": "UNC_M2M_RxR_CRD_STARVED.AK",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Injection Starvation : AK : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "Transgress Injection Starvation : BL - All",
"Counter": "0,1,2,3",
"EventCode": "0xE3",
"EventName": "UNC_M2M_RxR_CRD_STARVED.BL_ALL",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Injection Starvation : BL - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit. : All == Credited + Uncredited",
"UMask": "0x44",
"Unit": "M2M"
},
{
"BriefDescription": "Transgress Injection Starvation : BL - Credited",
"Counter": "0,1,2,3",
"EventCode": "0xE3",
"EventName": "UNC_M2M_RxR_CRD_STARVED.BL_CRD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Injection Starvation : BL - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
"UMask": "0x40",
"Unit": "M2M"
},
{
"BriefDescription": "Transgress Injection Starvation : BL - Uncredited",
"Counter": "0,1,2,3",
"EventCode": "0xE3",
"EventName": "UNC_M2M_RxR_CRD_STARVED.BL_UNCRD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Injection Starvation : BL - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
"UMask": "0x4",
"Unit": "M2M"
},
{
"BriefDescription": "Transgress Injection Starvation : IFV - Credited",
"Counter": "0,1,2,3",
"EventCode": "0xE3",
"EventName": "UNC_M2M_RxR_CRD_STARVED.IFV",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Injection Starvation : IFV - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
"UMask": "0x80",
"Unit": "M2M"
},
{
"BriefDescription": "Transgress Injection Starvation : IV",
"Counter": "0,1,2,3",
"EventCode": "0xE3",
"EventName": "UNC_M2M_RxR_CRD_STARVED.IV",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Injection Starvation : IV : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
"UMask": "0x8",
"Unit": "M2M"
},
{
"BriefDescription": "Transgress Injection Starvation",
"Counter": "0,1,2,3",
"EventCode": "0xe4",
"EventName": "UNC_M2M_RxR_CRD_STARVED_1",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Injection Starvation : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
"Unit": "M2M"
},
{
"BriefDescription": "Transgress Ingress Allocations : AD - All",
"Counter": "0,1,2,3",
"EventCode": "0xE1",
"EventName": "UNC_M2M_RxR_INSERTS.AD_ALL",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Ingress Allocations : AD - All : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited",
"UMask": "0x11",
"Unit": "M2M"
},
{
"BriefDescription": "Transgress Ingress Allocations : AD - Credited",
"Counter": "0,1,2,3",
"EventCode": "0xE1",
"EventName": "UNC_M2M_RxR_INSERTS.AD_CRD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Ingress Allocations : AD - Credited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
"UMask": "0x10",
"Unit": "M2M"
},
{
"BriefDescription": "Transgress Ingress Allocations : AD - Uncredited",
"Counter": "0,1,2,3",
"EventCode": "0xE1",
"EventName": "UNC_M2M_RxR_INSERTS.AD_UNCRD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Ingress Allocations : AD - Uncredited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "Transgress Ingress Allocations : AK",
"Counter": "0,1,2,3",
"EventCode": "0xE1",
"EventName": "UNC_M2M_RxR_INSERTS.AK",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Ingress Allocations : AK : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "Transgress Ingress Allocations : AKC - Uncredited",
"Counter": "0,1,2,3",
"EventCode": "0xE1",
"EventName": "UNC_M2M_RxR_INSERTS.AKC_UNCRD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Ingress Allocations : AKC - Uncredited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
"UMask": "0x80",
"Unit": "M2M"
},
{
"BriefDescription": "Transgress Ingress Allocations : BL - All",
"Counter": "0,1,2,3",
"EventCode": "0xE1",
"EventName": "UNC_M2M_RxR_INSERTS.BL_ALL",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Ingress Allocations : BL - All : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited",
"UMask": "0x44",
"Unit": "M2M"
},
{
"BriefDescription": "Transgress Ingress Allocations : BL - Credited",
"Counter": "0,1,2,3",
"EventCode": "0xE1",
"EventName": "UNC_M2M_RxR_INSERTS.BL_CRD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Ingress Allocations : BL - Credited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
"UMask": "0x40",
"Unit": "M2M"
},
{
"BriefDescription": "Transgress Ingress Allocations : BL - Uncredited",
"Counter": "0,1,2,3",
"EventCode": "0xE1",
"EventName": "UNC_M2M_RxR_INSERTS.BL_UNCRD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Ingress Allocations : BL - Uncredited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
"UMask": "0x4",
"Unit": "M2M"
},
{
"BriefDescription": "Transgress Ingress Allocations : IV",
"Counter": "0,1,2,3",
"EventCode": "0xE1",
"EventName": "UNC_M2M_RxR_INSERTS.IV",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Ingress Allocations : IV : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
"UMask": "0x8",
"Unit": "M2M"
},
{
"BriefDescription": "Transgress Ingress Occupancy : AD - All",
"Counter": "0,1,2,3",
"EventCode": "0xE0",
"EventName": "UNC_M2M_RxR_OCCUPANCY.AD_ALL",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Ingress Occupancy : AD - All : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited",
"UMask": "0x11",
"Unit": "M2M"
},
{
"BriefDescription": "Transgress Ingress Occupancy : AD - Credited",
"Counter": "0,1,2,3",
"EventCode": "0xE0",
"EventName": "UNC_M2M_RxR_OCCUPANCY.AD_CRD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Ingress Occupancy : AD - Credited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
"UMask": "0x10",
"Unit": "M2M"
},
{
"BriefDescription": "Transgress Ingress Occupancy : AD - Uncredited",
"Counter": "0,1,2,3",
"EventCode": "0xE0",
"EventName": "UNC_M2M_RxR_OCCUPANCY.AD_UNCRD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Ingress Occupancy : AD - Uncredited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "Transgress Ingress Occupancy : AK",
"Counter": "0,1,2,3",
"EventCode": "0xE0",
"EventName": "UNC_M2M_RxR_OCCUPANCY.AK",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Ingress Occupancy : AK : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "Transgress Ingress Occupancy : AKC - Uncredited",
"Counter": "0,1,2,3",
"EventCode": "0xE0",
"EventName": "UNC_M2M_RxR_OCCUPANCY.AKC_UNCRD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Ingress Occupancy : AKC - Uncredited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
"UMask": "0x80",
"Unit": "M2M"
},
{
"BriefDescription": "Transgress Ingress Occupancy : BL - All",
"Counter": "0,1,2,3",
"EventCode": "0xE0",
"EventName": "UNC_M2M_RxR_OCCUPANCY.BL_ALL",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Ingress Occupancy : BL - All : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited",
"UMask": "0x44",
"Unit": "M2M"
},
{
"BriefDescription": "Transgress Ingress Occupancy : BL - Credited",
"Counter": "0,1,2,3",
"EventCode": "0xE0",
"EventName": "UNC_M2M_RxR_OCCUPANCY.BL_CRD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Ingress Occupancy : BL - Credited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
"UMask": "0x20",
"Unit": "M2M"
},
{
"BriefDescription": "Transgress Ingress Occupancy : BL - Uncredited",
"Counter": "0,1,2,3",
"EventCode": "0xE0",
"EventName": "UNC_M2M_RxR_OCCUPANCY.BL_UNCRD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Ingress Occupancy : BL - Uncredited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
"UMask": "0x4",
"Unit": "M2M"
},
{
"BriefDescription": "Transgress Ingress Occupancy : IV",
"Counter": "0,1,2,3",
"EventCode": "0xE0",
"EventName": "UNC_M2M_RxR_OCCUPANCY.IV",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Ingress Occupancy : IV : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
"UMask": "0x8",
"Unit": "M2M"
},
{
"BriefDescription": "UNC_M2M_SCOREBOARD_AD_RETRY_ACCEPTS",
"Counter": "0,1,2,3",
"EventCode": "0x33",
"EventName": "UNC_M2M_SCOREBOARD_AD_RETRY_ACCEPTS",
"Experimental": "1",
"PerPkg": "1",
"Unit": "M2M"
},
{
"BriefDescription": "UNC_M2M_SCOREBOARD_AD_RETRY_REJECTS",
"Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "UNC_M2M_SCOREBOARD_AD_RETRY_REJECTS",
"Experimental": "1",
"PerPkg": "1",
"Unit": "M2M"
},
{
"BriefDescription": "Retry - Mem Mirroring Mode",
"Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_M2M_SCOREBOARD_BL_RETRY_ACCEPTS",
"Experimental": "1",
"PerPkg": "1",
"Unit": "M2M"
},
{
"BriefDescription": "Retry - Mem Mirroring Mode",
"Counter": "0,1,2,3",
"EventCode": "0x36",
"EventName": "UNC_M2M_SCOREBOARD_BL_RETRY_REJECTS",
"Experimental": "1",
"PerPkg": "1",
"Unit": "M2M"
},
{
"BriefDescription": "Scoreboard Accepts",
"Counter": "0,1,2,3",
"EventCode": "0x2F",
"EventName": "UNC_M2M_SCOREBOARD_RD_ACCEPTS",
"Experimental": "1",
"PerPkg": "1",
"Unit": "M2M"
},
{
"BriefDescription": "Scoreboard Rejects",
"Counter": "0,1,2,3",
"EventCode": "0x30",
"EventName": "UNC_M2M_SCOREBOARD_RD_REJECTS",
"Experimental": "1",
"PerPkg": "1",
"Unit": "M2M"
},
{
"BriefDescription": "Scoreboard Accepts",
"Counter": "0,1,2,3",
"EventCode": "0x31",
"EventName": "UNC_M2M_SCOREBOARD_WR_ACCEPTS",
"Experimental": "1",
"PerPkg": "1",
"Unit": "M2M"
},
{
"BriefDescription": "Scoreboard Rejects",
"Counter": "0,1,2,3",
"EventCode": "0x32",
"EventName": "UNC_M2M_SCOREBOARD_WR_REJECTS",
"Experimental": "1",
"PerPkg": "1",
"Unit": "M2M"
},
{
"BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 0",
"Counter": "0,1,2,3",
"EventCode": "0xD0",
"EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR0",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 0 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 1",
"Counter": "0,1,2,3",
"EventCode": "0xD0",
"EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR1",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 1 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 2",
"Counter": "0,1,2,3",
"EventCode": "0xD0",
"EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR2",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 2 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x4",
"Unit": "M2M"
},
{
"BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 3",
"Counter": "0,1,2,3",
"EventCode": "0xD0",
"EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR3",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 3 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x8",
"Unit": "M2M"
},
{
"BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 4",
"Counter": "0,1,2,3",
"EventCode": "0xD0",
"EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR4",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 4 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x10",
"Unit": "M2M"
},
{
"BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 5",
"Counter": "0,1,2,3",
"EventCode": "0xD0",
"EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR5",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 5 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x20",
"Unit": "M2M"
},
{
"BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 6",
"Counter": "0,1,2,3",
"EventCode": "0xD0",
"EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR6",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 6 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x40",
"Unit": "M2M"
},
{
"BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 7",
"Counter": "0,1,2,3",
"EventCode": "0xD0",
"EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR7",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 7 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x80",
"Unit": "M2M"
},
{
"BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 0",
"Counter": "0,1,2,3",
"EventCode": "0xD2",
"EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR0",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 0 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 1",
"Counter": "0,1,2,3",
"EventCode": "0xD2",
"EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR1",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 1 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 2",
"Counter": "0,1,2,3",
"EventCode": "0xD2",
"EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR2",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 2 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x4",
"Unit": "M2M"
},
{
"BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 3",
"Counter": "0,1,2,3",
"EventCode": "0xD2",
"EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR3",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 3 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x8",
"Unit": "M2M"
},
{
"BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 4",
"Counter": "0,1,2,3",
"EventCode": "0xD2",
"EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR4",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 4 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x10",
"Unit": "M2M"
},
{
"BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 5",
"Counter": "0,1,2,3",
"EventCode": "0xD2",
"EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR5",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 5 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x20",
"Unit": "M2M"
},
{
"BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 6",
"Counter": "0,1,2,3",
"EventCode": "0xD2",
"EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR6",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 6 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x40",
"Unit": "M2M"
},
{
"BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 7",
"Counter": "0,1,2,3",
"EventCode": "0xD2",
"EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR7",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 7 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x80",
"Unit": "M2M"
},
{
"BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 0",
"Counter": "0,1,2,3",
"EventCode": "0xD4",
"EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR0",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 0 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 1",
"Counter": "0,1,2,3",
"EventCode": "0xD4",
"EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR1",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 1 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 2",
"Counter": "0,1,2,3",
"EventCode": "0xD4",
"EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR2",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 2 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x4",
"Unit": "M2M"
},
{
"BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 3",
"Counter": "0,1,2,3",
"EventCode": "0xD4",
"EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR3",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 3 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x8",
"Unit": "M2M"
},
{
"BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 4",
"Counter": "0,1,2,3",
"EventCode": "0xD4",
"EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR4",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 4 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x10",
"Unit": "M2M"
},
{
"BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 5",
"Counter": "0,1,2,3",
"EventCode": "0xD4",
"EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR5",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 5 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x20",
"Unit": "M2M"
},
{
"BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 6",
"Counter": "0,1,2,3",
"EventCode": "0xD4",
"EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR6",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 6 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x40",
"Unit": "M2M"
},
{
"BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 7",
"Counter": "0,1,2,3",
"EventCode": "0xD4",
"EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR7",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 7 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x80",
"Unit": "M2M"
},
{
"BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 0",
"Counter": "0,1,2,3",
"EventCode": "0xD6",
"EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR0",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 0 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 1",
"Counter": "0,1,2,3",
"EventCode": "0xD6",
"EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR1",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 1 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 2",
"Counter": "0,1,2,3",
"EventCode": "0xD6",
"EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR2",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 2 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x4",
"Unit": "M2M"
},
{
"BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 3",
"Counter": "0,1,2,3",
"EventCode": "0xD6",
"EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR3",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 3 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x8",
"Unit": "M2M"
},
{
"BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 4",
"Counter": "0,1,2,3",
"EventCode": "0xD6",
"EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR4",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 4 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x10",
"Unit": "M2M"
},
{
"BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 5",
"Counter": "0,1,2,3",
"EventCode": "0xD6",
"EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR5",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 5 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x20",
"Unit": "M2M"
},
{
"BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 6",
"Counter": "0,1,2,3",
"EventCode": "0xD6",
"EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR6",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 6 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x40",
"Unit": "M2M"
},
{
"BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 7",
"Counter": "0,1,2,3",
"EventCode": "0xD6",
"EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR7",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 7 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x80",
"Unit": "M2M"
},
{
"BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 10",
"Counter": "0,1,2,3",
"EventCode": "0xD1",
"EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR10",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 10 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x4",
"Unit": "M2M"
},
{
"BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 8",
"Counter": "0,1,2,3",
"EventCode": "0xD1",
"EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR8",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 8 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 9",
"Counter": "0,1,2,3",
"EventCode": "0xD1",
"EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR9",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 9 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 10",
"Counter": "0,1,2,3",
"EventCode": "0xD3",
"EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR10",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 10 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x4",
"Unit": "M2M"
},
{
"BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 8",
"Counter": "0,1,2,3",
"EventCode": "0xD3",
"EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR8",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 8 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 9",
"Counter": "0,1,2,3",
"EventCode": "0xD3",
"EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR9",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 9 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 10",
"Counter": "0,1,2,3",
"EventCode": "0xD5",
"EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR10",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 10 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x4",
"Unit": "M2M"
},
{
"BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 8",
"Counter": "0,1,2,3",
"EventCode": "0xD5",
"EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR8",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 8 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 9",
"Counter": "0,1,2,3",
"EventCode": "0xD5",
"EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR9",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 9 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 10",
"Counter": "0,1,2,3",
"EventCode": "0xD7",
"EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR10",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 10 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x4",
"Unit": "M2M"
},
{
"BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 8",
"Counter": "0,1,2,3",
"EventCode": "0xD7",
"EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR8",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 8 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 9",
"Counter": "0,1,2,3",
"EventCode": "0xD7",
"EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR9",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 9 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "Tag Hit : Clean NearMem Read Hit",
"Counter": "0,1,2,3",
"EventCode": "0x2C",
"EventName": "UNC_M2M_TAG_HIT.NM_RD_HIT_CLEAN",
"PerPkg": "1",
"PublicDescription": "Tag Hit : Clean NearMem Read Hit : Tag Hit indicates when a request sent to the iMC hit in Near Memory. : Counts clean full line read hits (reads and RFOs).",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "Tag Hit : Dirty NearMem Read Hit",
"Counter": "0,1,2,3",
"EventCode": "0x2C",
"EventName": "UNC_M2M_TAG_HIT.NM_RD_HIT_DIRTY",
"PerPkg": "1",
"PublicDescription": "Tag Hit : Dirty NearMem Read Hit : Tag Hit indicates when a request sent to the iMC hit in Near Memory. : Counts dirty full line read hits (reads and RFOs).",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "Tag Hit : Clean NearMem Underfill Hit",
"Counter": "0,1,2,3",
"EventCode": "0x2C",
"EventName": "UNC_M2M_TAG_HIT.NM_UFILL_HIT_CLEAN",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Tag Hit : Clean NearMem Underfill Hit : Tag Hit indicates when a request sent to the iMC hit in Near Memory. : Counts clean underfill hits due to a partial write",
"UMask": "0x4",
"Unit": "M2M"
},
{
"BriefDescription": "Tag Hit : Dirty NearMem Underfill Hit",
"Counter": "0,1,2,3",
"EventCode": "0x2C",
"EventName": "UNC_M2M_TAG_HIT.NM_UFILL_HIT_DIRTY",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Tag Hit : Dirty NearMem Underfill Hit : Tag Hit indicates when a request sent to the iMC hit in Near Memory. : Counts dirty underfill read hits due to a partial write",
"UMask": "0x8",
"Unit": "M2M"
},
{
"BriefDescription": "Tag Miss",
"Counter": "0,1,2,3",
"EventCode": "0x61",
"EventName": "UNC_M2M_TAG_MISS",
"Experimental": "1",
"PerPkg": "1",
"Unit": "M2M"
},
{
"BriefDescription": "Number AD Ingress Credits",
"Counter": "0,1,2,3",
"EventCode": "0x41",
"EventName": "UNC_M2M_TGR_AD_CREDITS",
"Experimental": "1",
"PerPkg": "1",
"Unit": "M2M"
},
{
"BriefDescription": "Number BL Ingress Credits",
"Counter": "0,1,2,3",
"EventCode": "0x42",
"EventName": "UNC_M2M_TGR_BL_CREDITS",
"Experimental": "1",
"PerPkg": "1",
"Unit": "M2M"
},
{
"BriefDescription": "Tracker Cycles Full : Channel 0",
"Counter": "0,1,2,3",
"EventCode": "0x45",
"EventName": "UNC_M2M_TRACKER_FULL.CH0",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "Tracker Cycles Full : Channel 1",
"Counter": "0,1,2,3",
"EventCode": "0x45",
"EventName": "UNC_M2M_TRACKER_FULL.CH1",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "Tracker Cycles Full : Channel 2",
"Counter": "0,1,2,3",
"EventCode": "0x45",
"EventName": "UNC_M2M_TRACKER_FULL.CH2",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "M2M"
},
{
"BriefDescription": "Tracker Inserts : Channel 0",
"Counter": "0,1,2,3",
"EventCode": "0x49",
"EventName": "UNC_M2M_TRACKER_INSERTS.CH0",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "Tracker Inserts : Channel 1",
"Counter": "0,1,2,3",
"EventCode": "0x49",
"EventName": "UNC_M2M_TRACKER_INSERTS.CH1",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "Tracker Inserts : Channel 2",
"Counter": "0,1,2,3",
"EventCode": "0x49",
"EventName": "UNC_M2M_TRACKER_INSERTS.CH2",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "M2M"
},
{
"BriefDescription": "Tracker Cycles Not Empty : Channel 0",
"Counter": "0,1,2,3",
"EventCode": "0x46",
"EventName": "UNC_M2M_TRACKER_NE.CH0",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "Tracker Cycles Not Empty : Channel 1",
"Counter": "0,1,2,3",
"EventCode": "0x46",
"EventName": "UNC_M2M_TRACKER_NE.CH1",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "Tracker Cycles Not Empty : Channel 2",
"Counter": "0,1,2,3",
"EventCode": "0x46",
"EventName": "UNC_M2M_TRACKER_NE.CH2",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "M2M"
},
{
"BriefDescription": "Tracker Occupancy : Channel 0",
"Counter": "0,1,2,3",
"EventCode": "0x47",
"EventName": "UNC_M2M_TRACKER_OCCUPANCY.CH0",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "Tracker Occupancy : Channel 1",
"Counter": "0,1,2,3",
"EventCode": "0x47",
"EventName": "UNC_M2M_TRACKER_OCCUPANCY.CH1",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "Tracker Occupancy : Channel 2",
"Counter": "0,1,2,3",
"EventCode": "0x47",
"EventName": "UNC_M2M_TRACKER_OCCUPANCY.CH2",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "M2M"
},
{
"BriefDescription": "AD Egress (to CMS) Credit Acquired",
"Counter": "0,1,2,3",
"EventCode": "0x0d",
"EventName": "UNC_M2M_TxC_AD_CREDITS_ACQUIRED",
"Experimental": "1",
"PerPkg": "1",
"Unit": "M2M"
},
{
"BriefDescription": "AD Egress (to CMS) Credits Occupancy",
"Counter": "0,1,2,3",
"EventCode": "0x0e",
"EventName": "UNC_M2M_TxC_AD_CREDIT_OCCUPANCY",
"Experimental": "1",
"PerPkg": "1",
"Unit": "M2M"
},
{
"BriefDescription": "AD Egress (to CMS) Full",
"Counter": "0,1,2,3",
"EventCode": "0x0c",
"EventName": "UNC_M2M_TxC_AD_CYCLES_FULL",
"Experimental": "1",
"PerPkg": "1",
"Unit": "M2M"
},
{
"BriefDescription": "AD Egress (to CMS) Not Empty",
"Counter": "0,1,2,3",
"EventCode": "0x0b",
"EventName": "UNC_M2M_TxC_AD_CYCLES_NE",
"Experimental": "1",
"PerPkg": "1",
"Unit": "M2M"
},
{
"BriefDescription": "AD Egress (to CMS) Allocations",
"Counter": "0,1,2,3",
"EventCode": "0x09",
"EventName": "UNC_M2M_TxC_AD_INSERTS",
"Experimental": "1",
"PerPkg": "1",
"Unit": "M2M"
},
{
"BriefDescription": "Cycles with No AD Egress (to CMS) Credits",
"Counter": "0,1,2,3",
"EventCode": "0x0f",
"EventName": "UNC_M2M_TxC_AD_NO_CREDIT_CYCLES",
"Experimental": "1",
"PerPkg": "1",
"Unit": "M2M"
},
{
"BriefDescription": "Cycles Stalled with No AD Egress (to CMS) Credits",
"Counter": "0,1,2,3",
"EventCode": "0x10",
"EventName": "UNC_M2M_TxC_AD_NO_CREDIT_STALLED",
"Experimental": "1",
"PerPkg": "1",
"Unit": "M2M"
},
{
"BriefDescription": "AD Egress (to CMS) Occupancy",
"Counter": "0,1,2,3",
"EventCode": "0x0A",
"EventName": "UNC_M2M_TxC_AD_OCCUPANCY",
"Experimental": "1",
"PerPkg": "1",
"Unit": "M2M"
},
{
"BriefDescription": "Outbound Ring Transactions on AK : CRD Transactions to Cbo",
"Counter": "0,1,2,3",
"EventCode": "0x39",
"EventName": "UNC_M2M_TxC_AK.CRD_CBO",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "Outbound Ring Transactions on AK : NDR Transactions",
"Counter": "0,1,2,3",
"EventCode": "0x39",
"EventName": "UNC_M2M_TxC_AK.NDR",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "AKC Credits",
"Counter": "0,1,2,3",
"EventCode": "0x5F",
"EventName": "UNC_M2M_TxC_AKC_CREDITS",
"Experimental": "1",
"PerPkg": "1",
"Unit": "M2M"
},
{
"BriefDescription": "AK Egress (to CMS) Credit Acquired : Common Mesh Stop - Near Side",
"Counter": "0,1,2,3",
"EventCode": "0x1D",
"EventName": "UNC_M2M_TxC_AK_CREDITS_ACQUIRED.CMS0",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "AK Egress (to CMS) Credit Acquired : Common Mesh Stop - Far Side",
"Counter": "0,1,2,3",
"EventCode": "0x1D",
"EventName": "UNC_M2M_TxC_AK_CREDITS_ACQUIRED.CMS1",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "AK Egress (to CMS) Full : All",
"Counter": "0,1,2,3",
"EventCode": "0x14",
"EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.ALL",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x3",
"Unit": "M2M"
},
{
"BriefDescription": "AK Egress (to CMS) Full : Common Mesh Stop - Near Side",
"Counter": "0,1,2,3",
"EventCode": "0x14",
"EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.CMS0",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "AK Egress (to CMS) Full : Common Mesh Stop - Far Side",
"Counter": "0,1,2,3",
"EventCode": "0x14",
"EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.CMS1",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "AK Egress (to CMS) Full",
"Counter": "0,1,2,3",
"EventCode": "0x14",
"EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.RDCRD0",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "M2M"
},
{
"BriefDescription": "AK Egress (to CMS) Full",
"Counter": "0,1,2,3",
"EventCode": "0x14",
"EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.RDCRD1",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x88",
"Unit": "M2M"
},
{
"BriefDescription": "AK Egress (to CMS) Full",
"Counter": "0,1,2,3",
"EventCode": "0x14",
"EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCMP0",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "M2M"
},
{
"BriefDescription": "AK Egress (to CMS) Full",
"Counter": "0,1,2,3",
"EventCode": "0x14",
"EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCMP1",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0xa0",
"Unit": "M2M"
},
{
"BriefDescription": "AK Egress (to CMS) Full",
"Counter": "0,1,2,3",
"EventCode": "0x14",
"EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCRD0",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "M2M"
},
{
"BriefDescription": "AK Egress (to CMS) Full",
"Counter": "0,1,2,3",
"EventCode": "0x14",
"EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCRD1",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x90",
"Unit": "M2M"
},
{
"BriefDescription": "AK Egress (to CMS) Not Empty : All",
"Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "UNC_M2M_TxC_AK_CYCLES_NE.ALL",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x3",
"Unit": "M2M"
},
{
"BriefDescription": "AK Egress (to CMS) Not Empty : Common Mesh Stop - Near Side",
"Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "UNC_M2M_TxC_AK_CYCLES_NE.CMS0",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "AK Egress (to CMS) Not Empty : Common Mesh Stop - Far Side",
"Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "UNC_M2M_TxC_AK_CYCLES_NE.CMS1",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "AK Egress (to CMS) Not Empty",
"Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "UNC_M2M_TxC_AK_CYCLES_NE.RDCRD",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "M2M"
},
{
"BriefDescription": "AK Egress (to CMS) Not Empty",
"Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "UNC_M2M_TxC_AK_CYCLES_NE.WRCMP",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "M2M"
},
{
"BriefDescription": "AK Egress (to CMS) Not Empty",
"Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "UNC_M2M_TxC_AK_CYCLES_NE.WRCRD",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "M2M"
},
{
"BriefDescription": "AK Egress (to CMS) Allocations : All",
"Counter": "0,1,2,3",
"EventCode": "0x11",
"EventName": "UNC_M2M_TxC_AK_INSERTS.ALL",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x3",
"Unit": "M2M"
},
{
"BriefDescription": "AK Egress (to CMS) Allocations : Common Mesh Stop - Near Side",
"Counter": "0,1,2,3",
"EventCode": "0x11",
"EventName": "UNC_M2M_TxC_AK_INSERTS.CMS0",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "AK Egress (to CMS) Allocations : Common Mesh Stop - Far Side",
"Counter": "0,1,2,3",
"EventCode": "0x11",
"EventName": "UNC_M2M_TxC_AK_INSERTS.CMS1",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "AK Egress (to CMS) Allocations",
"Counter": "0,1,2,3",
"EventCode": "0x11",
"EventName": "UNC_M2M_TxC_AK_INSERTS.PREF_RD_CAM_HIT",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x40",
"Unit": "M2M"
},
{
"BriefDescription": "AK Egress (to CMS) Allocations",
"Counter": "0,1,2,3",
"EventCode": "0x11",
"EventName": "UNC_M2M_TxC_AK_INSERTS.RDCRD",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "M2M"
},
{
"BriefDescription": "AK Egress (to CMS) Allocations",
"Counter": "0,1,2,3",
"EventCode": "0x11",
"EventName": "UNC_M2M_TxC_AK_INSERTS.WRCMP",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "M2M"
},
{
"BriefDescription": "AK Egress (to CMS) Allocations",
"Counter": "0,1,2,3",
"EventCode": "0x11",
"EventName": "UNC_M2M_TxC_AK_INSERTS.WRCRD",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "M2M"
},
{
"BriefDescription": "Cycles with No AK Egress (to CMS) Credits : Common Mesh Stop - Near Side",
"Counter": "0,1,2,3",
"EventCode": "0x1F",
"EventName": "UNC_M2M_TxC_AK_NO_CREDIT_CYCLES.CMS0",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "Cycles with No AK Egress (to CMS) Credits : Common Mesh Stop - Far Side",
"Counter": "0,1,2,3",
"EventCode": "0x1F",
"EventName": "UNC_M2M_TxC_AK_NO_CREDIT_CYCLES.CMS1",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "Cycles Stalled with No AK Egress (to CMS) Credits : Common Mesh Stop - Near Side",
"Counter": "0,1,2,3",
"EventCode": "0x20",
"EventName": "UNC_M2M_TxC_AK_NO_CREDIT_STALLED.CMS0",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "Cycles Stalled with No AK Egress (to CMS) Credits : Common Mesh Stop - Far Side",
"Counter": "0,1,2,3",
"EventCode": "0x20",
"EventName": "UNC_M2M_TxC_AK_NO_CREDIT_STALLED.CMS1",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "AK Egress (to CMS) Occupancy : All",
"Counter": "0,1,2,3",
"EventCode": "0x12",
"EventName": "UNC_M2M_TxC_AK_OCCUPANCY.ALL",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x3",
"Unit": "M2M"
},
{
"BriefDescription": "AK Egress (to CMS) Occupancy : Common Mesh Stop - Near Side",
"Counter": "0,1,2,3",
"EventCode": "0x12",
"EventName": "UNC_M2M_TxC_AK_OCCUPANCY.CMS0",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "AK Egress (to CMS) Occupancy : Common Mesh Stop - Far Side",
"Counter": "0,1,2,3",
"EventCode": "0x12",
"EventName": "UNC_M2M_TxC_AK_OCCUPANCY.CMS1",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "AK Egress (to CMS) Occupancy",
"Counter": "0,1,2,3",
"EventCode": "0x12",
"EventName": "UNC_M2M_TxC_AK_OCCUPANCY.RDCRD",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "M2M"
},
{
"BriefDescription": "AK Egress (to CMS) Occupancy",
"Counter": "0,1,2,3",
"EventCode": "0x12",
"EventName": "UNC_M2M_TxC_AK_OCCUPANCY.WRCMP",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "M2M"
},
{
"BriefDescription": "AK Egress (to CMS) Occupancy",
"Counter": "0,1,2,3",
"EventCode": "0x12",
"EventName": "UNC_M2M_TxC_AK_OCCUPANCY.WRCRD",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "M2M"
},
{
"BriefDescription": "Outbound DRS Ring Transactions to Cache : Data to Cache",
"Counter": "0,1,2,3",
"EventCode": "0x40",
"EventName": "UNC_M2M_TxC_BL.DRS_CACHE",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "Outbound DRS Ring Transactions to Cache : Data to Core",
"Counter": "0,1,2,3",
"EventCode": "0x40",
"EventName": "UNC_M2M_TxC_BL.DRS_CORE",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "Outbound DRS Ring Transactions to Cache : Data to QPI",
"Counter": "0,1,2,3",
"EventCode": "0x40",
"EventName": "UNC_M2M_TxC_BL.DRS_UPI",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "M2M"
},
{
"BriefDescription": "BL Egress (to CMS) Credit Acquired : Common Mesh Stop - Near Side",
"Counter": "0,1,2,3",
"EventCode": "0x19",
"EventName": "UNC_M2M_TxC_BL_CREDITS_ACQUIRED.CMS0",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "BL Egress (to CMS) Credit Acquired : Common Mesh Stop - Far Side",
"Counter": "0,1,2,3",
"EventCode": "0x19",
"EventName": "UNC_M2M_TxC_BL_CREDITS_ACQUIRED.CMS1",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "BL Egress (to CMS) Full : All",
"Counter": "0,1,2,3",
"EventCode": "0x18",
"EventName": "UNC_M2M_TxC_BL_CYCLES_FULL.ALL",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x3",
"Unit": "M2M"
},
{
"BriefDescription": "BL Egress (to CMS) Full : Common Mesh Stop - Near Side",
"Counter": "0,1,2,3",
"EventCode": "0x18",
"EventName": "UNC_M2M_TxC_BL_CYCLES_FULL.CMS0",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "BL Egress (to CMS) Full : Common Mesh Stop - Far Side",
"Counter": "0,1,2,3",
"EventCode": "0x18",
"EventName": "UNC_M2M_TxC_BL_CYCLES_FULL.CMS1",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "BL Egress (to CMS) Not Empty : All",
"Counter": "0,1,2,3",
"EventCode": "0x17",
"EventName": "UNC_M2M_TxC_BL_CYCLES_NE.ALL",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x3",
"Unit": "M2M"
},
{
"BriefDescription": "BL Egress (to CMS) Not Empty : Common Mesh Stop - Near Side",
"Counter": "0,1,2,3",
"EventCode": "0x17",
"EventName": "UNC_M2M_TxC_BL_CYCLES_NE.CMS0",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "BL Egress (to CMS) Not Empty : Common Mesh Stop - Far Side",
"Counter": "0,1,2,3",
"EventCode": "0x17",
"EventName": "UNC_M2M_TxC_BL_CYCLES_NE.CMS1",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "BL Egress (to CMS) Allocations : All",
"Counter": "0,1,2,3",
"EventCode": "0x15",
"EventName": "UNC_M2M_TxC_BL_INSERTS.ALL",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x3",
"Unit": "M2M"
},
{
"BriefDescription": "BL Egress (to CMS) Allocations : Common Mesh Stop - Near Side",
"Counter": "0,1,2,3",
"EventCode": "0x15",
"EventName": "UNC_M2M_TxC_BL_INSERTS.CMS0",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "BL Egress (to CMS) Allocations : Common Mesh Stop - Far Side",
"Counter": "0,1,2,3",
"EventCode": "0x15",
"EventName": "UNC_M2M_TxC_BL_INSERTS.CMS1",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "Cycles with No BL Egress (to CMS) Credits : Common Mesh Stop - Near Side",
"Counter": "0,1,2,3",
"EventCode": "0x1B",
"EventName": "UNC_M2M_TxC_BL_NO_CREDIT_CYCLES.CMS0",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "Cycles with No BL Egress (to CMS) Credits : Common Mesh Stop - Far Side",
"Counter": "0,1,2,3",
"EventCode": "0x1B",
"EventName": "UNC_M2M_TxC_BL_NO_CREDIT_CYCLES.CMS1",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "Cycles Stalled with No BL Egress (to CMS) Credits : Common Mesh Stop - Near Side",
"Counter": "0,1,2,3",
"EventCode": "0x1C",
"EventName": "UNC_M2M_TxC_BL_NO_CREDIT_STALLED.CMS0",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "Cycles Stalled with No BL Egress (to CMS) Credits : Common Mesh Stop - Far Side",
"Counter": "0,1,2,3",
"EventCode": "0x1C",
"EventName": "UNC_M2M_TxC_BL_NO_CREDIT_STALLED.CMS1",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Horizontal ADS Used : AD - All",
"Counter": "0,1,2,3",
"EventCode": "0xA6",
"EventName": "UNC_M2M_TxR_HORZ_ADS_USED.AD_ALL",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal ADS Used : AD - All : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent. : All == Credited + Uncredited",
"UMask": "0x11",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Horizontal ADS Used : AD - Credited",
"Counter": "0,1,2,3",
"EventCode": "0xA6",
"EventName": "UNC_M2M_TxR_HORZ_ADS_USED.AD_CRD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal ADS Used : AD - Credited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
"UMask": "0x10",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Horizontal ADS Used : AD - Uncredited",
"Counter": "0,1,2,3",
"EventCode": "0xA6",
"EventName": "UNC_M2M_TxR_HORZ_ADS_USED.AD_UNCRD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal ADS Used : AD - Uncredited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Horizontal ADS Used : BL - All",
"Counter": "0,1,2,3",
"EventCode": "0xA6",
"EventName": "UNC_M2M_TxR_HORZ_ADS_USED.BL_ALL",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal ADS Used : BL - All : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent. : All == Credited + Uncredited",
"UMask": "0x44",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Horizontal ADS Used : BL - Credited",
"Counter": "0,1,2,3",
"EventCode": "0xA6",
"EventName": "UNC_M2M_TxR_HORZ_ADS_USED.BL_CRD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal ADS Used : BL - Credited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
"UMask": "0x40",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Horizontal ADS Used : BL - Uncredited",
"Counter": "0,1,2,3",
"EventCode": "0xA6",
"EventName": "UNC_M2M_TxR_HORZ_ADS_USED.BL_UNCRD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal ADS Used : BL - Uncredited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
"UMask": "0x4",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Horizontal Bypass Used : AD - All",
"Counter": "0,1,2,3",
"EventCode": "0xA7",
"EventName": "UNC_M2M_TxR_HORZ_BYPASS.AD_ALL",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Bypass Used : AD - All : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent. : All == Credited + Uncredited",
"UMask": "0x11",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Horizontal Bypass Used : AD - Credited",
"Counter": "0,1,2,3",
"EventCode": "0xA7",
"EventName": "UNC_M2M_TxR_HORZ_BYPASS.AD_CRD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Bypass Used : AD - Credited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
"UMask": "0x10",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Horizontal Bypass Used : AD - Uncredited",
"Counter": "0,1,2,3",
"EventCode": "0xA7",
"EventName": "UNC_M2M_TxR_HORZ_BYPASS.AD_UNCRD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Bypass Used : AD - Uncredited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Horizontal Bypass Used : AK",
"Counter": "0,1,2,3",
"EventCode": "0xA7",
"EventName": "UNC_M2M_TxR_HORZ_BYPASS.AK",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Bypass Used : AK : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Horizontal Bypass Used : AKC - Uncredited",
"Counter": "0,1,2,3",
"EventCode": "0xA7",
"EventName": "UNC_M2M_TxR_HORZ_BYPASS.AKC_UNCRD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Bypass Used : AKC - Uncredited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
"UMask": "0x80",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Horizontal Bypass Used : BL - All",
"Counter": "0,1,2,3",
"EventCode": "0xA7",
"EventName": "UNC_M2M_TxR_HORZ_BYPASS.BL_ALL",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Bypass Used : BL - All : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent. : All == Credited + Uncredited",
"UMask": "0x44",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Horizontal Bypass Used : BL - Credited",
"Counter": "0,1,2,3",
"EventCode": "0xA7",
"EventName": "UNC_M2M_TxR_HORZ_BYPASS.BL_CRD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Bypass Used : BL - Credited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
"UMask": "0x40",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Horizontal Bypass Used : BL - Uncredited",
"Counter": "0,1,2,3",
"EventCode": "0xA7",
"EventName": "UNC_M2M_TxR_HORZ_BYPASS.BL_UNCRD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Bypass Used : BL - Uncredited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
"UMask": "0x4",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Horizontal Bypass Used : IV",
"Counter": "0,1,2,3",
"EventCode": "0xA7",
"EventName": "UNC_M2M_TxR_HORZ_BYPASS.IV",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Bypass Used : IV : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
"UMask": "0x8",
"Unit": "M2M"
},
{
"BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - All",
"Counter": "0,1,2,3",
"EventCode": "0xA2",
"EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AD_ALL",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - All : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
"UMask": "0x11",
"Unit": "M2M"
},
{
"BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Credited",
"Counter": "0,1,2,3",
"EventCode": "0xA2",
"EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AD_CRD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x10",
"Unit": "M2M"
},
{
"BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Uncredited",
"Counter": "0,1,2,3",
"EventCode": "0xA2",
"EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AD_UNCRD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AK",
"Counter": "0,1,2,3",
"EventCode": "0xA2",
"EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AK",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AK : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AKC - Uncredited",
"Counter": "0,1,2,3",
"EventCode": "0xA2",
"EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AKC_UNCRD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AKC - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x80",
"Unit": "M2M"
},
{
"BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - All",
"Counter": "0,1,2,3",
"EventCode": "0xA2",
"EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.BL_ALL",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - All : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
"UMask": "0x44",
"Unit": "M2M"
},
{
"BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Credited",
"Counter": "0,1,2,3",
"EventCode": "0xA2",
"EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.BL_CRD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x40",
"Unit": "M2M"
},
{
"BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Uncredited",
"Counter": "0,1,2,3",
"EventCode": "0xA2",
"EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.BL_UNCRD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x4",
"Unit": "M2M"
},
{
"BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : IV",
"Counter": "0,1,2,3",
"EventCode": "0xA2",
"EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.IV",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : IV : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x8",
"Unit": "M2M"
},
{
"BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - All",
"Counter": "0,1,2,3",
"EventCode": "0xA3",
"EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AD_ALL",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - All : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
"UMask": "0x11",
"Unit": "M2M"
},
{
"BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Credited",
"Counter": "0,1,2,3",
"EventCode": "0xA3",
"EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AD_CRD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x10",
"Unit": "M2M"
},
{
"BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Uncredited",
"Counter": "0,1,2,3",
"EventCode": "0xA3",
"EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AD_UNCRD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AK",
"Counter": "0,1,2,3",
"EventCode": "0xA3",
"EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AK",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AK : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AKC - Uncredited",
"Counter": "0,1,2,3",
"EventCode": "0xA3",
"EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AKC_UNCRD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AKC - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x80",
"Unit": "M2M"
},
{
"BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - All",
"Counter": "0,1,2,3",
"EventCode": "0xA3",
"EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.BL_ALL",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - All : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
"UMask": "0x44",
"Unit": "M2M"
},
{
"BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Credited",
"Counter": "0,1,2,3",
"EventCode": "0xA3",
"EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.BL_CRD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x40",
"Unit": "M2M"
},
{
"BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Uncredited",
"Counter": "0,1,2,3",
"EventCode": "0xA3",
"EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.BL_UNCRD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x4",
"Unit": "M2M"
},
{
"BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : IV",
"Counter": "0,1,2,3",
"EventCode": "0xA3",
"EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.IV",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : IV : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x8",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Horizontal Egress Inserts : AD - All",
"Counter": "0,1,2,3",
"EventCode": "0xA1",
"EventName": "UNC_M2M_TxR_HORZ_INSERTS.AD_ALL",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress Inserts : AD - All : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
"UMask": "0x11",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Horizontal Egress Inserts : AD - Credited",
"Counter": "0,1,2,3",
"EventCode": "0xA1",
"EventName": "UNC_M2M_TxR_HORZ_INSERTS.AD_CRD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress Inserts : AD - Credited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x10",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Horizontal Egress Inserts : AD - Uncredited",
"Counter": "0,1,2,3",
"EventCode": "0xA1",
"EventName": "UNC_M2M_TxR_HORZ_INSERTS.AD_UNCRD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress Inserts : AD - Uncredited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Horizontal Egress Inserts : AK",
"Counter": "0,1,2,3",
"EventCode": "0xA1",
"EventName": "UNC_M2M_TxR_HORZ_INSERTS.AK",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress Inserts : AK : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Horizontal Egress Inserts : AKC - Uncredited",
"Counter": "0,1,2,3",
"EventCode": "0xA1",
"EventName": "UNC_M2M_TxR_HORZ_INSERTS.AKC_UNCRD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress Inserts : AKC - Uncredited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x80",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Horizontal Egress Inserts : BL - All",
"Counter": "0,1,2,3",
"EventCode": "0xA1",
"EventName": "UNC_M2M_TxR_HORZ_INSERTS.BL_ALL",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress Inserts : BL - All : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
"UMask": "0x44",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Horizontal Egress Inserts : BL - Credited",
"Counter": "0,1,2,3",
"EventCode": "0xA1",
"EventName": "UNC_M2M_TxR_HORZ_INSERTS.BL_CRD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress Inserts : BL - Credited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x40",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Horizontal Egress Inserts : BL - Uncredited",
"Counter": "0,1,2,3",
"EventCode": "0xA1",
"EventName": "UNC_M2M_TxR_HORZ_INSERTS.BL_UNCRD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress Inserts : BL - Uncredited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x4",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Horizontal Egress Inserts : IV",
"Counter": "0,1,2,3",
"EventCode": "0xA1",
"EventName": "UNC_M2M_TxR_HORZ_INSERTS.IV",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress Inserts : IV : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x8",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Horizontal Egress NACKs : AD - All",
"Counter": "0,1,2,3",
"EventCode": "0xA4",
"EventName": "UNC_M2M_TxR_HORZ_NACK.AD_ALL",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress NACKs : AD - All : Counts number of Egress packets NACK'ed on to the Horizontal Ring : All == Credited + Uncredited",
"UMask": "0x11",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Horizontal Egress NACKs : AD - Credited",
"Counter": "0,1,2,3",
"EventCode": "0xA4",
"EventName": "UNC_M2M_TxR_HORZ_NACK.AD_CRD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress NACKs : AD - Credited : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
"UMask": "0x10",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Horizontal Egress NACKs : AD - Uncredited",
"Counter": "0,1,2,3",
"EventCode": "0xA4",
"EventName": "UNC_M2M_TxR_HORZ_NACK.AD_UNCRD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress NACKs : AD - Uncredited : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Horizontal Egress NACKs : AK",
"Counter": "0,1,2,3",
"EventCode": "0xA4",
"EventName": "UNC_M2M_TxR_HORZ_NACK.AK",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress NACKs : AK : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Horizontal Egress NACKs : AKC - Uncredited",
"Counter": "0,1,2,3",
"EventCode": "0xA4",
"EventName": "UNC_M2M_TxR_HORZ_NACK.AKC_UNCRD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress NACKs : AKC - Uncredited : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
"UMask": "0x80",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Horizontal Egress NACKs : BL - All",
"Counter": "0,1,2,3",
"EventCode": "0xA4",
"EventName": "UNC_M2M_TxR_HORZ_NACK.BL_ALL",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress NACKs : BL - All : Counts number of Egress packets NACK'ed on to the Horizontal Ring : All == Credited + Uncredited",
"UMask": "0x44",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Horizontal Egress NACKs : BL - Credited",
"Counter": "0,1,2,3",
"EventCode": "0xA4",
"EventName": "UNC_M2M_TxR_HORZ_NACK.BL_CRD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress NACKs : BL - Credited : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
"UMask": "0x40",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Horizontal Egress NACKs : BL - Uncredited",
"Counter": "0,1,2,3",
"EventCode": "0xA4",
"EventName": "UNC_M2M_TxR_HORZ_NACK.BL_UNCRD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress NACKs : BL - Uncredited : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
"UMask": "0x4",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Horizontal Egress NACKs : IV",
"Counter": "0,1,2,3",
"EventCode": "0xA4",
"EventName": "UNC_M2M_TxR_HORZ_NACK.IV",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress NACKs : IV : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
"UMask": "0x8",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Horizontal Egress Occupancy : AD - All",
"Counter": "0,1,2,3",
"EventCode": "0xA0",
"EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AD_ALL",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress Occupancy : AD - All : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
"UMask": "0x11",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Horizontal Egress Occupancy : AD - Credited",
"Counter": "0,1,2,3",
"EventCode": "0xA0",
"EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AD_CRD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress Occupancy : AD - Credited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x10",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Horizontal Egress Occupancy : AD - Uncredited",
"Counter": "0,1,2,3",
"EventCode": "0xA0",
"EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AD_UNCRD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress Occupancy : AD - Uncredited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Horizontal Egress Occupancy : AK",
"Counter": "0,1,2,3",
"EventCode": "0xA0",
"EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AK",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress Occupancy : AK : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Horizontal Egress Occupancy : AKC - Uncredited",
"Counter": "0,1,2,3",
"EventCode": "0xA0",
"EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AKC_UNCRD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress Occupancy : AKC - Uncredited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x80",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Horizontal Egress Occupancy : BL - All",
"Counter": "0,1,2,3",
"EventCode": "0xA0",
"EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.BL_ALL",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress Occupancy : BL - All : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
"UMask": "0x44",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Horizontal Egress Occupancy : BL - Credited",
"Counter": "0,1,2,3",
"EventCode": "0xA0",
"EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.BL_CRD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress Occupancy : BL - Credited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x40",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Horizontal Egress Occupancy : BL - Uncredited",
"Counter": "0,1,2,3",
"EventCode": "0xA0",
"EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.BL_UNCRD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress Occupancy : BL - Uncredited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x4",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Horizontal Egress Occupancy : IV",
"Counter": "0,1,2,3",
"EventCode": "0xA0",
"EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.IV",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress Occupancy : IV : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x8",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Horizontal Egress Injection Starvation : AD - All",
"Counter": "0,1,2,3",
"EventCode": "0xA5",
"EventName": "UNC_M2M_TxR_HORZ_STARVED.AD_ALL",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress Injection Starvation : AD - All : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time. : All == Credited + Uncredited",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Horizontal Egress Injection Starvation : AD - Uncredited",
"Counter": "0,1,2,3",
"EventCode": "0xA5",
"EventName": "UNC_M2M_TxR_HORZ_STARVED.AD_UNCRD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress Injection Starvation : AD - Uncredited : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Horizontal Egress Injection Starvation : AK",
"Counter": "0,1,2,3",
"EventCode": "0xA5",
"EventName": "UNC_M2M_TxR_HORZ_STARVED.AK",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress Injection Starvation : AK : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Horizontal Egress Injection Starvation : AKC - Uncredited",
"Counter": "0,1,2,3",
"EventCode": "0xA5",
"EventName": "UNC_M2M_TxR_HORZ_STARVED.AKC_UNCRD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress Injection Starvation : AKC - Uncredited : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
"UMask": "0x80",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Horizontal Egress Injection Starvation : BL - All",
"Counter": "0,1,2,3",
"EventCode": "0xA5",
"EventName": "UNC_M2M_TxR_HORZ_STARVED.BL_ALL",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress Injection Starvation : BL - All : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time. : All == Credited + Uncredited",
"UMask": "0x4",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Horizontal Egress Injection Starvation : BL - Uncredited",
"Counter": "0,1,2,3",
"EventCode": "0xA5",
"EventName": "UNC_M2M_TxR_HORZ_STARVED.BL_UNCRD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress Injection Starvation : BL - Uncredited : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
"UMask": "0x4",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Horizontal Egress Injection Starvation : IV",
"Counter": "0,1,2,3",
"EventCode": "0xA5",
"EventName": "UNC_M2M_TxR_HORZ_STARVED.IV",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress Injection Starvation : IV : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
"UMask": "0x8",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Vertical ADS Used : AD - Agent 0",
"Counter": "0,1,2,3",
"EventCode": "0x9C",
"EventName": "UNC_M2M_TxR_VERT_ADS_USED.AD_AG0",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical ADS Used : AD - Agent 0 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Vertical ADS Used : AD - Agent 1",
"Counter": "0,1,2,3",
"EventCode": "0x9C",
"EventName": "UNC_M2M_TxR_VERT_ADS_USED.AD_AG1",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical ADS Used : AD - Agent 1 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
"UMask": "0x10",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Vertical ADS Used : BL - Agent 0",
"Counter": "0,1,2,3",
"EventCode": "0x9C",
"EventName": "UNC_M2M_TxR_VERT_ADS_USED.BL_AG0",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical ADS Used : BL - Agent 0 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
"UMask": "0x4",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Vertical ADS Used : BL - Agent 1",
"Counter": "0,1,2,3",
"EventCode": "0x9C",
"EventName": "UNC_M2M_TxR_VERT_ADS_USED.BL_AG1",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical ADS Used : BL - Agent 1 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
"UMask": "0x40",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Vertical ADS Used : AD - Agent 0",
"Counter": "0,1,2,3",
"EventCode": "0x9D",
"EventName": "UNC_M2M_TxR_VERT_BYPASS.AD_AG0",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical ADS Used : AD - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Vertical ADS Used : AD - Agent 1",
"Counter": "0,1,2,3",
"EventCode": "0x9D",
"EventName": "UNC_M2M_TxR_VERT_BYPASS.AD_AG1",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical ADS Used : AD - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
"UMask": "0x10",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Vertical ADS Used : AK - Agent 0",
"Counter": "0,1,2,3",
"EventCode": "0x9D",
"EventName": "UNC_M2M_TxR_VERT_BYPASS.AK_AG0",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical ADS Used : AK - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Vertical ADS Used : AK - Agent 1",
"Counter": "0,1,2,3",
"EventCode": "0x9D",
"EventName": "UNC_M2M_TxR_VERT_BYPASS.AK_AG1",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical ADS Used : AK - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
"UMask": "0x20",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Vertical ADS Used : BL - Agent 0",
"Counter": "0,1,2,3",
"EventCode": "0x9D",
"EventName": "UNC_M2M_TxR_VERT_BYPASS.BL_AG0",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical ADS Used : BL - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
"UMask": "0x4",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Vertical ADS Used : BL - Agent 1",
"Counter": "0,1,2,3",
"EventCode": "0x9D",
"EventName": "UNC_M2M_TxR_VERT_BYPASS.BL_AG1",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical ADS Used : BL - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
"UMask": "0x40",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Vertical ADS Used : IV - Agent 1",
"Counter": "0,1,2,3",
"EventCode": "0x9D",
"EventName": "UNC_M2M_TxR_VERT_BYPASS.IV_AG1",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical ADS Used : IV - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
"UMask": "0x8",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Vertical ADS Used : AKC - Agent 0",
"Counter": "0,1,2,3",
"EventCode": "0x9E",
"EventName": "UNC_M2M_TxR_VERT_BYPASS_1.AKC_AG0",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical ADS Used : AKC - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Vertical ADS Used : AKC - Agent 1",
"Counter": "0,1,2,3",
"EventCode": "0x9E",
"EventName": "UNC_M2M_TxR_VERT_BYPASS_1.AKC_AG1",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical ADS Used : AKC - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 0",
"Counter": "0,1,2,3",
"EventCode": "0x94",
"EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL0.AD_AG0",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 1",
"Counter": "0,1,2,3",
"EventCode": "0x94",
"EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL0.AD_AG1",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.",
"UMask": "0x10",
"Unit": "M2M"
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 0",
"Counter": "0,1,2,3",
"EventCode": "0x94",
"EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL0.AK_AG0",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 1",
"Counter": "0,1,2,3",
"EventCode": "0x94",
"EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL0.AK_AG1",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.",
"UMask": "0x20",
"Unit": "M2M"
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 0",
"Counter": "0,1,2,3",
"EventCode": "0x94",
"EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL0.BL_AG0",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.",
"UMask": "0x4",
"Unit": "M2M"
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 1",
"Counter": "0,1,2,3",
"EventCode": "0x94",
"EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL0.BL_AG1",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.",
"UMask": "0x40",
"Unit": "M2M"
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : IV - Agent 0",
"Counter": "0,1,2,3",
"EventCode": "0x94",
"EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL0.IV_AG0",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : IV - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.",
"UMask": "0x8",
"Unit": "M2M"
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 0",
"Counter": "0,1,2,3",
"EventCode": "0x95",
"EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL1.AKC_AG0",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 1",
"Counter": "0,1,2,3",
"EventCode": "0x95",
"EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL1.AKC_AG1",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 0",
"Counter": "0,1,2,3",
"EventCode": "0x96",
"EventName": "UNC_M2M_TxR_VERT_CYCLES_NE0.AD_AG0",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 1",
"Counter": "0,1,2,3",
"EventCode": "0x96",
"EventName": "UNC_M2M_TxR_VERT_CYCLES_NE0.AD_AG1",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.",
"UMask": "0x10",
"Unit": "M2M"
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 0",
"Counter": "0,1,2,3",
"EventCode": "0x96",
"EventName": "UNC_M2M_TxR_VERT_CYCLES_NE0.AK_AG0",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 1",
"Counter": "0,1,2,3",
"EventCode": "0x96",
"EventName": "UNC_M2M_TxR_VERT_CYCLES_NE0.AK_AG1",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.",
"UMask": "0x20",
"Unit": "M2M"
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 0",
"Counter": "0,1,2,3",
"EventCode": "0x96",
"EventName": "UNC_M2M_TxR_VERT_CYCLES_NE0.BL_AG0",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.",
"UMask": "0x4",
"Unit": "M2M"
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 1",
"Counter": "0,1,2,3",
"EventCode": "0x96",
"EventName": "UNC_M2M_TxR_VERT_CYCLES_NE0.BL_AG1",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.",
"UMask": "0x40",
"Unit": "M2M"
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : IV - Agent 0",
"Counter": "0,1,2,3",
"EventCode": "0x96",
"EventName": "UNC_M2M_TxR_VERT_CYCLES_NE0.IV_AG0",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : IV - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.",
"UMask": "0x8",
"Unit": "M2M"
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 0",
"Counter": "0,1,2,3",
"EventCode": "0x97",
"EventName": "UNC_M2M_TxR_VERT_CYCLES_NE1.AKC_AG0",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 1",
"Counter": "0,1,2,3",
"EventCode": "0x97",
"EventName": "UNC_M2M_TxR_VERT_CYCLES_NE1.AKC_AG1",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Vert Egress Allocations : AD - Agent 0",
"Counter": "0,1,2,3",
"EventCode": "0x92",
"EventName": "UNC_M2M_TxR_VERT_INSERTS0.AD_AG0",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vert Egress Allocations : AD - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Vert Egress Allocations : AD - Agent 1",
"Counter": "0,1,2,3",
"EventCode": "0x92",
"EventName": "UNC_M2M_TxR_VERT_INSERTS0.AD_AG1",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vert Egress Allocations : AD - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.",
"UMask": "0x10",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Vert Egress Allocations : AK - Agent 0",
"Counter": "0,1,2,3",
"EventCode": "0x92",
"EventName": "UNC_M2M_TxR_VERT_INSERTS0.AK_AG0",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vert Egress Allocations : AK - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Vert Egress Allocations : AK - Agent 1",
"Counter": "0,1,2,3",
"EventCode": "0x92",
"EventName": "UNC_M2M_TxR_VERT_INSERTS0.AK_AG1",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vert Egress Allocations : AK - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.",
"UMask": "0x20",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Vert Egress Allocations : BL - Agent 0",
"Counter": "0,1,2,3",
"EventCode": "0x92",
"EventName": "UNC_M2M_TxR_VERT_INSERTS0.BL_AG0",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vert Egress Allocations : BL - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.",
"UMask": "0x4",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Vert Egress Allocations : BL - Agent 1",
"Counter": "0,1,2,3",
"EventCode": "0x92",
"EventName": "UNC_M2M_TxR_VERT_INSERTS0.BL_AG1",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vert Egress Allocations : BL - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.",
"UMask": "0x40",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Vert Egress Allocations : IV - Agent 0",
"Counter": "0,1,2,3",
"EventCode": "0x92",
"EventName": "UNC_M2M_TxR_VERT_INSERTS0.IV_AG0",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vert Egress Allocations : IV - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.",
"UMask": "0x8",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Vert Egress Allocations : AKC - Agent 0",
"Counter": "0,1,2,3",
"EventCode": "0x93",
"EventName": "UNC_M2M_TxR_VERT_INSERTS1.AKC_AG0",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vert Egress Allocations : AKC - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Vert Egress Allocations : AKC - Agent 1",
"Counter": "0,1,2,3",
"EventCode": "0x93",
"EventName": "UNC_M2M_TxR_VERT_INSERTS1.AKC_AG1",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vert Egress Allocations : AKC - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Vertical Egress NACKs : AD - Agent 0",
"Counter": "0,1,2,3",
"EventCode": "0x98",
"EventName": "UNC_M2M_TxR_VERT_NACK0.AD_AG0",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical Egress NACKs : AD - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Vertical Egress NACKs : AD - Agent 1",
"Counter": "0,1,2,3",
"EventCode": "0x98",
"EventName": "UNC_M2M_TxR_VERT_NACK0.AD_AG1",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical Egress NACKs : AD - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
"UMask": "0x10",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Vertical Egress NACKs : AK - Agent 0",
"Counter": "0,1,2,3",
"EventCode": "0x98",
"EventName": "UNC_M2M_TxR_VERT_NACK0.AK_AG0",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical Egress NACKs : AK - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Vertical Egress NACKs : AK - Agent 1",
"Counter": "0,1,2,3",
"EventCode": "0x98",
"EventName": "UNC_M2M_TxR_VERT_NACK0.AK_AG1",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical Egress NACKs : AK - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
"UMask": "0x20",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Vertical Egress NACKs : BL - Agent 0",
"Counter": "0,1,2,3",
"EventCode": "0x98",
"EventName": "UNC_M2M_TxR_VERT_NACK0.BL_AG0",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical Egress NACKs : BL - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
"UMask": "0x4",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Vertical Egress NACKs : BL - Agent 1",
"Counter": "0,1,2,3",
"EventCode": "0x98",
"EventName": "UNC_M2M_TxR_VERT_NACK0.BL_AG1",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical Egress NACKs : BL - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
"UMask": "0x40",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Vertical Egress NACKs : IV",
"Counter": "0,1,2,3",
"EventCode": "0x98",
"EventName": "UNC_M2M_TxR_VERT_NACK0.IV_AG0",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical Egress NACKs : IV : Counts number of Egress packets NACK'ed on to the Vertical Ring",
"UMask": "0x8",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Vertical Egress NACKs : AKC - Agent 0",
"Counter": "0,1,2,3",
"EventCode": "0x99",
"EventName": "UNC_M2M_TxR_VERT_NACK1.AKC_AG0",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical Egress NACKs : AKC - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Vertical Egress NACKs : AKC - Agent 1",
"Counter": "0,1,2,3",
"EventCode": "0x99",
"EventName": "UNC_M2M_TxR_VERT_NACK1.AKC_AG1",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical Egress NACKs : AKC - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Vert Egress Occupancy : AD - Agent 0",
"Counter": "0,1,2,3",
"EventCode": "0x90",
"EventName": "UNC_M2M_TxR_VERT_OCCUPANCY0.AD_AG0",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vert Egress Occupancy : AD - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Vert Egress Occupancy : AD - Agent 1",
"Counter": "0,1,2,3",
"EventCode": "0x90",
"EventName": "UNC_M2M_TxR_VERT_OCCUPANCY0.AD_AG1",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vert Egress Occupancy : AD - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.",
"UMask": "0x10",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Vert Egress Occupancy : AK - Agent 0",
"Counter": "0,1,2,3",
"EventCode": "0x90",
"EventName": "UNC_M2M_TxR_VERT_OCCUPANCY0.AK_AG0",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vert Egress Occupancy : AK - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Vert Egress Occupancy : AK - Agent 1",
"Counter": "0,1,2,3",
"EventCode": "0x90",
"EventName": "UNC_M2M_TxR_VERT_OCCUPANCY0.AK_AG1",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vert Egress Occupancy : AK - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.",
"UMask": "0x20",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Vert Egress Occupancy : BL - Agent 0",
"Counter": "0,1,2,3",
"EventCode": "0x90",
"EventName": "UNC_M2M_TxR_VERT_OCCUPANCY0.BL_AG0",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vert Egress Occupancy : BL - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.",
"UMask": "0x4",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Vert Egress Occupancy : BL - Agent 1",
"Counter": "0,1,2,3",
"EventCode": "0x90",
"EventName": "UNC_M2M_TxR_VERT_OCCUPANCY0.BL_AG1",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vert Egress Occupancy : BL - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.",
"UMask": "0x40",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Vert Egress Occupancy : IV - Agent 0",
"Counter": "0,1,2,3",
"EventCode": "0x90",
"EventName": "UNC_M2M_TxR_VERT_OCCUPANCY0.IV_AG0",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vert Egress Occupancy : IV - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.",
"UMask": "0x8",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Vert Egress Occupancy : AKC - Agent 0",
"Counter": "0,1,2,3",
"EventCode": "0x91",
"EventName": "UNC_M2M_TxR_VERT_OCCUPANCY1.AKC_AG0",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vert Egress Occupancy : AKC - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Vert Egress Occupancy : AKC - Agent 1",
"Counter": "0,1,2,3",
"EventCode": "0x91",
"EventName": "UNC_M2M_TxR_VERT_OCCUPANCY1.AKC_AG1",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vert Egress Occupancy : AKC - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 0",
"Counter": "0,1,2,3",
"EventCode": "0x9A",
"EventName": "UNC_M2M_TxR_VERT_STARVED0.AD_AG0",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 1",
"Counter": "0,1,2,3",
"EventCode": "0x9A",
"EventName": "UNC_M2M_TxR_VERT_STARVED0.AD_AG1",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
"UMask": "0x10",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 0",
"Counter": "0,1,2,3",
"EventCode": "0x9A",
"EventName": "UNC_M2M_TxR_VERT_STARVED0.AK_AG0",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 1",
"Counter": "0,1,2,3",
"EventCode": "0x9A",
"EventName": "UNC_M2M_TxR_VERT_STARVED0.AK_AG1",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
"UMask": "0x20",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 0",
"Counter": "0,1,2,3",
"EventCode": "0x9A",
"EventName": "UNC_M2M_TxR_VERT_STARVED0.BL_AG0",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
"UMask": "0x4",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 1",
"Counter": "0,1,2,3",
"EventCode": "0x9A",
"EventName": "UNC_M2M_TxR_VERT_STARVED0.BL_AG1",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
"UMask": "0x40",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Vertical Egress Injection Starvation : IV",
"Counter": "0,1,2,3",
"EventCode": "0x9A",
"EventName": "UNC_M2M_TxR_VERT_STARVED0.IV_AG0",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical Egress Injection Starvation : IV : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
"UMask": "0x8",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0",
"Counter": "0,1,2,3",
"EventCode": "0x9B",
"EventName": "UNC_M2M_TxR_VERT_STARVED1.AKC_AG0",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 1",
"Counter": "0,1,2,3",
"EventCode": "0x9B",
"EventName": "UNC_M2M_TxR_VERT_STARVED1.AKC_AG1",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0",
"Counter": "0,1,2,3",
"EventCode": "0x9B",
"EventName": "UNC_M2M_TxR_VERT_STARVED1.TGC",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
"UMask": "0x4",
"Unit": "M2M"
},
{
"BriefDescription": "Vertical AD Ring In Use : Down and Even",
"Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "UNC_M2M_VERT_RING_AD_IN_USE.DN_EVEN",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Vertical AD Ring In Use : Down and Even : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x4",
"Unit": "M2M"
},
{
"BriefDescription": "Vertical AD Ring In Use : Down and Odd",
"Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "UNC_M2M_VERT_RING_AD_IN_USE.DN_ODD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Vertical AD Ring In Use : Down and Odd : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x8",
"Unit": "M2M"
},
{
"BriefDescription": "Vertical AD Ring In Use : Up and Even",
"Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "UNC_M2M_VERT_RING_AD_IN_USE.UP_EVEN",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Vertical AD Ring In Use : Up and Even : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "Vertical AD Ring In Use : Up and Odd",
"Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "UNC_M2M_VERT_RING_AD_IN_USE.UP_ODD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Vertical AD Ring In Use : Up and Odd : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "Vertical AKC Ring In Use : Down and Even",
"Counter": "0,1,2,3",
"EventCode": "0xB4",
"EventName": "UNC_M2M_VERT_RING_AKC_IN_USE.DN_EVEN",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Vertical AKC Ring In Use : Down and Even : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x4",
"Unit": "M2M"
},
{
"BriefDescription": "Vertical AKC Ring In Use : Down and Odd",
"Counter": "0,1,2,3",
"EventCode": "0xB4",
"EventName": "UNC_M2M_VERT_RING_AKC_IN_USE.DN_ODD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Vertical AKC Ring In Use : Down and Odd : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x8",
"Unit": "M2M"
},
{
"BriefDescription": "Vertical AKC Ring In Use : Up and Even",
"Counter": "0,1,2,3",
"EventCode": "0xB4",
"EventName": "UNC_M2M_VERT_RING_AKC_IN_USE.UP_EVEN",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Vertical AKC Ring In Use : Up and Even : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "Vertical AKC Ring In Use : Up and Odd",
"Counter": "0,1,2,3",
"EventCode": "0xB4",
"EventName": "UNC_M2M_VERT_RING_AKC_IN_USE.UP_ODD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Vertical AKC Ring In Use : Up and Odd : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "Vertical AK Ring In Use : Down and Even",
"Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UNC_M2M_VERT_RING_AK_IN_USE.DN_EVEN",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Vertical AK Ring In Use : Down and Even : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x4",
"Unit": "M2M"
},
{
"BriefDescription": "Vertical AK Ring In Use : Down and Odd",
"Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UNC_M2M_VERT_RING_AK_IN_USE.DN_ODD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Vertical AK Ring In Use : Down and Odd : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x8",
"Unit": "M2M"
},
{
"BriefDescription": "Vertical AK Ring In Use : Up and Even",
"Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UNC_M2M_VERT_RING_AK_IN_USE.UP_EVEN",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Vertical AK Ring In Use : Up and Even : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "Vertical AK Ring In Use : Up and Odd",
"Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UNC_M2M_VERT_RING_AK_IN_USE.UP_ODD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Vertical AK Ring In Use : Up and Odd : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "Vertical BL Ring in Use : Down and Even",
"Counter": "0,1,2,3",
"EventCode": "0xB2",
"EventName": "UNC_M2M_VERT_RING_BL_IN_USE.DN_EVEN",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Vertical BL Ring in Use : Down and Even : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x4",
"Unit": "M2M"
},
{
"BriefDescription": "Vertical BL Ring in Use : Down and Odd",
"Counter": "0,1,2,3",
"EventCode": "0xB2",
"EventName": "UNC_M2M_VERT_RING_BL_IN_USE.DN_ODD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Vertical BL Ring in Use : Down and Odd : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x8",
"Unit": "M2M"
},
{
"BriefDescription": "Vertical BL Ring in Use : Up and Even",
"Counter": "0,1,2,3",
"EventCode": "0xB2",
"EventName": "UNC_M2M_VERT_RING_BL_IN_USE.UP_EVEN",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Vertical BL Ring in Use : Up and Even : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "Vertical BL Ring in Use : Up and Odd",
"Counter": "0,1,2,3",
"EventCode": "0xB2",
"EventName": "UNC_M2M_VERT_RING_BL_IN_USE.UP_ODD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Vertical BL Ring in Use : Up and Odd : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "Vertical IV Ring in Use : Down",
"Counter": "0,1,2,3",
"EventCode": "0xB3",
"EventName": "UNC_M2M_VERT_RING_IV_IN_USE.DN",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Vertical IV Ring in Use : Down : Counts the number of cycles that the Vertical IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.",
"UMask": "0x4",
"Unit": "M2M"
},
{
"BriefDescription": "Vertical IV Ring in Use : Up",
"Counter": "0,1,2,3",
"EventCode": "0xB3",
"EventName": "UNC_M2M_VERT_RING_IV_IN_USE.UP",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Vertical IV Ring in Use : Up : Counts the number of cycles that the Vertical IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "Vertical TGC Ring In Use : Down and Even",
"Counter": "0,1,2,3",
"EventCode": "0xB5",
"EventName": "UNC_M2M_VERT_RING_TGC_IN_USE.DN_EVEN",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Vertical TGC Ring In Use : Down and Even : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x4",
"Unit": "M2M"
},
{
"BriefDescription": "Vertical TGC Ring In Use : Down and Odd",
"Counter": "0,1,2,3",
"EventCode": "0xB5",
"EventName": "UNC_M2M_VERT_RING_TGC_IN_USE.DN_ODD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Vertical TGC Ring In Use : Down and Odd : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x8",
"Unit": "M2M"
},
{
"BriefDescription": "Vertical TGC Ring In Use : Up and Even",
"Counter": "0,1,2,3",
"EventCode": "0xB5",
"EventName": "UNC_M2M_VERT_RING_TGC_IN_USE.UP_EVEN",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Vertical TGC Ring In Use : Up and Even : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "Vertical TGC Ring In Use : Up and Odd",
"Counter": "0,1,2,3",
"EventCode": "0xB5",
"EventName": "UNC_M2M_VERT_RING_TGC_IN_USE.UP_ODD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Vertical TGC Ring In Use : Up and Odd : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "WPQ Flush : Channel 0",
"Counter": "0,1,2,3",
"EventCode": "0x58",
"EventName": "UNC_M2M_WPQ_FLUSH.CH0",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "WPQ Flush : Channel 1",
"Counter": "0,1,2,3",
"EventCode": "0x58",
"EventName": "UNC_M2M_WPQ_FLUSH.CH1",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "WPQ Flush : Channel 2",
"Counter": "0,1,2,3",
"EventCode": "0x58",
"EventName": "UNC_M2M_WPQ_FLUSH.CH2",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "M2M"
},
{
"BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Regular : Channel 0",
"Counter": "0,1,2,3",
"EventCode": "0x4D",
"EventName": "UNC_M2M_WPQ_NO_REG_CRD.CHN0",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Regular : Channel 1",
"Counter": "0,1,2,3",
"EventCode": "0x4D",
"EventName": "UNC_M2M_WPQ_NO_REG_CRD.CHN1",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Regular : Channel 2",
"Counter": "0,1,2,3",
"EventCode": "0x4D",
"EventName": "UNC_M2M_WPQ_NO_REG_CRD.CHN2",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "M2M"
},
{
"BriefDescription": "M2M->iMC WPQ Cycles w/Credits - PMM : Channel 0",
"Counter": "0,1,2,3",
"EventCode": "0x51",
"EventName": "UNC_M2M_WPQ_NO_REG_CRD_PMM.CHN0",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "M2M->iMC WPQ Cycles w/Credits - PMM : Channel 1",
"Counter": "0,1,2,3",
"EventCode": "0x51",
"EventName": "UNC_M2M_WPQ_NO_REG_CRD_PMM.CHN1",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "M2M->iMC WPQ Cycles w/Credits - PMM : Channel 2",
"Counter": "0,1,2,3",
"EventCode": "0x51",
"EventName": "UNC_M2M_WPQ_NO_REG_CRD_PMM.CHN2",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "M2M"
},
{
"BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Special : Channel 0",
"Counter": "0,1,2,3",
"EventCode": "0x4E",
"EventName": "UNC_M2M_WPQ_NO_SPEC_CRD.CHN0",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Special : Channel 1",
"Counter": "0,1,2,3",
"EventCode": "0x4E",
"EventName": "UNC_M2M_WPQ_NO_SPEC_CRD.CHN1",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Special : Channel 2",
"Counter": "0,1,2,3",
"EventCode": "0x4E",
"EventName": "UNC_M2M_WPQ_NO_SPEC_CRD.CHN2",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "M2M"
},
{
"BriefDescription": "Write Tracker Cycles Full : Channel 0",
"Counter": "0,1,2,3",
"EventCode": "0x4A",
"EventName": "UNC_M2M_WR_TRACKER_FULL.CH0",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "Write Tracker Cycles Full : Channel 1",
"Counter": "0,1,2,3",
"EventCode": "0x4A",
"EventName": "UNC_M2M_WR_TRACKER_FULL.CH1",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "Write Tracker Cycles Full : Channel 2",
"Counter": "0,1,2,3",
"EventCode": "0x4A",
"EventName": "UNC_M2M_WR_TRACKER_FULL.CH2",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "M2M"
},
{
"BriefDescription": "Write Tracker Cycles Full : Mirror",
"Counter": "0,1,2,3",
"EventCode": "0x4A",
"EventName": "UNC_M2M_WR_TRACKER_FULL.MIRR",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "M2M"
},
{
"BriefDescription": "Write Tracker Inserts : Channel 0",
"Counter": "0,1,2,3",
"EventCode": "0x56",
"EventName": "UNC_M2M_WR_TRACKER_INSERTS.CH0",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "Write Tracker Inserts : Channel 1",
"Counter": "0,1,2,3",
"EventCode": "0x56",
"EventName": "UNC_M2M_WR_TRACKER_INSERTS.CH1",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "Write Tracker Inserts : Channel 2",
"Counter": "0,1,2,3",
"EventCode": "0x56",
"EventName": "UNC_M2M_WR_TRACKER_INSERTS.CH2",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "M2M"
},
{
"BriefDescription": "Write Tracker Cycles Not Empty : Channel 0",
"Counter": "0,1,2,3",
"EventCode": "0x4B",
"EventName": "UNC_M2M_WR_TRACKER_NE.CH0",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "Write Tracker Cycles Not Empty : Channel 1",
"Counter": "0,1,2,3",
"EventCode": "0x4B",
"EventName": "UNC_M2M_WR_TRACKER_NE.CH1",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "Write Tracker Cycles Not Empty : Channel 2",
"Counter": "0,1,2,3",
"EventCode": "0x4B",
"EventName": "UNC_M2M_WR_TRACKER_NE.CH2",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "M2M"
},
{
"BriefDescription": "Write Tracker Cycles Not Empty : Mirror",
"Counter": "0,1,2,3",
"EventCode": "0x4B",
"EventName": "UNC_M2M_WR_TRACKER_NE.MIRR",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "M2M"
},
{
"BriefDescription": "Write Tracker Cycles Not Empty",
"Counter": "0,1,2,3",
"EventCode": "0x4B",
"EventName": "UNC_M2M_WR_TRACKER_NE.MIRR_NONTGR",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "M2M"
},
{
"BriefDescription": "Write Tracker Cycles Not Empty",
"Counter": "0,1,2,3",
"EventCode": "0x4B",
"EventName": "UNC_M2M_WR_TRACKER_NE.MIRR_PWR",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "M2M"
},
{
"BriefDescription": "Write Tracker Non-Posted Inserts : Channel 0",
"Counter": "0,1,2,3",
"EventCode": "0x63",
"EventName": "UNC_M2M_WR_TRACKER_NONPOSTED_INSERTS.CH0",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "Write Tracker Non-Posted Inserts : Channel 1",
"Counter": "0,1,2,3",
"EventCode": "0x63",
"EventName": "UNC_M2M_WR_TRACKER_NONPOSTED_INSERTS.CH1",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "Write Tracker Non-Posted Inserts : Channel 2",
"Counter": "0,1,2,3",
"EventCode": "0x63",
"EventName": "UNC_M2M_WR_TRACKER_NONPOSTED_INSERTS.CH2",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "M2M"
},
{
"BriefDescription": "Write Tracker Non-Posted Occupancy : Channel 0",
"Counter": "0,1,2,3",
"EventCode": "0x62",
"EventName": "UNC_M2M_WR_TRACKER_NONPOSTED_OCCUPANCY.CH0",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "Write Tracker Non-Posted Occupancy : Channel 1",
"Counter": "0,1,2,3",
"EventCode": "0x62",
"EventName": "UNC_M2M_WR_TRACKER_NONPOSTED_OCCUPANCY.CH1",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "Write Tracker Non-Posted Occupancy : Channel 2",
"Counter": "0,1,2,3",
"EventCode": "0x62",
"EventName": "UNC_M2M_WR_TRACKER_NONPOSTED_OCCUPANCY.CH2",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "M2M"
},
{
"BriefDescription": "Write Tracker Occupancy : Channel 0",
"Counter": "0,1,2,3",
"EventCode": "0x55",
"EventName": "UNC_M2M_WR_TRACKER_OCCUPANCY.CH0",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "Write Tracker Occupancy : Channel 1",
"Counter": "0,1,2,3",
"EventCode": "0x55",
"EventName": "UNC_M2M_WR_TRACKER_OCCUPANCY.CH1",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "Write Tracker Occupancy : Channel 2",
"Counter": "0,1,2,3",
"EventCode": "0x55",
"EventName": "UNC_M2M_WR_TRACKER_OCCUPANCY.CH2",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "M2M"
},
{
"BriefDescription": "Write Tracker Occupancy : Mirror",
"Counter": "0,1,2,3",
"EventCode": "0x55",
"EventName": "UNC_M2M_WR_TRACKER_OCCUPANCY.MIRR",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "M2M"
},
{
"BriefDescription": "Write Tracker Occupancy",
"Counter": "0,1,2,3",
"EventCode": "0x55",
"EventName": "UNC_M2M_WR_TRACKER_OCCUPANCY.MIRR_NONTGR",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "M2M"
},
{
"BriefDescription": "Write Tracker Occupancy",
"Counter": "0,1,2,3",
"EventCode": "0x55",
"EventName": "UNC_M2M_WR_TRACKER_OCCUPANCY.MIRR_PWR",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "M2M"
},
{
"BriefDescription": "Write Tracker Posted Inserts : Channel 0",
"Counter": "0,1,2,3",
"EventCode": "0x5E",
"EventName": "UNC_M2M_WR_TRACKER_POSTED_INSERTS.CH0",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "Write Tracker Posted Inserts : Channel 1",
"Counter": "0,1,2,3",
"EventCode": "0x5E",
"EventName": "UNC_M2M_WR_TRACKER_POSTED_INSERTS.CH1",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "Write Tracker Posted Inserts : Channel 2",
"Counter": "0,1,2,3",
"EventCode": "0x5E",
"EventName": "UNC_M2M_WR_TRACKER_POSTED_INSERTS.CH2",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "M2M"
},
{
"BriefDescription": "Write Tracker Posted Occupancy : Channel 0",
"Counter": "0,1,2,3",
"EventCode": "0x5D",
"EventName": "UNC_M2M_WR_TRACKER_POSTED_OCCUPANCY.CH0",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M2M"
},
{
"BriefDescription": "Write Tracker Posted Occupancy : Channel 1",
"Counter": "0,1,2,3",
"EventCode": "0x5D",
"EventName": "UNC_M2M_WR_TRACKER_POSTED_OCCUPANCY.CH1",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M2M"
},
{
"BriefDescription": "Write Tracker Posted Occupancy : Channel 2",
"Counter": "0,1,2,3",
"EventCode": "0x5D",
"EventName": "UNC_M2M_WR_TRACKER_POSTED_OCCUPANCY.CH2",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "M2M"
},
{
"BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 0",
"Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED0.TGR0",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 0 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 1",
"Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED0.TGR1",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 1 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 2",
"Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED0.TGR2",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 2 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x4",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 3",
"Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED0.TGR3",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 3 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x8",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 4",
"Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED0.TGR4",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 4 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x10",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 5",
"Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED0.TGR5",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 5 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x20",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 6",
"Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED0.TGR6",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 6 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x40",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 7",
"Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED0.TGR7",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 7 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x80",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 10",
"Counter": "0,1,2,3",
"EventCode": "0x81",
"EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED1.TGR10",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 10 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x4",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 8",
"Counter": "0,1,2,3",
"EventCode": "0x81",
"EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED1.TGR8",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 8 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 9",
"Counter": "0,1,2,3",
"EventCode": "0x81",
"EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED1.TGR9",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 9 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 0",
"Counter": "0,1,2,3",
"EventCode": "0x82",
"EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY0.TGR0",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 0 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
"UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 1",
"Counter": "0,1,2,3",
"EventCode": "0x82",
"EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY0.TGR1",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 1 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
"UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 2",
"Counter": "0,1,2,3",
"EventCode": "0x82",
"EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY0.TGR2",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 2 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
"UMask": "0x4",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 3",
"Counter": "0,1,2,3",
"EventCode": "0x82",
"EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY0.TGR3",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 3 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
"UMask": "0x8",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 4",
"Counter": "0,1,2,3",
"EventCode": "0x82",
"EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY0.TGR4",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 4 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
"UMask": "0x10",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 5",
"Counter": "0,1,2,3",
"EventCode": "0x82",
"EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY0.TGR5",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 5 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
"UMask": "0x20",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 6",
"Counter": "0,1,2,3",
"EventCode": "0x82",
"EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY0.TGR6",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 6 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
"UMask": "0x40",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 7",
"Counter": "0,1,2,3",
"EventCode": "0x82",
"EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY0.TGR7",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 7 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
"UMask": "0x80",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 10",
"Counter": "0,1,2,3",
"EventCode": "0x83",
"EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY1.TGR10",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 10 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
"UMask": "0x4",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 8",
"Counter": "0,1,2,3",
"EventCode": "0x83",
"EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY1.TGR8",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 8 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
"UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 9",
"Counter": "0,1,2,3",
"EventCode": "0x83",
"EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY1.TGR9",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 9 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
"UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 0",
"Counter": "0,1,2,3",
"EventCode": "0x88",
"EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED0.TGR0",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 0 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 1",
"Counter": "0,1,2,3",
"EventCode": "0x88",
"EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED0.TGR1",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 1 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 2",
"Counter": "0,1,2,3",
"EventCode": "0x88",
"EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED0.TGR2",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 2 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x4",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 3",
"Counter": "0,1,2,3",
"EventCode": "0x88",
"EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED0.TGR3",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 3 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x8",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 4",
"Counter": "0,1,2,3",
"EventCode": "0x88",
"EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED0.TGR4",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 4 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x10",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 5",
"Counter": "0,1,2,3",
"EventCode": "0x88",
"EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED0.TGR5",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 5 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x20",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 6",
"Counter": "0,1,2,3",
"EventCode": "0x88",
"EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED0.TGR6",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 6 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x40",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 7",
"Counter": "0,1,2,3",
"EventCode": "0x88",
"EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED0.TGR7",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 7 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x80",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 10",
"Counter": "0,1,2,3",
"EventCode": "0x89",
"EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED1.TGR10",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 10 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x4",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 8",
"Counter": "0,1,2,3",
"EventCode": "0x89",
"EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED1.TGR8",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 8 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 9",
"Counter": "0,1,2,3",
"EventCode": "0x89",
"EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED1.TGR9",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 9 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 0",
"Counter": "0,1,2,3",
"EventCode": "0x8A",
"EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY0.TGR0",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 0 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
"UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 1",
"Counter": "0,1,2,3",
"EventCode": "0x8A",
"EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY0.TGR1",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 1 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
"UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 2",
"Counter": "0,1,2,3",
"EventCode": "0x8A",
"EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY0.TGR2",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 2 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
"UMask": "0x4",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 3",
"Counter": "0,1,2,3",
"EventCode": "0x8A",
"EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY0.TGR3",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 3 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
"UMask": "0x8",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 4",
"Counter": "0,1,2,3",
"EventCode": "0x8A",
"EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY0.TGR4",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 4 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
"UMask": "0x10",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 5",
"Counter": "0,1,2,3",
"EventCode": "0x8A",
"EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY0.TGR5",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 5 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
"UMask": "0x20",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 6",
"Counter": "0,1,2,3",
"EventCode": "0x8A",
"EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY0.TGR6",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 6 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
"UMask": "0x40",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 7",
"Counter": "0,1,2,3",
"EventCode": "0x8A",
"EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY0.TGR7",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 7 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
"UMask": "0x80",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 10",
"Counter": "0,1,2,3",
"EventCode": "0x8B",
"EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY1.TGR10",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 10 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
"UMask": "0x4",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 8",
"Counter": "0,1,2,3",
"EventCode": "0x8B",
"EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY1.TGR8",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 8 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
"UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 9",
"Counter": "0,1,2,3",
"EventCode": "0x8B",
"EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY1.TGR9",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 9 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
"UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 0",
"Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED0.TGR0",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 0 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 1",
"Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED0.TGR1",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 1 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 2",
"Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED0.TGR2",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 2 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x4",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 3",
"Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED0.TGR3",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 3 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x8",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 4",
"Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED0.TGR4",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 4 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x10",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 5",
"Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED0.TGR5",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 5 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x20",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 6",
"Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED0.TGR6",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 6 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x40",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 7",
"Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED0.TGR7",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 7 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x80",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 10",
"Counter": "0,1,2,3",
"EventCode": "0x85",
"EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED1.TGR10",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 10 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x4",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 8",
"Counter": "0,1,2,3",
"EventCode": "0x85",
"EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED1.TGR8",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 8 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 9",
"Counter": "0,1,2,3",
"EventCode": "0x85",
"EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED1.TGR9",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 9 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 0",
"Counter": "0,1,2,3",
"EventCode": "0x86",
"EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY0.TGR0",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 0 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
"UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 1",
"Counter": "0,1,2,3",
"EventCode": "0x86",
"EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY0.TGR1",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 1 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
"UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 2",
"Counter": "0,1,2,3",
"EventCode": "0x86",
"EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY0.TGR2",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 2 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
"UMask": "0x4",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 3",
"Counter": "0,1,2,3",
"EventCode": "0x86",
"EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY0.TGR3",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 3 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
"UMask": "0x8",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 4",
"Counter": "0,1,2,3",
"EventCode": "0x86",
"EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY0.TGR4",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 4 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
"UMask": "0x10",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 5",
"Counter": "0,1,2,3",
"EventCode": "0x86",
"EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY0.TGR5",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 5 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
"UMask": "0x20",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 6",
"Counter": "0,1,2,3",
"EventCode": "0x86",
"EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY0.TGR6",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 6 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
"UMask": "0x40",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 7",
"Counter": "0,1,2,3",
"EventCode": "0x86",
"EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY0.TGR7",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 7 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
"UMask": "0x80",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 10",
"Counter": "0,1,2,3",
"EventCode": "0x87",
"EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY1.TGR10",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 10 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
"UMask": "0x4",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 8",
"Counter": "0,1,2,3",
"EventCode": "0x87",
"EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY1.TGR8",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 8 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
"UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 9",
"Counter": "0,1,2,3",
"EventCode": "0x87",
"EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY1.TGR9",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 9 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
"UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 0",
"Counter": "0,1,2,3",
"EventCode": "0x8C",
"EventName": "UNC_M3UPI_AG1_BL_CRD_ACQUIRED0.TGR0",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 0 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 1",
"Counter": "0,1,2,3",
"EventCode": "0x8C",
"EventName": "UNC_M3UPI_AG1_BL_CRD_ACQUIRED0.TGR1",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 1 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 2",
"Counter": "0,1,2,3",
"EventCode": "0x8C",
"EventName": "UNC_M3UPI_AG1_BL_CRD_ACQUIRED0.TGR2",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 2 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x4",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 3",
"Counter": "0,1,2,3",
"EventCode": "0x8C",
"EventName": "UNC_M3UPI_AG1_BL_CRD_ACQUIRED0.TGR3",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 3 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x8",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4",
"Counter": "0,1,2,3",
"EventCode": "0x8C",
"EventName": "UNC_M3UPI_AG1_BL_CRD_ACQUIRED0.TGR4",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x10",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5",
"Counter": "0,1,2,3",
"EventCode": "0x8C",
"EventName": "UNC_M3UPI_AG1_BL_CRD_ACQUIRED0.TGR5",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x20",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4",
"Counter": "0,1,2,3",
"EventCode": "0x8C",
"EventName": "UNC_M3UPI_AG1_BL_CRD_ACQUIRED0.TGR6",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x40",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5",
"Counter": "0,1,2,3",
"EventCode": "0x8C",
"EventName": "UNC_M3UPI_AG1_BL_CRD_ACQUIRED0.TGR7",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x80",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 10",
"Counter": "0,1,2,3",
"EventCode": "0x8D",
"EventName": "UNC_M3UPI_AG1_BL_CRD_ACQUIRED1.TGR10",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 10 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x4",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 8",
"Counter": "0,1,2,3",
"EventCode": "0x8D",
"EventName": "UNC_M3UPI_AG1_BL_CRD_ACQUIRED1.TGR8",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 8 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 9",
"Counter": "0,1,2,3",
"EventCode": "0x8D",
"EventName": "UNC_M3UPI_AG1_BL_CRD_ACQUIRED1.TGR9",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 9 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 0",
"Counter": "0,1,2,3",
"EventCode": "0x8E",
"EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY0.TGR0",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 0 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
"UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 1",
"Counter": "0,1,2,3",
"EventCode": "0x8E",
"EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY0.TGR1",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 1 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
"UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 2",
"Counter": "0,1,2,3",
"EventCode": "0x8E",
"EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY0.TGR2",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 2 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
"UMask": "0x4",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 3",
"Counter": "0,1,2,3",
"EventCode": "0x8E",
"EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY0.TGR3",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 3 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
"UMask": "0x8",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 4",
"Counter": "0,1,2,3",
"EventCode": "0x8E",
"EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY0.TGR4",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 4 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
"UMask": "0x10",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 5",
"Counter": "0,1,2,3",
"EventCode": "0x8E",
"EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY0.TGR5",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 5 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
"UMask": "0x20",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 6",
"Counter": "0,1,2,3",
"EventCode": "0x8E",
"EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY0.TGR6",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 6 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
"UMask": "0x40",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 7",
"Counter": "0,1,2,3",
"EventCode": "0x8E",
"EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY0.TGR7",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 7 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
"UMask": "0x80",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 10",
"Counter": "0,1,2,3",
"EventCode": "0x8F",
"EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY1.TGR10",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 10 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
"UMask": "0x4",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 8",
"Counter": "0,1,2,3",
"EventCode": "0x8F",
"EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY1.TGR8",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 8 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
"UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 9",
"Counter": "0,1,2,3",
"EventCode": "0x8F",
"EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY1.TGR9",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 9 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
"UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "CBox AD Credits Empty : Requests",
"Counter": "0,1,2,3",
"EventCode": "0x22",
"EventName": "UNC_M3UPI_CHA_AD_CREDITS_EMPTY.REQ",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CBox AD Credits Empty : Requests : No credits available to send to Cbox on the AD Ring (covers higher CBoxes)",
"UMask": "0x4",
"Unit": "M3UPI"
},
{
"BriefDescription": "CBox AD Credits Empty : Snoops",
"Counter": "0,1,2,3",
"EventCode": "0x22",
"EventName": "UNC_M3UPI_CHA_AD_CREDITS_EMPTY.SNP",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CBox AD Credits Empty : Snoops : No credits available to send to Cbox on the AD Ring (covers higher CBoxes)",
"UMask": "0x8",
"Unit": "M3UPI"
},
{
"BriefDescription": "CBox AD Credits Empty : VNA Messages",
"Counter": "0,1,2,3",
"EventCode": "0x22",
"EventName": "UNC_M3UPI_CHA_AD_CREDITS_EMPTY.VNA",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CBox AD Credits Empty : VNA Messages : No credits available to send to Cbox on the AD Ring (covers higher CBoxes)",
"UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "CBox AD Credits Empty : Writebacks",
"Counter": "0,1,2,3",
"EventCode": "0x22",
"EventName": "UNC_M3UPI_CHA_AD_CREDITS_EMPTY.WB",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CBox AD Credits Empty : Writebacks : No credits available to send to Cbox on the AD Ring (covers higher CBoxes)",
"UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "Clockticks of the mesh to UPI (M3UPI)",
"Counter": "0,1,2,3",
"EventCode": "0x01",
"EventName": "UNC_M3UPI_CLOCKTICKS",
"PerPkg": "1",
"PublicDescription": "Clockticks of the mesh to UPI (M3UPI) : Counts the number of uclks in the M3 uclk domain. This could be slightly different than the count in the Ubox because of enable/freeze delays. However, because the M3 is close to the Ubox, they generally should not diverge by more than a handful of cycles.",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Clockticks",
"Counter": "0,1,2,3",
"EventCode": "0xc0",
"EventName": "UNC_M3UPI_CMS_CLOCKTICKS",
"Experimental": "1",
"PerPkg": "1",
"Unit": "M3UPI"
},
{
"BriefDescription": "D2C Sent",
"Counter": "0,1,2,3",
"EventCode": "0x2B",
"EventName": "UNC_M3UPI_D2C_SENT",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "D2C Sent : Count cases BL sends direct to core",
"Unit": "M3UPI"
},
{
"BriefDescription": "D2U Sent",
"Counter": "0,1,2,3",
"EventCode": "0x2A",
"EventName": "UNC_M3UPI_D2U_SENT",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "D2U Sent : Cases where SMI3 sends D2U command",
"Unit": "M3UPI"
},
{
"BriefDescription": "Distress signal asserted : DPT Local",
"Counter": "0,1,2,3",
"EventCode": "0xAF",
"EventName": "UNC_M3UPI_DISTRESS_ASSERTED.DPT_LOCAL",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Distress signal asserted : DPT Local : Counts the number of cycles either the local or incoming distress signals are asserted. : Dynamic Prefetch Throttle triggered by this tile",
"UMask": "0x4",
"Unit": "M3UPI"
},
{
"BriefDescription": "Distress signal asserted : DPT Remote",
"Counter": "0,1,2,3",
"EventCode": "0xAF",
"EventName": "UNC_M3UPI_DISTRESS_ASSERTED.DPT_NONLOCAL",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Distress signal asserted : DPT Remote : Counts the number of cycles either the local or incoming distress signals are asserted. : Dynamic Prefetch Throttle received by this tile",
"UMask": "0x8",
"Unit": "M3UPI"
},
{
"BriefDescription": "Distress signal asserted : DPT Stalled - IV",
"Counter": "0,1,2,3",
"EventCode": "0xAF",
"EventName": "UNC_M3UPI_DISTRESS_ASSERTED.DPT_STALL_IV",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Distress signal asserted : DPT Stalled - IV : Counts the number of cycles either the local or incoming distress signals are asserted. : DPT occurred while regular IVs were received, causing DPT to be stalled",
"UMask": "0x40",
"Unit": "M3UPI"
},
{
"BriefDescription": "Distress signal asserted : DPT Stalled - No Credit",
"Counter": "0,1,2,3",
"EventCode": "0xAF",
"EventName": "UNC_M3UPI_DISTRESS_ASSERTED.DPT_STALL_NOCRD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Distress signal asserted : DPT Stalled - No Credit : Counts the number of cycles either the local or incoming distress signals are asserted. : DPT occurred while credit not available causing DPT to be stalled",
"UMask": "0x80",
"Unit": "M3UPI"
},
{
"BriefDescription": "Distress signal asserted : Horizontal",
"Counter": "0,1,2,3",
"EventCode": "0xAF",
"EventName": "UNC_M3UPI_DISTRESS_ASSERTED.HORZ",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Distress signal asserted : Horizontal : Counts the number of cycles either the local or incoming distress signals are asserted. : If TGR egress is full, then agents will throttle outgoing AD IDI transactions",
"UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "Distress signal asserted : PMM Local",
"Counter": "0,1,2,3",
"EventCode": "0xAF",
"EventName": "UNC_M3UPI_DISTRESS_ASSERTED.PMM_LOCAL",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Distress signal asserted : PMM Local : Counts the number of cycles either the local or incoming distress signals are asserted. : If the CHA TOR has too many PMM transactions, this signal will throttle outgoing MS2IDI traffic",
"UMask": "0x10",
"Unit": "M3UPI"
},
{
"BriefDescription": "Distress signal asserted : PMM Remote",
"Counter": "0,1,2,3",
"EventCode": "0xAF",
"EventName": "UNC_M3UPI_DISTRESS_ASSERTED.PMM_NONLOCAL",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Distress signal asserted : PMM Remote : Counts the number of cycles either the local or incoming distress signals are asserted. : If another CHA TOR has too many PMM transactions, this signal will throttle outgoing MS2IDI traffic",
"UMask": "0x20",
"Unit": "M3UPI"
},
{
"BriefDescription": "Distress signal asserted : Vertical",
"Counter": "0,1,2,3",
"EventCode": "0xAF",
"EventName": "UNC_M3UPI_DISTRESS_ASSERTED.VERT",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Distress signal asserted : Vertical : Counts the number of cycles either the local or incoming distress signals are asserted. : If IRQ egress is full, then agents will throttle outgoing AD IDI transactions",
"UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "Egress Blocking due to Ordering requirements : Down",
"Counter": "0,1,2,3",
"EventCode": "0xBA",
"EventName": "UNC_M3UPI_EGRESS_ORDERING.IV_SNOOPGO_DN",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Egress Blocking due to Ordering requirements : Down : Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements",
"UMask": "0x4",
"Unit": "M3UPI"
},
{
"BriefDescription": "Egress Blocking due to Ordering requirements : Up",
"Counter": "0,1,2,3",
"EventCode": "0xBA",
"EventName": "UNC_M3UPI_EGRESS_ORDERING.IV_SNOOPGO_UP",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Egress Blocking due to Ordering requirements : Up : Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements",
"UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "Horizontal AD Ring In Use : Left and Even",
"Counter": "0,1,2,3",
"EventCode": "0xB6",
"EventName": "UNC_M3UPI_HORZ_RING_AD_IN_USE.LEFT_EVEN",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Horizontal AD Ring In Use : Left and Even : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "Horizontal AD Ring In Use : Left and Odd",
"Counter": "0,1,2,3",
"EventCode": "0xB6",
"EventName": "UNC_M3UPI_HORZ_RING_AD_IN_USE.LEFT_ODD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Horizontal AD Ring In Use : Left and Odd : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "Horizontal AD Ring In Use : Right and Even",
"Counter": "0,1,2,3",
"EventCode": "0xB6",
"EventName": "UNC_M3UPI_HORZ_RING_AD_IN_USE.RIGHT_EVEN",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Horizontal AD Ring In Use : Right and Even : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x4",
"Unit": "M3UPI"
},
{
"BriefDescription": "Horizontal AD Ring In Use : Right and Odd",
"Counter": "0,1,2,3",
"EventCode": "0xB6",
"EventName": "UNC_M3UPI_HORZ_RING_AD_IN_USE.RIGHT_ODD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Horizontal AD Ring In Use : Right and Odd : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x8",
"Unit": "M3UPI"
},
{
"BriefDescription": "Horizontal AK Ring In Use : Left and Even",
"Counter": "0,1,2,3",
"EventCode": "0xBB",
"EventName": "UNC_M3UPI_HORZ_RING_AKC_IN_USE.LEFT_EVEN",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Horizontal AK Ring In Use : Left and Even : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "Horizontal AK Ring In Use : Left and Odd",
"Counter": "0,1,2,3",
"EventCode": "0xBB",
"EventName": "UNC_M3UPI_HORZ_RING_AKC_IN_USE.LEFT_ODD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Horizontal AK Ring In Use : Left and Odd : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "Horizontal AK Ring In Use : Right and Even",
"Counter": "0,1,2,3",
"EventCode": "0xBB",
"EventName": "UNC_M3UPI_HORZ_RING_AKC_IN_USE.RIGHT_EVEN",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Horizontal AK Ring In Use : Right and Even : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x4",
"Unit": "M3UPI"
},
{
"BriefDescription": "Horizontal AK Ring In Use : Right and Odd",
"Counter": "0,1,2,3",
"EventCode": "0xBB",
"EventName": "UNC_M3UPI_HORZ_RING_AKC_IN_USE.RIGHT_ODD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Horizontal AK Ring In Use : Right and Odd : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x8",
"Unit": "M3UPI"
},
{
"BriefDescription": "Horizontal AK Ring In Use : Left and Even",
"Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "UNC_M3UPI_HORZ_RING_AK_IN_USE.LEFT_EVEN",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Horizontal AK Ring In Use : Left and Even : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "Horizontal AK Ring In Use : Left and Odd",
"Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "UNC_M3UPI_HORZ_RING_AK_IN_USE.LEFT_ODD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Horizontal AK Ring In Use : Left and Odd : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "Horizontal AK Ring In Use : Right and Even",
"Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "UNC_M3UPI_HORZ_RING_AK_IN_USE.RIGHT_EVEN",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Horizontal AK Ring In Use : Right and Even : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x4",
"Unit": "M3UPI"
},
{
"BriefDescription": "Horizontal AK Ring In Use : Right and Odd",
"Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "UNC_M3UPI_HORZ_RING_AK_IN_USE.RIGHT_ODD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Horizontal AK Ring In Use : Right and Odd : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x8",
"Unit": "M3UPI"
},
{
"BriefDescription": "Horizontal BL Ring in Use : Left and Even",
"Counter": "0,1,2,3",
"EventCode": "0xB8",
"EventName": "UNC_M3UPI_HORZ_RING_BL_IN_USE.LEFT_EVEN",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Horizontal BL Ring in Use : Left and Even : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "Horizontal BL Ring in Use : Left and Odd",
"Counter": "0,1,2,3",
"EventCode": "0xB8",
"EventName": "UNC_M3UPI_HORZ_RING_BL_IN_USE.LEFT_ODD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Horizontal BL Ring in Use : Left and Odd : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "Horizontal BL Ring in Use : Right and Even",
"Counter": "0,1,2,3",
"EventCode": "0xB8",
"EventName": "UNC_M3UPI_HORZ_RING_BL_IN_USE.RIGHT_EVEN",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Horizontal BL Ring in Use : Right and Even : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x4",
"Unit": "M3UPI"
},
{
"BriefDescription": "Horizontal BL Ring in Use : Right and Odd",
"Counter": "0,1,2,3",
"EventCode": "0xB8",
"EventName": "UNC_M3UPI_HORZ_RING_BL_IN_USE.RIGHT_ODD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Horizontal BL Ring in Use : Right and Odd : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x8",
"Unit": "M3UPI"
},
{
"BriefDescription": "Horizontal IV Ring in Use : Left",
"Counter": "0,1,2,3",
"EventCode": "0xB9",
"EventName": "UNC_M3UPI_HORZ_RING_IV_IN_USE.LEFT",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Horizontal IV Ring in Use : Left : Counts the number of cycles that the Horizontal IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.",
"UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "Horizontal IV Ring in Use : Right",
"Counter": "0,1,2,3",
"EventCode": "0xB9",
"EventName": "UNC_M3UPI_HORZ_RING_IV_IN_USE.RIGHT",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Horizontal IV Ring in Use : Right : Counts the number of cycles that the Horizontal IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.",
"UMask": "0x4",
"Unit": "M3UPI"
},
{
"BriefDescription": "M2 BL Credits Empty : IIO0 and IIO1 share the same ring destination. (1 VN0 credit only)",
"Counter": "0,1,2,3",
"EventCode": "0x23",
"EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO1_NCB",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "M2 BL Credits Empty : IIO0 and IIO1 share the same ring destination. (1 VN0 credit only) : No vn0 and vna credits available to send to M2",
"UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "M2 BL Credits Empty : IIO2",
"Counter": "0,1,2,3",
"EventCode": "0x23",
"EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO2_NCB",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "M2 BL Credits Empty : IIO2 : No vn0 and vna credits available to send to M2",
"UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "M2 BL Credits Empty : IIO3",
"Counter": "0,1,2,3",
"EventCode": "0x23",
"EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO3_NCB",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "M2 BL Credits Empty : IIO3 : No vn0 and vna credits available to send to M2",
"UMask": "0x4",
"Unit": "M3UPI"
},
{
"BriefDescription": "M2 BL Credits Empty : IIO4",
"Counter": "0,1,2,3",
"EventCode": "0x23",
"EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO4_NCB",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "M2 BL Credits Empty : IIO4 : No vn0 and vna credits available to send to M2",
"UMask": "0x8",
"Unit": "M3UPI"
},
{
"BriefDescription": "M2 BL Credits Empty : IIO5",
"Counter": "0,1,2,3",
"EventCode": "0x23",
"EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO5_NCB",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "M2 BL Credits Empty : IIO5 : No vn0 and vna credits available to send to M2",
"UMask": "0x10",
"Unit": "M3UPI"
},
{
"BriefDescription": "M2 BL Credits Empty : All IIO targets for NCS are in single mask. ORs them together",
"Counter": "0,1,2,3",
"EventCode": "0x23",
"EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.NCS",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "M2 BL Credits Empty : All IIO targets for NCS are in single mask. ORs them together : No vn0 and vna credits available to send to M2",
"UMask": "0x40",
"Unit": "M3UPI"
},
{
"BriefDescription": "M2 BL Credits Empty : Selected M2p BL NCS credits",
"Counter": "0,1,2,3",
"EventCode": "0x23",
"EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.NCS_SEL",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "M2 BL Credits Empty : Selected M2p BL NCS credits : No vn0 and vna credits available to send to M2",
"UMask": "0x80",
"Unit": "M3UPI"
},
{
"BriefDescription": "M2 BL Credits Empty : IIO5",
"Counter": "0,1,2,3",
"EventCode": "0x23",
"EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.UBOX_NCB",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "M2 BL Credits Empty : IIO5 : No vn0 and vna credits available to send to M2",
"UMask": "0x20",
"Unit": "M3UPI"
},
{
"BriefDescription": "Miscellaneous Events (mostly from MS2IDI) : Number of cycles MBE is high for MS2IDI0",
"Counter": "0,1,2,3",
"EventCode": "0xE6",
"EventName": "UNC_M3UPI_MISC_EXTERNAL.MBE_INST0",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "Miscellaneous Events (mostly from MS2IDI) : Number of cycles MBE is high for MS2IDI1",
"Counter": "0,1,2,3",
"EventCode": "0xE6",
"EventName": "UNC_M3UPI_MISC_EXTERNAL.MBE_INST1",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "Multi Slot Flit Received : AD - Slot 0",
"Counter": "0,1,2,3",
"EventCode": "0x3E",
"EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AD_SLOT0",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Multi Slot Flit Received : AD - Slot 0 : Multi slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks for AK allocations)",
"UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "Multi Slot Flit Received : AD - Slot 1",
"Counter": "0,1,2,3",
"EventCode": "0x3E",
"EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AD_SLOT1",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Multi Slot Flit Received : AD - Slot 1 : Multi slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks for AK allocations)",
"UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "Multi Slot Flit Received : AD - Slot 2",
"Counter": "0,1,2,3",
"EventCode": "0x3E",
"EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AD_SLOT2",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Multi Slot Flit Received : AD - Slot 2 : Multi slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks for AK allocations)",
"UMask": "0x4",
"Unit": "M3UPI"
},
{
"BriefDescription": "Multi Slot Flit Received : AK - Slot 0",
"Counter": "0,1,2,3",
"EventCode": "0x3E",
"EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AK_SLOT0",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Multi Slot Flit Received : AK - Slot 0 : Multi slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks for AK allocations)",
"UMask": "0x10",
"Unit": "M3UPI"
},
{
"BriefDescription": "Multi Slot Flit Received : AK - Slot 2",
"Counter": "0,1,2,3",
"EventCode": "0x3E",
"EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AK_SLOT2",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Multi Slot Flit Received : AK - Slot 2 : Multi slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks for AK allocations)",
"UMask": "0x20",
"Unit": "M3UPI"
},
{
"BriefDescription": "Multi Slot Flit Received : BL - Slot 0",
"Counter": "0,1,2,3",
"EventCode": "0x3E",
"EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.BL_SLOT0",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Multi Slot Flit Received : BL - Slot 0 : Multi slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks for AK allocations)",
"UMask": "0x8",
"Unit": "M3UPI"
},
{
"BriefDescription": "Messages that bounced on the Horizontal Ring. : AD",
"Counter": "0,1,2,3",
"EventCode": "0xAC",
"EventName": "UNC_M3UPI_RING_BOUNCES_HORZ.AD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Messages that bounced on the Horizontal Ring. : AD : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.",
"UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "Messages that bounced on the Horizontal Ring. : AK",
"Counter": "0,1,2,3",
"EventCode": "0xAC",
"EventName": "UNC_M3UPI_RING_BOUNCES_HORZ.AK",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Messages that bounced on the Horizontal Ring. : AK : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.",
"UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "Messages that bounced on the Horizontal Ring. : BL",
"Counter": "0,1,2,3",
"EventCode": "0xAC",
"EventName": "UNC_M3UPI_RING_BOUNCES_HORZ.BL",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Messages that bounced on the Horizontal Ring. : BL : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.",
"UMask": "0x4",
"Unit": "M3UPI"
},
{
"BriefDescription": "Messages that bounced on the Horizontal Ring. : IV",
"Counter": "0,1,2,3",
"EventCode": "0xAC",
"EventName": "UNC_M3UPI_RING_BOUNCES_HORZ.IV",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Messages that bounced on the Horizontal Ring. : IV : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.",
"UMask": "0x8",
"Unit": "M3UPI"
},
{
"BriefDescription": "Messages that bounced on the Vertical Ring. : AD",
"Counter": "0,1,2,3",
"EventCode": "0xAA",
"EventName": "UNC_M3UPI_RING_BOUNCES_VERT.AD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Messages that bounced on the Vertical Ring. : AD : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
"UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "Messages that bounced on the Vertical Ring. : Acknowledgements to core",
"Counter": "0,1,2,3",
"EventCode": "0xAA",
"EventName": "UNC_M3UPI_RING_BOUNCES_VERT.AK",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Messages that bounced on the Vertical Ring. : Acknowledgements to core : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
"UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "Messages that bounced on the Vertical Ring.",
"Counter": "0,1,2,3",
"EventCode": "0xAA",
"EventName": "UNC_M3UPI_RING_BOUNCES_VERT.AKC",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Messages that bounced on the Vertical Ring. : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
"UMask": "0x10",
"Unit": "M3UPI"
},
{
"BriefDescription": "Messages that bounced on the Vertical Ring. : Data Responses to core",
"Counter": "0,1,2,3",
"EventCode": "0xAA",
"EventName": "UNC_M3UPI_RING_BOUNCES_VERT.BL",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Messages that bounced on the Vertical Ring. : Data Responses to core : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
"UMask": "0x4",
"Unit": "M3UPI"
},
{
"BriefDescription": "Messages that bounced on the Vertical Ring. : Snoops of processor's cache.",
"Counter": "0,1,2,3",
"EventCode": "0xAA",
"EventName": "UNC_M3UPI_RING_BOUNCES_VERT.IV",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Messages that bounced on the Vertical Ring. : Snoops of processor's cache. : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
"UMask": "0x8",
"Unit": "M3UPI"
},
{
"BriefDescription": "Sink Starvation on Horizontal Ring : AD",
"Counter": "0,1,2,3",
"EventCode": "0xAD",
"EventName": "UNC_M3UPI_RING_SINK_STARVED_HORZ.AD",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "Sink Starvation on Horizontal Ring : AK",
"Counter": "0,1,2,3",
"EventCode": "0xAD",
"EventName": "UNC_M3UPI_RING_SINK_STARVED_HORZ.AK",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "Sink Starvation on Horizontal Ring : Acknowledgements to Agent 1",
"Counter": "0,1,2,3",
"EventCode": "0xAD",
"EventName": "UNC_M3UPI_RING_SINK_STARVED_HORZ.AK_AG1",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "M3UPI"
},
{
"BriefDescription": "Sink Starvation on Horizontal Ring : BL",
"Counter": "0,1,2,3",
"EventCode": "0xAD",
"EventName": "UNC_M3UPI_RING_SINK_STARVED_HORZ.BL",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "M3UPI"
},
{
"BriefDescription": "Sink Starvation on Horizontal Ring : IV",
"Counter": "0,1,2,3",
"EventCode": "0xAD",
"EventName": "UNC_M3UPI_RING_SINK_STARVED_HORZ.IV",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "M3UPI"
},
{
"BriefDescription": "Sink Starvation on Vertical Ring : AD",
"Counter": "0,1,2,3",
"EventCode": "0xAB",
"EventName": "UNC_M3UPI_RING_SINK_STARVED_VERT.AD",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "Sink Starvation on Vertical Ring : Acknowledgements to core",
"Counter": "0,1,2,3",
"EventCode": "0xAB",
"EventName": "UNC_M3UPI_RING_SINK_STARVED_VERT.AK",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "Sink Starvation on Vertical Ring",
"Counter": "0,1,2,3",
"EventCode": "0xAB",
"EventName": "UNC_M3UPI_RING_SINK_STARVED_VERT.AKC",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "M3UPI"
},
{
"BriefDescription": "Sink Starvation on Vertical Ring : Data Responses to core",
"Counter": "0,1,2,3",
"EventCode": "0xAB",
"EventName": "UNC_M3UPI_RING_SINK_STARVED_VERT.BL",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "M3UPI"
},
{
"BriefDescription": "Sink Starvation on Vertical Ring : Snoops of processor's cache.",
"Counter": "0,1,2,3",
"EventCode": "0xAB",
"EventName": "UNC_M3UPI_RING_SINK_STARVED_VERT.IV",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "M3UPI"
},
{
"BriefDescription": "Source Throttle",
"Counter": "0,1,2,3",
"EventCode": "0xae",
"EventName": "UNC_M3UPI_RING_SRC_THRTL",
"Experimental": "1",
"PerPkg": "1",
"Unit": "M3UPI"
},
{
"BriefDescription": "Lost Arb for VN0 : REQ on AD",
"Counter": "0,1,2,3",
"EventCode": "0x4B",
"EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.AD_REQ",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Lost Arb for VN0 : REQ on AD : VN0 message requested but lost arbitration : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.",
"UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "Lost Arb for VN0 : RSP on AD",
"Counter": "0,1,2,3",
"EventCode": "0x4B",
"EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.AD_RSP",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Lost Arb for VN0 : RSP on AD : VN0 message requested but lost arbitration : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
"UMask": "0x4",
"Unit": "M3UPI"
},
{
"BriefDescription": "Lost Arb for VN0 : SNP on AD",
"Counter": "0,1,2,3",
"EventCode": "0x4B",
"EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.AD_SNP",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Lost Arb for VN0 : SNP on AD : VN0 message requested but lost arbitration : Snoops (SNP) messages on AD. SNP is used for outgoing snoops.",
"UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "Lost Arb for VN0 : NCB on BL",
"Counter": "0,1,2,3",
"EventCode": "0x4B",
"EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.BL_NCB",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Lost Arb for VN0 : NCB on BL : VN0 message requested but lost arbitration : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.",
"UMask": "0x20",
"Unit": "M3UPI"
},
{
"BriefDescription": "Lost Arb for VN0 : NCS on BL",
"Counter": "0,1,2,3",
"EventCode": "0x4B",
"EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.BL_NCS",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Lost Arb for VN0 : NCS on BL : VN0 message requested but lost arbitration : Non-Coherent Standard (NCS) messages on BL.",
"UMask": "0x40",
"Unit": "M3UPI"
},
{
"BriefDescription": "Lost Arb for VN0 : RSP on BL",
"Counter": "0,1,2,3",
"EventCode": "0x4B",
"EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.BL_RSP",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Lost Arb for VN0 : RSP on BL : VN0 message requested but lost arbitration : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
"UMask": "0x8",
"Unit": "M3UPI"
},
{
"BriefDescription": "Lost Arb for VN0 : WB on BL",
"Counter": "0,1,2,3",
"EventCode": "0x4B",
"EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.BL_WB",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Lost Arb for VN0 : WB on BL : VN0 message requested but lost arbitration : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
"UMask": "0x10",
"Unit": "M3UPI"
},
{
"BriefDescription": "Lost Arb for VN1 : REQ on AD",
"Counter": "0,1,2,3",
"EventCode": "0x4C",
"EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.AD_REQ",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Lost Arb for VN1 : REQ on AD : VN1 message requested but lost arbitration : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.",
"UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "Lost Arb for VN1 : RSP on AD",
"Counter": "0,1,2,3",
"EventCode": "0x4C",
"EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.AD_RSP",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Lost Arb for VN1 : RSP on AD : VN1 message requested but lost arbitration : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
"UMask": "0x4",
"Unit": "M3UPI"
},
{
"BriefDescription": "Lost Arb for VN1 : SNP on AD",
"Counter": "0,1,2,3",
"EventCode": "0x4C",
"EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.AD_SNP",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Lost Arb for VN1 : SNP on AD : VN1 message requested but lost arbitration : Snoops (SNP) messages on AD. SNP is used for outgoing snoops.",
"UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "Lost Arb for VN1 : NCB on BL",
"Counter": "0,1,2,3",
"EventCode": "0x4C",
"EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.BL_NCB",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Lost Arb for VN1 : NCB on BL : VN1 message requested but lost arbitration : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.",
"UMask": "0x20",
"Unit": "M3UPI"
},
{
"BriefDescription": "Lost Arb for VN1 : NCS on BL",
"Counter": "0,1,2,3",
"EventCode": "0x4C",
"EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.BL_NCS",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Lost Arb for VN1 : NCS on BL : VN1 message requested but lost arbitration : Non-Coherent Standard (NCS) messages on BL.",
"UMask": "0x40",
"Unit": "M3UPI"
},
{
"BriefDescription": "Lost Arb for VN1 : RSP on BL",
"Counter": "0,1,2,3",
"EventCode": "0x4C",
"EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.BL_RSP",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Lost Arb for VN1 : RSP on BL : VN1 message requested but lost arbitration : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
"UMask": "0x8",
"Unit": "M3UPI"
},
{
"BriefDescription": "Lost Arb for VN1 : WB on BL",
"Counter": "0,1,2,3",
"EventCode": "0x4C",
"EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.BL_WB",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Lost Arb for VN1 : WB on BL : VN1 message requested but lost arbitration : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
"UMask": "0x10",
"Unit": "M3UPI"
},
{
"BriefDescription": "Arb Miscellaneous : AD, BL Parallel Win VN0",
"Counter": "0,1,2,3",
"EventCode": "0x4D",
"EventName": "UNC_M3UPI_RxC_ARB_MISC.ADBL_PARALLEL_WIN_VN0",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Arb Miscellaneous : AD, BL Parallel Win VN0 : AD and BL messages won arbitration concurrently / in parallel",
"UMask": "0x10",
"Unit": "M3UPI"
},
{
"BriefDescription": "Arb Miscellaneous : AD, BL Parallel Win VN1",
"Counter": "0,1,2,3",
"EventCode": "0x4D",
"EventName": "UNC_M3UPI_RxC_ARB_MISC.ADBL_PARALLEL_WIN_VN1",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Arb Miscellaneous : AD, BL Parallel Win VN1 : AD and BL messages won arbitration concurrently / in parallel",
"UMask": "0x20",
"Unit": "M3UPI"
},
{
"BriefDescription": "Arb Miscellaneous : Max Parallel Win",
"Counter": "0,1,2,3",
"EventCode": "0x4D",
"EventName": "UNC_M3UPI_RxC_ARB_MISC.ALL_PARALLEL_WIN",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Arb Miscellaneous : Max Parallel Win : VN0 and VN1 arbitration sub-pipelines both produced AD and BL winners (maximum possible parallel winners)",
"UMask": "0x80",
"Unit": "M3UPI"
},
{
"BriefDescription": "Arb Miscellaneous : No Progress on Pending AD VN0",
"Counter": "0,1,2,3",
"EventCode": "0x4D",
"EventName": "UNC_M3UPI_RxC_ARB_MISC.NO_PROG_AD_VN0",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Arb Miscellaneous : No Progress on Pending AD VN0 : Arbitration stage made no progress on pending ad vn0 messages because slotting stage cannot accept new message",
"UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "Arb Miscellaneous : No Progress on Pending AD VN1",
"Counter": "0,1,2,3",
"EventCode": "0x4D",
"EventName": "UNC_M3UPI_RxC_ARB_MISC.NO_PROG_AD_VN1",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Arb Miscellaneous : No Progress on Pending AD VN1 : Arbitration stage made no progress on pending ad vn1 messages because slotting stage cannot accept new message",
"UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "Arb Miscellaneous : No Progress on Pending BL VN0",
"Counter": "0,1,2,3",
"EventCode": "0x4D",
"EventName": "UNC_M3UPI_RxC_ARB_MISC.NO_PROG_BL_VN0",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Arb Miscellaneous : No Progress on Pending BL VN0 : Arbitration stage made no progress on pending bl vn0 messages because slotting stage cannot accept new message",
"UMask": "0x4",
"Unit": "M3UPI"
},
{
"BriefDescription": "Arb Miscellaneous : No Progress on Pending BL VN1",
"Counter": "0,1,2,3",
"EventCode": "0x4D",
"EventName": "UNC_M3UPI_RxC_ARB_MISC.NO_PROG_BL_VN1",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Arb Miscellaneous : No Progress on Pending BL VN1 : Arbitration stage made no progress on pending bl vn1 messages because slotting stage cannot accept new message",
"UMask": "0x8",
"Unit": "M3UPI"
},
{
"BriefDescription": "Arb Miscellaneous : VN0, VN1 Parallel Win",
"Counter": "0,1,2,3",
"EventCode": "0x4D",
"EventName": "UNC_M3UPI_RxC_ARB_MISC.VN01_PARALLEL_WIN",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Arb Miscellaneous : VN0, VN1 Parallel Win : VN0 and VN1 arbitration sub-pipelines had parallel winners (at least one AD or BL on each side)",
"UMask": "0x40",
"Unit": "M3UPI"
},
{
"BriefDescription": "No Credits to Arb for VN0 : REQ on AD",
"Counter": "0,1,2,3",
"EventCode": "0x47",
"EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN0.AD_REQ",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "No Credits to Arb for VN0 : REQ on AD : VN0 message is blocked from requesting arbitration due to lack of remote UPI credits : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.",
"UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "No Credits to Arb for VN0 : RSP on AD",
"Counter": "0,1,2,3",
"EventCode": "0x47",
"EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN0.AD_RSP",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "No Credits to Arb for VN0 : RSP on AD : VN0 message is blocked from requesting arbitration due to lack of remote UPI credits : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
"UMask": "0x4",
"Unit": "M3UPI"
},
{
"BriefDescription": "No Credits to Arb for VN0 : SNP on AD",
"Counter": "0,1,2,3",
"EventCode": "0x47",
"EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN0.AD_SNP",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "No Credits to Arb for VN0 : SNP on AD : VN0 message is blocked from requesting arbitration due to lack of remote UPI credits : Snoops (SNP) messages on AD. SNP is used for outgoing snoops.",
"UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "No Credits to Arb for VN0 : NCB on BL",
"Counter": "0,1,2,3",
"EventCode": "0x47",
"EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN0.BL_NCB",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "No Credits to Arb for VN0 : NCB on BL : VN0 message is blocked from requesting arbitration due to lack of remote UPI credits : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.",
"UMask": "0x20",
"Unit": "M3UPI"
},
{
"BriefDescription": "No Credits to Arb for VN0 : NCS on BL",
"Counter": "0,1,2,3",
"EventCode": "0x47",
"EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN0.BL_NCS",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "No Credits to Arb for VN0 : NCS on BL : VN0 message is blocked from requesting arbitration due to lack of remote UPI credits : Non-Coherent Standard (NCS) messages on BL.",
"UMask": "0x40",
"Unit": "M3UPI"
},
{
"BriefDescription": "No Credits to Arb for VN0 : RSP on BL",
"Counter": "0,1,2,3",
"EventCode": "0x47",
"EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN0.BL_RSP",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "No Credits to Arb for VN0 : RSP on BL : VN0 message is blocked from requesting arbitration due to lack of remote UPI credits : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
"UMask": "0x8",
"Unit": "M3UPI"
},
{
"BriefDescription": "No Credits to Arb for VN0 : WB on BL",
"Counter": "0,1,2,3",
"EventCode": "0x47",
"EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN0.BL_WB",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "No Credits to Arb for VN0 : WB on BL : VN0 message is blocked from requesting arbitration due to lack of remote UPI credits : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
"UMask": "0x10",
"Unit": "M3UPI"
},
{
"BriefDescription": "No Credits to Arb for VN1 : REQ on AD",
"Counter": "0,1,2,3",
"EventCode": "0x48",
"EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN1.AD_REQ",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "No Credits to Arb for VN1 : REQ on AD : VN1 message is blocked from requesting arbitration due to lack of remote UPI credits : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.",
"UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "No Credits to Arb for VN1 : RSP on AD",
"Counter": "0,1,2,3",
"EventCode": "0x48",
"EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN1.AD_RSP",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "No Credits to Arb for VN1 : RSP on AD : VN1 message is blocked from requesting arbitration due to lack of remote UPI credits : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
"UMask": "0x4",
"Unit": "M3UPI"
},
{
"BriefDescription": "No Credits to Arb for VN1 : SNP on AD",
"Counter": "0,1,2,3",
"EventCode": "0x48",
"EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN1.AD_SNP",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "No Credits to Arb for VN1 : SNP on AD : VN1 message is blocked from requesting arbitration due to lack of remote UPI credits : Snoops (SNP) messages on AD. SNP is used for outgoing snoops.",
"UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "No Credits to Arb for VN1 : NCB on BL",
"Counter": "0,1,2,3",
"EventCode": "0x48",
"EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN1.BL_NCB",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "No Credits to Arb for VN1 : NCB on BL : VN1 message is blocked from requesting arbitration due to lack of remote UPI credits : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.",
"UMask": "0x20",
"Unit": "M3UPI"
},
{
"BriefDescription": "No Credits to Arb for VN1 : NCS on BL",
"Counter": "0,1,2,3",
"EventCode": "0x48",
"EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN1.BL_NCS",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "No Credits to Arb for VN1 : NCS on BL : VN1 message is blocked from requesting arbitration due to lack of remote UPI credits : Non-Coherent Standard (NCS) messages on BL.",
"UMask": "0x40",
"Unit": "M3UPI"
},
{
"BriefDescription": "No Credits to Arb for VN1 : RSP on BL",
"Counter": "0,1,2,3",
"EventCode": "0x48",
"EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN1.BL_RSP",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "No Credits to Arb for VN1 : RSP on BL : VN1 message is blocked from requesting arbitration due to lack of remote UPI credits : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
"UMask": "0x8",
"Unit": "M3UPI"
},
{
"BriefDescription": "No Credits to Arb for VN1 : WB on BL",
"Counter": "0,1,2,3",
"EventCode": "0x48",
"EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN1.BL_WB",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "No Credits to Arb for VN1 : WB on BL : VN1 message is blocked from requesting arbitration due to lack of remote UPI credits : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
"UMask": "0x10",
"Unit": "M3UPI"
},
{
"BriefDescription": "Can't Arb for VN0 : REQ on AD",
"Counter": "0,1,2,3",
"EventCode": "0x49",
"EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN0.AD_REQ",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Can't Arb for VN0 : REQ on AD : VN0 message was not able to request arbitration while some other message won arbitration : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.",
"UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "Can't Arb for VN0 : RSP on AD",
"Counter": "0,1,2,3",
"EventCode": "0x49",
"EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN0.AD_RSP",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Can't Arb for VN0 : RSP on AD : VN0 message was not able to request arbitration while some other message won arbitration : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
"UMask": "0x4",
"Unit": "M3UPI"
},
{
"BriefDescription": "Can't Arb for VN0 : SNP on AD",
"Counter": "0,1,2,3",
"EventCode": "0x49",
"EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN0.AD_SNP",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Can't Arb for VN0 : SNP on AD : VN0 message was not able to request arbitration while some other message won arbitration : Snoops (SNP) messages on AD. SNP is used for outgoing snoops.",
"UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "Can't Arb for VN0 : NCB on BL",
"Counter": "0,1,2,3",
"EventCode": "0x49",
"EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN0.BL_NCB",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Can't Arb for VN0 : NCB on BL : VN0 message was not able to request arbitration while some other message won arbitration : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.",
"UMask": "0x20",
"Unit": "M3UPI"
},
{
"BriefDescription": "Can't Arb for VN0 : NCS on BL",
"Counter": "0,1,2,3",
"EventCode": "0x49",
"EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN0.BL_NCS",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Can't Arb for VN0 : NCS on BL : VN0 message was not able to request arbitration while some other message won arbitration : Non-Coherent Standard (NCS) messages on BL.",
"UMask": "0x40",
"Unit": "M3UPI"
},
{
"BriefDescription": "Can't Arb for VN0 : RSP on BL",
"Counter": "0,1,2,3",
"EventCode": "0x49",
"EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN0.BL_RSP",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Can't Arb for VN0 : RSP on BL : VN0 message was not able to request arbitration while some other message won arbitration : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
"UMask": "0x8",
"Unit": "M3UPI"
},
{
"BriefDescription": "Can't Arb for VN0 : WB on BL",
"Counter": "0,1,2,3",
"EventCode": "0x49",
"EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN0.BL_WB",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Can't Arb for VN0 : WB on BL : VN0 message was not able to request arbitration while some other message won arbitration : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
"UMask": "0x10",
"Unit": "M3UPI"
},
{
"BriefDescription": "Can't Arb for VN1 : REQ on AD",
"Counter": "0,1,2,3",
"EventCode": "0x4A",
"EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN1.AD_REQ",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Can't Arb for VN1 : REQ on AD : VN1 message was not able to request arbitration while some other message won arbitration : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.",
"UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "Can't Arb for VN1 : RSP on AD",
"Counter": "0,1,2,3",
"EventCode": "0x4A",
"EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN1.AD_RSP",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Can't Arb for VN1 : RSP on AD : VN1 message was not able to request arbitration while some other message won arbitration : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
"UMask": "0x4",
"Unit": "M3UPI"
},
{
"BriefDescription": "Can't Arb for VN1 : SNP on AD",
"Counter": "0,1,2,3",
"EventCode": "0x4A",
"EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN1.AD_SNP",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Can't Arb for VN1 : SNP on AD : VN1 message was not able to request arbitration while some other message won arbitration : Snoops (SNP) messages on AD. SNP is used for outgoing snoops.",
"UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "Can't Arb for VN1 : NCB on BL",
"Counter": "0,1,2,3",
"EventCode": "0x4A",
"EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN1.BL_NCB",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Can't Arb for VN1 : NCB on BL : VN1 message was not able to request arbitration while some other message won arbitration : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.",
"UMask": "0x20",
"Unit": "M3UPI"
},
{
"BriefDescription": "Can't Arb for VN1 : NCS on BL",
"Counter": "0,1,2,3",
"EventCode": "0x4A",
"EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN1.BL_NCS",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Can't Arb for VN1 : NCS on BL : VN1 message was not able to request arbitration while some other message won arbitration : Non-Coherent Standard (NCS) messages on BL.",
"UMask": "0x40",
"Unit": "M3UPI"
},
{
"BriefDescription": "Can't Arb for VN1 : RSP on BL",
"Counter": "0,1,2,3",
"EventCode": "0x4A",
"EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN1.BL_RSP",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Can't Arb for VN1 : RSP on BL : VN1 message was not able to request arbitration while some other message won arbitration : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
"UMask": "0x8",
"Unit": "M3UPI"
},
{
"BriefDescription": "Can't Arb for VN1 : WB on BL",
"Counter": "0,1,2,3",
"EventCode": "0x4A",
"EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN1.BL_WB",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Can't Arb for VN1 : WB on BL : VN1 message was not able to request arbitration while some other message won arbitration : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
"UMask": "0x10",
"Unit": "M3UPI"
},
{
"BriefDescription": "Ingress Queue Bypasses : AD to Slot 0 on BL Arb",
"Counter": "0,1,2",
"EventCode": "0x40",
"EventName": "UNC_M3UPI_RxC_BYPASSED.AD_S0_BL_ARB",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Ingress Queue Bypasses : AD to Slot 0 on BL Arb : Number of times message is bypassed around the Ingress Queue : AD is taking bypass to slot 0 of independent flit while bl message is in arbitration",
"UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "Ingress Queue Bypasses : AD to Slot 0 on Idle",
"Counter": "0,1,2",
"EventCode": "0x40",
"EventName": "UNC_M3UPI_RxC_BYPASSED.AD_S0_IDLE",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Ingress Queue Bypasses : AD to Slot 0 on Idle : Number of times message is bypassed around the Ingress Queue : AD is taking bypass to slot 0 of independent flit while pipeline is idle",
"UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "Ingress Queue Bypasses : AD + BL to Slot 1",
"Counter": "0,1,2",
"EventCode": "0x40",
"EventName": "UNC_M3UPI_RxC_BYPASSED.AD_S1_BL_SLOT",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Ingress Queue Bypasses : AD + BL to Slot 1 : Number of times message is bypassed around the Ingress Queue : AD is taking bypass to flit slot 1 while merging with bl message in same flit",
"UMask": "0x4",
"Unit": "M3UPI"
},
{
"BriefDescription": "Ingress Queue Bypasses : AD + BL to Slot 2",
"Counter": "0,1,2",
"EventCode": "0x40",
"EventName": "UNC_M3UPI_RxC_BYPASSED.AD_S2_BL_SLOT",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Ingress Queue Bypasses : AD + BL to Slot 2 : Number of times message is bypassed around the Ingress Queue : AD is taking bypass to flit slot 2 while merging with bl message in same flit",
"UMask": "0x8",
"Unit": "M3UPI"
},
{
"BriefDescription": "Miscellaneous Credit Events : Any In BGF FIFO",
"Counter": "0,1,2,3",
"EventCode": "0x5F",
"EventName": "UNC_M3UPI_RxC_CRD_MISC.ANY_BGF_FIFO",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Miscellaneous Credit Events : Any In BGF FIFO : Indication that at least one packet (flit) is in the bgf (fifo only)",
"UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "Miscellaneous Credit Events : Any in BGF Path",
"Counter": "0,1,2,3",
"EventCode": "0x5F",
"EventName": "UNC_M3UPI_RxC_CRD_MISC.ANY_BGF_PATH",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Miscellaneous Credit Events : Any in BGF Path : Indication that at least one packet (flit) is in the bgf path (i.e. pipe to fifo)",
"UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "Miscellaneous Credit Events",
"Counter": "0,1,2,3",
"EventCode": "0x5F",
"EventName": "UNC_M3UPI_RxC_CRD_MISC.LT1_FOR_D2K",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Miscellaneous Credit Events : d2k credit count is less than 1",
"UMask": "0x10",
"Unit": "M3UPI"
},
{
"BriefDescription": "Miscellaneous Credit Events",
"Counter": "0,1,2,3",
"EventCode": "0x5F",
"EventName": "UNC_M3UPI_RxC_CRD_MISC.LT2_FOR_D2K",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Miscellaneous Credit Events : d2k credit count is less than 2",
"UMask": "0x20",
"Unit": "M3UPI"
},
{
"BriefDescription": "Miscellaneous Credit Events : No D2K For Arb",
"Counter": "0,1,2,3",
"EventCode": "0x5F",
"EventName": "UNC_M3UPI_RxC_CRD_MISC.VN0_NO_D2K_FOR_ARB",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Miscellaneous Credit Events : No D2K For Arb : VN0 BL RSP message was blocked from arbitration request due to lack of D2K CMP credit",
"UMask": "0x4",
"Unit": "M3UPI"
},
{
"BriefDescription": "Miscellaneous Credit Events",
"Counter": "0,1,2,3",
"EventCode": "0x5F",
"EventName": "UNC_M3UPI_RxC_CRD_MISC.VN1_NO_D2K_FOR_ARB",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Miscellaneous Credit Events : VN1 BL RSP message was blocked from arbitration request due to lack of D2K CMP credits",
"UMask": "0x8",
"Unit": "M3UPI"
},
{
"BriefDescription": "Credit Occupancy : Credits Consumed",
"Counter": "0,1,2,3",
"EventCode": "0x60",
"EventName": "UNC_M3UPI_RxC_CRD_OCC.CONSUMED",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Credit Occupancy : Credits Consumed : number of remote vna credits consumed per cycle",
"UMask": "0x80",
"Unit": "M3UPI"
},
{
"BriefDescription": "Credit Occupancy : D2K Credits",
"Counter": "0,1,2,3",
"EventCode": "0x60",
"EventName": "UNC_M3UPI_RxC_CRD_OCC.D2K_CRD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Credit Occupancy : D2K Credits : D2K completion fifo credit occupancy (credits in use), accumulated across all cycles",
"UMask": "0x10",
"Unit": "M3UPI"
},
{
"BriefDescription": "Credit Occupancy : Packets in BGF FIFO",
"Counter": "0,1,2,3",
"EventCode": "0x60",
"EventName": "UNC_M3UPI_RxC_CRD_OCC.FLITS_IN_FIFO",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Credit Occupancy : Packets in BGF FIFO : Occupancy of m3upi ingress -> upi link layer bgf; packets (flits) in fifo",
"UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "Credit Occupancy : Packets in BGF Path",
"Counter": "0,1,2,3",
"EventCode": "0x60",
"EventName": "UNC_M3UPI_RxC_CRD_OCC.FLITS_IN_PATH",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Credit Occupancy : Packets in BGF Path : Occupancy of m3upi ingress -> upi link layer bgf; packets (flits) in path (i.e. pipe to fifo or fifo)",
"UMask": "0x4",
"Unit": "M3UPI"
},
{
"BriefDescription": "Credit Occupancy",
"Counter": "0,1,2,3",
"EventCode": "0x60",
"EventName": "UNC_M3UPI_RxC_CRD_OCC.P1P_FIFO",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Credit Occupancy : count of bl messages in pump-1-pending state, in completion fifo only",
"UMask": "0x40",
"Unit": "M3UPI"
},
{
"BriefDescription": "Credit Occupancy",
"Counter": "0,1,2,3",
"EventCode": "0x60",
"EventName": "UNC_M3UPI_RxC_CRD_OCC.P1P_TOTAL",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Credit Occupancy : count of bl messages in pump-1-pending state, in marker table and in fifo",
"UMask": "0x20",
"Unit": "M3UPI"
},
{
"BriefDescription": "Credit Occupancy : Transmit Credits",
"Counter": "0,1,2,3",
"EventCode": "0x60",
"EventName": "UNC_M3UPI_RxC_CRD_OCC.TxQ_CRD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Credit Occupancy : Transmit Credits : Link layer transmit queue credit occupancy (credits in use), accumulated across all cycles",
"UMask": "0x8",
"Unit": "M3UPI"
},
{
"BriefDescription": "Credit Occupancy : VNA In Use",
"Counter": "0,1,2,3",
"EventCode": "0x60",
"EventName": "UNC_M3UPI_RxC_CRD_OCC.VNA_IN_USE",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Credit Occupancy : VNA In Use : Remote UPI VNA credit occupancy (number of credits in use), accumulated across all cycles",
"UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty : REQ on AD",
"Counter": "0,1,2,3",
"EventCode": "0x43",
"EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.AD_REQ",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty : REQ on AD : Counts the number of cycles when the UPI Ingress is not empty. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters. : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.",
"UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty : RSP on AD",
"Counter": "0,1,2,3",
"EventCode": "0x43",
"EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.AD_RSP",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty : RSP on AD : Counts the number of cycles when the UPI Ingress is not empty. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters. : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
"UMask": "0x4",
"Unit": "M3UPI"
},
{
"BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty : SNP on AD",
"Counter": "0,1,2,3",
"EventCode": "0x43",
"EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.AD_SNP",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty : SNP on AD : Counts the number of cycles when the UPI Ingress is not empty. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters. : Snoops (SNP) messages on AD. SNP is used for outgoing snoops.",
"UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty : NCB on BL",
"Counter": "0,1,2,3",
"EventCode": "0x43",
"EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.BL_NCB",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty : NCB on BL : Counts the number of cycles when the UPI Ingress is not empty. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters. : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.",
"UMask": "0x20",
"Unit": "M3UPI"
},
{
"BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty : NCS on BL",
"Counter": "0,1,2,3",
"EventCode": "0x43",
"EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.BL_NCS",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty : NCS on BL : Counts the number of cycles when the UPI Ingress is not empty. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters. : Non-Coherent Standard (NCS) messages on BL.",
"UMask": "0x40",
"Unit": "M3UPI"
},
{
"BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty : RSP on BL",
"Counter": "0,1,2,3",
"EventCode": "0x43",
"EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.BL_RSP",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty : RSP on BL : Counts the number of cycles when the UPI Ingress is not empty. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters. : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
"UMask": "0x8",
"Unit": "M3UPI"
},
{
"BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty : WB on BL",
"Counter": "0,1,2,3",
"EventCode": "0x43",
"EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.BL_WB",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty : WB on BL : Counts the number of cycles when the UPI Ingress is not empty. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters. : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
"UMask": "0x10",
"Unit": "M3UPI"
},
{
"BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty : REQ on AD",
"Counter": "0,1,2,3",
"EventCode": "0x44",
"EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.AD_REQ",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty : REQ on AD : Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.",
"UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty : RSP on AD",
"Counter": "0,1,2,3",
"EventCode": "0x44",
"EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.AD_RSP",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty : RSP on AD : Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
"UMask": "0x4",
"Unit": "M3UPI"
},
{
"BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty : SNP on AD",
"Counter": "0,1,2,3",
"EventCode": "0x44",
"EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.AD_SNP",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty : SNP on AD : Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Snoops (SNP) messages on AD. SNP is used for outgoing snoops.",
"UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty : NCB on BL",
"Counter": "0,1,2,3",
"EventCode": "0x44",
"EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.BL_NCB",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty : NCB on BL : Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.",
"UMask": "0x20",
"Unit": "M3UPI"
},
{
"BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty : NCS on BL",
"Counter": "0,1,2,3",
"EventCode": "0x44",
"EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.BL_NCS",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty : NCS on BL : Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Non-Coherent Standard (NCS) messages on BL.",
"UMask": "0x40",
"Unit": "M3UPI"
},
{
"BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty : RSP on BL",
"Counter": "0,1,2,3",
"EventCode": "0x44",
"EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.BL_RSP",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty : RSP on BL : Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
"UMask": "0x8",
"Unit": "M3UPI"
},
{
"BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty : WB on BL",
"Counter": "0,1,2,3",
"EventCode": "0x44",
"EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.BL_WB",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty : WB on BL : Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
"UMask": "0x10",
"Unit": "M3UPI"
},
{
"BriefDescription": "Data Flit Not Sent : All",
"Counter": "0,1,2,3",
"EventCode": "0x55",
"EventName": "UNC_M3UPI_RxC_DATA_FLITS_NOT_SENT.ALL",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Data Flit Not Sent : All : Data flit is ready for transmission but could not be sent : data flit is ready for transmission but could not be sent for any reason, e.g. low credits, low tsv, stall injection",
"UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "Data Flit Not Sent : No BGF Credits",
"Counter": "0,1,2,3",
"EventCode": "0x55",
"EventName": "UNC_M3UPI_RxC_DATA_FLITS_NOT_SENT.NO_BGF",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Data Flit Not Sent : No BGF Credits : Data flit is ready for transmission but could not be sent",
"UMask": "0x8",
"Unit": "M3UPI"
},
{
"BriefDescription": "Data Flit Not Sent : No TxQ Credits",
"Counter": "0,1,2,3",
"EventCode": "0x55",
"EventName": "UNC_M3UPI_RxC_DATA_FLITS_NOT_SENT.NO_TXQ",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Data Flit Not Sent : No TxQ Credits : Data flit is ready for transmission but could not be sent",
"UMask": "0x10",
"Unit": "M3UPI"
},
{
"BriefDescription": "Data Flit Not Sent : TSV High",
"Counter": "0,1,2,3",
"EventCode": "0x55",
"EventName": "UNC_M3UPI_RxC_DATA_FLITS_NOT_SENT.TSV_HI",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Data Flit Not Sent : TSV High : Data flit is ready for transmission but could not be sent : data flit is ready for transmission but was not sent while tsv high",
"UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "Data Flit Not Sent : Cycle valid for Flit",
"Counter": "0,1,2,3",
"EventCode": "0x55",
"EventName": "UNC_M3UPI_RxC_DATA_FLITS_NOT_SENT.VALID_FOR_FLIT",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Data Flit Not Sent : Cycle valid for Flit : Data flit is ready for transmission but could not be sent : data flit is ready for transmission but was not sent while cycle is valid for flit transmission",
"UMask": "0x4",
"Unit": "M3UPI"
},
{
"BriefDescription": "Generating BL Data Flit Sequence : Wait on Pump 0",
"Counter": "0,1,2,3",
"EventCode": "0x57",
"EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P0_WAIT",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Generating BL Data Flit Sequence : Wait on Pump 0 : generating bl data flit sequence; waiting for data pump 0",
"UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "Generating BL Data Flit Sequence",
"Counter": "0,1,2,3",
"EventCode": "0x57",
"EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_AT_LIMIT",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Generating BL Data Flit Sequence : pump-1-pending logic is at capacity (pending table plus completion fifo at limit)",
"UMask": "0x10",
"Unit": "M3UPI"
},
{
"BriefDescription": "Generating BL Data Flit Sequence",
"Counter": "0,1,2,3",
"EventCode": "0x57",
"EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_BUSY",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Generating BL Data Flit Sequence : pump-1-pending logic is tracking at least one message",
"UMask": "0x8",
"Unit": "M3UPI"
},
{
"BriefDescription": "Generating BL Data Flit Sequence",
"Counter": "0,1,2,3",
"EventCode": "0x57",
"EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_FIFO_FULL",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Generating BL Data Flit Sequence : pump-1-pending completion fifo is full",
"UMask": "0x40",
"Unit": "M3UPI"
},
{
"BriefDescription": "Generating BL Data Flit Sequence",
"Counter": "0,1,2,3",
"EventCode": "0x57",
"EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_HOLD_P0",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Generating BL Data Flit Sequence : pump-1-pending logic is at or near capacity, such that pump-0-only bl messages are getting stalled in slotting stage",
"UMask": "0x20",
"Unit": "M3UPI"
},
{
"BriefDescription": "Generating BL Data Flit Sequence",
"Counter": "0,1,2,3",
"EventCode": "0x57",
"EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_TO_LIMBO",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Generating BL Data Flit Sequence : a bl message finished but is in limbo and moved to pump-1-pending logic",
"UMask": "0x4",
"Unit": "M3UPI"
},
{
"BriefDescription": "Generating BL Data Flit Sequence : Wait on Pump 1",
"Counter": "0,1,2,3",
"EventCode": "0x57",
"EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1_WAIT",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Generating BL Data Flit Sequence : Wait on Pump 1 : generating bl data flit sequence; waiting for data pump 1",
"UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "UNC_M3UPI_RxC_FLITS_MISC.S2REQ_IN_HOLDOFF",
"Counter": "0,1,2,3",
"EventCode": "0x58",
"EventName": "UNC_M3UPI_RxC_FLITS_MISC.S2REQ_IN_HOLDOFF",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": ": slot 2 request naturally serviced during hold-off period",
"UMask": "0x4",
"Unit": "M3UPI"
},
{
"BriefDescription": "UNC_M3UPI_RxC_FLITS_MISC.S2REQ_IN_SERVICE",
"Counter": "0,1,2,3",
"EventCode": "0x58",
"EventName": "UNC_M3UPI_RxC_FLITS_MISC.S2REQ_IN_SERVICE",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": ": slot 2 request forcibly serviced during service window",
"UMask": "0x8",
"Unit": "M3UPI"
},
{
"BriefDescription": "UNC_M3UPI_RxC_FLITS_MISC.S2REQ_RECEIVED",
"Counter": "0,1,2,3",
"EventCode": "0x58",
"EventName": "UNC_M3UPI_RxC_FLITS_MISC.S2REQ_RECEIVED",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": ": slot 2 request received from link layer while idle (with no slot 2 request active immediately prior)",
"UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "UNC_M3UPI_RxC_FLITS_MISC.S2REQ_WITHDRAWN",
"Counter": "0,1,2,3",
"EventCode": "0x58",
"EventName": "UNC_M3UPI_RxC_FLITS_MISC.S2REQ_WITHDRAWN",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": ": slot 2 request withdrawn during hold-off period or service window",
"UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "Slotting BL Message Into Header Flit : All",
"Counter": "0,1,2,3",
"EventCode": "0x56",
"EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.ALL",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "Slotting BL Message Into Header Flit : Needs Data Flit",
"Counter": "0,1,2,3",
"EventCode": "0x56",
"EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.NEED_DATA",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Slotting BL Message Into Header Flit : Needs Data Flit : BL message requires data flit sequence",
"UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "Slotting BL Message Into Header Flit : Wait on Pump 0",
"Counter": "0,1,2,3",
"EventCode": "0x56",
"EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P0_WAIT",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Slotting BL Message Into Header Flit : Wait on Pump 0 : Waiting for header pump 0",
"UMask": "0x4",
"Unit": "M3UPI"
},
{
"BriefDescription": "Slotting BL Message Into Header Flit : Don't Need Pump 1",
"Counter": "0,1,2,3",
"EventCode": "0x56",
"EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P1_NOT_REQ",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Slotting BL Message Into Header Flit : Don't Need Pump 1 : Header pump 1 is not required for flit",
"UMask": "0x10",
"Unit": "M3UPI"
},
{
"BriefDescription": "Slotting BL Message Into Header Flit : Don't Need Pump 1 - Bubble",
"Counter": "0,1,2,3",
"EventCode": "0x56",
"EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P1_NOT_REQ_BUT_BUBBLE",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Slotting BL Message Into Header Flit : Don't Need Pump 1 - Bubble : Header pump 1 is not required for flit but flit transmission delayed",
"UMask": "0x20",
"Unit": "M3UPI"
},
{
"BriefDescription": "Slotting BL Message Into Header Flit : Don't Need Pump 1 - Not Avail",
"Counter": "0,1,2,3",
"EventCode": "0x56",
"EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P1_NOT_REQ_NOT_AVAIL",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Slotting BL Message Into Header Flit : Don't Need Pump 1 - Not Avail : Header pump 1 is not required for flit and not available",
"UMask": "0x40",
"Unit": "M3UPI"
},
{
"BriefDescription": "Slotting BL Message Into Header Flit : Wait on Pump 1",
"Counter": "0,1,2,3",
"EventCode": "0x56",
"EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P1_WAIT",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Slotting BL Message Into Header Flit : Wait on Pump 1 : Waiting for header pump 1",
"UMask": "0x8",
"Unit": "M3UPI"
},
{
"BriefDescription": "Flit Gen - Header 1 : Accumulate",
"Counter": "0,1,2,3",
"EventCode": "0x51",
"EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.ACCUM",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Flit Gen - Header 1 : Accumulate : Events related to Header Flit Generation - Set 1 : Header flit slotting control state machine is in any accumulate state; multi-message flit may be assembled over multiple cycles",
"UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "Flit Gen - Header 1 : Accumulate Ready",
"Counter": "0,1,2,3",
"EventCode": "0x51",
"EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.ACCUM_READ",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Flit Gen - Header 1 : Accumulate Ready : Events related to Header Flit Generation - Set 1 : header flit slotting control state machine is in accum_ready state; flit is ready to send but transmission is blocked; more messages may be slotted into flit",
"UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "Flit Gen - Header 1 : Accumulate Wasted",
"Counter": "0,1,2,3",
"EventCode": "0x51",
"EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.ACCUM_WASTED",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Flit Gen - Header 1 : Accumulate Wasted : Events related to Header Flit Generation - Set 1 : Flit is being assembled over multiple cycles, but no additional message is being slotted into flit in current cycle; accumulate cycle is wasted",
"UMask": "0x4",
"Unit": "M3UPI"
},
{
"BriefDescription": "Flit Gen - Header 1 : Run-Ahead - Blocked",
"Counter": "0,1,2,3",
"EventCode": "0x51",
"EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.AHEAD_BLOCKED",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Flit Gen - Header 1 : Run-Ahead - Blocked : Events related to Header Flit Generation - Set 1 : Header flit slotting entered run-ahead state; new header flit is started while transmission of prior, fully assembled flit is blocked",
"UMask": "0x8",
"Unit": "M3UPI"
},
{
"BriefDescription": "Flit Gen - Header 1",
"Counter": "0,1,2,3",
"EventCode": "0x51",
"EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.AHEAD_MSG1_AFTER",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Flit Gen - Header 1 : Events related to Header Flit Generation - Set 1 : run-ahead mode: message was slotted only after run-ahead was over; run-ahead mode definitely wasted",
"UMask": "0x80",
"Unit": "M3UPI"
},
{
"BriefDescription": "Flit Gen - Header 1 : Run-Ahead - Message",
"Counter": "0,1,2,3",
"EventCode": "0x51",
"EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.AHEAD_MSG1_DURING",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Flit Gen - Header 1 : Run-Ahead - Message : Events related to Header Flit Generation - Set 1 : run-ahead mode: one message slotted during run-ahead",
"UMask": "0x10",
"Unit": "M3UPI"
},
{
"BriefDescription": "Flit Gen - Header 1",
"Counter": "0,1,2,3",
"EventCode": "0x51",
"EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.AHEAD_MSG2_AFTER",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Flit Gen - Header 1 : Events related to Header Flit Generation - Set 1 : run-ahead mode: second message slotted immediately after run-ahead; potential run-ahead success",
"UMask": "0x20",
"Unit": "M3UPI"
},
{
"BriefDescription": "Flit Gen - Header 1",
"Counter": "0,1,2,3",
"EventCode": "0x51",
"EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.AHEAD_MSG2_SENT",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Flit Gen - Header 1 : Events related to Header Flit Generation - Set 1 : run-ahead mode: two (or three) message flit sent immediately after run-ahead; complete run-ahead success",
"UMask": "0x40",
"Unit": "M3UPI"
},
{
"BriefDescription": "Flit Gen - Header 2 : Parallel Ok",
"Counter": "0,1,2,3",
"EventCode": "0x52",
"EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR2.PAR",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Flit Gen - Header 2 : Parallel Ok : Events related to Header Flit Generation - Set 2 : new header flit construction may proceed in parallel with data flit sequence",
"UMask": "0x4",
"Unit": "M3UPI"
},
{
"BriefDescription": "Flit Gen - Header 2 : Parallel Flit Finished",
"Counter": "0,1,2,3",
"EventCode": "0x52",
"EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR2.PAR_FLIT",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Flit Gen - Header 2 : Parallel Flit Finished : Events related to Header Flit Generation - Set 2 : header flit finished assembly in parallel with data flit sequence",
"UMask": "0x10",
"Unit": "M3UPI"
},
{
"BriefDescription": "Flit Gen - Header 2 : Parallel Message",
"Counter": "0,1,2,3",
"EventCode": "0x52",
"EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR2.PAR_MSG",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Flit Gen - Header 2 : Parallel Message : Events related to Header Flit Generation - Set 2 : message is slotted into header flit in parallel with data flit sequence",
"UMask": "0x8",
"Unit": "M3UPI"
},
{
"BriefDescription": "Flit Gen - Header 2 : Rate-matching Stall",
"Counter": "0,1,2,3",
"EventCode": "0x52",
"EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR2.RMSTALL",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Flit Gen - Header 2 : Rate-matching Stall : Events related to Header Flit Generation - Set 2 : Rate-matching stall injected",
"UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "Flit Gen - Header 2 : Rate-matching Stall - No Message",
"Counter": "0,1,2,3",
"EventCode": "0x52",
"EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR2.RMSTALL_NOMSG",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Flit Gen - Header 2 : Rate-matching Stall - No Message : Events related to Header Flit Generation - Set 2 : Rate matching stall injected, but no additional message slotted during stall cycle",
"UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "Sent Header Flit : One Message",
"Counter": "0,1,2,3",
"EventCode": "0x54",
"EventName": "UNC_M3UPI_RxC_HDR_FLITS_SENT.1_MSG",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Sent Header Flit : One Message : One message in flit; VNA or non-VNA flit",
"UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "Sent Header Flit : One Message in non-VNA",
"Counter": "0,1,2,3",
"EventCode": "0x54",
"EventName": "UNC_M3UPI_RxC_HDR_FLITS_SENT.1_MSG_VNX",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Sent Header Flit : One Message in non-VNA : One message in flit; non-VNA flit",
"UMask": "0x8",
"Unit": "M3UPI"
},
{
"BriefDescription": "Sent Header Flit : Two Messages",
"Counter": "0,1,2,3",
"EventCode": "0x54",
"EventName": "UNC_M3UPI_RxC_HDR_FLITS_SENT.2_MSGS",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Sent Header Flit : Two Messages : Two messages in flit; VNA flit",
"UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "Sent Header Flit : Three Messages",
"Counter": "0,1,2,3",
"EventCode": "0x54",
"EventName": "UNC_M3UPI_RxC_HDR_FLITS_SENT.3_MSGS",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Sent Header Flit : Three Messages : Three messages in flit; VNA flit",
"UMask": "0x4",
"Unit": "M3UPI"
},
{
"BriefDescription": "Sent Header Flit : One Slot Taken",
"Counter": "0,1,2,3",
"EventCode": "0x54",
"EventName": "UNC_M3UPI_RxC_HDR_FLITS_SENT.SLOTS_1",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "M3UPI"
},
{
"BriefDescription": "Sent Header Flit : Two Slots Taken",
"Counter": "0,1,2,3",
"EventCode": "0x54",
"EventName": "UNC_M3UPI_RxC_HDR_FLITS_SENT.SLOTS_2",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "M3UPI"
},
{
"BriefDescription": "Sent Header Flit : All Slots Taken",
"Counter": "0,1,2,3",
"EventCode": "0x54",
"EventName": "UNC_M3UPI_RxC_HDR_FLITS_SENT.SLOTS_3",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x40",
"Unit": "M3UPI"
},
{
"BriefDescription": "Header Not Sent : All",
"Counter": "0,1,2,3",
"EventCode": "0x53",
"EventName": "UNC_M3UPI_RxC_HDR_FLIT_NOT_SENT.ALL",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Header Not Sent : All : header flit is ready for transmission but could not be sent : header flit is ready for transmission but could not be sent for any reason, e.g. no credits, low tsv, stall injection",
"UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "Header Not Sent : No BGF Credits",
"Counter": "0,1,2,3",
"EventCode": "0x53",
"EventName": "UNC_M3UPI_RxC_HDR_FLIT_NOT_SENT.NO_BGF_CRD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Header Not Sent : No BGF Credits : header flit is ready for transmission but could not be sent : No BGF credits available",
"UMask": "0x8",
"Unit": "M3UPI"
},
{
"BriefDescription": "Header Not Sent : No BGF Credits + No Extra Message Slotted",
"Counter": "0,1,2,3",
"EventCode": "0x53",
"EventName": "UNC_M3UPI_RxC_HDR_FLIT_NOT_SENT.NO_BGF_NO_MSG",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Header Not Sent : No BGF Credits + No Extra Message Slotted : header flit is ready for transmission but could not be sent : No BGF credits available; no additional message slotted into flit",
"UMask": "0x20",
"Unit": "M3UPI"
},
{
"BriefDescription": "Header Not Sent : No TxQ Credits",
"Counter": "0,1,2,3",
"EventCode": "0x53",
"EventName": "UNC_M3UPI_RxC_HDR_FLIT_NOT_SENT.NO_TXQ_CRD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Header Not Sent : No TxQ Credits : header flit is ready for transmission but could not be sent : No TxQ credits available",
"UMask": "0x10",
"Unit": "M3UPI"
},
{
"BriefDescription": "Header Not Sent : No TxQ Credits + No Extra Message Slotted",
"Counter": "0,1,2,3",
"EventCode": "0x53",
"EventName": "UNC_M3UPI_RxC_HDR_FLIT_NOT_SENT.NO_TXQ_NO_MSG",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Header Not Sent : No TxQ Credits + No Extra Message Slotted : header flit is ready for transmission but could not be sent : No TxQ credits available; no additional message slotted into flit",
"UMask": "0x40",
"Unit": "M3UPI"
},
{
"BriefDescription": "Header Not Sent : TSV High",
"Counter": "0,1,2,3",
"EventCode": "0x53",
"EventName": "UNC_M3UPI_RxC_HDR_FLIT_NOT_SENT.TSV_HI",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Header Not Sent : TSV High : header flit is ready for transmission but could not be sent : header flit is ready for transmission but was not sent while tsv high",
"UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "Header Not Sent : Cycle valid for Flit",
"Counter": "0,1,2,3",
"EventCode": "0x53",
"EventName": "UNC_M3UPI_RxC_HDR_FLIT_NOT_SENT.VALID_FOR_FLIT",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Header Not Sent : Cycle valid for Flit : header flit is ready for transmission but could not be sent : header flit is ready for transmission but was not sent while cycle is valid for flit transmission",
"UMask": "0x4",
"Unit": "M3UPI"
},
{
"BriefDescription": "Message Held : Can't Slot AD",
"Counter": "0,1,2",
"EventCode": "0x50",
"EventName": "UNC_M3UPI_RxC_HELD.CANT_SLOT_AD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Message Held : Can't Slot AD : some AD message could not be slotted (logical OR of all AD events under INGR_SLOT_CANT_MC_VN{0,1})",
"UMask": "0x10",
"Unit": "M3UPI"
},
{
"BriefDescription": "Message Held : Can't Slot BL",
"Counter": "0,1,2",
"EventCode": "0x50",
"EventName": "UNC_M3UPI_RxC_HELD.CANT_SLOT_BL",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Message Held : Can't Slot BL : some BL message could not be slotted (logical OR of all BL events under INGR_SLOT_CANT_MC_VN{0,1})",
"UMask": "0x20",
"Unit": "M3UPI"
},
{
"BriefDescription": "Message Held : Parallel Attempt",
"Counter": "0,1,2",
"EventCode": "0x50",
"EventName": "UNC_M3UPI_RxC_HELD.PARALLEL_ATTEMPT",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Message Held : Parallel Attempt : ad and bl messages attempted to slot into the same flit in parallel",
"UMask": "0x4",
"Unit": "M3UPI"
},
{
"BriefDescription": "Message Held : Parallel Success",
"Counter": "0,1,2",
"EventCode": "0x50",
"EventName": "UNC_M3UPI_RxC_HELD.PARALLEL_SUCCESS",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Message Held : Parallel Success : ad and bl messages were actually slotted into the same flit in parallel",
"UMask": "0x8",
"Unit": "M3UPI"
},
{
"BriefDescription": "Message Held : VN0",
"Counter": "0,1,2",
"EventCode": "0x50",
"EventName": "UNC_M3UPI_RxC_HELD.VN0",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Message Held : VN0 : vn0 message(s) that couldn't be slotted into last vn0 flit are held in slotting stage while processing vn1 flit",
"UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "Message Held : VN1",
"Counter": "0,1,2",
"EventCode": "0x50",
"EventName": "UNC_M3UPI_RxC_HELD.VN1",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Message Held : VN1 : vn1 message(s) that couldn't be slotted into last vn1 flit are held in slotting stage while processing vn0 flit",
"UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts : REQ on AD",
"Counter": "0,1,2,3",
"EventCode": "0x41",
"EventName": "UNC_M3UPI_RxC_INSERTS_VN0.AD_REQ",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN0 Ingress (from CMS) Queue - Inserts : REQ on AD : Counts the number of allocations into the UPI Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.",
"UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts : RSP on AD",
"Counter": "0,1,2,3",
"EventCode": "0x41",
"EventName": "UNC_M3UPI_RxC_INSERTS_VN0.AD_RSP",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN0 Ingress (from CMS) Queue - Inserts : RSP on AD : Counts the number of allocations into the UPI Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
"UMask": "0x4",
"Unit": "M3UPI"
},
{
"BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts : SNP on AD",
"Counter": "0,1,2,3",
"EventCode": "0x41",
"EventName": "UNC_M3UPI_RxC_INSERTS_VN0.AD_SNP",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN0 Ingress (from CMS) Queue - Inserts : SNP on AD : Counts the number of allocations into the UPI Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Snoops (SNP) messages on AD. SNP is used for outgoing snoops.",
"UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts : NCB on BL",
"Counter": "0,1,2,3",
"EventCode": "0x41",
"EventName": "UNC_M3UPI_RxC_INSERTS_VN0.BL_NCB",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN0 Ingress (from CMS) Queue - Inserts : NCB on BL : Counts the number of allocations into the UPI Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.",
"UMask": "0x20",
"Unit": "M3UPI"
},
{
"BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts : NCS on BL",
"Counter": "0,1,2,3",
"EventCode": "0x41",
"EventName": "UNC_M3UPI_RxC_INSERTS_VN0.BL_NCS",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN0 Ingress (from CMS) Queue - Inserts : NCS on BL : Counts the number of allocations into the UPI Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Non-Coherent Standard (NCS) messages on BL.",
"UMask": "0x40",
"Unit": "M3UPI"
},
{
"BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts : RSP on BL",
"Counter": "0,1,2,3",
"EventCode": "0x41",
"EventName": "UNC_M3UPI_RxC_INSERTS_VN0.BL_RSP",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN0 Ingress (from CMS) Queue - Inserts : RSP on BL : Counts the number of allocations into the UPI Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
"UMask": "0x8",
"Unit": "M3UPI"
},
{
"BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts : WB on BL",
"Counter": "0,1,2,3",
"EventCode": "0x41",
"EventName": "UNC_M3UPI_RxC_INSERTS_VN0.BL_WB",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN0 Ingress (from CMS) Queue - Inserts : WB on BL : Counts the number of allocations into the UPI Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
"UMask": "0x10",
"Unit": "M3UPI"
},
{
"BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts : REQ on AD",
"Counter": "0,1,2,3",
"EventCode": "0x42",
"EventName": "UNC_M3UPI_RxC_INSERTS_VN1.AD_REQ",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN1 Ingress (from CMS) Queue - Inserts : REQ on AD : Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.",
"UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts : RSP on AD",
"Counter": "0,1,2,3",
"EventCode": "0x42",
"EventName": "UNC_M3UPI_RxC_INSERTS_VN1.AD_RSP",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN1 Ingress (from CMS) Queue - Inserts : RSP on AD : Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
"UMask": "0x4",
"Unit": "M3UPI"
},
{
"BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts : SNP on AD",
"Counter": "0,1,2,3",
"EventCode": "0x42",
"EventName": "UNC_M3UPI_RxC_INSERTS_VN1.AD_SNP",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN1 Ingress (from CMS) Queue - Inserts : SNP on AD : Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Snoops (SNP) messages on AD. SNP is used for outgoing snoops.",
"UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts : NCB on BL",
"Counter": "0,1,2,3",
"EventCode": "0x42",
"EventName": "UNC_M3UPI_RxC_INSERTS_VN1.BL_NCB",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN1 Ingress (from CMS) Queue - Inserts : NCB on BL : Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.",
"UMask": "0x20",
"Unit": "M3UPI"
},
{
"BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts : NCS on BL",
"Counter": "0,1,2,3",
"EventCode": "0x42",
"EventName": "UNC_M3UPI_RxC_INSERTS_VN1.BL_NCS",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN1 Ingress (from CMS) Queue - Inserts : NCS on BL : Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Non-Coherent Standard (NCS) messages on BL.",
"UMask": "0x40",
"Unit": "M3UPI"
},
{
"BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts : RSP on BL",
"Counter": "0,1,2,3",
"EventCode": "0x42",
"EventName": "UNC_M3UPI_RxC_INSERTS_VN1.BL_RSP",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN1 Ingress (from CMS) Queue - Inserts : RSP on BL : Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
"UMask": "0x8",
"Unit": "M3UPI"
},
{
"BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts : WB on BL",
"Counter": "0,1,2,3",
"EventCode": "0x42",
"EventName": "UNC_M3UPI_RxC_INSERTS_VN1.BL_WB",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN1 Ingress (from CMS) Queue - Inserts : WB on BL : Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
"UMask": "0x10",
"Unit": "M3UPI"
},
{
"BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy : REQ on AD",
"Counter": "0,1,2,3",
"EventCode": "0x45",
"EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.AD_REQ",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN0 Ingress (from CMS) Queue - Occupancy : REQ on AD : Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency. : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.",
"UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy : RSP on AD",
"Counter": "0,1,2,3",
"EventCode": "0x45",
"EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.AD_RSP",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN0 Ingress (from CMS) Queue - Occupancy : RSP on AD : Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency. : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
"UMask": "0x4",
"Unit": "M3UPI"
},
{
"BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy : SNP on AD",
"Counter": "0,1,2,3",
"EventCode": "0x45",
"EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.AD_SNP",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN0 Ingress (from CMS) Queue - Occupancy : SNP on AD : Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency. : Snoops (SNP) messages on AD. SNP is used for outgoing snoops.",
"UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy : NCB on BL",
"Counter": "0,1,2,3",
"EventCode": "0x45",
"EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.BL_NCB",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN0 Ingress (from CMS) Queue - Occupancy : NCB on BL : Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency. : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.",
"UMask": "0x20",
"Unit": "M3UPI"
},
{
"BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy : NCS on BL",
"Counter": "0,1,2,3",
"EventCode": "0x45",
"EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.BL_NCS",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN0 Ingress (from CMS) Queue - Occupancy : NCS on BL : Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency. : Non-Coherent Standard (NCS) messages on BL.",
"UMask": "0x40",
"Unit": "M3UPI"
},
{
"BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy : RSP on BL",
"Counter": "0,1,2,3",
"EventCode": "0x45",
"EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.BL_RSP",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN0 Ingress (from CMS) Queue - Occupancy : RSP on BL : Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency. : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
"UMask": "0x8",
"Unit": "M3UPI"
},
{
"BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy : WB on BL",
"Counter": "0,1,2,3",
"EventCode": "0x45",
"EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.BL_WB",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN0 Ingress (from CMS) Queue - Occupancy : WB on BL : Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency. : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
"UMask": "0x10",
"Unit": "M3UPI"
},
{
"BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy : REQ on AD",
"Counter": "0,1,2,3",
"EventCode": "0x46",
"EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.AD_REQ",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN1 Ingress (from CMS) Queue - Occupancy : REQ on AD : Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency. : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.",
"UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy : RSP on AD",
"Counter": "0,1,2,3",
"EventCode": "0x46",
"EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.AD_RSP",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN1 Ingress (from CMS) Queue - Occupancy : RSP on AD : Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency. : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
"UMask": "0x4",
"Unit": "M3UPI"
},
{
"BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy : SNP on AD",
"Counter": "0,1,2,3",
"EventCode": "0x46",
"EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.AD_SNP",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN1 Ingress (from CMS) Queue - Occupancy : SNP on AD : Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency. : Snoops (SNP) messages on AD. SNP is used for outgoing snoops.",
"UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy : NCB on BL",
"Counter": "0,1,2,3",
"EventCode": "0x46",
"EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.BL_NCB",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN1 Ingress (from CMS) Queue - Occupancy : NCB on BL : Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency. : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.",
"UMask": "0x20",
"Unit": "M3UPI"
},
{
"BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy : NCS on BL",
"Counter": "0,1,2,3",
"EventCode": "0x46",
"EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.BL_NCS",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN1 Ingress (from CMS) Queue - Occupancy : NCS on BL : Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency. : Non-Coherent Standard (NCS) messages on BL.",
"UMask": "0x40",
"Unit": "M3UPI"
},
{
"BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy : RSP on BL",
"Counter": "0,1,2,3",
"EventCode": "0x46",
"EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.BL_RSP",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN1 Ingress (from CMS) Queue - Occupancy : RSP on BL : Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency. : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
"UMask": "0x8",
"Unit": "M3UPI"
},
{
"BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy : WB on BL",
"Counter": "0,1,2,3",
"EventCode": "0x46",
"EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.BL_WB",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN1 Ingress (from CMS) Queue - Occupancy : WB on BL : Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency. : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
"UMask": "0x10",
"Unit": "M3UPI"
},
{
"BriefDescription": "VN0 message can't slot into flit : REQ on AD",
"Counter": "0,1,2",
"EventCode": "0x4E",
"EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.AD_REQ",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN0 message can't slot into flit : REQ on AD : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.",
"UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "VN0 message can't slot into flit : RSP on AD",
"Counter": "0,1,2",
"EventCode": "0x4E",
"EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.AD_RSP",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN0 message can't slot into flit : RSP on AD : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
"UMask": "0x4",
"Unit": "M3UPI"
},
{
"BriefDescription": "VN0 message can't slot into flit : SNP on AD",
"Counter": "0,1,2",
"EventCode": "0x4E",
"EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.AD_SNP",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN0 message can't slot into flit : SNP on AD : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Snoops (SNP) messages on AD. SNP is used for outgoing snoops.",
"UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "VN0 message can't slot into flit : NCB on BL",
"Counter": "0,1,2",
"EventCode": "0x4E",
"EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.BL_NCB",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN0 message can't slot into flit : NCB on BL : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.",
"UMask": "0x20",
"Unit": "M3UPI"
},
{
"BriefDescription": "VN0 message can't slot into flit : NCS on BL",
"Counter": "0,1,2",
"EventCode": "0x4E",
"EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.BL_NCS",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN0 message can't slot into flit : NCS on BL : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Non-Coherent Standard (NCS) messages on BL.",
"UMask": "0x40",
"Unit": "M3UPI"
},
{
"BriefDescription": "VN0 message can't slot into flit : RSP on BL",
"Counter": "0,1,2",
"EventCode": "0x4E",
"EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.BL_RSP",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN0 message can't slot into flit : RSP on BL : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
"UMask": "0x8",
"Unit": "M3UPI"
},
{
"BriefDescription": "VN0 message can't slot into flit : WB on BL",
"Counter": "0,1,2",
"EventCode": "0x4E",
"EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.BL_WB",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN0 message can't slot into flit : WB on BL : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
"UMask": "0x10",
"Unit": "M3UPI"
},
{
"BriefDescription": "VN1 message can't slot into flit : REQ on AD",
"Counter": "0,1,2",
"EventCode": "0x4F",
"EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.AD_REQ",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN1 message can't slot into flit : REQ on AD : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.",
"UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "VN1 message can't slot into flit : RSP on AD",
"Counter": "0,1,2",
"EventCode": "0x4F",
"EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.AD_RSP",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN1 message can't slot into flit : RSP on AD : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
"UMask": "0x4",
"Unit": "M3UPI"
},
{
"BriefDescription": "VN1 message can't slot into flit : SNP on AD",
"Counter": "0,1,2",
"EventCode": "0x4F",
"EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.AD_SNP",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN1 message can't slot into flit : SNP on AD : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Snoops (SNP) messages on AD. SNP is used for outgoing snoops.",
"UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "VN1 message can't slot into flit : NCB on BL",
"Counter": "0,1,2",
"EventCode": "0x4F",
"EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.BL_NCB",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN1 message can't slot into flit : NCB on BL : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.",
"UMask": "0x20",
"Unit": "M3UPI"
},
{
"BriefDescription": "VN1 message can't slot into flit : NCS on BL",
"Counter": "0,1,2",
"EventCode": "0x4F",
"EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.BL_NCS",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN1 message can't slot into flit : NCS on BL : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Non-Coherent Standard (NCS) messages on BL.",
"UMask": "0x40",
"Unit": "M3UPI"
},
{
"BriefDescription": "VN1 message can't slot into flit : RSP on BL",
"Counter": "0,1,2",
"EventCode": "0x4F",
"EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.BL_RSP",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN1 message can't slot into flit : RSP on BL : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
"UMask": "0x8",
"Unit": "M3UPI"
},
{
"BriefDescription": "VN1 message can't slot into flit : WB on BL",
"Counter": "0,1,2",
"EventCode": "0x4F",
"EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.BL_WB",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN1 message can't slot into flit : WB on BL : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
"UMask": "0x10",
"Unit": "M3UPI"
},
{
"BriefDescription": "Remote VNA Credits : Any In Use",
"Counter": "0,1,2,3",
"EventCode": "0x5A",
"EventName": "UNC_M3UPI_RxC_VNA_CRD.ANY_IN_USE",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Remote VNA Credits : Any In Use : At least one remote vna credit is in use",
"UMask": "0x20",
"Unit": "M3UPI"
},
{
"BriefDescription": "Remote VNA Credits : Corrected",
"Counter": "0,1,2,3",
"EventCode": "0x5A",
"EventName": "UNC_M3UPI_RxC_VNA_CRD.CORRECTED",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Remote VNA Credits : Corrected : Number of remote vna credits corrected (local return) per cycle",
"UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "Remote VNA Credits : Level < 1",
"Counter": "0,1,2,3",
"EventCode": "0x5A",
"EventName": "UNC_M3UPI_RxC_VNA_CRD.LT1",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Remote VNA Credits : Level < 1 : Remote vna credit level is less than 1 (i.e. no vna credits available)",
"UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "Remote VNA Credits : Level < 10",
"Counter": "0,1,2,3",
"EventCode": "0x5A",
"EventName": "UNC_M3UPI_RxC_VNA_CRD.LT10",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Remote VNA Credits : Level < 10 : remote vna credit level is less than 10; parallel vn0/vn1 arb not possible",
"UMask": "0x10",
"Unit": "M3UPI"
},
{
"BriefDescription": "Remote VNA Credits : Level < 4",
"Counter": "0,1,2,3",
"EventCode": "0x5A",
"EventName": "UNC_M3UPI_RxC_VNA_CRD.LT4",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Remote VNA Credits : Level < 4 : Remote vna credit level is less than 4; bl (or ad requiring 4 vna) cannot arb on vna",
"UMask": "0x4",
"Unit": "M3UPI"
},
{
"BriefDescription": "Remote VNA Credits : Level < 5",
"Counter": "0,1,2,3",
"EventCode": "0x5A",
"EventName": "UNC_M3UPI_RxC_VNA_CRD.LT5",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Remote VNA Credits : Level < 5 : Remote vna credit level is less than 5; parallel ad/bl arb on vna not possible",
"UMask": "0x8",
"Unit": "M3UPI"
},
{
"BriefDescription": "UNC_M3UPI_RxC_VNA_CRD_MISC.REQ_ADBL_ALLOC_L5",
"Counter": "0,1,2,3",
"EventCode": "0x59",
"EventName": "UNC_M3UPI_RxC_VNA_CRD_MISC.REQ_ADBL_ALLOC_L5",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": ": remote vna credit count was less than 5 and allocation to ad or bl messages was required",
"UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "UNC_M3UPI_RxC_VNA_CRD_MISC.REQ_VN01_ALLOC_LT10",
"Counter": "0,1,2,3",
"EventCode": "0x59",
"EventName": "UNC_M3UPI_RxC_VNA_CRD_MISC.REQ_VN01_ALLOC_LT10",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": ": remote vna credit count was less than 10 and allocation to vn0 or vn1 was required",
"UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN0_JUST_AD",
"Counter": "0,1,2,3",
"EventCode": "0x59",
"EventName": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN0_JUST_AD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": ": on vn0, remote vna credits were allocated only to ad messages, not to bl",
"UMask": "0x10",
"Unit": "M3UPI"
},
{
"BriefDescription": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN0_JUST_BL",
"Counter": "0,1,2,3",
"EventCode": "0x59",
"EventName": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN0_JUST_BL",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": ": on vn0, remote vna credits were allocated only to bl messages, not to ad",
"UMask": "0x20",
"Unit": "M3UPI"
},
{
"BriefDescription": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN0_ONLY",
"Counter": "0,1,2,3",
"EventCode": "0x59",
"EventName": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN0_ONLY",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": ": remote vna credits were allocated only to vn0, not to vn1",
"UMask": "0x4",
"Unit": "M3UPI"
},
{
"BriefDescription": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN1_JUST_AD",
"Counter": "0,1,2,3",
"EventCode": "0x59",
"EventName": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN1_JUST_AD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": ": on vn1, remote vna credits were allocated only to ad messages, not to bl",
"UMask": "0x40",
"Unit": "M3UPI"
},
{
"BriefDescription": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN1_JUST_BL",
"Counter": "0,1,2,3",
"EventCode": "0x59",
"EventName": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN1_JUST_BL",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": ": on vn1, remote vna credits were allocated only to bl messages, not to ad",
"UMask": "0x80",
"Unit": "M3UPI"
},
{
"BriefDescription": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN1_ONLY",
"Counter": "0,1,2,3",
"EventCode": "0x59",
"EventName": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN1_ONLY",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": ": remote vna credits were allocated only to vn1, not to vn0",
"UMask": "0x8",
"Unit": "M3UPI"
},
{
"BriefDescription": "Transgress Injection Starvation : AD - All",
"Counter": "0,1,2,3",
"EventCode": "0xE5",
"EventName": "UNC_M3UPI_RxR_BUSY_STARVED.AD_ALL",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Injection Starvation : AD - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority : All == Credited + Uncredited",
"UMask": "0x11",
"Unit": "M3UPI"
},
{
"BriefDescription": "Transgress Injection Starvation : AD - Credited",
"Counter": "0,1,2,3",
"EventCode": "0xE5",
"EventName": "UNC_M3UPI_RxR_BUSY_STARVED.AD_CRD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Injection Starvation : AD - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority",
"UMask": "0x10",
"Unit": "M3UPI"
},
{
"BriefDescription": "Transgress Injection Starvation : AD - Uncredited",
"Counter": "0,1,2,3",
"EventCode": "0xE5",
"EventName": "UNC_M3UPI_RxR_BUSY_STARVED.AD_UNCRD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Injection Starvation : AD - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority",
"UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "Transgress Injection Starvation : BL - All",
"Counter": "0,1,2,3",
"EventCode": "0xE5",
"EventName": "UNC_M3UPI_RxR_BUSY_STARVED.BL_ALL",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Injection Starvation : BL - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority : All == Credited + Uncredited",
"UMask": "0x44",
"Unit": "M3UPI"
},
{
"BriefDescription": "Transgress Injection Starvation : BL - Credited",
"Counter": "0,1,2,3",
"EventCode": "0xE5",
"EventName": "UNC_M3UPI_RxR_BUSY_STARVED.BL_CRD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Injection Starvation : BL - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority",
"UMask": "0x40",
"Unit": "M3UPI"
},
{
"BriefDescription": "Transgress Injection Starvation : BL - Uncredited",
"Counter": "0,1,2,3",
"EventCode": "0xE5",
"EventName": "UNC_M3UPI_RxR_BUSY_STARVED.BL_UNCRD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Injection Starvation : BL - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority",
"UMask": "0x4",
"Unit": "M3UPI"
},
{
"BriefDescription": "Transgress Ingress Bypass : AD - All",
"Counter": "0,1,2,3",
"EventCode": "0xE2",
"EventName": "UNC_M3UPI_RxR_BYPASS.AD_ALL",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Ingress Bypass : AD - All : Number of packets bypassing the CMS Ingress : All == Credited + Uncredited",
"UMask": "0x11",
"Unit": "M3UPI"
},
{
"BriefDescription": "Transgress Ingress Bypass : AD - Credited",
"Counter": "0,1,2,3",
"EventCode": "0xE2",
"EventName": "UNC_M3UPI_RxR_BYPASS.AD_CRD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Ingress Bypass : AD - Credited : Number of packets bypassing the CMS Ingress",
"UMask": "0x10",
"Unit": "M3UPI"
},
{
"BriefDescription": "Transgress Ingress Bypass : AD - Uncredited",
"Counter": "0,1,2,3",
"EventCode": "0xE2",
"EventName": "UNC_M3UPI_RxR_BYPASS.AD_UNCRD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Ingress Bypass : AD - Uncredited : Number of packets bypassing the CMS Ingress",
"UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "Transgress Ingress Bypass : AK",
"Counter": "0,1,2,3",
"EventCode": "0xE2",
"EventName": "UNC_M3UPI_RxR_BYPASS.AK",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Ingress Bypass : AK : Number of packets bypassing the CMS Ingress",
"UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "Transgress Ingress Bypass : AKC - Uncredited",
"Counter": "0,1,2,3",
"EventCode": "0xE2",
"EventName": "UNC_M3UPI_RxR_BYPASS.AKC_UNCRD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Ingress Bypass : AKC - Uncredited : Number of packets bypassing the CMS Ingress",
"UMask": "0x80",
"Unit": "M3UPI"
},
{
"BriefDescription": "Transgress Ingress Bypass : BL - All",
"Counter": "0,1,2,3",
"EventCode": "0xE2",
"EventName": "UNC_M3UPI_RxR_BYPASS.BL_ALL",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Ingress Bypass : BL - All : Number of packets bypassing the CMS Ingress : All == Credited + Uncredited",
"UMask": "0x44",
"Unit": "M3UPI"
},
{
"BriefDescription": "Transgress Ingress Bypass : BL - Credited",
"Counter": "0,1,2,3",
"EventCode": "0xE2",
"EventName": "UNC_M3UPI_RxR_BYPASS.BL_CRD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Ingress Bypass : BL - Credited : Number of packets bypassing the CMS Ingress",
"UMask": "0x40",
"Unit": "M3UPI"
},
{
"BriefDescription": "Transgress Ingress Bypass : BL - Uncredited",
"Counter": "0,1,2,3",
"EventCode": "0xE2",
"EventName": "UNC_M3UPI_RxR_BYPASS.BL_UNCRD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Ingress Bypass : BL - Uncredited : Number of packets bypassing the CMS Ingress",
"UMask": "0x4",
"Unit": "M3UPI"
},
{
"BriefDescription": "Transgress Ingress Bypass : IV",
"Counter": "0,1,2,3",
"EventCode": "0xE2",
"EventName": "UNC_M3UPI_RxR_BYPASS.IV",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Ingress Bypass : IV : Number of packets bypassing the CMS Ingress",
"UMask": "0x8",
"Unit": "M3UPI"
},
{
"BriefDescription": "Transgress Injection Starvation : AD - All",
"Counter": "0,1,2,3",
"EventCode": "0xE3",
"EventName": "UNC_M3UPI_RxR_CRD_STARVED.AD_ALL",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Injection Starvation : AD - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit. : All == Credited + Uncredited",
"UMask": "0x11",
"Unit": "M3UPI"
},
{
"BriefDescription": "Transgress Injection Starvation : AD - Credited",
"Counter": "0,1,2,3",
"EventCode": "0xE3",
"EventName": "UNC_M3UPI_RxR_CRD_STARVED.AD_CRD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Injection Starvation : AD - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
"UMask": "0x10",
"Unit": "M3UPI"
},
{
"BriefDescription": "Transgress Injection Starvation : AD - Uncredited",
"Counter": "0,1,2,3",
"EventCode": "0xE3",
"EventName": "UNC_M3UPI_RxR_CRD_STARVED.AD_UNCRD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Injection Starvation : AD - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
"UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "Transgress Injection Starvation : AK",
"Counter": "0,1,2,3",
"EventCode": "0xE3",
"EventName": "UNC_M3UPI_RxR_CRD_STARVED.AK",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Injection Starvation : AK : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
"UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "Transgress Injection Starvation : BL - All",
"Counter": "0,1,2,3",
"EventCode": "0xE3",
"EventName": "UNC_M3UPI_RxR_CRD_STARVED.BL_ALL",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Injection Starvation : BL - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit. : All == Credited + Uncredited",
"UMask": "0x44",
"Unit": "M3UPI"
},
{
"BriefDescription": "Transgress Injection Starvation : BL - Credited",
"Counter": "0,1,2,3",
"EventCode": "0xE3",
"EventName": "UNC_M3UPI_RxR_CRD_STARVED.BL_CRD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Injection Starvation : BL - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
"UMask": "0x40",
"Unit": "M3UPI"
},
{
"BriefDescription": "Transgress Injection Starvation : BL - Uncredited",
"Counter": "0,1,2,3",
"EventCode": "0xE3",
"EventName": "UNC_M3UPI_RxR_CRD_STARVED.BL_UNCRD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Injection Starvation : BL - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
"UMask": "0x4",
"Unit": "M3UPI"
},
{
"BriefDescription": "Transgress Injection Starvation : IFV - Credited",
"Counter": "0,1,2,3",
"EventCode": "0xE3",
"EventName": "UNC_M3UPI_RxR_CRD_STARVED.IFV",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Injection Starvation : IFV - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
"UMask": "0x80",
"Unit": "M3UPI"
},
{
"BriefDescription": "Transgress Injection Starvation : IV",
"Counter": "0,1,2,3",
"EventCode": "0xE3",
"EventName": "UNC_M3UPI_RxR_CRD_STARVED.IV",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Injection Starvation : IV : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
"UMask": "0x8",
"Unit": "M3UPI"
},
{
"BriefDescription": "Transgress Injection Starvation",
"Counter": "0,1,2,3",
"EventCode": "0xe4",
"EventName": "UNC_M3UPI_RxR_CRD_STARVED_1",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Injection Starvation : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
"Unit": "M3UPI"
},
{
"BriefDescription": "Transgress Ingress Allocations : AD - All",
"Counter": "0,1,2,3",
"EventCode": "0xE1",
"EventName": "UNC_M3UPI_RxR_INSERTS.AD_ALL",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Ingress Allocations : AD - All : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited",
"UMask": "0x11",
"Unit": "M3UPI"
},
{
"BriefDescription": "Transgress Ingress Allocations : AD - Credited",
"Counter": "0,1,2,3",
"EventCode": "0xE1",
"EventName": "UNC_M3UPI_RxR_INSERTS.AD_CRD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Ingress Allocations : AD - Credited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
"UMask": "0x10",
"Unit": "M3UPI"
},
{
"BriefDescription": "Transgress Ingress Allocations : AD - Uncredited",
"Counter": "0,1,2,3",
"EventCode": "0xE1",
"EventName": "UNC_M3UPI_RxR_INSERTS.AD_UNCRD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Ingress Allocations : AD - Uncredited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
"UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "Transgress Ingress Allocations : AK",
"Counter": "0,1,2,3",
"EventCode": "0xE1",
"EventName": "UNC_M3UPI_RxR_INSERTS.AK",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Ingress Allocations : AK : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
"UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "Transgress Ingress Allocations : AKC - Uncredited",
"Counter": "0,1,2,3",
"EventCode": "0xE1",
"EventName": "UNC_M3UPI_RxR_INSERTS.AKC_UNCRD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Ingress Allocations : AKC - Uncredited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
"UMask": "0x80",
"Unit": "M3UPI"
},
{
"BriefDescription": "Transgress Ingress Allocations : BL - All",
"Counter": "0,1,2,3",
"EventCode": "0xE1",
"EventName": "UNC_M3UPI_RxR_INSERTS.BL_ALL",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Ingress Allocations : BL - All : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited",
"UMask": "0x44",
"Unit": "M3UPI"
},
{
"BriefDescription": "Transgress Ingress Allocations : BL - Credited",
"Counter": "0,1,2,3",
"EventCode": "0xE1",
"EventName": "UNC_M3UPI_RxR_INSERTS.BL_CRD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Ingress Allocations : BL - Credited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
"UMask": "0x40",
"Unit": "M3UPI"
},
{
"BriefDescription": "Transgress Ingress Allocations : BL - Uncredited",
"Counter": "0,1,2,3",
"EventCode": "0xE1",
"EventName": "UNC_M3UPI_RxR_INSERTS.BL_UNCRD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Ingress Allocations : BL - Uncredited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
"UMask": "0x4",
"Unit": "M3UPI"
},
{
"BriefDescription": "Transgress Ingress Allocations : IV",
"Counter": "0,1,2,3",
"EventCode": "0xE1",
"EventName": "UNC_M3UPI_RxR_INSERTS.IV",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Ingress Allocations : IV : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
"UMask": "0x8",
"Unit": "M3UPI"
},
{
"BriefDescription": "Transgress Ingress Occupancy : AD - All",
"Counter": "0,1,2,3",
"EventCode": "0xE0",
"EventName": "UNC_M3UPI_RxR_OCCUPANCY.AD_ALL",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Ingress Occupancy : AD - All : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited",
"UMask": "0x11",
"Unit": "M3UPI"
},
{
"BriefDescription": "Transgress Ingress Occupancy : AD - Credited",
"Counter": "0,1,2,3",
"EventCode": "0xE0",
"EventName": "UNC_M3UPI_RxR_OCCUPANCY.AD_CRD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Ingress Occupancy : AD - Credited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
"UMask": "0x10",
"Unit": "M3UPI"
},
{
"BriefDescription": "Transgress Ingress Occupancy : AD - Uncredited",
"Counter": "0,1,2,3",
"EventCode": "0xE0",
"EventName": "UNC_M3UPI_RxR_OCCUPANCY.AD_UNCRD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Ingress Occupancy : AD - Uncredited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
"UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "Transgress Ingress Occupancy : AK",
"Counter": "0,1,2,3",
"EventCode": "0xE0",
"EventName": "UNC_M3UPI_RxR_OCCUPANCY.AK",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Ingress Occupancy : AK : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
"UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "Transgress Ingress Occupancy : AKC - Uncredited",
"Counter": "0,1,2,3",
"EventCode": "0xE0",
"EventName": "UNC_M3UPI_RxR_OCCUPANCY.AKC_UNCRD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Ingress Occupancy : AKC - Uncredited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
"UMask": "0x80",
"Unit": "M3UPI"
},
{
"BriefDescription": "Transgress Ingress Occupancy : BL - All",
"Counter": "0,1,2,3",
"EventCode": "0xE0",
"EventName": "UNC_M3UPI_RxR_OCCUPANCY.BL_ALL",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Ingress Occupancy : BL - All : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited",
"UMask": "0x44",
"Unit": "M3UPI"
},
{
"BriefDescription": "Transgress Ingress Occupancy : BL - Credited",
"Counter": "0,1,2,3",
"EventCode": "0xE0",
"EventName": "UNC_M3UPI_RxR_OCCUPANCY.BL_CRD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Ingress Occupancy : BL - Credited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
"UMask": "0x20",
"Unit": "M3UPI"
},
{
"BriefDescription": "Transgress Ingress Occupancy : BL - Uncredited",
"Counter": "0,1,2,3",
"EventCode": "0xE0",
"EventName": "UNC_M3UPI_RxR_OCCUPANCY.BL_UNCRD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Ingress Occupancy : BL - Uncredited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
"UMask": "0x4",
"Unit": "M3UPI"
},
{
"BriefDescription": "Transgress Ingress Occupancy : IV",
"Counter": "0,1,2,3",
"EventCode": "0xE0",
"EventName": "UNC_M3UPI_RxR_OCCUPANCY.IV",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Transgress Ingress Occupancy : IV : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
"UMask": "0x8",
"Unit": "M3UPI"
},
{
"BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 0",
"Counter": "0,1,2,3",
"EventCode": "0xD0",
"EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR0",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 0 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 1",
"Counter": "0,1,2,3",
"EventCode": "0xD0",
"EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR1",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 1 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 2",
"Counter": "0,1,2,3",
"EventCode": "0xD0",
"EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR2",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 2 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x4",
"Unit": "M3UPI"
},
{
"BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 3",
"Counter": "0,1,2,3",
"EventCode": "0xD0",
"EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR3",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 3 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x8",
"Unit": "M3UPI"
},
{
"BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 4",
"Counter": "0,1,2,3",
"EventCode": "0xD0",
"EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR4",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 4 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x10",
"Unit": "M3UPI"
},
{
"BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 5",
"Counter": "0,1,2,3",
"EventCode": "0xD0",
"EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR5",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 5 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x20",
"Unit": "M3UPI"
},
{
"BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 6",
"Counter": "0,1,2,3",
"EventCode": "0xD0",
"EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR6",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 6 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x40",
"Unit": "M3UPI"
},
{
"BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 7",
"Counter": "0,1,2,3",
"EventCode": "0xD0",
"EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR7",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 7 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x80",
"Unit": "M3UPI"
},
{
"BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 0",
"Counter": "0,1,2,3",
"EventCode": "0xD2",
"EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR0",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 0 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 1",
"Counter": "0,1,2,3",
"EventCode": "0xD2",
"EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR1",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 1 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 2",
"Counter": "0,1,2,3",
"EventCode": "0xD2",
"EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR2",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 2 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x4",
"Unit": "M3UPI"
},
{
"BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 3",
"Counter": "0,1,2,3",
"EventCode": "0xD2",
"EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR3",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 3 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x8",
"Unit": "M3UPI"
},
{
"BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 4",
"Counter": "0,1,2,3",
"EventCode": "0xD2",
"EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR4",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 4 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x10",
"Unit": "M3UPI"
},
{
"BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 5",
"Counter": "0,1,2,3",
"EventCode": "0xD2",
"EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR5",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 5 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x20",
"Unit": "M3UPI"
},
{
"BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 6",
"Counter": "0,1,2,3",
"EventCode": "0xD2",
"EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR6",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 6 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x40",
"Unit": "M3UPI"
},
{
"BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 7",
"Counter": "0,1,2,3",
"EventCode": "0xD2",
"EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR7",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 7 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x80",
"Unit": "M3UPI"
},
{
"BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 0",
"Counter": "0,1,2,3",
"EventCode": "0xD4",
"EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR0",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 0 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 1",
"Counter": "0,1,2,3",
"EventCode": "0xD4",
"EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR1",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 1 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 2",
"Counter": "0,1,2,3",
"EventCode": "0xD4",
"EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR2",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 2 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x4",
"Unit": "M3UPI"
},
{
"BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 3",
"Counter": "0,1,2,3",
"EventCode": "0xD4",
"EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR3",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 3 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x8",
"Unit": "M3UPI"
},
{
"BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 4",
"Counter": "0,1,2,3",
"EventCode": "0xD4",
"EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR4",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 4 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x10",
"Unit": "M3UPI"
},
{
"BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 5",
"Counter": "0,1,2,3",
"EventCode": "0xD4",
"EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR5",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 5 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x20",
"Unit": "M3UPI"
},
{
"BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 6",
"Counter": "0,1,2,3",
"EventCode": "0xD4",
"EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR6",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 6 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x40",
"Unit": "M3UPI"
},
{
"BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 7",
"Counter": "0,1,2,3",
"EventCode": "0xD4",
"EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR7",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 7 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x80",
"Unit": "M3UPI"
},
{
"BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 0",
"Counter": "0,1,2,3",
"EventCode": "0xD6",
"EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR0",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 0 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 1",
"Counter": "0,1,2,3",
"EventCode": "0xD6",
"EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR1",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 1 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 2",
"Counter": "0,1,2,3",
"EventCode": "0xD6",
"EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR2",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 2 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x4",
"Unit": "M3UPI"
},
{
"BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 3",
"Counter": "0,1,2,3",
"EventCode": "0xD6",
"EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR3",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 3 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x8",
"Unit": "M3UPI"
},
{
"BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 4",
"Counter": "0,1,2,3",
"EventCode": "0xD6",
"EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR4",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 4 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x10",
"Unit": "M3UPI"
},
{
"BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 5",
"Counter": "0,1,2,3",
"EventCode": "0xD6",
"EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR5",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 5 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x20",
"Unit": "M3UPI"
},
{
"BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 6",
"Counter": "0,1,2,3",
"EventCode": "0xD6",
"EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR6",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 6 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x40",
"Unit": "M3UPI"
},
{
"BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 7",
"Counter": "0,1,2,3",
"EventCode": "0xD6",
"EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR7",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 7 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x80",
"Unit": "M3UPI"
},
{
"BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 10",
"Counter": "0,1,2,3",
"EventCode": "0xD1",
"EventName": "UNC_M3UPI_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR10",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 10 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x4",
"Unit": "M3UPI"
},
{
"BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 8",
"Counter": "0,1,2,3",
"EventCode": "0xD1",
"EventName": "UNC_M3UPI_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR8",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 8 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 9",
"Counter": "0,1,2,3",
"EventCode": "0xD1",
"EventName": "UNC_M3UPI_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR9",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 9 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 10",
"Counter": "0,1,2,3",
"EventCode": "0xD3",
"EventName": "UNC_M3UPI_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR10",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 10 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x4",
"Unit": "M3UPI"
},
{
"BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 8",
"Counter": "0,1,2,3",
"EventCode": "0xD3",
"EventName": "UNC_M3UPI_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR8",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 8 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 9",
"Counter": "0,1,2,3",
"EventCode": "0xD3",
"EventName": "UNC_M3UPI_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR9",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 9 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 10",
"Counter": "0,1,2,3",
"EventCode": "0xD5",
"EventName": "UNC_M3UPI_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR10",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 10 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x4",
"Unit": "M3UPI"
},
{
"BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 8",
"Counter": "0,1,2,3",
"EventCode": "0xD5",
"EventName": "UNC_M3UPI_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR8",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 8 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 9",
"Counter": "0,1,2,3",
"EventCode": "0xD5",
"EventName": "UNC_M3UPI_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR9",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 9 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 10",
"Counter": "0,1,2,3",
"EventCode": "0xD7",
"EventName": "UNC_M3UPI_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR10",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 10 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x4",
"Unit": "M3UPI"
},
{
"BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 8",
"Counter": "0,1,2,3",
"EventCode": "0xD7",
"EventName": "UNC_M3UPI_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR8",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 8 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 9",
"Counter": "0,1,2,3",
"EventCode": "0xD7",
"EventName": "UNC_M3UPI_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR9",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 9 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "Failed ARB for AD : VN0 REQ Messages",
"Counter": "0,1,2,3",
"EventCode": "0x30",
"EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN0_REQ",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Failed ARB for AD : VN0 REQ Messages : AD arb but no win; arb request asserted but not won",
"UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "Failed ARB for AD : VN0 RSP Messages",
"Counter": "0,1,2,3",
"EventCode": "0x30",
"EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN0_RSP",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Failed ARB for AD : VN0 RSP Messages : AD arb but no win; arb request asserted but not won",
"UMask": "0x4",
"Unit": "M3UPI"
},
{
"BriefDescription": "Failed ARB for AD : VN0 SNP Messages",
"Counter": "0,1,2,3",
"EventCode": "0x30",
"EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN0_SNP",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Failed ARB for AD : VN0 SNP Messages : AD arb but no win; arb request asserted but not won",
"UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "Failed ARB for AD : VN0 WB Messages",
"Counter": "0,1,2,3",
"EventCode": "0x30",
"EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN0_WB",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Failed ARB for AD : VN0 WB Messages : AD arb but no win; arb request asserted but not won",
"UMask": "0x8",
"Unit": "M3UPI"
},
{
"BriefDescription": "Failed ARB for AD : VN1 REQ Messages",
"Counter": "0,1,2,3",
"EventCode": "0x30",
"EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN1_REQ",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Failed ARB for AD : VN1 REQ Messages : AD arb but no win; arb request asserted but not won",
"UMask": "0x10",
"Unit": "M3UPI"
},
{
"BriefDescription": "Failed ARB for AD : VN1 RSP Messages",
"Counter": "0,1,2,3",
"EventCode": "0x30",
"EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN1_RSP",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Failed ARB for AD : VN1 RSP Messages : AD arb but no win; arb request asserted but not won",
"UMask": "0x40",
"Unit": "M3UPI"
},
{
"BriefDescription": "Failed ARB for AD : VN1 SNP Messages",
"Counter": "0,1,2,3",
"EventCode": "0x30",
"EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN1_SNP",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Failed ARB for AD : VN1 SNP Messages : AD arb but no win; arb request asserted but not won",
"UMask": "0x20",
"Unit": "M3UPI"
},
{
"BriefDescription": "Failed ARB for AD : VN1 WB Messages",
"Counter": "0,1,2,3",
"EventCode": "0x30",
"EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN1_WB",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Failed ARB for AD : VN1 WB Messages : AD arb but no win; arb request asserted but not won",
"UMask": "0x80",
"Unit": "M3UPI"
},
{
"BriefDescription": "AD FlowQ Bypass",
"Counter": "0,1,2,3",
"EventCode": "0x2C",
"EventName": "UNC_M3UPI_TxC_AD_FLQ_BYPASS.AD_SLOT0",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "AD FlowQ Bypass : Counts cases when the AD flowQ is bypassed (S0, S1 and S2 indicate which slot was bypassed with S0 having the highest priority and S2 the least)",
"UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "AD FlowQ Bypass",
"Counter": "0,1,2,3",
"EventCode": "0x2C",
"EventName": "UNC_M3UPI_TxC_AD_FLQ_BYPASS.AD_SLOT1",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "AD FlowQ Bypass : Counts cases when the AD flowQ is bypassed (S0, S1 and S2 indicate which slot was bypassed with S0 having the highest priority and S2 the least)",
"UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "AD FlowQ Bypass",
"Counter": "0,1,2,3",
"EventCode": "0x2C",
"EventName": "UNC_M3UPI_TxC_AD_FLQ_BYPASS.AD_SLOT2",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "AD FlowQ Bypass : Counts cases when the AD flowQ is bypassed (S0, S1 and S2 indicate which slot was bypassed with S0 having the highest priority and S2 the least)",
"UMask": "0x4",
"Unit": "M3UPI"
},
{
"BriefDescription": "AD FlowQ Bypass",
"Counter": "0,1,2,3",
"EventCode": "0x2C",
"EventName": "UNC_M3UPI_TxC_AD_FLQ_BYPASS.BL_EARLY_RSP",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "AD FlowQ Bypass : Counts cases when the AD flowQ is bypassed (S0, S1 and S2 indicate which slot was bypassed with S0 having the highest priority and S2 the least)",
"UMask": "0x8",
"Unit": "M3UPI"
},
{
"BriefDescription": "AD Flow Q Not Empty : VN0 REQ Messages",
"Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN0_REQ",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "AD Flow Q Not Empty : VN0 REQ Messages : Number of cycles the AD Egress queue is Not Empty",
"UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "AD Flow Q Not Empty : VN0 RSP Messages",
"Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN0_RSP",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "AD Flow Q Not Empty : VN0 RSP Messages : Number of cycles the AD Egress queue is Not Empty",
"UMask": "0x4",
"Unit": "M3UPI"
},
{
"BriefDescription": "AD Flow Q Not Empty : VN0 SNP Messages",
"Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN0_SNP",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "AD Flow Q Not Empty : VN0 SNP Messages : Number of cycles the AD Egress queue is Not Empty",
"UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "AD Flow Q Not Empty : VN0 WB Messages",
"Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN0_WB",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "AD Flow Q Not Empty : VN0 WB Messages : Number of cycles the AD Egress queue is Not Empty",
"UMask": "0x8",
"Unit": "M3UPI"
},
{
"BriefDescription": "AD Flow Q Not Empty : VN1 REQ Messages",
"Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN1_REQ",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "AD Flow Q Not Empty : VN1 REQ Messages : Number of cycles the AD Egress queue is Not Empty",
"UMask": "0x10",
"Unit": "M3UPI"
},
{
"BriefDescription": "AD Flow Q Not Empty : VN1 RSP Messages",
"Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN1_RSP",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "AD Flow Q Not Empty : VN1 RSP Messages : Number of cycles the AD Egress queue is Not Empty",
"UMask": "0x40",
"Unit": "M3UPI"
},
{
"BriefDescription": "AD Flow Q Not Empty : VN1 SNP Messages",
"Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN1_SNP",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "AD Flow Q Not Empty : VN1 SNP Messages : Number of cycles the AD Egress queue is Not Empty",
"UMask": "0x20",
"Unit": "M3UPI"
},
{
"BriefDescription": "AD Flow Q Not Empty : VN1 WB Messages",
"Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN1_WB",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "AD Flow Q Not Empty : VN1 WB Messages : Number of cycles the AD Egress queue is Not Empty",
"UMask": "0x80",
"Unit": "M3UPI"
},
{
"BriefDescription": "AD Flow Q Inserts : VN0 REQ Messages",
"Counter": "0,1,2,3",
"EventCode": "0x2D",
"EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN0_REQ",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "AD Flow Q Inserts : VN0 REQ Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.",
"UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "AD Flow Q Inserts : VN0 RSP Messages",
"Counter": "0,1,2,3",
"EventCode": "0x2D",
"EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN0_RSP",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "AD Flow Q Inserts : VN0 RSP Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.",
"UMask": "0x4",
"Unit": "M3UPI"
},
{
"BriefDescription": "AD Flow Q Inserts : VN0 SNP Messages",
"Counter": "0,1,2,3",
"EventCode": "0x2D",
"EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN0_SNP",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "AD Flow Q Inserts : VN0 SNP Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.",
"UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "AD Flow Q Inserts : VN0 WB Messages",
"Counter": "0,1,2,3",
"EventCode": "0x2D",
"EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN0_WB",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "AD Flow Q Inserts : VN0 WB Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.",
"UMask": "0x8",
"Unit": "M3UPI"
},
{
"BriefDescription": "AD Flow Q Inserts : VN1 REQ Messages",
"Counter": "0,1,2,3",
"EventCode": "0x2D",
"EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN1_REQ",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "AD Flow Q Inserts : VN1 REQ Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.",
"UMask": "0x10",
"Unit": "M3UPI"
},
{
"BriefDescription": "AD Flow Q Inserts : VN1 RSP Messages",
"Counter": "0,1,2,3",
"EventCode": "0x2D",
"EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN1_RSP",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "AD Flow Q Inserts : VN1 RSP Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.",
"UMask": "0x40",
"Unit": "M3UPI"
},
{
"BriefDescription": "AD Flow Q Inserts : VN1 SNP Messages",
"Counter": "0,1,2,3",
"EventCode": "0x2D",
"EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN1_SNP",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "AD Flow Q Inserts : VN1 SNP Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.",
"UMask": "0x20",
"Unit": "M3UPI"
},
{
"BriefDescription": "AD Flow Q Occupancy : VN0 REQ Messages",
"Counter": "0",
"EventCode": "0x1C",
"EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN0_REQ",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "AD Flow Q Occupancy : VN0 RSP Messages",
"Counter": "0",
"EventCode": "0x1C",
"EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN0_RSP",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "M3UPI"
},
{
"BriefDescription": "AD Flow Q Occupancy : VN0 SNP Messages",
"Counter": "0",
"EventCode": "0x1C",
"EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN0_SNP",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "AD Flow Q Occupancy : VN0 WB Messages",
"Counter": "0",
"EventCode": "0x1C",
"EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN0_WB",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "M3UPI"
},
{
"BriefDescription": "AD Flow Q Occupancy : VN1 REQ Messages",
"Counter": "0",
"EventCode": "0x1C",
"EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN1_REQ",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "M3UPI"
},
{
"BriefDescription": "AD Flow Q Occupancy : VN1 RSP Messages",
"Counter": "0",
"EventCode": "0x1C",
"EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN1_RSP",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x40",
"Unit": "M3UPI"
},
{
"BriefDescription": "AD Flow Q Occupancy : VN1 SNP Messages",
"Counter": "0",
"EventCode": "0x1C",
"EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN1_SNP",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "M3UPI"
},
{
"BriefDescription": "AK Flow Q Inserts",
"Counter": "0,1,2,3",
"EventCode": "0x2F",
"EventName": "UNC_M3UPI_TxC_AK_FLQ_INSERTS",
"Experimental": "1",
"PerPkg": "1",
"Unit": "M3UPI"
},
{
"BriefDescription": "AK Flow Q Occupancy",
"Counter": "0",
"EventCode": "0x1E",
"EventName": "UNC_M3UPI_TxC_AK_FLQ_OCCUPANCY",
"Experimental": "1",
"PerPkg": "1",
"Unit": "M3UPI"
},
{
"BriefDescription": "Failed ARB for BL : VN0 NCB Messages",
"Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN0_NCB",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Failed ARB for BL : VN0 NCB Messages : BL arb but no win; arb request asserted but not won",
"UMask": "0x4",
"Unit": "M3UPI"
},
{
"BriefDescription": "Failed ARB for BL : VN0 NCS Messages",
"Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN0_NCS",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Failed ARB for BL : VN0 NCS Messages : BL arb but no win; arb request asserted but not won",
"UMask": "0x8",
"Unit": "M3UPI"
},
{
"BriefDescription": "Failed ARB for BL : VN0 RSP Messages",
"Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN0_RSP",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Failed ARB for BL : VN0 RSP Messages : BL arb but no win; arb request asserted but not won",
"UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "Failed ARB for BL : VN0 WB Messages",
"Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN0_WB",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Failed ARB for BL : VN0 WB Messages : BL arb but no win; arb request asserted but not won",
"UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "Failed ARB for BL : VN1 NCS Messages",
"Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN1_NCB",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Failed ARB for BL : VN1 NCS Messages : BL arb but no win; arb request asserted but not won",
"UMask": "0x40",
"Unit": "M3UPI"
},
{
"BriefDescription": "Failed ARB for BL : VN1 NCB Messages",
"Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN1_NCS",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Failed ARB for BL : VN1 NCB Messages : BL arb but no win; arb request asserted but not won",
"UMask": "0x80",
"Unit": "M3UPI"
},
{
"BriefDescription": "Failed ARB for BL : VN1 RSP Messages",
"Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN1_RSP",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Failed ARB for BL : VN1 RSP Messages : BL arb but no win; arb request asserted but not won",
"UMask": "0x10",
"Unit": "M3UPI"
},
{
"BriefDescription": "Failed ARB for BL : VN1 WB Messages",
"Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN1_WB",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Failed ARB for BL : VN1 WB Messages : BL arb but no win; arb request asserted but not won",
"UMask": "0x20",
"Unit": "M3UPI"
},
{
"BriefDescription": "BL Flow Q Not Empty : VN0 REQ Messages",
"Counter": "0,1,2,3",
"EventCode": "0x28",
"EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN0_REQ",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "BL Flow Q Not Empty : VN0 REQ Messages : Number of cycles the BL Egress queue is Not Empty",
"UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "BL Flow Q Not Empty : VN0 RSP Messages",
"Counter": "0,1,2,3",
"EventCode": "0x28",
"EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN0_RSP",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "BL Flow Q Not Empty : VN0 RSP Messages : Number of cycles the BL Egress queue is Not Empty",
"UMask": "0x4",
"Unit": "M3UPI"
},
{
"BriefDescription": "BL Flow Q Not Empty : VN0 SNP Messages",
"Counter": "0,1,2,3",
"EventCode": "0x28",
"EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN0_SNP",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "BL Flow Q Not Empty : VN0 SNP Messages : Number of cycles the BL Egress queue is Not Empty",
"UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "BL Flow Q Not Empty : VN0 WB Messages",
"Counter": "0,1,2,3",
"EventCode": "0x28",
"EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN0_WB",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "BL Flow Q Not Empty : VN0 WB Messages : Number of cycles the BL Egress queue is Not Empty",
"UMask": "0x8",
"Unit": "M3UPI"
},
{
"BriefDescription": "BL Flow Q Not Empty : VN1 REQ Messages",
"Counter": "0,1,2,3",
"EventCode": "0x28",
"EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN1_REQ",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "BL Flow Q Not Empty : VN1 REQ Messages : Number of cycles the BL Egress queue is Not Empty",
"UMask": "0x10",
"Unit": "M3UPI"
},
{
"BriefDescription": "BL Flow Q Not Empty : VN1 RSP Messages",
"Counter": "0,1,2,3",
"EventCode": "0x28",
"EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN1_RSP",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "BL Flow Q Not Empty : VN1 RSP Messages : Number of cycles the BL Egress queue is Not Empty",
"UMask": "0x40",
"Unit": "M3UPI"
},
{
"BriefDescription": "BL Flow Q Not Empty : VN1 SNP Messages",
"Counter": "0,1,2,3",
"EventCode": "0x28",
"EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN1_SNP",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "BL Flow Q Not Empty : VN1 SNP Messages : Number of cycles the BL Egress queue is Not Empty",
"UMask": "0x20",
"Unit": "M3UPI"
},
{
"BriefDescription": "BL Flow Q Not Empty : VN1 WB Messages",
"Counter": "0,1,2,3",
"EventCode": "0x28",
"EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN1_WB",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "BL Flow Q Not Empty : VN1 WB Messages : Number of cycles the BL Egress queue is Not Empty",
"UMask": "0x80",
"Unit": "M3UPI"
},
{
"BriefDescription": "BL Flow Q Inserts : VN0 RSP Messages",
"Counter": "0,1,2,3",
"EventCode": "0x2E",
"EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN0_NCB",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "BL Flow Q Inserts : VN0 RSP Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.",
"UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "BL Flow Q Inserts : VN0 WB Messages",
"Counter": "0,1,2,3",
"EventCode": "0x2E",
"EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN0_NCS",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "BL Flow Q Inserts : VN0 WB Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.",
"UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "BL Flow Q Inserts : VN0 NCS Messages",
"Counter": "0,1,2,3",
"EventCode": "0x2E",
"EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN0_RSP",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "BL Flow Q Inserts : VN0 NCS Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.",
"UMask": "0x8",
"Unit": "M3UPI"
},
{
"BriefDescription": "BL Flow Q Inserts : VN0 NCB Messages",
"Counter": "0,1,2,3",
"EventCode": "0x2E",
"EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN0_WB",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "BL Flow Q Inserts : VN0 NCB Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.",
"UMask": "0x4",
"Unit": "M3UPI"
},
{
"BriefDescription": "BL Flow Q Inserts : VN1 RSP Messages",
"Counter": "0,1,2,3",
"EventCode": "0x2E",
"EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN1_NCB",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "BL Flow Q Inserts : VN1 RSP Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.",
"UMask": "0x10",
"Unit": "M3UPI"
},
{
"BriefDescription": "BL Flow Q Inserts : VN1 WB Messages",
"Counter": "0,1,2,3",
"EventCode": "0x2E",
"EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN1_NCS",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "BL Flow Q Inserts : VN1 WB Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.",
"UMask": "0x20",
"Unit": "M3UPI"
},
{
"BriefDescription": "BL Flow Q Inserts : VN1_NCB Messages",
"Counter": "0,1,2,3",
"EventCode": "0x2E",
"EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN1_RSP",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "BL Flow Q Inserts : VN1_NCB Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.",
"UMask": "0x80",
"Unit": "M3UPI"
},
{
"BriefDescription": "BL Flow Q Inserts : VN1_NCS Messages",
"Counter": "0,1,2,3",
"EventCode": "0x2E",
"EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN1_WB",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "BL Flow Q Inserts : VN1_NCS Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.",
"UMask": "0x40",
"Unit": "M3UPI"
},
{
"BriefDescription": "BL Flow Q Occupancy : VN0 NCB Messages",
"Counter": "0",
"EventCode": "0x1D",
"EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN0_NCB",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "M3UPI"
},
{
"BriefDescription": "BL Flow Q Occupancy : VN0 NCS Messages",
"Counter": "0",
"EventCode": "0x1D",
"EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN0_NCS",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "M3UPI"
},
{
"BriefDescription": "BL Flow Q Occupancy : VN0 RSP Messages",
"Counter": "0",
"EventCode": "0x1D",
"EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN0_RSP",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "BL Flow Q Occupancy : VN0 WB Messages",
"Counter": "0",
"EventCode": "0x1D",
"EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN0_WB",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "BL Flow Q Occupancy : VN1_NCS Messages",
"Counter": "0",
"EventCode": "0x1D",
"EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN1_NCB",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x40",
"Unit": "M3UPI"
},
{
"BriefDescription": "BL Flow Q Occupancy : VN1_NCB Messages",
"Counter": "0",
"EventCode": "0x1D",
"EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN1_NCS",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x80",
"Unit": "M3UPI"
},
{
"BriefDescription": "BL Flow Q Occupancy : VN1 RSP Messages",
"Counter": "0",
"EventCode": "0x1D",
"EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN1_RSP",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "M3UPI"
},
{
"BriefDescription": "BL Flow Q Occupancy : VN1 WB Messages",
"Counter": "0",
"EventCode": "0x1D",
"EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN1_WB",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "M3UPI"
},
{
"BriefDescription": "BL Flow Q Occupancy : VN0 RSP Messages",
"Counter": "0",
"EventCode": "0x1F",
"EventName": "UNC_M3UPI_TxC_BL_WB_FLQ_OCCUPANCY.VN0_LOCAL",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "BL Flow Q Occupancy : VN0 WB Messages",
"Counter": "0",
"EventCode": "0x1F",
"EventName": "UNC_M3UPI_TxC_BL_WB_FLQ_OCCUPANCY.VN0_THROUGH",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "BL Flow Q Occupancy : VN0 NCB Messages",
"Counter": "0",
"EventCode": "0x1F",
"EventName": "UNC_M3UPI_TxC_BL_WB_FLQ_OCCUPANCY.VN0_WRPULL",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "M3UPI"
},
{
"BriefDescription": "BL Flow Q Occupancy : VN1 RSP Messages",
"Counter": "0",
"EventCode": "0x1F",
"EventName": "UNC_M3UPI_TxC_BL_WB_FLQ_OCCUPANCY.VN1_LOCAL",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "M3UPI"
},
{
"BriefDescription": "BL Flow Q Occupancy : VN1 WB Messages",
"Counter": "0",
"EventCode": "0x1F",
"EventName": "UNC_M3UPI_TxC_BL_WB_FLQ_OCCUPANCY.VN1_THROUGH",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "M3UPI"
},
{
"BriefDescription": "BL Flow Q Occupancy : VN1_NCS Messages",
"Counter": "0",
"EventCode": "0x1F",
"EventName": "UNC_M3UPI_TxC_BL_WB_FLQ_OCCUPANCY.VN1_WRPULL",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x40",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Horizontal ADS Used : AD - All",
"Counter": "0,1,2,3",
"EventCode": "0xA6",
"EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.AD_ALL",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal ADS Used : AD - All : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent. : All == Credited + Uncredited",
"UMask": "0x11",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Horizontal ADS Used : AD - Credited",
"Counter": "0,1,2,3",
"EventCode": "0xA6",
"EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.AD_CRD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal ADS Used : AD - Credited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
"UMask": "0x10",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Horizontal ADS Used : AD - Uncredited",
"Counter": "0,1,2,3",
"EventCode": "0xA6",
"EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.AD_UNCRD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal ADS Used : AD - Uncredited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
"UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Horizontal ADS Used : BL - All",
"Counter": "0,1,2,3",
"EventCode": "0xA6",
"EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.BL_ALL",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal ADS Used : BL - All : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent. : All == Credited + Uncredited",
"UMask": "0x44",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Horizontal ADS Used : BL - Credited",
"Counter": "0,1,2,3",
"EventCode": "0xA6",
"EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.BL_CRD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal ADS Used : BL - Credited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
"UMask": "0x40",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Horizontal ADS Used : BL - Uncredited",
"Counter": "0,1,2,3",
"EventCode": "0xA6",
"EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.BL_UNCRD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal ADS Used : BL - Uncredited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
"UMask": "0x4",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Horizontal Bypass Used : AD - All",
"Counter": "0,1,2,3",
"EventCode": "0xA7",
"EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.AD_ALL",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Bypass Used : AD - All : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent. : All == Credited + Uncredited",
"UMask": "0x11",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Horizontal Bypass Used : AD - Credited",
"Counter": "0,1,2,3",
"EventCode": "0xA7",
"EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.AD_CRD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Bypass Used : AD - Credited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
"UMask": "0x10",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Horizontal Bypass Used : AD - Uncredited",
"Counter": "0,1,2,3",
"EventCode": "0xA7",
"EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.AD_UNCRD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Bypass Used : AD - Uncredited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
"UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Horizontal Bypass Used : AK",
"Counter": "0,1,2,3",
"EventCode": "0xA7",
"EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.AK",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Bypass Used : AK : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
"UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Horizontal Bypass Used : AKC - Uncredited",
"Counter": "0,1,2,3",
"EventCode": "0xA7",
"EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.AKC_UNCRD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Bypass Used : AKC - Uncredited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
"UMask": "0x80",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Horizontal Bypass Used : BL - All",
"Counter": "0,1,2,3",
"EventCode": "0xA7",
"EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.BL_ALL",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Bypass Used : BL - All : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent. : All == Credited + Uncredited",
"UMask": "0x44",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Horizontal Bypass Used : BL - Credited",
"Counter": "0,1,2,3",
"EventCode": "0xA7",
"EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.BL_CRD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Bypass Used : BL - Credited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
"UMask": "0x40",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Horizontal Bypass Used : BL - Uncredited",
"Counter": "0,1,2,3",
"EventCode": "0xA7",
"EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.BL_UNCRD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Bypass Used : BL - Uncredited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
"UMask": "0x4",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Horizontal Bypass Used : IV",
"Counter": "0,1,2,3",
"EventCode": "0xA7",
"EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.IV",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Bypass Used : IV : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
"UMask": "0x8",
"Unit": "M3UPI"
},
{
"BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - All",
"Counter": "0,1,2,3",
"EventCode": "0xA2",
"EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.AD_ALL",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - All : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
"UMask": "0x11",
"Unit": "M3UPI"
},
{
"BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Credited",
"Counter": "0,1,2,3",
"EventCode": "0xA2",
"EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.AD_CRD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x10",
"Unit": "M3UPI"
},
{
"BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Uncredited",
"Counter": "0,1,2,3",
"EventCode": "0xA2",
"EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.AD_UNCRD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AK",
"Counter": "0,1,2,3",
"EventCode": "0xA2",
"EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.AK",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AK : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AKC - Uncredited",
"Counter": "0,1,2,3",
"EventCode": "0xA2",
"EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.AKC_UNCRD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AKC - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x80",
"Unit": "M3UPI"
},
{
"BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - All",
"Counter": "0,1,2,3",
"EventCode": "0xA2",
"EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.BL_ALL",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - All : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
"UMask": "0x44",
"Unit": "M3UPI"
},
{
"BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Credited",
"Counter": "0,1,2,3",
"EventCode": "0xA2",
"EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.BL_CRD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x40",
"Unit": "M3UPI"
},
{
"BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Uncredited",
"Counter": "0,1,2,3",
"EventCode": "0xA2",
"EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.BL_UNCRD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x4",
"Unit": "M3UPI"
},
{
"BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : IV",
"Counter": "0,1,2,3",
"EventCode": "0xA2",
"EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.IV",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : IV : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x8",
"Unit": "M3UPI"
},
{
"BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - All",
"Counter": "0,1,2,3",
"EventCode": "0xA3",
"EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.AD_ALL",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - All : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
"UMask": "0x11",
"Unit": "M3UPI"
},
{
"BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Credited",
"Counter": "0,1,2,3",
"EventCode": "0xA3",
"EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.AD_CRD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x10",
"Unit": "M3UPI"
},
{
"BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Uncredited",
"Counter": "0,1,2,3",
"EventCode": "0xA3",
"EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.AD_UNCRD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AK",
"Counter": "0,1,2,3",
"EventCode": "0xA3",
"EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.AK",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AK : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AKC - Uncredited",
"Counter": "0,1,2,3",
"EventCode": "0xA3",
"EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.AKC_UNCRD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AKC - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x80",
"Unit": "M3UPI"
},
{
"BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - All",
"Counter": "0,1,2,3",
"EventCode": "0xA3",
"EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.BL_ALL",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - All : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
"UMask": "0x44",
"Unit": "M3UPI"
},
{
"BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Credited",
"Counter": "0,1,2,3",
"EventCode": "0xA3",
"EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.BL_CRD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x40",
"Unit": "M3UPI"
},
{
"BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Uncredited",
"Counter": "0,1,2,3",
"EventCode": "0xA3",
"EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.BL_UNCRD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x4",
"Unit": "M3UPI"
},
{
"BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : IV",
"Counter": "0,1,2,3",
"EventCode": "0xA3",
"EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.IV",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : IV : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x8",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Horizontal Egress Inserts : AD - All",
"Counter": "0,1,2,3",
"EventCode": "0xA1",
"EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.AD_ALL",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress Inserts : AD - All : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
"UMask": "0x11",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Horizontal Egress Inserts : AD - Credited",
"Counter": "0,1,2,3",
"EventCode": "0xA1",
"EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.AD_CRD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress Inserts : AD - Credited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x10",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Horizontal Egress Inserts : AD - Uncredited",
"Counter": "0,1,2,3",
"EventCode": "0xA1",
"EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.AD_UNCRD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress Inserts : AD - Uncredited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Horizontal Egress Inserts : AK",
"Counter": "0,1,2,3",
"EventCode": "0xA1",
"EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.AK",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress Inserts : AK : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Horizontal Egress Inserts : AKC - Uncredited",
"Counter": "0,1,2,3",
"EventCode": "0xA1",
"EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.AKC_UNCRD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress Inserts : AKC - Uncredited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x80",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Horizontal Egress Inserts : BL - All",
"Counter": "0,1,2,3",
"EventCode": "0xA1",
"EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.BL_ALL",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress Inserts : BL - All : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
"UMask": "0x44",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Horizontal Egress Inserts : BL - Credited",
"Counter": "0,1,2,3",
"EventCode": "0xA1",
"EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.BL_CRD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress Inserts : BL - Credited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x40",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Horizontal Egress Inserts : BL - Uncredited",
"Counter": "0,1,2,3",
"EventCode": "0xA1",
"EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.BL_UNCRD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress Inserts : BL - Uncredited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x4",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Horizontal Egress Inserts : IV",
"Counter": "0,1,2,3",
"EventCode": "0xA1",
"EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.IV",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress Inserts : IV : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x8",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Horizontal Egress NACKs : AD - All",
"Counter": "0,1,2,3",
"EventCode": "0xA4",
"EventName": "UNC_M3UPI_TxR_HORZ_NACK.AD_ALL",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress NACKs : AD - All : Counts number of Egress packets NACK'ed on to the Horizontal Ring : All == Credited + Uncredited",
"UMask": "0x11",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Horizontal Egress NACKs : AD - Credited",
"Counter": "0,1,2,3",
"EventCode": "0xA4",
"EventName": "UNC_M3UPI_TxR_HORZ_NACK.AD_CRD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress NACKs : AD - Credited : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
"UMask": "0x10",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Horizontal Egress NACKs : AD - Uncredited",
"Counter": "0,1,2,3",
"EventCode": "0xA4",
"EventName": "UNC_M3UPI_TxR_HORZ_NACK.AD_UNCRD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress NACKs : AD - Uncredited : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
"UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Horizontal Egress NACKs : AK",
"Counter": "0,1,2,3",
"EventCode": "0xA4",
"EventName": "UNC_M3UPI_TxR_HORZ_NACK.AK",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress NACKs : AK : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
"UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Horizontal Egress NACKs : AKC - Uncredited",
"Counter": "0,1,2,3",
"EventCode": "0xA4",
"EventName": "UNC_M3UPI_TxR_HORZ_NACK.AKC_UNCRD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress NACKs : AKC - Uncredited : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
"UMask": "0x80",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Horizontal Egress NACKs : BL - All",
"Counter": "0,1,2,3",
"EventCode": "0xA4",
"EventName": "UNC_M3UPI_TxR_HORZ_NACK.BL_ALL",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress NACKs : BL - All : Counts number of Egress packets NACK'ed on to the Horizontal Ring : All == Credited + Uncredited",
"UMask": "0x44",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Horizontal Egress NACKs : BL - Credited",
"Counter": "0,1,2,3",
"EventCode": "0xA4",
"EventName": "UNC_M3UPI_TxR_HORZ_NACK.BL_CRD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress NACKs : BL - Credited : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
"UMask": "0x40",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Horizontal Egress NACKs : BL - Uncredited",
"Counter": "0,1,2,3",
"EventCode": "0xA4",
"EventName": "UNC_M3UPI_TxR_HORZ_NACK.BL_UNCRD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress NACKs : BL - Uncredited : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
"UMask": "0x4",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Horizontal Egress NACKs : IV",
"Counter": "0,1,2,3",
"EventCode": "0xA4",
"EventName": "UNC_M3UPI_TxR_HORZ_NACK.IV",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress NACKs : IV : Counts number of Egress packets NACK'ed on to the Horizontal Ring",
"UMask": "0x8",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Horizontal Egress Occupancy : AD - All",
"Counter": "0,1,2,3",
"EventCode": "0xA0",
"EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.AD_ALL",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress Occupancy : AD - All : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
"UMask": "0x11",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Horizontal Egress Occupancy : AD - Credited",
"Counter": "0,1,2,3",
"EventCode": "0xA0",
"EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.AD_CRD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress Occupancy : AD - Credited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x10",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Horizontal Egress Occupancy : AD - Uncredited",
"Counter": "0,1,2,3",
"EventCode": "0xA0",
"EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.AD_UNCRD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress Occupancy : AD - Uncredited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Horizontal Egress Occupancy : AK",
"Counter": "0,1,2,3",
"EventCode": "0xA0",
"EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.AK",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress Occupancy : AK : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Horizontal Egress Occupancy : AKC - Uncredited",
"Counter": "0,1,2,3",
"EventCode": "0xA0",
"EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.AKC_UNCRD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress Occupancy : AKC - Uncredited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x80",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Horizontal Egress Occupancy : BL - All",
"Counter": "0,1,2,3",
"EventCode": "0xA0",
"EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.BL_ALL",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress Occupancy : BL - All : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited",
"UMask": "0x44",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Horizontal Egress Occupancy : BL - Credited",
"Counter": "0,1,2,3",
"EventCode": "0xA0",
"EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.BL_CRD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress Occupancy : BL - Credited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x40",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Horizontal Egress Occupancy : BL - Uncredited",
"Counter": "0,1,2,3",
"EventCode": "0xA0",
"EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.BL_UNCRD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress Occupancy : BL - Uncredited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x4",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Horizontal Egress Occupancy : IV",
"Counter": "0,1,2,3",
"EventCode": "0xA0",
"EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.IV",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress Occupancy : IV : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x8",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Horizontal Egress Injection Starvation : AD - All",
"Counter": "0,1,2,3",
"EventCode": "0xA5",
"EventName": "UNC_M3UPI_TxR_HORZ_STARVED.AD_ALL",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress Injection Starvation : AD - All : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time. : All == Credited + Uncredited",
"UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Horizontal Egress Injection Starvation : AD - Uncredited",
"Counter": "0,1,2,3",
"EventCode": "0xA5",
"EventName": "UNC_M3UPI_TxR_HORZ_STARVED.AD_UNCRD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress Injection Starvation : AD - Uncredited : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
"UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Horizontal Egress Injection Starvation : AK",
"Counter": "0,1,2,3",
"EventCode": "0xA5",
"EventName": "UNC_M3UPI_TxR_HORZ_STARVED.AK",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress Injection Starvation : AK : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
"UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Horizontal Egress Injection Starvation : AKC - Uncredited",
"Counter": "0,1,2,3",
"EventCode": "0xA5",
"EventName": "UNC_M3UPI_TxR_HORZ_STARVED.AKC_UNCRD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress Injection Starvation : AKC - Uncredited : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
"UMask": "0x80",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Horizontal Egress Injection Starvation : BL - All",
"Counter": "0,1,2,3",
"EventCode": "0xA5",
"EventName": "UNC_M3UPI_TxR_HORZ_STARVED.BL_ALL",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress Injection Starvation : BL - All : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time. : All == Credited + Uncredited",
"UMask": "0x4",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Horizontal Egress Injection Starvation : BL - Uncredited",
"Counter": "0,1,2,3",
"EventCode": "0xA5",
"EventName": "UNC_M3UPI_TxR_HORZ_STARVED.BL_UNCRD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress Injection Starvation : BL - Uncredited : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
"UMask": "0x4",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Horizontal Egress Injection Starvation : IV",
"Counter": "0,1,2,3",
"EventCode": "0xA5",
"EventName": "UNC_M3UPI_TxR_HORZ_STARVED.IV",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Horizontal Egress Injection Starvation : IV : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
"UMask": "0x8",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Vertical ADS Used : AD - Agent 0",
"Counter": "0,1,2,3",
"EventCode": "0x9C",
"EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.AD_AG0",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical ADS Used : AD - Agent 0 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
"UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Vertical ADS Used : AD - Agent 1",
"Counter": "0,1,2,3",
"EventCode": "0x9C",
"EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.AD_AG1",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical ADS Used : AD - Agent 1 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
"UMask": "0x10",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Vertical ADS Used : BL - Agent 0",
"Counter": "0,1,2,3",
"EventCode": "0x9C",
"EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.BL_AG0",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical ADS Used : BL - Agent 0 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
"UMask": "0x4",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Vertical ADS Used : BL - Agent 1",
"Counter": "0,1,2,3",
"EventCode": "0x9C",
"EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.BL_AG1",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical ADS Used : BL - Agent 1 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
"UMask": "0x40",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Vertical ADS Used : AD - Agent 0",
"Counter": "0,1,2,3",
"EventCode": "0x9D",
"EventName": "UNC_M3UPI_TxR_VERT_BYPASS.AD_AG0",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical ADS Used : AD - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
"UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Vertical ADS Used : AD - Agent 1",
"Counter": "0,1,2,3",
"EventCode": "0x9D",
"EventName": "UNC_M3UPI_TxR_VERT_BYPASS.AD_AG1",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical ADS Used : AD - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
"UMask": "0x10",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Vertical ADS Used : AK - Agent 0",
"Counter": "0,1,2,3",
"EventCode": "0x9D",
"EventName": "UNC_M3UPI_TxR_VERT_BYPASS.AK_AG0",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical ADS Used : AK - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
"UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Vertical ADS Used : AK - Agent 1",
"Counter": "0,1,2,3",
"EventCode": "0x9D",
"EventName": "UNC_M3UPI_TxR_VERT_BYPASS.AK_AG1",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical ADS Used : AK - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
"UMask": "0x20",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Vertical ADS Used : BL - Agent 0",
"Counter": "0,1,2,3",
"EventCode": "0x9D",
"EventName": "UNC_M3UPI_TxR_VERT_BYPASS.BL_AG0",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical ADS Used : BL - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
"UMask": "0x4",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Vertical ADS Used : BL - Agent 1",
"Counter": "0,1,2,3",
"EventCode": "0x9D",
"EventName": "UNC_M3UPI_TxR_VERT_BYPASS.BL_AG1",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical ADS Used : BL - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
"UMask": "0x40",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Vertical ADS Used : IV - Agent 1",
"Counter": "0,1,2,3",
"EventCode": "0x9D",
"EventName": "UNC_M3UPI_TxR_VERT_BYPASS.IV_AG1",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical ADS Used : IV - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
"UMask": "0x8",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Vertical ADS Used : AKC - Agent 0",
"Counter": "0,1,2,3",
"EventCode": "0x9E",
"EventName": "UNC_M3UPI_TxR_VERT_BYPASS_1.AKC_AG0",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical ADS Used : AKC - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
"UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Vertical ADS Used : AKC - Agent 1",
"Counter": "0,1,2,3",
"EventCode": "0x9E",
"EventName": "UNC_M3UPI_TxR_VERT_BYPASS_1.AKC_AG1",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical ADS Used : AKC - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
"UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 0",
"Counter": "0,1,2,3",
"EventCode": "0x94",
"EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL0.AD_AG0",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.",
"UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 1",
"Counter": "0,1,2,3",
"EventCode": "0x94",
"EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL0.AD_AG1",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.",
"UMask": "0x10",
"Unit": "M3UPI"
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 0",
"Counter": "0,1,2,3",
"EventCode": "0x94",
"EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL0.AK_AG0",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.",
"UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 1",
"Counter": "0,1,2,3",
"EventCode": "0x94",
"EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL0.AK_AG1",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.",
"UMask": "0x20",
"Unit": "M3UPI"
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 0",
"Counter": "0,1,2,3",
"EventCode": "0x94",
"EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL0.BL_AG0",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.",
"UMask": "0x4",
"Unit": "M3UPI"
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 1",
"Counter": "0,1,2,3",
"EventCode": "0x94",
"EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL0.BL_AG1",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.",
"UMask": "0x40",
"Unit": "M3UPI"
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : IV - Agent 0",
"Counter": "0,1,2,3",
"EventCode": "0x94",
"EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL0.IV_AG0",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : IV - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.",
"UMask": "0x8",
"Unit": "M3UPI"
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 0",
"Counter": "0,1,2,3",
"EventCode": "0x95",
"EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL1.AKC_AG0",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.",
"UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 1",
"Counter": "0,1,2,3",
"EventCode": "0x95",
"EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL1.AKC_AG1",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.",
"UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 0",
"Counter": "0,1,2,3",
"EventCode": "0x96",
"EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE0.AD_AG0",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.",
"UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 1",
"Counter": "0,1,2,3",
"EventCode": "0x96",
"EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE0.AD_AG1",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.",
"UMask": "0x10",
"Unit": "M3UPI"
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 0",
"Counter": "0,1,2,3",
"EventCode": "0x96",
"EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE0.AK_AG0",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.",
"UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 1",
"Counter": "0,1,2,3",
"EventCode": "0x96",
"EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE0.AK_AG1",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.",
"UMask": "0x20",
"Unit": "M3UPI"
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 0",
"Counter": "0,1,2,3",
"EventCode": "0x96",
"EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE0.BL_AG0",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.",
"UMask": "0x4",
"Unit": "M3UPI"
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 1",
"Counter": "0,1,2,3",
"EventCode": "0x96",
"EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE0.BL_AG1",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.",
"UMask": "0x40",
"Unit": "M3UPI"
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : IV - Agent 0",
"Counter": "0,1,2,3",
"EventCode": "0x96",
"EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE0.IV_AG0",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : IV - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.",
"UMask": "0x8",
"Unit": "M3UPI"
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 0",
"Counter": "0,1,2,3",
"EventCode": "0x97",
"EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE1.AKC_AG0",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.",
"UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 1",
"Counter": "0,1,2,3",
"EventCode": "0x97",
"EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE1.AKC_AG1",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.",
"UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Vert Egress Allocations : AD - Agent 0",
"Counter": "0,1,2,3",
"EventCode": "0x92",
"EventName": "UNC_M3UPI_TxR_VERT_INSERTS0.AD_AG0",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vert Egress Allocations : AD - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.",
"UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Vert Egress Allocations : AD - Agent 1",
"Counter": "0,1,2,3",
"EventCode": "0x92",
"EventName": "UNC_M3UPI_TxR_VERT_INSERTS0.AD_AG1",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vert Egress Allocations : AD - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.",
"UMask": "0x10",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Vert Egress Allocations : AK - Agent 0",
"Counter": "0,1,2,3",
"EventCode": "0x92",
"EventName": "UNC_M3UPI_TxR_VERT_INSERTS0.AK_AG0",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vert Egress Allocations : AK - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.",
"UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Vert Egress Allocations : AK - Agent 1",
"Counter": "0,1,2,3",
"EventCode": "0x92",
"EventName": "UNC_M3UPI_TxR_VERT_INSERTS0.AK_AG1",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vert Egress Allocations : AK - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.",
"UMask": "0x20",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Vert Egress Allocations : BL - Agent 0",
"Counter": "0,1,2,3",
"EventCode": "0x92",
"EventName": "UNC_M3UPI_TxR_VERT_INSERTS0.BL_AG0",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vert Egress Allocations : BL - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.",
"UMask": "0x4",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Vert Egress Allocations : BL - Agent 1",
"Counter": "0,1,2,3",
"EventCode": "0x92",
"EventName": "UNC_M3UPI_TxR_VERT_INSERTS0.BL_AG1",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vert Egress Allocations : BL - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.",
"UMask": "0x40",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Vert Egress Allocations : IV - Agent 0",
"Counter": "0,1,2,3",
"EventCode": "0x92",
"EventName": "UNC_M3UPI_TxR_VERT_INSERTS0.IV_AG0",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vert Egress Allocations : IV - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.",
"UMask": "0x8",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Vert Egress Allocations : AKC - Agent 0",
"Counter": "0,1,2,3",
"EventCode": "0x93",
"EventName": "UNC_M3UPI_TxR_VERT_INSERTS1.AKC_AG0",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vert Egress Allocations : AKC - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.",
"UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Vert Egress Allocations : AKC - Agent 1",
"Counter": "0,1,2,3",
"EventCode": "0x93",
"EventName": "UNC_M3UPI_TxR_VERT_INSERTS1.AKC_AG1",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vert Egress Allocations : AKC - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.",
"UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Vertical Egress NACKs : AD - Agent 0",
"Counter": "0,1,2,3",
"EventCode": "0x98",
"EventName": "UNC_M3UPI_TxR_VERT_NACK0.AD_AG0",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical Egress NACKs : AD - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
"UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Vertical Egress NACKs : AD - Agent 1",
"Counter": "0,1,2,3",
"EventCode": "0x98",
"EventName": "UNC_M3UPI_TxR_VERT_NACK0.AD_AG1",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical Egress NACKs : AD - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
"UMask": "0x10",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Vertical Egress NACKs : AK - Agent 0",
"Counter": "0,1,2,3",
"EventCode": "0x98",
"EventName": "UNC_M3UPI_TxR_VERT_NACK0.AK_AG0",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical Egress NACKs : AK - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
"UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Vertical Egress NACKs : AK - Agent 1",
"Counter": "0,1,2,3",
"EventCode": "0x98",
"EventName": "UNC_M3UPI_TxR_VERT_NACK0.AK_AG1",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical Egress NACKs : AK - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
"UMask": "0x20",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Vertical Egress NACKs : BL - Agent 0",
"Counter": "0,1,2,3",
"EventCode": "0x98",
"EventName": "UNC_M3UPI_TxR_VERT_NACK0.BL_AG0",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical Egress NACKs : BL - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
"UMask": "0x4",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Vertical Egress NACKs : BL - Agent 1",
"Counter": "0,1,2,3",
"EventCode": "0x98",
"EventName": "UNC_M3UPI_TxR_VERT_NACK0.BL_AG1",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical Egress NACKs : BL - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
"UMask": "0x40",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Vertical Egress NACKs : IV",
"Counter": "0,1,2,3",
"EventCode": "0x98",
"EventName": "UNC_M3UPI_TxR_VERT_NACK0.IV_AG0",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical Egress NACKs : IV : Counts number of Egress packets NACK'ed on to the Vertical Ring",
"UMask": "0x8",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Vertical Egress NACKs : AKC - Agent 0",
"Counter": "0,1,2,3",
"EventCode": "0x99",
"EventName": "UNC_M3UPI_TxR_VERT_NACK1.AKC_AG0",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical Egress NACKs : AKC - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
"UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Vertical Egress NACKs : AKC - Agent 1",
"Counter": "0,1,2,3",
"EventCode": "0x99",
"EventName": "UNC_M3UPI_TxR_VERT_NACK1.AKC_AG1",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical Egress NACKs : AKC - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring",
"UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Vert Egress Occupancy : AD - Agent 0",
"Counter": "0,1,2,3",
"EventCode": "0x90",
"EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY0.AD_AG0",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vert Egress Occupancy : AD - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.",
"UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Vert Egress Occupancy : AD - Agent 1",
"Counter": "0,1,2,3",
"EventCode": "0x90",
"EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY0.AD_AG1",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vert Egress Occupancy : AD - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.",
"UMask": "0x10",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Vert Egress Occupancy : AK - Agent 0",
"Counter": "0,1,2,3",
"EventCode": "0x90",
"EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY0.AK_AG0",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vert Egress Occupancy : AK - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.",
"UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Vert Egress Occupancy : AK - Agent 1",
"Counter": "0,1,2,3",
"EventCode": "0x90",
"EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY0.AK_AG1",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vert Egress Occupancy : AK - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.",
"UMask": "0x20",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Vert Egress Occupancy : BL - Agent 0",
"Counter": "0,1,2,3",
"EventCode": "0x90",
"EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY0.BL_AG0",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vert Egress Occupancy : BL - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.",
"UMask": "0x4",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Vert Egress Occupancy : BL - Agent 1",
"Counter": "0,1,2,3",
"EventCode": "0x90",
"EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY0.BL_AG1",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vert Egress Occupancy : BL - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.",
"UMask": "0x40",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Vert Egress Occupancy : IV - Agent 0",
"Counter": "0,1,2,3",
"EventCode": "0x90",
"EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY0.IV_AG0",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vert Egress Occupancy : IV - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.",
"UMask": "0x8",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Vert Egress Occupancy : AKC - Agent 0",
"Counter": "0,1,2,3",
"EventCode": "0x91",
"EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY1.AKC_AG0",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vert Egress Occupancy : AKC - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.",
"UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Vert Egress Occupancy : AKC - Agent 1",
"Counter": "0,1,2,3",
"EventCode": "0x91",
"EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY1.AKC_AG1",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vert Egress Occupancy : AKC - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.",
"UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 0",
"Counter": "0,1,2,3",
"EventCode": "0x9A",
"EventName": "UNC_M3UPI_TxR_VERT_STARVED0.AD_AG0",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
"UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 1",
"Counter": "0,1,2,3",
"EventCode": "0x9A",
"EventName": "UNC_M3UPI_TxR_VERT_STARVED0.AD_AG1",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
"UMask": "0x10",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 0",
"Counter": "0,1,2,3",
"EventCode": "0x9A",
"EventName": "UNC_M3UPI_TxR_VERT_STARVED0.AK_AG0",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
"UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 1",
"Counter": "0,1,2,3",
"EventCode": "0x9A",
"EventName": "UNC_M3UPI_TxR_VERT_STARVED0.AK_AG1",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
"UMask": "0x20",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 0",
"Counter": "0,1,2,3",
"EventCode": "0x9A",
"EventName": "UNC_M3UPI_TxR_VERT_STARVED0.BL_AG0",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
"UMask": "0x4",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 1",
"Counter": "0,1,2,3",
"EventCode": "0x9A",
"EventName": "UNC_M3UPI_TxR_VERT_STARVED0.BL_AG1",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
"UMask": "0x40",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Vertical Egress Injection Starvation : IV",
"Counter": "0,1,2,3",
"EventCode": "0x9A",
"EventName": "UNC_M3UPI_TxR_VERT_STARVED0.IV_AG0",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical Egress Injection Starvation : IV : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
"UMask": "0x8",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0",
"Counter": "0,1,2,3",
"EventCode": "0x9B",
"EventName": "UNC_M3UPI_TxR_VERT_STARVED1.AKC_AG0",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
"UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 1",
"Counter": "0,1,2,3",
"EventCode": "0x9B",
"EventName": "UNC_M3UPI_TxR_VERT_STARVED1.AKC_AG1",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
"UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0",
"Counter": "0,1,2,3",
"EventCode": "0x9B",
"EventName": "UNC_M3UPI_TxR_VERT_STARVED1.TGC",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
"UMask": "0x4",
"Unit": "M3UPI"
},
{
"BriefDescription": "UPI0 AD Credits Empty : VN0 REQ Messages",
"Counter": "0,1,2,3",
"EventCode": "0x20",
"EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN0_REQ",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "UPI0 AD Credits Empty : VN0 REQ Messages : No credits available to send to UPIs on the AD Ring",
"UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "UPI0 AD Credits Empty : VN0 RSP Messages",
"Counter": "0,1,2,3",
"EventCode": "0x20",
"EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN0_RSP",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "UPI0 AD Credits Empty : VN0 RSP Messages : No credits available to send to UPIs on the AD Ring",
"UMask": "0x8",
"Unit": "M3UPI"
},
{
"BriefDescription": "UPI0 AD Credits Empty : VN0 SNP Messages",
"Counter": "0,1,2,3",
"EventCode": "0x20",
"EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN0_SNP",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "UPI0 AD Credits Empty : VN0 SNP Messages : No credits available to send to UPIs on the AD Ring",
"UMask": "0x4",
"Unit": "M3UPI"
},
{
"BriefDescription": "UPI0 AD Credits Empty : VN1 REQ Messages",
"Counter": "0,1,2,3",
"EventCode": "0x20",
"EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN1_REQ",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "UPI0 AD Credits Empty : VN1 REQ Messages : No credits available to send to UPIs on the AD Ring",
"UMask": "0x10",
"Unit": "M3UPI"
},
{
"BriefDescription": "UPI0 AD Credits Empty : VN1 RSP Messages",
"Counter": "0,1,2,3",
"EventCode": "0x20",
"EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN1_RSP",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "UPI0 AD Credits Empty : VN1 RSP Messages : No credits available to send to UPIs on the AD Ring",
"UMask": "0x40",
"Unit": "M3UPI"
},
{
"BriefDescription": "UPI0 AD Credits Empty : VN1 SNP Messages",
"Counter": "0,1,2,3",
"EventCode": "0x20",
"EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN1_SNP",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "UPI0 AD Credits Empty : VN1 SNP Messages : No credits available to send to UPIs on the AD Ring",
"UMask": "0x20",
"Unit": "M3UPI"
},
{
"BriefDescription": "UPI0 AD Credits Empty : VNA",
"Counter": "0,1,2,3",
"EventCode": "0x20",
"EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VNA",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "UPI0 AD Credits Empty : VNA : No credits available to send to UPIs on the AD Ring",
"UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "UPI0 BL Credits Empty : VN0 RSP Messages",
"Counter": "0,1,2,3",
"EventCode": "0x21",
"EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN0_NCS_NCB",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "UPI0 BL Credits Empty : VN0 RSP Messages : No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode)",
"UMask": "0x4",
"Unit": "M3UPI"
},
{
"BriefDescription": "UPI0 BL Credits Empty : VN0 REQ Messages",
"Counter": "0,1,2,3",
"EventCode": "0x21",
"EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN0_RSP",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "UPI0 BL Credits Empty : VN0 REQ Messages : No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode)",
"UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "UPI0 BL Credits Empty : VN0 SNP Messages",
"Counter": "0,1,2,3",
"EventCode": "0x21",
"EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN0_WB",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "UPI0 BL Credits Empty : VN0 SNP Messages : No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode)",
"UMask": "0x8",
"Unit": "M3UPI"
},
{
"BriefDescription": "UPI0 BL Credits Empty : VN1 RSP Messages",
"Counter": "0,1,2,3",
"EventCode": "0x21",
"EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN1_NCS_NCB",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "UPI0 BL Credits Empty : VN1 RSP Messages : No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode)",
"UMask": "0x20",
"Unit": "M3UPI"
},
{
"BriefDescription": "UPI0 BL Credits Empty : VN1 REQ Messages",
"Counter": "0,1,2,3",
"EventCode": "0x21",
"EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN1_RSP",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "UPI0 BL Credits Empty : VN1 REQ Messages : No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode)",
"UMask": "0x10",
"Unit": "M3UPI"
},
{
"BriefDescription": "UPI0 BL Credits Empty : VN1 SNP Messages",
"Counter": "0,1,2,3",
"EventCode": "0x21",
"EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN1_WB",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "UPI0 BL Credits Empty : VN1 SNP Messages : No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode)",
"UMask": "0x40",
"Unit": "M3UPI"
},
{
"BriefDescription": "UPI0 BL Credits Empty : VNA",
"Counter": "0,1,2,3",
"EventCode": "0x21",
"EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VNA",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "UPI0 BL Credits Empty : VNA : No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode)",
"UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "FlowQ Generated Prefetch",
"Counter": "0,1,2,3",
"EventCode": "0x29",
"EventName": "UNC_M3UPI_UPI_PREFETCH_SPAWN",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "FlowQ Generated Prefetch : Count cases where FlowQ causes spawn of Prefetch to iMC/SMI3 target",
"Unit": "M3UPI"
},
{
"BriefDescription": "Vertical AD Ring In Use : Down and Even",
"Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "UNC_M3UPI_VERT_RING_AD_IN_USE.DN_EVEN",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Vertical AD Ring In Use : Down and Even : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x4",
"Unit": "M3UPI"
},
{
"BriefDescription": "Vertical AD Ring In Use : Down and Odd",
"Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "UNC_M3UPI_VERT_RING_AD_IN_USE.DN_ODD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Vertical AD Ring In Use : Down and Odd : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x8",
"Unit": "M3UPI"
},
{
"BriefDescription": "Vertical AD Ring In Use : Up and Even",
"Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "UNC_M3UPI_VERT_RING_AD_IN_USE.UP_EVEN",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Vertical AD Ring In Use : Up and Even : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "Vertical AD Ring In Use : Up and Odd",
"Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "UNC_M3UPI_VERT_RING_AD_IN_USE.UP_ODD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Vertical AD Ring In Use : Up and Odd : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "Vertical AKC Ring In Use : Down and Even",
"Counter": "0,1,2,3",
"EventCode": "0xB4",
"EventName": "UNC_M3UPI_VERT_RING_AKC_IN_USE.DN_EVEN",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Vertical AKC Ring In Use : Down and Even : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x4",
"Unit": "M3UPI"
},
{
"BriefDescription": "Vertical AKC Ring In Use : Down and Odd",
"Counter": "0,1,2,3",
"EventCode": "0xB4",
"EventName": "UNC_M3UPI_VERT_RING_AKC_IN_USE.DN_ODD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Vertical AKC Ring In Use : Down and Odd : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x8",
"Unit": "M3UPI"
},
{
"BriefDescription": "Vertical AKC Ring In Use : Up and Even",
"Counter": "0,1,2,3",
"EventCode": "0xB4",
"EventName": "UNC_M3UPI_VERT_RING_AKC_IN_USE.UP_EVEN",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Vertical AKC Ring In Use : Up and Even : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "Vertical AKC Ring In Use : Up and Odd",
"Counter": "0,1,2,3",
"EventCode": "0xB4",
"EventName": "UNC_M3UPI_VERT_RING_AKC_IN_USE.UP_ODD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Vertical AKC Ring In Use : Up and Odd : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "Vertical AK Ring In Use : Down and Even",
"Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UNC_M3UPI_VERT_RING_AK_IN_USE.DN_EVEN",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Vertical AK Ring In Use : Down and Even : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x4",
"Unit": "M3UPI"
},
{
"BriefDescription": "Vertical AK Ring In Use : Down and Odd",
"Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UNC_M3UPI_VERT_RING_AK_IN_USE.DN_ODD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Vertical AK Ring In Use : Down and Odd : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x8",
"Unit": "M3UPI"
},
{
"BriefDescription": "Vertical AK Ring In Use : Up and Even",
"Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UNC_M3UPI_VERT_RING_AK_IN_USE.UP_EVEN",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Vertical AK Ring In Use : Up and Even : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "Vertical AK Ring In Use : Up and Odd",
"Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UNC_M3UPI_VERT_RING_AK_IN_USE.UP_ODD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Vertical AK Ring In Use : Up and Odd : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "Vertical BL Ring in Use : Down and Even",
"Counter": "0,1,2,3",
"EventCode": "0xB2",
"EventName": "UNC_M3UPI_VERT_RING_BL_IN_USE.DN_EVEN",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Vertical BL Ring in Use : Down and Even : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x4",
"Unit": "M3UPI"
},
{
"BriefDescription": "Vertical BL Ring in Use : Down and Odd",
"Counter": "0,1,2,3",
"EventCode": "0xB2",
"EventName": "UNC_M3UPI_VERT_RING_BL_IN_USE.DN_ODD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Vertical BL Ring in Use : Down and Odd : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x8",
"Unit": "M3UPI"
},
{
"BriefDescription": "Vertical BL Ring in Use : Up and Even",
"Counter": "0,1,2,3",
"EventCode": "0xB2",
"EventName": "UNC_M3UPI_VERT_RING_BL_IN_USE.UP_EVEN",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Vertical BL Ring in Use : Up and Even : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "Vertical BL Ring in Use : Up and Odd",
"Counter": "0,1,2,3",
"EventCode": "0xB2",
"EventName": "UNC_M3UPI_VERT_RING_BL_IN_USE.UP_ODD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Vertical BL Ring in Use : Up and Odd : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "Vertical IV Ring in Use : Down",
"Counter": "0,1,2,3",
"EventCode": "0xB3",
"EventName": "UNC_M3UPI_VERT_RING_IV_IN_USE.DN",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Vertical IV Ring in Use : Down : Counts the number of cycles that the Vertical IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.",
"UMask": "0x4",
"Unit": "M3UPI"
},
{
"BriefDescription": "Vertical IV Ring in Use : Up",
"Counter": "0,1,2,3",
"EventCode": "0xB3",
"EventName": "UNC_M3UPI_VERT_RING_IV_IN_USE.UP",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Vertical IV Ring in Use : Up : Counts the number of cycles that the Vertical IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.",
"UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "Vertical TGC Ring In Use : Down and Even",
"Counter": "0,1,2,3",
"EventCode": "0xB5",
"EventName": "UNC_M3UPI_VERT_RING_TGC_IN_USE.DN_EVEN",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Vertical TGC Ring In Use : Down and Even : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x4",
"Unit": "M3UPI"
},
{
"BriefDescription": "Vertical TGC Ring In Use : Down and Odd",
"Counter": "0,1,2,3",
"EventCode": "0xB5",
"EventName": "UNC_M3UPI_VERT_RING_TGC_IN_USE.DN_ODD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Vertical TGC Ring In Use : Down and Odd : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x8",
"Unit": "M3UPI"
},
{
"BriefDescription": "Vertical TGC Ring In Use : Up and Even",
"Counter": "0,1,2,3",
"EventCode": "0xB5",
"EventName": "UNC_M3UPI_VERT_RING_TGC_IN_USE.UP_EVEN",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Vertical TGC Ring In Use : Up and Even : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "Vertical TGC Ring In Use : Up and Odd",
"Counter": "0,1,2,3",
"EventCode": "0xB5",
"EventName": "UNC_M3UPI_VERT_RING_TGC_IN_USE.UP_ODD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Vertical TGC Ring In Use : Up and Odd : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "VN0 Credit Used : WB on BL",
"Counter": "0,1,2,3",
"EventCode": "0x5B",
"EventName": "UNC_M3UPI_VN0_CREDITS_USED.NCB",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN0 Credit Used : WB on BL : Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across UPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers. : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
"UMask": "0x10",
"Unit": "M3UPI"
},
{
"BriefDescription": "VN0 Credit Used : NCB on BL",
"Counter": "0,1,2,3",
"EventCode": "0x5B",
"EventName": "UNC_M3UPI_VN0_CREDITS_USED.NCS",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN0 Credit Used : NCB on BL : Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across UPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers. : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.",
"UMask": "0x20",
"Unit": "M3UPI"
},
{
"BriefDescription": "VN0 Credit Used : REQ on AD",
"Counter": "0,1,2,3",
"EventCode": "0x5B",
"EventName": "UNC_M3UPI_VN0_CREDITS_USED.REQ",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN0 Credit Used : REQ on AD : Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across UPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers. : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.",
"UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "VN0 Credit Used : RSP on AD",
"Counter": "0,1,2,3",
"EventCode": "0x5B",
"EventName": "UNC_M3UPI_VN0_CREDITS_USED.RSP",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN0 Credit Used : RSP on AD : Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across UPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers. : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
"UMask": "0x4",
"Unit": "M3UPI"
},
{
"BriefDescription": "VN0 Credit Used : SNP on AD",
"Counter": "0,1,2,3",
"EventCode": "0x5B",
"EventName": "UNC_M3UPI_VN0_CREDITS_USED.SNP",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN0 Credit Used : SNP on AD : Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across UPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers. : Snoops (SNP) messages on AD. SNP is used for outgoing snoops.",
"UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "VN0 Credit Used : RSP on BL",
"Counter": "0,1,2,3",
"EventCode": "0x5B",
"EventName": "UNC_M3UPI_VN0_CREDITS_USED.WB",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN0 Credit Used : RSP on BL : Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across UPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers. : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
"UMask": "0x8",
"Unit": "M3UPI"
},
{
"BriefDescription": "VN0 No Credits : WB on BL",
"Counter": "0,1,2,3",
"EventCode": "0x5D",
"EventName": "UNC_M3UPI_VN0_NO_CREDITS.NCB",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN0 No Credits : WB on BL : Number of Cycles there were no VN0 Credits : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
"UMask": "0x10",
"Unit": "M3UPI"
},
{
"BriefDescription": "VN0 No Credits : NCB on BL",
"Counter": "0,1,2,3",
"EventCode": "0x5D",
"EventName": "UNC_M3UPI_VN0_NO_CREDITS.NCS",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN0 No Credits : NCB on BL : Number of Cycles there were no VN0 Credits : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.",
"UMask": "0x20",
"Unit": "M3UPI"
},
{
"BriefDescription": "VN0 No Credits : REQ on AD",
"Counter": "0,1,2,3",
"EventCode": "0x5D",
"EventName": "UNC_M3UPI_VN0_NO_CREDITS.REQ",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN0 No Credits : REQ on AD : Number of Cycles there were no VN0 Credits : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.",
"UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "VN0 No Credits : RSP on AD",
"Counter": "0,1,2,3",
"EventCode": "0x5D",
"EventName": "UNC_M3UPI_VN0_NO_CREDITS.RSP",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN0 No Credits : RSP on AD : Number of Cycles there were no VN0 Credits : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
"UMask": "0x4",
"Unit": "M3UPI"
},
{
"BriefDescription": "VN0 No Credits : SNP on AD",
"Counter": "0,1,2,3",
"EventCode": "0x5D",
"EventName": "UNC_M3UPI_VN0_NO_CREDITS.SNP",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN0 No Credits : SNP on AD : Number of Cycles there were no VN0 Credits : Snoops (SNP) messages on AD. SNP is used for outgoing snoops.",
"UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "VN0 No Credits : RSP on BL",
"Counter": "0,1,2,3",
"EventCode": "0x5D",
"EventName": "UNC_M3UPI_VN0_NO_CREDITS.WB",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN0 No Credits : RSP on BL : Number of Cycles there were no VN0 Credits : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
"UMask": "0x8",
"Unit": "M3UPI"
},
{
"BriefDescription": "VN1 Credit Used : WB on BL",
"Counter": "0,1,2,3",
"EventCode": "0x5C",
"EventName": "UNC_M3UPI_VN1_CREDITS_USED.NCB",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN1 Credit Used : WB on BL : Number of times a VN1 credit was used on the WB message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers. : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
"UMask": "0x10",
"Unit": "M3UPI"
},
{
"BriefDescription": "VN1 Credit Used : NCB on BL",
"Counter": "0,1,2,3",
"EventCode": "0x5C",
"EventName": "UNC_M3UPI_VN1_CREDITS_USED.NCS",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN1 Credit Used : NCB on BL : Number of times a VN1 credit was used on the WB message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers. : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.",
"UMask": "0x20",
"Unit": "M3UPI"
},
{
"BriefDescription": "VN1 Credit Used : REQ on AD",
"Counter": "0,1,2,3",
"EventCode": "0x5C",
"EventName": "UNC_M3UPI_VN1_CREDITS_USED.REQ",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN1 Credit Used : REQ on AD : Number of times a VN1 credit was used on the WB message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers. : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.",
"UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "VN1 Credit Used : RSP on AD",
"Counter": "0,1,2,3",
"EventCode": "0x5C",
"EventName": "UNC_M3UPI_VN1_CREDITS_USED.RSP",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN1 Credit Used : RSP on AD : Number of times a VN1 credit was used on the WB message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers. : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
"UMask": "0x4",
"Unit": "M3UPI"
},
{
"BriefDescription": "VN1 Credit Used : SNP on AD",
"Counter": "0,1,2,3",
"EventCode": "0x5C",
"EventName": "UNC_M3UPI_VN1_CREDITS_USED.SNP",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN1 Credit Used : SNP on AD : Number of times a VN1 credit was used on the WB message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers. : Snoops (SNP) messages on AD. SNP is used for outgoing snoops.",
"UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "VN1 Credit Used : RSP on BL",
"Counter": "0,1,2,3",
"EventCode": "0x5C",
"EventName": "UNC_M3UPI_VN1_CREDITS_USED.WB",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN1 Credit Used : RSP on BL : Number of times a VN1 credit was used on the WB message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers. : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
"UMask": "0x8",
"Unit": "M3UPI"
},
{
"BriefDescription": "VN1 No Credits : WB on BL",
"Counter": "0,1,2,3",
"EventCode": "0x5E",
"EventName": "UNC_M3UPI_VN1_NO_CREDITS.NCB",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN1 No Credits : WB on BL : Number of Cycles there were no VN1 Credits : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
"UMask": "0x10",
"Unit": "M3UPI"
},
{
"BriefDescription": "VN1 No Credits : NCB on BL",
"Counter": "0,1,2,3",
"EventCode": "0x5E",
"EventName": "UNC_M3UPI_VN1_NO_CREDITS.NCS",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN1 No Credits : NCB on BL : Number of Cycles there were no VN1 Credits : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.",
"UMask": "0x20",
"Unit": "M3UPI"
},
{
"BriefDescription": "VN1 No Credits : REQ on AD",
"Counter": "0,1,2,3",
"EventCode": "0x5E",
"EventName": "UNC_M3UPI_VN1_NO_CREDITS.REQ",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN1 No Credits : REQ on AD : Number of Cycles there were no VN1 Credits : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.",
"UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "VN1 No Credits : RSP on AD",
"Counter": "0,1,2,3",
"EventCode": "0x5E",
"EventName": "UNC_M3UPI_VN1_NO_CREDITS.RSP",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN1 No Credits : RSP on AD : Number of Cycles there were no VN1 Credits : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
"UMask": "0x4",
"Unit": "M3UPI"
},
{
"BriefDescription": "VN1 No Credits : SNP on AD",
"Counter": "0,1,2,3",
"EventCode": "0x5E",
"EventName": "UNC_M3UPI_VN1_NO_CREDITS.SNP",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN1 No Credits : SNP on AD : Number of Cycles there were no VN1 Credits : Snoops (SNP) messages on AD. SNP is used for outgoing snoops.",
"UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "VN1 No Credits : RSP on BL",
"Counter": "0,1,2,3",
"EventCode": "0x5E",
"EventName": "UNC_M3UPI_VN1_NO_CREDITS.WB",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN1 No Credits : RSP on BL : Number of Cycles there were no VN1 Credits : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
"UMask": "0x8",
"Unit": "M3UPI"
},
{
"BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_EQ_LOCALDEST_VN0",
"Counter": "0,1,2,3",
"EventCode": "0x7E",
"EventName": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_EQ_LOCALDEST_VN0",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x82",
"Unit": "M3UPI"
},
{
"BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_EQ_LOCALDEST_VN1",
"Counter": "0,1,2,3",
"EventCode": "0x7E",
"EventName": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_EQ_LOCALDEST_VN1",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0xa0",
"Unit": "M3UPI"
},
{
"BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_GT_LOCALDEST_VN0",
"Counter": "0,1,2,3",
"EventCode": "0x7E",
"EventName": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_GT_LOCALDEST_VN0",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x81",
"Unit": "M3UPI"
},
{
"BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_GT_LOCALDEST_VN1",
"Counter": "0,1,2,3",
"EventCode": "0x7E",
"EventName": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_GT_LOCALDEST_VN1",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x90",
"Unit": "M3UPI"
},
{
"BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_LT_LOCALDEST_VN0",
"Counter": "0,1,2,3",
"EventCode": "0x7E",
"EventName": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_LT_LOCALDEST_VN0",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x84",
"Unit": "M3UPI"
},
{
"BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_LT_LOCALDEST_VN1",
"Counter": "0,1,2,3",
"EventCode": "0x7E",
"EventName": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_LT_LOCALDEST_VN1",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0xc0",
"Unit": "M3UPI"
},
{
"BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.RT_EQ_LOCALDEST_VN0",
"Counter": "0,1,2,3",
"EventCode": "0x7E",
"EventName": "UNC_M3UPI_WB_OCC_COMPARE.RT_EQ_LOCALDEST_VN0",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.RT_EQ_LOCALDEST_VN1",
"Counter": "0,1,2,3",
"EventCode": "0x7E",
"EventName": "UNC_M3UPI_WB_OCC_COMPARE.RT_EQ_LOCALDEST_VN1",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "M3UPI"
},
{
"BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.RT_GT_LOCALDEST_VN0",
"Counter": "0,1,2,3",
"EventCode": "0x7E",
"EventName": "UNC_M3UPI_WB_OCC_COMPARE.RT_GT_LOCALDEST_VN0",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.RT_GT_LOCALDEST_VN1",
"Counter": "0,1,2,3",
"EventCode": "0x7E",
"EventName": "UNC_M3UPI_WB_OCC_COMPARE.RT_GT_LOCALDEST_VN1",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "M3UPI"
},
{
"BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.RT_LT_LOCALDEST_VN0",
"Counter": "0,1,2,3",
"EventCode": "0x7E",
"EventName": "UNC_M3UPI_WB_OCC_COMPARE.RT_LT_LOCALDEST_VN0",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "M3UPI"
},
{
"BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.RT_LT_LOCALDEST_VN1",
"Counter": "0,1,2,3",
"EventCode": "0x7E",
"EventName": "UNC_M3UPI_WB_OCC_COMPARE.RT_LT_LOCALDEST_VN1",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x40",
"Unit": "M3UPI"
},
{
"BriefDescription": "UNC_M3UPI_WB_PENDING.LOCALDEST_VN0",
"Counter": "0,1,2,3",
"EventCode": "0x7D",
"EventName": "UNC_M3UPI_WB_PENDING.LOCALDEST_VN0",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "UNC_M3UPI_WB_PENDING.LOCALDEST_VN1",
"Counter": "0,1,2,3",
"EventCode": "0x7D",
"EventName": "UNC_M3UPI_WB_PENDING.LOCALDEST_VN1",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "M3UPI"
},
{
"BriefDescription": "UNC_M3UPI_WB_PENDING.LOCAL_AND_RT_VN0",
"Counter": "0,1,2,3",
"EventCode": "0x7D",
"EventName": "UNC_M3UPI_WB_PENDING.LOCAL_AND_RT_VN0",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "M3UPI"
},
{
"BriefDescription": "UNC_M3UPI_WB_PENDING.LOCAL_AND_RT_VN1",
"Counter": "0,1,2,3",
"EventCode": "0x7D",
"EventName": "UNC_M3UPI_WB_PENDING.LOCAL_AND_RT_VN1",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x40",
"Unit": "M3UPI"
},
{
"BriefDescription": "UNC_M3UPI_WB_PENDING.ROUTETHRU_VN0",
"Counter": "0,1,2,3",
"EventCode": "0x7D",
"EventName": "UNC_M3UPI_WB_PENDING.ROUTETHRU_VN0",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "UNC_M3UPI_WB_PENDING.ROUTETHRU_VN1",
"Counter": "0,1,2,3",
"EventCode": "0x7D",
"EventName": "UNC_M3UPI_WB_PENDING.ROUTETHRU_VN1",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "M3UPI"
},
{
"BriefDescription": "UNC_M3UPI_WB_PENDING.WAITING4PULL_VN0",
"Counter": "0,1,2,3",
"EventCode": "0x7D",
"EventName": "UNC_M3UPI_WB_PENDING.WAITING4PULL_VN0",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "M3UPI"
},
{
"BriefDescription": "UNC_M3UPI_WB_PENDING.WAITING4PULL_VN1",
"Counter": "0,1,2,3",
"EventCode": "0x7D",
"EventName": "UNC_M3UPI_WB_PENDING.WAITING4PULL_VN1",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x80",
"Unit": "M3UPI"
},
{
"BriefDescription": "UNC_M3UPI_XPT_PFTCH.ARB",
"Counter": "0,1,2,3",
"EventCode": "0x61",
"EventName": "UNC_M3UPI_XPT_PFTCH.ARB",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": ": xpt prefetch message is making arbitration request",
"UMask": "0x4",
"Unit": "M3UPI"
},
{
"BriefDescription": "UNC_M3UPI_XPT_PFTCH.ARRIVED",
"Counter": "0,1,2,3",
"EventCode": "0x61",
"EventName": "UNC_M3UPI_XPT_PFTCH.ARRIVED",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": ": xpt prefetch message arrived in ingress pipeline",
"UMask": "0x1",
"Unit": "M3UPI"
},
{
"BriefDescription": "UNC_M3UPI_XPT_PFTCH.BYPASS",
"Counter": "0,1,2,3",
"EventCode": "0x61",
"EventName": "UNC_M3UPI_XPT_PFTCH.BYPASS",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": ": xpt prefetch message took bypass path",
"UMask": "0x2",
"Unit": "M3UPI"
},
{
"BriefDescription": "UNC_M3UPI_XPT_PFTCH.FLITTED",
"Counter": "0,1,2,3",
"EventCode": "0x61",
"EventName": "UNC_M3UPI_XPT_PFTCH.FLITTED",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": ": xpt prefetch message was slotted into flit (non bypass)",
"UMask": "0x10",
"Unit": "M3UPI"
},
{
"BriefDescription": "UNC_M3UPI_XPT_PFTCH.LOST_ARB",
"Counter": "0,1,2,3",
"EventCode": "0x61",
"EventName": "UNC_M3UPI_XPT_PFTCH.LOST_ARB",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": ": xpt prefetch message lost arbitration",
"UMask": "0x8",
"Unit": "M3UPI"
},
{
"BriefDescription": "UNC_M3UPI_XPT_PFTCH.LOST_OLD",
"Counter": "0,1,2,3",
"EventCode": "0x61",
"EventName": "UNC_M3UPI_XPT_PFTCH.LOST_OLD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": ": xpt prefetch message was dropped because it became too old",
"UMask": "0x20",
"Unit": "M3UPI"
},
{
"BriefDescription": "UNC_M3UPI_XPT_PFTCH.LOST_QFULL",
"Counter": "0,1,2,3",
"EventCode": "0x61",
"EventName": "UNC_M3UPI_XPT_PFTCH.LOST_QFULL",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": ": xpt prefetch message was dropped because it was overwritten by new message while prefetch queue was full",
"UMask": "0x20",
"Unit": "M3UPI"
},
{
"BriefDescription": "Number of kfclks",
"Counter": "0,1,2,3",
"EventCode": "0x01",
"EventName": "UNC_UPI_CLOCKTICKS",
"PerPkg": "1",
"PublicDescription": "Number of kfclks : Counts the number of clocks in the UPI LL. This clock runs at 1/8th the GT/s speed of the UPI link. For example, a 8GT/s link will have qfclk or 1GHz. Current products do not support dynamic link speeds, so this frequency is fixed.",
"Unit": "UPI"
},
{
"BriefDescription": "Direct packet attempts : D2C",
"Counter": "0,1,2,3",
"EventCode": "0x12",
"EventName": "UNC_UPI_DIRECT_ATTEMPTS.D2C",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Direct packet attempts : D2C : Counts the number of DRS packets that we attempted to do direct2core/direct2UPI on. There are 4 mutually exclusive filters. Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases. Note that this does not count packets that are not candidates for Direct2Core. The only candidates for Direct2Core are DRS packets destined for Cbos.",
"UMask": "0x1",
"Unit": "UPI"
},
{
"BriefDescription": "Direct packet attempts : D2K",
"Counter": "0,1,2,3",
"EventCode": "0x12",
"EventName": "UNC_UPI_DIRECT_ATTEMPTS.D2K",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Direct packet attempts : D2K : Counts the number of DRS packets that we attempted to do direct2core/direct2UPI on. There are 4 mutually exclusive filters. Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases. Note that this does not count packets that are not candidates for Direct2Core. The only candidates for Direct2Core are DRS packets destined for Cbos.",
"UMask": "0x2",
"Unit": "UPI"
},
{
"BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ0",
"Counter": "0,1,2,3",
"EventCode": "0x18",
"EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ0",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "UPI"
},
{
"BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ1",
"Counter": "0,1,2,3",
"EventCode": "0x18",
"EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ1",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "UPI"
},
{
"BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ2",
"Counter": "0,1,2,3",
"EventCode": "0x18",
"EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ2",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "UPI"
},
{
"BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ0",
"Counter": "0,1,2,3",
"EventCode": "0x18",
"EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ0",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "UPI"
},
{
"BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ1",
"Counter": "0,1,2,3",
"EventCode": "0x18",
"EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ1",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "UPI"
},
{
"BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ2",
"Counter": "0,1,2,3",
"EventCode": "0x18",
"EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ2",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x40",
"Unit": "UPI"
},
{
"BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ3",
"Counter": "0,1,2,3",
"EventCode": "0x18",
"EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ3",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x80",
"Unit": "UPI"
},
{
"BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.BL_VNA_EQ0",
"Counter": "0,1,2,3",
"EventCode": "0x18",
"EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.BL_VNA_EQ0",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "UPI"
},
{
"BriefDescription": "Cycles in L1",
"Counter": "0,1,2,3",
"EventCode": "0x21",
"EventName": "UNC_UPI_L1_POWER_CYCLES",
"PerPkg": "1",
"PublicDescription": "Cycles in L1 : Number of UPI qfclk cycles spent in L1 power mode. L1 is a mode that totally shuts down a UPI link. Use edge detect to count the number of instances when the UPI link entered L1. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another. Because L1 totally shuts down the link, it takes a good amount of time to exit this mode.",
"Unit": "UPI"
},
{
"BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.BGF_CRD",
"Counter": "0,1,2,3",
"EventCode": "0x14",
"EventName": "UNC_UPI_M3_BYP_BLOCKED.BGF_CRD",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "UPI"
},
{
"BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_AD_VNA_LE2",
"Counter": "0,1,2,3",
"EventCode": "0x14",
"EventName": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_AD_VNA_LE2",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "UPI"
},
{
"BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_AK_VNA_LE3",
"Counter": "0,1,2,3",
"EventCode": "0x14",
"EventName": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_AK_VNA_LE3",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "UPI"
},
{
"BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_BL_VNA_EQ0",
"Counter": "0,1,2,3",
"EventCode": "0x14",
"EventName": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_BL_VNA_EQ0",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "UPI"
},
{
"BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.GV_BLOCK",
"Counter": "0,1,2,3",
"EventCode": "0x14",
"EventName": "UNC_UPI_M3_BYP_BLOCKED.GV_BLOCK",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "UPI"
},
{
"BriefDescription": "UNC_UPI_M3_CRD_RETURN_BLOCKED",
"Counter": "0,1,2,3",
"EventCode": "0x16",
"EventName": "UNC_UPI_M3_CRD_RETURN_BLOCKED",
"Experimental": "1",
"PerPkg": "1",
"Unit": "UPI"
},
{
"BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.BGF_CRD",
"Counter": "0,1,2,3",
"EventCode": "0x15",
"EventName": "UNC_UPI_M3_RXQ_BLOCKED.BGF_CRD",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "UPI"
},
{
"BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AD_VNA_BTW_2_THRESH",
"Counter": "0,1,2,3",
"EventCode": "0x15",
"EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AD_VNA_BTW_2_THRESH",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "UPI"
},
{
"BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AD_VNA_LE2",
"Counter": "0,1,2,3",
"EventCode": "0x15",
"EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AD_VNA_LE2",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "UPI"
},
{
"BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AK_VNA_LE3",
"Counter": "0,1,2,3",
"EventCode": "0x15",
"EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AK_VNA_LE3",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "UPI"
},
{
"BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_BL_VNA_BTW_0_THRESH",
"Counter": "0,1,2,3",
"EventCode": "0x15",
"EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_BL_VNA_BTW_0_THRESH",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "UPI"
},
{
"BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_BL_VNA_EQ0",
"Counter": "0,1,2,3",
"EventCode": "0x15",
"EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_BL_VNA_EQ0",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "UPI"
},
{
"BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.GV_BLOCK",
"Counter": "0,1,2,3",
"EventCode": "0x15",
"EventName": "UNC_UPI_M3_RXQ_BLOCKED.GV_BLOCK",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x40",
"Unit": "UPI"
},
{
"BriefDescription": "Cycles where phy is not in L0, L0c, L0p, L1",
"Counter": "0,1,2,3",
"EventCode": "0x20",
"EventName": "UNC_UPI_PHY_INIT_CYCLES",
"Experimental": "1",
"PerPkg": "1",
"Unit": "UPI"
},
{
"BriefDescription": "L1 Req Nack",
"Counter": "0,1,2,3",
"EventCode": "0x23",
"EventName": "UNC_UPI_POWER_L1_NACK",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "L1 Req Nack : Counts the number of times a link sends/receives a LinkReqNAck. When the UPI links would like to change power state, the Tx side initiates a request to the Rx side requesting to change states. This requests can either be accepted or denied. If the Rx side replies with an Ack, the power mode will change. If it replies with NAck, no change will take place. This can be filtered based on Rx and Tx. An Rx LinkReqNAck refers to receiving an NAck (meaning this agent's Tx originally requested the power change). A Tx LinkReqNAck refers to sending this command (meaning the peer agent's Tx originally requested the power change and this agent accepted it).",
"Unit": "UPI"
},
{
"BriefDescription": "L1 Req (same as L1 Ack).",
"Counter": "0,1,2,3",
"EventCode": "0x22",
"EventName": "UNC_UPI_POWER_L1_REQ",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "L1 Req (same as L1 Ack). : Counts the number of times a link sends/receives a LinkReqAck. When the UPI links would like to change power state, the Tx side initiates a request to the Rx side requesting to change states. This requests can either be accepted or denied. If the Rx side replies with an Ack, the power mode will change. If it replies with NAck, no change will take place. This can be filtered based on Rx and Tx. An Rx LinkReqAck refers to receiving an Ack (meaning this agent's Tx originally requested the power change). A Tx LinkReqAck refers to sending this command (meaning the peer agent's Tx originally requested the power change and this agent accepted it).",
"Unit": "UPI"
},
{
"BriefDescription": "UNC_UPI_REQ_SLOT2_FROM_M3.ACK",
"Counter": "0,1,2,3",
"EventCode": "0x46",
"EventName": "UNC_UPI_REQ_SLOT2_FROM_M3.ACK",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "UPI"
},
{
"BriefDescription": "UNC_UPI_REQ_SLOT2_FROM_M3.VN0",
"Counter": "0,1,2,3",
"EventCode": "0x46",
"EventName": "UNC_UPI_REQ_SLOT2_FROM_M3.VN0",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "UPI"
},
{
"BriefDescription": "UNC_UPI_REQ_SLOT2_FROM_M3.VN1",
"Counter": "0,1,2,3",
"EventCode": "0x46",
"EventName": "UNC_UPI_REQ_SLOT2_FROM_M3.VN1",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "UPI"
},
{
"BriefDescription": "UNC_UPI_REQ_SLOT2_FROM_M3.VNA",
"Counter": "0,1,2,3",
"EventCode": "0x46",
"EventName": "UNC_UPI_REQ_SLOT2_FROM_M3.VNA",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "UPI"
},
{
"BriefDescription": "Cycles in L0p",
"Counter": "0,1,2,3",
"EventCode": "0x25",
"EventName": "UNC_UPI_RxL0P_POWER_CYCLES",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles in L0p : Number of UPI qfclk cycles spent in L0p power mode. L0p is a mode where we disable 1/2 of the UPI lanes, decreasing our bandwidth in order to save power. It increases snoop and data transfer latencies and decreases overall bandwidth. This mode can be very useful in NUMA optimized workloads that largely only utilize UPI for snoops and their responses. Use edge detect to count the number of instances when the UPI link entered L0p. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another.",
"Unit": "UPI"
},
{
"BriefDescription": "Cycles in L0",
"Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "UNC_UPI_RxL0_POWER_CYCLES",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles in L0 : Number of UPI qfclk cycles spent in L0 power mode in the Link Layer. L0 is the default mode which provides the highest performance with the most power. Use edge detect to count the number of instances that the link entered L0. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another. The phy layer sometimes leaves L0 for training, which will not be captured by this event.",
"Unit": "UPI"
},
{
"BriefDescription": "Matches on Receive path of a UPI Port : Non-Coherent Bypass",
"Counter": "0,1,2,3",
"EventCode": "0x05",
"EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCB",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Matches on Receive path of a UPI Port : Non-Coherent Bypass : Matches on Receive path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled.",
"UMask": "0xe",
"Unit": "UPI"
},
{
"BriefDescription": "Matches on Receive path of a UPI Port : Non-Coherent Bypass, Match Opcode",
"Counter": "0,1,2,3",
"EventCode": "0x05",
"EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCB_OPC",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Matches on Receive path of a UPI Port : Non-Coherent Bypass, Match Opcode : Matches on Receive path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled.",
"UMask": "0x10e",
"Unit": "UPI"
},
{
"BriefDescription": "Matches on Receive path of a UPI Port : Non-Coherent Standard",
"Counter": "0,1,2,3",
"EventCode": "0x05",
"EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCS",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Matches on Receive path of a UPI Port : Non-Coherent Standard : Matches on Receive path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled.",
"UMask": "0xf",
"Unit": "UPI"
},
{
"BriefDescription": "Matches on Receive path of a UPI Port : Non-Coherent Standard, Match Opcode",
"Counter": "0,1,2,3",
"EventCode": "0x05",
"EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCS_OPC",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Matches on Receive path of a UPI Port : Non-Coherent Standard, Match Opcode : Matches on Receive path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled.",
"UMask": "0x10f",
"Unit": "UPI"
},
{
"BriefDescription": "Matches on Receive path of a UPI Port : Request",
"Counter": "0,1,2,3",
"EventCode": "0x05",
"EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.REQ",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Matches on Receive path of a UPI Port : Request : Matches on Receive path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled.",
"UMask": "0x8",
"Unit": "UPI"
},
{
"BriefDescription": "Matches on Receive path of a UPI Port : Request, Match Opcode",
"Counter": "0,1,2,3",
"EventCode": "0x05",
"EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.REQ_OPC",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Matches on Receive path of a UPI Port : Request, Match Opcode : Matches on Receive path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled.",
"UMask": "0x108",
"Unit": "UPI"
},
{
"BriefDescription": "Matches on Receive path of a UPI Port : Response - Conflict",
"Counter": "0,1,2,3",
"EventCode": "0x05",
"EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSPCNFLT",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Matches on Receive path of a UPI Port : Response - Conflict : Matches on Receive path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled.",
"UMask": "0x1aa",
"Unit": "UPI"
},
{
"BriefDescription": "Matches on Receive path of a UPI Port : Response - Invalid",
"Counter": "0,1,2,3",
"EventCode": "0x05",
"EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSPI",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Matches on Receive path of a UPI Port : Response - Invalid : Matches on Receive path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled.",
"UMask": "0x12a",
"Unit": "UPI"
},
{
"BriefDescription": "Matches on Receive path of a UPI Port : Response - Data",
"Counter": "0,1,2,3",
"EventCode": "0x05",
"EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_DATA",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Matches on Receive path of a UPI Port : Response - Data : Matches on Receive path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled.",
"UMask": "0xc",
"Unit": "UPI"
},
{
"BriefDescription": "Matches on Receive path of a UPI Port : Response - Data, Match Opcode",
"Counter": "0,1,2,3",
"EventCode": "0x05",
"EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_DATA_OPC",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Matches on Receive path of a UPI Port : Response - Data, Match Opcode : Matches on Receive path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled.",
"UMask": "0x10c",
"Unit": "UPI"
},
{
"BriefDescription": "Matches on Receive path of a UPI Port : Response - No Data",
"Counter": "0,1,2,3",
"EventCode": "0x05",
"EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_NODATA",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Matches on Receive path of a UPI Port : Response - No Data : Matches on Receive path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled.",
"UMask": "0xa",
"Unit": "UPI"
},
{
"BriefDescription": "Matches on Receive path of a UPI Port : Response - No Data, Match Opcode",
"Counter": "0,1,2,3",
"EventCode": "0x05",
"EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_NODATA_OPC",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Matches on Receive path of a UPI Port : Response - No Data, Match Opcode : Matches on Receive path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled.",
"UMask": "0x10a",
"Unit": "UPI"
},
{
"BriefDescription": "Matches on Receive path of a UPI Port : Snoop",
"Counter": "0,1,2,3",
"EventCode": "0x05",
"EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.SNP",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Matches on Receive path of a UPI Port : Snoop : Matches on Receive path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled.",
"UMask": "0x9",
"Unit": "UPI"
},
{
"BriefDescription": "Matches on Receive path of a UPI Port : Snoop, Match Opcode",
"Counter": "0,1,2,3",
"EventCode": "0x05",
"EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.SNP_OPC",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Matches on Receive path of a UPI Port : Snoop, Match Opcode : Matches on Receive path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled.",
"UMask": "0x109",
"Unit": "UPI"
},
{
"BriefDescription": "Matches on Receive path of a UPI Port : Writeback",
"Counter": "0,1,2,3",
"EventCode": "0x05",
"EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.WB",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Matches on Receive path of a UPI Port : Writeback : Matches on Receive path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled.",
"UMask": "0xd",
"Unit": "UPI"
},
{
"BriefDescription": "Matches on Receive path of a UPI Port : Writeback, Match Opcode",
"Counter": "0,1,2,3",
"EventCode": "0x05",
"EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.WB_OPC",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Matches on Receive path of a UPI Port : Writeback, Match Opcode : Matches on Receive path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled.",
"UMask": "0x10d",
"Unit": "UPI"
},
{
"BriefDescription": "RxQ Flit Buffer Bypassed : Slot 0",
"Counter": "0,1,2,3",
"EventCode": "0x31",
"EventName": "UNC_UPI_RxL_BYPASSED.SLOT0",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "RxQ Flit Buffer Bypassed : Slot 0 : Counts the number of times that an incoming flit was able to bypass the flit buffer and pass directly across the BGF and into the Egress. This is a latency optimization, and should generally be the common case. If this value is less than the number of flits transferred, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency.",
"UMask": "0x1",
"Unit": "UPI"
},
{
"BriefDescription": "RxQ Flit Buffer Bypassed : Slot 1",
"Counter": "0,1,2,3",
"EventCode": "0x31",
"EventName": "UNC_UPI_RxL_BYPASSED.SLOT1",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "RxQ Flit Buffer Bypassed : Slot 1 : Counts the number of times that an incoming flit was able to bypass the flit buffer and pass directly across the BGF and into the Egress. This is a latency optimization, and should generally be the common case. If this value is less than the number of flits transferred, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency.",
"UMask": "0x2",
"Unit": "UPI"
},
{
"BriefDescription": "RxQ Flit Buffer Bypassed : Slot 2",
"Counter": "0,1,2,3",
"EventCode": "0x31",
"EventName": "UNC_UPI_RxL_BYPASSED.SLOT2",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "RxQ Flit Buffer Bypassed : Slot 2 : Counts the number of times that an incoming flit was able to bypass the flit buffer and pass directly across the BGF and into the Egress. This is a latency optimization, and should generally be the common case. If this value is less than the number of flits transferred, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency.",
"UMask": "0x4",
"Unit": "UPI"
},
{
"BriefDescription": "CRC Errors Detected",
"Counter": "0,1,2,3",
"EventCode": "0x0B",
"EventName": "UNC_UPI_RxL_CRC_ERRORS",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "CRC Errors Detected : Number of CRC errors detected in the UPI Agent. Each UPI flit incorporates 8 bits of CRC for error detection. This counts the number of flits where the CRC was able to detect an error. After an error has been detected, the UPI agent will send a request to the transmitting socket to resend the flit (as well as any flits that came after it).",
"Unit": "UPI"
},
{
"BriefDescription": "LLR Requests Sent",
"Counter": "0,1,2,3",
"EventCode": "0x08",
"EventName": "UNC_UPI_RxL_CRC_LLR_REQ_TRANSMIT",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "LLR Requests Sent : Number of LLR Requests were transmitted. This should generally be <= the number of CRC errors detected. If multiple errors are detected before the Rx side receives a LLC_REQ_ACK from the Tx side, there is no need to send more LLR_REQ_NACKs.",
"Unit": "UPI"
},
{
"BriefDescription": "VN0 Credit Consumed",
"Counter": "0,1,2,3",
"EventCode": "0x39",
"EventName": "UNC_UPI_RxL_CREDITS_CONSUMED_VN0",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN0 Credit Consumed : Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.",
"Unit": "UPI"
},
{
"BriefDescription": "VN1 Credit Consumed",
"Counter": "0,1,2,3",
"EventCode": "0x3A",
"EventName": "UNC_UPI_RxL_CREDITS_CONSUMED_VN1",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VN1 Credit Consumed : Counts the number of times that an RxQ VN1 credit was consumed (i.e. message uses a VN1 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.",
"Unit": "UPI"
},
{
"BriefDescription": "VNA Credit Consumed",
"Counter": "0,1,2,3",
"EventCode": "0x38",
"EventName": "UNC_UPI_RxL_CREDITS_CONSUMED_VNA",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VNA Credit Consumed : Counts the number of times that an RxQ VNA credit was consumed (i.e. message uses a VNA credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.",
"Unit": "UPI"
},
{
"BriefDescription": "Valid Flits Received : All Data",
"Counter": "0,1,2,3",
"EventCode": "0x03",
"EventName": "UNC_UPI_RxL_FLITS.ALL_DATA",
"PerPkg": "1",
"PublicDescription": "Valid Flits Received : All Data : Shows legal flit time (hides impact of L0p and L0c).",
"UMask": "0xf",
"Unit": "UPI"
},
{
"BriefDescription": "Valid Flits Received : Null FLITs received from any slot",
"Counter": "0,1,2,3",
"EventCode": "0x03",
"EventName": "UNC_UPI_RxL_FLITS.ALL_NULL",
"PerPkg": "1",
"PublicDescription": "Valid Flits Received : Null FLITs received from any slot : Shows legal flit time (hides impact of L0p and L0c).",
"UMask": "0x27",
"Unit": "UPI"
},
{
"BriefDescription": "Valid Flits Received : Data",
"Counter": "0,1,2,3",
"EventCode": "0x03",
"EventName": "UNC_UPI_RxL_FLITS.DATA",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Valid Flits Received : Data : Shows legal flit time (hides impact of L0p and L0c). : Count Data Flits (which consume all slots), but how much to count is based on Slot0-2 mask, so count can be 0-3 depending on which slots are enabled for counting..",
"UMask": "0x8",
"Unit": "UPI"
},
{
"BriefDescription": "Valid Flits Received : Null FLITs received from any slot",
"Counter": "0,1,2,3",
"EventCode": "0x03",
"EventName": "UNC_UPI_RxL_FLITS.IDLE",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Valid Flits Received : Null FLITs received from any slot : Shows legal flit time (hides impact of L0p and L0c).",
"UMask": "0x47",
"Unit": "UPI"
},
{
"BriefDescription": "Valid Flits Received : LLCRD Not Empty",
"Counter": "0,1,2,3",
"EventCode": "0x03",
"EventName": "UNC_UPI_RxL_FLITS.LLCRD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Valid Flits Received : LLCRD Not Empty : Shows legal flit time (hides impact of L0p and L0c). : Enables counting of LLCRD (with non-zero payload). This only applies to slot 2 since LLCRD is only allowed in slot 2",
"UMask": "0x10",
"Unit": "UPI"
},
{
"BriefDescription": "Valid Flits Received : LLCTRL",
"Counter": "0,1,2,3",
"EventCode": "0x03",
"EventName": "UNC_UPI_RxL_FLITS.LLCTRL",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Valid Flits Received : LLCTRL : Shows legal flit time (hides impact of L0p and L0c). : Equivalent to an idle packet. Enables counting of slot 0 LLCTRL messages.",
"UMask": "0x40",
"Unit": "UPI"
},
{
"BriefDescription": "Valid Flits Received : All Non Data",
"Counter": "0,1,2,3",
"EventCode": "0x03",
"EventName": "UNC_UPI_RxL_FLITS.NON_DATA",
"PerPkg": "1",
"PublicDescription": "Valid Flits Received : All Non Data : Shows legal flit time (hides impact of L0p and L0c).",
"UMask": "0x97",
"Unit": "UPI"
},
{
"BriefDescription": "Valid Flits Received : Slot NULL or LLCRD Empty",
"Counter": "0,1,2,3",
"EventCode": "0x03",
"EventName": "UNC_UPI_RxL_FLITS.NULL",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Valid Flits Received : Slot NULL or LLCRD Empty : Shows legal flit time (hides impact of L0p and L0c). : LLCRD with all zeros is treated as NULL. Slot 1 is not treated as NULL if slot 0 is a dual slot. This can apply to slot 0,1, or 2.",
"UMask": "0x20",
"Unit": "UPI"
},
{
"BriefDescription": "Valid Flits Received : Protocol Header",
"Counter": "0,1,2,3",
"EventCode": "0x03",
"EventName": "UNC_UPI_RxL_FLITS.PROTHDR",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Valid Flits Received : Protocol Header : Shows legal flit time (hides impact of L0p and L0c). : Enables count of protocol headers in slot 0,1,2 (depending on slot uMask bits)",
"UMask": "0x80",
"Unit": "UPI"
},
{
"BriefDescription": "Valid Flits Received : Slot 0",
"Counter": "0,1,2,3",
"EventCode": "0x03",
"EventName": "UNC_UPI_RxL_FLITS.SLOT0",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Valid Flits Received : Slot 0 : Shows legal flit time (hides impact of L0p and L0c). : Count Slot 0 - Other mask bits determine types of headers to count.",
"UMask": "0x1",
"Unit": "UPI"
},
{
"BriefDescription": "Valid Flits Received : Slot 1",
"Counter": "0,1,2,3",
"EventCode": "0x03",
"EventName": "UNC_UPI_RxL_FLITS.SLOT1",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Valid Flits Received : Slot 1 : Shows legal flit time (hides impact of L0p and L0c). : Count Slot 1 - Other mask bits determine types of headers to count.",
"UMask": "0x2",
"Unit": "UPI"
},
{
"BriefDescription": "Valid Flits Received : Slot 2",
"Counter": "0,1,2,3",
"EventCode": "0x03",
"EventName": "UNC_UPI_RxL_FLITS.SLOT2",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Valid Flits Received : Slot 2 : Shows legal flit time (hides impact of L0p and L0c). : Count Slot 2 - Other mask bits determine types of headers to count.",
"UMask": "0x4",
"Unit": "UPI"
},
{
"BriefDescription": "RxQ Flit Buffer Allocations : Slot 0",
"Counter": "0,1,2,3",
"EventCode": "0x30",
"EventName": "UNC_UPI_RxL_INSERTS.SLOT0",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "RxQ Flit Buffer Allocations : Slot 0 : Number of allocations into the UPI Rx Flit Buffer. Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.",
"UMask": "0x1",
"Unit": "UPI"
},
{
"BriefDescription": "RxQ Flit Buffer Allocations : Slot 1",
"Counter": "0,1,2,3",
"EventCode": "0x30",
"EventName": "UNC_UPI_RxL_INSERTS.SLOT1",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "RxQ Flit Buffer Allocations : Slot 1 : Number of allocations into the UPI Rx Flit Buffer. Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.",
"UMask": "0x2",
"Unit": "UPI"
},
{
"BriefDescription": "RxQ Flit Buffer Allocations : Slot 2",
"Counter": "0,1,2,3",
"EventCode": "0x30",
"EventName": "UNC_UPI_RxL_INSERTS.SLOT2",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "RxQ Flit Buffer Allocations : Slot 2 : Number of allocations into the UPI Rx Flit Buffer. Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.",
"UMask": "0x4",
"Unit": "UPI"
},
{
"BriefDescription": "RxQ Occupancy - All Packets : Slot 0",
"Counter": "0,1,2,3",
"EventCode": "0x32",
"EventName": "UNC_UPI_RxL_OCCUPANCY.SLOT0",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "RxQ Occupancy - All Packets : Slot 0 : Accumulates the number of elements in the UPI RxQ in each cycle. Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.",
"UMask": "0x1",
"Unit": "UPI"
},
{
"BriefDescription": "RxQ Occupancy - All Packets : Slot 1",
"Counter": "0,1,2,3",
"EventCode": "0x32",
"EventName": "UNC_UPI_RxL_OCCUPANCY.SLOT1",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "RxQ Occupancy - All Packets : Slot 1 : Accumulates the number of elements in the UPI RxQ in each cycle. Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.",
"UMask": "0x2",
"Unit": "UPI"
},
{
"BriefDescription": "RxQ Occupancy - All Packets : Slot 2",
"Counter": "0,1,2,3",
"EventCode": "0x32",
"EventName": "UNC_UPI_RxL_OCCUPANCY.SLOT2",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "RxQ Occupancy - All Packets : Slot 2 : Accumulates the number of elements in the UPI RxQ in each cycle. Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.",
"UMask": "0x4",
"Unit": "UPI"
},
{
"BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S0_RXQ1",
"Counter": "0,1,2,3",
"EventCode": "0x33",
"EventName": "UNC_UPI_RxL_SLOT_BYPASS.S0_RXQ1",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "UPI"
},
{
"BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S0_RXQ2",
"Counter": "0,1,2,3",
"EventCode": "0x33",
"EventName": "UNC_UPI_RxL_SLOT_BYPASS.S0_RXQ2",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "UPI"
},
{
"BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S1_RXQ0",
"Counter": "0,1,2,3",
"EventCode": "0x33",
"EventName": "UNC_UPI_RxL_SLOT_BYPASS.S1_RXQ0",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "UPI"
},
{
"BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S1_RXQ2",
"Counter": "0,1,2,3",
"EventCode": "0x33",
"EventName": "UNC_UPI_RxL_SLOT_BYPASS.S1_RXQ2",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "UPI"
},
{
"BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S2_RXQ0",
"Counter": "0,1,2,3",
"EventCode": "0x33",
"EventName": "UNC_UPI_RxL_SLOT_BYPASS.S2_RXQ0",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "UPI"
},
{
"BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S2_RXQ1",
"Counter": "0,1,2,3",
"EventCode": "0x33",
"EventName": "UNC_UPI_RxL_SLOT_BYPASS.S2_RXQ1",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "UPI"
},
{
"BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.CFG_CTL",
"Counter": "0,1,2,3",
"EventCode": "0x2A",
"EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.CFG_CTL",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "UPI"
},
{
"BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.DFX",
"Counter": "0,1,2,3",
"EventCode": "0x2A",
"EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.DFX",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x40",
"Unit": "UPI"
},
{
"BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.RETRY",
"Counter": "0,1,2,3",
"EventCode": "0x2A",
"EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.RETRY",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "UPI"
},
{
"BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ",
"Counter": "0,1,2,3",
"EventCode": "0x2A",
"EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "UPI"
},
{
"BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ_BYPASS",
"Counter": "0,1,2,3",
"EventCode": "0x2A",
"EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ_BYPASS",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "UPI"
},
{
"BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ_CRED",
"Counter": "0,1,2,3",
"EventCode": "0x2A",
"EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ_CRED",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "UPI"
},
{
"BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.SPARE",
"Counter": "0,1,2,3",
"EventCode": "0x2A",
"EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.SPARE",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x80",
"Unit": "UPI"
},
{
"BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.TXQ",
"Counter": "0,1,2,3",
"EventCode": "0x2A",
"EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.TXQ",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "UPI"
},
{
"BriefDescription": "Cycles in L0p",
"Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "UNC_UPI_TxL0P_POWER_CYCLES",
"PerPkg": "1",
"PublicDescription": "Cycles in L0p : Number of UPI qfclk cycles spent in L0p power mode. L0p is a mode where we disable 1/2 of the UPI lanes, decreasing our bandwidth in order to save power. It increases snoop and data transfer latencies and decreases overall bandwidth. This mode can be very useful in NUMA optimized workloads that largely only utilize UPI for snoops and their responses. Use edge detect to count the number of instances when the UPI link entered L0p. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another.",
"Unit": "UPI"
},
{
"BriefDescription": "UNC_UPI_TxL0P_POWER_CYCLES_LL_ENTER",
"Counter": "0,1,2,3",
"EventCode": "0x28",
"EventName": "UNC_UPI_TxL0P_POWER_CYCLES_LL_ENTER",
"Experimental": "1",
"PerPkg": "1",
"Unit": "UPI"
},
{
"BriefDescription": "UNC_UPI_TxL0P_POWER_CYCLES_M3_EXIT",
"Counter": "0,1,2,3",
"EventCode": "0x29",
"EventName": "UNC_UPI_TxL0P_POWER_CYCLES_M3_EXIT",
"Experimental": "1",
"PerPkg": "1",
"Unit": "UPI"
},
{
"BriefDescription": "Cycles in L0",
"Counter": "0,1,2,3",
"EventCode": "0x26",
"EventName": "UNC_UPI_TxL0_POWER_CYCLES",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles in L0 : Number of UPI qfclk cycles spent in L0 power mode in the Link Layer. L0 is the default mode which provides the highest performance with the most power. Use edge detect to count the number of instances that the link entered L0. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another. The phy layer sometimes leaves L0 for training, which will not be captured by this event.",
"Unit": "UPI"
},
{
"BriefDescription": "Matches on Transmit path of a UPI Port : Non-Coherent Bypass",
"Counter": "0,1,2,3",
"EventCode": "0x04",
"EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCB",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Matches on Transmit path of a UPI Port : Non-Coherent Bypass : Matches on Transmit path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled.",
"UMask": "0xe",
"Unit": "UPI"
},
{
"BriefDescription": "Matches on Transmit path of a UPI Port : Non-Coherent Bypass, Match Opcode",
"Counter": "0,1,2,3",
"EventCode": "0x04",
"EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCB_OPC",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Matches on Transmit path of a UPI Port : Non-Coherent Bypass, Match Opcode : Matches on Transmit path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled.",
"UMask": "0x10e",
"Unit": "UPI"
},
{
"BriefDescription": "Matches on Transmit path of a UPI Port : Non-Coherent Standard",
"Counter": "0,1,2,3",
"EventCode": "0x04",
"EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCS",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Matches on Transmit path of a UPI Port : Non-Coherent Standard : Matches on Transmit path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled.",
"UMask": "0xf",
"Unit": "UPI"
},
{
"BriefDescription": "Matches on Transmit path of a UPI Port : Non-Coherent Standard, Match Opcode",
"Counter": "0,1,2,3",
"EventCode": "0x04",
"EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCS_OPC",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Matches on Transmit path of a UPI Port : Non-Coherent Standard, Match Opcode : Matches on Transmit path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled.",
"UMask": "0x10f",
"Unit": "UPI"
},
{
"BriefDescription": "Matches on Transmit path of a UPI Port : Request",
"Counter": "0,1,2,3",
"EventCode": "0x04",
"EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.REQ",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Matches on Transmit path of a UPI Port : Request : Matches on Transmit path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled.",
"UMask": "0x8",
"Unit": "UPI"
},
{
"BriefDescription": "Matches on Transmit path of a UPI Port : Request, Match Opcode",
"Counter": "0,1,2,3",
"EventCode": "0x04",
"EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.REQ_OPC",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Matches on Transmit path of a UPI Port : Request, Match Opcode : Matches on Transmit path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled.",
"UMask": "0x108",
"Unit": "UPI"
},
{
"BriefDescription": "Matches on Transmit path of a UPI Port : Response - Conflict",
"Counter": "0,1,2,3",
"EventCode": "0x04",
"EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSPCNFLT",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Matches on Transmit path of a UPI Port : Response - Conflict : Matches on Transmit path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled.",
"UMask": "0x1aa",
"Unit": "UPI"
},
{
"BriefDescription": "Matches on Transmit path of a UPI Port : Response - Invalid",
"Counter": "0,1,2,3",
"EventCode": "0x04",
"EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSPI",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Matches on Transmit path of a UPI Port : Response - Invalid : Matches on Transmit path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled.",
"UMask": "0x12a",
"Unit": "UPI"
},
{
"BriefDescription": "Matches on Transmit path of a UPI Port : Response - Data",
"Counter": "0,1,2,3",
"EventCode": "0x04",
"EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_DATA",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Matches on Transmit path of a UPI Port : Response - Data : Matches on Transmit path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled.",
"UMask": "0xc",
"Unit": "UPI"
},
{
"BriefDescription": "Matches on Transmit path of a UPI Port : Response - Data, Match Opcode",
"Counter": "0,1,2,3",
"EventCode": "0x04",
"EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_DATA_OPC",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Matches on Transmit path of a UPI Port : Response - Data, Match Opcode : Matches on Transmit path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled.",
"UMask": "0x10c",
"Unit": "UPI"
},
{
"BriefDescription": "Matches on Transmit path of a UPI Port : Response - No Data",
"Counter": "0,1,2,3",
"EventCode": "0x04",
"EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_NODATA",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Matches on Transmit path of a UPI Port : Response - No Data : Matches on Transmit path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled.",
"UMask": "0xa",
"Unit": "UPI"
},
{
"BriefDescription": "Matches on Transmit path of a UPI Port : Response - No Data, Match Opcode",
"Counter": "0,1,2,3",
"EventCode": "0x04",
"EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_NODATA_OPC",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Matches on Transmit path of a UPI Port : Response - No Data, Match Opcode : Matches on Transmit path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled.",
"UMask": "0x10a",
"Unit": "UPI"
},
{
"BriefDescription": "Matches on Transmit path of a UPI Port : Snoop",
"Counter": "0,1,2,3",
"EventCode": "0x04",
"EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.SNP",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Matches on Transmit path of a UPI Port : Snoop : Matches on Transmit path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled.",
"UMask": "0x9",
"Unit": "UPI"
},
{
"BriefDescription": "Matches on Transmit path of a UPI Port : Snoop, Match Opcode",
"Counter": "0,1,2,3",
"EventCode": "0x04",
"EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.SNP_OPC",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Matches on Transmit path of a UPI Port : Snoop, Match Opcode : Matches on Transmit path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled.",
"UMask": "0x109",
"Unit": "UPI"
},
{
"BriefDescription": "Matches on Transmit path of a UPI Port : Writeback",
"Counter": "0,1,2,3",
"EventCode": "0x04",
"EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.WB",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Matches on Transmit path of a UPI Port : Writeback : Matches on Transmit path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled.",
"UMask": "0xd",
"Unit": "UPI"
},
{
"BriefDescription": "Matches on Transmit path of a UPI Port : Writeback, Match Opcode",
"Counter": "0,1,2,3",
"EventCode": "0x04",
"EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.WB_OPC",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Matches on Transmit path of a UPI Port : Writeback, Match Opcode : Matches on Transmit path of a UPI port. Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases. Note: If Message Class is disabled, we expect opcode to also be disabled.",
"UMask": "0x10d",
"Unit": "UPI"
},
{
"BriefDescription": "Tx Flit Buffer Bypassed",
"Counter": "0,1,2,3",
"EventCode": "0x41",
"EventName": "UNC_UPI_TxL_BYPASSED",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Tx Flit Buffer Bypassed : Counts the number of times that an incoming flit was able to bypass the Tx flit buffer and pass directly out the UPI Link. Generally, when data is transmitted across UPI, it will bypass the TxQ and pass directly to the link. However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link.",
"Unit": "UPI"
},
{
"BriefDescription": "Valid Flits Sent : All Data",
"Counter": "0,1,2,3",
"EventCode": "0x02",
"EventName": "UNC_UPI_TxL_FLITS.ALL_DATA",
"PerPkg": "1",
"PublicDescription": "Valid Flits Sent : All Data : Shows legal flit time (hides impact of L0p and L0c).",
"UMask": "0xf",
"Unit": "UPI"
},
{
"BriefDescription": "Valid Flits Sent : Null FLITs transmitted to any slot",
"Counter": "0,1,2,3",
"EventCode": "0x02",
"EventName": "UNC_UPI_TxL_FLITS.ALL_NULL",
"PerPkg": "1",
"PublicDescription": "Valid Flits Sent : Null FLITs transmitted to any slot : Shows legal flit time (hides impact of L0p and L0c).",
"UMask": "0x27",
"Unit": "UPI"
},
{
"BriefDescription": "Valid Flits Sent : Data",
"Counter": "0,1,2,3",
"EventCode": "0x02",
"EventName": "UNC_UPI_TxL_FLITS.DATA",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Valid Flits Sent : Data : Shows legal flit time (hides impact of L0p and L0c). : Count Data Flits (which consume all slots), but how much to count is based on Slot0-2 mask, so count can be 0-3 depending on which slots are enabled for counting..",
"UMask": "0x8",
"Unit": "UPI"
},
{
"BriefDescription": "Valid Flits Sent : Idle",
"Counter": "0,1,2,3",
"EventCode": "0x02",
"EventName": "UNC_UPI_TxL_FLITS.IDLE",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Valid Flits Sent : Idle : Shows legal flit time (hides impact of L0p and L0c).",
"UMask": "0x47",
"Unit": "UPI"
},
{
"BriefDescription": "Valid Flits Sent : LLCRD Not Empty",
"Counter": "0,1,2,3",
"EventCode": "0x02",
"EventName": "UNC_UPI_TxL_FLITS.LLCRD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Valid Flits Sent : LLCRD Not Empty : Shows legal flit time (hides impact of L0p and L0c). : Enables counting of LLCRD (with non-zero payload). This only applies to slot 2 since LLCRD is only allowed in slot 2",
"UMask": "0x10",
"Unit": "UPI"
},
{
"BriefDescription": "Valid Flits Sent : LLCTRL",
"Counter": "0,1,2,3",
"EventCode": "0x02",
"EventName": "UNC_UPI_TxL_FLITS.LLCTRL",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Valid Flits Sent : LLCTRL : Shows legal flit time (hides impact of L0p and L0c). : Equivalent to an idle packet. Enables counting of slot 0 LLCTRL messages.",
"UMask": "0x40",
"Unit": "UPI"
},
{
"BriefDescription": "Valid Flits Sent : All Non Data",
"Counter": "0,1,2,3",
"EventCode": "0x02",
"EventName": "UNC_UPI_TxL_FLITS.NON_DATA",
"PerPkg": "1",
"PublicDescription": "Valid Flits Sent : All Non Data : Shows legal flit time (hides impact of L0p and L0c).",
"UMask": "0x97",
"Unit": "UPI"
},
{
"BriefDescription": "Valid Flits Sent : Slot NULL or LLCRD Empty",
"Counter": "0,1,2,3",
"EventCode": "0x02",
"EventName": "UNC_UPI_TxL_FLITS.NULL",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Valid Flits Sent : Slot NULL or LLCRD Empty : Shows legal flit time (hides impact of L0p and L0c). : LLCRD with all zeros is treated as NULL. Slot 1 is not treated as NULL if slot 0 is a dual slot. This can apply to slot 0,1, or 2.",
"UMask": "0x20",
"Unit": "UPI"
},
{
"BriefDescription": "Valid Flits Sent : Protocol Header",
"Counter": "0,1,2,3",
"EventCode": "0x02",
"EventName": "UNC_UPI_TxL_FLITS.PROTHDR",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Valid Flits Sent : Protocol Header : Shows legal flit time (hides impact of L0p and L0c). : Enables count of protocol headers in slot 0,1,2 (depending on slot uMask bits)",
"UMask": "0x80",
"Unit": "UPI"
},
{
"BriefDescription": "Valid Flits Sent : Slot 0",
"Counter": "0,1,2,3",
"EventCode": "0x02",
"EventName": "UNC_UPI_TxL_FLITS.SLOT0",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Valid Flits Sent : Slot 0 : Shows legal flit time (hides impact of L0p and L0c). : Count Slot 0 - Other mask bits determine types of headers to count.",
"UMask": "0x1",
"Unit": "UPI"
},
{
"BriefDescription": "Valid Flits Sent : Slot 1",
"Counter": "0,1,2,3",
"EventCode": "0x02",
"EventName": "UNC_UPI_TxL_FLITS.SLOT1",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Valid Flits Sent : Slot 1 : Shows legal flit time (hides impact of L0p and L0c). : Count Slot 1 - Other mask bits determine types of headers to count.",
"UMask": "0x2",
"Unit": "UPI"
},
{
"BriefDescription": "Valid Flits Sent : Slot 2",
"Counter": "0,1,2,3",
"EventCode": "0x02",
"EventName": "UNC_UPI_TxL_FLITS.SLOT2",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Valid Flits Sent : Slot 2 : Shows legal flit time (hides impact of L0p and L0c). : Count Slot 2 - Other mask bits determine types of headers to count.",
"UMask": "0x4",
"Unit": "UPI"
},
{
"BriefDescription": "Tx Flit Buffer Allocations",
"Counter": "0,1,2,3",
"EventCode": "0x40",
"EventName": "UNC_UPI_TxL_INSERTS",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Tx Flit Buffer Allocations : Number of allocations into the UPI Tx Flit Buffer. Generally, when data is transmitted across UPI, it will bypass the TxQ and pass directly to the link. However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.",
"Unit": "UPI"
},
{
"BriefDescription": "Tx Flit Buffer Occupancy",
"Counter": "0,1,2,3",
"EventCode": "0x42",
"EventName": "UNC_UPI_TxL_OCCUPANCY",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Tx Flit Buffer Occupancy : Accumulates the number of flits in the TxQ. Generally, when data is transmitted across UPI, it will bypass the TxQ and pass directly to the link. However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link. This can be used with the cycles not empty event to track average occupancy, or the allocations event to track average lifetime in the TxQ.",
"Unit": "UPI"
},
{
"BriefDescription": "UNC_UPI_VNA_CREDIT_RETURN_BLOCKED_VN01",
"Counter": "0,1,2,3",
"EventCode": "0x45",
"EventName": "UNC_UPI_VNA_CREDIT_RETURN_BLOCKED_VN01",
"Experimental": "1",
"PerPkg": "1",
"Unit": "UPI"
},
{
"BriefDescription": "VNA Credits Pending Return - Occupancy",
"Counter": "0,1,2,3",
"EventCode": "0x44",
"EventName": "UNC_UPI_VNA_CREDIT_RETURN_OCCUPANCY",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "VNA Credits Pending Return - Occupancy : Number of VNA credits in the Rx side that are waitng to be returned back across the link.",
"Unit": "UPI"
},
{
"BriefDescription": "Clockticks in the UBOX using a dedicated 48-bit Fixed Counter",
"Counter": "FIXED",
"EventCode": "0xff",
"EventName": "UNC_U_CLOCKTICKS",
"PerPkg": "1",
"Unit": "UBOX"
},
{
"BriefDescription": "Message Received : Doorbell",
"Counter": "0,1",
"EventCode": "0x42",
"EventName": "UNC_U_EVENT_MSG.DOORBELL_RCVD",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "UBOX"
},
{
"BriefDescription": "Message Received : Interrupt",
"Counter": "0,1",
"EventCode": "0x42",
"EventName": "UNC_U_EVENT_MSG.INT_PRIO",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Message Received : Interrupt : Interrupts",
"UMask": "0x10",
"Unit": "UBOX"
},
{
"BriefDescription": "Message Received : IPI",
"Counter": "0,1",
"EventCode": "0x42",
"EventName": "UNC_U_EVENT_MSG.IPI_RCVD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Message Received : IPI : Inter Processor Interrupts",
"UMask": "0x4",
"Unit": "UBOX"
},
{
"BriefDescription": "Message Received : MSI",
"Counter": "0,1",
"EventCode": "0x42",
"EventName": "UNC_U_EVENT_MSG.MSI_RCVD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Message Received : MSI : Message Signaled Interrupts - interrupts sent by devices (including PCIe via IOxAPIC) (Socket Mode only)",
"UMask": "0x2",
"Unit": "UBOX"
},
{
"BriefDescription": "Message Received : VLW",
"Counter": "0,1",
"EventCode": "0x42",
"EventName": "UNC_U_EVENT_MSG.VLW_RCVD",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Message Received : VLW : Virtual Logical Wire (legacy) message were received from Uncore.",
"UMask": "0x1",
"Unit": "UBOX"
},
{
"BriefDescription": "IDI Lock/SplitLock Cycles",
"Counter": "0,1",
"EventCode": "0x44",
"EventName": "UNC_U_LOCK_CYCLES",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "IDI Lock/SplitLock Cycles : Number of times an IDI Lock/SplitLock sequence was started",
"Unit": "UBOX"
},
{
"BriefDescription": "UNC_U_M2U_MISC1.RxC_CYCLES_NE_CBO_NCB",
"Counter": "0,1",
"EventCode": "0x4D",
"EventName": "UNC_U_M2U_MISC1.RxC_CYCLES_NE_CBO_NCB",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "UBOX"
},
{
"BriefDescription": "UNC_U_M2U_MISC1.RxC_CYCLES_NE_CBO_NCS",
"Counter": "0,1",
"EventCode": "0x4D",
"EventName": "UNC_U_M2U_MISC1.RxC_CYCLES_NE_CBO_NCS",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "UBOX"
},
{
"BriefDescription": "UNC_U_M2U_MISC1.RxC_CYCLES_NE_UPI_NCB",
"Counter": "0,1",
"EventCode": "0x4D",
"EventName": "UNC_U_M2U_MISC1.RxC_CYCLES_NE_UPI_NCB",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "UBOX"
},
{
"BriefDescription": "UNC_U_M2U_MISC1.RxC_CYCLES_NE_UPI_NCS",
"Counter": "0,1",
"EventCode": "0x4D",
"EventName": "UNC_U_M2U_MISC1.RxC_CYCLES_NE_UPI_NCS",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "UBOX"
},
{
"BriefDescription": "UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_CBO_NCB",
"Counter": "0,1",
"EventCode": "0x4D",
"EventName": "UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_CBO_NCB",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "UBOX"
},
{
"BriefDescription": "UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_CBO_NCS",
"Counter": "0,1",
"EventCode": "0x4D",
"EventName": "UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_CBO_NCS",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "UBOX"
},
{
"BriefDescription": "UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_UPI_NCB",
"Counter": "0,1",
"EventCode": "0x4D",
"EventName": "UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_UPI_NCB",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x40",
"Unit": "UBOX"
},
{
"BriefDescription": "UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_UPI_NCS",
"Counter": "0,1",
"EventCode": "0x4D",
"EventName": "UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_UPI_NCS",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x80",
"Unit": "UBOX"
},
{
"BriefDescription": "UNC_U_M2U_MISC2.RxC_CYCLES_EMPTY_BL",
"Counter": "0,1",
"EventCode": "0x4E",
"EventName": "UNC_U_M2U_MISC2.RxC_CYCLES_EMPTY_BL",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "UBOX"
},
{
"BriefDescription": "UNC_U_M2U_MISC2.RxC_CYCLES_FULL_BL",
"Counter": "0,1",
"EventCode": "0x4E",
"EventName": "UNC_U_M2U_MISC2.RxC_CYCLES_FULL_BL",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "UBOX"
},
{
"BriefDescription": "UNC_U_M2U_MISC2.TxC_CYCLES_CRD_OVF_VN0_NCB",
"Counter": "0,1",
"EventCode": "0x4E",
"EventName": "UNC_U_M2U_MISC2.TxC_CYCLES_CRD_OVF_VN0_NCB",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "UBOX"
},
{
"BriefDescription": "UNC_U_M2U_MISC2.TxC_CYCLES_CRD_OVF_VN0_NCS",
"Counter": "0,1",
"EventCode": "0x4E",
"EventName": "UNC_U_M2U_MISC2.TxC_CYCLES_CRD_OVF_VN0_NCS",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "UBOX"
},
{
"BriefDescription": "UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_AK",
"Counter": "0,1",
"EventCode": "0x4E",
"EventName": "UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_AK",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "UBOX"
},
{
"BriefDescription": "UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_AKC",
"Counter": "0,1",
"EventCode": "0x4E",
"EventName": "UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_AKC",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x40",
"Unit": "UBOX"
},
{
"BriefDescription": "UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_BL",
"Counter": "0,1",
"EventCode": "0x4E",
"EventName": "UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_BL",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "UBOX"
},
{
"BriefDescription": "UNC_U_M2U_MISC2.TxC_CYCLES_FULL_BL",
"Counter": "0,1",
"EventCode": "0x4E",
"EventName": "UNC_U_M2U_MISC2.TxC_CYCLES_FULL_BL",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x80",
"Unit": "UBOX"
},
{
"BriefDescription": "UNC_U_M2U_MISC3.TxC_CYCLES_FULL_AK",
"Counter": "0,1",
"EventCode": "0x4F",
"EventName": "UNC_U_M2U_MISC3.TxC_CYCLES_FULL_AK",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "UBOX"
},
{
"BriefDescription": "UNC_U_M2U_MISC3.TxC_CYCLES_FULL_AKC",
"Counter": "0,1",
"EventCode": "0x4F",
"EventName": "UNC_U_M2U_MISC3.TxC_CYCLES_FULL_AKC",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "UBOX"
},
{
"BriefDescription": "Cycles PHOLD Assert to Ack : Assert to ACK",
"Counter": "0,1",
"EventCode": "0x45",
"EventName": "UNC_U_PHOLD_CYCLES.ASSERT_TO_ACK",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "Cycles PHOLD Assert to Ack : Assert to ACK : PHOLD cycles.",
"UMask": "0x1",
"Unit": "UBOX"
},
{
"BriefDescription": "UNC_U_RACU_DRNG.PFTCH_BUF_EMPTY",
"Counter": "0,1",
"EventCode": "0x4C",
"EventName": "UNC_U_RACU_DRNG.PFTCH_BUF_EMPTY",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "UBOX"
},
{
"BriefDescription": "UNC_U_RACU_DRNG.RDRAND",
"Counter": "0,1",
"EventCode": "0x4C",
"EventName": "UNC_U_RACU_DRNG.RDRAND",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "UBOX"
},
{
"BriefDescription": "UNC_U_RACU_DRNG.RDSEED",
"Counter": "0,1",
"EventCode": "0x4C",
"EventName": "UNC_U_RACU_DRNG.RDSEED",
"Experimental": "1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "UBOX"
},
{
"BriefDescription": "RACU Request",
"Counter": "0,1",
"EventCode": "0x46",
"EventName": "UNC_U_RACU_REQUESTS",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "RACU Request : Number outstanding register requests within message channel tracker",
"Unit": "UBOX"
}
]
Codebase Browser
linux