[
{
"BriefDescription": "Counts the number of request that were not accepted into the L2Q because the L2Q is FULL.",
"Counter": "0,1",
"EventCode": "0x31",
"EventName": "CORE_REJECT_L2Q.ALL",
"PublicDescription": "Counts the number of (demand and L1 prefetchers) core requests rejected by the L2Q due to a full or nearly full w condition which likely indicates back pressure from L2Q. It also counts requests that would have gone directly to the XQ, but are rejected due to a full or nearly full condition, indicating back pressure from the IDI link. The L2Q may also reject transactions from a core to insure fairness between cores, or to delay a core?s dirty eviction when the address conflicts incoming external snoops. (Note that L2 prefetcher requests that are dropped are not counted by this event.)",
"SampleAfterValue": "200003"
},
{
"BriefDescription": "Cycles code-fetch stalled due to an outstanding ICache miss.",
"Counter": "0,1",
"EventCode": "0x86",
"EventName": "FETCH_STALL.ICACHE_FILL_PENDING_CYCLES",
"PublicDescription": "Counts cycles that fetch is stalled due to an outstanding ICache miss. That is, the decoder queue is able to accept bytes, but the fetch unit is unable to provide bytes due to an ICache miss. Note: this event is not the same as the total number of cycles spent retrieving instruction cache lines from the memory hierarchy.\r\nCounts cycles that fetch is stalled due to any reason. That is, the decoder queue is able to accept bytes, but the fetch unit is unable to provide bytes. This will include cycles due to an ITLB miss, ICache miss and other events.",
"SampleAfterValue": "200003",
"UMask": "0x4"
},
{
"BriefDescription": "Counts the number of request from the L2 that were not accepted into the XQ",
"Counter": "0,1",
"EventCode": "0x30",
"EventName": "L2_REJECT_XQ.ALL",
"PublicDescription": "This event counts the number of demand and prefetch transactions that the L2 XQ rejects due to a full or near full condition which likely indicates back pressure from the IDI link. The XQ may reject transactions from the L2Q (non-cacheable requests), BBS (L2 misses) and WOB (L2 write-back victims).",
"SampleAfterValue": "200003"
},
{
"BriefDescription": "L2 cache request misses",
"Counter": "0,1",
"EventCode": "0x2E",
"EventName": "LONGEST_LAT_CACHE.MISS",
"PublicDescription": "This event counts the total number of L2 cache references and the number of L2 cache misses respectively.",
"SampleAfterValue": "200003",
"UMask": "0x41"
},
{
"BriefDescription": "L2 cache requests from this core",
"Counter": "0,1",
"EventCode": "0x2E",
"EventName": "LONGEST_LAT_CACHE.REFERENCE",
"PublicDescription": "This event counts requests originating from the core that references a cache line in the L2 cache.",
"SampleAfterValue": "200003",
"UMask": "0x4f"
},
{
"BriefDescription": "All Loads",
"Counter": "0,1",
"EventCode": "0x04",
"EventName": "MEM_UOPS_RETIRED.ALL_LOADS",
"PublicDescription": "This event counts the number of load ops retired.",
"SampleAfterValue": "200003",
"UMask": "0x40"
},
{
"BriefDescription": "All Stores",
"Counter": "0,1",
"EventCode": "0x04",
"EventName": "MEM_UOPS_RETIRED.ALL_STORES",
"PublicDescription": "This event counts the number of store ops retired.",
"SampleAfterValue": "200003",
"UMask": "0x80"
},
{
"BriefDescription": "Cross core or cross module hitm",
"Counter": "0,1",
"EventCode": "0x04",
"EventName": "MEM_UOPS_RETIRED.HITM",
"PEBS": "1",
"PublicDescription": "This event counts the number of load ops retired that got data from the other core or from the other module.",
"SampleAfterValue": "200003",
"UMask": "0x20"
},
{
"BriefDescription": "Loads missed L1",
"Counter": "0,1",
"EventCode": "0x04",
"EventName": "MEM_UOPS_RETIRED.L1_MISS_LOADS",
"PublicDescription": "This event counts the number of load ops retired that miss in L1 Data cache. Note that prefetch misses will not be counted.",
"SampleAfterValue": "200003",
"UMask": "0x1"
},
{
"BriefDescription": "Loads hit L2",
"Counter": "0,1",
"EventCode": "0x04",
"EventName": "MEM_UOPS_RETIRED.L2_HIT_LOADS",
"PEBS": "1",
"PublicDescription": "This event counts the number of load ops retired that hit in the L2.",
"SampleAfterValue": "200003",
"UMask": "0x2"
},
{
"BriefDescription": "Loads missed L2",
"Counter": "0,1",
"EventCode": "0x04",
"EventName": "MEM_UOPS_RETIRED.L2_MISS_LOADS",
"PEBS": "1",
"PublicDescription": "This event counts the number of load ops retired that miss in the L2.",
"SampleAfterValue": "100007",
"UMask": "0x4"
},
{
"BriefDescription": "Loads missed UTLB",
"Counter": "0,1",
"EventCode": "0x04",
"EventName": "MEM_UOPS_RETIRED.UTLB_MISS",
"PublicDescription": "This event counts the number of load ops retired that had UTLB miss.",
"SampleAfterValue": "200003",
"UMask": "0x10"
},
{
"BriefDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction",
"Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any code reads (demand & prefetch) that have any response type.",
"Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0000010044",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any code reads (demand & prefetch) that miss L2.",
"Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.L2_MISS.ANY",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1680000044",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any code reads (demand & prefetch) that hit in the other module where modified copies were found in other core's L1 cache.",
"Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.L2_MISS.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000000044",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any code reads (demand & prefetch) that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",
"Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.L2_MISS.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0400000044",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any code reads (demand & prefetch) that miss L2 with a snoop miss response.",
"Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.L2_MISS.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0200000044",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any data read (demand & prefetch) that have any response type.",
"Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0000013091",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any data read (demand & prefetch) that miss L2.",
"Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_MISS.ANY",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1680003091",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any data read (demand & prefetch) that hit in the other module where modified copies were found in other core's L1 cache.",
"Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_MISS.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000003091",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any data read (demand & prefetch) that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",
"Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_MISS.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0400003091",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any data read (demand & prefetch) that miss L2 with a snoop miss response.",
"Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_MISS.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0200003091",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any request that have any response type.",
"Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0000018008",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any request that hit in the other module where modified copies were found in other core's L1 cache.",
"Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_MISS.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000008008",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any request that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",
"Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_MISS.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0400008008",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any request that miss L2 with a snoop miss response.",
"Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_MISS.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0200008008",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any rfo reads (demand & prefetch) that have any response type.",
"Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0000010022",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any rfo reads (demand & prefetch) that miss L2.",
"Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_MISS.ANY",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1680000022",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any rfo reads (demand & prefetch) that hit in the other module where modified copies were found in other core's L1 cache.",
"Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_MISS.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000000022",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any rfo reads (demand & prefetch) that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",
"Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_MISS.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0400000022",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any rfo reads (demand & prefetch) that miss L2 with a snoop miss response.",
"Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_MISS.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0200000022",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts writeback (modified to exclusive) that miss L2.",
"Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.COREWB.L2_MISS.ANY",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1680000008",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts writeback (modified to exclusive) that miss L2 with no details on snoop-related information.",
"Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.COREWB.L2_MISS.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0080000008",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand and DCU prefetch instruction cacheline that have any response type.",
"Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0000010004",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand and DCU prefetch instruction cacheline that miss L2.",
"Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_MISS.ANY",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1680000004",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand and DCU prefetch instruction cacheline that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",
"Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_MISS.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0400000004",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand and DCU prefetch instruction cacheline that miss L2 with a snoop miss response.",
"Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_MISS.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0200000004",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand and DCU prefetch instruction cacheline that are are outstanding, per cycle, from the time of the L2 miss to when any response is received.",
"Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.OUTSTANDING",
"MSRIndex": "0x1a6",
"MSRValue": "0x4000000004",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand and DCU prefetch data read that have any response type.",
"Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0000010001",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand and DCU prefetch data read that miss L2.",
"Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_MISS.ANY",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1680000001",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand and DCU prefetch data read that hit in the other module where modified copies were found in other core's L1 cache.",
"Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_MISS.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000000001",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand and DCU prefetch data read that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",
"Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_MISS.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0400000001",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand and DCU prefetch data read that miss L2 with a snoop miss response.",
"Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_MISS.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0200000001",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand and DCU prefetch data read that are are outstanding, per cycle, from the time of the L2 miss to when any response is received.",
"Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.OUTSTANDING",
"MSRIndex": "0x1a6",
"MSRValue": "0x4000000001",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand and DCU prefetch RFOs that miss L2.",
"Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_MISS.ANY",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1680000002",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand and DCU prefetch RFOs that hit in the other module where modified copies were found in other core's L1 cache.",
"Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_MISS.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000000002",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand and DCU prefetch RFOs that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",
"Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_MISS.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0400000002",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand and DCU prefetch RFOs that miss L2 with a snoop miss response.",
"Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_MISS.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0200000002",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand and DCU prefetch RFOs that are are outstanding, per cycle, from the time of the L2 miss to when any response is received.",
"Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.OUTSTANDING",
"MSRIndex": "0x1a6",
"MSRValue": "0x4000000002",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand reads of partial cache lines (including UC and WC) that miss L2.",
"Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PARTIAL_READS.L2_MISS.ANY",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1680000080",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Countsof demand RFO requests to write to partial cache lines that miss L2.",
"Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.L2_MISS.ANY",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1680000100",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts DCU hardware prefetcher data read that have any response type.",
"Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0000012000",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts DCU hardware prefetcher data read that miss L2.",
"Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_MISS.ANY",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1680002000",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts DCU hardware prefetcher data read that hit in the other module where modified copies were found in other core's L1 cache.",
"Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_MISS.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000002000",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts DCU hardware prefetcher data read that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",
"Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_MISS.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0400002000",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts DCU hardware prefetcher data read that miss L2 with a snoop miss response.",
"Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_MISS.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0200002000",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts code reads generated by L2 prefetchers that miss L2.",
"Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L2_MISS.ANY",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1680000040",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts code reads generated by L2 prefetchers that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",
"Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L2_MISS.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0400000040",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts code reads generated by L2 prefetchers that miss L2 with a snoop miss response.",
"Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L2_MISS.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0200000040",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts data cacheline reads generated by L2 prefetchers that miss L2.",
"Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L2_MISS.ANY",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1680000010",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts data cacheline reads generated by L2 prefetchers that hit in the other module where modified copies were found in other core's L1 cache.",
"Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L2_MISS.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000000010",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts data cacheline reads generated by L2 prefetchers that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",
"Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L2_MISS.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0400000010",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts data cacheline reads generated by L2 prefetchers that miss L2 with a snoop miss response.",
"Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L2_MISS.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0200000010",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts RFO requests generated by L2 prefetchers that miss L2.",
"Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_MISS.ANY",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1680000020",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts RFO requests generated by L2 prefetchers that hit in the other module where modified copies were found in other core's L1 cache.",
"Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_MISS.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000000020",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts RFO requests generated by L2 prefetchers that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",
"Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_MISS.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0400000020",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts RFO requests generated by L2 prefetchers that miss L2 with a snoop miss response.",
"Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_MISS.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0200000020",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Counts streaming store that miss L2.",
"Counter": "0,1",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.STREAMING_STORES.L2_MISS.ANY",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1680004800",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Any reissued load uops",
"Counter": "0,1",
"EventCode": "0x03",
"EventName": "REHABQ.ANY_LD",
"PublicDescription": "This event counts the number of load uops reissued from Rehabq.",
"SampleAfterValue": "200003",
"UMask": "0x40"
},
{
"BriefDescription": "Any reissued store uops",
"Counter": "0,1",
"EventCode": "0x03",
"EventName": "REHABQ.ANY_ST",
"PublicDescription": "This event counts the number of store uops reissued from Rehabq.",
"SampleAfterValue": "200003",
"UMask": "0x80"
},
{
"BriefDescription": "Loads blocked due to store data not ready",
"Counter": "0,1",
"EventCode": "0x03",
"EventName": "REHABQ.LD_BLOCK_STD_NOTREADY",
"PublicDescription": "This event counts the cases where a forward was technically possible, but did not occur because the store data was not available at the right time.",
"SampleAfterValue": "200003",
"UMask": "0x2"
},
{
"BriefDescription": "Loads blocked due to store forward restriction",
"Counter": "0,1",
"EventCode": "0x03",
"EventName": "REHABQ.LD_BLOCK_ST_FORWARD",
"PEBS": "1",
"PublicDescription": "This event counts the number of retired loads that were prohibited from receiving forwarded data from the store because of address mismatch.",
"SampleAfterValue": "200003",
"UMask": "0x1"
},
{
"BriefDescription": "Load uops that split cache line boundary",
"Counter": "0,1",
"EventCode": "0x03",
"EventName": "REHABQ.LD_SPLITS",
"PEBS": "1",
"PublicDescription": "This event counts the number of retire loads that experienced cache line boundary splits.",
"SampleAfterValue": "200003",
"UMask": "0x8"
},
{
"BriefDescription": "Uops with lock semantics",
"Counter": "0,1",
"EventCode": "0x03",
"EventName": "REHABQ.LOCK",
"PublicDescription": "This event counts the number of retired memory operations with lock semantics. These are either implicit locked instructions such as the XCHG instruction or instructions with an explicit LOCK prefix (0xF0).",
"SampleAfterValue": "200003",
"UMask": "0x10"
},
{
"BriefDescription": "Store address buffer full",
"Counter": "0,1",
"EventCode": "0x03",
"EventName": "REHABQ.STA_FULL",
"PublicDescription": "This event counts the number of retired stores that are delayed because there is not a store address buffer available.",
"SampleAfterValue": "200003",
"UMask": "0x20"
},
{
"BriefDescription": "Store uops that split cache line boundary",
"Counter": "0,1",
"EventCode": "0x03",
"EventName": "REHABQ.ST_SPLITS",
"PublicDescription": "This event counts the number of retire stores that experienced cache line boundary splits.",
"SampleAfterValue": "200003",
"UMask": "0x4"
}
]
Codebase Browser
linux