/*
* Copyright 2023 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef _mmhub_4_1_0_OFFSET_HEADER
#define _mmhub_4_1_0_OFFSET_HEADER
// addressBlock: mmhub_dagb_dagbdec
// base address: 0x68000
#define regDAGB0_RDCLI0 0x0000
#define regDAGB0_RDCLI0_BASE_IDX 0
#define regDAGB0_RDCLI1 0x0001
#define regDAGB0_RDCLI1_BASE_IDX 0
#define regDAGB0_RDCLI2 0x0002
#define regDAGB0_RDCLI2_BASE_IDX 0
#define regDAGB0_RDCLI3 0x0003
#define regDAGB0_RDCLI3_BASE_IDX 0
#define regDAGB0_RDCLI4 0x0004
#define regDAGB0_RDCLI4_BASE_IDX 0
#define regDAGB0_RDCLI5 0x0005
#define regDAGB0_RDCLI5_BASE_IDX 0
#define regDAGB0_RDCLI6 0x0006
#define regDAGB0_RDCLI6_BASE_IDX 0
#define regDAGB0_RDCLI7 0x0007
#define regDAGB0_RDCLI7_BASE_IDX 0
#define regDAGB0_RDCLI8 0x0008
#define regDAGB0_RDCLI8_BASE_IDX 0
#define regDAGB0_RDCLI9 0x0009
#define regDAGB0_RDCLI9_BASE_IDX 0
#define regDAGB0_RDCLI10 0x000a
#define regDAGB0_RDCLI10_BASE_IDX 0
#define regDAGB0_RDCLI11 0x000b
#define regDAGB0_RDCLI11_BASE_IDX 0
#define regDAGB0_RDCLI12 0x000c
#define regDAGB0_RDCLI12_BASE_IDX 0
#define regDAGB0_RDCLI13 0x000d
#define regDAGB0_RDCLI13_BASE_IDX 0
#define regDAGB0_RDCLI14 0x000e
#define regDAGB0_RDCLI14_BASE_IDX 0
#define regDAGB0_RDCLI15 0x000f
#define regDAGB0_RDCLI15_BASE_IDX 0
#define regDAGB0_RDCLI16 0x0010
#define regDAGB0_RDCLI16_BASE_IDX 0
#define regDAGB0_RDCLI17 0x0011
#define regDAGB0_RDCLI17_BASE_IDX 0
#define regDAGB0_RDCLI18 0x0012
#define regDAGB0_RDCLI18_BASE_IDX 0
#define regDAGB0_RDCLI19 0x0013
#define regDAGB0_RDCLI19_BASE_IDX 0
#define regDAGB0_RDCLI20 0x0014
#define regDAGB0_RDCLI20_BASE_IDX 0
#define regDAGB0_RDCLI21 0x0015
#define regDAGB0_RDCLI21_BASE_IDX 0
#define regDAGB0_RDCLI22 0x0016
#define regDAGB0_RDCLI22_BASE_IDX 0
#define regDAGB0_RDCLI23 0x0017
#define regDAGB0_RDCLI23_BASE_IDX 0
#define regDAGB0_RD_CNTL 0x001a
#define regDAGB0_RD_CNTL_BASE_IDX 0
#define regDAGB0_RD_IO_CNTL 0x001b
#define regDAGB0_RD_IO_CNTL_BASE_IDX 0
#define regDAGB0_RD_GMI_CNTL 0x001c
#define regDAGB0_RD_GMI_CNTL_BASE_IDX 0
#define regDAGB0_RD_ADDR_DAGB 0x001d
#define regDAGB0_RD_ADDR_DAGB_BASE_IDX 0
#define regDAGB0_RD_CGTT_CLK_CTRL 0x001e
#define regDAGB0_RD_CGTT_CLK_CTRL_BASE_IDX 0
#define regDAGB0_L1TLB_RD_CGTT_CLK_CTRL 0x001f
#define regDAGB0_L1TLB_RD_CGTT_CLK_CTRL_BASE_IDX 0
#define regDAGB0_RD_ADDR_DAGB_MAX_BURST0 0x0020
#define regDAGB0_RD_ADDR_DAGB_MAX_BURST0_BASE_IDX 0
#define regDAGB0_RD_ADDR_DAGB_LAZY_TIMER0 0x0021
#define regDAGB0_RD_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 0
#define regDAGB0_RD_ADDR_DAGB_MAX_BURST1 0x0022
#define regDAGB0_RD_ADDR_DAGB_MAX_BURST1_BASE_IDX 0
#define regDAGB0_RD_ADDR_DAGB_LAZY_TIMER1 0x0023
#define regDAGB0_RD_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 0
#define regDAGB0_RD_ADDR_DAGB_MAX_BURST2 0x0024
#define regDAGB0_RD_ADDR_DAGB_MAX_BURST2_BASE_IDX 0
#define regDAGB0_RD_ADDR_DAGB_LAZY_TIMER2 0x0025
#define regDAGB0_RD_ADDR_DAGB_LAZY_TIMER2_BASE_IDX 0
#define regDAGB0_RD_VC0_CNTL 0x0026
#define regDAGB0_RD_VC0_CNTL_BASE_IDX 0
#define regDAGB0_RD_VC1_CNTL 0x0027
#define regDAGB0_RD_VC1_CNTL_BASE_IDX 0
#define regDAGB0_RD_VC2_CNTL 0x0028
#define regDAGB0_RD_VC2_CNTL_BASE_IDX 0
#define regDAGB0_RD_VC3_CNTL 0x0029
#define regDAGB0_RD_VC3_CNTL_BASE_IDX 0
#define regDAGB0_RD_VC4_CNTL 0x002a
#define regDAGB0_RD_VC4_CNTL_BASE_IDX 0
#define regDAGB0_RD_VC5_CNTL 0x002b
#define regDAGB0_RD_VC5_CNTL_BASE_IDX 0
#define regDAGB0_RD_IO_VC_CNTL 0x002c
#define regDAGB0_RD_IO_VC_CNTL_BASE_IDX 0
#define regDAGB0_RD_GMI_VC_CNTL 0x002d
#define regDAGB0_RD_GMI_VC_CNTL_BASE_IDX 0
#define regDAGB0_RD_CNTL_MISC 0x002e
#define regDAGB0_RD_CNTL_MISC_BASE_IDX 0
#define regDAGB0_RD_TLB_CREDIT 0x002f
#define regDAGB0_RD_TLB_CREDIT_BASE_IDX 0
#define regDAGB0_RDCLI_ASK_PENDING 0x0030
#define regDAGB0_RDCLI_ASK_PENDING_BASE_IDX 0
#define regDAGB0_RDCLI_GO_PENDING 0x0031
#define regDAGB0_RDCLI_GO_PENDING_BASE_IDX 0
#define regDAGB0_RDCLI_GBLSEND_PENDING 0x0032
#define regDAGB0_RDCLI_GBLSEND_PENDING_BASE_IDX 0
#define regDAGB0_RDCLI_TLB_PENDING 0x0033
#define regDAGB0_RDCLI_TLB_PENDING_BASE_IDX 0
#define regDAGB0_RDCLI_OARB_PENDING 0x0034
#define regDAGB0_RDCLI_OARB_PENDING_BASE_IDX 0
#define regDAGB0_RDCLI_ASK2ARB_PENDING 0x0035
#define regDAGB0_RDCLI_ASK2ARB_PENDING_BASE_IDX 0
#define regDAGB0_RDCLI_ASK2DF_PENDING 0x0036
#define regDAGB0_RDCLI_ASK2DF_PENDING_BASE_IDX 0
#define regDAGB0_RDCLI_OSD_PENDING 0x0037
#define regDAGB0_RDCLI_OSD_PENDING_BASE_IDX 0
#define regDAGB0_RDCLI_ASK_OSD_PENDING 0x0038
#define regDAGB0_RDCLI_ASK_OSD_PENDING_BASE_IDX 0
#define regDAGB0_WRCLI0 0x0039
#define regDAGB0_WRCLI0_BASE_IDX 0
#define regDAGB0_WRCLI1 0x003a
#define regDAGB0_WRCLI1_BASE_IDX 0
#define regDAGB0_WRCLI2 0x003b
#define regDAGB0_WRCLI2_BASE_IDX 0
#define regDAGB0_WRCLI3 0x003c
#define regDAGB0_WRCLI3_BASE_IDX 0
#define regDAGB0_WRCLI4 0x003d
#define regDAGB0_WRCLI4_BASE_IDX 0
#define regDAGB0_WRCLI5 0x003e
#define regDAGB0_WRCLI5_BASE_IDX 0
#define regDAGB0_WRCLI6 0x003f
#define regDAGB0_WRCLI6_BASE_IDX 0
#define regDAGB0_WRCLI7 0x0040
#define regDAGB0_WRCLI7_BASE_IDX 0
#define regDAGB0_WRCLI8 0x0041
#define regDAGB0_WRCLI8_BASE_IDX 0
#define regDAGB0_WRCLI9 0x0042
#define regDAGB0_WRCLI9_BASE_IDX 0
#define regDAGB0_WRCLI10 0x0043
#define regDAGB0_WRCLI10_BASE_IDX 0
#define regDAGB0_WRCLI11 0x0044
#define regDAGB0_WRCLI11_BASE_IDX 0
#define regDAGB0_WRCLI12 0x0045
#define regDAGB0_WRCLI12_BASE_IDX 0
#define regDAGB0_WRCLI13 0x0046
#define regDAGB0_WRCLI13_BASE_IDX 0
#define regDAGB0_WRCLI14 0x0047
#define regDAGB0_WRCLI14_BASE_IDX 0
#define regDAGB0_WRCLI15 0x0048
#define regDAGB0_WRCLI15_BASE_IDX 0
#define regDAGB0_WRCLI16 0x0049
#define regDAGB0_WRCLI16_BASE_IDX 0
#define regDAGB0_WRCLI17 0x004a
#define regDAGB0_WRCLI17_BASE_IDX 0
#define regDAGB0_WRCLI18 0x004b
#define regDAGB0_WRCLI18_BASE_IDX 0
#define regDAGB0_WRCLI19 0x004c
#define regDAGB0_WRCLI19_BASE_IDX 0
#define regDAGB0_WRCLI20 0x004d
#define regDAGB0_WRCLI20_BASE_IDX 0
#define regDAGB0_WRCLI21 0x004e
#define regDAGB0_WRCLI21_BASE_IDX 0
#define regDAGB0_WRCLI22 0x004f
#define regDAGB0_WRCLI22_BASE_IDX 0
#define regDAGB0_WRCLI23 0x0050
#define regDAGB0_WRCLI23_BASE_IDX 0
#define regDAGB0_WR_CNTL 0x0071
#define regDAGB0_WR_CNTL_BASE_IDX 0
#define regDAGB0_WR_IO_CNTL 0x0072
#define regDAGB0_WR_IO_CNTL_BASE_IDX 0
#define regDAGB0_WR_GMI_CNTL 0x0073
#define regDAGB0_WR_GMI_CNTL_BASE_IDX 0
#define regDAGB0_WR_ADDR_DAGB 0x0074
#define regDAGB0_WR_ADDR_DAGB_BASE_IDX 0
#define regDAGB0_WR_CGTT_CLK_CTRL 0x0075
#define regDAGB0_WR_CGTT_CLK_CTRL_BASE_IDX 0
#define regDAGB0_L1TLB_WR_CGTT_CLK_CTRL 0x0076
#define regDAGB0_L1TLB_WR_CGTT_CLK_CTRL_BASE_IDX 0
#define regDAGB0_WR_ADDR_DAGB_MAX_BURST0 0x0077
#define regDAGB0_WR_ADDR_DAGB_MAX_BURST0_BASE_IDX 0
#define regDAGB0_WR_ADDR_DAGB_LAZY_TIMER0 0x0078
#define regDAGB0_WR_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 0
#define regDAGB0_WR_ADDR_DAGB_MAX_BURST1 0x0079
#define regDAGB0_WR_ADDR_DAGB_MAX_BURST1_BASE_IDX 0
#define regDAGB0_WR_ADDR_DAGB_LAZY_TIMER1 0x007a
#define regDAGB0_WR_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 0
#define regDAGB0_WR_ADDR_DAGB_MAX_BURST2 0x007b
#define regDAGB0_WR_ADDR_DAGB_MAX_BURST2_BASE_IDX 0
#define regDAGB0_WR_ADDR_DAGB_LAZY_TIMER2 0x007c
#define regDAGB0_WR_ADDR_DAGB_LAZY_TIMER2_BASE_IDX 0
#define regDAGB0_WR_DATA_DAGB 0x007d
#define regDAGB0_WR_DATA_DAGB_BASE_IDX 0
#define regDAGB0_WR_DATA_DAGB_MAX_BURST0 0x007e
#define regDAGB0_WR_DATA_DAGB_MAX_BURST0_BASE_IDX 0
#define regDAGB0_WR_DATA_DAGB_LAZY_TIMER0 0x007f
#define regDAGB0_WR_DATA_DAGB_LAZY_TIMER0_BASE_IDX 0
#define regDAGB0_WR_DATA_DAGB_MAX_BURST1 0x0080
#define regDAGB0_WR_DATA_DAGB_MAX_BURST1_BASE_IDX 0
#define regDAGB0_WR_DATA_DAGB_LAZY_TIMER1 0x0081
#define regDAGB0_WR_DATA_DAGB_LAZY_TIMER1_BASE_IDX 0
#define regDAGB0_WR_DATA_DAGB_MAX_BURST2 0x0082
#define regDAGB0_WR_DATA_DAGB_MAX_BURST2_BASE_IDX 0
#define regDAGB0_WR_DATA_DAGB_LAZY_TIMER2 0x0083
#define regDAGB0_WR_DATA_DAGB_LAZY_TIMER2_BASE_IDX 0
#define regDAGB0_WR_VC0_CNTL 0x0084
#define regDAGB0_WR_VC0_CNTL_BASE_IDX 0
#define regDAGB0_WR_VC1_CNTL 0x0085
#define regDAGB0_WR_VC1_CNTL_BASE_IDX 0
#define regDAGB0_WR_VC2_CNTL 0x0086
#define regDAGB0_WR_VC2_CNTL_BASE_IDX 0
#define regDAGB0_WR_VC3_CNTL 0x0087
#define regDAGB0_WR_VC3_CNTL_BASE_IDX 0
#define regDAGB0_WR_VC4_CNTL 0x0088
#define regDAGB0_WR_VC4_CNTL_BASE_IDX 0
#define regDAGB0_WR_VC5_CNTL 0x0089
#define regDAGB0_WR_VC5_CNTL_BASE_IDX 0
#define regDAGB0_WR_IO_VC_CNTL 0x008a
#define regDAGB0_WR_IO_VC_CNTL_BASE_IDX 0
#define regDAGB0_WR_GMI_VC_CNTL 0x008b
#define regDAGB0_WR_GMI_VC_CNTL_BASE_IDX 0
#define regDAGB0_WR_CNTL_MISC 0x008c
#define regDAGB0_WR_CNTL_MISC_BASE_IDX 0
#define regDAGB0_WR_TLB_CREDIT 0x008d
#define regDAGB0_WR_TLB_CREDIT_BASE_IDX 0
#define regDAGB0_WR_DATA_FIFO_CREDIT_CNTL1 0x008e
#define regDAGB0_WR_DATA_FIFO_CREDIT_CNTL1_BASE_IDX 0
#define regDAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1 0x008f
#define regDAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1_BASE_IDX 0
#define regDAGB0_WRCLI_ASK_PENDING 0x0090
#define regDAGB0_WRCLI_ASK_PENDING_BASE_IDX 0
#define regDAGB0_WRCLI_GO_PENDING 0x0091
#define regDAGB0_WRCLI_GO_PENDING_BASE_IDX 0
#define regDAGB0_WRCLI_GBLSEND_PENDING 0x0092
#define regDAGB0_WRCLI_GBLSEND_PENDING_BASE_IDX 0
#define regDAGB0_WRCLI_TLB_PENDING 0x0093
#define regDAGB0_WRCLI_TLB_PENDING_BASE_IDX 0
#define regDAGB0_WRCLI_OARB_PENDING 0x0094
#define regDAGB0_WRCLI_OARB_PENDING_BASE_IDX 0
#define regDAGB0_WRCLI_ASK2ARB_PENDING 0x0095
#define regDAGB0_WRCLI_ASK2ARB_PENDING_BASE_IDX 0
#define regDAGB0_WRCLI_ASK2DF_PENDING 0x0096
#define regDAGB0_WRCLI_ASK2DF_PENDING_BASE_IDX 0
#define regDAGB0_WRCLI_OSD_PENDING 0x0097
#define regDAGB0_WRCLI_OSD_PENDING_BASE_IDX 0
#define regDAGB0_WRCLI_ASK_OSD_PENDING 0x0098
#define regDAGB0_WRCLI_ASK_OSD_PENDING_BASE_IDX 0
#define regDAGB0_WRCLI_DBUS_ASK_PENDING 0x0099
#define regDAGB0_WRCLI_DBUS_ASK_PENDING_BASE_IDX 0
#define regDAGB0_WRCLI_DBUS_GO_PENDING 0x009a
#define regDAGB0_WRCLI_DBUS_GO_PENDING_BASE_IDX 0
#define regDAGB0_SDP_ERR_STATUS 0x009d
#define regDAGB0_SDP_ERR_STATUS_BASE_IDX 0
#define regDAGB0_DAGB_DLY 0x009f
#define regDAGB0_DAGB_DLY_BASE_IDX 0
#define regDAGB0_CNTL_MISC 0x00a0
#define regDAGB0_CNTL_MISC_BASE_IDX 0
#define regDAGB0_CNTL_MISC2 0x00a1
#define regDAGB0_CNTL_MISC2_BASE_IDX 0
#define regDAGB0_FIFO_EMPTY 0x00a2
#define regDAGB0_FIFO_EMPTY_BASE_IDX 0
#define regDAGB0_FIFO_FULL 0x00a3
#define regDAGB0_FIFO_FULL_BASE_IDX 0
#define regDAGB0_RD_CREDITS_FULL 0x00a4
#define regDAGB0_RD_CREDITS_FULL_BASE_IDX 0
#define regDAGB0_WR_CREDITS_FULL 0x00a5
#define regDAGB0_WR_CREDITS_FULL_BASE_IDX 0
#define regDAGB0_PERFCOUNTER_LO 0x00a6
#define regDAGB0_PERFCOUNTER_LO_BASE_IDX 0
#define regDAGB0_PERFCOUNTER_HI 0x00a7
#define regDAGB0_PERFCOUNTER_HI_BASE_IDX 0
#define regDAGB0_PERFCOUNTER0_CFG 0x00a8
#define regDAGB0_PERFCOUNTER0_CFG_BASE_IDX 0
#define regDAGB0_PERFCOUNTER1_CFG 0x00a9
#define regDAGB0_PERFCOUNTER1_CFG_BASE_IDX 0
#define regDAGB0_PERFCOUNTER2_CFG 0x00aa
#define regDAGB0_PERFCOUNTER2_CFG_BASE_IDX 0
#define regDAGB0_PERFCOUNTER_RSLT_CNTL 0x00ab
#define regDAGB0_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0
#define regDAGB0_L1TLB_REG_RW 0x00ac
#define regDAGB0_L1TLB_REG_RW_BASE_IDX 0
#define regDAGB0_RESERVE0 0x00ad
#define regDAGB0_RESERVE0_BASE_IDX 0
#define regDAGB0_RESERVE1 0x00ae
#define regDAGB0_RESERVE1_BASE_IDX 0
#define regDAGB0_RESERVE2 0x00af
#define regDAGB0_RESERVE2_BASE_IDX 0
#define regDAGB0_RESERVE3 0x00b0
#define regDAGB0_RESERVE3_BASE_IDX 0
#define regDAGB0_SDP_RD_BW_CNTL 0x00b1
#define regDAGB0_SDP_RD_BW_CNTL_BASE_IDX 0
#define regDAGB0_SDP_PRIORITY_OVERRIDE 0x00b3
#define regDAGB0_SDP_PRIORITY_OVERRIDE_BASE_IDX 0
#define regDAGB0_SDP_RD_PRIORITY 0x00b4
#define regDAGB0_SDP_RD_PRIORITY_BASE_IDX 0
#define regDAGB0_SDP_WR_PRIORITY 0x00b5
#define regDAGB0_SDP_WR_PRIORITY_BASE_IDX 0
#define regDAGB0_SDP_RD_CLI2SDP_VC_MAP 0x00b6
#define regDAGB0_SDP_RD_CLI2SDP_VC_MAP_BASE_IDX 0
#define regDAGB0_SDP_WR_CLI2SDP_VC_MAP 0x00b7
#define regDAGB0_SDP_WR_CLI2SDP_VC_MAP_BASE_IDX 0
#define regDAGB0_SDP_ENABLE 0x00b8
#define regDAGB0_SDP_ENABLE_BASE_IDX 0
#define regDAGB0_SDP_CREDITS 0x00b9
#define regDAGB0_SDP_CREDITS_BASE_IDX 0
#define regDAGB0_SDP_TAG_RESERVE0 0x00ba
#define regDAGB0_SDP_TAG_RESERVE0_BASE_IDX 0
#define regDAGB0_SDP_TAG_RESERVE1 0x00bb
#define regDAGB0_SDP_TAG_RESERVE1_BASE_IDX 0
#define regDAGB0_SDP_VCC_RESERVE0 0x00bc
#define regDAGB0_SDP_VCC_RESERVE0_BASE_IDX 0
#define regDAGB0_SDP_VCC_RESERVE1 0x00bd
#define regDAGB0_SDP_VCC_RESERVE1_BASE_IDX 0
#define regDAGB0_SDP_REQ_CNTL 0x00be
#define regDAGB0_SDP_REQ_CNTL_BASE_IDX 0
#define regDAGB0_SDP_MISC_AON 0x00bf
#define regDAGB0_SDP_MISC_AON_BASE_IDX 0
#define regDAGB0_SDP_MISC 0x00c0
#define regDAGB0_SDP_MISC_BASE_IDX 0
#define regDAGB0_SDP_MISC2 0x00c1
#define regDAGB0_SDP_MISC2_BASE_IDX 0
#define regDAGB0_SDP_VCD_RESERVE0 0x00c2
#define regDAGB0_SDP_VCD_RESERVE0_BASE_IDX 0
#define regDAGB0_SDP_VCD_RESERVE1 0x00c3
#define regDAGB0_SDP_VCD_RESERVE1_BASE_IDX 0
#define regDAGB0_SDP_ARB_CNTL0 0x00c4
#define regDAGB0_SDP_ARB_CNTL0_BASE_IDX 0
#define regDAGB0_SDP_ARB_CNTL1 0x00c5
#define regDAGB0_SDP_ARB_CNTL1_BASE_IDX 0
#define regDAGB0_FATAL_ERROR_CLEAR 0x00c8
#define regDAGB0_FATAL_ERROR_CLEAR_BASE_IDX 0
#define regDAGB0_FATAL_ERROR_STATUS0 0x00c9
#define regDAGB0_FATAL_ERROR_STATUS0_BASE_IDX 0
#define regDAGB0_FATAL_ERROR_STATUS1 0x00ca
#define regDAGB0_FATAL_ERROR_STATUS1_BASE_IDX 0
#define regDAGB0_FATAL_ERROR_STATUS2 0x00cb
#define regDAGB0_FATAL_ERROR_STATUS2_BASE_IDX 0
#define regDAGB0_FATAL_ERROR_STATUS3 0x00cc
#define regDAGB0_FATAL_ERROR_STATUS3_BASE_IDX 0
#define regDAGB0_FATAL_ERROR_STATUS4 0x00cd
#define regDAGB0_FATAL_ERROR_STATUS4_BASE_IDX 0
#define regDAGB0_SDP_CGTT_CLK_CTRL 0x00ce
#define regDAGB0_SDP_CGTT_CLK_CTRL_BASE_IDX 0
#define regDAGB0_SDP_LATENCY_SAMPLING 0x00cf
#define regDAGB0_SDP_LATENCY_SAMPLING_BASE_IDX 0
#define regDAGB0_WRCLI_GPU_SNOOP_OVERRIDE 0x00d4
#define regDAGB0_WRCLI_GPU_SNOOP_OVERRIDE_BASE_IDX 0
#define regDAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE 0x00d9
#define regDAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE_BASE_IDX 0
#define regDAGB1_RDCLI0 0x0200
#define regDAGB1_RDCLI0_BASE_IDX 0
#define regDAGB1_RDCLI1 0x0201
#define regDAGB1_RDCLI1_BASE_IDX 0
#define regDAGB1_RDCLI2 0x0202
#define regDAGB1_RDCLI2_BASE_IDX 0
#define regDAGB1_RDCLI3 0x0203
#define regDAGB1_RDCLI3_BASE_IDX 0
#define regDAGB1_RDCLI4 0x0204
#define regDAGB1_RDCLI4_BASE_IDX 0
#define regDAGB1_RDCLI5 0x0205
#define regDAGB1_RDCLI5_BASE_IDX 0
#define regDAGB1_RDCLI6 0x0206
#define regDAGB1_RDCLI6_BASE_IDX 0
#define regDAGB1_RDCLI7 0x0207
#define regDAGB1_RDCLI7_BASE_IDX 0
#define regDAGB1_RDCLI8 0x0208
#define regDAGB1_RDCLI8_BASE_IDX 0
#define regDAGB1_RDCLI9 0x0209
#define regDAGB1_RDCLI9_BASE_IDX 0
#define regDAGB1_RDCLI10 0x020a
#define regDAGB1_RDCLI10_BASE_IDX 0
#define regDAGB1_RDCLI11 0x020b
#define regDAGB1_RDCLI11_BASE_IDX 0
#define regDAGB1_RDCLI12 0x020c
#define regDAGB1_RDCLI12_BASE_IDX 0
#define regDAGB1_RDCLI13 0x020d
#define regDAGB1_RDCLI13_BASE_IDX 0
#define regDAGB1_RDCLI14 0x020e
#define regDAGB1_RDCLI14_BASE_IDX 0
#define regDAGB1_RDCLI15 0x020f
#define regDAGB1_RDCLI15_BASE_IDX 0
#define regDAGB1_RDCLI16 0x0210
#define regDAGB1_RDCLI16_BASE_IDX 0
#define regDAGB1_RDCLI17 0x0211
#define regDAGB1_RDCLI17_BASE_IDX 0
#define regDAGB1_RDCLI18 0x0212
#define regDAGB1_RDCLI18_BASE_IDX 0
#define regDAGB1_RDCLI19 0x0213
#define regDAGB1_RDCLI19_BASE_IDX 0
#define regDAGB1_RDCLI20 0x0214
#define regDAGB1_RDCLI20_BASE_IDX 0
#define regDAGB1_RDCLI21 0x0215
#define regDAGB1_RDCLI21_BASE_IDX 0
#define regDAGB1_RDCLI22 0x0216
#define regDAGB1_RDCLI22_BASE_IDX 0
#define regDAGB1_RDCLI23 0x0217
#define regDAGB1_RDCLI23_BASE_IDX 0
#define regDAGB1_RD_CNTL 0x021a
#define regDAGB1_RD_CNTL_BASE_IDX 0
#define regDAGB1_RD_IO_CNTL 0x021b
#define regDAGB1_RD_IO_CNTL_BASE_IDX 0
#define regDAGB1_RD_GMI_CNTL 0x021c
#define regDAGB1_RD_GMI_CNTL_BASE_IDX 0
#define regDAGB1_RD_ADDR_DAGB 0x021d
#define regDAGB1_RD_ADDR_DAGB_BASE_IDX 0
#define regDAGB1_RD_CGTT_CLK_CTRL 0x021e
#define regDAGB1_RD_CGTT_CLK_CTRL_BASE_IDX 0
#define regDAGB1_L1TLB_RD_CGTT_CLK_CTRL 0x021f
#define regDAGB1_L1TLB_RD_CGTT_CLK_CTRL_BASE_IDX 0
#define regDAGB1_RD_ADDR_DAGB_MAX_BURST0 0x0220
#define regDAGB1_RD_ADDR_DAGB_MAX_BURST0_BASE_IDX 0
#define regDAGB1_RD_ADDR_DAGB_LAZY_TIMER0 0x0221
#define regDAGB1_RD_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 0
#define regDAGB1_RD_ADDR_DAGB_MAX_BURST1 0x0222
#define regDAGB1_RD_ADDR_DAGB_MAX_BURST1_BASE_IDX 0
#define regDAGB1_RD_ADDR_DAGB_LAZY_TIMER1 0x0223
#define regDAGB1_RD_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 0
#define regDAGB1_RD_ADDR_DAGB_MAX_BURST2 0x0224
#define regDAGB1_RD_ADDR_DAGB_MAX_BURST2_BASE_IDX 0
#define regDAGB1_RD_ADDR_DAGB_LAZY_TIMER2 0x0225
#define regDAGB1_RD_ADDR_DAGB_LAZY_TIMER2_BASE_IDX 0
#define regDAGB1_RD_VC0_CNTL 0x0226
#define regDAGB1_RD_VC0_CNTL_BASE_IDX 0
#define regDAGB1_RD_VC1_CNTL 0x0227
#define regDAGB1_RD_VC1_CNTL_BASE_IDX 0
#define regDAGB1_RD_VC2_CNTL 0x0228
#define regDAGB1_RD_VC2_CNTL_BASE_IDX 0
#define regDAGB1_RD_VC3_CNTL 0x0229
#define regDAGB1_RD_VC3_CNTL_BASE_IDX 0
#define regDAGB1_RD_VC4_CNTL 0x022a
#define regDAGB1_RD_VC4_CNTL_BASE_IDX 0
#define regDAGB1_RD_VC5_CNTL 0x022b
#define regDAGB1_RD_VC5_CNTL_BASE_IDX 0
#define regDAGB1_RD_IO_VC_CNTL 0x022c
#define regDAGB1_RD_IO_VC_CNTL_BASE_IDX 0
#define regDAGB1_RD_GMI_VC_CNTL 0x022d
#define regDAGB1_RD_GMI_VC_CNTL_BASE_IDX 0
#define regDAGB1_RD_CNTL_MISC 0x022e
#define regDAGB1_RD_CNTL_MISC_BASE_IDX 0
#define regDAGB1_RD_TLB_CREDIT 0x022f
#define regDAGB1_RD_TLB_CREDIT_BASE_IDX 0
#define regDAGB1_RDCLI_ASK_PENDING 0x0230
#define regDAGB1_RDCLI_ASK_PENDING_BASE_IDX 0
#define regDAGB1_RDCLI_GO_PENDING 0x0231
#define regDAGB1_RDCLI_GO_PENDING_BASE_IDX 0
#define regDAGB1_RDCLI_GBLSEND_PENDING 0x0232
#define regDAGB1_RDCLI_GBLSEND_PENDING_BASE_IDX 0
#define regDAGB1_RDCLI_TLB_PENDING 0x0233
#define regDAGB1_RDCLI_TLB_PENDING_BASE_IDX 0
#define regDAGB1_RDCLI_OARB_PENDING 0x0234
#define regDAGB1_RDCLI_OARB_PENDING_BASE_IDX 0
#define regDAGB1_RDCLI_ASK2ARB_PENDING 0x0235
#define regDAGB1_RDCLI_ASK2ARB_PENDING_BASE_IDX 0
#define regDAGB1_RDCLI_ASK2DF_PENDING 0x0236
#define regDAGB1_RDCLI_ASK2DF_PENDING_BASE_IDX 0
#define regDAGB1_RDCLI_OSD_PENDING 0x0237
#define regDAGB1_RDCLI_OSD_PENDING_BASE_IDX 0
#define regDAGB1_RDCLI_ASK_OSD_PENDING 0x0238
#define regDAGB1_RDCLI_ASK_OSD_PENDING_BASE_IDX 0
#define regDAGB1_SDP_ERR_STATUS 0x023b
#define regDAGB1_SDP_ERR_STATUS_BASE_IDX 0
#define regDAGB1_DAGB_DLY 0x023c
#define regDAGB1_DAGB_DLY_BASE_IDX 0
#define regDAGB1_CNTL_MISC 0x023d
#define regDAGB1_CNTL_MISC_BASE_IDX 0
#define regDAGB1_CNTL_MISC2 0x023e
#define regDAGB1_CNTL_MISC2_BASE_IDX 0
#define regDAGB1_FIFO_EMPTY 0x023f
#define regDAGB1_FIFO_EMPTY_BASE_IDX 0
#define regDAGB1_FIFO_FULL 0x0240
#define regDAGB1_FIFO_FULL_BASE_IDX 0
#define regDAGB1_RD_CREDITS_FULL 0x0241
#define regDAGB1_RD_CREDITS_FULL_BASE_IDX 0
#define regDAGB1_PERFCOUNTER_LO 0x0242
#define regDAGB1_PERFCOUNTER_LO_BASE_IDX 0
#define regDAGB1_PERFCOUNTER_HI 0x0243
#define regDAGB1_PERFCOUNTER_HI_BASE_IDX 0
#define regDAGB1_PERFCOUNTER0_CFG 0x0244
#define regDAGB1_PERFCOUNTER0_CFG_BASE_IDX 0
#define regDAGB1_PERFCOUNTER1_CFG 0x0245
#define regDAGB1_PERFCOUNTER1_CFG_BASE_IDX 0
#define regDAGB1_PERFCOUNTER2_CFG 0x0246
#define regDAGB1_PERFCOUNTER2_CFG_BASE_IDX 0
#define regDAGB1_PERFCOUNTER_RSLT_CNTL 0x0247
#define regDAGB1_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0
#define regDAGB1_L1TLB_REG_RW 0x0248
#define regDAGB1_L1TLB_REG_RW_BASE_IDX 0
#define regDAGB1_RESERVE0 0x0249
#define regDAGB1_RESERVE0_BASE_IDX 0
#define regDAGB1_RESERVE1 0x024a
#define regDAGB1_RESERVE1_BASE_IDX 0
#define regDAGB1_RESERVE2 0x024b
#define regDAGB1_RESERVE2_BASE_IDX 0
#define regDAGB1_RESERVE3 0x024c
#define regDAGB1_RESERVE3_BASE_IDX 0
#define regDAGB1_SDP_RD_BW_CNTL 0x024d
#define regDAGB1_SDP_RD_BW_CNTL_BASE_IDX 0
#define regDAGB1_SDP_PRIORITY_OVERRIDE 0x024f
#define regDAGB1_SDP_PRIORITY_OVERRIDE_BASE_IDX 0
#define regDAGB1_SDP_RD_PRIORITY 0x0250
#define regDAGB1_SDP_RD_PRIORITY_BASE_IDX 0
#define regDAGB1_SDP_RD_CLI2SDP_VC_MAP 0x0251
#define regDAGB1_SDP_RD_CLI2SDP_VC_MAP_BASE_IDX 0
#define regDAGB1_SDP_ENABLE 0x0252
#define regDAGB1_SDP_ENABLE_BASE_IDX 0
#define regDAGB1_SDP_CREDITS 0x0253
#define regDAGB1_SDP_CREDITS_BASE_IDX 0
#define regDAGB1_SDP_TAG_RESERVE0 0x0254
#define regDAGB1_SDP_TAG_RESERVE0_BASE_IDX 0
#define regDAGB1_SDP_TAG_RESERVE1 0x0255
#define regDAGB1_SDP_TAG_RESERVE1_BASE_IDX 0
#define regDAGB1_SDP_VCC_RESERVE0 0x0256
#define regDAGB1_SDP_VCC_RESERVE0_BASE_IDX 0
#define regDAGB1_SDP_VCC_RESERVE1 0x0257
#define regDAGB1_SDP_VCC_RESERVE1_BASE_IDX 0
#define regDAGB1_SDP_REQ_CNTL 0x0258
#define regDAGB1_SDP_REQ_CNTL_BASE_IDX 0
#define regDAGB1_SDP_MISC_AON 0x0259
#define regDAGB1_SDP_MISC_AON_BASE_IDX 0
#define regDAGB1_SDP_MISC 0x025a
#define regDAGB1_SDP_MISC_BASE_IDX 0
#define regDAGB1_SDP_MISC2 0x025b
#define regDAGB1_SDP_MISC2_BASE_IDX 0
#define regDAGB1_SDP_ARB_CNTL0 0x025c
#define regDAGB1_SDP_ARB_CNTL0_BASE_IDX 0
#define regDAGB1_SDP_ARB_CNTL1 0x025d
#define regDAGB1_SDP_ARB_CNTL1_BASE_IDX 0
#define regDAGB1_SDP_CGTT_CLK_CTRL 0x025e
#define regDAGB1_SDP_CGTT_CLK_CTRL_BASE_IDX 0
#define regDAGB1_SDP_LATENCY_SAMPLING 0x025f
#define regDAGB1_SDP_LATENCY_SAMPLING_BASE_IDX 0
// addressBlock: mmhub_pctldec
// base address: 0x69000
#define regPCTL_CTRL 0x0400
#define regPCTL_CTRL_BASE_IDX 0
#define regPCTL_MMHUB_DEEPSLEEP_IB 0x0401
#define regPCTL_MMHUB_DEEPSLEEP_IB_BASE_IDX 0
#define regPCTL_MMHUB_DEEPSLEEP_OVERRIDE 0x0402
#define regPCTL_MMHUB_DEEPSLEEP_OVERRIDE_BASE_IDX 0
#define regPCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB 0x0403
#define regPCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB_BASE_IDX 0
#define regPCTL_PG_IGNORE_DEEPSLEEP 0x0404
#define regPCTL_PG_IGNORE_DEEPSLEEP_BASE_IDX 0
#define regPCTL_PG_IGNORE_DEEPSLEEP_IB 0x0405
#define regPCTL_PG_IGNORE_DEEPSLEEP_IB_BASE_IDX 0
#define regPCTL_UTCL2_MISC 0x0406
#define regPCTL_UTCL2_MISC_BASE_IDX 0
#define regPCTL_SLICE0_CFG_DAGB_WRBUSY 0x0407
#define regPCTL_SLICE0_CFG_DAGB_WRBUSY_BASE_IDX 0
#define regPCTL_SLICE0_CFG_DAGB_RDBUSY 0x0408
#define regPCTL_SLICE0_CFG_DAGB_RDBUSY_BASE_IDX 0
#define regPCTL_SLICE0_CFG_DS_ALLOW 0x0409
#define regPCTL_SLICE0_CFG_DS_ALLOW_BASE_IDX 0
#define regPCTL_SLICE0_CFG_DS_ALLOW_IB 0x040a
#define regPCTL_SLICE0_CFG_DS_ALLOW_IB_BASE_IDX 0
#define regPCTL_SLICE0_MISC 0x040b
#define regPCTL_SLICE0_MISC_BASE_IDX 0
#define regPCTL_SLICE1_CFG_DAGB_WRBUSY 0x040c
#define regPCTL_SLICE1_CFG_DAGB_WRBUSY_BASE_IDX 0
#define regPCTL_SLICE1_CFG_DAGB_RDBUSY 0x040d
#define regPCTL_SLICE1_CFG_DAGB_RDBUSY_BASE_IDX 0
#define regPCTL_SLICE1_CFG_DS_ALLOW 0x040e
#define regPCTL_SLICE1_CFG_DS_ALLOW_BASE_IDX 0
#define regPCTL_SLICE1_CFG_DS_ALLOW_IB 0x040f
#define regPCTL_SLICE1_CFG_DS_ALLOW_IB_BASE_IDX 0
#define regPCTL_SLICE1_MISC 0x0410
#define regPCTL_SLICE1_MISC_BASE_IDX 0
#define regPCTL_RENG_CTRL 0x0416
#define regPCTL_RENG_CTRL_BASE_IDX 0
#define regPCTL_UTCL2_RENG_EXECUTE 0x0417
#define regPCTL_UTCL2_RENG_EXECUTE_BASE_IDX 0
#define regPCTL_UTCL2_RENG_RAM_INDEX 0x0418
#define regPCTL_UTCL2_RENG_RAM_INDEX_BASE_IDX 0
#define regPCTL_UTCL2_RENG_RAM_DATA 0x0419
#define regPCTL_UTCL2_RENG_RAM_DATA_BASE_IDX 0
#define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE0 0x041a
#define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX 0
#define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE1 0x041b
#define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX 0
#define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE2 0x041c
#define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX 0
#define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE3 0x041d
#define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE3_BASE_IDX 0
#define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE4 0x041e
#define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE4_BASE_IDX 0
#define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0 0x041f
#define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0_BASE_IDX 0
#define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1 0x0420
#define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX 0
#define regPCTL_SLICE0_RENG_EXECUTE 0x0421
#define regPCTL_SLICE0_RENG_EXECUTE_BASE_IDX 0
#define regPCTL_SLICE0_RENG_RAM_INDEX 0x0422
#define regPCTL_SLICE0_RENG_RAM_INDEX_BASE_IDX 0
#define regPCTL_SLICE0_RENG_RAM_DATA 0x0423
#define regPCTL_SLICE0_RENG_RAM_DATA_BASE_IDX 0
#define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE0 0x0424
#define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX 0
#define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE1 0x0425
#define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX 0
#define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE2 0x0426
#define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX 0
#define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE3 0x0427
#define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE3_BASE_IDX 0
#define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE4 0x0428
#define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE4_BASE_IDX 0
#define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0 0x0429
#define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0_BASE_IDX 0
#define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1 0x042a
#define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX 0
#define regPCTL_SLICE1_RENG_EXECUTE 0x042b
#define regPCTL_SLICE1_RENG_EXECUTE_BASE_IDX 0
#define regPCTL_SLICE1_RENG_RAM_INDEX 0x042c
#define regPCTL_SLICE1_RENG_RAM_INDEX_BASE_IDX 0
#define regPCTL_SLICE1_RENG_RAM_DATA 0x042d
#define regPCTL_SLICE1_RENG_RAM_DATA_BASE_IDX 0
#define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE0 0x042e
#define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX 0
#define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE1 0x042f
#define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX 0
#define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE2 0x0430
#define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX 0
#define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE3 0x0431
#define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE3_BASE_IDX 0
#define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE4 0x0432
#define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE4_BASE_IDX 0
#define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0 0x0433
#define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0_BASE_IDX 0
#define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1 0x0434
#define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX 0
#define regPCTL_STATUS 0x043f
#define regPCTL_STATUS_BASE_IDX 0
#define regPCTL_PERFCOUNTER_LO 0x0440
#define regPCTL_PERFCOUNTER_LO_BASE_IDX 0
#define regPCTL_PERFCOUNTER_HI 0x0441
#define regPCTL_PERFCOUNTER_HI_BASE_IDX 0
#define regPCTL_PERFCOUNTER0_CFG 0x0442
#define regPCTL_PERFCOUNTER0_CFG_BASE_IDX 0
#define regPCTL_PERFCOUNTER1_CFG 0x0443
#define regPCTL_PERFCOUNTER1_CFG_BASE_IDX 0
#define regPCTL_PERFCOUNTER_RSLT_CNTL 0x0444
#define regPCTL_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0
#define regPCTL_RESERVED_0 0x0445
#define regPCTL_RESERVED_0_BASE_IDX 0
#define regPCTL_RESERVED_1 0x0446
#define regPCTL_RESERVED_1_BASE_IDX 0
#define regPCTL_RESERVED_2 0x0447
#define regPCTL_RESERVED_2_BASE_IDX 0
#define regPCTL_RESERVED_3 0x0448
#define regPCTL_RESERVED_3_BASE_IDX 0
// addressBlock: mmhub_mmutcl2_mmvmsharedpfdec
// base address: 0x69300
#define regMMMC_VM_NB_MMIOBASE 0x04c0
#define regMMMC_VM_NB_MMIOBASE_BASE_IDX 0
#define regMMMC_VM_NB_MMIOLIMIT 0x04c1
#define regMMMC_VM_NB_MMIOLIMIT_BASE_IDX 0
#define regMMMC_VM_NB_PCI_CTRL 0x04c2
#define regMMMC_VM_NB_PCI_CTRL_BASE_IDX 0
#define regMMMC_VM_NB_PCI_ARB 0x04c3
#define regMMMC_VM_NB_PCI_ARB_BASE_IDX 0
#define regMMMC_VM_NB_TOP_OF_DRAM_SLOT1 0x04c4
#define regMMMC_VM_NB_TOP_OF_DRAM_SLOT1_BASE_IDX 0
#define regMMMC_VM_NB_LOWER_TOP_OF_DRAM2 0x04c5
#define regMMMC_VM_NB_LOWER_TOP_OF_DRAM2_BASE_IDX 0
#define regMMMC_VM_NB_UPPER_TOP_OF_DRAM2 0x04c6
#define regMMMC_VM_NB_UPPER_TOP_OF_DRAM2_BASE_IDX 0
#define regMMMC_VM_FB_OFFSET 0x04c7
#define regMMMC_VM_FB_OFFSET_BASE_IDX 0
#define regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB 0x04c8
#define regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_BASE_IDX 0
#define regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB 0x04c9
#define regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_BASE_IDX 0
#define regMMMC_VM_STEERING 0x04ca
#define regMMMC_VM_STEERING_BASE_IDX 0
#define regMMMC_SHARED_VIRT_RESET_REQ 0x04cb
#define regMMMC_SHARED_VIRT_RESET_REQ_BASE_IDX 0
#define regMMMC_VM_CACHEABLE_DRAM_ADDRESS_START 0x04cc
#define regMMMC_VM_CACHEABLE_DRAM_ADDRESS_START_BASE_IDX 0
#define regMMMC_VM_CACHEABLE_DRAM_ADDRESS_END 0x04cd
#define regMMMC_VM_CACHEABLE_DRAM_ADDRESS_END_BASE_IDX 0
#define regMMMC_VM_LOCAL_SYSMEM_ADDRESS_START 0x04ce
#define regMMMC_VM_LOCAL_SYSMEM_ADDRESS_START_BASE_IDX 0
#define regMMMC_VM_LOCAL_SYSMEM_ADDRESS_END 0x04cf
#define regMMMC_VM_LOCAL_SYSMEM_ADDRESS_END_BASE_IDX 0
#define regMMMC_VM_APT_CNTL 0x04d0
#define regMMMC_VM_APT_CNTL_BASE_IDX 0
#define regMMMC_VM_LOCAL_FB_ADDRESS_START 0x04d1
#define regMMMC_VM_LOCAL_FB_ADDRESS_START_BASE_IDX 0
#define regMMMC_VM_LOCAL_FB_ADDRESS_END 0x04d2
#define regMMMC_VM_LOCAL_FB_ADDRESS_END_BASE_IDX 0
#define regMMMC_VM_LOCAL_FB_ADDRESS_LOCK_CNTL 0x04d3
#define regMMMC_VM_LOCAL_FB_ADDRESS_LOCK_CNTL_BASE_IDX 0
#define regMMUTCL2_CGTT_CLK_CTRL 0x04d4
#define regMMUTCL2_CGTT_CLK_CTRL_BASE_IDX 0
#define regMMMC_SHARED_ACTIVE_FCN_ID 0x04d5
#define regMMMC_SHARED_ACTIVE_FCN_ID_BASE_IDX 0
#define regMMUTCL2_CGTT_BUSY_CTRL 0x04d6
#define regMMUTCL2_CGTT_BUSY_CTRL_BASE_IDX 0
#define regMMUTCL2_HARVEST_BYPASS_GROUPS 0x04d7
#define regMMUTCL2_HARVEST_BYPASS_GROUPS_BASE_IDX 0
#define regMMUTCL2_GROUP_RET_FAULT_STATUS 0x04d9
#define regMMUTCL2_GROUP_RET_FAULT_STATUS_BASE_IDX 0
// addressBlock: mmhub_mmutcl2_mmvml2pfdec
// base address: 0x69390
#define regMMVM_L2_CNTL 0x04e4
#define regMMVM_L2_CNTL_BASE_IDX 0
#define regMMVM_L2_CNTL2 0x04e5
#define regMMVM_L2_CNTL2_BASE_IDX 0
#define regMMVM_L2_CNTL3 0x04e6
#define regMMVM_L2_CNTL3_BASE_IDX 0
#define regMMVM_L2_STATUS 0x04e7
#define regMMVM_L2_STATUS_BASE_IDX 0
#define regMMVM_DUMMY_PAGE_FAULT_CNTL 0x04e8
#define regMMVM_DUMMY_PAGE_FAULT_CNTL_BASE_IDX 0
#define regMMVM_DUMMY_PAGE_FAULT_ADDR_LO32 0x04e9
#define regMMVM_DUMMY_PAGE_FAULT_ADDR_LO32_BASE_IDX 0
#define regMMVM_DUMMY_PAGE_FAULT_ADDR_HI32 0x04ea
#define regMMVM_DUMMY_PAGE_FAULT_ADDR_HI32_BASE_IDX 0
#define regMMVM_INVALIDATE_CNTL 0x04eb
#define regMMVM_INVALIDATE_CNTL_BASE_IDX 0
#define regMMVM_L2_PROTECTION_FAULT_CNTL 0x04ec
#define regMMVM_L2_PROTECTION_FAULT_CNTL_BASE_IDX 0
#define regMMVM_L2_PROTECTION_FAULT_CNTL2 0x04ed
#define regMMVM_L2_PROTECTION_FAULT_CNTL2_BASE_IDX 0
#define regMMVM_L2_PROTECTION_FAULT_MM_CNTL3 0x04ee
#define regMMVM_L2_PROTECTION_FAULT_MM_CNTL3_BASE_IDX 0
#define regMMVM_L2_PROTECTION_FAULT_MM_CNTL4 0x04ef
#define regMMVM_L2_PROTECTION_FAULT_MM_CNTL4_BASE_IDX 0
#define regMMVM_L2_PROTECTION_FAULT_STATUS_LO32 0x04f0
#define regMMVM_L2_PROTECTION_FAULT_STATUS_LO32_BASE_IDX 0
#define regMMVM_L2_PROTECTION_FAULT_STATUS_HI32 0x04f1
#define regMMVM_L2_PROTECTION_FAULT_STATUS_HI32_BASE_IDX 0
#define regMMVM_L2_PROTECTION_FAULT_ADDR_LO32 0x04f2
#define regMMVM_L2_PROTECTION_FAULT_ADDR_LO32_BASE_IDX 0
#define regMMVM_L2_PROTECTION_FAULT_ADDR_HI32 0x04f3
#define regMMVM_L2_PROTECTION_FAULT_ADDR_HI32_BASE_IDX 0
#define regMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32 0x04f4
#define regMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32_BASE_IDX 0
#define regMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32 0x04f5
#define regMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32_BASE_IDX 0
#define regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32 0x04f7
#define regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32_BASE_IDX 0
#define regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32 0x04f8
#define regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32_BASE_IDX 0
#define regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32 0x04f9
#define regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32_BASE_IDX 0
#define regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32 0x04fa
#define regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32_BASE_IDX 0
#define regMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32 0x04fb
#define regMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32_BASE_IDX 0
#define regMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32 0x04fc
#define regMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32_BASE_IDX 0
#define regMMVM_L2_CNTL4 0x04fd
#define regMMVM_L2_CNTL4_BASE_IDX 0
#define regMMVM_L2_MM_GROUP_RT_CLASSES 0x04fe
#define regMMVM_L2_MM_GROUP_RT_CLASSES_BASE_IDX 0
#define regMMVM_L2_BANK_SELECT_RESERVED_CID 0x04ff
#define regMMVM_L2_BANK_SELECT_RESERVED_CID_BASE_IDX 0
#define regMMVM_L2_BANK_SELECT_RESERVED_CID2 0x0500
#define regMMVM_L2_BANK_SELECT_RESERVED_CID2_BASE_IDX 0
#define regMMVM_L2_CACHE_PARITY_CNTL 0x0501
#define regMMVM_L2_CACHE_PARITY_CNTL_BASE_IDX 0
#define regMMVM_L2_CGTT_CLK_CTRL 0x0502
#define regMMVM_L2_CGTT_CLK_CTRL_BASE_IDX 0
#define regMMVM_L2_CNTL5 0x0503
#define regMMVM_L2_CNTL5_BASE_IDX 0
#define regMMVM_L2_GCR_CNTL 0x0504
#define regMMVM_L2_GCR_CNTL_BASE_IDX 0
#define regMMVM_L2_CGTT_BUSY_CTRL 0x0505
#define regMMVM_L2_CGTT_BUSY_CTRL_BASE_IDX 0
#define regMMVM_L2_PTE_CACHE_DUMP_CNTL 0x0506
#define regMMVM_L2_PTE_CACHE_DUMP_CNTL_BASE_IDX 0
#define regMMVM_L2_PTE_CACHE_DUMP_READ 0x0507
#define regMMVM_L2_PTE_CACHE_DUMP_READ_BASE_IDX 0
#define regMMVM_L2_BANK_SELECT_MASKS 0x0510
#define regMMVM_L2_BANK_SELECT_MASKS_BASE_IDX 0
#define regMMUTCL2_CREDIT_SAFETY_GROUP_RET_CDC 0x0511
#define regMMUTCL2_CREDIT_SAFETY_GROUP_RET_CDC_BASE_IDX 0
#define regMMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC 0x0512
#define regMMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC_BASE_IDX 0
#define regMMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC 0x0513
#define regMMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC_BASE_IDX 0
#define regMMVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT 0x0514
#define regMMVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT_BASE_IDX 0
#define regMMVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ 0x0515
#define regMMVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ_BASE_IDX 0
// addressBlock: mmhub_mmutcl2_mmvml2prdec
// base address: 0x694d0
#define regMMMC_VM_L2_PERFCOUNTER_LO 0x0534
#define regMMMC_VM_L2_PERFCOUNTER_LO_BASE_IDX 0
#define regMMMC_VM_L2_PERFCOUNTER_HI 0x0535
#define regMMMC_VM_L2_PERFCOUNTER_HI_BASE_IDX 0
#define regMMUTCL2_PERFCOUNTER_LO 0x0536
#define regMMUTCL2_PERFCOUNTER_LO_BASE_IDX 0
#define regMMUTCL2_PERFCOUNTER_HI 0x0537
#define regMMUTCL2_PERFCOUNTER_HI_BASE_IDX 0
// addressBlock: mmhub_mmutcl2_mmvml2pldec
// base address: 0x69510
#define regMMMC_VM_L2_PERFCOUNTER0_CFG 0x0544
#define regMMMC_VM_L2_PERFCOUNTER0_CFG_BASE_IDX 0
#define regMMMC_VM_L2_PERFCOUNTER1_CFG 0x0545
#define regMMMC_VM_L2_PERFCOUNTER1_CFG_BASE_IDX 0
#define regMMMC_VM_L2_PERFCOUNTER2_CFG 0x0546
#define regMMMC_VM_L2_PERFCOUNTER2_CFG_BASE_IDX 0
#define regMMMC_VM_L2_PERFCOUNTER3_CFG 0x0547
#define regMMMC_VM_L2_PERFCOUNTER3_CFG_BASE_IDX 0
#define regMMMC_VM_L2_PERFCOUNTER4_CFG 0x0548
#define regMMMC_VM_L2_PERFCOUNTER4_CFG_BASE_IDX 0
#define regMMMC_VM_L2_PERFCOUNTER5_CFG 0x0549
#define regMMMC_VM_L2_PERFCOUNTER5_CFG_BASE_IDX 0
#define regMMMC_VM_L2_PERFCOUNTER6_CFG 0x054a
#define regMMMC_VM_L2_PERFCOUNTER6_CFG_BASE_IDX 0
#define regMMMC_VM_L2_PERFCOUNTER7_CFG 0x054b
#define regMMMC_VM_L2_PERFCOUNTER7_CFG_BASE_IDX 0
#define regMMMC_VM_L2_PERFCOUNTER_RSLT_CNTL 0x054c
#define regMMMC_VM_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0
#define regMMUTCL2_PERFCOUNTER0_CFG 0x054d
#define regMMUTCL2_PERFCOUNTER0_CFG_BASE_IDX 0
#define regMMUTCL2_PERFCOUNTER1_CFG 0x054e
#define regMMUTCL2_PERFCOUNTER1_CFG_BASE_IDX 0
#define regMMUTCL2_PERFCOUNTER2_CFG 0x054f
#define regMMUTCL2_PERFCOUNTER2_CFG_BASE_IDX 0
#define regMMUTCL2_PERFCOUNTER3_CFG 0x0550
#define regMMUTCL2_PERFCOUNTER3_CFG_BASE_IDX 0
#define regMMUTCL2_PERFCOUNTER_RSLT_CNTL 0x0551
#define regMMUTCL2_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0
// addressBlock: mmhub_mmutcl2_mmvmsharedvcdec
// base address: 0x69550
#define regMMMC_VM_FB_LOCATION_BASE 0x0554
#define regMMMC_VM_FB_LOCATION_BASE_BASE_IDX 0
#define regMMMC_VM_FB_LOCATION_TOP 0x0555
#define regMMMC_VM_FB_LOCATION_TOP_BASE_IDX 0
#define regMMMC_VM_AGP_TOP 0x0556
#define regMMMC_VM_AGP_TOP_BASE_IDX 0
#define regMMMC_VM_AGP_BOT 0x0557
#define regMMMC_VM_AGP_BOT_BASE_IDX 0
#define regMMMC_VM_AGP_BASE 0x0558
#define regMMMC_VM_AGP_BASE_BASE_IDX 0
#define regMMMC_VM_SYSTEM_APERTURE_LOW_ADDR 0x0559
#define regMMMC_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 0
#define regMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x055a
#define regMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 0
#define regMMMC_VM_MX_L1_TLB_CNTL 0x055b
#define regMMMC_VM_MX_L1_TLB_CNTL_BASE_IDX 0
// addressBlock: mmhub_mmutcl2_mmvml2vcdec
// base address: 0x69590
#define regMMVM_CONTEXT0_CNTL 0x0564
#define regMMVM_CONTEXT0_CNTL_BASE_IDX 0
#define regMMVM_CONTEXT1_CNTL 0x0565
#define regMMVM_CONTEXT1_CNTL_BASE_IDX 0
#define regMMVM_CONTEXT2_CNTL 0x0566
#define regMMVM_CONTEXT2_CNTL_BASE_IDX 0
#define regMMVM_CONTEXT3_CNTL 0x0567
#define regMMVM_CONTEXT3_CNTL_BASE_IDX 0
#define regMMVM_CONTEXT4_CNTL 0x0568
#define regMMVM_CONTEXT4_CNTL_BASE_IDX 0
#define regMMVM_CONTEXT5_CNTL 0x0569
#define regMMVM_CONTEXT5_CNTL_BASE_IDX 0
#define regMMVM_CONTEXT6_CNTL 0x056a
#define regMMVM_CONTEXT6_CNTL_BASE_IDX 0
#define regMMVM_CONTEXT7_CNTL 0x056b
#define regMMVM_CONTEXT7_CNTL_BASE_IDX 0
#define regMMVM_CONTEXT8_CNTL 0x056c
#define regMMVM_CONTEXT8_CNTL_BASE_IDX 0
#define regMMVM_CONTEXT9_CNTL 0x056d
#define regMMVM_CONTEXT9_CNTL_BASE_IDX 0
#define regMMVM_CONTEXT10_CNTL 0x056e
#define regMMVM_CONTEXT10_CNTL_BASE_IDX 0
#define regMMVM_CONTEXT11_CNTL 0x056f
#define regMMVM_CONTEXT11_CNTL_BASE_IDX 0
#define regMMVM_CONTEXT12_CNTL 0x0570
#define regMMVM_CONTEXT12_CNTL_BASE_IDX 0
#define regMMVM_CONTEXT13_CNTL 0x0571
#define regMMVM_CONTEXT13_CNTL_BASE_IDX 0
#define regMMVM_CONTEXT14_CNTL 0x0572
#define regMMVM_CONTEXT14_CNTL_BASE_IDX 0
#define regMMVM_CONTEXT15_CNTL 0x0573
#define regMMVM_CONTEXT15_CNTL_BASE_IDX 0
#define regMMVM_CONTEXTS_DISABLE 0x0574
#define regMMVM_CONTEXTS_DISABLE_BASE_IDX 0
#define regMMVM_INVALIDATE_ENG0_SEM 0x0575
#define regMMVM_INVALIDATE_ENG0_SEM_BASE_IDX 0
#define regMMVM_INVALIDATE_ENG1_SEM 0x0576
#define regMMVM_INVALIDATE_ENG1_SEM_BASE_IDX 0
#define regMMVM_INVALIDATE_ENG2_SEM 0x0577
#define regMMVM_INVALIDATE_ENG2_SEM_BASE_IDX 0
#define regMMVM_INVALIDATE_ENG3_SEM 0x0578
#define regMMVM_INVALIDATE_ENG3_SEM_BASE_IDX 0
#define regMMVM_INVALIDATE_ENG4_SEM 0x0579
#define regMMVM_INVALIDATE_ENG4_SEM_BASE_IDX 0
#define regMMVM_INVALIDATE_ENG5_SEM 0x057a
#define regMMVM_INVALIDATE_ENG5_SEM_BASE_IDX 0
#define regMMVM_INVALIDATE_ENG6_SEM 0x057b
#define regMMVM_INVALIDATE_ENG6_SEM_BASE_IDX 0
#define regMMVM_INVALIDATE_ENG7_SEM 0x057c
#define regMMVM_INVALIDATE_ENG7_SEM_BASE_IDX 0
#define regMMVM_INVALIDATE_ENG8_SEM 0x057d
#define regMMVM_INVALIDATE_ENG8_SEM_BASE_IDX 0
#define regMMVM_INVALIDATE_ENG9_SEM 0x057e
#define regMMVM_INVALIDATE_ENG9_SEM_BASE_IDX 0
#define regMMVM_INVALIDATE_ENG10_SEM 0x057f
#define regMMVM_INVALIDATE_ENG10_SEM_BASE_IDX 0
#define regMMVM_INVALIDATE_ENG11_SEM 0x0580
#define regMMVM_INVALIDATE_ENG11_SEM_BASE_IDX 0
#define regMMVM_INVALIDATE_ENG12_SEM 0x0581
#define regMMVM_INVALIDATE_ENG12_SEM_BASE_IDX 0
#define regMMVM_INVALIDATE_ENG13_SEM 0x0582
#define regMMVM_INVALIDATE_ENG13_SEM_BASE_IDX 0
#define regMMVM_INVALIDATE_ENG14_SEM 0x0583
#define regMMVM_INVALIDATE_ENG14_SEM_BASE_IDX 0
#define regMMVM_INVALIDATE_ENG15_SEM 0x0584
#define regMMVM_INVALIDATE_ENG15_SEM_BASE_IDX 0
#define regMMVM_INVALIDATE_ENG16_SEM 0x0585
#define regMMVM_INVALIDATE_ENG16_SEM_BASE_IDX 0
#define regMMVM_INVALIDATE_ENG17_SEM 0x0586
#define regMMVM_INVALIDATE_ENG17_SEM_BASE_IDX 0
#define regMMVM_INVALIDATE_ENG0_REQ 0x0587
#define regMMVM_INVALIDATE_ENG0_REQ_BASE_IDX 0
#define regMMVM_INVALIDATE_ENG1_REQ 0x0588
#define regMMVM_INVALIDATE_ENG1_REQ_BASE_IDX 0
#define regMMVM_INVALIDATE_ENG2_REQ 0x0589
#define regMMVM_INVALIDATE_ENG2_REQ_BASE_IDX 0
#define regMMVM_INVALIDATE_ENG3_REQ 0x058a
#define regMMVM_INVALIDATE_ENG3_REQ_BASE_IDX 0
#define regMMVM_INVALIDATE_ENG4_REQ 0x058b
#define regMMVM_INVALIDATE_ENG4_REQ_BASE_IDX 0
#define regMMVM_INVALIDATE_ENG5_REQ 0x058c
#define regMMVM_INVALIDATE_ENG5_REQ_BASE_IDX 0
#define regMMVM_INVALIDATE_ENG6_REQ 0x058d
#define regMMVM_INVALIDATE_ENG6_REQ_BASE_IDX 0
#define regMMVM_INVALIDATE_ENG7_REQ 0x058e
#define regMMVM_INVALIDATE_ENG7_REQ_BASE_IDX 0
#define regMMVM_INVALIDATE_ENG8_REQ 0x058f
#define regMMVM_INVALIDATE_ENG8_REQ_BASE_IDX 0
#define regMMVM_INVALIDATE_ENG9_REQ 0x0590
#define regMMVM_INVALIDATE_ENG9_REQ_BASE_IDX 0
#define regMMVM_INVALIDATE_ENG10_REQ 0x0591
#define regMMVM_INVALIDATE_ENG10_REQ_BASE_IDX 0
#define regMMVM_INVALIDATE_ENG11_REQ 0x0592
#define regMMVM_INVALIDATE_ENG11_REQ_BASE_IDX 0
#define regMMVM_INVALIDATE_ENG12_REQ 0x0593
#define regMMVM_INVALIDATE_ENG12_REQ_BASE_IDX 0
#define regMMVM_INVALIDATE_ENG13_REQ 0x0594
#define regMMVM_INVALIDATE_ENG13_REQ_BASE_IDX 0
#define regMMVM_INVALIDATE_ENG14_REQ 0x0595
#define regMMVM_INVALIDATE_ENG14_REQ_BASE_IDX 0
#define regMMVM_INVALIDATE_ENG15_REQ 0x0596
#define regMMVM_INVALIDATE_ENG15_REQ_BASE_IDX 0
#define regMMVM_INVALIDATE_ENG16_REQ 0x0597
#define regMMVM_INVALIDATE_ENG16_REQ_BASE_IDX 0
#define regMMVM_INVALIDATE_ENG17_REQ 0x0598
#define regMMVM_INVALIDATE_ENG17_REQ_BASE_IDX 0
#define regMMVM_INVALIDATE_ENG0_ACK 0x0599
#define regMMVM_INVALIDATE_ENG0_ACK_BASE_IDX 0
#define regMMVM_INVALIDATE_ENG1_ACK 0x059a
#define regMMVM_INVALIDATE_ENG1_ACK_BASE_IDX 0
#define regMMVM_INVALIDATE_ENG2_ACK 0x059b
#define regMMVM_INVALIDATE_ENG2_ACK_BASE_IDX 0
#define regMMVM_INVALIDATE_ENG3_ACK 0x059c
#define regMMVM_INVALIDATE_ENG3_ACK_BASE_IDX 0
#define regMMVM_INVALIDATE_ENG4_ACK 0x059d
#define regMMVM_INVALIDATE_ENG4_ACK_BASE_IDX 0
#define regMMVM_INVALIDATE_ENG5_ACK 0x059e
#define regMMVM_INVALIDATE_ENG5_ACK_BASE_IDX 0
#define regMMVM_INVALIDATE_ENG6_ACK 0x059f
#define regMMVM_INVALIDATE_ENG6_ACK_BASE_IDX 0
#define regMMVM_INVALIDATE_ENG7_ACK 0x05a0
#define regMMVM_INVALIDATE_ENG7_ACK_BASE_IDX 0
#define regMMVM_INVALIDATE_ENG8_ACK 0x05a1
#define regMMVM_INVALIDATE_ENG8_ACK_BASE_IDX 0
#define regMMVM_INVALIDATE_ENG9_ACK 0x05a2
#define regMMVM_INVALIDATE_ENG9_ACK_BASE_IDX 0
#define regMMVM_INVALIDATE_ENG10_ACK 0x05a3
#define regMMVM_INVALIDATE_ENG10_ACK_BASE_IDX 0
#define regMMVM_INVALIDATE_ENG11_ACK 0x05a4
#define regMMVM_INVALIDATE_ENG11_ACK_BASE_IDX 0
#define regMMVM_INVALIDATE_ENG12_ACK 0x05a5
#define regMMVM_INVALIDATE_ENG12_ACK_BASE_IDX 0
#define regMMVM_INVALIDATE_ENG13_ACK 0x05a6
#define regMMVM_INVALIDATE_ENG13_ACK_BASE_IDX 0
#define regMMVM_INVALIDATE_ENG14_ACK 0x05a7
#define regMMVM_INVALIDATE_ENG14_ACK_BASE_IDX 0
#define regMMVM_INVALIDATE_ENG15_ACK 0x05a8
#define regMMVM_INVALIDATE_ENG15_ACK_BASE_IDX 0
#define regMMVM_INVALIDATE_ENG16_ACK 0x05a9
#define regMMVM_INVALIDATE_ENG16_ACK_BASE_IDX 0
#define regMMVM_INVALIDATE_ENG17_ACK 0x05aa
#define regMMVM_INVALIDATE_ENG17_ACK_BASE_IDX 0
#define regMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32 0x05ab
#define regMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32_BASE_IDX 0
#define regMMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32 0x05ac
#define regMMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32_BASE_IDX 0
#define regMMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 0x05ad
#define regMMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32_BASE_IDX 0
#define regMMVM_INVALIDATE_ENG1_ADDR_RANGE_HI32 0x05ae
#define regMMVM_INVALIDATE_ENG1_ADDR_RANGE_HI32_BASE_IDX 0
#define regMMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32 0x05af
#define regMMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32_BASE_IDX 0
#define regMMVM_INVALIDATE_ENG2_ADDR_RANGE_HI32 0x05b0
#define regMMVM_INVALIDATE_ENG2_ADDR_RANGE_HI32_BASE_IDX 0
#define regMMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32 0x05b1
#define regMMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32_BASE_IDX 0
#define regMMVM_INVALIDATE_ENG3_ADDR_RANGE_HI32 0x05b2
#define regMMVM_INVALIDATE_ENG3_ADDR_RANGE_HI32_BASE_IDX 0
#define regMMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32 0x05b3
#define regMMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32_BASE_IDX 0
#define regMMVM_INVALIDATE_ENG4_ADDR_RANGE_HI32 0x05b4
#define regMMVM_INVALIDATE_ENG4_ADDR_RANGE_HI32_BASE_IDX 0
#define regMMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32 0x05b5
#define regMMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32_BASE_IDX 0
#define regMMVM_INVALIDATE_ENG5_ADDR_RANGE_HI32 0x05b6
#define regMMVM_INVALIDATE_ENG5_ADDR_RANGE_HI32_BASE_IDX 0
#define regMMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32 0x05b7
#define regMMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32_BASE_IDX 0
#define regMMVM_INVALIDATE_ENG6_ADDR_RANGE_HI32 0x05b8
#define regMMVM_INVALIDATE_ENG6_ADDR_RANGE_HI32_BASE_IDX 0
#define regMMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32 0x05b9
#define regMMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32_BASE_IDX 0
#define regMMVM_INVALIDATE_ENG7_ADDR_RANGE_HI32 0x05ba
#define regMMVM_INVALIDATE_ENG7_ADDR_RANGE_HI32_BASE_IDX 0
#define regMMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32 0x05bb
#define regMMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32_BASE_IDX 0
#define regMMVM_INVALIDATE_ENG8_ADDR_RANGE_HI32 0x05bc
#define regMMVM_INVALIDATE_ENG8_ADDR_RANGE_HI32_BASE_IDX 0
#define regMMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32 0x05bd
#define regMMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32_BASE_IDX 0
#define regMMVM_INVALIDATE_ENG9_ADDR_RANGE_HI32 0x05be
#define regMMVM_INVALIDATE_ENG9_ADDR_RANGE_HI32_BASE_IDX 0
#define regMMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32 0x05bf
#define regMMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32_BASE_IDX 0
#define regMMVM_INVALIDATE_ENG10_ADDR_RANGE_HI32 0x05c0
#define regMMVM_INVALIDATE_ENG10_ADDR_RANGE_HI32_BASE_IDX 0
#define regMMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32 0x05c1
#define regMMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32_BASE_IDX 0
#define regMMVM_INVALIDATE_ENG11_ADDR_RANGE_HI32 0x05c2
#define regMMVM_INVALIDATE_ENG11_ADDR_RANGE_HI32_BASE_IDX 0
#define regMMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32 0x05c3
#define regMMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32_BASE_IDX 0
#define regMMVM_INVALIDATE_ENG12_ADDR_RANGE_HI32 0x05c4
#define regMMVM_INVALIDATE_ENG12_ADDR_RANGE_HI32_BASE_IDX 0
#define regMMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32 0x05c5
#define regMMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32_BASE_IDX 0
#define regMMVM_INVALIDATE_ENG13_ADDR_RANGE_HI32 0x05c6
#define regMMVM_INVALIDATE_ENG13_ADDR_RANGE_HI32_BASE_IDX 0
#define regMMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32 0x05c7
#define regMMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32_BASE_IDX 0
#define regMMVM_INVALIDATE_ENG14_ADDR_RANGE_HI32 0x05c8
#define regMMVM_INVALIDATE_ENG14_ADDR_RANGE_HI32_BASE_IDX 0
#define regMMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32 0x05c9
#define regMMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32_BASE_IDX 0
#define regMMVM_INVALIDATE_ENG15_ADDR_RANGE_HI32 0x05ca
#define regMMVM_INVALIDATE_ENG15_ADDR_RANGE_HI32_BASE_IDX 0
#define regMMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32 0x05cb
#define regMMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32_BASE_IDX 0
#define regMMVM_INVALIDATE_ENG16_ADDR_RANGE_HI32 0x05cc
#define regMMVM_INVALIDATE_ENG16_ADDR_RANGE_HI32_BASE_IDX 0
#define regMMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32 0x05cd
#define regMMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32_BASE_IDX 0
#define regMMVM_INVALIDATE_ENG17_ADDR_RANGE_HI32 0x05ce
#define regMMVM_INVALIDATE_ENG17_ADDR_RANGE_HI32_BASE_IDX 0
#define regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 0x05cf
#define regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
#define regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 0x05d0
#define regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
#define regMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 0x05d1
#define regMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
#define regMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 0x05d2
#define regMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
#define regMMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 0x05d3
#define regMMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
#define regMMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 0x05d4
#define regMMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
#define regMMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 0x05d5
#define regMMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
#define regMMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 0x05d6
#define regMMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
#define regMMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 0x05d7
#define regMMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
#define regMMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 0x05d8
#define regMMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
#define regMMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 0x05d9
#define regMMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
#define regMMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 0x05da
#define regMMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
#define regMMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 0x05db
#define regMMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
#define regMMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 0x05dc
#define regMMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
#define regMMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 0x05dd
#define regMMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
#define regMMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 0x05de
#define regMMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
#define regMMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 0x05df
#define regMMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
#define regMMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 0x05e0
#define regMMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
#define regMMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 0x05e1
#define regMMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
#define regMMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 0x05e2
#define regMMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
#define regMMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 0x05e3
#define regMMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
#define regMMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 0x05e4
#define regMMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
#define regMMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 0x05e5
#define regMMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
#define regMMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 0x05e6
#define regMMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
#define regMMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 0x05e7
#define regMMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
#define regMMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 0x05e8
#define regMMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
#define regMMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 0x05e9
#define regMMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
#define regMMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 0x05ea
#define regMMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
#define regMMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 0x05eb
#define regMMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
#define regMMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 0x05ec
#define regMMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
#define regMMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 0x05ed
#define regMMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
#define regMMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 0x05ee
#define regMMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
#define regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 0x05ef
#define regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
#define regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 0x05f0
#define regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
#define regMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 0x05f1
#define regMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
#define regMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 0x05f2
#define regMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
#define regMMVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 0x05f3
#define regMMVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
#define regMMVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 0x05f4
#define regMMVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
#define regMMVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 0x05f5
#define regMMVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
#define regMMVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 0x05f6
#define regMMVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
#define regMMVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 0x05f7
#define regMMVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
#define regMMVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 0x05f8
#define regMMVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
#define regMMVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 0x05f9
#define regMMVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
#define regMMVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 0x05fa
#define regMMVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
#define regMMVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 0x05fb
#define regMMVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
#define regMMVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 0x05fc
#define regMMVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
#define regMMVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 0x05fd
#define regMMVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
#define regMMVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 0x05fe
#define regMMVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
#define regMMVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 0x05ff
#define regMMVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
#define regMMVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 0x0600
#define regMMVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
#define regMMVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 0x0601
#define regMMVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
#define regMMVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 0x0602
#define regMMVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
#define regMMVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 0x0603
#define regMMVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
#define regMMVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 0x0604
#define regMMVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
#define regMMVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 0x0605
#define regMMVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
#define regMMVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 0x0606
#define regMMVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
#define regMMVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 0x0607
#define regMMVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
#define regMMVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 0x0608
#define regMMVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
#define regMMVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 0x0609
#define regMMVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
#define regMMVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 0x060a
#define regMMVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
#define regMMVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 0x060b
#define regMMVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
#define regMMVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 0x060c
#define regMMVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
#define regMMVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 0x060d
#define regMMVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
#define regMMVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 0x060e
#define regMMVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
#define regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 0x060f
#define regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
#define regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 0x0610
#define regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
#define regMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 0x0611
#define regMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
#define regMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 0x0612
#define regMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
#define regMMVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 0x0613
#define regMMVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
#define regMMVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 0x0614
#define regMMVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
#define regMMVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 0x0615
#define regMMVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
#define regMMVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 0x0616
#define regMMVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
#define regMMVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 0x0617
#define regMMVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
#define regMMVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 0x0618
#define regMMVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
#define regMMVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 0x0619
#define regMMVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
#define regMMVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 0x061a
#define regMMVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
#define regMMVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 0x061b
#define regMMVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
#define regMMVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 0x061c
#define regMMVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
#define regMMVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 0x061d
#define regMMVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
#define regMMVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 0x061e
#define regMMVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
#define regMMVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 0x061f
#define regMMVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
#define regMMVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 0x0620
#define regMMVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
#define regMMVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 0x0621
#define regMMVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
#define regMMVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 0x0622
#define regMMVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
#define regMMVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 0x0623
#define regMMVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
#define regMMVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 0x0624
#define regMMVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
#define regMMVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 0x0625
#define regMMVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
#define regMMVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 0x0626
#define regMMVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
#define regMMVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 0x0627
#define regMMVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
#define regMMVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 0x0628
#define regMMVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
#define regMMVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 0x0629
#define regMMVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
#define regMMVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 0x062a
#define regMMVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
#define regMMVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 0x062b
#define regMMVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
#define regMMVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 0x062c
#define regMMVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
#define regMMVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 0x062d
#define regMMVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
#define regMMVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 0x062e
#define regMMVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
#define regMMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x062f
#define regMMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0
#define regMMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x0630
#define regMMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0
#define regMMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x0631
#define regMMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0
#define regMMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x0632
#define regMMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0
#define regMMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x0633
#define regMMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0
#define regMMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x0634
#define regMMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0
#define regMMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x0635
#define regMMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0
#define regMMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x0636
#define regMMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0
#define regMMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x0637
#define regMMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0
#define regMMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x0638
#define regMMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0
#define regMMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x0639
#define regMMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0
#define regMMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x063a
#define regMMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0
#define regMMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x063b
#define regMMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0
#define regMMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x063c
#define regMMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0
#define regMMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x063d
#define regMMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0
#define regMMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x063e
#define regMMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0
#define regMMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x063f
#define regMMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0
// addressBlock: mmhub_mmutcl2_mmvml2pspdec
// base address: 0x69b10
#define regMMUTCL2_TRANSLATION_BYPASS_BY_VMID 0x06c4
#define regMMUTCL2_TRANSLATION_BYPASS_BY_VMID_BASE_IDX 0
#define regMMVM_IOMMU_GPU_HOST_TRANSLATION_ENABLE 0x06c6
#define regMMVM_IOMMU_GPU_HOST_TRANSLATION_ENABLE_BASE_IDX 0
#define regMMUTC_GPUVA_VMID_TRANSLATION_ASSIST_CNTL 0x06c7
#define regMMUTC_GPUVA_VMID_TRANSLATION_ASSIST_CNTL_BASE_IDX 0
#define regMMVM_IOMMU_CONTROL_REGISTER 0x06c8
#define regMMVM_IOMMU_CONTROL_REGISTER_BASE_IDX 0
#define regMMVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER 0x06c9
#define regMMVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER_BASE_IDX 0
#define regMMUTC_TRANSLATION_FAULT_CNTL0 0x06ca
#define regMMUTC_TRANSLATION_FAULT_CNTL0_BASE_IDX 0
#define regMMUTC_TRANSLATION_FAULT_CNTL1 0x06cb
#define regMMUTC_TRANSLATION_FAULT_CNTL1_BASE_IDX 0
#define regMMUTCL2_VSCH_POWER_STATUS 0x06cc
#define regMMUTCL2_VSCH_POWER_STATUS_BASE_IDX 0
#endif
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