/*
* Copyright (C) 2017 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef _dcn_1_0_OFFSET_HEADER
#define _dcn_1_0_OFFSET_HEADER
// addressBlock: dce_dc_hda_azcontroller_azdec
// base address: 0x1300000
// addressBlock: dce_dc_hda_azendpoint_azdec
// base address: 0x1300000
// addressBlock: dce_dc_hda_azinputendpoint_azdec
// base address: 0x1300000
// addressBlock: dce_dc_hda_azroot_azdec
// base address: 0x1300000
// addressBlock: dce_dc_hda_azstream0_azdec
// base address: 0x1300000
// addressBlock: dce_dc_hda_azstream1_azdec
// base address: 0x1300020
// addressBlock: dce_dc_hda_azstream2_azdec
// base address: 0x1300040
// addressBlock: dce_dc_hda_azstream3_azdec
// base address: 0x1300060
// addressBlock: dce_dc_hda_azstream4_azdec
// base address: 0x1300080
// addressBlock: dce_dc_hda_azstream5_azdec
// base address: 0x13000a0
// addressBlock: dce_dc_hda_azstream6_azdec
// base address: 0x13000c0
// addressBlock: dce_dc_hda_azstream7_azdec
// base address: 0x13000e0
// addressBlock: dce_dc_mmhubbub_vga_dispdec[72..76]
// base address: 0x48
#define mmVGA_MEM_WRITE_PAGE_ADDR 0x0000
#define mmVGA_MEM_WRITE_PAGE_ADDR_BASE_IDX 0
#define mmVGA_MEM_READ_PAGE_ADDR 0x0001
#define mmVGA_MEM_READ_PAGE_ADDR_BASE_IDX 0
// addressBlock: dce_dc_mmhubbub_vga_dispdec[948..986]
// base address: 0x3b4
#define mmCRTC8_IDX 0x002d
#define mmCRTC8_IDX_BASE_IDX 1
#define mmCRTC8_DATA 0x002d
#define mmCRTC8_DATA_BASE_IDX 1
#define mmGENFC_WT 0x002e
#define mmGENFC_WT_BASE_IDX 1
#define mmGENS1 0x002e
#define mmGENS1_BASE_IDX 1
#define mmATTRDW 0x0030
#define mmATTRDW_BASE_IDX 1
#define mmATTRX 0x0030
#define mmATTRX_BASE_IDX 1
#define mmATTRDR 0x0030
#define mmATTRDR_BASE_IDX 1
#define mmGENMO_WT 0x0030
#define mmGENMO_WT_BASE_IDX 1
#define mmGENS0 0x0030
#define mmGENS0_BASE_IDX 1
#define mmGENENB 0x0030
#define mmGENENB_BASE_IDX 1
#define mmSEQ8_IDX 0x0031
#define mmSEQ8_IDX_BASE_IDX 1
#define mmSEQ8_DATA 0x0031
#define mmSEQ8_DATA_BASE_IDX 1
#define mmDAC_MASK 0x0031
#define mmDAC_MASK_BASE_IDX 1
#define mmDAC_R_INDEX 0x0031
#define mmDAC_R_INDEX_BASE_IDX 1
#define mmDAC_W_INDEX 0x0032
#define mmDAC_W_INDEX_BASE_IDX 1
#define mmDAC_DATA 0x0032
#define mmDAC_DATA_BASE_IDX 1
#define mmGENFC_RD 0x0032
#define mmGENFC_RD_BASE_IDX 1
#define mmGENMO_RD 0x0033
#define mmGENMO_RD_BASE_IDX 1
#define mmGRPH8_IDX 0x0033
#define mmGRPH8_IDX_BASE_IDX 1
#define mmGRPH8_DATA 0x0033
#define mmGRPH8_DATA_BASE_IDX 1
#define mmCRTC8_IDX_1 0x0035
#define mmCRTC8_IDX_1_BASE_IDX 1
#define mmCRTC8_DATA_1 0x0035
#define mmCRTC8_DATA_1_BASE_IDX 1
#define mmGENFC_WT_1 0x0036
#define mmGENFC_WT_1_BASE_IDX 1
#define mmGENS1_1 0x0036
#define mmGENS1_1_BASE_IDX 1
// addressBlock: dce_dc_hda_azcontroller_azdec
// base address: 0x0
#define mmCORB_WRITE_POINTER 0x0000
#define mmCORB_WRITE_POINTER_BASE_IDX 0
#define mmCORB_READ_POINTER 0x0000
#define mmCORB_READ_POINTER_BASE_IDX 0
#define mmCORB_CONTROL 0x0001
#define mmCORB_CONTROL_BASE_IDX 0
#define mmCORB_STATUS 0x0001
#define mmCORB_STATUS_BASE_IDX 0
#define mmCORB_SIZE 0x0001
#define mmCORB_SIZE_BASE_IDX 0
#define mmRIRB_LOWER_BASE_ADDRESS 0x0002
#define mmRIRB_LOWER_BASE_ADDRESS_BASE_IDX 0
#define mmRIRB_UPPER_BASE_ADDRESS 0x0003
#define mmRIRB_UPPER_BASE_ADDRESS_BASE_IDX 0
#define mmRIRB_WRITE_POINTER 0x0004
#define mmRIRB_WRITE_POINTER_BASE_IDX 0
#define mmRESPONSE_INTERRUPT_COUNT 0x0004
#define mmRESPONSE_INTERRUPT_COUNT_BASE_IDX 0
#define mmRIRB_CONTROL 0x0005
#define mmRIRB_CONTROL_BASE_IDX 0
#define mmRIRB_STATUS 0x0005
#define mmRIRB_STATUS_BASE_IDX 0
#define mmRIRB_SIZE 0x0005
#define mmRIRB_SIZE_BASE_IDX 0
#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE 0x0006
#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_BASE_IDX 0
#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x0006
#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX 0
#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x0006
#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX 0
#define mmIMMEDIATE_RESPONSE_INPUT_INTERFACE 0x0007
#define mmIMMEDIATE_RESPONSE_INPUT_INTERFACE_BASE_IDX 0
#define mmIMMEDIATE_COMMAND_STATUS 0x0008
#define mmIMMEDIATE_COMMAND_STATUS_BASE_IDX 0
#define mmDMA_POSITION_LOWER_BASE_ADDRESS 0x000a
#define mmDMA_POSITION_LOWER_BASE_ADDRESS_BASE_IDX 0
#define mmDMA_POSITION_UPPER_BASE_ADDRESS 0x000b
#define mmDMA_POSITION_UPPER_BASE_ADDRESS_BASE_IDX 0
#define mmWALL_CLOCK_COUNTER_ALIAS 0x074c
#define mmWALL_CLOCK_COUNTER_ALIAS_BASE_IDX 1
// addressBlock: dce_dc_hda_azendpoint_azdec
// base address: 0x0
#define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x0006
#define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX 0
#define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x0006
#define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX 0
// addressBlock: dce_dc_hda_azinputendpoint_azdec
// base address: 0x0
#define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA 0x0006
#define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA_BASE_IDX 0
#define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX 0x0006
#define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX_BASE_IDX 0
// addressBlock: dce_dc_hda_azroot_azdec
// base address: 0x0
#define mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x0006
#define mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX 0
#define mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x0006
#define mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX 0
// addressBlock: dce_dc_hda_azstream0_azdec
// base address: 0x0
#define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x000e
#define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0
#define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x000f
#define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0
#define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0010
#define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0
#define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0011
#define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0
#define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x0012
#define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0
#define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x0012
#define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0
#define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x0014
#define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0
#define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x0015
#define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0
#define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0761
#define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1
// addressBlock: dce_dc_hda_azstream1_azdec
// base address: 0x20
#define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x0016
#define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0
#define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x0017
#define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0
#define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0018
#define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0
#define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0019
#define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0
#define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x001a
#define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0
#define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x001a
#define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0
#define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x001c
#define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0
#define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x001d
#define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0
#define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0769
#define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1
// addressBlock: dce_dc_hda_azstream2_azdec
// base address: 0x40
#define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x001e
#define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0
#define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x001f
#define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0
#define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0020
#define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0
#define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0021
#define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0
#define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x0022
#define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0
#define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x0022
#define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0
#define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x0024
#define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0
#define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x0025
#define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0
#define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0771
#define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1
// addressBlock: dce_dc_hda_azstream3_azdec
// base address: 0x60
#define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x0026
#define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0
#define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x0027
#define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0
#define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0028
#define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0
#define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0029
#define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0
#define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x002a
#define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0
#define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x002a
#define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0
#define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x002c
#define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0
#define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x002d
#define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0
#define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0779
#define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1
// addressBlock: dce_dc_hda_azstream4_azdec
// base address: 0x80
#define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x002e
#define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0
#define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x002f
#define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0
#define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0030
#define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0
#define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0031
#define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0
#define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x0032
#define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0
#define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x0032
#define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0
#define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x0034
#define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0
#define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x0035
#define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0
#define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0781
#define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1
// addressBlock: dce_dc_hda_azstream5_azdec
// base address: 0xa0
#define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x0036
#define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0
#define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x0037
#define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0
#define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0038
#define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0
#define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0039
#define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0
#define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x003a
#define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0
#define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x003a
#define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0
#define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x003c
#define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0
#define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x003d
#define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0
#define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0789
#define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1
// addressBlock: dce_dc_hda_azstream6_azdec
// base address: 0xc0
#define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x003e
#define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0
#define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x003f
#define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0
#define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0040
#define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0
#define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0041
#define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0
#define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x0042
#define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0
#define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x0042
#define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0
#define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x0044
#define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0
#define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x0045
#define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0
#define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0791
#define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1
// addressBlock: dce_dc_hda_azstream7_azdec
// base address: 0xe0
#define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x0046
#define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0
#define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x0047
#define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0
#define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0048
#define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0
#define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0049
#define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0
#define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x004a
#define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0
#define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x004a
#define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0
#define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x004c
#define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0
#define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x004d
#define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0
#define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0799
#define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1
// addressBlock: dce_dc_mmhubbub_vga_dispdec[72..76]
// base address: 0x48
//#define mmVGA_VGA_MEM_WRITE_PAGE_ADDR 0x0000
//#define mmVGA_VGA_MEM_READ_PAGE_ADDR 0x0001
// addressBlock: dce_dc_mmhubbub_vga_dispdec
// base address: 0x0
//#define mmVGA_VGA_MEM_WRITE_PAGE_ADDR 0x0000
//#define mmVGA_VGA_MEM_READ_PAGE_ADDR 0x0001
#define mmVGA_RENDER_CONTROL 0x0000
#define mmVGA_RENDER_CONTROL_BASE_IDX 1
#define mmVGA_SEQUENCER_RESET_CONTROL 0x0001
#define mmVGA_SEQUENCER_RESET_CONTROL_BASE_IDX 1
#define mmVGA_MODE_CONTROL 0x0002
#define mmVGA_MODE_CONTROL_BASE_IDX 1
#define mmVGA_SURFACE_PITCH_SELECT 0x0003
#define mmVGA_SURFACE_PITCH_SELECT_BASE_IDX 1
#define mmVGA_MEMORY_BASE_ADDRESS 0x0004
#define mmVGA_MEMORY_BASE_ADDRESS_BASE_IDX 1
#define mmVGA_DISPBUF1_SURFACE_ADDR 0x0006
#define mmVGA_DISPBUF1_SURFACE_ADDR_BASE_IDX 1
#define mmVGA_DISPBUF2_SURFACE_ADDR 0x0008
#define mmVGA_DISPBUF2_SURFACE_ADDR_BASE_IDX 1
#define mmVGA_MEMORY_BASE_ADDRESS_HIGH 0x0009
#define mmVGA_MEMORY_BASE_ADDRESS_HIGH_BASE_IDX 1
#define mmVGA_HDP_CONTROL 0x000a
#define mmVGA_HDP_CONTROL_BASE_IDX 1
#define mmVGA_CACHE_CONTROL 0x000b
#define mmVGA_CACHE_CONTROL_BASE_IDX 1
#define mmD1VGA_CONTROL 0x000c
#define mmD1VGA_CONTROL_BASE_IDX 1
#define mmD2VGA_CONTROL 0x000e
#define mmD2VGA_CONTROL_BASE_IDX 1
#define mmVGA_STATUS 0x0010
#define mmVGA_STATUS_BASE_IDX 1
#define mmVGA_INTERRUPT_CONTROL 0x0011
#define mmVGA_INTERRUPT_CONTROL_BASE_IDX 1
#define mmVGA_STATUS_CLEAR 0x0012
#define mmVGA_STATUS_CLEAR_BASE_IDX 1
#define mmVGA_INTERRUPT_STATUS 0x0013
#define mmVGA_INTERRUPT_STATUS_BASE_IDX 1
#define mmVGA_MAIN_CONTROL 0x0014
#define mmVGA_MAIN_CONTROL_BASE_IDX 1
#define mmVGA_TEST_CONTROL 0x0015
#define mmVGA_TEST_CONTROL_BASE_IDX 1
#define mmVGA_QOS_CTRL 0x0018
#define mmVGA_QOS_CTRL_BASE_IDX 1
//#define mmVGA_CRTC8_IDX 0x002d
//#define mmVGA_CRTC8_DATA 0x002d
//#define mmVGA_GENFC_WT 0x002e
//#define mmVGA_GENS1 0x002e
//#define mmVGA_ATTRDW 0x0030
//#define mmVGA_ATTRX 0x0030
//#define mmVGA_ATTRDR 0x0030
//#define mmVGA_GENMO_WT 0x0030
//#define mmVGA_GENS0 0x0030
//#define mmVGA_GENENB 0x0030
//#define mmVGA_SEQ8_IDX 0x0031
//#define mmVGA_SEQ8_DATA 0x0031
//#define mmVGA_DAC_MASK 0x0031
//#define mmVGA_DAC_R_INDEX 0x0031
//#define mmVGA_DAC_W_INDEX 0x0032
//#define mmVGA_DAC_DATA 0x0032
//#define mmVGA_GENFC_RD 0x0032
//#define mmVGA_GENMO_RD 0x0033
//#define mmVGA_GRPH8_IDX 0x0033
//#define mmVGA_GRPH8_DATA 0x0033
//#define mmVGA_CRTC8_IDX_1 0x0035
//#define mmVGA_CRTC8_DATA_1 0x0035
//#define mmVGA_GENFC_WT_1 0x0036
//#define mmVGA_GENS1_1 0x0036
#define mmD3VGA_CONTROL 0x0038
#define mmD3VGA_CONTROL_BASE_IDX 1
#define mmD4VGA_CONTROL 0x0039
#define mmD4VGA_CONTROL_BASE_IDX 1
#define mmD5VGA_CONTROL 0x003a
#define mmD5VGA_CONTROL_BASE_IDX 1
#define mmD6VGA_CONTROL 0x003b
#define mmD6VGA_CONTROL_BASE_IDX 1
#define mmVGA_SOURCE_SELECT 0x003c
#define mmVGA_SOURCE_SELECT_BASE_IDX 1
// addressBlock: dce_dc_dccg_dccg_dispdec
// base address: 0x0
#define mmPHYPLLA_PIXCLK_RESYNC_CNTL 0x0040
#define mmPHYPLLA_PIXCLK_RESYNC_CNTL_BASE_IDX 1
#define mmPHYPLLB_PIXCLK_RESYNC_CNTL 0x0041
#define mmPHYPLLB_PIXCLK_RESYNC_CNTL_BASE_IDX 1
#define mmPHYPLLC_PIXCLK_RESYNC_CNTL 0x0042
#define mmPHYPLLC_PIXCLK_RESYNC_CNTL_BASE_IDX 1
#define mmPHYPLLD_PIXCLK_RESYNC_CNTL 0x0043
#define mmPHYPLLD_PIXCLK_RESYNC_CNTL_BASE_IDX 1
#define mmDP_DTO_DBUF_EN 0x0044
#define mmDP_DTO_DBUF_EN_BASE_IDX 1
#define mmDPREFCLK_CGTT_BLK_CTRL_REG 0x0048
#define mmDPREFCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1
#define mmREFCLK_CNTL 0x0049
#define mmREFCLK_CNTL_BASE_IDX 1
#define mmMIPI_CLK_CNTL 0x004a
#define mmMIPI_CLK_CNTL_BASE_IDX 1
#define mmREFCLK_CGTT_BLK_CTRL_REG 0x004b
#define mmREFCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1
#define mmPHYPLLE_PIXCLK_RESYNC_CNTL 0x004c
#define mmPHYPLLE_PIXCLK_RESYNC_CNTL_BASE_IDX 1
#define mmDCCG_PERFMON_CNTL2 0x004e
#define mmDCCG_PERFMON_CNTL2_BASE_IDX 1
#define mmDSICLK_CGTT_BLK_CTRL_REG 0x004f
#define mmDSICLK_CGTT_BLK_CTRL_REG_BASE_IDX 1
#define mmDCCG_CBUS_WRCMD_DELAY 0x0050
#define mmDCCG_CBUS_WRCMD_DELAY_BASE_IDX 1
#define mmDCCG_DS_DTO_INCR 0x0053
#define mmDCCG_DS_DTO_INCR_BASE_IDX 1
#define mmDCCG_DS_DTO_MODULO 0x0054
#define mmDCCG_DS_DTO_MODULO_BASE_IDX 1
#define mmDCCG_DS_CNTL 0x0055
#define mmDCCG_DS_CNTL_BASE_IDX 1
#define mmDCCG_DS_HW_CAL_INTERVAL 0x0056
#define mmDCCG_DS_HW_CAL_INTERVAL_BASE_IDX 1
#define mmSYMCLKG_CLOCK_ENABLE 0x0057
#define mmSYMCLKG_CLOCK_ENABLE_BASE_IDX 1
#define mmDPREFCLK_CNTL 0x0058
#define mmDPREFCLK_CNTL_BASE_IDX 1
#define mmAOMCLK0_CNTL 0x0059
#define mmAOMCLK0_CNTL_BASE_IDX 1
#define mmAOMCLK1_CNTL 0x005a
#define mmAOMCLK1_CNTL_BASE_IDX 1
#define mmAOMCLK2_CNTL 0x005b
#define mmAOMCLK2_CNTL_BASE_IDX 1
#define mmDCCG_AUDIO_DTO2_PHASE 0x005c
#define mmDCCG_AUDIO_DTO2_PHASE_BASE_IDX 1
#define mmDCCG_AUDIO_DTO2_MODULO 0x005d
#define mmDCCG_AUDIO_DTO2_MODULO_BASE_IDX 1
#define mmDCE_VERSION 0x005e
#define mmDCE_VERSION_BASE_IDX 1
#define mmPHYPLLG_PIXCLK_RESYNC_CNTL 0x005f
#define mmPHYPLLG_PIXCLK_RESYNC_CNTL_BASE_IDX 1
#define mmDCCG_GTC_CNTL 0x0060
#define mmDCCG_GTC_CNTL_BASE_IDX 1
#define mmDCCG_GTC_DTO_INCR 0x0061
#define mmDCCG_GTC_DTO_INCR_BASE_IDX 1
#define mmDCCG_GTC_DTO_MODULO 0x0062
#define mmDCCG_GTC_DTO_MODULO_BASE_IDX 1
#define mmDCCG_GTC_CURRENT 0x0063
#define mmDCCG_GTC_CURRENT_BASE_IDX 1
#define mmMIPI_DTO_CNTL 0x0065
#define mmMIPI_DTO_CNTL_BASE_IDX 1
#define mmMIPI_DTO_PHASE 0x0066
#define mmMIPI_DTO_PHASE_BASE_IDX 1
#define mmMIPI_DTO_MODULO 0x0067
#define mmMIPI_DTO_MODULO_BASE_IDX 1
#define mmDAC_CLK_ENABLE 0x0068
#define mmDAC_CLK_ENABLE_BASE_IDX 1
#define mmDVO_CLK_ENABLE 0x0069
#define mmDVO_CLK_ENABLE_BASE_IDX 1
#define mmAVSYNC_COUNTER_WRITE 0x006a
#define mmAVSYNC_COUNTER_WRITE_BASE_IDX 1
#define mmAVSYNC_COUNTER_CONTROL 0x006b
#define mmAVSYNC_COUNTER_CONTROL_BASE_IDX 1
#define mmAVSYNC_COUNTER_READ 0x006f
#define mmAVSYNC_COUNTER_READ_BASE_IDX 1
#define mmMILLISECOND_TIME_BASE_DIV 0x0070
#define mmMILLISECOND_TIME_BASE_DIV_BASE_IDX 1
#define mmDISPCLK_FREQ_CHANGE_CNTL 0x0071
#define mmDISPCLK_FREQ_CHANGE_CNTL_BASE_IDX 1
#define mmDC_MEM_GLOBAL_PWR_REQ_CNTL 0x0072
#define mmDC_MEM_GLOBAL_PWR_REQ_CNTL_BASE_IDX 1
#define mmDCCG_PERFMON_CNTL 0x0073
#define mmDCCG_PERFMON_CNTL_BASE_IDX 1
#define mmDCCG_GATE_DISABLE_CNTL 0x0074
#define mmDCCG_GATE_DISABLE_CNTL_BASE_IDX 1
#define mmDISPCLK_CGTT_BLK_CTRL_REG 0x0075
#define mmDISPCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1
#define mmSOCCLK_CGTT_BLK_CTRL_REG 0x0076
#define mmSOCCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1
#define mmDCCG_CAC_STATUS 0x0077
#define mmDCCG_CAC_STATUS_BASE_IDX 1
#define mmPIXCLK1_RESYNC_CNTL 0x0078
#define mmPIXCLK1_RESYNC_CNTL_BASE_IDX 1
#define mmPIXCLK2_RESYNC_CNTL 0x0079
#define mmPIXCLK2_RESYNC_CNTL_BASE_IDX 1
#define mmPIXCLK0_RESYNC_CNTL 0x007a
#define mmPIXCLK0_RESYNC_CNTL_BASE_IDX 1
#define mmMICROSECOND_TIME_BASE_DIV 0x007b
#define mmMICROSECOND_TIME_BASE_DIV_BASE_IDX 1
#define mmDCCG_GATE_DISABLE_CNTL2 0x007c
#define mmDCCG_GATE_DISABLE_CNTL2_BASE_IDX 1
#define mmSYMCLK_CGTT_BLK_CTRL_REG 0x007d
#define mmSYMCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1
#define mmPHYPLLF_PIXCLK_RESYNC_CNTL 0x007e
#define mmPHYPLLF_PIXCLK_RESYNC_CNTL_BASE_IDX 1
#define mmDCCG_DISP_CNTL_REG 0x007f
#define mmDCCG_DISP_CNTL_REG_BASE_IDX 1
#define mmOTG0_PIXEL_RATE_CNTL 0x0080
#define mmOTG0_PIXEL_RATE_CNTL_BASE_IDX 1
#define mmDP_DTO0_PHASE 0x0081
#define mmDP_DTO0_PHASE_BASE_IDX 1
#define mmDP_DTO0_MODULO 0x0082
#define mmDP_DTO0_MODULO_BASE_IDX 1
#define mmOTG0_PHYPLL_PIXEL_RATE_CNTL 0x0083
#define mmOTG0_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1
#define mmOTG1_PIXEL_RATE_CNTL 0x0084
#define mmOTG1_PIXEL_RATE_CNTL_BASE_IDX 1
#define mmDP_DTO1_PHASE 0x0085
#define mmDP_DTO1_PHASE_BASE_IDX 1
#define mmDP_DTO1_MODULO 0x0086
#define mmDP_DTO1_MODULO_BASE_IDX 1
#define mmOTG1_PHYPLL_PIXEL_RATE_CNTL 0x0087
#define mmOTG1_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1
#define mmOTG2_PIXEL_RATE_CNTL 0x0088
#define mmOTG2_PIXEL_RATE_CNTL_BASE_IDX 1
#define mmDP_DTO2_PHASE 0x0089
#define mmDP_DTO2_PHASE_BASE_IDX 1
#define mmDP_DTO2_MODULO 0x008a
#define mmDP_DTO2_MODULO_BASE_IDX 1
#define mmOTG2_PHYPLL_PIXEL_RATE_CNTL 0x008b
#define mmOTG2_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1
#define mmOTG3_PIXEL_RATE_CNTL 0x008c
#define mmOTG3_PIXEL_RATE_CNTL_BASE_IDX 1
#define mmDP_DTO3_PHASE 0x008d
#define mmDP_DTO3_PHASE_BASE_IDX 1
#define mmDP_DTO3_MODULO 0x008e
#define mmDP_DTO3_MODULO_BASE_IDX 1
#define mmOTG3_PHYPLL_PIXEL_RATE_CNTL 0x008f
#define mmOTG3_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1
#define mmOTG4_PIXEL_RATE_CNTL 0x0090
#define mmOTG4_PIXEL_RATE_CNTL_BASE_IDX 1
#define mmDP_DTO4_PHASE 0x0091
#define mmDP_DTO4_PHASE_BASE_IDX 1
#define mmDP_DTO4_MODULO 0x0092
#define mmDP_DTO4_MODULO_BASE_IDX 1
#define mmOTG4_PHYPLL_PIXEL_RATE_CNTL 0x0093
#define mmOTG4_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1
#define mmOTG5_PIXEL_RATE_CNTL 0x0094
#define mmOTG5_PIXEL_RATE_CNTL_BASE_IDX 1
#define mmDP_DTO5_PHASE 0x0095
#define mmDP_DTO5_PHASE_BASE_IDX 1
#define mmDP_DTO5_MODULO 0x0096
#define mmDP_DTO5_MODULO_BASE_IDX 1
#define mmOTG5_PHYPLL_PIXEL_RATE_CNTL 0x0097
#define mmOTG5_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1
#define mmDPPCLK_CGTT_BLK_CTRL_REG 0x0098
#define mmDPPCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1
#define mmSYMCLKA_CLOCK_ENABLE 0x00a0
#define mmSYMCLKA_CLOCK_ENABLE_BASE_IDX 1
#define mmSYMCLKB_CLOCK_ENABLE 0x00a1
#define mmSYMCLKB_CLOCK_ENABLE_BASE_IDX 1
#define mmSYMCLKC_CLOCK_ENABLE 0x00a2
#define mmSYMCLKC_CLOCK_ENABLE_BASE_IDX 1
#define mmSYMCLKD_CLOCK_ENABLE 0x00a3
#define mmSYMCLKD_CLOCK_ENABLE_BASE_IDX 1
#define mmSYMCLKE_CLOCK_ENABLE 0x00a4
#define mmSYMCLKE_CLOCK_ENABLE_BASE_IDX 1
#define mmSYMCLKF_CLOCK_ENABLE 0x00a5
#define mmSYMCLKF_CLOCK_ENABLE_BASE_IDX 1
#define mmDCCG_SOFT_RESET 0x00a6
#define mmDCCG_SOFT_RESET_BASE_IDX 1
#define mmDVOACLKD_CNTL 0x00a8
#define mmDVOACLKD_CNTL_BASE_IDX 1
#define mmDVOACLKC_MVP_CNTL 0x00a9
#define mmDVOACLKC_MVP_CNTL_BASE_IDX 1
#define mmDVOACLKC_CNTL 0x00aa
#define mmDVOACLKC_CNTL_BASE_IDX 1
#define mmDCCG_AUDIO_DTO_SOURCE 0x00ab
#define mmDCCG_AUDIO_DTO_SOURCE_BASE_IDX 1
#define mmDCCG_AUDIO_DTO0_PHASE 0x00ac
#define mmDCCG_AUDIO_DTO0_PHASE_BASE_IDX 1
#define mmDCCG_AUDIO_DTO0_MODULE 0x00ad
#define mmDCCG_AUDIO_DTO0_MODULE_BASE_IDX 1
#define mmDCCG_AUDIO_DTO1_PHASE 0x00ae
#define mmDCCG_AUDIO_DTO1_PHASE_BASE_IDX 1
#define mmDCCG_AUDIO_DTO1_MODULE 0x00af
#define mmDCCG_AUDIO_DTO1_MODULE_BASE_IDX 1
#define mmDCCG_VSYNC_OTG0_LATCH_VALUE 0x00b0
#define mmDCCG_VSYNC_OTG0_LATCH_VALUE_BASE_IDX 1
#define mmDCCG_VSYNC_OTG1_LATCH_VALUE 0x00b1
#define mmDCCG_VSYNC_OTG1_LATCH_VALUE_BASE_IDX 1
#define mmDCCG_VSYNC_OTG2_LATCH_VALUE 0x00b2
#define mmDCCG_VSYNC_OTG2_LATCH_VALUE_BASE_IDX 1
#define mmDCCG_VSYNC_OTG3_LATCH_VALUE 0x00b3
#define mmDCCG_VSYNC_OTG3_LATCH_VALUE_BASE_IDX 1
#define mmDCCG_VSYNC_OTG4_LATCH_VALUE 0x00b4
#define mmDCCG_VSYNC_OTG4_LATCH_VALUE_BASE_IDX 1
#define mmDCCG_VSYNC_OTG5_LATCH_VALUE 0x00b5
#define mmDCCG_VSYNC_OTG5_LATCH_VALUE_BASE_IDX 1
#define mmDCCG_VSYNC_CNT_CTRL 0x00b8
#define mmDCCG_VSYNC_CNT_CTRL_BASE_IDX 1
#define mmDCCG_VSYNC_CNT_INT_CTRL 0x00b9
#define mmDCCG_VSYNC_CNT_INT_CTRL_BASE_IDX 1
#define mmDCCG_TEST_CLK_SEL 0x00be
#define mmDCCG_TEST_CLK_SEL_BASE_IDX 1
// addressBlock: dce_dc_dccg_dccg_dfs_dispdec
// base address: 0x0
#define mmDENTIST_DISPCLK_CNTL 0x0064
#define mmDENTIST_DISPCLK_CNTL_BASE_IDX 1
// addressBlock: dce_dc_dccg_dccg_dcperfmon0_dc_perfmon_dispdec
// base address: 0x0
#define mmDC_PERFMON0_PERFCOUNTER_CNTL 0x0000
#define mmDC_PERFMON0_PERFCOUNTER_CNTL_BASE_IDX 2
#define mmDC_PERFMON0_PERFCOUNTER_CNTL2 0x0001
#define mmDC_PERFMON0_PERFCOUNTER_CNTL2_BASE_IDX 2
#define mmDC_PERFMON0_PERFCOUNTER_STATE 0x0002
#define mmDC_PERFMON0_PERFCOUNTER_STATE_BASE_IDX 2
#define mmDC_PERFMON0_PERFMON_CNTL 0x0003
#define mmDC_PERFMON0_PERFMON_CNTL_BASE_IDX 2
#define mmDC_PERFMON0_PERFMON_CNTL2 0x0004
#define mmDC_PERFMON0_PERFMON_CNTL2_BASE_IDX 2
#define mmDC_PERFMON0_PERFMON_CVALUE_INT_MISC 0x0005
#define mmDC_PERFMON0_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
#define mmDC_PERFMON0_PERFMON_CVALUE_LOW 0x0006
#define mmDC_PERFMON0_PERFMON_CVALUE_LOW_BASE_IDX 2
#define mmDC_PERFMON0_PERFMON_HI 0x0007
#define mmDC_PERFMON0_PERFMON_HI_BASE_IDX 2
#define mmDC_PERFMON0_PERFMON_LOW 0x0008
#define mmDC_PERFMON0_PERFMON_LOW_BASE_IDX 2
// addressBlock: dce_dc_dccg_dccg_dcperfmon1_dc_perfmon_dispdec
// base address: 0x30
#define mmDC_PERFMON1_PERFCOUNTER_CNTL 0x000c
#define mmDC_PERFMON1_PERFCOUNTER_CNTL_BASE_IDX 2
#define mmDC_PERFMON1_PERFCOUNTER_CNTL2 0x000d
#define mmDC_PERFMON1_PERFCOUNTER_CNTL2_BASE_IDX 2
#define mmDC_PERFMON1_PERFCOUNTER_STATE 0x000e
#define mmDC_PERFMON1_PERFCOUNTER_STATE_BASE_IDX 2
#define mmDC_PERFMON1_PERFMON_CNTL 0x000f
#define mmDC_PERFMON1_PERFMON_CNTL_BASE_IDX 2
#define mmDC_PERFMON1_PERFMON_CNTL2 0x0010
#define mmDC_PERFMON1_PERFMON_CNTL2_BASE_IDX 2
#define mmDC_PERFMON1_PERFMON_CVALUE_INT_MISC 0x0011
#define mmDC_PERFMON1_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
#define mmDC_PERFMON1_PERFMON_CVALUE_LOW 0x0012
#define mmDC_PERFMON1_PERFMON_CVALUE_LOW_BASE_IDX 2
#define mmDC_PERFMON1_PERFMON_HI 0x0013
#define mmDC_PERFMON1_PERFMON_HI_BASE_IDX 2
#define mmDC_PERFMON1_PERFMON_LOW 0x0014
#define mmDC_PERFMON1_PERFMON_LOW_BASE_IDX 2
// addressBlock: dce_dc_dccg_dccg_pll_dispdec
// base address: 0x0
#define mmPLL_MACRO_CNTL_RESERVED0 0x0018
#define mmPLL_MACRO_CNTL_RESERVED0_BASE_IDX 2
#define mmPLL_MACRO_CNTL_RESERVED1 0x0019
#define mmPLL_MACRO_CNTL_RESERVED1_BASE_IDX 2
#define mmPLL_MACRO_CNTL_RESERVED2 0x001a
#define mmPLL_MACRO_CNTL_RESERVED2_BASE_IDX 2
#define mmPLL_MACRO_CNTL_RESERVED3 0x001b
#define mmPLL_MACRO_CNTL_RESERVED3_BASE_IDX 2
#define mmPLL_MACRO_CNTL_RESERVED4 0x001c
#define mmPLL_MACRO_CNTL_RESERVED4_BASE_IDX 2
#define mmPLL_MACRO_CNTL_RESERVED5 0x001d
#define mmPLL_MACRO_CNTL_RESERVED5_BASE_IDX 2
#define mmPLL_MACRO_CNTL_RESERVED6 0x001e
#define mmPLL_MACRO_CNTL_RESERVED6_BASE_IDX 2
#define mmPLL_MACRO_CNTL_RESERVED7 0x001f
#define mmPLL_MACRO_CNTL_RESERVED7_BASE_IDX 2
#define mmPLL_MACRO_CNTL_RESERVED8 0x0020
#define mmPLL_MACRO_CNTL_RESERVED8_BASE_IDX 2
#define mmPLL_MACRO_CNTL_RESERVED9 0x0021
#define mmPLL_MACRO_CNTL_RESERVED9_BASE_IDX 2
#define mmPLL_MACRO_CNTL_RESERVED10 0x0022
#define mmPLL_MACRO_CNTL_RESERVED10_BASE_IDX 2
#define mmPLL_MACRO_CNTL_RESERVED11 0x0023
#define mmPLL_MACRO_CNTL_RESERVED11_BASE_IDX 2
#define mmPLL_MACRO_CNTL_RESERVED12 0x0024
#define mmPLL_MACRO_CNTL_RESERVED12_BASE_IDX 2
#define mmPLL_MACRO_CNTL_RESERVED13 0x0025
#define mmPLL_MACRO_CNTL_RESERVED13_BASE_IDX 2
#define mmPLL_MACRO_CNTL_RESERVED14 0x0026
#define mmPLL_MACRO_CNTL_RESERVED14_BASE_IDX 2
#define mmPLL_MACRO_CNTL_RESERVED15 0x0027
#define mmPLL_MACRO_CNTL_RESERVED15_BASE_IDX 2
#define mmPLL_MACRO_CNTL_RESERVED16 0x0028
#define mmPLL_MACRO_CNTL_RESERVED16_BASE_IDX 2
#define mmPLL_MACRO_CNTL_RESERVED17 0x0029
#define mmPLL_MACRO_CNTL_RESERVED17_BASE_IDX 2
#define mmPLL_MACRO_CNTL_RESERVED18 0x002a
#define mmPLL_MACRO_CNTL_RESERVED18_BASE_IDX 2
#define mmPLL_MACRO_CNTL_RESERVED19 0x002b
#define mmPLL_MACRO_CNTL_RESERVED19_BASE_IDX 2
#define mmPLL_MACRO_CNTL_RESERVED20 0x002c
#define mmPLL_MACRO_CNTL_RESERVED20_BASE_IDX 2
#define mmPLL_MACRO_CNTL_RESERVED21 0x002d
#define mmPLL_MACRO_CNTL_RESERVED21_BASE_IDX 2
#define mmPLL_MACRO_CNTL_RESERVED22 0x002e
#define mmPLL_MACRO_CNTL_RESERVED22_BASE_IDX 2
#define mmPLL_MACRO_CNTL_RESERVED23 0x002f
#define mmPLL_MACRO_CNTL_RESERVED23_BASE_IDX 2
#define mmPLL_MACRO_CNTL_RESERVED24 0x0030
#define mmPLL_MACRO_CNTL_RESERVED24_BASE_IDX 2
#define mmPLL_MACRO_CNTL_RESERVED25 0x0031
#define mmPLL_MACRO_CNTL_RESERVED25_BASE_IDX 2
#define mmPLL_MACRO_CNTL_RESERVED26 0x0032
#define mmPLL_MACRO_CNTL_RESERVED26_BASE_IDX 2
#define mmPLL_MACRO_CNTL_RESERVED27 0x0033
#define mmPLL_MACRO_CNTL_RESERVED27_BASE_IDX 2
#define mmPLL_MACRO_CNTL_RESERVED28 0x0034
#define mmPLL_MACRO_CNTL_RESERVED28_BASE_IDX 2
#define mmPLL_MACRO_CNTL_RESERVED29 0x0035
#define mmPLL_MACRO_CNTL_RESERVED29_BASE_IDX 2
#define mmPLL_MACRO_CNTL_RESERVED30 0x0036
#define mmPLL_MACRO_CNTL_RESERVED30_BASE_IDX 2
#define mmPLL_MACRO_CNTL_RESERVED31 0x0037
#define mmPLL_MACRO_CNTL_RESERVED31_BASE_IDX 2
#define mmPLL_MACRO_CNTL_RESERVED32 0x0038
#define mmPLL_MACRO_CNTL_RESERVED32_BASE_IDX 2
#define mmPLL_MACRO_CNTL_RESERVED33 0x0039
#define mmPLL_MACRO_CNTL_RESERVED33_BASE_IDX 2
#define mmPLL_MACRO_CNTL_RESERVED34 0x003a
#define mmPLL_MACRO_CNTL_RESERVED34_BASE_IDX 2
#define mmPLL_MACRO_CNTL_RESERVED35 0x003b
#define mmPLL_MACRO_CNTL_RESERVED35_BASE_IDX 2
#define mmPLL_MACRO_CNTL_RESERVED36 0x003c
#define mmPLL_MACRO_CNTL_RESERVED36_BASE_IDX 2
#define mmPLL_MACRO_CNTL_RESERVED37 0x003d
#define mmPLL_MACRO_CNTL_RESERVED37_BASE_IDX 2
#define mmPLL_MACRO_CNTL_RESERVED38 0x003e
#define mmPLL_MACRO_CNTL_RESERVED38_BASE_IDX 2
#define mmPLL_MACRO_CNTL_RESERVED39 0x003f
#define mmPLL_MACRO_CNTL_RESERVED39_BASE_IDX 2
#define mmPLL_MACRO_CNTL_RESERVED40 0x0040
#define mmPLL_MACRO_CNTL_RESERVED40_BASE_IDX 2
#define mmPLL_MACRO_CNTL_RESERVED41 0x0041
#define mmPLL_MACRO_CNTL_RESERVED41_BASE_IDX 2
// addressBlock: dce_dc_dmu_rbbmif_dispdec
// base address: 0x0
#define mmRBBMIF_TIMEOUT 0x0055
#define mmRBBMIF_TIMEOUT_BASE_IDX 2
#define mmRBBMIF_STATUS 0x0056
#define mmRBBMIF_STATUS_BASE_IDX 2
#define mmRBBMIF_INT_STATUS 0x0057
#define mmRBBMIF_INT_STATUS_BASE_IDX 2
#define mmRBBMIF_TIMEOUT_DIS 0x0058
#define mmRBBMIF_TIMEOUT_DIS_BASE_IDX 2
#define mmRBBMIF_STATUS_FLAG 0x0059
#define mmRBBMIF_STATUS_FLAG_BASE_IDX 2
// addressBlock: dce_dc_dmu_dc_pg_dispdec
// base address: 0x0
#define mmDOMAIN0_PG_CONFIG 0x008a
#define mmDOMAIN0_PG_CONFIG_BASE_IDX 2
#define mmDOMAIN0_PG_STATUS 0x008b
#define mmDOMAIN0_PG_STATUS_BASE_IDX 2
#define mmDOMAIN1_PG_CONFIG 0x008c
#define mmDOMAIN1_PG_CONFIG_BASE_IDX 2
#define mmDOMAIN1_PG_STATUS 0x008d
#define mmDOMAIN1_PG_STATUS_BASE_IDX 2
#define mmDOMAIN2_PG_CONFIG 0x008e
#define mmDOMAIN2_PG_CONFIG_BASE_IDX 2
#define mmDOMAIN2_PG_STATUS 0x008f
#define mmDOMAIN2_PG_STATUS_BASE_IDX 2
#define mmDOMAIN3_PG_CONFIG 0x0090
#define mmDOMAIN3_PG_CONFIG_BASE_IDX 2
#define mmDOMAIN3_PG_STATUS 0x0091
#define mmDOMAIN3_PG_STATUS_BASE_IDX 2
#define mmDOMAIN4_PG_CONFIG 0x0092
#define mmDOMAIN4_PG_CONFIG_BASE_IDX 2
#define mmDOMAIN4_PG_STATUS 0x0093
#define mmDOMAIN4_PG_STATUS_BASE_IDX 2
#define mmDOMAIN5_PG_CONFIG 0x0094
#define mmDOMAIN5_PG_CONFIG_BASE_IDX 2
#define mmDOMAIN5_PG_STATUS 0x0095
#define mmDOMAIN5_PG_STATUS_BASE_IDX 2
#define mmDOMAIN6_PG_CONFIG 0x0096
#define mmDOMAIN6_PG_CONFIG_BASE_IDX 2
#define mmDOMAIN6_PG_STATUS 0x0097
#define mmDOMAIN6_PG_STATUS_BASE_IDX 2
#define mmDOMAIN7_PG_CONFIG 0x0098
#define mmDOMAIN7_PG_CONFIG_BASE_IDX 2
#define mmDOMAIN7_PG_STATUS 0x0099
#define mmDOMAIN7_PG_STATUS_BASE_IDX 2
#define mmDOMAIN8_PG_CONFIG 0x009a
#define mmDOMAIN8_PG_CONFIG_BASE_IDX 2
#define mmDOMAIN8_PG_STATUS 0x009b
#define mmDOMAIN8_PG_STATUS_BASE_IDX 2
#define mmDOMAIN9_PG_CONFIG 0x009c
#define mmDOMAIN9_PG_CONFIG_BASE_IDX 2
#define mmDOMAIN9_PG_STATUS 0x009d
#define mmDOMAIN9_PG_STATUS_BASE_IDX 2
#define mmDOMAIN10_PG_CONFIG 0x009e
#define mmDOMAIN10_PG_CONFIG_BASE_IDX 2
#define mmDOMAIN10_PG_STATUS 0x009f
#define mmDOMAIN10_PG_STATUS_BASE_IDX 2
#define mmDOMAIN11_PG_CONFIG 0x00a0
#define mmDOMAIN11_PG_CONFIG_BASE_IDX 2
#define mmDOMAIN11_PG_STATUS 0x00a1
#define mmDOMAIN11_PG_STATUS_BASE_IDX 2
#define mmDOMAIN12_PG_CONFIG 0x00a2
#define mmDOMAIN12_PG_CONFIG_BASE_IDX 2
#define mmDOMAIN12_PG_STATUS 0x00a3
#define mmDOMAIN12_PG_STATUS_BASE_IDX 2
#define mmDOMAIN13_PG_CONFIG 0x00a4
#define mmDOMAIN13_PG_CONFIG_BASE_IDX 2
#define mmDOMAIN13_PG_STATUS 0x00a5
#define mmDOMAIN13_PG_STATUS_BASE_IDX 2
#define mmDOMAIN14_PG_CONFIG 0x00a6
#define mmDOMAIN14_PG_CONFIG_BASE_IDX 2
#define mmDOMAIN14_PG_STATUS 0x00a7
#define mmDOMAIN14_PG_STATUS_BASE_IDX 2
#define mmDOMAIN15_PG_CONFIG 0x00a8
#define mmDOMAIN15_PG_CONFIG_BASE_IDX 2
#define mmDOMAIN15_PG_STATUS 0x00a9
#define mmDOMAIN15_PG_STATUS_BASE_IDX 2
#define mmDCPG_INTERRUPT_STATUS 0x00aa
#define mmDCPG_INTERRUPT_STATUS_BASE_IDX 2
#define mmDCPG_INTERRUPT_CONTROL_1 0x00ab
#define mmDCPG_INTERRUPT_CONTROL_1_BASE_IDX 2
#define mmDCPG_INTERRUPT_CONTROL_2 0x00ac
#define mmDCPG_INTERRUPT_CONTROL_2_BASE_IDX 2
#define mmDC_IP_REQUEST_CNTL 0x00ad
#define mmDC_IP_REQUEST_CNTL_BASE_IDX 2
#define mmDC_PGCNTL_STATUS_REG 0x00ae
#define mmDC_PGCNTL_STATUS_REG_BASE_IDX 2
// addressBlock: dce_dc_dmu_dmu_dcperfmon_dc_perfmon_dispdec
// base address: 0x2f8
#define mmDC_PERFMON2_PERFCOUNTER_CNTL 0x00be
#define mmDC_PERFMON2_PERFCOUNTER_CNTL_BASE_IDX 2
#define mmDC_PERFMON2_PERFCOUNTER_CNTL2 0x00bf
#define mmDC_PERFMON2_PERFCOUNTER_CNTL2_BASE_IDX 2
#define mmDC_PERFMON2_PERFCOUNTER_STATE 0x00c0
#define mmDC_PERFMON2_PERFCOUNTER_STATE_BASE_IDX 2
#define mmDC_PERFMON2_PERFMON_CNTL 0x00c1
#define mmDC_PERFMON2_PERFMON_CNTL_BASE_IDX 2
#define mmDC_PERFMON2_PERFMON_CNTL2 0x00c2
#define mmDC_PERFMON2_PERFMON_CNTL2_BASE_IDX 2
#define mmDC_PERFMON2_PERFMON_CVALUE_INT_MISC 0x00c3
#define mmDC_PERFMON2_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
#define mmDC_PERFMON2_PERFMON_CVALUE_LOW 0x00c4
#define mmDC_PERFMON2_PERFMON_CVALUE_LOW_BASE_IDX 2
#define mmDC_PERFMON2_PERFMON_HI 0x00c5
#define mmDC_PERFMON2_PERFMON_HI_BASE_IDX 2
#define mmDC_PERFMON2_PERFMON_LOW 0x00c6
#define mmDC_PERFMON2_PERFMON_LOW_BASE_IDX 2
// addressBlock: dce_dc_dmu_dmu_misc_dispdec
// base address: 0x0
#define mmCC_DC_PIPE_DIS 0x00ca
#define mmCC_DC_PIPE_DIS_BASE_IDX 2
#define mmDMU_CLK_CNTL 0x00cb
#define mmDMU_CLK_CNTL_BASE_IDX 2
#define mmDMU_MEM_PWR_CNTL 0x00cc
#define mmDMU_MEM_PWR_CNTL_BASE_IDX 2
#define mmDMCU_SMU_INTERRUPT_CNTL 0x00cd
#define mmDMCU_SMU_INTERRUPT_CNTL_BASE_IDX 2
#define mmSMU_INTERRUPT_CONTROL 0x00ce
#define mmSMU_INTERRUPT_CONTROL_BASE_IDX 2
// addressBlock: dce_dc_dmu_dmcu_dispdec
// base address: 0x0
#define mmDMCU_CTRL 0x00da
#define mmDMCU_CTRL_BASE_IDX 2
#define mmDMCU_STATUS 0x00db
#define mmDMCU_STATUS_BASE_IDX 2
#define mmDMCU_PC_START_ADDR 0x00dc
#define mmDMCU_PC_START_ADDR_BASE_IDX 2
#define mmDMCU_FW_START_ADDR 0x00dd
#define mmDMCU_FW_START_ADDR_BASE_IDX 2
#define mmDMCU_FW_END_ADDR 0x00de
#define mmDMCU_FW_END_ADDR_BASE_IDX 2
#define mmDMCU_FW_ISR_START_ADDR 0x00df
#define mmDMCU_FW_ISR_START_ADDR_BASE_IDX 2
#define mmDMCU_FW_CS_HI 0x00e0
#define mmDMCU_FW_CS_HI_BASE_IDX 2
#define mmDMCU_FW_CS_LO 0x00e1
#define mmDMCU_FW_CS_LO_BASE_IDX 2
#define mmDMCU_RAM_ACCESS_CTRL 0x00e2
#define mmDMCU_RAM_ACCESS_CTRL_BASE_IDX 2
#define mmDMCU_ERAM_WR_CTRL 0x00e3
#define mmDMCU_ERAM_WR_CTRL_BASE_IDX 2
#define mmDMCU_ERAM_WR_DATA 0x00e4
#define mmDMCU_ERAM_WR_DATA_BASE_IDX 2
#define mmDMCU_ERAM_RD_CTRL 0x00e5
#define mmDMCU_ERAM_RD_CTRL_BASE_IDX 2
#define mmDMCU_ERAM_RD_DATA 0x00e6
#define mmDMCU_ERAM_RD_DATA_BASE_IDX 2
#define mmDMCU_IRAM_WR_CTRL 0x00e7
#define mmDMCU_IRAM_WR_CTRL_BASE_IDX 2
#define mmDMCU_IRAM_WR_DATA 0x00e8
#define mmDMCU_IRAM_WR_DATA_BASE_IDX 2
#define mmDMCU_IRAM_RD_CTRL 0x00e9
#define mmDMCU_IRAM_RD_CTRL_BASE_IDX 2
#define mmDMCU_IRAM_RD_DATA 0x00ea
#define mmDMCU_IRAM_RD_DATA_BASE_IDX 2
#define mmDMCU_EVENT_TRIGGER 0x00eb
#define mmDMCU_EVENT_TRIGGER_BASE_IDX 2
#define mmDMCU_UC_INTERNAL_INT_STATUS 0x00ec
#define mmDMCU_UC_INTERNAL_INT_STATUS_BASE_IDX 2
#define mmDMCU_SS_INTERRUPT_CNTL_STATUS 0x00ed
#define mmDMCU_SS_INTERRUPT_CNTL_STATUS_BASE_IDX 2
#define mmDMCU_INTERRUPT_STATUS 0x00ee
#define mmDMCU_INTERRUPT_STATUS_BASE_IDX 2
#define mmDMCU_INTERRUPT_STATUS_1 0x00ef
#define mmDMCU_INTERRUPT_STATUS_1_BASE_IDX 2
#define mmDMCU_INTERRUPT_TO_HOST_EN_MASK 0x00f0
#define mmDMCU_INTERRUPT_TO_HOST_EN_MASK_BASE_IDX 2
#define mmDMCU_INTERRUPT_TO_UC_EN_MASK 0x00f1
#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_BASE_IDX 2
#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_1 0x00f2
#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_1_BASE_IDX 2
#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL 0x00f3
#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_BASE_IDX 2
#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1 0x00f4
#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1_BASE_IDX 2
#define mmDC_DMCU_SCRATCH 0x00f5
#define mmDC_DMCU_SCRATCH_BASE_IDX 2
#define mmDMCU_INT_CNT 0x00f6
#define mmDMCU_INT_CNT_BASE_IDX 2
#define mmDMCU_FW_CHECKSUM_SMPL_BYTE_POS 0x00f7
#define mmDMCU_FW_CHECKSUM_SMPL_BYTE_POS_BASE_IDX 2
#define mmDMCU_UC_CLK_GATING_CNTL 0x00f8
#define mmDMCU_UC_CLK_GATING_CNTL_BASE_IDX 2
#define mmMASTER_COMM_DATA_REG1 0x00f9
#define mmMASTER_COMM_DATA_REG1_BASE_IDX 2
#define mmMASTER_COMM_DATA_REG2 0x00fa
#define mmMASTER_COMM_DATA_REG2_BASE_IDX 2
#define mmMASTER_COMM_DATA_REG3 0x00fb
#define mmMASTER_COMM_DATA_REG3_BASE_IDX 2
#define mmMASTER_COMM_CMD_REG 0x00fc
#define mmMASTER_COMM_CMD_REG_BASE_IDX 2
#define mmMASTER_COMM_CNTL_REG 0x00fd
#define mmMASTER_COMM_CNTL_REG_BASE_IDX 2
#define mmSLAVE_COMM_DATA_REG1 0x00fe
#define mmSLAVE_COMM_DATA_REG1_BASE_IDX 2
#define mmSLAVE_COMM_DATA_REG2 0x00ff
#define mmSLAVE_COMM_DATA_REG2_BASE_IDX 2
#define mmSLAVE_COMM_DATA_REG3 0x0100
#define mmSLAVE_COMM_DATA_REG3_BASE_IDX 2
#define mmSLAVE_COMM_CMD_REG 0x0101
#define mmSLAVE_COMM_CMD_REG_BASE_IDX 2
#define mmSLAVE_COMM_CNTL_REG 0x0102
#define mmSLAVE_COMM_CNTL_REG_BASE_IDX 2
#define mmDMCU_PERFMON_INTERRUPT_STATUS1 0x0105
#define mmDMCU_PERFMON_INTERRUPT_STATUS1_BASE_IDX 2
#define mmDMCU_PERFMON_INTERRUPT_STATUS2 0x0106
#define mmDMCU_PERFMON_INTERRUPT_STATUS2_BASE_IDX 2
#define mmDMCU_PERFMON_INTERRUPT_STATUS3 0x0107
#define mmDMCU_PERFMON_INTERRUPT_STATUS3_BASE_IDX 2
#define mmDMCU_PERFMON_INTERRUPT_STATUS4 0x0108
#define mmDMCU_PERFMON_INTERRUPT_STATUS4_BASE_IDX 2
#define mmDMCU_PERFMON_INTERRUPT_STATUS5 0x0109
#define mmDMCU_PERFMON_INTERRUPT_STATUS5_BASE_IDX 2
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1 0x010a
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1_BASE_IDX 2
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2 0x010b
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2_BASE_IDX 2
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3 0x010c
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3_BASE_IDX 2
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4 0x010d
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4_BASE_IDX 2
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5 0x010e
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5_BASE_IDX 2
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1 0x010f
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1_BASE_IDX 2
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2 0x0110
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2_BASE_IDX 2
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3 0x0111
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3_BASE_IDX 2
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4 0x0112
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4_BASE_IDX 2
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5 0x0113
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5_BASE_IDX 2
#define mmDMCU_DPRX_INTERRUPT_STATUS1 0x0114
#define mmDMCU_DPRX_INTERRUPT_STATUS1_BASE_IDX 2
#define mmDMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1 0x0115
#define mmDMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1_BASE_IDX 2
#define mmDMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1 0x0116
#define mmDMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1_BASE_IDX 2
#define mmDMCU_INTERRUPT_STATUS_CONTINUE 0x0119
#define mmDMCU_INTERRUPT_STATUS_CONTINUE_BASE_IDX 2
#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE 0x011a
#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE_BASE_IDX 2
#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE 0x011b
#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE_BASE_IDX 2
#define mmDMCU_INT_CNT_CONTINUE 0x011c
#define mmDMCU_INT_CNT_CONTINUE_BASE_IDX 2
// addressBlock: dce_dc_dmu_ihc_dispdec
// base address: 0x0
#define mmDC_GPU_TIMER_START_POSITION_V_UPDATE 0x0126
#define mmDC_GPU_TIMER_START_POSITION_V_UPDATE_BASE_IDX 2
#define mmDC_GPU_TIMER_START_POSITION_VSTARTUP 0x0127
#define mmDC_GPU_TIMER_START_POSITION_VSTARTUP_BASE_IDX 2
#define mmDC_GPU_TIMER_READ 0x0128
#define mmDC_GPU_TIMER_READ_BASE_IDX 2
#define mmDC_GPU_TIMER_READ_CNTL 0x0129
#define mmDC_GPU_TIMER_READ_CNTL_BASE_IDX 2
#define mmDISP_INTERRUPT_STATUS 0x012a
#define mmDISP_INTERRUPT_STATUS_BASE_IDX 2
#define mmDISP_INTERRUPT_STATUS_CONTINUE 0x012b
#define mmDISP_INTERRUPT_STATUS_CONTINUE_BASE_IDX 2
#define mmDISP_INTERRUPT_STATUS_CONTINUE2 0x012c
#define mmDISP_INTERRUPT_STATUS_CONTINUE2_BASE_IDX 2
#define mmDISP_INTERRUPT_STATUS_CONTINUE3 0x012d
#define mmDISP_INTERRUPT_STATUS_CONTINUE3_BASE_IDX 2
#define mmDISP_INTERRUPT_STATUS_CONTINUE4 0x012e
#define mmDISP_INTERRUPT_STATUS_CONTINUE4_BASE_IDX 2
#define mmDISP_INTERRUPT_STATUS_CONTINUE5 0x012f
#define mmDISP_INTERRUPT_STATUS_CONTINUE5_BASE_IDX 2
#define mmDISP_INTERRUPT_STATUS_CONTINUE6 0x0130
#define mmDISP_INTERRUPT_STATUS_CONTINUE6_BASE_IDX 2
#define mmDISP_INTERRUPT_STATUS_CONTINUE7 0x0131
#define mmDISP_INTERRUPT_STATUS_CONTINUE7_BASE_IDX 2
#define mmDISP_INTERRUPT_STATUS_CONTINUE8 0x0132
#define mmDISP_INTERRUPT_STATUS_CONTINUE8_BASE_IDX 2
#define mmDISP_INTERRUPT_STATUS_CONTINUE9 0x0133
#define mmDISP_INTERRUPT_STATUS_CONTINUE9_BASE_IDX 2
#define mmDISP_INTERRUPT_STATUS_CONTINUE10 0x0134
#define mmDISP_INTERRUPT_STATUS_CONTINUE10_BASE_IDX 2
#define mmDISP_INTERRUPT_STATUS_CONTINUE11 0x0135
#define mmDISP_INTERRUPT_STATUS_CONTINUE11_BASE_IDX 2
#define mmDISP_INTERRUPT_STATUS_CONTINUE12 0x0136
#define mmDISP_INTERRUPT_STATUS_CONTINUE12_BASE_IDX 2
#define mmDISP_INTERRUPT_STATUS_CONTINUE13 0x0137
#define mmDISP_INTERRUPT_STATUS_CONTINUE13_BASE_IDX 2
#define mmDISP_INTERRUPT_STATUS_CONTINUE14 0x0138
#define mmDISP_INTERRUPT_STATUS_CONTINUE14_BASE_IDX 2
#define mmDISP_INTERRUPT_STATUS_CONTINUE15 0x0139
#define mmDISP_INTERRUPT_STATUS_CONTINUE15_BASE_IDX 2
#define mmDISP_INTERRUPT_STATUS_CONTINUE16 0x013a
#define mmDISP_INTERRUPT_STATUS_CONTINUE16_BASE_IDX 2
#define mmDISP_INTERRUPT_STATUS_CONTINUE17 0x013b
#define mmDISP_INTERRUPT_STATUS_CONTINUE17_BASE_IDX 2
#define mmDISP_INTERRUPT_STATUS_CONTINUE18 0x013c
#define mmDISP_INTERRUPT_STATUS_CONTINUE18_BASE_IDX 2
#define mmDISP_INTERRUPT_STATUS_CONTINUE19 0x013d
#define mmDISP_INTERRUPT_STATUS_CONTINUE19_BASE_IDX 2
#define mmDISP_INTERRUPT_STATUS_CONTINUE20 0x013e
#define mmDISP_INTERRUPT_STATUS_CONTINUE20_BASE_IDX 2
#define mmDISP_INTERRUPT_STATUS_CONTINUE21 0x013f
#define mmDISP_INTERRUPT_STATUS_CONTINUE21_BASE_IDX 2
#define mmDISP_INTERRUPT_STATUS_CONTINUE22 0x0140
#define mmDISP_INTERRUPT_STATUS_CONTINUE22_BASE_IDX 2
#define mmDC_GPU_TIMER_START_POSITION_VREADY 0x0141
#define mmDC_GPU_TIMER_START_POSITION_VREADY_BASE_IDX 2
#define mmDC_GPU_TIMER_START_POSITION_FLIP 0x0142
#define mmDC_GPU_TIMER_START_POSITION_FLIP_BASE_IDX 2
#define mmDC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK 0x0143
#define mmDC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK_BASE_IDX 2
#define mmDC_GPU_TIMER_START_POSITION_FLIP_AWAY 0x0144
#define mmDC_GPU_TIMER_START_POSITION_FLIP_AWAY_BASE_IDX 2
// addressBlock: dce_dc_wb0_dispdec_cnv_dispdec
// base address: 0x0
#define mmCNV0_WB_ENABLE 0x01da
#define mmCNV0_WB_ENABLE_BASE_IDX 2
#define mmCNV0_WB_EC_CONFIG 0x01db
#define mmCNV0_WB_EC_CONFIG_BASE_IDX 2
#define mmCNV0_CNV_MODE 0x01dc
#define mmCNV0_CNV_MODE_BASE_IDX 2
#define mmCNV0_CNV_WINDOW_START 0x01dd
#define mmCNV0_CNV_WINDOW_START_BASE_IDX 2
#define mmCNV0_CNV_WINDOW_SIZE 0x01de
#define mmCNV0_CNV_WINDOW_SIZE_BASE_IDX 2
#define mmCNV0_CNV_UPDATE 0x01df
#define mmCNV0_CNV_UPDATE_BASE_IDX 2
#define mmCNV0_CNV_SOURCE_SIZE 0x01e0
#define mmCNV0_CNV_SOURCE_SIZE_BASE_IDX 2
#define mmCNV0_CNV_CSC_CONTROL 0x01e1
#define mmCNV0_CNV_CSC_CONTROL_BASE_IDX 2
#define mmCNV0_CNV_CSC_C11_C12 0x01e2
#define mmCNV0_CNV_CSC_C11_C12_BASE_IDX 2
#define mmCNV0_CNV_CSC_C13_C14 0x01e3
#define mmCNV0_CNV_CSC_C13_C14_BASE_IDX 2
#define mmCNV0_CNV_CSC_C21_C22 0x01e4
#define mmCNV0_CNV_CSC_C21_C22_BASE_IDX 2
#define mmCNV0_CNV_CSC_C23_C24 0x01e5
#define mmCNV0_CNV_CSC_C23_C24_BASE_IDX 2
#define mmCNV0_CNV_CSC_C31_C32 0x01e6
#define mmCNV0_CNV_CSC_C31_C32_BASE_IDX 2
#define mmCNV0_CNV_CSC_C33_C34 0x01e7
#define mmCNV0_CNV_CSC_C33_C34_BASE_IDX 2
#define mmCNV0_CNV_CSC_ROUND_OFFSET_R 0x01e8
#define mmCNV0_CNV_CSC_ROUND_OFFSET_R_BASE_IDX 2
#define mmCNV0_CNV_CSC_ROUND_OFFSET_G 0x01e9
#define mmCNV0_CNV_CSC_ROUND_OFFSET_G_BASE_IDX 2
#define mmCNV0_CNV_CSC_ROUND_OFFSET_B 0x01ea
#define mmCNV0_CNV_CSC_ROUND_OFFSET_B_BASE_IDX 2
#define mmCNV0_CNV_CSC_CLAMP_R 0x01eb
#define mmCNV0_CNV_CSC_CLAMP_R_BASE_IDX 2
#define mmCNV0_CNV_CSC_CLAMP_G 0x01ec
#define mmCNV0_CNV_CSC_CLAMP_G_BASE_IDX 2
#define mmCNV0_CNV_CSC_CLAMP_B 0x01ed
#define mmCNV0_CNV_CSC_CLAMP_B_BASE_IDX 2
#define mmCNV0_CNV_TEST_CNTL 0x01ee
#define mmCNV0_CNV_TEST_CNTL_BASE_IDX 2
#define mmCNV0_CNV_TEST_CRC_RED 0x01ef
#define mmCNV0_CNV_TEST_CRC_RED_BASE_IDX 2
#define mmCNV0_CNV_TEST_CRC_GREEN 0x01f0
#define mmCNV0_CNV_TEST_CRC_GREEN_BASE_IDX 2
#define mmCNV0_CNV_TEST_CRC_BLUE 0x01f1
#define mmCNV0_CNV_TEST_CRC_BLUE_BASE_IDX 2
#define mmCNV0_CNV_INPUT_SELECT 0x01f5
#define mmCNV0_CNV_INPUT_SELECT_BASE_IDX 2
#define mmCNV0_WB_SOFT_RESET 0x01f8
#define mmCNV0_WB_SOFT_RESET_BASE_IDX 2
#define mmCNV0_WB_WARM_UP_MODE_CTL1 0x01f9
#define mmCNV0_WB_WARM_UP_MODE_CTL1_BASE_IDX 2
#define mmCNV0_WB_WARM_UP_MODE_CTL2 0x01fa
#define mmCNV0_WB_WARM_UP_MODE_CTL2_BASE_IDX 2
// addressBlock: dce_dc_wb0_dispdec_wbscl_dispdec
// base address: 0x0
#define mmWBSCL0_WBSCL_COEF_RAM_SELECT 0x020a
#define mmWBSCL0_WBSCL_COEF_RAM_SELECT_BASE_IDX 2
#define mmWBSCL0_WBSCL_COEF_RAM_TAP_DATA 0x020b
#define mmWBSCL0_WBSCL_COEF_RAM_TAP_DATA_BASE_IDX 2
#define mmWBSCL0_WBSCL_MODE 0x020c
#define mmWBSCL0_WBSCL_MODE_BASE_IDX 2
#define mmWBSCL0_WBSCL_TAP_CONTROL 0x020d
#define mmWBSCL0_WBSCL_TAP_CONTROL_BASE_IDX 2
#define mmWBSCL0_WBSCL_DEST_SIZE 0x020e
#define mmWBSCL0_WBSCL_DEST_SIZE_BASE_IDX 2
#define mmWBSCL0_WBSCL_HORZ_FILTER_SCALE_RATIO 0x020f
#define mmWBSCL0_WBSCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2
#define mmWBSCL0_WBSCL_HORZ_FILTER_INIT_Y_RGB 0x0210
#define mmWBSCL0_WBSCL_HORZ_FILTER_INIT_Y_RGB_BASE_IDX 2
#define mmWBSCL0_WBSCL_HORZ_FILTER_INIT_CBCR 0x0211
#define mmWBSCL0_WBSCL_HORZ_FILTER_INIT_CBCR_BASE_IDX 2
#define mmWBSCL0_WBSCL_VERT_FILTER_SCALE_RATIO 0x0212
#define mmWBSCL0_WBSCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2
#define mmWBSCL0_WBSCL_VERT_FILTER_INIT_Y_RGB 0x0213
#define mmWBSCL0_WBSCL_VERT_FILTER_INIT_Y_RGB_BASE_IDX 2
#define mmWBSCL0_WBSCL_VERT_FILTER_INIT_CBCR 0x0214
#define mmWBSCL0_WBSCL_VERT_FILTER_INIT_CBCR_BASE_IDX 2
#define mmWBSCL0_WBSCL_ROUND_OFFSET 0x0215
#define mmWBSCL0_WBSCL_ROUND_OFFSET_BASE_IDX 2
#define mmWBSCL0_WBSCL_CLAMP 0x0216
#define mmWBSCL0_WBSCL_CLAMP_BASE_IDX 2
#define mmWBSCL0_WBSCL_OVERFLOW_STATUS 0x0217
#define mmWBSCL0_WBSCL_OVERFLOW_STATUS_BASE_IDX 2
#define mmWBSCL0_WBSCL_COEF_RAM_CONFLICT_STATUS 0x0218
#define mmWBSCL0_WBSCL_COEF_RAM_CONFLICT_STATUS_BASE_IDX 2
#define mmWBSCL0_WBSCL_OUTSIDE_PIX_STRATEGY 0x0219
#define mmWBSCL0_WBSCL_OUTSIDE_PIX_STRATEGY_BASE_IDX 2
#define mmWBSCL0_WBSCL_TEST_CNTL 0x021a
#define mmWBSCL0_WBSCL_TEST_CNTL_BASE_IDX 2
#define mmWBSCL0_WBSCL_TEST_CRC_RED 0x021b
#define mmWBSCL0_WBSCL_TEST_CRC_RED_BASE_IDX 2
#define mmWBSCL0_WBSCL_TEST_CRC_GREEN 0x021c
#define mmWBSCL0_WBSCL_TEST_CRC_GREEN_BASE_IDX 2
#define mmWBSCL0_WBSCL_TEST_CRC_BLUE 0x021d
#define mmWBSCL0_WBSCL_TEST_CRC_BLUE_BASE_IDX 2
#define mmWBSCL0_WBSCL_BACKPRESSURE_CNT_EN 0x021e
#define mmWBSCL0_WBSCL_BACKPRESSURE_CNT_EN_BASE_IDX 2
#define mmWBSCL0_WB_MCIF_BACKPRESSURE_CNT 0x021f
#define mmWBSCL0_WB_MCIF_BACKPRESSURE_CNT_BASE_IDX 2
#define mmWBSCL0_WBSCL_RAM_SHUTDOWN 0x0222
#define mmWBSCL0_WBSCL_RAM_SHUTDOWN_BASE_IDX 2
// addressBlock: dce_dc_wb0_dispdec_wb_dcperfmon_dc_perfmon_dispdec
// base address: 0x8e8
#define mmDC_PERFMON3_PERFCOUNTER_CNTL 0x023a
#define mmDC_PERFMON3_PERFCOUNTER_CNTL_BASE_IDX 2
#define mmDC_PERFMON3_PERFCOUNTER_CNTL2 0x023b
#define mmDC_PERFMON3_PERFCOUNTER_CNTL2_BASE_IDX 2
#define mmDC_PERFMON3_PERFCOUNTER_STATE 0x023c
#define mmDC_PERFMON3_PERFCOUNTER_STATE_BASE_IDX 2
#define mmDC_PERFMON3_PERFMON_CNTL 0x023d
#define mmDC_PERFMON3_PERFMON_CNTL_BASE_IDX 2
#define mmDC_PERFMON3_PERFMON_CNTL2 0x023e
#define mmDC_PERFMON3_PERFMON_CNTL2_BASE_IDX 2
#define mmDC_PERFMON3_PERFMON_CVALUE_INT_MISC 0x023f
#define mmDC_PERFMON3_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
#define mmDC_PERFMON3_PERFMON_CVALUE_LOW 0x0240
#define mmDC_PERFMON3_PERFMON_CVALUE_LOW_BASE_IDX 2
#define mmDC_PERFMON3_PERFMON_HI 0x0241
#define mmDC_PERFMON3_PERFMON_HI_BASE_IDX 2
#define mmDC_PERFMON3_PERFMON_LOW 0x0242
#define mmDC_PERFMON3_PERFMON_LOW_BASE_IDX 2
// addressBlock: dce_dc_wb1_dispdec_cnv_dispdec
// base address: 0x1b0
#define mmCNV1_WB_ENABLE 0x0246
#define mmCNV1_WB_ENABLE_BASE_IDX 2
#define mmCNV1_WB_EC_CONFIG 0x0247
#define mmCNV1_WB_EC_CONFIG_BASE_IDX 2
#define mmCNV1_CNV_MODE 0x0248
#define mmCNV1_CNV_MODE_BASE_IDX 2
#define mmCNV1_CNV_WINDOW_START 0x0249
#define mmCNV1_CNV_WINDOW_START_BASE_IDX 2
#define mmCNV1_CNV_WINDOW_SIZE 0x024a
#define mmCNV1_CNV_WINDOW_SIZE_BASE_IDX 2
#define mmCNV1_CNV_UPDATE 0x024b
#define mmCNV1_CNV_UPDATE_BASE_IDX 2
#define mmCNV1_CNV_SOURCE_SIZE 0x024c
#define mmCNV1_CNV_SOURCE_SIZE_BASE_IDX 2
#define mmCNV1_CNV_CSC_CONTROL 0x024d
#define mmCNV1_CNV_CSC_CONTROL_BASE_IDX 2
#define mmCNV1_CNV_CSC_C11_C12 0x024e
#define mmCNV1_CNV_CSC_C11_C12_BASE_IDX 2
#define mmCNV1_CNV_CSC_C13_C14 0x024f
#define mmCNV1_CNV_CSC_C13_C14_BASE_IDX 2
#define mmCNV1_CNV_CSC_C21_C22 0x0250
#define mmCNV1_CNV_CSC_C21_C22_BASE_IDX 2
#define mmCNV1_CNV_CSC_C23_C24 0x0251
#define mmCNV1_CNV_CSC_C23_C24_BASE_IDX 2
#define mmCNV1_CNV_CSC_C31_C32 0x0252
#define mmCNV1_CNV_CSC_C31_C32_BASE_IDX 2
#define mmCNV1_CNV_CSC_C33_C34 0x0253
#define mmCNV1_CNV_CSC_C33_C34_BASE_IDX 2
#define mmCNV1_CNV_CSC_ROUND_OFFSET_R 0x0254
#define mmCNV1_CNV_CSC_ROUND_OFFSET_R_BASE_IDX 2
#define mmCNV1_CNV_CSC_ROUND_OFFSET_G 0x0255
#define mmCNV1_CNV_CSC_ROUND_OFFSET_G_BASE_IDX 2
#define mmCNV1_CNV_CSC_ROUND_OFFSET_B 0x0256
#define mmCNV1_CNV_CSC_ROUND_OFFSET_B_BASE_IDX 2
#define mmCNV1_CNV_CSC_CLAMP_R 0x0257
#define mmCNV1_CNV_CSC_CLAMP_R_BASE_IDX 2
#define mmCNV1_CNV_CSC_CLAMP_G 0x0258
#define mmCNV1_CNV_CSC_CLAMP_G_BASE_IDX 2
#define mmCNV1_CNV_CSC_CLAMP_B 0x0259
#define mmCNV1_CNV_CSC_CLAMP_B_BASE_IDX 2
#define mmCNV1_CNV_TEST_CNTL 0x025a
#define mmCNV1_CNV_TEST_CNTL_BASE_IDX 2
#define mmCNV1_CNV_TEST_CRC_RED 0x025b
#define mmCNV1_CNV_TEST_CRC_RED_BASE_IDX 2
#define mmCNV1_CNV_TEST_CRC_GREEN 0x025c
#define mmCNV1_CNV_TEST_CRC_GREEN_BASE_IDX 2
#define mmCNV1_CNV_TEST_CRC_BLUE 0x025d
#define mmCNV1_CNV_TEST_CRC_BLUE_BASE_IDX 2
#define mmCNV1_CNV_INPUT_SELECT 0x0261
#define mmCNV1_CNV_INPUT_SELECT_BASE_IDX 2
#define mmCNV1_WB_SOFT_RESET 0x0264
#define mmCNV1_WB_SOFT_RESET_BASE_IDX 2
#define mmCNV1_WB_WARM_UP_MODE_CTL1 0x0265
#define mmCNV1_WB_WARM_UP_MODE_CTL1_BASE_IDX 2
#define mmCNV1_WB_WARM_UP_MODE_CTL2 0x0266
#define mmCNV1_WB_WARM_UP_MODE_CTL2_BASE_IDX 2
// addressBlock: dce_dc_wb1_dispdec_wbscl_dispdec
// base address: 0x1b0
#define mmWBSCL1_WBSCL_COEF_RAM_SELECT 0x0276
#define mmWBSCL1_WBSCL_COEF_RAM_SELECT_BASE_IDX 2
#define mmWBSCL1_WBSCL_COEF_RAM_TAP_DATA 0x0277
#define mmWBSCL1_WBSCL_COEF_RAM_TAP_DATA_BASE_IDX 2
#define mmWBSCL1_WBSCL_MODE 0x0278
#define mmWBSCL1_WBSCL_MODE_BASE_IDX 2
#define mmWBSCL1_WBSCL_TAP_CONTROL 0x0279
#define mmWBSCL1_WBSCL_TAP_CONTROL_BASE_IDX 2
#define mmWBSCL1_WBSCL_DEST_SIZE 0x027a
#define mmWBSCL1_WBSCL_DEST_SIZE_BASE_IDX 2
#define mmWBSCL1_WBSCL_HORZ_FILTER_SCALE_RATIO 0x027b
#define mmWBSCL1_WBSCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2
#define mmWBSCL1_WBSCL_HORZ_FILTER_INIT_Y_RGB 0x027c
#define mmWBSCL1_WBSCL_HORZ_FILTER_INIT_Y_RGB_BASE_IDX 2
#define mmWBSCL1_WBSCL_HORZ_FILTER_INIT_CBCR 0x027d
#define mmWBSCL1_WBSCL_HORZ_FILTER_INIT_CBCR_BASE_IDX 2
#define mmWBSCL1_WBSCL_VERT_FILTER_SCALE_RATIO 0x027e
#define mmWBSCL1_WBSCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2
#define mmWBSCL1_WBSCL_VERT_FILTER_INIT_Y_RGB 0x027f
#define mmWBSCL1_WBSCL_VERT_FILTER_INIT_Y_RGB_BASE_IDX 2
#define mmWBSCL1_WBSCL_VERT_FILTER_INIT_CBCR 0x0280
#define mmWBSCL1_WBSCL_VERT_FILTER_INIT_CBCR_BASE_IDX 2
#define mmWBSCL1_WBSCL_ROUND_OFFSET 0x0281
#define mmWBSCL1_WBSCL_ROUND_OFFSET_BASE_IDX 2
#define mmWBSCL1_WBSCL_CLAMP 0x0282
#define mmWBSCL1_WBSCL_CLAMP_BASE_IDX 2
#define mmWBSCL1_WBSCL_OVERFLOW_STATUS 0x0283
#define mmWBSCL1_WBSCL_OVERFLOW_STATUS_BASE_IDX 2
#define mmWBSCL1_WBSCL_COEF_RAM_CONFLICT_STATUS 0x0284
#define mmWBSCL1_WBSCL_COEF_RAM_CONFLICT_STATUS_BASE_IDX 2
#define mmWBSCL1_WBSCL_OUTSIDE_PIX_STRATEGY 0x0285
#define mmWBSCL1_WBSCL_OUTSIDE_PIX_STRATEGY_BASE_IDX 2
#define mmWBSCL1_WBSCL_TEST_CNTL 0x0286
#define mmWBSCL1_WBSCL_TEST_CNTL_BASE_IDX 2
#define mmWBSCL1_WBSCL_TEST_CRC_RED 0x0287
#define mmWBSCL1_WBSCL_TEST_CRC_RED_BASE_IDX 2
#define mmWBSCL1_WBSCL_TEST_CRC_GREEN 0x0288
#define mmWBSCL1_WBSCL_TEST_CRC_GREEN_BASE_IDX 2
#define mmWBSCL1_WBSCL_TEST_CRC_BLUE 0x0289
#define mmWBSCL1_WBSCL_TEST_CRC_BLUE_BASE_IDX 2
#define mmWBSCL1_WBSCL_BACKPRESSURE_CNT_EN 0x028a
#define mmWBSCL1_WBSCL_BACKPRESSURE_CNT_EN_BASE_IDX 2
#define mmWBSCL1_WB_MCIF_BACKPRESSURE_CNT 0x028b
#define mmWBSCL1_WB_MCIF_BACKPRESSURE_CNT_BASE_IDX 2
#define mmWBSCL1_WBSCL_RAM_SHUTDOWN 0x028e
#define mmWBSCL1_WBSCL_RAM_SHUTDOWN_BASE_IDX 2
// addressBlock: dce_dc_wb1_dispdec_wb_dcperfmon_dc_perfmon_dispdec
// base address: 0xa98
#define mmDC_PERFMON4_PERFCOUNTER_CNTL 0x02a6
#define mmDC_PERFMON4_PERFCOUNTER_CNTL_BASE_IDX 2
#define mmDC_PERFMON4_PERFCOUNTER_CNTL2 0x02a7
#define mmDC_PERFMON4_PERFCOUNTER_CNTL2_BASE_IDX 2
#define mmDC_PERFMON4_PERFCOUNTER_STATE 0x02a8
#define mmDC_PERFMON4_PERFCOUNTER_STATE_BASE_IDX 2
#define mmDC_PERFMON4_PERFMON_CNTL 0x02a9
#define mmDC_PERFMON4_PERFMON_CNTL_BASE_IDX 2
#define mmDC_PERFMON4_PERFMON_CNTL2 0x02aa
#define mmDC_PERFMON4_PERFMON_CNTL2_BASE_IDX 2
#define mmDC_PERFMON4_PERFMON_CVALUE_INT_MISC 0x02ab
#define mmDC_PERFMON4_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
#define mmDC_PERFMON4_PERFMON_CVALUE_LOW 0x02ac
#define mmDC_PERFMON4_PERFMON_CVALUE_LOW_BASE_IDX 2
#define mmDC_PERFMON4_PERFMON_HI 0x02ad
#define mmDC_PERFMON4_PERFMON_HI_BASE_IDX 2
#define mmDC_PERFMON4_PERFMON_LOW 0x02ae
#define mmDC_PERFMON4_PERFMON_LOW_BASE_IDX 2
// addressBlock: dce_dc_mmhubbub_mcif_wb0_dispdec
// base address: 0x0
#define mmMCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL 0x02b2
#define mmMCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL_BASE_IDX 2
#define mmMCIF_WB0_MCIF_WB_BUFMGR_CUR_LINE_R 0x02b3
#define mmMCIF_WB0_MCIF_WB_BUFMGR_CUR_LINE_R_BASE_IDX 2
#define mmMCIF_WB0_MCIF_WB_BUFMGR_STATUS 0x02b4
#define mmMCIF_WB0_MCIF_WB_BUFMGR_STATUS_BASE_IDX 2
#define mmMCIF_WB0_MCIF_WB_BUF_PITCH 0x02b5
#define mmMCIF_WB0_MCIF_WB_BUF_PITCH_BASE_IDX 2
#define mmMCIF_WB0_MCIF_WB_BUF_1_STATUS 0x02b6
#define mmMCIF_WB0_MCIF_WB_BUF_1_STATUS_BASE_IDX 2
#define mmMCIF_WB0_MCIF_WB_BUF_1_STATUS2 0x02b7
#define mmMCIF_WB0_MCIF_WB_BUF_1_STATUS2_BASE_IDX 2
#define mmMCIF_WB0_MCIF_WB_BUF_2_STATUS 0x02b8
#define mmMCIF_WB0_MCIF_WB_BUF_2_STATUS_BASE_IDX 2
#define mmMCIF_WB0_MCIF_WB_BUF_2_STATUS2 0x02b9
#define mmMCIF_WB0_MCIF_WB_BUF_2_STATUS2_BASE_IDX 2
#define mmMCIF_WB0_MCIF_WB_BUF_3_STATUS 0x02ba
#define mmMCIF_WB0_MCIF_WB_BUF_3_STATUS_BASE_IDX 2
#define mmMCIF_WB0_MCIF_WB_BUF_3_STATUS2 0x02bb
#define mmMCIF_WB0_MCIF_WB_BUF_3_STATUS2_BASE_IDX 2
#define mmMCIF_WB0_MCIF_WB_BUF_4_STATUS 0x02bc
#define mmMCIF_WB0_MCIF_WB_BUF_4_STATUS_BASE_IDX 2
#define mmMCIF_WB0_MCIF_WB_BUF_4_STATUS2 0x02bd
#define mmMCIF_WB0_MCIF_WB_BUF_4_STATUS2_BASE_IDX 2
#define mmMCIF_WB0_MCIF_WB_ARBITRATION_CONTROL 0x02be
#define mmMCIF_WB0_MCIF_WB_ARBITRATION_CONTROL_BASE_IDX 2
#define mmMCIF_WB0_MCIF_WB_SCLK_CHANGE 0x02bf
#define mmMCIF_WB0_MCIF_WB_SCLK_CHANGE_BASE_IDX 2
#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y 0x02c2
#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_BASE_IDX 2
#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_OFFSET 0x02c3
#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_OFFSET_BASE_IDX 2
#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C 0x02c4
#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C_BASE_IDX 2
#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C_OFFSET 0x02c5
#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C_OFFSET_BASE_IDX 2
#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y 0x02c6
#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_BASE_IDX 2
#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_OFFSET 0x02c7
#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_OFFSET_BASE_IDX 2
#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C 0x02c8
#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C_BASE_IDX 2
#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C_OFFSET 0x02c9
#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C_OFFSET_BASE_IDX 2
#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y 0x02ca
#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_BASE_IDX 2
#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_OFFSET 0x02cb
#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_OFFSET_BASE_IDX 2
#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C 0x02cc
#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C_BASE_IDX 2
#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C_OFFSET 0x02cd
#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C_OFFSET_BASE_IDX 2
#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y 0x02ce
#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_BASE_IDX 2
#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_OFFSET 0x02cf
#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_OFFSET_BASE_IDX 2
#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C 0x02d0
#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C_BASE_IDX 2
#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C_OFFSET 0x02d1
#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C_OFFSET_BASE_IDX 2
#define mmMCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL 0x02d2
#define mmMCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL_BASE_IDX 2
#define mmMCIF_WB0_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK 0x02d3
#define mmMCIF_WB0_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK_BASE_IDX 2
#define mmMCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL 0x02d4
#define mmMCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL_BASE_IDX 2
#define mmMCIF_WB0_MCIF_WB_WATERMARK 0x02d5
#define mmMCIF_WB0_MCIF_WB_WATERMARK_BASE_IDX 2
#define mmMCIF_WB0_MCIF_WB_CLOCK_GATER_CONTROL 0x02d6
#define mmMCIF_WB0_MCIF_WB_CLOCK_GATER_CONTROL_BASE_IDX 2
#define mmMCIF_WB0_MCIF_WB_WARM_UP_CNTL 0x02d7
#define mmMCIF_WB0_MCIF_WB_WARM_UP_CNTL_BASE_IDX 2
#define mmMCIF_WB0_MCIF_WB_SELF_REFRESH_CONTROL 0x02d8
#define mmMCIF_WB0_MCIF_WB_SELF_REFRESH_CONTROL_BASE_IDX 2
#define mmMCIF_WB0_MULTI_LEVEL_QOS_CTRL 0x02d9
#define mmMCIF_WB0_MULTI_LEVEL_QOS_CTRL_BASE_IDX 2
#define mmMCIF_WB0_MCIF_WB_BUF_LUMA_SIZE 0x02db
#define mmMCIF_WB0_MCIF_WB_BUF_LUMA_SIZE_BASE_IDX 2
#define mmMCIF_WB0_MCIF_WB_BUF_CHROMA_SIZE 0x02dc
#define mmMCIF_WB0_MCIF_WB_BUF_CHROMA_SIZE_BASE_IDX 2
// addressBlock: dce_dc_mmhubbub_mcif_wb1_dispdec
// base address: 0x100
#define mmMCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL 0x02f2
#define mmMCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL_BASE_IDX 2
#define mmMCIF_WB1_MCIF_WB_BUFMGR_CUR_LINE_R 0x02f3
#define mmMCIF_WB1_MCIF_WB_BUFMGR_CUR_LINE_R_BASE_IDX 2
#define mmMCIF_WB1_MCIF_WB_BUFMGR_STATUS 0x02f4
#define mmMCIF_WB1_MCIF_WB_BUFMGR_STATUS_BASE_IDX 2
#define mmMCIF_WB1_MCIF_WB_BUF_PITCH 0x02f5
#define mmMCIF_WB1_MCIF_WB_BUF_PITCH_BASE_IDX 2
#define mmMCIF_WB1_MCIF_WB_BUF_1_STATUS 0x02f6
#define mmMCIF_WB1_MCIF_WB_BUF_1_STATUS_BASE_IDX 2
#define mmMCIF_WB1_MCIF_WB_BUF_1_STATUS2 0x02f7
#define mmMCIF_WB1_MCIF_WB_BUF_1_STATUS2_BASE_IDX 2
#define mmMCIF_WB1_MCIF_WB_BUF_2_STATUS 0x02f8
#define mmMCIF_WB1_MCIF_WB_BUF_2_STATUS_BASE_IDX 2
#define mmMCIF_WB1_MCIF_WB_BUF_2_STATUS2 0x02f9
#define mmMCIF_WB1_MCIF_WB_BUF_2_STATUS2_BASE_IDX 2
#define mmMCIF_WB1_MCIF_WB_BUF_3_STATUS 0x02fa
#define mmMCIF_WB1_MCIF_WB_BUF_3_STATUS_BASE_IDX 2
#define mmMCIF_WB1_MCIF_WB_BUF_3_STATUS2 0x02fb
#define mmMCIF_WB1_MCIF_WB_BUF_3_STATUS2_BASE_IDX 2
#define mmMCIF_WB1_MCIF_WB_BUF_4_STATUS 0x02fc
#define mmMCIF_WB1_MCIF_WB_BUF_4_STATUS_BASE_IDX 2
#define mmMCIF_WB1_MCIF_WB_BUF_4_STATUS2 0x02fd
#define mmMCIF_WB1_MCIF_WB_BUF_4_STATUS2_BASE_IDX 2
#define mmMCIF_WB1_MCIF_WB_ARBITRATION_CONTROL 0x02fe
#define mmMCIF_WB1_MCIF_WB_ARBITRATION_CONTROL_BASE_IDX 2
#define mmMCIF_WB1_MCIF_WB_SCLK_CHANGE 0x02ff
#define mmMCIF_WB1_MCIF_WB_SCLK_CHANGE_BASE_IDX 2
#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y 0x0302
#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_BASE_IDX 2
#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_OFFSET 0x0303
#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_OFFSET_BASE_IDX 2
#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C 0x0304
#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C_BASE_IDX 2
#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C_OFFSET 0x0305
#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C_OFFSET_BASE_IDX 2
#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y 0x0306
#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_BASE_IDX 2
#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_OFFSET 0x0307
#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_OFFSET_BASE_IDX 2
#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C 0x0308
#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C_BASE_IDX 2
#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C_OFFSET 0x0309
#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C_OFFSET_BASE_IDX 2
#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y 0x030a
#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_BASE_IDX 2
#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_OFFSET 0x030b
#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_OFFSET_BASE_IDX 2
#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C 0x030c
#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C_BASE_IDX 2
#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C_OFFSET 0x030d
#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C_OFFSET_BASE_IDX 2
#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y 0x030e
#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_BASE_IDX 2
#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_OFFSET 0x030f
#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_OFFSET_BASE_IDX 2
#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C 0x0310
#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C_BASE_IDX 2
#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C_OFFSET 0x0311
#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C_OFFSET_BASE_IDX 2
#define mmMCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL 0x0312
#define mmMCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL_BASE_IDX 2
#define mmMCIF_WB1_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK 0x0313
#define mmMCIF_WB1_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK_BASE_IDX 2
#define mmMCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL 0x0314
#define mmMCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL_BASE_IDX 2
#define mmMCIF_WB1_MCIF_WB_WATERMARK 0x0315
#define mmMCIF_WB1_MCIF_WB_WATERMARK_BASE_IDX 2
#define mmMCIF_WB1_MCIF_WB_CLOCK_GATER_CONTROL 0x0316
#define mmMCIF_WB1_MCIF_WB_CLOCK_GATER_CONTROL_BASE_IDX 2
#define mmMCIF_WB1_MCIF_WB_WARM_UP_CNTL 0x0317
#define mmMCIF_WB1_MCIF_WB_WARM_UP_CNTL_BASE_IDX 2
#define mmMCIF_WB1_MCIF_WB_SELF_REFRESH_CONTROL 0x0318
#define mmMCIF_WB1_MCIF_WB_SELF_REFRESH_CONTROL_BASE_IDX 2
#define mmMCIF_WB1_MULTI_LEVEL_QOS_CTRL 0x0319
#define mmMCIF_WB1_MULTI_LEVEL_QOS_CTRL_BASE_IDX 2
#define mmMCIF_WB1_MCIF_WB_BUF_LUMA_SIZE 0x031b
#define mmMCIF_WB1_MCIF_WB_BUF_LUMA_SIZE_BASE_IDX 2
#define mmMCIF_WB1_MCIF_WB_BUF_CHROMA_SIZE 0x031c
#define mmMCIF_WB1_MCIF_WB_BUF_CHROMA_SIZE_BASE_IDX 2
// addressBlock: dce_dc_mmhubbub_mmhubbub_dispdec
// base address: 0x0
#define mmWBIF0_MISC_CTRL 0x0333
#define mmWBIF0_MISC_CTRL_BASE_IDX 2
#define mmWBIF0_SMU_WM_CONTROL 0x0334
#define mmWBIF0_SMU_WM_CONTROL_BASE_IDX 2
#define mmWBIF0_PHASE0_OUTSTANDING_COUNTER 0x0335
#define mmWBIF0_PHASE0_OUTSTANDING_COUNTER_BASE_IDX 2
#define mmWBIF0_PHASE1_OUTSTANDING_COUNTER 0x0336
#define mmWBIF0_PHASE1_OUTSTANDING_COUNTER_BASE_IDX 2
#define mmWBIF1_MISC_CTRL 0x0337
#define mmWBIF1_MISC_CTRL_BASE_IDX 2
#define mmWBIF1_SMU_WM_CONTROL 0x0338
#define mmWBIF1_SMU_WM_CONTROL_BASE_IDX 2
#define mmWBIF1_PHASE0_OUTSTANDING_COUNTER 0x0339
#define mmWBIF1_PHASE0_OUTSTANDING_COUNTER_BASE_IDX 2
#define mmWBIF1_PHASE1_OUTSTANDING_COUNTER 0x033a
#define mmWBIF1_PHASE1_OUTSTANDING_COUNTER_BASE_IDX 2
#define mmVGA_SRC_SPLIT_CNTL 0x033b
#define mmVGA_SRC_SPLIT_CNTL_BASE_IDX 2
#define mmMMHUBBUB_MEM_PWR_STATUS 0x033c
#define mmMMHUBBUB_MEM_PWR_STATUS_BASE_IDX 2
#define mmMMHUBBUB_MEM_PWR_CNTL 0x033d
#define mmMMHUBBUB_MEM_PWR_CNTL_BASE_IDX 2
#define mmMMHUBBUB_CLOCK_CNTL 0x033e
#define mmMMHUBBUB_CLOCK_CNTL_BASE_IDX 2
#define mmMMHUBBUB_SOFT_RESET 0x033f
#define mmMMHUBBUB_SOFT_RESET_BASE_IDX 2
// addressBlock: dce_dc_mmhubbub_vgaif_dispdec
// base address: 0x0
#define mmMCIF_CONTROL 0x034a
#define mmMCIF_CONTROL_BASE_IDX 2
#define mmMCIF_WRITE_COMBINE_CONTROL 0x034b
#define mmMCIF_WRITE_COMBINE_CONTROL_BASE_IDX 2
#define mmMCIF_PHASE0_OUTSTANDING_COUNTER 0x034e
#define mmMCIF_PHASE0_OUTSTANDING_COUNTER_BASE_IDX 2
#define mmMCIF_PHASE1_OUTSTANDING_COUNTER 0x034f
#define mmMCIF_PHASE1_OUTSTANDING_COUNTER_BASE_IDX 2
#define mmMCIF_PHASE2_OUTSTANDING_COUNTER 0x0350
#define mmMCIF_PHASE2_OUTSTANDING_COUNTER_BASE_IDX 2
// addressBlock: dce_dc_mmhubbub_mmhubbub_dcperfmon_dc_perfmon_dispdec
// base address: 0xd48
#define mmDC_PERFMON5_PERFCOUNTER_CNTL 0x0352
#define mmDC_PERFMON5_PERFCOUNTER_CNTL_BASE_IDX 2
#define mmDC_PERFMON5_PERFCOUNTER_CNTL2 0x0353
#define mmDC_PERFMON5_PERFCOUNTER_CNTL2_BASE_IDX 2
#define mmDC_PERFMON5_PERFCOUNTER_STATE 0x0354
#define mmDC_PERFMON5_PERFCOUNTER_STATE_BASE_IDX 2
#define mmDC_PERFMON5_PERFMON_CNTL 0x0355
#define mmDC_PERFMON5_PERFMON_CNTL_BASE_IDX 2
#define mmDC_PERFMON5_PERFMON_CNTL2 0x0356
#define mmDC_PERFMON5_PERFMON_CNTL2_BASE_IDX 2
#define mmDC_PERFMON5_PERFMON_CVALUE_INT_MISC 0x0357
#define mmDC_PERFMON5_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
#define mmDC_PERFMON5_PERFMON_CVALUE_LOW 0x0358
#define mmDC_PERFMON5_PERFMON_CVALUE_LOW_BASE_IDX 2
#define mmDC_PERFMON5_PERFMON_HI 0x0359
#define mmDC_PERFMON5_PERFMON_HI_BASE_IDX 2
#define mmDC_PERFMON5_PERFMON_LOW 0x035a
#define mmDC_PERFMON5_PERFMON_LOW_BASE_IDX 2
// addressBlock: dce_dc_hda_azf0stream0_dispdec
// base address: 0x0
#define mmAZF0STREAM0_AZALIA_STREAM_INDEX 0x035e
#define mmAZF0STREAM0_AZALIA_STREAM_INDEX_BASE_IDX 2
#define mmAZF0STREAM0_AZALIA_STREAM_DATA 0x035f
#define mmAZF0STREAM0_AZALIA_STREAM_DATA_BASE_IDX 2
// addressBlock: dce_dc_hda_azf0stream1_dispdec
// base address: 0x8
#define mmAZF0STREAM1_AZALIA_STREAM_INDEX 0x0360
#define mmAZF0STREAM1_AZALIA_STREAM_INDEX_BASE_IDX 2
#define mmAZF0STREAM1_AZALIA_STREAM_DATA 0x0361
#define mmAZF0STREAM1_AZALIA_STREAM_DATA_BASE_IDX 2
// addressBlock: dce_dc_hda_azf0stream2_dispdec
// base address: 0x10
#define mmAZF0STREAM2_AZALIA_STREAM_INDEX 0x0362
#define mmAZF0STREAM2_AZALIA_STREAM_INDEX_BASE_IDX 2
#define mmAZF0STREAM2_AZALIA_STREAM_DATA 0x0363
#define mmAZF0STREAM2_AZALIA_STREAM_DATA_BASE_IDX 2
// addressBlock: dce_dc_hda_azf0stream3_dispdec
// base address: 0x18
#define mmAZF0STREAM3_AZALIA_STREAM_INDEX 0x0364
#define mmAZF0STREAM3_AZALIA_STREAM_INDEX_BASE_IDX 2
#define mmAZF0STREAM3_AZALIA_STREAM_DATA 0x0365
#define mmAZF0STREAM3_AZALIA_STREAM_DATA_BASE_IDX 2
// addressBlock: dce_dc_hda_azf0stream4_dispdec
// base address: 0x20
#define mmAZF0STREAM4_AZALIA_STREAM_INDEX 0x0366
#define mmAZF0STREAM4_AZALIA_STREAM_INDEX_BASE_IDX 2
#define mmAZF0STREAM4_AZALIA_STREAM_DATA 0x0367
#define mmAZF0STREAM4_AZALIA_STREAM_DATA_BASE_IDX 2
// addressBlock: dce_dc_hda_azf0stream5_dispdec
// base address: 0x28
#define mmAZF0STREAM5_AZALIA_STREAM_INDEX 0x0368
#define mmAZF0STREAM5_AZALIA_STREAM_INDEX_BASE_IDX 2
#define mmAZF0STREAM5_AZALIA_STREAM_DATA 0x0369
#define mmAZF0STREAM5_AZALIA_STREAM_DATA_BASE_IDX 2
// addressBlock: dce_dc_hda_azf0stream6_dispdec
// base address: 0x30
#define mmAZF0STREAM6_AZALIA_STREAM_INDEX 0x036a
#define mmAZF0STREAM6_AZALIA_STREAM_INDEX_BASE_IDX 2
#define mmAZF0STREAM6_AZALIA_STREAM_DATA 0x036b
#define mmAZF0STREAM6_AZALIA_STREAM_DATA_BASE_IDX 2
// addressBlock: dce_dc_hda_azf0stream7_dispdec
// base address: 0x38
#define mmAZF0STREAM7_AZALIA_STREAM_INDEX 0x036c
#define mmAZF0STREAM7_AZALIA_STREAM_INDEX_BASE_IDX 2
#define mmAZF0STREAM7_AZALIA_STREAM_DATA 0x036d
#define mmAZF0STREAM7_AZALIA_STREAM_DATA_BASE_IDX 2
// addressBlock: dce_dc_hda_az_misc_dispdec
// base address: 0x0
#define mmAZ_CLOCK_CNTL 0x0372
#define mmAZ_CLOCK_CNTL_BASE_IDX 2
// addressBlock: dce_dc_hda_az_dcperfmon_dc_perfmon_dispdec
// base address: 0xde8
#define mmDC_PERFMON6_PERFCOUNTER_CNTL 0x037a
#define mmDC_PERFMON6_PERFCOUNTER_CNTL_BASE_IDX 2
#define mmDC_PERFMON6_PERFCOUNTER_CNTL2 0x037b
#define mmDC_PERFMON6_PERFCOUNTER_CNTL2_BASE_IDX 2
#define mmDC_PERFMON6_PERFCOUNTER_STATE 0x037c
#define mmDC_PERFMON6_PERFCOUNTER_STATE_BASE_IDX 2
#define mmDC_PERFMON6_PERFMON_CNTL 0x037d
#define mmDC_PERFMON6_PERFMON_CNTL_BASE_IDX 2
#define mmDC_PERFMON6_PERFMON_CNTL2 0x037e
#define mmDC_PERFMON6_PERFMON_CNTL2_BASE_IDX 2
#define mmDC_PERFMON6_PERFMON_CVALUE_INT_MISC 0x037f
#define mmDC_PERFMON6_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
#define mmDC_PERFMON6_PERFMON_CVALUE_LOW 0x0380
#define mmDC_PERFMON6_PERFMON_CVALUE_LOW_BASE_IDX 2
#define mmDC_PERFMON6_PERFMON_HI 0x0381
#define mmDC_PERFMON6_PERFMON_HI_BASE_IDX 2
#define mmDC_PERFMON6_PERFMON_LOW 0x0382
#define mmDC_PERFMON6_PERFMON_LOW_BASE_IDX 2
// addressBlock: dce_dc_hda_azf0endpoint0_dispdec
// base address: 0x0
#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x0386
#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2
#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA 0x0387
#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2
// addressBlock: dce_dc_hda_azf0endpoint1_dispdec
// base address: 0x18
#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x038c
#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2
#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA 0x038d
#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2
// addressBlock: dce_dc_hda_azf0endpoint2_dispdec
// base address: 0x30
#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x0392
#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2
#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA 0x0393
#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2
// addressBlock: dce_dc_hda_azf0endpoint3_dispdec
// base address: 0x48
#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x0398
#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2
#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA 0x0399
#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2
// addressBlock: dce_dc_hda_azf0endpoint4_dispdec
// base address: 0x60
#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x039e
#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2
#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA 0x039f
#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2
// addressBlock: dce_dc_hda_azf0endpoint5_dispdec
// base address: 0x78
#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x03a4
#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2
#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA 0x03a5
#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2
// addressBlock: dce_dc_hda_azf0endpoint6_dispdec
// base address: 0x90
#define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x03aa
#define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2
#define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA 0x03ab
#define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2
// addressBlock: dce_dc_hda_azf0endpoint7_dispdec
// base address: 0xa8
#define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x03b0
#define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2
#define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA 0x03b1
#define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2
// addressBlock: dce_dc_hda_azf0controller_dispdec
// base address: 0x0
#define mmAZALIA_CONTROLLER_CLOCK_GATING 0x03c2
#define mmAZALIA_CONTROLLER_CLOCK_GATING_BASE_IDX 2
#define mmAZALIA_AUDIO_DTO 0x03c3
#define mmAZALIA_AUDIO_DTO_BASE_IDX 2
#define mmAZALIA_AUDIO_DTO_CONTROL 0x03c4
#define mmAZALIA_AUDIO_DTO_CONTROL_BASE_IDX 2
#define mmAZALIA_SOCCLK_CONTROL 0x03c5
#define mmAZALIA_SOCCLK_CONTROL_BASE_IDX 2
#define mmAZALIA_UNDERFLOW_FILLER_SAMPLE 0x03c6
#define mmAZALIA_UNDERFLOW_FILLER_SAMPLE_BASE_IDX 2
#define mmAZALIA_DATA_DMA_CONTROL 0x03c7
#define mmAZALIA_DATA_DMA_CONTROL_BASE_IDX 2
#define mmAZALIA_BDL_DMA_CONTROL 0x03c8
#define mmAZALIA_BDL_DMA_CONTROL_BASE_IDX 2
#define mmAZALIA_RIRB_AND_DP_CONTROL 0x03c9
#define mmAZALIA_RIRB_AND_DP_CONTROL_BASE_IDX 2
#define mmAZALIA_CORB_DMA_CONTROL 0x03ca
#define mmAZALIA_CORB_DMA_CONTROL_BASE_IDX 2
#define mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER 0x03d1
#define mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER_BASE_IDX 2
#define mmAZALIA_CYCLIC_BUFFER_SYNC 0x03d2
#define mmAZALIA_CYCLIC_BUFFER_SYNC_BASE_IDX 2
#define mmAZALIA_GLOBAL_CAPABILITIES 0x03d3
#define mmAZALIA_GLOBAL_CAPABILITIES_BASE_IDX 2
#define mmAZALIA_OUTPUT_PAYLOAD_CAPABILITY 0x03d4
#define mmAZALIA_OUTPUT_PAYLOAD_CAPABILITY_BASE_IDX 2
#define mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL 0x03d5
#define mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL_BASE_IDX 2
#define mmAZALIA_INPUT_PAYLOAD_CAPABILITY 0x03d6
#define mmAZALIA_INPUT_PAYLOAD_CAPABILITY_BASE_IDX 2
#define mmAZALIA_INPUT_CRC0_CONTROL0 0x03d9
#define mmAZALIA_INPUT_CRC0_CONTROL0_BASE_IDX 2
#define mmAZALIA_INPUT_CRC0_CONTROL1 0x03da
#define mmAZALIA_INPUT_CRC0_CONTROL1_BASE_IDX 2
#define mmAZALIA_INPUT_CRC0_CONTROL2 0x03db
#define mmAZALIA_INPUT_CRC0_CONTROL2_BASE_IDX 2
#define mmAZALIA_INPUT_CRC0_CONTROL3 0x03dc
#define mmAZALIA_INPUT_CRC0_CONTROL3_BASE_IDX 2
#define mmAZALIA_INPUT_CRC0_RESULT 0x03dd
#define mmAZALIA_INPUT_CRC0_RESULT_BASE_IDX 2
#define mmAZALIA_INPUT_CRC1_CONTROL0 0x03de
#define mmAZALIA_INPUT_CRC1_CONTROL0_BASE_IDX 2
#define mmAZALIA_INPUT_CRC1_CONTROL1 0x03df
#define mmAZALIA_INPUT_CRC1_CONTROL1_BASE_IDX 2
#define mmAZALIA_INPUT_CRC1_CONTROL2 0x03e0
#define mmAZALIA_INPUT_CRC1_CONTROL2_BASE_IDX 2
#define mmAZALIA_INPUT_CRC1_CONTROL3 0x03e1
#define mmAZALIA_INPUT_CRC1_CONTROL3_BASE_IDX 2
#define mmAZALIA_INPUT_CRC1_RESULT 0x03e2
#define mmAZALIA_INPUT_CRC1_RESULT_BASE_IDX 2
#define mmAZALIA_CRC0_CONTROL0 0x03e3
#define mmAZALIA_CRC0_CONTROL0_BASE_IDX 2
#define mmAZALIA_CRC0_CONTROL1 0x03e4
#define mmAZALIA_CRC0_CONTROL1_BASE_IDX 2
#define mmAZALIA_CRC0_CONTROL2 0x03e5
#define mmAZALIA_CRC0_CONTROL2_BASE_IDX 2
#define mmAZALIA_CRC0_CONTROL3 0x03e6
#define mmAZALIA_CRC0_CONTROL3_BASE_IDX 2
#define mmAZALIA_CRC0_RESULT 0x03e7
#define mmAZALIA_CRC0_RESULT_BASE_IDX 2
#define mmAZALIA_CRC1_CONTROL0 0x03e8
#define mmAZALIA_CRC1_CONTROL0_BASE_IDX 2
#define mmAZALIA_CRC1_CONTROL1 0x03e9
#define mmAZALIA_CRC1_CONTROL1_BASE_IDX 2
#define mmAZALIA_CRC1_CONTROL2 0x03ea
#define mmAZALIA_CRC1_CONTROL2_BASE_IDX 2
#define mmAZALIA_CRC1_CONTROL3 0x03eb
#define mmAZALIA_CRC1_CONTROL3_BASE_IDX 2
#define mmAZALIA_CRC1_RESULT 0x03ec
#define mmAZALIA_CRC1_RESULT_BASE_IDX 2
#define mmAZALIA_MEM_PWR_CTRL 0x03ee
#define mmAZALIA_MEM_PWR_CTRL_BASE_IDX 2
#define mmAZALIA_MEM_PWR_STATUS 0x03ef
#define mmAZALIA_MEM_PWR_STATUS_BASE_IDX 2
// addressBlock: dce_dc_hda_azf0root_dispdec
// base address: 0x0
#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID 0x0406
#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_BASE_IDX 2
#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID 0x0407
#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID_BASE_IDX 2
#define mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL 0x0408
#define mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL_BASE_IDX 2
#define mmAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL 0x0409
#define mmAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL_BASE_IDX 2
#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE 0x040a
#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_BASE_IDX 2
#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES 0x040b
#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES_BASE_IDX 2
#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS 0x040c
#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_BASE_IDX 2
#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES 0x040d
#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES_BASE_IDX 2
#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE 0x040e
#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE_BASE_IDX 2
#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET 0x040f
#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET_BASE_IDX 2
#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID 0x0410
#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_BASE_IDX 2
#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION 0x0411
#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION_BASE_IDX 2
#define mmCC_RCU_DC_AUDIO_PORT_CONNECTIVITY 0x0412
#define mmCC_RCU_DC_AUDIO_PORT_CONNECTIVITY_BASE_IDX 2
#define mmCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY 0x0413
#define mmCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_BASE_IDX 2
#define mmAZALIA_F0_GTC_GROUP_OFFSET0 0x0415
#define mmAZALIA_F0_GTC_GROUP_OFFSET0_BASE_IDX 2
#define mmAZALIA_F0_GTC_GROUP_OFFSET1 0x0416
#define mmAZALIA_F0_GTC_GROUP_OFFSET1_BASE_IDX 2
#define mmAZALIA_F0_GTC_GROUP_OFFSET2 0x0417
#define mmAZALIA_F0_GTC_GROUP_OFFSET2_BASE_IDX 2
#define mmAZALIA_F0_GTC_GROUP_OFFSET3 0x0418
#define mmAZALIA_F0_GTC_GROUP_OFFSET3_BASE_IDX 2
#define mmAZALIA_F0_GTC_GROUP_OFFSET4 0x0419
#define mmAZALIA_F0_GTC_GROUP_OFFSET4_BASE_IDX 2
#define mmAZALIA_F0_GTC_GROUP_OFFSET5 0x041a
#define mmAZALIA_F0_GTC_GROUP_OFFSET5_BASE_IDX 2
#define mmAZALIA_F0_GTC_GROUP_OFFSET6 0x041b
#define mmAZALIA_F0_GTC_GROUP_OFFSET6_BASE_IDX 2
#define mmREG_DC_AUDIO_PORT_CONNECTIVITY 0x041c
#define mmREG_DC_AUDIO_PORT_CONNECTIVITY_BASE_IDX 2
#define mmREG_DC_AUDIO_INPUT_PORT_CONNECTIVITY 0x041d
#define mmREG_DC_AUDIO_INPUT_PORT_CONNECTIVITY_BASE_IDX 2
// addressBlock: dce_dc_hda_azf0stream8_dispdec
// base address: 0x320
#define mmAZF0STREAM8_AZALIA_STREAM_INDEX 0x0426
#define mmAZF0STREAM8_AZALIA_STREAM_INDEX_BASE_IDX 2
#define mmAZF0STREAM8_AZALIA_STREAM_DATA 0x0427
#define mmAZF0STREAM8_AZALIA_STREAM_DATA_BASE_IDX 2
// addressBlock: dce_dc_hda_azf0stream9_dispdec
// base address: 0x328
#define mmAZF0STREAM9_AZALIA_STREAM_INDEX 0x0428
#define mmAZF0STREAM9_AZALIA_STREAM_INDEX_BASE_IDX 2
#define mmAZF0STREAM9_AZALIA_STREAM_DATA 0x0429
#define mmAZF0STREAM9_AZALIA_STREAM_DATA_BASE_IDX 2
// addressBlock: dce_dc_hda_azf0stream10_dispdec
// base address: 0x330
#define mmAZF0STREAM10_AZALIA_STREAM_INDEX 0x042a
#define mmAZF0STREAM10_AZALIA_STREAM_INDEX_BASE_IDX 2
#define mmAZF0STREAM10_AZALIA_STREAM_DATA 0x042b
#define mmAZF0STREAM10_AZALIA_STREAM_DATA_BASE_IDX 2
// addressBlock: dce_dc_hda_azf0stream11_dispdec
// base address: 0x338
#define mmAZF0STREAM11_AZALIA_STREAM_INDEX 0x042c
#define mmAZF0STREAM11_AZALIA_STREAM_INDEX_BASE_IDX 2
#define mmAZF0STREAM11_AZALIA_STREAM_DATA 0x042d
#define mmAZF0STREAM11_AZALIA_STREAM_DATA_BASE_IDX 2
// addressBlock: dce_dc_hda_azf0stream12_dispdec
// base address: 0x340
#define mmAZF0STREAM12_AZALIA_STREAM_INDEX 0x042e
#define mmAZF0STREAM12_AZALIA_STREAM_INDEX_BASE_IDX 2
#define mmAZF0STREAM12_AZALIA_STREAM_DATA 0x042f
#define mmAZF0STREAM12_AZALIA_STREAM_DATA_BASE_IDX 2
// addressBlock: dce_dc_hda_azf0stream13_dispdec
// base address: 0x348
#define mmAZF0STREAM13_AZALIA_STREAM_INDEX 0x0430
#define mmAZF0STREAM13_AZALIA_STREAM_INDEX_BASE_IDX 2
#define mmAZF0STREAM13_AZALIA_STREAM_DATA 0x0431
#define mmAZF0STREAM13_AZALIA_STREAM_DATA_BASE_IDX 2
// addressBlock: dce_dc_hda_azf0stream14_dispdec
// base address: 0x350
#define mmAZF0STREAM14_AZALIA_STREAM_INDEX 0x0432
#define mmAZF0STREAM14_AZALIA_STREAM_INDEX_BASE_IDX 2
#define mmAZF0STREAM14_AZALIA_STREAM_DATA 0x0433
#define mmAZF0STREAM14_AZALIA_STREAM_DATA_BASE_IDX 2
// addressBlock: dce_dc_hda_azf0stream15_dispdec
// base address: 0x358
#define mmAZF0STREAM15_AZALIA_STREAM_INDEX 0x0434
#define mmAZF0STREAM15_AZALIA_STREAM_INDEX_BASE_IDX 2
#define mmAZF0STREAM15_AZALIA_STREAM_DATA 0x0435
#define mmAZF0STREAM15_AZALIA_STREAM_DATA_BASE_IDX 2
// addressBlock: dce_dc_hda_azf0inputendpoint0_dispdec
// base address: 0x0
#define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x043a
#define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2
#define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x043b
#define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2
// addressBlock: dce_dc_hda_azf0inputendpoint1_dispdec
// base address: 0x10
#define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x043e
#define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2
#define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x043f
#define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2
// addressBlock: dce_dc_hda_azf0inputendpoint2_dispdec
// base address: 0x20
#define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0442
#define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2
#define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0443
#define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2
// addressBlock: dce_dc_hda_azf0inputendpoint3_dispdec
// base address: 0x30
#define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0446
#define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2
#define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0447
#define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2
// addressBlock: dce_dc_hda_azf0inputendpoint4_dispdec
// base address: 0x40
#define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x044a
#define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2
#define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x044b
#define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2
// addressBlock: dce_dc_hda_azf0inputendpoint5_dispdec
// base address: 0x50
#define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x044e
#define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2
#define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x044f
#define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2
// addressBlock: dce_dc_hda_azf0inputendpoint6_dispdec
// base address: 0x60
#define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0452
#define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2
#define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0453
#define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2
// addressBlock: dce_dc_hda_azf0inputendpoint7_dispdec
// base address: 0x70
#define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0456
#define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2
#define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0457
#define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2
// addressBlock: dce_dc_dchubbub_hubbub_sdpif_dispdec
// base address: 0x0
#define mmDCHUBBUB_SDPIF_CFG0 0x048f
#define mmDCHUBBUB_SDPIF_CFG0_BASE_IDX 2
#define mmDCHUBBUB_SDPIF_CFG1 0x0490
#define mmDCHUBBUB_SDPIF_CFG1_BASE_IDX 2
#define mmDCHUBBUB_FORCE_IO_STATUS_0 0x0491
#define mmDCHUBBUB_FORCE_IO_STATUS_0_BASE_IDX 2
#define mmDCHUBBUB_FORCE_IO_STATUS_1 0x0492
#define mmDCHUBBUB_FORCE_IO_STATUS_1_BASE_IDX 2
#define mmDCHUBBUB_SDPIF_FB_BASE 0x0493
#define mmDCHUBBUB_SDPIF_FB_BASE_BASE_IDX 2
#define mmDCHUBBUB_SDPIF_FB_TOP 0x0494
#define mmDCHUBBUB_SDPIF_FB_TOP_BASE_IDX 2
#define mmDCHUBBUB_SDPIF_FB_OFFSET 0x0495
#define mmDCHUBBUB_SDPIF_FB_OFFSET_BASE_IDX 2
#define mmDCHUBBUB_SDPIF_AGP_BOT 0x0496
#define mmDCHUBBUB_SDPIF_AGP_BOT_BASE_IDX 2
#define mmDCHUBBUB_SDPIF_AGP_TOP 0x0497
#define mmDCHUBBUB_SDPIF_AGP_TOP_BASE_IDX 2
#define mmDCHUBBUB_SDPIF_AGP_BASE 0x0498
#define mmDCHUBBUB_SDPIF_AGP_BASE_BASE_IDX 2
#define mmDCHUBBUB_SDPIF_APER_BASE 0x0499
#define mmDCHUBBUB_SDPIF_APER_BASE_BASE_IDX 2
#define mmDCHUBBUB_SDPIF_APER_TOP 0x049a
#define mmDCHUBBUB_SDPIF_APER_TOP_BASE_IDX 2
#define mmDCHUBBUB_SDPIF_APER_DEF_0 0x049b
#define mmDCHUBBUB_SDPIF_APER_DEF_0_BASE_IDX 2
#define mmDCHUBBUB_SDPIF_APER_DEF_1 0x049c
#define mmDCHUBBUB_SDPIF_APER_DEF_1_BASE_IDX 2
#define mmDCHUBBUB_SDPIF_MMIO_CNTRL_0 0x049d
#define mmDCHUBBUB_SDPIF_MMIO_CNTRL_0_BASE_IDX 2
#define mmDCHUBBUB_SDPIF_MMIO_CNTRL_1 0x049e
#define mmDCHUBBUB_SDPIF_MMIO_CNTRL_1_BASE_IDX 2
#define mmDCHUBBUB_SDPIF_MMIO_CNTRL_W 0x049f
#define mmDCHUBBUB_SDPIF_MMIO_CNTRL_W_BASE_IDX 2
#define mmDCHUBBUB_SDPIF_MARC_BASE_LO_0 0x04a0
#define mmDCHUBBUB_SDPIF_MARC_BASE_LO_0_BASE_IDX 2
#define mmDCHUBBUB_SDPIF_MARC_BASE_HI_0 0x04a1
#define mmDCHUBBUB_SDPIF_MARC_BASE_HI_0_BASE_IDX 2
#define mmDCHUBBUB_SDPIF_MARC_RELOC_LO_0 0x04a2
#define mmDCHUBBUB_SDPIF_MARC_RELOC_LO_0_BASE_IDX 2
#define mmDCHUBBUB_SDPIF_MARC_RELOC_HI_0 0x04a3
#define mmDCHUBBUB_SDPIF_MARC_RELOC_HI_0_BASE_IDX 2
#define mmDCHUBBUB_SDPIF_MARC_LENGTH_LO_0 0x04a4
#define mmDCHUBBUB_SDPIF_MARC_LENGTH_LO_0_BASE_IDX 2
#define mmDCHUBBUB_SDPIF_MARC_LENGTH_HI_0 0x04a5
#define mmDCHUBBUB_SDPIF_MARC_LENGTH_HI_0_BASE_IDX 2
#define mmDCHUBBUB_SDPIF_MARC_BASE_LO_1 0x04a6
#define mmDCHUBBUB_SDPIF_MARC_BASE_LO_1_BASE_IDX 2
#define mmDCHUBBUB_SDPIF_MARC_BASE_HI_1 0x04a7
#define mmDCHUBBUB_SDPIF_MARC_BASE_HI_1_BASE_IDX 2
#define mmDCHUBBUB_SDPIF_MARC_RELOC_LO_1 0x04a8
#define mmDCHUBBUB_SDPIF_MARC_RELOC_LO_1_BASE_IDX 2
#define mmDCHUBBUB_SDPIF_MARC_RELOC_HI_1 0x04a9
#define mmDCHUBBUB_SDPIF_MARC_RELOC_HI_1_BASE_IDX 2
#define mmDCHUBBUB_SDPIF_MARC_LENGTH_LO_1 0x04aa
#define mmDCHUBBUB_SDPIF_MARC_LENGTH_LO_1_BASE_IDX 2
#define mmDCHUBBUB_SDPIF_MARC_LENGTH_HI_1 0x04ab
#define mmDCHUBBUB_SDPIF_MARC_LENGTH_HI_1_BASE_IDX 2
#define mmDCHUBBUB_SDPIF_MARC_BASE_LO_2 0x04ac
#define mmDCHUBBUB_SDPIF_MARC_BASE_LO_2_BASE_IDX 2
#define mmDCHUBBUB_SDPIF_MARC_BASE_HI_2 0x04ad
#define mmDCHUBBUB_SDPIF_MARC_BASE_HI_2_BASE_IDX 2
#define mmDCHUBBUB_SDPIF_MARC_RELOC_LO_2 0x04ae
#define mmDCHUBBUB_SDPIF_MARC_RELOC_LO_2_BASE_IDX 2
#define mmDCHUBBUB_SDPIF_MARC_RELOC_HI_2 0x04af
#define mmDCHUBBUB_SDPIF_MARC_RELOC_HI_2_BASE_IDX 2
#define mmDCHUBBUB_SDPIF_MARC_LENGTH_LO_2 0x04b0
#define mmDCHUBBUB_SDPIF_MARC_LENGTH_LO_2_BASE_IDX 2
#define mmDCHUBBUB_SDPIF_MARC_LENGTH_HI_2 0x04b1
#define mmDCHUBBUB_SDPIF_MARC_LENGTH_HI_2_BASE_IDX 2
#define mmDCHUBBUB_SDPIF_MARC_BASE_LO_3 0x04b2
#define mmDCHUBBUB_SDPIF_MARC_BASE_LO_3_BASE_IDX 2
#define mmDCHUBBUB_SDPIF_MARC_BASE_HI_3 0x04b3
#define mmDCHUBBUB_SDPIF_MARC_BASE_HI_3_BASE_IDX 2
#define mmDCHUBBUB_SDPIF_MARC_RELOC_LO_3 0x04b4
#define mmDCHUBBUB_SDPIF_MARC_RELOC_LO_3_BASE_IDX 2
#define mmDCHUBBUB_SDPIF_MARC_RELOC_HI_3 0x04b5
#define mmDCHUBBUB_SDPIF_MARC_RELOC_HI_3_BASE_IDX 2
#define mmDCHUBBUB_SDPIF_MARC_LENGTH_LO_3 0x04b6
#define mmDCHUBBUB_SDPIF_MARC_LENGTH_LO_3_BASE_IDX 2
#define mmDCHUBBUB_SDPIF_MARC_LENGTH_HI_3 0x04b7
#define mmDCHUBBUB_SDPIF_MARC_LENGTH_HI_3_BASE_IDX 2
#define mmDCHUBBUB_SDPIF_PIPE_SEC_LVL 0x04b8
#define mmDCHUBBUB_SDPIF_PIPE_SEC_LVL_BASE_IDX 2
#define mmDCHUBBUB_SDPIF_MEM_PWR_CTRL 0x04b9
#define mmDCHUBBUB_SDPIF_MEM_PWR_CTRL_BASE_IDX 2
#define mmDCHUBBUB_SDPIF_MEM_PWR_STATUS 0x04ba
#define mmDCHUBBUB_SDPIF_MEM_PWR_STATUS_BASE_IDX 2
// addressBlock: dce_dc_dchubbub_hubbub_ret_path_dispdec
// base address: 0x0
#define mmDCHUBBUB_RET_PATH_DCC_CFG 0x04cf
#define mmDCHUBBUB_RET_PATH_DCC_CFG_BASE_IDX 2
#define mmDCHUBBUB_RET_PATH_DCC_CFG0_0 0x04d0
#define mmDCHUBBUB_RET_PATH_DCC_CFG0_0_BASE_IDX 2
#define mmDCHUBBUB_RET_PATH_DCC_CFG0_1 0x04d1
#define mmDCHUBBUB_RET_PATH_DCC_CFG0_1_BASE_IDX 2
#define mmDCHUBBUB_RET_PATH_DCC_CFG1_0 0x04d2
#define mmDCHUBBUB_RET_PATH_DCC_CFG1_0_BASE_IDX 2
#define mmDCHUBBUB_RET_PATH_DCC_CFG1_1 0x04d3
#define mmDCHUBBUB_RET_PATH_DCC_CFG1_1_BASE_IDX 2
#define mmDCHUBBUB_RET_PATH_DCC_CFG2_0 0x04d4
#define mmDCHUBBUB_RET_PATH_DCC_CFG2_0_BASE_IDX 2
#define mmDCHUBBUB_RET_PATH_DCC_CFG2_1 0x04d5
#define mmDCHUBBUB_RET_PATH_DCC_CFG2_1_BASE_IDX 2
#define mmDCHUBBUB_RET_PATH_DCC_CFG3_0 0x04d6
#define mmDCHUBBUB_RET_PATH_DCC_CFG3_0_BASE_IDX 2
#define mmDCHUBBUB_RET_PATH_DCC_CFG3_1 0x04d7
#define mmDCHUBBUB_RET_PATH_DCC_CFG3_1_BASE_IDX 2
#define mmDCHUBBUB_RET_PATH_DCC_CFG4_0 0x04d8
#define mmDCHUBBUB_RET_PATH_DCC_CFG4_0_BASE_IDX 2
#define mmDCHUBBUB_RET_PATH_DCC_CFG4_1 0x04d9
#define mmDCHUBBUB_RET_PATH_DCC_CFG4_1_BASE_IDX 2
#define mmDCHUBBUB_RET_PATH_DCC_CFG5_0 0x04da
#define mmDCHUBBUB_RET_PATH_DCC_CFG5_0_BASE_IDX 2
#define mmDCHUBBUB_RET_PATH_DCC_CFG5_1 0x04db
#define mmDCHUBBUB_RET_PATH_DCC_CFG5_1_BASE_IDX 2
#define mmDCHUBBUB_RET_PATH_DCC_CFG6_0 0x04dc
#define mmDCHUBBUB_RET_PATH_DCC_CFG6_0_BASE_IDX 2
#define mmDCHUBBUB_RET_PATH_DCC_CFG6_1 0x04dd
#define mmDCHUBBUB_RET_PATH_DCC_CFG6_1_BASE_IDX 2
#define mmDCHUBBUB_RET_PATH_DCC_CFG7_0 0x04de
#define mmDCHUBBUB_RET_PATH_DCC_CFG7_0_BASE_IDX 2
#define mmDCHUBBUB_RET_PATH_DCC_CFG7_1 0x04df
#define mmDCHUBBUB_RET_PATH_DCC_CFG7_1_BASE_IDX 2
#define mmDCHUBBUB_RET_PATH_MEM_PWR_CTRL 0x04e0
#define mmDCHUBBUB_RET_PATH_MEM_PWR_CTRL_BASE_IDX 2
#define mmDCHUBBUB_RET_PATH_MEM_PWR_STATUS 0x04e1
#define mmDCHUBBUB_RET_PATH_MEM_PWR_STATUS_BASE_IDX 2
#define mmDCHUBBUB_CRC_CTRL 0x04e2
#define mmDCHUBBUB_CRC_CTRL_BASE_IDX 2
#define mmDCHUBBUB_CRC0_VAL_R_G 0x04e3
#define mmDCHUBBUB_CRC0_VAL_R_G_BASE_IDX 2
#define mmDCHUBBUB_CRC0_VAL_B_A 0x04e4
#define mmDCHUBBUB_CRC0_VAL_B_A_BASE_IDX 2
#define mmDCHUBBUB_CRC1_VAL_R_G 0x04e5
#define mmDCHUBBUB_CRC1_VAL_R_G_BASE_IDX 2
#define mmDCHUBBUB_CRC1_VAL_B_A 0x04e6
#define mmDCHUBBUB_CRC1_VAL_B_A_BASE_IDX 2
// addressBlock: dce_dc_dchubbub_hubbub_dispdec
// base address: 0x0
#define mmDCHUBBUB_ARB_DF_REQ_OUTSTAND 0x0505
#define mmDCHUBBUB_ARB_DF_REQ_OUTSTAND_BASE_IDX 2
#define mmDCHUBBUB_ARB_SAT_LEVEL 0x0506
#define mmDCHUBBUB_ARB_SAT_LEVEL_BASE_IDX 2
#define mmDCHUBBUB_ARB_QOS_FORCE 0x0507
#define mmDCHUBBUB_ARB_QOS_FORCE_BASE_IDX 2
#define mmDCHUBBUB_ARB_DRAM_STATE_CNTL 0x0508
#define mmDCHUBBUB_ARB_DRAM_STATE_CNTL_BASE_IDX 2
#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A 0x0509
#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A_BASE_IDX 2
#define mmDCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A 0x050a
#define mmDCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A_BASE_IDX 2
#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A 0x050b
#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A_BASE_IDX 2
#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A 0x050c
#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A_BASE_IDX 2
#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A 0x050d
#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A_BASE_IDX 2
#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B 0x050e
#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B_BASE_IDX 2
#define mmDCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B 0x050f
#define mmDCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B_BASE_IDX 2
#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B 0x0510
#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B_BASE_IDX 2
#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B 0x0511
#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B_BASE_IDX 2
#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B 0x0512
#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B_BASE_IDX 2
#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C 0x0513
#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C_BASE_IDX 2
#define mmDCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C 0x0514
#define mmDCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C_BASE_IDX 2
#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C 0x0515
#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C_BASE_IDX 2
#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C 0x0516
#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C_BASE_IDX 2
#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C 0x0517
#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C_BASE_IDX 2
#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D 0x0518
#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D_BASE_IDX 2
#define mmDCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D 0x0519
#define mmDCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D_BASE_IDX 2
#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D 0x051a
#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D_BASE_IDX 2
#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D 0x051b
#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D_BASE_IDX 2
#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D 0x051c
#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D_BASE_IDX 2
#define mmDCHUBBUB_ARB_WATERMARK_CHANGE_CNTL 0x051d
#define mmDCHUBBUB_ARB_WATERMARK_CHANGE_CNTL_BASE_IDX 2
#define mmDCHUBBUB_ARB_TIMEOUT_ENABLE 0x051e
#define mmDCHUBBUB_ARB_TIMEOUT_ENABLE_BASE_IDX 2
#define mmDCHUBBUB_GLOBAL_TIMER_CNTL 0x051f
#define mmDCHUBBUB_GLOBAL_TIMER_CNTL_BASE_IDX 2
#define mmSURFACE_CHECK0_ADDRESS_LSB 0x0520
#define mmSURFACE_CHECK0_ADDRESS_LSB_BASE_IDX 2
#define mmSURFACE_CHECK0_ADDRESS_MSB 0x0521
#define mmSURFACE_CHECK0_ADDRESS_MSB_BASE_IDX 2
#define mmSURFACE_CHECK1_ADDRESS_LSB 0x0522
#define mmSURFACE_CHECK1_ADDRESS_LSB_BASE_IDX 2
#define mmSURFACE_CHECK1_ADDRESS_MSB 0x0523
#define mmSURFACE_CHECK1_ADDRESS_MSB_BASE_IDX 2
#define mmSURFACE_CHECK2_ADDRESS_LSB 0x0524
#define mmSURFACE_CHECK2_ADDRESS_LSB_BASE_IDX 2
#define mmSURFACE_CHECK2_ADDRESS_MSB 0x0525
#define mmSURFACE_CHECK2_ADDRESS_MSB_BASE_IDX 2
#define mmSURFACE_CHECK3_ADDRESS_LSB 0x0526
#define mmSURFACE_CHECK3_ADDRESS_LSB_BASE_IDX 2
#define mmSURFACE_CHECK3_ADDRESS_MSB 0x0527
#define mmSURFACE_CHECK3_ADDRESS_MSB_BASE_IDX 2
#define mmVTG0_CONTROL 0x0528
#define mmVTG0_CONTROL_BASE_IDX 2
#define mmVTG1_CONTROL 0x0529
#define mmVTG1_CONTROL_BASE_IDX 2
#define mmVTG2_CONTROL 0x052a
#define mmVTG2_CONTROL_BASE_IDX 2
#define mmVTG3_CONTROL 0x052b
#define mmVTG3_CONTROL_BASE_IDX 2
#define mmVTG4_CONTROL 0x052c
#define mmVTG4_CONTROL_BASE_IDX 2
#define mmVTG5_CONTROL 0x052d
#define mmVTG5_CONTROL_BASE_IDX 2
#define mmDCHUBBUB_SOFT_RESET 0x052e
#define mmDCHUBBUB_SOFT_RESET_BASE_IDX 2
#define mmDCHUBBUB_CLOCK_CNTL 0x052f
#define mmDCHUBBUB_CLOCK_CNTL_BASE_IDX 2
#define mmDCFCLK_CNTL 0x0530
#define mmDCFCLK_CNTL_BASE_IDX 2
#define mmDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL 0x0531
#define mmDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL_BASE_IDX 2
#define mmDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2 0x0532
#define mmDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2_BASE_IDX 2
#define mmDCHUBBUB_VLINE_SNAPSHOT 0x0533
#define mmDCHUBBUB_VLINE_SNAPSHOT_BASE_IDX 2
#define mmDCHUBBUB_SPARE 0x0534
#define mmDCHUBBUB_SPARE_BASE_IDX 2
#define mmDCHUBBUB_TEST_DEBUG_INDEX 0x053a
#define mmDCHUBBUB_TEST_DEBUG_INDEX_BASE_IDX 2
#define mmDCHUBBUB_TEST_DEBUG_DATA 0x053b
#define mmDCHUBBUB_TEST_DEBUG_DATA_BASE_IDX 2
// addressBlock: dce_dc_dchubbub_dchubbub_dcperfmon_dc_perfmon_dispdec
// base address: 0x1534
#define mmDC_PERFMON7_PERFCOUNTER_CNTL 0x054d
#define mmDC_PERFMON7_PERFCOUNTER_CNTL_BASE_IDX 2
#define mmDC_PERFMON7_PERFCOUNTER_CNTL2 0x054e
#define mmDC_PERFMON7_PERFCOUNTER_CNTL2_BASE_IDX 2
#define mmDC_PERFMON7_PERFCOUNTER_STATE 0x054f
#define mmDC_PERFMON7_PERFCOUNTER_STATE_BASE_IDX 2
#define mmDC_PERFMON7_PERFMON_CNTL 0x0550
#define mmDC_PERFMON7_PERFMON_CNTL_BASE_IDX 2
#define mmDC_PERFMON7_PERFMON_CNTL2 0x0551
#define mmDC_PERFMON7_PERFMON_CNTL2_BASE_IDX 2
#define mmDC_PERFMON7_PERFMON_CVALUE_INT_MISC 0x0552
#define mmDC_PERFMON7_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
#define mmDC_PERFMON7_PERFMON_CVALUE_LOW 0x0553
#define mmDC_PERFMON7_PERFMON_CVALUE_LOW_BASE_IDX 2
#define mmDC_PERFMON7_PERFMON_HI 0x0554
#define mmDC_PERFMON7_PERFMON_HI_BASE_IDX 2
#define mmDC_PERFMON7_PERFMON_LOW 0x0555
#define mmDC_PERFMON7_PERFMON_LOW_BASE_IDX 2
// addressBlock: dce_dc_dcbubp0_dispdec_hubp_dispdec
// base address: 0x0
#define mmHUBP0_DCSURF_SURFACE_CONFIG 0x0559
#define mmHUBP0_DCSURF_SURFACE_CONFIG_BASE_IDX 2
#define mmHUBP0_DCSURF_ADDR_CONFIG 0x055a
#define mmHUBP0_DCSURF_ADDR_CONFIG_BASE_IDX 2
#define mmHUBP0_DCSURF_TILING_CONFIG 0x055b
#define mmHUBP0_DCSURF_TILING_CONFIG_BASE_IDX 2
#define mmHUBP0_DCSURF_PRI_VIEWPORT_START 0x055c
#define mmHUBP0_DCSURF_PRI_VIEWPORT_START_BASE_IDX 2
#define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION 0x055d
#define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2
#define mmHUBP0_DCSURF_PRI_VIEWPORT_START_C 0x055e
#define mmHUBP0_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX 2
#define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C 0x055f
#define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX 2
#define mmHUBP0_DCSURF_SEC_VIEWPORT_START 0x0560
#define mmHUBP0_DCSURF_SEC_VIEWPORT_START_BASE_IDX 2
#define mmHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION 0x0561
#define mmHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX 2
#define mmHUBP0_DCSURF_SEC_VIEWPORT_START_C 0x0562
#define mmHUBP0_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX 2
#define mmHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C 0x0563
#define mmHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX 2
#define mmHUBP0_DCHUBP_REQ_SIZE_CONFIG 0x0564
#define mmHUBP0_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX 2
#define mmHUBP0_DCHUBP_REQ_SIZE_CONFIG_C 0x0565
#define mmHUBP0_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX 2
#define mmHUBP0_DCHUBP_CNTL 0x0566
#define mmHUBP0_DCHUBP_CNTL_BASE_IDX 2
#define mmHUBP0_HUBP_CLK_CNTL 0x0567
#define mmHUBP0_HUBP_CLK_CNTL_BASE_IDX 2
#define mmHUBP0_DCHUBP_VMPG_CONFIG 0x0568
#define mmHUBP0_DCHUBP_VMPG_CONFIG_BASE_IDX 2
#define mmHUBP0_HUBPREQ_DEBUG_DB 0x0569
#define mmHUBP0_HUBPREQ_DEBUG_DB_BASE_IDX 2
#define mmHUBP0_HUBPREQ_DEBUG 0x056a
#define mmHUBP0_HUBPREQ_DEBUG_BASE_IDX 2
#define mmHUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK 0x056e
#define mmHUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX 2
#define mmHUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK 0x056f
#define mmHUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX 2
// addressBlock: dce_dc_dcbubp0_dispdec_hubpreq_dispdec
// base address: 0x0
#define mmHUBPREQ0_DCSURF_SURFACE_PITCH 0x057b
#define mmHUBPREQ0_DCSURF_SURFACE_PITCH_BASE_IDX 2
#define mmHUBPREQ0_DCSURF_SURFACE_PITCH_C 0x057c
#define mmHUBPREQ0_DCSURF_SURFACE_PITCH_C_BASE_IDX 2
#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS 0x057d
#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2
#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0x057e
#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0x057f
#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2
#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x0580
#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS 0x0581
#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2
#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0x0582
#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0x0583
#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2
#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x0584
#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS 0x0585
#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX 2
#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH 0x0586
#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2
#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C 0x0587
#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX 2
#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0x0588
#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS 0x0589
#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX 2
#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH 0x058a
#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2
#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C 0x058b
#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX 2
#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0x058c
#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
#define mmHUBPREQ0_DCSURF_SURFACE_CONTROL 0x058d
#define mmHUBPREQ0_DCSURF_SURFACE_CONTROL_BASE_IDX 2
#define mmHUBPREQ0_DCSURF_FLIP_CONTROL 0x058e
#define mmHUBPREQ0_DCSURF_FLIP_CONTROL_BASE_IDX 2
#define mmHUBPREQ0_DCSURF_FLIP_CONTROL2 0x058f
#define mmHUBPREQ0_DCSURF_FLIP_CONTROL2_BASE_IDX 2
#define mmHUBPREQ0_DCSURF_FRAME_PACING_CONTROL 0x0590
#define mmHUBPREQ0_DCSURF_FRAME_PACING_CONTROL_BASE_IDX 2
#define mmHUBPREQ0_DCSURF_FRAME_PACING_TIME 0x0591
#define mmHUBPREQ0_DCSURF_FRAME_PACING_TIME_BASE_IDX 2
#define mmHUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT 0x0592
#define mmHUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX 2
#define mmHUBPREQ0_DCSURF_SURFACE_INUSE 0x0593
#define mmHUBPREQ0_DCSURF_SURFACE_INUSE_BASE_IDX 2
#define mmHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH 0x0594
#define mmHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX 2
#define mmHUBPREQ0_DCSURF_SURFACE_INUSE_C 0x0595
#define mmHUBPREQ0_DCSURF_SURFACE_INUSE_C_BASE_IDX 2
#define mmHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C 0x0596
#define mmHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX 2
#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE 0x0597
#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX 2
#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0x0598
#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX 2
#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C 0x0599
#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX 2
#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0x059a
#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX 2
#define mmHUBPREQ0_DCN_EXPANSION_MODE 0x059b
#define mmHUBPREQ0_DCN_EXPANSION_MODE_BASE_IDX 2
#define mmHUBPREQ0_DCN_TTU_QOS_WM 0x059c
#define mmHUBPREQ0_DCN_TTU_QOS_WM_BASE_IDX 2
#define mmHUBPREQ0_DCN_GLOBAL_TTU_CNTL 0x059d
#define mmHUBPREQ0_DCN_GLOBAL_TTU_CNTL_BASE_IDX 2
#define mmHUBPREQ0_DCN_SURF0_TTU_CNTL0 0x059e
#define mmHUBPREQ0_DCN_SURF0_TTU_CNTL0_BASE_IDX 2
#define mmHUBPREQ0_DCN_SURF0_TTU_CNTL1 0x059f
#define mmHUBPREQ0_DCN_SURF0_TTU_CNTL1_BASE_IDX 2
#define mmHUBPREQ0_DCN_SURF1_TTU_CNTL0 0x05a0
#define mmHUBPREQ0_DCN_SURF1_TTU_CNTL0_BASE_IDX 2
#define mmHUBPREQ0_DCN_SURF1_TTU_CNTL1 0x05a1
#define mmHUBPREQ0_DCN_SURF1_TTU_CNTL1_BASE_IDX 2
#define mmHUBPREQ0_DCN_CUR0_TTU_CNTL0 0x05a2
#define mmHUBPREQ0_DCN_CUR0_TTU_CNTL0_BASE_IDX 2
#define mmHUBPREQ0_DCN_CUR0_TTU_CNTL1 0x05a3
#define mmHUBPREQ0_DCN_CUR0_TTU_CNTL1_BASE_IDX 2
#define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB 0x05a4
#define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB_BASE_IDX 2
#define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB 0x05a5
#define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB_BASE_IDX 2
#define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB 0x05a6
#define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB_BASE_IDX 2
#define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB 0x05a7
#define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB_BASE_IDX 2
#define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB 0x05a8
#define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_BASE_IDX 2
#define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB 0x05a9
#define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_BASE_IDX 2
#define mmHUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB 0x05aa
#define mmHUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB_BASE_IDX 2
#define mmHUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB 0x05ab
#define mmHUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB_BASE_IDX 2
#define mmHUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB 0x05ac
#define mmHUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB_BASE_IDX 2
#define mmHUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB 0x05ad
#define mmHUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB_BASE_IDX 2
#define mmHUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB 0x05ae
#define mmHUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB_BASE_IDX 2
#define mmHUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB 0x05af
#define mmHUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB_BASE_IDX 2
#define mmHUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB 0x05b0
#define mmHUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB_BASE_IDX 2
#define mmHUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB 0x05b1
#define mmHUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB_BASE_IDX 2
#define mmHUBPREQ0_DCN_VM_CONTEXT0_STATUS 0x05b2
#define mmHUBPREQ0_DCN_VM_CONTEXT0_STATUS_BASE_IDX 2
#define mmHUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB 0x05b3
#define mmHUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB_BASE_IDX 2
#define mmHUBPREQ0_DCN_VM_CONTEXT0_CNTL 0x05b4
#define mmHUBPREQ0_DCN_VM_CONTEXT0_CNTL_BASE_IDX 2
#define mmHUBPREQ0_DCN_VM_MX_L1_TLB_CNTL 0x05b5
#define mmHUBPREQ0_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX 2
#define mmHUBPREQ0_BLANK_OFFSET_0 0x05b6
#define mmHUBPREQ0_BLANK_OFFSET_0_BASE_IDX 2
#define mmHUBPREQ0_BLANK_OFFSET_1 0x05b7
#define mmHUBPREQ0_BLANK_OFFSET_1_BASE_IDX 2
#define mmHUBPREQ0_DST_DIMENSIONS 0x05b8
#define mmHUBPREQ0_DST_DIMENSIONS_BASE_IDX 2
#define mmHUBPREQ0_DST_AFTER_SCALER 0x05b9
#define mmHUBPREQ0_DST_AFTER_SCALER_BASE_IDX 2
#define mmHUBPREQ0_PREFETCH_SETTINS 0x05ba
#define mmHUBPREQ0_PREFETCH_SETTINS_BASE_IDX 2
#define mmHUBPREQ0_PREFETCH_SETTINS_C 0x05bb
#define mmHUBPREQ0_PREFETCH_SETTINS_C_BASE_IDX 2
#define mmHUBPREQ0_VBLANK_PARAMETERS_0 0x05bc
#define mmHUBPREQ0_VBLANK_PARAMETERS_0_BASE_IDX 2
#define mmHUBPREQ0_VBLANK_PARAMETERS_1 0x05bd
#define mmHUBPREQ0_VBLANK_PARAMETERS_1_BASE_IDX 2
#define mmHUBPREQ0_VBLANK_PARAMETERS_2 0x05be
#define mmHUBPREQ0_VBLANK_PARAMETERS_2_BASE_IDX 2
#define mmHUBPREQ0_VBLANK_PARAMETERS_3 0x05bf
#define mmHUBPREQ0_VBLANK_PARAMETERS_3_BASE_IDX 2
#define mmHUBPREQ0_VBLANK_PARAMETERS_4 0x05c0
#define mmHUBPREQ0_VBLANK_PARAMETERS_4_BASE_IDX 2
#define mmHUBPREQ0_NOM_PARAMETERS_0 0x05c1
#define mmHUBPREQ0_NOM_PARAMETERS_0_BASE_IDX 2
#define mmHUBPREQ0_NOM_PARAMETERS_1 0x05c2
#define mmHUBPREQ0_NOM_PARAMETERS_1_BASE_IDX 2
#define mmHUBPREQ0_NOM_PARAMETERS_2 0x05c3
#define mmHUBPREQ0_NOM_PARAMETERS_2_BASE_IDX 2
#define mmHUBPREQ0_NOM_PARAMETERS_3 0x05c4
#define mmHUBPREQ0_NOM_PARAMETERS_3_BASE_IDX 2
#define mmHUBPREQ0_NOM_PARAMETERS_4 0x05c5
#define mmHUBPREQ0_NOM_PARAMETERS_4_BASE_IDX 2
#define mmHUBPREQ0_NOM_PARAMETERS_5 0x05c6
#define mmHUBPREQ0_NOM_PARAMETERS_5_BASE_IDX 2
#define mmHUBPREQ0_NOM_PARAMETERS_6 0x05c7
#define mmHUBPREQ0_NOM_PARAMETERS_6_BASE_IDX 2
#define mmHUBPREQ0_NOM_PARAMETERS_7 0x05c8
#define mmHUBPREQ0_NOM_PARAMETERS_7_BASE_IDX 2
#define mmHUBPREQ0_PER_LINE_DELIVERY_PRE 0x05c9
#define mmHUBPREQ0_PER_LINE_DELIVERY_PRE_BASE_IDX 2
#define mmHUBPREQ0_PER_LINE_DELIVERY 0x05ca
#define mmHUBPREQ0_PER_LINE_DELIVERY_BASE_IDX 2
#define mmHUBPREQ0_CURSOR_SETTINS 0x05cb
#define mmHUBPREQ0_CURSOR_SETTINS_BASE_IDX 2
#define mmHUBPREQ0_REF_FREQ_TO_PIX_FREQ 0x05cc
#define mmHUBPREQ0_REF_FREQ_TO_PIX_FREQ_BASE_IDX 2
#define mmHUBPREQ0_HUBPREQ_MEM_PWR_CTRL 0x05cd
#define mmHUBPREQ0_HUBPREQ_MEM_PWR_CTRL_BASE_IDX 2
#define mmHUBPREQ0_HUBPREQ_MEM_PWR_STATUS 0x05ce
#define mmHUBPREQ0_HUBPREQ_MEM_PWR_STATUS_BASE_IDX 2
// addressBlock: dce_dc_dcbubp0_dispdec_hubpret_dispdec
// base address: 0x0
#define mmHUBPRET0_HUBPRET_CONTROL 0x05e0
#define mmHUBPRET0_HUBPRET_CONTROL_BASE_IDX 2
#define mmHUBPRET0_HUBPRET_MEM_PWR_CTRL 0x05e1
#define mmHUBPRET0_HUBPRET_MEM_PWR_CTRL_BASE_IDX 2
#define mmHUBPRET0_HUBPRET_MEM_PWR_STATUS 0x05e2
#define mmHUBPRET0_HUBPRET_MEM_PWR_STATUS_BASE_IDX 2
#define mmHUBPRET0_HUBPRET_READ_LINE_CTRL0 0x05e3
#define mmHUBPRET0_HUBPRET_READ_LINE_CTRL0_BASE_IDX 2
#define mmHUBPRET0_HUBPRET_READ_LINE_CTRL1 0x05e4
#define mmHUBPRET0_HUBPRET_READ_LINE_CTRL1_BASE_IDX 2
#define mmHUBPRET0_HUBPRET_READ_LINE0 0x05e5
#define mmHUBPRET0_HUBPRET_READ_LINE0_BASE_IDX 2
#define mmHUBPRET0_HUBPRET_READ_LINE1 0x05e6
#define mmHUBPRET0_HUBPRET_READ_LINE1_BASE_IDX 2
#define mmHUBPRET0_HUBPRET_INTERRUPT 0x05e7
#define mmHUBPRET0_HUBPRET_INTERRUPT_BASE_IDX 2
#define mmHUBPRET0_HUBPRET_READ_LINE_VALUE 0x05e8
#define mmHUBPRET0_HUBPRET_READ_LINE_VALUE_BASE_IDX 2
#define mmHUBPRET0_HUBPRET_READ_LINE_STATUS 0x05e9
#define mmHUBPRET0_HUBPRET_READ_LINE_STATUS_BASE_IDX 2
// addressBlock: dce_dc_dcbubp0_dispdec_cursor_dispdec
// base address: 0x0
#define mmCURSOR0_CURSOR_CONTROL 0x05ec
#define mmCURSOR0_CURSOR_CONTROL_BASE_IDX 2
#define mmCURSOR0_CURSOR_SURFACE_ADDRESS 0x05ed
#define mmCURSOR0_CURSOR_SURFACE_ADDRESS_BASE_IDX 2
#define mmCURSOR0_CURSOR_SURFACE_ADDRESS_HIGH 0x05ee
#define mmCURSOR0_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX 2
#define mmCURSOR0_CURSOR_SIZE 0x05ef
#define mmCURSOR0_CURSOR_SIZE_BASE_IDX 2
#define mmCURSOR0_CURSOR_POSITION 0x05f0
#define mmCURSOR0_CURSOR_POSITION_BASE_IDX 2
#define mmCURSOR0_CURSOR_HOT_SPOT 0x05f1
#define mmCURSOR0_CURSOR_HOT_SPOT_BASE_IDX 2
#define mmCURSOR0_CURSOR_STEREO_CONTROL 0x05f2
#define mmCURSOR0_CURSOR_STEREO_CONTROL_BASE_IDX 2
#define mmCURSOR0_CURSOR_DST_OFFSET 0x05f3
#define mmCURSOR0_CURSOR_DST_OFFSET_BASE_IDX 2
#define mmCURSOR0_CURSOR_MEM_PWR_CTRL 0x05f4
#define mmCURSOR0_CURSOR_MEM_PWR_CTRL_BASE_IDX 2
#define mmCURSOR0_CURSOR_MEM_PWR_STATUS 0x05f5
#define mmCURSOR0_CURSOR_MEM_PWR_STATUS_BASE_IDX 2
// addressBlock: dce_dc_dcbubp0_dispdec_hubp_dcperfmon_dc_perfmon_dispdec
// base address: 0x1844
#define mmDC_PERFMON8_PERFCOUNTER_CNTL 0x0611
#define mmDC_PERFMON8_PERFCOUNTER_CNTL_BASE_IDX 2
#define mmDC_PERFMON8_PERFCOUNTER_CNTL2 0x0612
#define mmDC_PERFMON8_PERFCOUNTER_CNTL2_BASE_IDX 2
#define mmDC_PERFMON8_PERFCOUNTER_STATE 0x0613
#define mmDC_PERFMON8_PERFCOUNTER_STATE_BASE_IDX 2
#define mmDC_PERFMON8_PERFMON_CNTL 0x0614
#define mmDC_PERFMON8_PERFMON_CNTL_BASE_IDX 2
#define mmDC_PERFMON8_PERFMON_CNTL2 0x0615
#define mmDC_PERFMON8_PERFMON_CNTL2_BASE_IDX 2
#define mmDC_PERFMON8_PERFMON_CVALUE_INT_MISC 0x0616
#define mmDC_PERFMON8_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
#define mmDC_PERFMON8_PERFMON_CVALUE_LOW 0x0617
#define mmDC_PERFMON8_PERFMON_CVALUE_LOW_BASE_IDX 2
#define mmDC_PERFMON8_PERFMON_HI 0x0618
#define mmDC_PERFMON8_PERFMON_HI_BASE_IDX 2
#define mmDC_PERFMON8_PERFMON_LOW 0x0619
#define mmDC_PERFMON8_PERFMON_LOW_BASE_IDX 2
// addressBlock: dce_dc_dcbubp1_dispdec_hubp_dispdec
// base address: 0x310
#define mmHUBP1_DCSURF_SURFACE_CONFIG 0x061d
#define mmHUBP1_DCSURF_SURFACE_CONFIG_BASE_IDX 2
#define mmHUBP1_DCSURF_ADDR_CONFIG 0x061e
#define mmHUBP1_DCSURF_ADDR_CONFIG_BASE_IDX 2
#define mmHUBP1_DCSURF_TILING_CONFIG 0x061f
#define mmHUBP1_DCSURF_TILING_CONFIG_BASE_IDX 2
#define mmHUBP1_DCSURF_PRI_VIEWPORT_START 0x0620
#define mmHUBP1_DCSURF_PRI_VIEWPORT_START_BASE_IDX 2
#define mmHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION 0x0621
#define mmHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2
#define mmHUBP1_DCSURF_PRI_VIEWPORT_START_C 0x0622
#define mmHUBP1_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX 2
#define mmHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C 0x0623
#define mmHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX 2
#define mmHUBP1_DCSURF_SEC_VIEWPORT_START 0x0624
#define mmHUBP1_DCSURF_SEC_VIEWPORT_START_BASE_IDX 2
#define mmHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION 0x0625
#define mmHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX 2
#define mmHUBP1_DCSURF_SEC_VIEWPORT_START_C 0x0626
#define mmHUBP1_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX 2
#define mmHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C 0x0627
#define mmHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX 2
#define mmHUBP1_DCHUBP_REQ_SIZE_CONFIG 0x0628
#define mmHUBP1_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX 2
#define mmHUBP1_DCHUBP_REQ_SIZE_CONFIG_C 0x0629
#define mmHUBP1_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX 2
#define mmHUBP1_DCHUBP_CNTL 0x062a
#define mmHUBP1_DCHUBP_CNTL_BASE_IDX 2
#define mmHUBP1_HUBP_CLK_CNTL 0x062b
#define mmHUBP1_HUBP_CLK_CNTL_BASE_IDX 2
#define mmHUBP1_DCHUBP_VMPG_CONFIG 0x062c
#define mmHUBP1_DCHUBP_VMPG_CONFIG_BASE_IDX 2
#define mmHUBP1_HUBPREQ_DEBUG_DB 0x062d
#define mmHUBP1_HUBPREQ_DEBUG_DB_BASE_IDX 2
#define mmHUBP1_HUBPREQ_DEBUG 0x062e
#define mmHUBP1_HUBPREQ_DEBUG_BASE_IDX 2
#define mmHUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK 0x0632
#define mmHUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX 2
#define mmHUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK 0x0633
#define mmHUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX 2
// addressBlock: dce_dc_dcbubp1_dispdec_hubpreq_dispdec
// base address: 0x310
#define mmHUBPREQ1_DCSURF_SURFACE_PITCH 0x063f
#define mmHUBPREQ1_DCSURF_SURFACE_PITCH_BASE_IDX 2
#define mmHUBPREQ1_DCSURF_SURFACE_PITCH_C 0x0640
#define mmHUBPREQ1_DCSURF_SURFACE_PITCH_C_BASE_IDX 2
#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS 0x0641
#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2
#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0x0642
#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0x0643
#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2
#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x0644
#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS 0x0645
#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2
#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0x0646
#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0x0647
#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2
#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x0648
#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS 0x0649
#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX 2
#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH 0x064a
#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2
#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C 0x064b
#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX 2
#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0x064c
#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS 0x064d
#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX 2
#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH 0x064e
#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2
#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C 0x064f
#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX 2
#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0x0650
#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
#define mmHUBPREQ1_DCSURF_SURFACE_CONTROL 0x0651
#define mmHUBPREQ1_DCSURF_SURFACE_CONTROL_BASE_IDX 2
#define mmHUBPREQ1_DCSURF_FLIP_CONTROL 0x0652
#define mmHUBPREQ1_DCSURF_FLIP_CONTROL_BASE_IDX 2
#define mmHUBPREQ1_DCSURF_FLIP_CONTROL2 0x0653
#define mmHUBPREQ1_DCSURF_FLIP_CONTROL2_BASE_IDX 2
#define mmHUBPREQ1_DCSURF_FRAME_PACING_CONTROL 0x0654
#define mmHUBPREQ1_DCSURF_FRAME_PACING_CONTROL_BASE_IDX 2
#define mmHUBPREQ1_DCSURF_FRAME_PACING_TIME 0x0655
#define mmHUBPREQ1_DCSURF_FRAME_PACING_TIME_BASE_IDX 2
#define mmHUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT 0x0656
#define mmHUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX 2
#define mmHUBPREQ1_DCSURF_SURFACE_INUSE 0x0657
#define mmHUBPREQ1_DCSURF_SURFACE_INUSE_BASE_IDX 2
#define mmHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH 0x0658
#define mmHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX 2
#define mmHUBPREQ1_DCSURF_SURFACE_INUSE_C 0x0659
#define mmHUBPREQ1_DCSURF_SURFACE_INUSE_C_BASE_IDX 2
#define mmHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C 0x065a
#define mmHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX 2
#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE 0x065b
#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX 2
#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0x065c
#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX 2
#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C 0x065d
#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX 2
#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0x065e
#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX 2
#define mmHUBPREQ1_DCN_EXPANSION_MODE 0x065f
#define mmHUBPREQ1_DCN_EXPANSION_MODE_BASE_IDX 2
#define mmHUBPREQ1_DCN_TTU_QOS_WM 0x0660
#define mmHUBPREQ1_DCN_TTU_QOS_WM_BASE_IDX 2
#define mmHUBPREQ1_DCN_GLOBAL_TTU_CNTL 0x0661
#define mmHUBPREQ1_DCN_GLOBAL_TTU_CNTL_BASE_IDX 2
#define mmHUBPREQ1_DCN_SURF0_TTU_CNTL0 0x0662
#define mmHUBPREQ1_DCN_SURF0_TTU_CNTL0_BASE_IDX 2
#define mmHUBPREQ1_DCN_SURF0_TTU_CNTL1 0x0663
#define mmHUBPREQ1_DCN_SURF0_TTU_CNTL1_BASE_IDX 2
#define mmHUBPREQ1_DCN_SURF1_TTU_CNTL0 0x0664
#define mmHUBPREQ1_DCN_SURF1_TTU_CNTL0_BASE_IDX 2
#define mmHUBPREQ1_DCN_SURF1_TTU_CNTL1 0x0665
#define mmHUBPREQ1_DCN_SURF1_TTU_CNTL1_BASE_IDX 2
#define mmHUBPREQ1_DCN_CUR0_TTU_CNTL0 0x0666
#define mmHUBPREQ1_DCN_CUR0_TTU_CNTL0_BASE_IDX 2
#define mmHUBPREQ1_DCN_CUR0_TTU_CNTL1 0x0667
#define mmHUBPREQ1_DCN_CUR0_TTU_CNTL1_BASE_IDX 2
#define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB 0x0668
#define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB_BASE_IDX 2
#define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB 0x0669
#define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB_BASE_IDX 2
#define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB 0x066a
#define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB_BASE_IDX 2
#define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB 0x066b
#define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB_BASE_IDX 2
#define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB 0x066c
#define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_BASE_IDX 2
#define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB 0x066d
#define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_BASE_IDX 2
#define mmHUBPREQ1_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB 0x066e
#define mmHUBPREQ1_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB_BASE_IDX 2
#define mmHUBPREQ1_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB 0x066f
#define mmHUBPREQ1_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB_BASE_IDX 2
#define mmHUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB 0x0670
#define mmHUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB_BASE_IDX 2
#define mmHUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB 0x0671
#define mmHUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB_BASE_IDX 2
#define mmHUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB 0x0672
#define mmHUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB_BASE_IDX 2
#define mmHUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB 0x0673
#define mmHUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB_BASE_IDX 2
#define mmHUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB 0x0674
#define mmHUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB_BASE_IDX 2
#define mmHUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB 0x0675
#define mmHUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB_BASE_IDX 2
#define mmHUBPREQ1_DCN_VM_CONTEXT0_STATUS 0x0676
#define mmHUBPREQ1_DCN_VM_CONTEXT0_STATUS_BASE_IDX 2
#define mmHUBPREQ1_DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB 0x0677
#define mmHUBPREQ1_DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB_BASE_IDX 2
#define mmHUBPREQ1_DCN_VM_CONTEXT0_CNTL 0x0678
#define mmHUBPREQ1_DCN_VM_CONTEXT0_CNTL_BASE_IDX 2
#define mmHUBPREQ1_DCN_VM_MX_L1_TLB_CNTL 0x0679
#define mmHUBPREQ1_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX 2
#define mmHUBPREQ1_BLANK_OFFSET_0 0x067a
#define mmHUBPREQ1_BLANK_OFFSET_0_BASE_IDX 2
#define mmHUBPREQ1_BLANK_OFFSET_1 0x067b
#define mmHUBPREQ1_BLANK_OFFSET_1_BASE_IDX 2
#define mmHUBPREQ1_DST_DIMENSIONS 0x067c
#define mmHUBPREQ1_DST_DIMENSIONS_BASE_IDX 2
#define mmHUBPREQ1_DST_AFTER_SCALER 0x067d
#define mmHUBPREQ1_DST_AFTER_SCALER_BASE_IDX 2
#define mmHUBPREQ1_PREFETCH_SETTINS 0x067e
#define mmHUBPREQ1_PREFETCH_SETTINS_BASE_IDX 2
#define mmHUBPREQ1_PREFETCH_SETTINS_C 0x067f
#define mmHUBPREQ1_PREFETCH_SETTINS_C_BASE_IDX 2
#define mmHUBPREQ1_VBLANK_PARAMETERS_0 0x0680
#define mmHUBPREQ1_VBLANK_PARAMETERS_0_BASE_IDX 2
#define mmHUBPREQ1_VBLANK_PARAMETERS_1 0x0681
#define mmHUBPREQ1_VBLANK_PARAMETERS_1_BASE_IDX 2
#define mmHUBPREQ1_VBLANK_PARAMETERS_2 0x0682
#define mmHUBPREQ1_VBLANK_PARAMETERS_2_BASE_IDX 2
#define mmHUBPREQ1_VBLANK_PARAMETERS_3 0x0683
#define mmHUBPREQ1_VBLANK_PARAMETERS_3_BASE_IDX 2
#define mmHUBPREQ1_VBLANK_PARAMETERS_4 0x0684
#define mmHUBPREQ1_VBLANK_PARAMETERS_4_BASE_IDX 2
#define mmHUBPREQ1_NOM_PARAMETERS_0 0x0685
#define mmHUBPREQ1_NOM_PARAMETERS_0_BASE_IDX 2
#define mmHUBPREQ1_NOM_PARAMETERS_1 0x0686
#define mmHUBPREQ1_NOM_PARAMETERS_1_BASE_IDX 2
#define mmHUBPREQ1_NOM_PARAMETERS_2 0x0687
#define mmHUBPREQ1_NOM_PARAMETERS_2_BASE_IDX 2
#define mmHUBPREQ1_NOM_PARAMETERS_3 0x0688
#define mmHUBPREQ1_NOM_PARAMETERS_3_BASE_IDX 2
#define mmHUBPREQ1_NOM_PARAMETERS_4 0x0689
#define mmHUBPREQ1_NOM_PARAMETERS_4_BASE_IDX 2
#define mmHUBPREQ1_NOM_PARAMETERS_5 0x068a
#define mmHUBPREQ1_NOM_PARAMETERS_5_BASE_IDX 2
#define mmHUBPREQ1_NOM_PARAMETERS_6 0x068b
#define mmHUBPREQ1_NOM_PARAMETERS_6_BASE_IDX 2
#define mmHUBPREQ1_NOM_PARAMETERS_7 0x068c
#define mmHUBPREQ1_NOM_PARAMETERS_7_BASE_IDX 2
#define mmHUBPREQ1_PER_LINE_DELIVERY_PRE 0x068d
#define mmHUBPREQ1_PER_LINE_DELIVERY_PRE_BASE_IDX 2
#define mmHUBPREQ1_PER_LINE_DELIVERY 0x068e
#define mmHUBPREQ1_PER_LINE_DELIVERY_BASE_IDX 2
#define mmHUBPREQ1_CURSOR_SETTINS 0x068f
#define mmHUBPREQ1_CURSOR_SETTINS_BASE_IDX 2
#define mmHUBPREQ1_REF_FREQ_TO_PIX_FREQ 0x0690
#define mmHUBPREQ1_REF_FREQ_TO_PIX_FREQ_BASE_IDX 2
#define mmHUBPREQ1_HUBPREQ_MEM_PWR_CTRL 0x0691
#define mmHUBPREQ1_HUBPREQ_MEM_PWR_CTRL_BASE_IDX 2
#define mmHUBPREQ1_HUBPREQ_MEM_PWR_STATUS 0x0692
#define mmHUBPREQ1_HUBPREQ_MEM_PWR_STATUS_BASE_IDX 2
// addressBlock: dce_dc_dcbubp1_dispdec_hubpret_dispdec
// base address: 0x310
#define mmHUBPRET1_HUBPRET_CONTROL 0x06a4
#define mmHUBPRET1_HUBPRET_CONTROL_BASE_IDX 2
#define mmHUBPRET1_HUBPRET_MEM_PWR_CTRL 0x06a5
#define mmHUBPRET1_HUBPRET_MEM_PWR_CTRL_BASE_IDX 2
#define mmHUBPRET1_HUBPRET_MEM_PWR_STATUS 0x06a6
#define mmHUBPRET1_HUBPRET_MEM_PWR_STATUS_BASE_IDX 2
#define mmHUBPRET1_HUBPRET_READ_LINE_CTRL0 0x06a7
#define mmHUBPRET1_HUBPRET_READ_LINE_CTRL0_BASE_IDX 2
#define mmHUBPRET1_HUBPRET_READ_LINE_CTRL1 0x06a8
#define mmHUBPRET1_HUBPRET_READ_LINE_CTRL1_BASE_IDX 2
#define mmHUBPRET1_HUBPRET_READ_LINE0 0x06a9
#define mmHUBPRET1_HUBPRET_READ_LINE0_BASE_IDX 2
#define mmHUBPRET1_HUBPRET_READ_LINE1 0x06aa
#define mmHUBPRET1_HUBPRET_READ_LINE1_BASE_IDX 2
#define mmHUBPRET1_HUBPRET_INTERRUPT 0x06ab
#define mmHUBPRET1_HUBPRET_INTERRUPT_BASE_IDX 2
#define mmHUBPRET1_HUBPRET_READ_LINE_VALUE 0x06ac
#define mmHUBPRET1_HUBPRET_READ_LINE_VALUE_BASE_IDX 2
#define mmHUBPRET1_HUBPRET_READ_LINE_STATUS 0x06ad
#define mmHUBPRET1_HUBPRET_READ_LINE_STATUS_BASE_IDX 2
// addressBlock: dce_dc_dcbubp1_dispdec_cursor_dispdec
// base address: 0x310
#define mmCURSOR1_CURSOR_CONTROL 0x06b0
#define mmCURSOR1_CURSOR_CONTROL_BASE_IDX 2
#define mmCURSOR1_CURSOR_SURFACE_ADDRESS 0x06b1
#define mmCURSOR1_CURSOR_SURFACE_ADDRESS_BASE_IDX 2
#define mmCURSOR1_CURSOR_SURFACE_ADDRESS_HIGH 0x06b2
#define mmCURSOR1_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX 2
#define mmCURSOR1_CURSOR_SIZE 0x06b3
#define mmCURSOR1_CURSOR_SIZE_BASE_IDX 2
#define mmCURSOR1_CURSOR_POSITION 0x06b4
#define mmCURSOR1_CURSOR_POSITION_BASE_IDX 2
#define mmCURSOR1_CURSOR_HOT_SPOT 0x06b5
#define mmCURSOR1_CURSOR_HOT_SPOT_BASE_IDX 2
#define mmCURSOR1_CURSOR_STEREO_CONTROL 0x06b6
#define mmCURSOR1_CURSOR_STEREO_CONTROL_BASE_IDX 2
#define mmCURSOR1_CURSOR_DST_OFFSET 0x06b7
#define mmCURSOR1_CURSOR_DST_OFFSET_BASE_IDX 2
#define mmCURSOR1_CURSOR_MEM_PWR_CTRL 0x06b8
#define mmCURSOR1_CURSOR_MEM_PWR_CTRL_BASE_IDX 2
#define mmCURSOR1_CURSOR_MEM_PWR_STATUS 0x06b9
#define mmCURSOR1_CURSOR_MEM_PWR_STATUS_BASE_IDX 2
// addressBlock: dce_dc_dcbubp1_dispdec_hubp_dcperfmon_dc_perfmon_dispdec
// base address: 0x1b54
#define mmDC_PERFMON9_PERFCOUNTER_CNTL 0x06d5
#define mmDC_PERFMON9_PERFCOUNTER_CNTL_BASE_IDX 2
#define mmDC_PERFMON9_PERFCOUNTER_CNTL2 0x06d6
#define mmDC_PERFMON9_PERFCOUNTER_CNTL2_BASE_IDX 2
#define mmDC_PERFMON9_PERFCOUNTER_STATE 0x06d7
#define mmDC_PERFMON9_PERFCOUNTER_STATE_BASE_IDX 2
#define mmDC_PERFMON9_PERFMON_CNTL 0x06d8
#define mmDC_PERFMON9_PERFMON_CNTL_BASE_IDX 2
#define mmDC_PERFMON9_PERFMON_CNTL2 0x06d9
#define mmDC_PERFMON9_PERFMON_CNTL2_BASE_IDX 2
#define mmDC_PERFMON9_PERFMON_CVALUE_INT_MISC 0x06da
#define mmDC_PERFMON9_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
#define mmDC_PERFMON9_PERFMON_CVALUE_LOW 0x06db
#define mmDC_PERFMON9_PERFMON_CVALUE_LOW_BASE_IDX 2
#define mmDC_PERFMON9_PERFMON_HI 0x06dc
#define mmDC_PERFMON9_PERFMON_HI_BASE_IDX 2
#define mmDC_PERFMON9_PERFMON_LOW 0x06dd
#define mmDC_PERFMON9_PERFMON_LOW_BASE_IDX 2
// addressBlock: dce_dc_dcbubp2_dispdec_hubp_dispdec
// base address: 0x620
#define mmHUBP2_DCSURF_SURFACE_CONFIG 0x06e1
#define mmHUBP2_DCSURF_SURFACE_CONFIG_BASE_IDX 2
#define mmHUBP2_DCSURF_ADDR_CONFIG 0x06e2
#define mmHUBP2_DCSURF_ADDR_CONFIG_BASE_IDX 2
#define mmHUBP2_DCSURF_TILING_CONFIG 0x06e3
#define mmHUBP2_DCSURF_TILING_CONFIG_BASE_IDX 2
#define mmHUBP2_DCSURF_PRI_VIEWPORT_START 0x06e4
#define mmHUBP2_DCSURF_PRI_VIEWPORT_START_BASE_IDX 2
#define mmHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION 0x06e5
#define mmHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2
#define mmHUBP2_DCSURF_PRI_VIEWPORT_START_C 0x06e6
#define mmHUBP2_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX 2
#define mmHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C 0x06e7
#define mmHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX 2
#define mmHUBP2_DCSURF_SEC_VIEWPORT_START 0x06e8
#define mmHUBP2_DCSURF_SEC_VIEWPORT_START_BASE_IDX 2
#define mmHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION 0x06e9
#define mmHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX 2
#define mmHUBP2_DCSURF_SEC_VIEWPORT_START_C 0x06ea
#define mmHUBP2_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX 2
#define mmHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C 0x06eb
#define mmHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX 2
#define mmHUBP2_DCHUBP_REQ_SIZE_CONFIG 0x06ec
#define mmHUBP2_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX 2
#define mmHUBP2_DCHUBP_REQ_SIZE_CONFIG_C 0x06ed
#define mmHUBP2_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX 2
#define mmHUBP2_DCHUBP_CNTL 0x06ee
#define mmHUBP2_DCHUBP_CNTL_BASE_IDX 2
#define mmHUBP2_HUBP_CLK_CNTL 0x06ef
#define mmHUBP2_HUBP_CLK_CNTL_BASE_IDX 2
#define mmHUBP2_DCHUBP_VMPG_CONFIG 0x06f0
#define mmHUBP2_DCHUBP_VMPG_CONFIG_BASE_IDX 2
#define mmHUBP2_HUBPREQ_DEBUG_DB 0x06f1
#define mmHUBP2_HUBPREQ_DEBUG_DB_BASE_IDX 2
#define mmHUBP2_HUBPREQ_DEBUG 0x06f2
#define mmHUBP2_HUBPREQ_DEBUG_BASE_IDX 2
#define mmHUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK 0x06f6
#define mmHUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX 2
#define mmHUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK 0x06f7
#define mmHUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX 2
// addressBlock: dce_dc_dcbubp2_dispdec_hubpreq_dispdec
// base address: 0x620
#define mmHUBPREQ2_DCSURF_SURFACE_PITCH 0x0703
#define mmHUBPREQ2_DCSURF_SURFACE_PITCH_BASE_IDX 2
#define mmHUBPREQ2_DCSURF_SURFACE_PITCH_C 0x0704
#define mmHUBPREQ2_DCSURF_SURFACE_PITCH_C_BASE_IDX 2
#define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS 0x0705
#define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2
#define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0x0706
#define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
#define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0x0707
#define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2
#define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x0708
#define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
#define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS 0x0709
#define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2
#define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0x070a
#define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
#define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0x070b
#define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2
#define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x070c
#define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
#define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS 0x070d
#define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX 2
#define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH 0x070e
#define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2
#define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C 0x070f
#define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX 2
#define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0x0710
#define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
#define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS 0x0711
#define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX 2
#define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH 0x0712
#define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2
#define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C 0x0713
#define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX 2
#define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0x0714
#define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
#define mmHUBPREQ2_DCSURF_SURFACE_CONTROL 0x0715
#define mmHUBPREQ2_DCSURF_SURFACE_CONTROL_BASE_IDX 2
#define mmHUBPREQ2_DCSURF_FLIP_CONTROL 0x0716
#define mmHUBPREQ2_DCSURF_FLIP_CONTROL_BASE_IDX 2
#define mmHUBPREQ2_DCSURF_FLIP_CONTROL2 0x0717
#define mmHUBPREQ2_DCSURF_FLIP_CONTROL2_BASE_IDX 2
#define mmHUBPREQ2_DCSURF_FRAME_PACING_CONTROL 0x0718
#define mmHUBPREQ2_DCSURF_FRAME_PACING_CONTROL_BASE_IDX 2
#define mmHUBPREQ2_DCSURF_FRAME_PACING_TIME 0x0719
#define mmHUBPREQ2_DCSURF_FRAME_PACING_TIME_BASE_IDX 2
#define mmHUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT 0x071a
#define mmHUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX 2
#define mmHUBPREQ2_DCSURF_SURFACE_INUSE 0x071b
#define mmHUBPREQ2_DCSURF_SURFACE_INUSE_BASE_IDX 2
#define mmHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH 0x071c
#define mmHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX 2
#define mmHUBPREQ2_DCSURF_SURFACE_INUSE_C 0x071d
#define mmHUBPREQ2_DCSURF_SURFACE_INUSE_C_BASE_IDX 2
#define mmHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C 0x071e
#define mmHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX 2
#define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE 0x071f
#define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX 2
#define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0x0720
#define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX 2
#define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C 0x0721
#define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX 2
#define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0x0722
#define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX 2
#define mmHUBPREQ2_DCN_EXPANSION_MODE 0x0723
#define mmHUBPREQ2_DCN_EXPANSION_MODE_BASE_IDX 2
#define mmHUBPREQ2_DCN_TTU_QOS_WM 0x0724
#define mmHUBPREQ2_DCN_TTU_QOS_WM_BASE_IDX 2
#define mmHUBPREQ2_DCN_GLOBAL_TTU_CNTL 0x0725
#define mmHUBPREQ2_DCN_GLOBAL_TTU_CNTL_BASE_IDX 2
#define mmHUBPREQ2_DCN_SURF0_TTU_CNTL0 0x0726
#define mmHUBPREQ2_DCN_SURF0_TTU_CNTL0_BASE_IDX 2
#define mmHUBPREQ2_DCN_SURF0_TTU_CNTL1 0x0727
#define mmHUBPREQ2_DCN_SURF0_TTU_CNTL1_BASE_IDX 2
#define mmHUBPREQ2_DCN_SURF1_TTU_CNTL0 0x0728
#define mmHUBPREQ2_DCN_SURF1_TTU_CNTL0_BASE_IDX 2
#define mmHUBPREQ2_DCN_SURF1_TTU_CNTL1 0x0729
#define mmHUBPREQ2_DCN_SURF1_TTU_CNTL1_BASE_IDX 2
#define mmHUBPREQ2_DCN_CUR0_TTU_CNTL0 0x072a
#define mmHUBPREQ2_DCN_CUR0_TTU_CNTL0_BASE_IDX 2
#define mmHUBPREQ2_DCN_CUR0_TTU_CNTL1 0x072b
#define mmHUBPREQ2_DCN_CUR0_TTU_CNTL1_BASE_IDX 2
#define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB 0x072c
#define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB_BASE_IDX 2
#define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB 0x072d
#define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB_BASE_IDX 2
#define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB 0x072e
#define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB_BASE_IDX 2
#define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB 0x072f
#define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB_BASE_IDX 2
#define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB 0x0730
#define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_BASE_IDX 2
#define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB 0x0731
#define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_BASE_IDX 2
#define mmHUBPREQ2_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB 0x0732
#define mmHUBPREQ2_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB_BASE_IDX 2
#define mmHUBPREQ2_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB 0x0733
#define mmHUBPREQ2_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB_BASE_IDX 2
#define mmHUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB 0x0734
#define mmHUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB_BASE_IDX 2
#define mmHUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB 0x0735
#define mmHUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB_BASE_IDX 2
#define mmHUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB 0x0736
#define mmHUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB_BASE_IDX 2
#define mmHUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB 0x0737
#define mmHUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB_BASE_IDX 2
#define mmHUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB 0x0738
#define mmHUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB_BASE_IDX 2
#define mmHUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB 0x0739
#define mmHUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB_BASE_IDX 2
#define mmHUBPREQ2_DCN_VM_CONTEXT0_STATUS 0x073a
#define mmHUBPREQ2_DCN_VM_CONTEXT0_STATUS_BASE_IDX 2
#define mmHUBPREQ2_DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB 0x073b
#define mmHUBPREQ2_DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB_BASE_IDX 2
#define mmHUBPREQ2_DCN_VM_CONTEXT0_CNTL 0x073c
#define mmHUBPREQ2_DCN_VM_CONTEXT0_CNTL_BASE_IDX 2
#define mmHUBPREQ2_DCN_VM_MX_L1_TLB_CNTL 0x073d
#define mmHUBPREQ2_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX 2
#define mmHUBPREQ2_BLANK_OFFSET_0 0x073e
#define mmHUBPREQ2_BLANK_OFFSET_0_BASE_IDX 2
#define mmHUBPREQ2_BLANK_OFFSET_1 0x073f
#define mmHUBPREQ2_BLANK_OFFSET_1_BASE_IDX 2
#define mmHUBPREQ2_DST_DIMENSIONS 0x0740
#define mmHUBPREQ2_DST_DIMENSIONS_BASE_IDX 2
#define mmHUBPREQ2_DST_AFTER_SCALER 0x0741
#define mmHUBPREQ2_DST_AFTER_SCALER_BASE_IDX 2
#define mmHUBPREQ2_PREFETCH_SETTINS 0x0742
#define mmHUBPREQ2_PREFETCH_SETTINS_BASE_IDX 2
#define mmHUBPREQ2_PREFETCH_SETTINS_C 0x0743
#define mmHUBPREQ2_PREFETCH_SETTINS_C_BASE_IDX 2
#define mmHUBPREQ2_VBLANK_PARAMETERS_0 0x0744
#define mmHUBPREQ2_VBLANK_PARAMETERS_0_BASE_IDX 2
#define mmHUBPREQ2_VBLANK_PARAMETERS_1 0x0745
#define mmHUBPREQ2_VBLANK_PARAMETERS_1_BASE_IDX 2
#define mmHUBPREQ2_VBLANK_PARAMETERS_2 0x0746
#define mmHUBPREQ2_VBLANK_PARAMETERS_2_BASE_IDX 2
#define mmHUBPREQ2_VBLANK_PARAMETERS_3 0x0747
#define mmHUBPREQ2_VBLANK_PARAMETERS_3_BASE_IDX 2
#define mmHUBPREQ2_VBLANK_PARAMETERS_4 0x0748
#define mmHUBPREQ2_VBLANK_PARAMETERS_4_BASE_IDX 2
#define mmHUBPREQ2_NOM_PARAMETERS_0 0x0749
#define mmHUBPREQ2_NOM_PARAMETERS_0_BASE_IDX 2
#define mmHUBPREQ2_NOM_PARAMETERS_1 0x074a
#define mmHUBPREQ2_NOM_PARAMETERS_1_BASE_IDX 2
#define mmHUBPREQ2_NOM_PARAMETERS_2 0x074b
#define mmHUBPREQ2_NOM_PARAMETERS_2_BASE_IDX 2
#define mmHUBPREQ2_NOM_PARAMETERS_3 0x074c
#define mmHUBPREQ2_NOM_PARAMETERS_3_BASE_IDX 2
#define mmHUBPREQ2_NOM_PARAMETERS_4 0x074d
#define mmHUBPREQ2_NOM_PARAMETERS_4_BASE_IDX 2
#define mmHUBPREQ2_NOM_PARAMETERS_5 0x074e
#define mmHUBPREQ2_NOM_PARAMETERS_5_BASE_IDX 2
#define mmHUBPREQ2_NOM_PARAMETERS_6 0x074f
#define mmHUBPREQ2_NOM_PARAMETERS_6_BASE_IDX 2
#define mmHUBPREQ2_NOM_PARAMETERS_7 0x0750
#define mmHUBPREQ2_NOM_PARAMETERS_7_BASE_IDX 2
#define mmHUBPREQ2_PER_LINE_DELIVERY_PRE 0x0751
#define mmHUBPREQ2_PER_LINE_DELIVERY_PRE_BASE_IDX 2
#define mmHUBPREQ2_PER_LINE_DELIVERY 0x0752
#define mmHUBPREQ2_PER_LINE_DELIVERY_BASE_IDX 2
#define mmHUBPREQ2_CURSOR_SETTINS 0x0753
#define mmHUBPREQ2_CURSOR_SETTINS_BASE_IDX 2
#define mmHUBPREQ2_REF_FREQ_TO_PIX_FREQ 0x0754
#define mmHUBPREQ2_REF_FREQ_TO_PIX_FREQ_BASE_IDX 2
#define mmHUBPREQ2_HUBPREQ_MEM_PWR_CTRL 0x0755
#define mmHUBPREQ2_HUBPREQ_MEM_PWR_CTRL_BASE_IDX 2
#define mmHUBPREQ2_HUBPREQ_MEM_PWR_STATUS 0x0756
#define mmHUBPREQ2_HUBPREQ_MEM_PWR_STATUS_BASE_IDX 2
// addressBlock: dce_dc_dcbubp2_dispdec_hubpret_dispdec
// base address: 0x620
#define mmHUBPRET2_HUBPRET_CONTROL 0x0768
#define mmHUBPRET2_HUBPRET_CONTROL_BASE_IDX 2
#define mmHUBPRET2_HUBPRET_MEM_PWR_CTRL 0x0769
#define mmHUBPRET2_HUBPRET_MEM_PWR_CTRL_BASE_IDX 2
#define mmHUBPRET2_HUBPRET_MEM_PWR_STATUS 0x076a
#define mmHUBPRET2_HUBPRET_MEM_PWR_STATUS_BASE_IDX 2
#define mmHUBPRET2_HUBPRET_READ_LINE_CTRL0 0x076b
#define mmHUBPRET2_HUBPRET_READ_LINE_CTRL0_BASE_IDX 2
#define mmHUBPRET2_HUBPRET_READ_LINE_CTRL1 0x076c
#define mmHUBPRET2_HUBPRET_READ_LINE_CTRL1_BASE_IDX 2
#define mmHUBPRET2_HUBPRET_READ_LINE0 0x076d
#define mmHUBPRET2_HUBPRET_READ_LINE0_BASE_IDX 2
#define mmHUBPRET2_HUBPRET_READ_LINE1 0x076e
#define mmHUBPRET2_HUBPRET_READ_LINE1_BASE_IDX 2
#define mmHUBPRET2_HUBPRET_INTERRUPT 0x076f
#define mmHUBPRET2_HUBPRET_INTERRUPT_BASE_IDX 2
#define mmHUBPRET2_HUBPRET_READ_LINE_VALUE 0x0770
#define mmHUBPRET2_HUBPRET_READ_LINE_VALUE_BASE_IDX 2
#define mmHUBPRET2_HUBPRET_READ_LINE_STATUS 0x0771
#define mmHUBPRET2_HUBPRET_READ_LINE_STATUS_BASE_IDX 2
// addressBlock: dce_dc_dcbubp2_dispdec_cursor_dispdec
// base address: 0x620
#define mmCURSOR2_CURSOR_CONTROL 0x0774
#define mmCURSOR2_CURSOR_CONTROL_BASE_IDX 2
#define mmCURSOR2_CURSOR_SURFACE_ADDRESS 0x0775
#define mmCURSOR2_CURSOR_SURFACE_ADDRESS_BASE_IDX 2
#define mmCURSOR2_CURSOR_SURFACE_ADDRESS_HIGH 0x0776
#define mmCURSOR2_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX 2
#define mmCURSOR2_CURSOR_SIZE 0x0777
#define mmCURSOR2_CURSOR_SIZE_BASE_IDX 2
#define mmCURSOR2_CURSOR_POSITION 0x0778
#define mmCURSOR2_CURSOR_POSITION_BASE_IDX 2
#define mmCURSOR2_CURSOR_HOT_SPOT 0x0779
#define mmCURSOR2_CURSOR_HOT_SPOT_BASE_IDX 2
#define mmCURSOR2_CURSOR_STEREO_CONTROL 0x077a
#define mmCURSOR2_CURSOR_STEREO_CONTROL_BASE_IDX 2
#define mmCURSOR2_CURSOR_DST_OFFSET 0x077b
#define mmCURSOR2_CURSOR_DST_OFFSET_BASE_IDX 2
#define mmCURSOR2_CURSOR_MEM_PWR_CTRL 0x077c
#define mmCURSOR2_CURSOR_MEM_PWR_CTRL_BASE_IDX 2
#define mmCURSOR2_CURSOR_MEM_PWR_STATUS 0x077d
#define mmCURSOR2_CURSOR_MEM_PWR_STATUS_BASE_IDX 2
// addressBlock: dce_dc_dcbubp2_dispdec_hubp_dcperfmon_dc_perfmon_dispdec
// base address: 0x1e64
#define mmDC_PERFMON10_PERFCOUNTER_CNTL 0x0799
#define mmDC_PERFMON10_PERFCOUNTER_CNTL_BASE_IDX 2
#define mmDC_PERFMON10_PERFCOUNTER_CNTL2 0x079a
#define mmDC_PERFMON10_PERFCOUNTER_CNTL2_BASE_IDX 2
#define mmDC_PERFMON10_PERFCOUNTER_STATE 0x079b
#define mmDC_PERFMON10_PERFCOUNTER_STATE_BASE_IDX 2
#define mmDC_PERFMON10_PERFMON_CNTL 0x079c
#define mmDC_PERFMON10_PERFMON_CNTL_BASE_IDX 2
#define mmDC_PERFMON10_PERFMON_CNTL2 0x079d
#define mmDC_PERFMON10_PERFMON_CNTL2_BASE_IDX 2
#define mmDC_PERFMON10_PERFMON_CVALUE_INT_MISC 0x079e
#define mmDC_PERFMON10_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
#define mmDC_PERFMON10_PERFMON_CVALUE_LOW 0x079f
#define mmDC_PERFMON10_PERFMON_CVALUE_LOW_BASE_IDX 2
#define mmDC_PERFMON10_PERFMON_HI 0x07a0
#define mmDC_PERFMON10_PERFMON_HI_BASE_IDX 2
#define mmDC_PERFMON10_PERFMON_LOW 0x07a1
#define mmDC_PERFMON10_PERFMON_LOW_BASE_IDX 2
// addressBlock: dce_dc_dcbubp3_dispdec_hubp_dispdec
// base address: 0x930
#define mmHUBP3_DCSURF_SURFACE_CONFIG 0x07a5
#define mmHUBP3_DCSURF_SURFACE_CONFIG_BASE_IDX 2
#define mmHUBP3_DCSURF_ADDR_CONFIG 0x07a6
#define mmHUBP3_DCSURF_ADDR_CONFIG_BASE_IDX 2
#define mmHUBP3_DCSURF_TILING_CONFIG 0x07a7
#define mmHUBP3_DCSURF_TILING_CONFIG_BASE_IDX 2
#define mmHUBP3_DCSURF_PRI_VIEWPORT_START 0x07a8
#define mmHUBP3_DCSURF_PRI_VIEWPORT_START_BASE_IDX 2
#define mmHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION 0x07a9
#define mmHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2
#define mmHUBP3_DCSURF_PRI_VIEWPORT_START_C 0x07aa
#define mmHUBP3_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX 2
#define mmHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C 0x07ab
#define mmHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX 2
#define mmHUBP3_DCSURF_SEC_VIEWPORT_START 0x07ac
#define mmHUBP3_DCSURF_SEC_VIEWPORT_START_BASE_IDX 2
#define mmHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION 0x07ad
#define mmHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX 2
#define mmHUBP3_DCSURF_SEC_VIEWPORT_START_C 0x07ae
#define mmHUBP3_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX 2
#define mmHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C 0x07af
#define mmHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX 2
#define mmHUBP3_DCHUBP_REQ_SIZE_CONFIG 0x07b0
#define mmHUBP3_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX 2
#define mmHUBP3_DCHUBP_REQ_SIZE_CONFIG_C 0x07b1
#define mmHUBP3_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX 2
#define mmHUBP3_DCHUBP_CNTL 0x07b2
#define mmHUBP3_DCHUBP_CNTL_BASE_IDX 2
#define mmHUBP3_HUBP_CLK_CNTL 0x07b3
#define mmHUBP3_HUBP_CLK_CNTL_BASE_IDX 2
#define mmHUBP3_DCHUBP_VMPG_CONFIG 0x07b4
#define mmHUBP3_DCHUBP_VMPG_CONFIG_BASE_IDX 2
#define mmHUBP3_HUBPREQ_DEBUG_DB 0x07b5
#define mmHUBP3_HUBPREQ_DEBUG_DB_BASE_IDX 2
#define mmHUBP3_HUBPREQ_DEBUG 0x07b6
#define mmHUBP3_HUBPREQ_DEBUG_BASE_IDX 2
#define mmHUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK 0x07ba
#define mmHUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX 2
#define mmHUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK 0x07bb
#define mmHUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX 2
// addressBlock: dce_dc_dcbubp3_dispdec_hubpreq_dispdec
// base address: 0x930
#define mmHUBPREQ3_DCSURF_SURFACE_PITCH 0x07c7
#define mmHUBPREQ3_DCSURF_SURFACE_PITCH_BASE_IDX 2
#define mmHUBPREQ3_DCSURF_SURFACE_PITCH_C 0x07c8
#define mmHUBPREQ3_DCSURF_SURFACE_PITCH_C_BASE_IDX 2
#define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS 0x07c9
#define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2
#define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0x07ca
#define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
#define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0x07cb
#define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2
#define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x07cc
#define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
#define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS 0x07cd
#define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2
#define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0x07ce
#define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
#define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0x07cf
#define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2
#define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x07d0
#define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
#define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS 0x07d1
#define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX 2
#define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH 0x07d2
#define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2
#define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C 0x07d3
#define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX 2
#define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0x07d4
#define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
#define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS 0x07d5
#define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX 2
#define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH 0x07d6
#define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2
#define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C 0x07d7
#define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX 2
#define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0x07d8
#define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
#define mmHUBPREQ3_DCSURF_SURFACE_CONTROL 0x07d9
#define mmHUBPREQ3_DCSURF_SURFACE_CONTROL_BASE_IDX 2
#define mmHUBPREQ3_DCSURF_FLIP_CONTROL 0x07da
#define mmHUBPREQ3_DCSURF_FLIP_CONTROL_BASE_IDX 2
#define mmHUBPREQ3_DCSURF_FLIP_CONTROL2 0x07db
#define mmHUBPREQ3_DCSURF_FLIP_CONTROL2_BASE_IDX 2
#define mmHUBPREQ3_DCSURF_FRAME_PACING_CONTROL 0x07dc
#define mmHUBPREQ3_DCSURF_FRAME_PACING_CONTROL_BASE_IDX 2
#define mmHUBPREQ3_DCSURF_FRAME_PACING_TIME 0x07dd
#define mmHUBPREQ3_DCSURF_FRAME_PACING_TIME_BASE_IDX 2
#define mmHUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT 0x07de
#define mmHUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX 2
#define mmHUBPREQ3_DCSURF_SURFACE_INUSE 0x07df
#define mmHUBPREQ3_DCSURF_SURFACE_INUSE_BASE_IDX 2
#define mmHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH 0x07e0
#define mmHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX 2
#define mmHUBPREQ3_DCSURF_SURFACE_INUSE_C 0x07e1
#define mmHUBPREQ3_DCSURF_SURFACE_INUSE_C_BASE_IDX 2
#define mmHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C 0x07e2
#define mmHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX 2
#define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE 0x07e3
#define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX 2
#define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0x07e4
#define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX 2
#define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C 0x07e5
#define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX 2
#define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0x07e6
#define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX 2
#define mmHUBPREQ3_DCN_EXPANSION_MODE 0x07e7
#define mmHUBPREQ3_DCN_EXPANSION_MODE_BASE_IDX 2
#define mmHUBPREQ3_DCN_TTU_QOS_WM 0x07e8
#define mmHUBPREQ3_DCN_TTU_QOS_WM_BASE_IDX 2
#define mmHUBPREQ3_DCN_GLOBAL_TTU_CNTL 0x07e9
#define mmHUBPREQ3_DCN_GLOBAL_TTU_CNTL_BASE_IDX 2
#define mmHUBPREQ3_DCN_SURF0_TTU_CNTL0 0x07ea
#define mmHUBPREQ3_DCN_SURF0_TTU_CNTL0_BASE_IDX 2
#define mmHUBPREQ3_DCN_SURF0_TTU_CNTL1 0x07eb
#define mmHUBPREQ3_DCN_SURF0_TTU_CNTL1_BASE_IDX 2
#define mmHUBPREQ3_DCN_SURF1_TTU_CNTL0 0x07ec
#define mmHUBPREQ3_DCN_SURF1_TTU_CNTL0_BASE_IDX 2
#define mmHUBPREQ3_DCN_SURF1_TTU_CNTL1 0x07ed
#define mmHUBPREQ3_DCN_SURF1_TTU_CNTL1_BASE_IDX 2
#define mmHUBPREQ3_DCN_CUR0_TTU_CNTL0 0x07ee
#define mmHUBPREQ3_DCN_CUR0_TTU_CNTL0_BASE_IDX 2
#define mmHUBPREQ3_DCN_CUR0_TTU_CNTL1 0x07ef
#define mmHUBPREQ3_DCN_CUR0_TTU_CNTL1_BASE_IDX 2
#define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB 0x07f0
#define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB_BASE_IDX 2
#define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB 0x07f1
#define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB_BASE_IDX 2
#define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB 0x07f2
#define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB_BASE_IDX 2
#define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB 0x07f3
#define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB_BASE_IDX 2
#define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB 0x07f4
#define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_BASE_IDX 2
#define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB 0x07f5
#define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_BASE_IDX 2
#define mmHUBPREQ3_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB 0x07f6
#define mmHUBPREQ3_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB_BASE_IDX 2
#define mmHUBPREQ3_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB 0x07f7
#define mmHUBPREQ3_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB_BASE_IDX 2
#define mmHUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB 0x07f8
#define mmHUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB_BASE_IDX 2
#define mmHUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB 0x07f9
#define mmHUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB_BASE_IDX 2
#define mmHUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB 0x07fa
#define mmHUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB_BASE_IDX 2
#define mmHUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB 0x07fb
#define mmHUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB_BASE_IDX 2
#define mmHUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB 0x07fc
#define mmHUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB_BASE_IDX 2
#define mmHUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB 0x07fd
#define mmHUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB_BASE_IDX 2
#define mmHUBPREQ3_DCN_VM_CONTEXT0_STATUS 0x07fe
#define mmHUBPREQ3_DCN_VM_CONTEXT0_STATUS_BASE_IDX 2
#define mmHUBPREQ3_DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB 0x07ff
#define mmHUBPREQ3_DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB_BASE_IDX 2
#define mmHUBPREQ3_DCN_VM_CONTEXT0_CNTL 0x0800
#define mmHUBPREQ3_DCN_VM_CONTEXT0_CNTL_BASE_IDX 2
#define mmHUBPREQ3_DCN_VM_MX_L1_TLB_CNTL 0x0801
#define mmHUBPREQ3_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX 2
#define mmHUBPREQ3_BLANK_OFFSET_0 0x0802
#define mmHUBPREQ3_BLANK_OFFSET_0_BASE_IDX 2
#define mmHUBPREQ3_BLANK_OFFSET_1 0x0803
#define mmHUBPREQ3_BLANK_OFFSET_1_BASE_IDX 2
#define mmHUBPREQ3_DST_DIMENSIONS 0x0804
#define mmHUBPREQ3_DST_DIMENSIONS_BASE_IDX 2
#define mmHUBPREQ3_DST_AFTER_SCALER 0x0805
#define mmHUBPREQ3_DST_AFTER_SCALER_BASE_IDX 2
#define mmHUBPREQ3_PREFETCH_SETTINS 0x0806
#define mmHUBPREQ3_PREFETCH_SETTINS_BASE_IDX 2
#define mmHUBPREQ3_PREFETCH_SETTINS_C 0x0807
#define mmHUBPREQ3_PREFETCH_SETTINS_C_BASE_IDX 2
#define mmHUBPREQ3_VBLANK_PARAMETERS_0 0x0808
#define mmHUBPREQ3_VBLANK_PARAMETERS_0_BASE_IDX 2
#define mmHUBPREQ3_VBLANK_PARAMETERS_1 0x0809
#define mmHUBPREQ3_VBLANK_PARAMETERS_1_BASE_IDX 2
#define mmHUBPREQ3_VBLANK_PARAMETERS_2 0x080a
#define mmHUBPREQ3_VBLANK_PARAMETERS_2_BASE_IDX 2
#define mmHUBPREQ3_VBLANK_PARAMETERS_3 0x080b
#define mmHUBPREQ3_VBLANK_PARAMETERS_3_BASE_IDX 2
#define mmHUBPREQ3_VBLANK_PARAMETERS_4 0x080c
#define mmHUBPREQ3_VBLANK_PARAMETERS_4_BASE_IDX 2
#define mmHUBPREQ3_NOM_PARAMETERS_0 0x080d
#define mmHUBPREQ3_NOM_PARAMETERS_0_BASE_IDX 2
#define mmHUBPREQ3_NOM_PARAMETERS_1 0x080e
#define mmHUBPREQ3_NOM_PARAMETERS_1_BASE_IDX 2
#define mmHUBPREQ3_NOM_PARAMETERS_2 0x080f
#define mmHUBPREQ3_NOM_PARAMETERS_2_BASE_IDX 2
#define mmHUBPREQ3_NOM_PARAMETERS_3 0x0810
#define mmHUBPREQ3_NOM_PARAMETERS_3_BASE_IDX 2
#define mmHUBPREQ3_NOM_PARAMETERS_4 0x0811
#define mmHUBPREQ3_NOM_PARAMETERS_4_BASE_IDX 2
#define mmHUBPREQ3_NOM_PARAMETERS_5 0x0812
#define mmHUBPREQ3_NOM_PARAMETERS_5_BASE_IDX 2
#define mmHUBPREQ3_NOM_PARAMETERS_6 0x0813
#define mmHUBPREQ3_NOM_PARAMETERS_6_BASE_IDX 2
#define mmHUBPREQ3_NOM_PARAMETERS_7 0x0814
#define mmHUBPREQ3_NOM_PARAMETERS_7_BASE_IDX 2
#define mmHUBPREQ3_PER_LINE_DELIVERY_PRE 0x0815
#define mmHUBPREQ3_PER_LINE_DELIVERY_PRE_BASE_IDX 2
#define mmHUBPREQ3_PER_LINE_DELIVERY 0x0816
#define mmHUBPREQ3_PER_LINE_DELIVERY_BASE_IDX 2
#define mmHUBPREQ3_CURSOR_SETTINS 0x0817
#define mmHUBPREQ3_CURSOR_SETTINS_BASE_IDX 2
#define mmHUBPREQ3_REF_FREQ_TO_PIX_FREQ 0x0818
#define mmHUBPREQ3_REF_FREQ_TO_PIX_FREQ_BASE_IDX 2
#define mmHUBPREQ3_HUBPREQ_MEM_PWR_CTRL 0x0819
#define mmHUBPREQ3_HUBPREQ_MEM_PWR_CTRL_BASE_IDX 2
#define mmHUBPREQ3_HUBPREQ_MEM_PWR_STATUS 0x081a
#define mmHUBPREQ3_HUBPREQ_MEM_PWR_STATUS_BASE_IDX 2
// addressBlock: dce_dc_dcbubp3_dispdec_hubpret_dispdec
// base address: 0x930
#define mmHUBPRET3_HUBPRET_CONTROL 0x082c
#define mmHUBPRET3_HUBPRET_CONTROL_BASE_IDX 2
#define mmHUBPRET3_HUBPRET_MEM_PWR_CTRL 0x082d
#define mmHUBPRET3_HUBPRET_MEM_PWR_CTRL_BASE_IDX 2
#define mmHUBPRET3_HUBPRET_MEM_PWR_STATUS 0x082e
#define mmHUBPRET3_HUBPRET_MEM_PWR_STATUS_BASE_IDX 2
#define mmHUBPRET3_HUBPRET_READ_LINE_CTRL0 0x082f
#define mmHUBPRET3_HUBPRET_READ_LINE_CTRL0_BASE_IDX 2
#define mmHUBPRET3_HUBPRET_READ_LINE_CTRL1 0x0830
#define mmHUBPRET3_HUBPRET_READ_LINE_CTRL1_BASE_IDX 2
#define mmHUBPRET3_HUBPRET_READ_LINE0 0x0831
#define mmHUBPRET3_HUBPRET_READ_LINE0_BASE_IDX 2
#define mmHUBPRET3_HUBPRET_READ_LINE1 0x0832
#define mmHUBPRET3_HUBPRET_READ_LINE1_BASE_IDX 2
#define mmHUBPRET3_HUBPRET_INTERRUPT 0x0833
#define mmHUBPRET3_HUBPRET_INTERRUPT_BASE_IDX 2
#define mmHUBPRET3_HUBPRET_READ_LINE_VALUE 0x0834
#define mmHUBPRET3_HUBPRET_READ_LINE_VALUE_BASE_IDX 2
#define mmHUBPRET3_HUBPRET_READ_LINE_STATUS 0x0835
#define mmHUBPRET3_HUBPRET_READ_LINE_STATUS_BASE_IDX 2
// addressBlock: dce_dc_dcbubp3_dispdec_cursor_dispdec
// base address: 0x930
#define mmCURSOR3_CURSOR_CONTROL 0x0838
#define mmCURSOR3_CURSOR_CONTROL_BASE_IDX 2
#define mmCURSOR3_CURSOR_SURFACE_ADDRESS 0x0839
#define mmCURSOR3_CURSOR_SURFACE_ADDRESS_BASE_IDX 2
#define mmCURSOR3_CURSOR_SURFACE_ADDRESS_HIGH 0x083a
#define mmCURSOR3_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX 2
#define mmCURSOR3_CURSOR_SIZE 0x083b
#define mmCURSOR3_CURSOR_SIZE_BASE_IDX 2
#define mmCURSOR3_CURSOR_POSITION 0x083c
#define mmCURSOR3_CURSOR_POSITION_BASE_IDX 2
#define mmCURSOR3_CURSOR_HOT_SPOT 0x083d
#define mmCURSOR3_CURSOR_HOT_SPOT_BASE_IDX 2
#define mmCURSOR3_CURSOR_STEREO_CONTROL 0x083e
#define mmCURSOR3_CURSOR_STEREO_CONTROL_BASE_IDX 2
#define mmCURSOR3_CURSOR_DST_OFFSET 0x083f
#define mmCURSOR3_CURSOR_DST_OFFSET_BASE_IDX 2
#define mmCURSOR3_CURSOR_MEM_PWR_CTRL 0x0840
#define mmCURSOR3_CURSOR_MEM_PWR_CTRL_BASE_IDX 2
#define mmCURSOR3_CURSOR_MEM_PWR_STATUS 0x0841
#define mmCURSOR3_CURSOR_MEM_PWR_STATUS_BASE_IDX 2
// addressBlock: dce_dc_dcbubp3_dispdec_hubp_dcperfmon_dc_perfmon_dispdec
// base address: 0x2174
#define mmDC_PERFMON11_PERFCOUNTER_CNTL 0x085d
#define mmDC_PERFMON11_PERFCOUNTER_CNTL_BASE_IDX 2
#define mmDC_PERFMON11_PERFCOUNTER_CNTL2 0x085e
#define mmDC_PERFMON11_PERFCOUNTER_CNTL2_BASE_IDX 2
#define mmDC_PERFMON11_PERFCOUNTER_STATE 0x085f
#define mmDC_PERFMON11_PERFCOUNTER_STATE_BASE_IDX 2
#define mmDC_PERFMON11_PERFMON_CNTL 0x0860
#define mmDC_PERFMON11_PERFMON_CNTL_BASE_IDX 2
#define mmDC_PERFMON11_PERFMON_CNTL2 0x0861
#define mmDC_PERFMON11_PERFMON_CNTL2_BASE_IDX 2
#define mmDC_PERFMON11_PERFMON_CVALUE_INT_MISC 0x0862
#define mmDC_PERFMON11_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
#define mmDC_PERFMON11_PERFMON_CVALUE_LOW 0x0863
#define mmDC_PERFMON11_PERFMON_CVALUE_LOW_BASE_IDX 2
#define mmDC_PERFMON11_PERFMON_HI 0x0864
#define mmDC_PERFMON11_PERFMON_HI_BASE_IDX 2
#define mmDC_PERFMON11_PERFMON_LOW 0x0865
#define mmDC_PERFMON11_PERFMON_LOW_BASE_IDX 2
// addressBlock: dce_dc_dpp0_dispdec_dpp_top_dispdec
// base address: 0x0
#define mmDPP_TOP0_DPP_CONTROL 0x0c3d
#define mmDPP_TOP0_DPP_CONTROL_BASE_IDX 2
#define mmDPP_TOP0_DPP_SOFT_RESET 0x0c3e
#define mmDPP_TOP0_DPP_SOFT_RESET_BASE_IDX 2
#define mmDPP_TOP0_DPP_CRC_VAL_R_G 0x0c3f
#define mmDPP_TOP0_DPP_CRC_VAL_R_G_BASE_IDX 2
#define mmDPP_TOP0_DPP_CRC_VAL_B_A 0x0c40
#define mmDPP_TOP0_DPP_CRC_VAL_B_A_BASE_IDX 2
#define mmDPP_TOP0_DPP_CRC_CTRL 0x0c41
#define mmDPP_TOP0_DPP_CRC_CTRL_BASE_IDX 2
#define mmDPP_TOP0_HOST_READ_CONTROL 0x0c42
#define mmDPP_TOP0_HOST_READ_CONTROL_BASE_IDX 2
// addressBlock: dce_dc_dpp0_dispdec_cnvc_cfg_dispdec
// base address: 0x0
#define mmCNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT 0x0c47
#define mmCNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX 2
#define mmCNVC_CFG0_FORMAT_CONTROL 0x0c48
#define mmCNVC_CFG0_FORMAT_CONTROL_BASE_IDX 2
#define mmCNVC_CFG0_FCNV_FP_SCALE_BIAS 0x0c49
#define mmCNVC_CFG0_FCNV_FP_SCALE_BIAS_BASE_IDX 2
#define mmCNVC_CFG0_DENORM_CONTROL 0x0c4a
#define mmCNVC_CFG0_DENORM_CONTROL_BASE_IDX 2
#define mmCNVC_CFG0_COLOR_KEYER_CONTROL 0x0c4c
#define mmCNVC_CFG0_COLOR_KEYER_CONTROL_BASE_IDX 2
#define mmCNVC_CFG0_COLOR_KEYER_ALPHA 0x0c4d
#define mmCNVC_CFG0_COLOR_KEYER_ALPHA_BASE_IDX 2
#define mmCNVC_CFG0_COLOR_KEYER_RED 0x0c4e
#define mmCNVC_CFG0_COLOR_KEYER_RED_BASE_IDX 2
#define mmCNVC_CFG0_COLOR_KEYER_GREEN 0x0c4f
#define mmCNVC_CFG0_COLOR_KEYER_GREEN_BASE_IDX 2
#define mmCNVC_CFG0_COLOR_KEYER_BLUE 0x0c50
#define mmCNVC_CFG0_COLOR_KEYER_BLUE_BASE_IDX 2
// addressBlock: dce_dc_dpp0_dispdec_cnvc_cur_dispdec
// base address: 0x0
#define mmCNVC_CUR0_CURSOR0_CONTROL 0x0c58
#define mmCNVC_CUR0_CURSOR0_CONTROL_BASE_IDX 2
#define mmCNVC_CUR0_CURSOR0_COLOR0 0x0c59
#define mmCNVC_CUR0_CURSOR0_COLOR0_BASE_IDX 2
#define mmCNVC_CUR0_CURSOR0_COLOR1 0x0c5a
#define mmCNVC_CUR0_CURSOR0_COLOR1_BASE_IDX 2
#define mmCNVC_CUR0_CURSOR0_FP_SCALE_BIAS 0x0c5b
#define mmCNVC_CUR0_CURSOR0_FP_SCALE_BIAS_BASE_IDX 2
// addressBlock: dce_dc_dpp0_dispdec_dscl_dispdec
// base address: 0x0
#define mmDSCL0_SCL_COEF_RAM_TAP_SELECT 0x0c62
#define mmDSCL0_SCL_COEF_RAM_TAP_SELECT_BASE_IDX 2
#define mmDSCL0_SCL_COEF_RAM_TAP_DATA 0x0c63
#define mmDSCL0_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2
#define mmDSCL0_SCL_MODE 0x0c64
#define mmDSCL0_SCL_MODE_BASE_IDX 2
#define mmDSCL0_SCL_TAP_CONTROL 0x0c65
#define mmDSCL0_SCL_TAP_CONTROL_BASE_IDX 2
#define mmDSCL0_DSCL_CONTROL 0x0c66
#define mmDSCL0_DSCL_CONTROL_BASE_IDX 2
#define mmDSCL0_DSCL_2TAP_CONTROL 0x0c67
#define mmDSCL0_DSCL_2TAP_CONTROL_BASE_IDX 2
#define mmDSCL0_SCL_MANUAL_REPLICATE_CONTROL 0x0c68
#define mmDSCL0_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2
#define mmDSCL0_SCL_HORZ_FILTER_SCALE_RATIO 0x0c69
#define mmDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2
#define mmDSCL0_SCL_HORZ_FILTER_INIT 0x0c6a
#define mmDSCL0_SCL_HORZ_FILTER_INIT_BASE_IDX 2
#define mmDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C 0x0c6b
#define mmDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2
#define mmDSCL0_SCL_HORZ_FILTER_INIT_C 0x0c6c
#define mmDSCL0_SCL_HORZ_FILTER_INIT_C_BASE_IDX 2
#define mmDSCL0_SCL_VERT_FILTER_SCALE_RATIO 0x0c6d
#define mmDSCL0_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2
#define mmDSCL0_SCL_VERT_FILTER_INIT 0x0c6e
#define mmDSCL0_SCL_VERT_FILTER_INIT_BASE_IDX 2
#define mmDSCL0_SCL_VERT_FILTER_INIT_BOT 0x0c6f
#define mmDSCL0_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2
#define mmDSCL0_SCL_VERT_FILTER_SCALE_RATIO_C 0x0c70
#define mmDSCL0_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2
#define mmDSCL0_SCL_VERT_FILTER_INIT_C 0x0c71
#define mmDSCL0_SCL_VERT_FILTER_INIT_C_BASE_IDX 2
#define mmDSCL0_SCL_VERT_FILTER_INIT_BOT_C 0x0c72
#define mmDSCL0_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX 2
#define mmDSCL0_SCL_BLACK_OFFSET 0x0c73
#define mmDSCL0_SCL_BLACK_OFFSET_BASE_IDX 2
#define mmDSCL0_DSCL_UPDATE 0x0c74
#define mmDSCL0_DSCL_UPDATE_BASE_IDX 2
#define mmDSCL0_DSCL_AUTOCAL 0x0c75
#define mmDSCL0_DSCL_AUTOCAL_BASE_IDX 2
#define mmDSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT 0x0c76
#define mmDSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2
#define mmDSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM 0x0c77
#define mmDSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2
#define mmDSCL0_OTG_H_BLANK 0x0c78
#define mmDSCL0_OTG_H_BLANK_BASE_IDX 2
#define mmDSCL0_OTG_V_BLANK 0x0c79
#define mmDSCL0_OTG_V_BLANK_BASE_IDX 2
#define mmDSCL0_RECOUT_START 0x0c7a
#define mmDSCL0_RECOUT_START_BASE_IDX 2
#define mmDSCL0_RECOUT_SIZE 0x0c7b
#define mmDSCL0_RECOUT_SIZE_BASE_IDX 2
#define mmDSCL0_MPC_SIZE 0x0c7c
#define mmDSCL0_MPC_SIZE_BASE_IDX 2
#define mmDSCL0_LB_DATA_FORMAT 0x0c7d
#define mmDSCL0_LB_DATA_FORMAT_BASE_IDX 2
#define mmDSCL0_LB_MEMORY_CTRL 0x0c7e
#define mmDSCL0_LB_MEMORY_CTRL_BASE_IDX 2
#define mmDSCL0_LB_V_COUNTER 0x0c7f
#define mmDSCL0_LB_V_COUNTER_BASE_IDX 2
#define mmDSCL0_DSCL_MEM_PWR_CTRL 0x0c80
#define mmDSCL0_DSCL_MEM_PWR_CTRL_BASE_IDX 2
#define mmDSCL0_DSCL_MEM_PWR_STATUS 0x0c81
#define mmDSCL0_DSCL_MEM_PWR_STATUS_BASE_IDX 2
#define mmDSCL0_OBUF_CONTROL 0x0c82
#define mmDSCL0_OBUF_CONTROL_BASE_IDX 2
#define mmDSCL0_OBUF_MEM_PWR_CTRL 0x0c83
#define mmDSCL0_OBUF_MEM_PWR_CTRL_BASE_IDX 2
// addressBlock: dce_dc_dpp0_dispdec_cm_dispdec
// base address: 0x0
#define mmCM0_CM_CONTROL 0x0c92
#define mmCM0_CM_CONTROL_BASE_IDX 2
#define mmCM0_CM_COMA_C11_C12 0x0c93
#define mmCM0_CM_COMA_C11_C12_BASE_IDX 2
#define mmCM0_CM_COMA_C13_C14 0x0c94
#define mmCM0_CM_COMA_C13_C14_BASE_IDX 2
#define mmCM0_CM_COMA_C21_C22 0x0c95
#define mmCM0_CM_COMA_C21_C22_BASE_IDX 2
#define mmCM0_CM_COMA_C23_C24 0x0c96
#define mmCM0_CM_COMA_C23_C24_BASE_IDX 2
#define mmCM0_CM_COMA_C31_C32 0x0c97
#define mmCM0_CM_COMA_C31_C32_BASE_IDX 2
#define mmCM0_CM_COMA_C33_C34 0x0c98
#define mmCM0_CM_COMA_C33_C34_BASE_IDX 2
#define mmCM0_CM_COMB_C11_C12 0x0c99
#define mmCM0_CM_COMB_C11_C12_BASE_IDX 2
#define mmCM0_CM_COMB_C13_C14 0x0c9a
#define mmCM0_CM_COMB_C13_C14_BASE_IDX 2
#define mmCM0_CM_COMB_C21_C22 0x0c9b
#define mmCM0_CM_COMB_C21_C22_BASE_IDX 2
#define mmCM0_CM_COMB_C23_C24 0x0c9c
#define mmCM0_CM_COMB_C23_C24_BASE_IDX 2
#define mmCM0_CM_COMB_C31_C32 0x0c9d
#define mmCM0_CM_COMB_C31_C32_BASE_IDX 2
#define mmCM0_CM_COMB_C33_C34 0x0c9e
#define mmCM0_CM_COMB_C33_C34_BASE_IDX 2
#define mmCM0_CM_IGAM_CONTROL 0x0c9f
#define mmCM0_CM_IGAM_CONTROL_BASE_IDX 2
#define mmCM0_CM_IGAM_LUT_RW_CONTROL 0x0ca0
#define mmCM0_CM_IGAM_LUT_RW_CONTROL_BASE_IDX 2
#define mmCM0_CM_IGAM_LUT_RW_INDEX 0x0ca1
#define mmCM0_CM_IGAM_LUT_RW_INDEX_BASE_IDX 2
#define mmCM0_CM_IGAM_LUT_SEQ_COLOR 0x0ca2
#define mmCM0_CM_IGAM_LUT_SEQ_COLOR_BASE_IDX 2
#define mmCM0_CM_IGAM_LUT_30_COLOR 0x0ca3
#define mmCM0_CM_IGAM_LUT_30_COLOR_BASE_IDX 2
#define mmCM0_CM_IGAM_LUT_PWL_DATA 0x0ca4
#define mmCM0_CM_IGAM_LUT_PWL_DATA_BASE_IDX 2
#define mmCM0_CM_IGAM_LUT_AUTOFILL 0x0ca5
#define mmCM0_CM_IGAM_LUT_AUTOFILL_BASE_IDX 2
#define mmCM0_CM_IGAM_LUT_BW_OFFSET_BLUE 0x0ca6
#define mmCM0_CM_IGAM_LUT_BW_OFFSET_BLUE_BASE_IDX 2
#define mmCM0_CM_IGAM_LUT_BW_OFFSET_GREEN 0x0ca7
#define mmCM0_CM_IGAM_LUT_BW_OFFSET_GREEN_BASE_IDX 2
#define mmCM0_CM_IGAM_LUT_BW_OFFSET_RED 0x0ca8
#define mmCM0_CM_IGAM_LUT_BW_OFFSET_RED_BASE_IDX 2
#define mmCM0_CM_ICSC_CONTROL 0x0ca9
#define mmCM0_CM_ICSC_CONTROL_BASE_IDX 2
#define mmCM0_CM_ICSC_C11_C12 0x0caa
#define mmCM0_CM_ICSC_C11_C12_BASE_IDX 2
#define mmCM0_CM_ICSC_C13_C14 0x0cab
#define mmCM0_CM_ICSC_C13_C14_BASE_IDX 2
#define mmCM0_CM_ICSC_C21_C22 0x0cac
#define mmCM0_CM_ICSC_C21_C22_BASE_IDX 2
#define mmCM0_CM_ICSC_C23_C24 0x0cad
#define mmCM0_CM_ICSC_C23_C24_BASE_IDX 2
#define mmCM0_CM_ICSC_C31_C32 0x0cae
#define mmCM0_CM_ICSC_C31_C32_BASE_IDX 2
#define mmCM0_CM_ICSC_C33_C34 0x0caf
#define mmCM0_CM_ICSC_C33_C34_BASE_IDX 2
#define mmCM0_CM_GAMUT_REMAP_CONTROL 0x0cb0
#define mmCM0_CM_GAMUT_REMAP_CONTROL_BASE_IDX 2
#define mmCM0_CM_GAMUT_REMAP_C11_C12 0x0cb1
#define mmCM0_CM_GAMUT_REMAP_C11_C12_BASE_IDX 2
#define mmCM0_CM_GAMUT_REMAP_C13_C14 0x0cb2
#define mmCM0_CM_GAMUT_REMAP_C13_C14_BASE_IDX 2
#define mmCM0_CM_GAMUT_REMAP_C21_C22 0x0cb3
#define mmCM0_CM_GAMUT_REMAP_C21_C22_BASE_IDX 2
#define mmCM0_CM_GAMUT_REMAP_C23_C24 0x0cb4
#define mmCM0_CM_GAMUT_REMAP_C23_C24_BASE_IDX 2
#define mmCM0_CM_GAMUT_REMAP_C31_C32 0x0cb5
#define mmCM0_CM_GAMUT_REMAP_C31_C32_BASE_IDX 2
#define mmCM0_CM_GAMUT_REMAP_C33_C34 0x0cb6
#define mmCM0_CM_GAMUT_REMAP_C33_C34_BASE_IDX 2
#define mmCM0_CM_OCSC_CONTROL 0x0cb7
#define mmCM0_CM_OCSC_CONTROL_BASE_IDX 2
#define mmCM0_CM_OCSC_C11_C12 0x0cb8
#define mmCM0_CM_OCSC_C11_C12_BASE_IDX 2
#define mmCM0_CM_OCSC_C13_C14 0x0cb9
#define mmCM0_CM_OCSC_C13_C14_BASE_IDX 2
#define mmCM0_CM_OCSC_C21_C22 0x0cba
#define mmCM0_CM_OCSC_C21_C22_BASE_IDX 2
#define mmCM0_CM_OCSC_C23_C24 0x0cbb
#define mmCM0_CM_OCSC_C23_C24_BASE_IDX 2
#define mmCM0_CM_OCSC_C31_C32 0x0cbc
#define mmCM0_CM_OCSC_C31_C32_BASE_IDX 2
#define mmCM0_CM_OCSC_C33_C34 0x0cbd
#define mmCM0_CM_OCSC_C33_C34_BASE_IDX 2
#define mmCM0_CM_BNS_VALUES_R 0x0cbe
#define mmCM0_CM_BNS_VALUES_R_BASE_IDX 2
#define mmCM0_CM_BNS_VALUES_G 0x0cbf
#define mmCM0_CM_BNS_VALUES_G_BASE_IDX 2
#define mmCM0_CM_BNS_VALUES_B 0x0cc0
#define mmCM0_CM_BNS_VALUES_B_BASE_IDX 2
#define mmCM0_CM_DGAM_CONTROL 0x0cc1
#define mmCM0_CM_DGAM_CONTROL_BASE_IDX 2
#define mmCM0_CM_DGAM_LUT_INDEX 0x0cc2
#define mmCM0_CM_DGAM_LUT_INDEX_BASE_IDX 2
#define mmCM0_CM_DGAM_LUT_DATA 0x0cc3
#define mmCM0_CM_DGAM_LUT_DATA_BASE_IDX 2
#define mmCM0_CM_DGAM_LUT_WRITE_EN_MASK 0x0cc4
#define mmCM0_CM_DGAM_LUT_WRITE_EN_MASK_BASE_IDX 2
#define mmCM0_CM_DGAM_RAMA_START_CNTL_B 0x0cc5
#define mmCM0_CM_DGAM_RAMA_START_CNTL_B_BASE_IDX 2
#define mmCM0_CM_DGAM_RAMA_START_CNTL_G 0x0cc6
#define mmCM0_CM_DGAM_RAMA_START_CNTL_G_BASE_IDX 2
#define mmCM0_CM_DGAM_RAMA_START_CNTL_R 0x0cc7
#define mmCM0_CM_DGAM_RAMA_START_CNTL_R_BASE_IDX 2
#define mmCM0_CM_DGAM_RAMA_SLOPE_CNTL_B 0x0cc8
#define mmCM0_CM_DGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2
#define mmCM0_CM_DGAM_RAMA_SLOPE_CNTL_G 0x0cc9
#define mmCM0_CM_DGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2
#define mmCM0_CM_DGAM_RAMA_SLOPE_CNTL_R 0x0cca
#define mmCM0_CM_DGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2
#define mmCM0_CM_DGAM_RAMA_END_CNTL1_B 0x0ccb
#define mmCM0_CM_DGAM_RAMA_END_CNTL1_B_BASE_IDX 2
#define mmCM0_CM_DGAM_RAMA_END_CNTL2_B 0x0ccc
#define mmCM0_CM_DGAM_RAMA_END_CNTL2_B_BASE_IDX 2
#define mmCM0_CM_DGAM_RAMA_END_CNTL1_G 0x0ccd
#define mmCM0_CM_DGAM_RAMA_END_CNTL1_G_BASE_IDX 2
#define mmCM0_CM_DGAM_RAMA_END_CNTL2_G 0x0cce
#define mmCM0_CM_DGAM_RAMA_END_CNTL2_G_BASE_IDX 2
#define mmCM0_CM_DGAM_RAMA_END_CNTL1_R 0x0ccf
#define mmCM0_CM_DGAM_RAMA_END_CNTL1_R_BASE_IDX 2
#define mmCM0_CM_DGAM_RAMA_END_CNTL2_R 0x0cd0
#define mmCM0_CM_DGAM_RAMA_END_CNTL2_R_BASE_IDX 2
#define mmCM0_CM_DGAM_RAMA_REGION_0_1 0x0cd1
#define mmCM0_CM_DGAM_RAMA_REGION_0_1_BASE_IDX 2
#define mmCM0_CM_DGAM_RAMA_REGION_2_3 0x0cd2
#define mmCM0_CM_DGAM_RAMA_REGION_2_3_BASE_IDX 2
#define mmCM0_CM_DGAM_RAMA_REGION_4_5 0x0cd3
#define mmCM0_CM_DGAM_RAMA_REGION_4_5_BASE_IDX 2
#define mmCM0_CM_DGAM_RAMA_REGION_6_7 0x0cd4
#define mmCM0_CM_DGAM_RAMA_REGION_6_7_BASE_IDX 2
#define mmCM0_CM_DGAM_RAMA_REGION_8_9 0x0cd5
#define mmCM0_CM_DGAM_RAMA_REGION_8_9_BASE_IDX 2
#define mmCM0_CM_DGAM_RAMA_REGION_10_11 0x0cd6
#define mmCM0_CM_DGAM_RAMA_REGION_10_11_BASE_IDX 2
#define mmCM0_CM_DGAM_RAMA_REGION_12_13 0x0cd7
#define mmCM0_CM_DGAM_RAMA_REGION_12_13_BASE_IDX 2
#define mmCM0_CM_DGAM_RAMA_REGION_14_15 0x0cd8
#define mmCM0_CM_DGAM_RAMA_REGION_14_15_BASE_IDX 2
#define mmCM0_CM_DGAM_RAMB_START_CNTL_B 0x0cd9
#define mmCM0_CM_DGAM_RAMB_START_CNTL_B_BASE_IDX 2
#define mmCM0_CM_DGAM_RAMB_START_CNTL_G 0x0cda
#define mmCM0_CM_DGAM_RAMB_START_CNTL_G_BASE_IDX 2
#define mmCM0_CM_DGAM_RAMB_START_CNTL_R 0x0cdb
#define mmCM0_CM_DGAM_RAMB_START_CNTL_R_BASE_IDX 2
#define mmCM0_CM_DGAM_RAMB_SLOPE_CNTL_B 0x0cdc
#define mmCM0_CM_DGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2
#define mmCM0_CM_DGAM_RAMB_SLOPE_CNTL_G 0x0cdd
#define mmCM0_CM_DGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2
#define mmCM0_CM_DGAM_RAMB_SLOPE_CNTL_R 0x0cde
#define mmCM0_CM_DGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2
#define mmCM0_CM_DGAM_RAMB_END_CNTL1_B 0x0cdf
#define mmCM0_CM_DGAM_RAMB_END_CNTL1_B_BASE_IDX 2
#define mmCM0_CM_DGAM_RAMB_END_CNTL2_B 0x0ce0
#define mmCM0_CM_DGAM_RAMB_END_CNTL2_B_BASE_IDX 2
#define mmCM0_CM_DGAM_RAMB_END_CNTL1_G 0x0ce1
#define mmCM0_CM_DGAM_RAMB_END_CNTL1_G_BASE_IDX 2
#define mmCM0_CM_DGAM_RAMB_END_CNTL2_G 0x0ce2
#define mmCM0_CM_DGAM_RAMB_END_CNTL2_G_BASE_IDX 2
#define mmCM0_CM_DGAM_RAMB_END_CNTL1_R 0x0ce3
#define mmCM0_CM_DGAM_RAMB_END_CNTL1_R_BASE_IDX 2
#define mmCM0_CM_DGAM_RAMB_END_CNTL2_R 0x0ce4
#define mmCM0_CM_DGAM_RAMB_END_CNTL2_R_BASE_IDX 2
#define mmCM0_CM_DGAM_RAMB_REGION_0_1 0x0ce5
#define mmCM0_CM_DGAM_RAMB_REGION_0_1_BASE_IDX 2
#define mmCM0_CM_DGAM_RAMB_REGION_2_3 0x0ce6
#define mmCM0_CM_DGAM_RAMB_REGION_2_3_BASE_IDX 2
#define mmCM0_CM_DGAM_RAMB_REGION_4_5 0x0ce7
#define mmCM0_CM_DGAM_RAMB_REGION_4_5_BASE_IDX 2
#define mmCM0_CM_DGAM_RAMB_REGION_6_7 0x0ce8
#define mmCM0_CM_DGAM_RAMB_REGION_6_7_BASE_IDX 2
#define mmCM0_CM_DGAM_RAMB_REGION_8_9 0x0ce9
#define mmCM0_CM_DGAM_RAMB_REGION_8_9_BASE_IDX 2
#define mmCM0_CM_DGAM_RAMB_REGION_10_11 0x0cea
#define mmCM0_CM_DGAM_RAMB_REGION_10_11_BASE_IDX 2
#define mmCM0_CM_DGAM_RAMB_REGION_12_13 0x0ceb
#define mmCM0_CM_DGAM_RAMB_REGION_12_13_BASE_IDX 2
#define mmCM0_CM_DGAM_RAMB_REGION_14_15 0x0cec
#define mmCM0_CM_DGAM_RAMB_REGION_14_15_BASE_IDX 2
#define mmCM0_CM_RGAM_CONTROL 0x0ced
#define mmCM0_CM_RGAM_CONTROL_BASE_IDX 2
#define mmCM0_CM_RGAM_LUT_INDEX 0x0cee
#define mmCM0_CM_RGAM_LUT_INDEX_BASE_IDX 2
#define mmCM0_CM_RGAM_LUT_DATA 0x0cef
#define mmCM0_CM_RGAM_LUT_DATA_BASE_IDX 2
#define mmCM0_CM_RGAM_LUT_WRITE_EN_MASK 0x0cf0
#define mmCM0_CM_RGAM_LUT_WRITE_EN_MASK_BASE_IDX 2
#define mmCM0_CM_RGAM_RAMA_START_CNTL_B 0x0cf1
#define mmCM0_CM_RGAM_RAMA_START_CNTL_B_BASE_IDX 2
#define mmCM0_CM_RGAM_RAMA_START_CNTL_G 0x0cf2
#define mmCM0_CM_RGAM_RAMA_START_CNTL_G_BASE_IDX 2
#define mmCM0_CM_RGAM_RAMA_START_CNTL_R 0x0cf3
#define mmCM0_CM_RGAM_RAMA_START_CNTL_R_BASE_IDX 2
#define mmCM0_CM_RGAM_RAMA_SLOPE_CNTL_B 0x0cf4
#define mmCM0_CM_RGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2
#define mmCM0_CM_RGAM_RAMA_SLOPE_CNTL_G 0x0cf5
#define mmCM0_CM_RGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2
#define mmCM0_CM_RGAM_RAMA_SLOPE_CNTL_R 0x0cf6
#define mmCM0_CM_RGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2
#define mmCM0_CM_RGAM_RAMA_END_CNTL1_B 0x0cf7
#define mmCM0_CM_RGAM_RAMA_END_CNTL1_B_BASE_IDX 2
#define mmCM0_CM_RGAM_RAMA_END_CNTL2_B 0x0cf8
#define mmCM0_CM_RGAM_RAMA_END_CNTL2_B_BASE_IDX 2
#define mmCM0_CM_RGAM_RAMA_END_CNTL1_G 0x0cf9
#define mmCM0_CM_RGAM_RAMA_END_CNTL1_G_BASE_IDX 2
#define mmCM0_CM_RGAM_RAMA_END_CNTL2_G 0x0cfa
#define mmCM0_CM_RGAM_RAMA_END_CNTL2_G_BASE_IDX 2
#define mmCM0_CM_RGAM_RAMA_END_CNTL1_R 0x0cfb
#define mmCM0_CM_RGAM_RAMA_END_CNTL1_R_BASE_IDX 2
#define mmCM0_CM_RGAM_RAMA_END_CNTL2_R 0x0cfc
#define mmCM0_CM_RGAM_RAMA_END_CNTL2_R_BASE_IDX 2
#define mmCM0_CM_RGAM_RAMA_REGION_0_1 0x0cfd
#define mmCM0_CM_RGAM_RAMA_REGION_0_1_BASE_IDX 2
#define mmCM0_CM_RGAM_RAMA_REGION_2_3 0x0cfe
#define mmCM0_CM_RGAM_RAMA_REGION_2_3_BASE_IDX 2
#define mmCM0_CM_RGAM_RAMA_REGION_4_5 0x0cff
#define mmCM0_CM_RGAM_RAMA_REGION_4_5_BASE_IDX 2
#define mmCM0_CM_RGAM_RAMA_REGION_6_7 0x0d00
#define mmCM0_CM_RGAM_RAMA_REGION_6_7_BASE_IDX 2
#define mmCM0_CM_RGAM_RAMA_REGION_8_9 0x0d01
#define mmCM0_CM_RGAM_RAMA_REGION_8_9_BASE_IDX 2
#define mmCM0_CM_RGAM_RAMA_REGION_10_11 0x0d02
#define mmCM0_CM_RGAM_RAMA_REGION_10_11_BASE_IDX 2
#define mmCM0_CM_RGAM_RAMA_REGION_12_13 0x0d03
#define mmCM0_CM_RGAM_RAMA_REGION_12_13_BASE_IDX 2
#define mmCM0_CM_RGAM_RAMA_REGION_14_15 0x0d04
#define mmCM0_CM_RGAM_RAMA_REGION_14_15_BASE_IDX 2
#define mmCM0_CM_RGAM_RAMA_REGION_16_17 0x0d05
#define mmCM0_CM_RGAM_RAMA_REGION_16_17_BASE_IDX 2
#define mmCM0_CM_RGAM_RAMA_REGION_18_19 0x0d06
#define mmCM0_CM_RGAM_RAMA_REGION_18_19_BASE_IDX 2
#define mmCM0_CM_RGAM_RAMA_REGION_20_21 0x0d07
#define mmCM0_CM_RGAM_RAMA_REGION_20_21_BASE_IDX 2
#define mmCM0_CM_RGAM_RAMA_REGION_22_23 0x0d08
#define mmCM0_CM_RGAM_RAMA_REGION_22_23_BASE_IDX 2
#define mmCM0_CM_RGAM_RAMA_REGION_24_25 0x0d09
#define mmCM0_CM_RGAM_RAMA_REGION_24_25_BASE_IDX 2
#define mmCM0_CM_RGAM_RAMA_REGION_26_27 0x0d0a
#define mmCM0_CM_RGAM_RAMA_REGION_26_27_BASE_IDX 2
#define mmCM0_CM_RGAM_RAMA_REGION_28_29 0x0d0b
#define mmCM0_CM_RGAM_RAMA_REGION_28_29_BASE_IDX 2
#define mmCM0_CM_RGAM_RAMA_REGION_30_31 0x0d0c
#define mmCM0_CM_RGAM_RAMA_REGION_30_31_BASE_IDX 2
#define mmCM0_CM_RGAM_RAMA_REGION_32_33 0x0d0d
#define mmCM0_CM_RGAM_RAMA_REGION_32_33_BASE_IDX 2
#define mmCM0_CM_RGAM_RAMB_START_CNTL_B 0x0d0e
#define mmCM0_CM_RGAM_RAMB_START_CNTL_B_BASE_IDX 2
#define mmCM0_CM_RGAM_RAMB_START_CNTL_G 0x0d0f
#define mmCM0_CM_RGAM_RAMB_START_CNTL_G_BASE_IDX 2
#define mmCM0_CM_RGAM_RAMB_START_CNTL_R 0x0d10
#define mmCM0_CM_RGAM_RAMB_START_CNTL_R_BASE_IDX 2
#define mmCM0_CM_RGAM_RAMB_SLOPE_CNTL_B 0x0d11
#define mmCM0_CM_RGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2
#define mmCM0_CM_RGAM_RAMB_SLOPE_CNTL_G 0x0d12
#define mmCM0_CM_RGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2
#define mmCM0_CM_RGAM_RAMB_SLOPE_CNTL_R 0x0d13
#define mmCM0_CM_RGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2
#define mmCM0_CM_RGAM_RAMB_END_CNTL1_B 0x0d14
#define mmCM0_CM_RGAM_RAMB_END_CNTL1_B_BASE_IDX 2
#define mmCM0_CM_RGAM_RAMB_END_CNTL2_B 0x0d15
#define mmCM0_CM_RGAM_RAMB_END_CNTL2_B_BASE_IDX 2
#define mmCM0_CM_RGAM_RAMB_END_CNTL1_G 0x0d16
#define mmCM0_CM_RGAM_RAMB_END_CNTL1_G_BASE_IDX 2
#define mmCM0_CM_RGAM_RAMB_END_CNTL2_G 0x0d17
#define mmCM0_CM_RGAM_RAMB_END_CNTL2_G_BASE_IDX 2
#define mmCM0_CM_RGAM_RAMB_END_CNTL1_R 0x0d18
#define mmCM0_CM_RGAM_RAMB_END_CNTL1_R_BASE_IDX 2
#define mmCM0_CM_RGAM_RAMB_END_CNTL2_R 0x0d19
#define mmCM0_CM_RGAM_RAMB_END_CNTL2_R_BASE_IDX 2
#define mmCM0_CM_RGAM_RAMB_REGION_0_1 0x0d1a
#define mmCM0_CM_RGAM_RAMB_REGION_0_1_BASE_IDX 2
#define mmCM0_CM_RGAM_RAMB_REGION_2_3 0x0d1b
#define mmCM0_CM_RGAM_RAMB_REGION_2_3_BASE_IDX 2
#define mmCM0_CM_RGAM_RAMB_REGION_4_5 0x0d1c
#define mmCM0_CM_RGAM_RAMB_REGION_4_5_BASE_IDX 2
#define mmCM0_CM_RGAM_RAMB_REGION_6_7 0x0d1d
#define mmCM0_CM_RGAM_RAMB_REGION_6_7_BASE_IDX 2
#define mmCM0_CM_RGAM_RAMB_REGION_8_9 0x0d1e
#define mmCM0_CM_RGAM_RAMB_REGION_8_9_BASE_IDX 2
#define mmCM0_CM_RGAM_RAMB_REGION_10_11 0x0d1f
#define mmCM0_CM_RGAM_RAMB_REGION_10_11_BASE_IDX 2
#define mmCM0_CM_RGAM_RAMB_REGION_12_13 0x0d20
#define mmCM0_CM_RGAM_RAMB_REGION_12_13_BASE_IDX 2
#define mmCM0_CM_RGAM_RAMB_REGION_14_15 0x0d21
#define mmCM0_CM_RGAM_RAMB_REGION_14_15_BASE_IDX 2
#define mmCM0_CM_RGAM_RAMB_REGION_16_17 0x0d22
#define mmCM0_CM_RGAM_RAMB_REGION_16_17_BASE_IDX 2
#define mmCM0_CM_RGAM_RAMB_REGION_18_19 0x0d23
#define mmCM0_CM_RGAM_RAMB_REGION_18_19_BASE_IDX 2
#define mmCM0_CM_RGAM_RAMB_REGION_20_21 0x0d24
#define mmCM0_CM_RGAM_RAMB_REGION_20_21_BASE_IDX 2
#define mmCM0_CM_RGAM_RAMB_REGION_22_23 0x0d25
#define mmCM0_CM_RGAM_RAMB_REGION_22_23_BASE_IDX 2
#define mmCM0_CM_RGAM_RAMB_REGION_24_25 0x0d26
#define mmCM0_CM_RGAM_RAMB_REGION_24_25_BASE_IDX 2
#define mmCM0_CM_RGAM_RAMB_REGION_26_27 0x0d27
#define mmCM0_CM_RGAM_RAMB_REGION_26_27_BASE_IDX 2
#define mmCM0_CM_RGAM_RAMB_REGION_28_29 0x0d28
#define mmCM0_CM_RGAM_RAMB_REGION_28_29_BASE_IDX 2
#define mmCM0_CM_RGAM_RAMB_REGION_30_31 0x0d29
#define mmCM0_CM_RGAM_RAMB_REGION_30_31_BASE_IDX 2
#define mmCM0_CM_RGAM_RAMB_REGION_32_33 0x0d2a
#define mmCM0_CM_RGAM_RAMB_REGION_32_33_BASE_IDX 2
#define mmCM0_CM_HDR_MULT_COEF 0x0d2b
#define mmCM0_CM_HDR_MULT_COEF_BASE_IDX 2
#define mmCM0_CM_RANGE_CLAMP_CONTROL_R 0x0d2c
#define mmCM0_CM_RANGE_CLAMP_CONTROL_R_BASE_IDX 2
#define mmCM0_CM_RANGE_CLAMP_CONTROL_G 0x0d2d
#define mmCM0_CM_RANGE_CLAMP_CONTROL_G_BASE_IDX 2
#define mmCM0_CM_RANGE_CLAMP_CONTROL_B 0x0d2e
#define mmCM0_CM_RANGE_CLAMP_CONTROL_B_BASE_IDX 2
#define mmCM0_CM_DENORM_CONTROL 0x0d2f
#define mmCM0_CM_DENORM_CONTROL_BASE_IDX 2
#define mmCM0_CM_CMOUT_CONTROL 0x0d30
#define mmCM0_CM_CMOUT_CONTROL_BASE_IDX 2
#define mmCM0_CM_CMOUT_RANDOM_SEEDS 0x0d31
#define mmCM0_CM_CMOUT_RANDOM_SEEDS_BASE_IDX 2
#define mmCM0_CM_MEM_PWR_CTRL 0x0d32
#define mmCM0_CM_MEM_PWR_CTRL_BASE_IDX 2
#define mmCM0_CM_MEM_PWR_STATUS 0x0d33
#define mmCM0_CM_MEM_PWR_STATUS_BASE_IDX 2
#define mmCM0_CM_TEST_DEBUG_INDEX 0x0d35
#define mmCM0_CM_TEST_DEBUG_INDEX_BASE_IDX 2
#define mmCM0_CM_TEST_DEBUG_DATA 0x0d36
#define mmCM0_CM_TEST_DEBUG_DATA_BASE_IDX 2
// addressBlock: dce_dc_dpp0_dispdec_dpp_dcperfmon_dc_perfmon_dispdec
// base address: 0x3530
#define mmDC_PERFMON12_PERFCOUNTER_CNTL 0x0d4c
#define mmDC_PERFMON12_PERFCOUNTER_CNTL_BASE_IDX 2
#define mmDC_PERFMON12_PERFCOUNTER_CNTL2 0x0d4d
#define mmDC_PERFMON12_PERFCOUNTER_CNTL2_BASE_IDX 2
#define mmDC_PERFMON12_PERFCOUNTER_STATE 0x0d4e
#define mmDC_PERFMON12_PERFCOUNTER_STATE_BASE_IDX 2
#define mmDC_PERFMON12_PERFMON_CNTL 0x0d4f
#define mmDC_PERFMON12_PERFMON_CNTL_BASE_IDX 2
#define mmDC_PERFMON12_PERFMON_CNTL2 0x0d50
#define mmDC_PERFMON12_PERFMON_CNTL2_BASE_IDX 2
#define mmDC_PERFMON12_PERFMON_CVALUE_INT_MISC 0x0d51
#define mmDC_PERFMON12_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
#define mmDC_PERFMON12_PERFMON_CVALUE_LOW 0x0d52
#define mmDC_PERFMON12_PERFMON_CVALUE_LOW_BASE_IDX 2
#define mmDC_PERFMON12_PERFMON_HI 0x0d53
#define mmDC_PERFMON12_PERFMON_HI_BASE_IDX 2
#define mmDC_PERFMON12_PERFMON_LOW 0x0d54
#define mmDC_PERFMON12_PERFMON_LOW_BASE_IDX 2
// addressBlock: dce_dc_dpp1_dispdec_dpp_top_dispdec
// base address: 0x46c
#define mmDPP_TOP1_DPP_CONTROL 0x0d58
#define mmDPP_TOP1_DPP_CONTROL_BASE_IDX 2
#define mmDPP_TOP1_DPP_SOFT_RESET 0x0d59
#define mmDPP_TOP1_DPP_SOFT_RESET_BASE_IDX 2
#define mmDPP_TOP1_DPP_CRC_VAL_R_G 0x0d5a
#define mmDPP_TOP1_DPP_CRC_VAL_R_G_BASE_IDX 2
#define mmDPP_TOP1_DPP_CRC_VAL_B_A 0x0d5b
#define mmDPP_TOP1_DPP_CRC_VAL_B_A_BASE_IDX 2
#define mmDPP_TOP1_DPP_CRC_CTRL 0x0d5c
#define mmDPP_TOP1_DPP_CRC_CTRL_BASE_IDX 2
#define mmDPP_TOP1_HOST_READ_CONTROL 0x0d5d
#define mmDPP_TOP1_HOST_READ_CONTROL_BASE_IDX 2
// addressBlock: dce_dc_dpp1_dispdec_cnvc_cfg_dispdec
// base address: 0x46c
#define mmCNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT 0x0d62
#define mmCNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX 2
#define mmCNVC_CFG1_FORMAT_CONTROL 0x0d63
#define mmCNVC_CFG1_FORMAT_CONTROL_BASE_IDX 2
#define mmCNVC_CFG1_FCNV_FP_SCALE_BIAS 0x0d64
#define mmCNVC_CFG1_FCNV_FP_SCALE_BIAS_BASE_IDX 2
#define mmCNVC_CFG1_DENORM_CONTROL 0x0d65
#define mmCNVC_CFG1_DENORM_CONTROL_BASE_IDX 2
#define mmCNVC_CFG1_COLOR_KEYER_CONTROL 0x0d67
#define mmCNVC_CFG1_COLOR_KEYER_CONTROL_BASE_IDX 2
#define mmCNVC_CFG1_COLOR_KEYER_ALPHA 0x0d68
#define mmCNVC_CFG1_COLOR_KEYER_ALPHA_BASE_IDX 2
#define mmCNVC_CFG1_COLOR_KEYER_RED 0x0d69
#define mmCNVC_CFG1_COLOR_KEYER_RED_BASE_IDX 2
#define mmCNVC_CFG1_COLOR_KEYER_GREEN 0x0d6a
#define mmCNVC_CFG1_COLOR_KEYER_GREEN_BASE_IDX 2
#define mmCNVC_CFG1_COLOR_KEYER_BLUE 0x0d6b
#define mmCNVC_CFG1_COLOR_KEYER_BLUE_BASE_IDX 2
// addressBlock: dce_dc_dpp1_dispdec_cnvc_cur_dispdec
// base address: 0x46c
#define mmCNVC_CUR1_CURSOR0_CONTROL 0x0d73
#define mmCNVC_CUR1_CURSOR0_CONTROL_BASE_IDX 2
#define mmCNVC_CUR1_CURSOR0_COLOR0 0x0d74
#define mmCNVC_CUR1_CURSOR0_COLOR0_BASE_IDX 2
#define mmCNVC_CUR1_CURSOR0_COLOR1 0x0d75
#define mmCNVC_CUR1_CURSOR0_COLOR1_BASE_IDX 2
#define mmCNVC_CUR1_CURSOR0_FP_SCALE_BIAS 0x0d76
#define mmCNVC_CUR1_CURSOR0_FP_SCALE_BIAS_BASE_IDX 2
// addressBlock: dce_dc_dpp1_dispdec_dscl_dispdec
// base address: 0x46c
#define mmDSCL1_SCL_COEF_RAM_TAP_SELECT 0x0d7d
#define mmDSCL1_SCL_COEF_RAM_TAP_SELECT_BASE_IDX 2
#define mmDSCL1_SCL_COEF_RAM_TAP_DATA 0x0d7e
#define mmDSCL1_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2
#define mmDSCL1_SCL_MODE 0x0d7f
#define mmDSCL1_SCL_MODE_BASE_IDX 2
#define mmDSCL1_SCL_TAP_CONTROL 0x0d80
#define mmDSCL1_SCL_TAP_CONTROL_BASE_IDX 2
#define mmDSCL1_DSCL_CONTROL 0x0d81
#define mmDSCL1_DSCL_CONTROL_BASE_IDX 2
#define mmDSCL1_DSCL_2TAP_CONTROL 0x0d82
#define mmDSCL1_DSCL_2TAP_CONTROL_BASE_IDX 2
#define mmDSCL1_SCL_MANUAL_REPLICATE_CONTROL 0x0d83
#define mmDSCL1_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2
#define mmDSCL1_SCL_HORZ_FILTER_SCALE_RATIO 0x0d84
#define mmDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2
#define mmDSCL1_SCL_HORZ_FILTER_INIT 0x0d85
#define mmDSCL1_SCL_HORZ_FILTER_INIT_BASE_IDX 2
#define mmDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C 0x0d86
#define mmDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2
#define mmDSCL1_SCL_HORZ_FILTER_INIT_C 0x0d87
#define mmDSCL1_SCL_HORZ_FILTER_INIT_C_BASE_IDX 2
#define mmDSCL1_SCL_VERT_FILTER_SCALE_RATIO 0x0d88
#define mmDSCL1_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2
#define mmDSCL1_SCL_VERT_FILTER_INIT 0x0d89
#define mmDSCL1_SCL_VERT_FILTER_INIT_BASE_IDX 2
#define mmDSCL1_SCL_VERT_FILTER_INIT_BOT 0x0d8a
#define mmDSCL1_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2
#define mmDSCL1_SCL_VERT_FILTER_SCALE_RATIO_C 0x0d8b
#define mmDSCL1_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2
#define mmDSCL1_SCL_VERT_FILTER_INIT_C 0x0d8c
#define mmDSCL1_SCL_VERT_FILTER_INIT_C_BASE_IDX 2
#define mmDSCL1_SCL_VERT_FILTER_INIT_BOT_C 0x0d8d
#define mmDSCL1_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX 2
#define mmDSCL1_SCL_BLACK_OFFSET 0x0d8e
#define mmDSCL1_SCL_BLACK_OFFSET_BASE_IDX 2
#define mmDSCL1_DSCL_UPDATE 0x0d8f
#define mmDSCL1_DSCL_UPDATE_BASE_IDX 2
#define mmDSCL1_DSCL_AUTOCAL 0x0d90
#define mmDSCL1_DSCL_AUTOCAL_BASE_IDX 2
#define mmDSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT 0x0d91
#define mmDSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2
#define mmDSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM 0x0d92
#define mmDSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2
#define mmDSCL1_OTG_H_BLANK 0x0d93
#define mmDSCL1_OTG_H_BLANK_BASE_IDX 2
#define mmDSCL1_OTG_V_BLANK 0x0d94
#define mmDSCL1_OTG_V_BLANK_BASE_IDX 2
#define mmDSCL1_RECOUT_START 0x0d95
#define mmDSCL1_RECOUT_START_BASE_IDX 2
#define mmDSCL1_RECOUT_SIZE 0x0d96
#define mmDSCL1_RECOUT_SIZE_BASE_IDX 2
#define mmDSCL1_MPC_SIZE 0x0d97
#define mmDSCL1_MPC_SIZE_BASE_IDX 2
#define mmDSCL1_LB_DATA_FORMAT 0x0d98
#define mmDSCL1_LB_DATA_FORMAT_BASE_IDX 2
#define mmDSCL1_LB_MEMORY_CTRL 0x0d99
#define mmDSCL1_LB_MEMORY_CTRL_BASE_IDX 2
#define mmDSCL1_LB_V_COUNTER 0x0d9a
#define mmDSCL1_LB_V_COUNTER_BASE_IDX 2
#define mmDSCL1_DSCL_MEM_PWR_CTRL 0x0d9b
#define mmDSCL1_DSCL_MEM_PWR_CTRL_BASE_IDX 2
#define mmDSCL1_DSCL_MEM_PWR_STATUS 0x0d9c
#define mmDSCL1_DSCL_MEM_PWR_STATUS_BASE_IDX 2
#define mmDSCL1_OBUF_CONTROL 0x0d9d
#define mmDSCL1_OBUF_CONTROL_BASE_IDX 2
#define mmDSCL1_OBUF_MEM_PWR_CTRL 0x0d9e
#define mmDSCL1_OBUF_MEM_PWR_CTRL_BASE_IDX 2
// addressBlock: dce_dc_dpp1_dispdec_cm_dispdec
// base address: 0x46c
#define mmCM1_CM_CONTROL 0x0dad
#define mmCM1_CM_CONTROL_BASE_IDX 2
#define mmCM1_CM_COMA_C11_C12 0x0dae
#define mmCM1_CM_COMA_C11_C12_BASE_IDX 2
#define mmCM1_CM_COMA_C13_C14 0x0daf
#define mmCM1_CM_COMA_C13_C14_BASE_IDX 2
#define mmCM1_CM_COMA_C21_C22 0x0db0
#define mmCM1_CM_COMA_C21_C22_BASE_IDX 2
#define mmCM1_CM_COMA_C23_C24 0x0db1
#define mmCM1_CM_COMA_C23_C24_BASE_IDX 2
#define mmCM1_CM_COMA_C31_C32 0x0db2
#define mmCM1_CM_COMA_C31_C32_BASE_IDX 2
#define mmCM1_CM_COMA_C33_C34 0x0db3
#define mmCM1_CM_COMA_C33_C34_BASE_IDX 2
#define mmCM1_CM_COMB_C11_C12 0x0db4
#define mmCM1_CM_COMB_C11_C12_BASE_IDX 2
#define mmCM1_CM_COMB_C13_C14 0x0db5
#define mmCM1_CM_COMB_C13_C14_BASE_IDX 2
#define mmCM1_CM_COMB_C21_C22 0x0db6
#define mmCM1_CM_COMB_C21_C22_BASE_IDX 2
#define mmCM1_CM_COMB_C23_C24 0x0db7
#define mmCM1_CM_COMB_C23_C24_BASE_IDX 2
#define mmCM1_CM_COMB_C31_C32 0x0db8
#define mmCM1_CM_COMB_C31_C32_BASE_IDX 2
#define mmCM1_CM_COMB_C33_C34 0x0db9
#define mmCM1_CM_COMB_C33_C34_BASE_IDX 2
#define mmCM1_CM_IGAM_CONTROL 0x0dba
#define mmCM1_CM_IGAM_CONTROL_BASE_IDX 2
#define mmCM1_CM_IGAM_LUT_RW_CONTROL 0x0dbb
#define mmCM1_CM_IGAM_LUT_RW_CONTROL_BASE_IDX 2
#define mmCM1_CM_IGAM_LUT_RW_INDEX 0x0dbc
#define mmCM1_CM_IGAM_LUT_RW_INDEX_BASE_IDX 2
#define mmCM1_CM_IGAM_LUT_SEQ_COLOR 0x0dbd
#define mmCM1_CM_IGAM_LUT_SEQ_COLOR_BASE_IDX 2
#define mmCM1_CM_IGAM_LUT_30_COLOR 0x0dbe
#define mmCM1_CM_IGAM_LUT_30_COLOR_BASE_IDX 2
#define mmCM1_CM_IGAM_LUT_PWL_DATA 0x0dbf
#define mmCM1_CM_IGAM_LUT_PWL_DATA_BASE_IDX 2
#define mmCM1_CM_IGAM_LUT_AUTOFILL 0x0dc0
#define mmCM1_CM_IGAM_LUT_AUTOFILL_BASE_IDX 2
#define mmCM1_CM_IGAM_LUT_BW_OFFSET_BLUE 0x0dc1
#define mmCM1_CM_IGAM_LUT_BW_OFFSET_BLUE_BASE_IDX 2
#define mmCM1_CM_IGAM_LUT_BW_OFFSET_GREEN 0x0dc2
#define mmCM1_CM_IGAM_LUT_BW_OFFSET_GREEN_BASE_IDX 2
#define mmCM1_CM_IGAM_LUT_BW_OFFSET_RED 0x0dc3
#define mmCM1_CM_IGAM_LUT_BW_OFFSET_RED_BASE_IDX 2
#define mmCM1_CM_ICSC_CONTROL 0x0dc4
#define mmCM1_CM_ICSC_CONTROL_BASE_IDX 2
#define mmCM1_CM_ICSC_C11_C12 0x0dc5
#define mmCM1_CM_ICSC_C11_C12_BASE_IDX 2
#define mmCM1_CM_ICSC_C13_C14 0x0dc6
#define mmCM1_CM_ICSC_C13_C14_BASE_IDX 2
#define mmCM1_CM_ICSC_C21_C22 0x0dc7
#define mmCM1_CM_ICSC_C21_C22_BASE_IDX 2
#define mmCM1_CM_ICSC_C23_C24 0x0dc8
#define mmCM1_CM_ICSC_C23_C24_BASE_IDX 2
#define mmCM1_CM_ICSC_C31_C32 0x0dc9
#define mmCM1_CM_ICSC_C31_C32_BASE_IDX 2
#define mmCM1_CM_ICSC_C33_C34 0x0dca
#define mmCM1_CM_ICSC_C33_C34_BASE_IDX 2
#define mmCM1_CM_GAMUT_REMAP_CONTROL 0x0dcb
#define mmCM1_CM_GAMUT_REMAP_CONTROL_BASE_IDX 2
#define mmCM1_CM_GAMUT_REMAP_C11_C12 0x0dcc
#define mmCM1_CM_GAMUT_REMAP_C11_C12_BASE_IDX 2
#define mmCM1_CM_GAMUT_REMAP_C13_C14 0x0dcd
#define mmCM1_CM_GAMUT_REMAP_C13_C14_BASE_IDX 2
#define mmCM1_CM_GAMUT_REMAP_C21_C22 0x0dce
#define mmCM1_CM_GAMUT_REMAP_C21_C22_BASE_IDX 2
#define mmCM1_CM_GAMUT_REMAP_C23_C24 0x0dcf
#define mmCM1_CM_GAMUT_REMAP_C23_C24_BASE_IDX 2
#define mmCM1_CM_GAMUT_REMAP_C31_C32 0x0dd0
#define mmCM1_CM_GAMUT_REMAP_C31_C32_BASE_IDX 2
#define mmCM1_CM_GAMUT_REMAP_C33_C34 0x0dd1
#define mmCM1_CM_GAMUT_REMAP_C33_C34_BASE_IDX 2
#define mmCM1_CM_OCSC_CONTROL 0x0dd2
#define mmCM1_CM_OCSC_CONTROL_BASE_IDX 2
#define mmCM1_CM_OCSC_C11_C12 0x0dd3
#define mmCM1_CM_OCSC_C11_C12_BASE_IDX 2
#define mmCM1_CM_OCSC_C13_C14 0x0dd4
#define mmCM1_CM_OCSC_C13_C14_BASE_IDX 2
#define mmCM1_CM_OCSC_C21_C22 0x0dd5
#define mmCM1_CM_OCSC_C21_C22_BASE_IDX 2
#define mmCM1_CM_OCSC_C23_C24 0x0dd6
#define mmCM1_CM_OCSC_C23_C24_BASE_IDX 2
#define mmCM1_CM_OCSC_C31_C32 0x0dd7
#define mmCM1_CM_OCSC_C31_C32_BASE_IDX 2
#define mmCM1_CM_OCSC_C33_C34 0x0dd8
#define mmCM1_CM_OCSC_C33_C34_BASE_IDX 2
#define mmCM1_CM_BNS_VALUES_R 0x0dd9
#define mmCM1_CM_BNS_VALUES_R_BASE_IDX 2
#define mmCM1_CM_BNS_VALUES_G 0x0dda
#define mmCM1_CM_BNS_VALUES_G_BASE_IDX 2
#define mmCM1_CM_BNS_VALUES_B 0x0ddb
#define mmCM1_CM_BNS_VALUES_B_BASE_IDX 2
#define mmCM1_CM_DGAM_CONTROL 0x0ddc
#define mmCM1_CM_DGAM_CONTROL_BASE_IDX 2
#define mmCM1_CM_DGAM_LUT_INDEX 0x0ddd
#define mmCM1_CM_DGAM_LUT_INDEX_BASE_IDX 2
#define mmCM1_CM_DGAM_LUT_DATA 0x0dde
#define mmCM1_CM_DGAM_LUT_DATA_BASE_IDX 2
#define mmCM1_CM_DGAM_LUT_WRITE_EN_MASK 0x0ddf
#define mmCM1_CM_DGAM_LUT_WRITE_EN_MASK_BASE_IDX 2
#define mmCM1_CM_DGAM_RAMA_START_CNTL_B 0x0de0
#define mmCM1_CM_DGAM_RAMA_START_CNTL_B_BASE_IDX 2
#define mmCM1_CM_DGAM_RAMA_START_CNTL_G 0x0de1
#define mmCM1_CM_DGAM_RAMA_START_CNTL_G_BASE_IDX 2
#define mmCM1_CM_DGAM_RAMA_START_CNTL_R 0x0de2
#define mmCM1_CM_DGAM_RAMA_START_CNTL_R_BASE_IDX 2
#define mmCM1_CM_DGAM_RAMA_SLOPE_CNTL_B 0x0de3
#define mmCM1_CM_DGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2
#define mmCM1_CM_DGAM_RAMA_SLOPE_CNTL_G 0x0de4
#define mmCM1_CM_DGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2
#define mmCM1_CM_DGAM_RAMA_SLOPE_CNTL_R 0x0de5
#define mmCM1_CM_DGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2
#define mmCM1_CM_DGAM_RAMA_END_CNTL1_B 0x0de6
#define mmCM1_CM_DGAM_RAMA_END_CNTL1_B_BASE_IDX 2
#define mmCM1_CM_DGAM_RAMA_END_CNTL2_B 0x0de7
#define mmCM1_CM_DGAM_RAMA_END_CNTL2_B_BASE_IDX 2
#define mmCM1_CM_DGAM_RAMA_END_CNTL1_G 0x0de8
#define mmCM1_CM_DGAM_RAMA_END_CNTL1_G_BASE_IDX 2
#define mmCM1_CM_DGAM_RAMA_END_CNTL2_G 0x0de9
#define mmCM1_CM_DGAM_RAMA_END_CNTL2_G_BASE_IDX 2
#define mmCM1_CM_DGAM_RAMA_END_CNTL1_R 0x0dea
#define mmCM1_CM_DGAM_RAMA_END_CNTL1_R_BASE_IDX 2
#define mmCM1_CM_DGAM_RAMA_END_CNTL2_R 0x0deb
#define mmCM1_CM_DGAM_RAMA_END_CNTL2_R_BASE_IDX 2
#define mmCM1_CM_DGAM_RAMA_REGION_0_1 0x0dec
#define mmCM1_CM_DGAM_RAMA_REGION_0_1_BASE_IDX 2
#define mmCM1_CM_DGAM_RAMA_REGION_2_3 0x0ded
#define mmCM1_CM_DGAM_RAMA_REGION_2_3_BASE_IDX 2
#define mmCM1_CM_DGAM_RAMA_REGION_4_5 0x0dee
#define mmCM1_CM_DGAM_RAMA_REGION_4_5_BASE_IDX 2
#define mmCM1_CM_DGAM_RAMA_REGION_6_7 0x0def
#define mmCM1_CM_DGAM_RAMA_REGION_6_7_BASE_IDX 2
#define mmCM1_CM_DGAM_RAMA_REGION_8_9 0x0df0
#define mmCM1_CM_DGAM_RAMA_REGION_8_9_BASE_IDX 2
#define mmCM1_CM_DGAM_RAMA_REGION_10_11 0x0df1
#define mmCM1_CM_DGAM_RAMA_REGION_10_11_BASE_IDX 2
#define mmCM1_CM_DGAM_RAMA_REGION_12_13 0x0df2
#define mmCM1_CM_DGAM_RAMA_REGION_12_13_BASE_IDX 2
#define mmCM1_CM_DGAM_RAMA_REGION_14_15 0x0df3
#define mmCM1_CM_DGAM_RAMA_REGION_14_15_BASE_IDX 2
#define mmCM1_CM_DGAM_RAMB_START_CNTL_B 0x0df4
#define mmCM1_CM_DGAM_RAMB_START_CNTL_B_BASE_IDX 2
#define mmCM1_CM_DGAM_RAMB_START_CNTL_G 0x0df5
#define mmCM1_CM_DGAM_RAMB_START_CNTL_G_BASE_IDX 2
#define mmCM1_CM_DGAM_RAMB_START_CNTL_R 0x0df6
#define mmCM1_CM_DGAM_RAMB_START_CNTL_R_BASE_IDX 2
#define mmCM1_CM_DGAM_RAMB_SLOPE_CNTL_B 0x0df7
#define mmCM1_CM_DGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2
#define mmCM1_CM_DGAM_RAMB_SLOPE_CNTL_G 0x0df8
#define mmCM1_CM_DGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2
#define mmCM1_CM_DGAM_RAMB_SLOPE_CNTL_R 0x0df9
#define mmCM1_CM_DGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2
#define mmCM1_CM_DGAM_RAMB_END_CNTL1_B 0x0dfa
#define mmCM1_CM_DGAM_RAMB_END_CNTL1_B_BASE_IDX 2
#define mmCM1_CM_DGAM_RAMB_END_CNTL2_B 0x0dfb
#define mmCM1_CM_DGAM_RAMB_END_CNTL2_B_BASE_IDX 2
#define mmCM1_CM_DGAM_RAMB_END_CNTL1_G 0x0dfc
#define mmCM1_CM_DGAM_RAMB_END_CNTL1_G_BASE_IDX 2
#define mmCM1_CM_DGAM_RAMB_END_CNTL2_G 0x0dfd
#define mmCM1_CM_DGAM_RAMB_END_CNTL2_G_BASE_IDX 2
#define mmCM1_CM_DGAM_RAMB_END_CNTL1_R 0x0dfe
#define mmCM1_CM_DGAM_RAMB_END_CNTL1_R_BASE_IDX 2
#define mmCM1_CM_DGAM_RAMB_END_CNTL2_R 0x0dff
#define mmCM1_CM_DGAM_RAMB_END_CNTL2_R_BASE_IDX 2
#define mmCM1_CM_DGAM_RAMB_REGION_0_1 0x0e00
#define mmCM1_CM_DGAM_RAMB_REGION_0_1_BASE_IDX 2
#define mmCM1_CM_DGAM_RAMB_REGION_2_3 0x0e01
#define mmCM1_CM_DGAM_RAMB_REGION_2_3_BASE_IDX 2
#define mmCM1_CM_DGAM_RAMB_REGION_4_5 0x0e02
#define mmCM1_CM_DGAM_RAMB_REGION_4_5_BASE_IDX 2
#define mmCM1_CM_DGAM_RAMB_REGION_6_7 0x0e03
#define mmCM1_CM_DGAM_RAMB_REGION_6_7_BASE_IDX 2
#define mmCM1_CM_DGAM_RAMB_REGION_8_9 0x0e04
#define mmCM1_CM_DGAM_RAMB_REGION_8_9_BASE_IDX 2
#define mmCM1_CM_DGAM_RAMB_REGION_10_11 0x0e05
#define mmCM1_CM_DGAM_RAMB_REGION_10_11_BASE_IDX 2
#define mmCM1_CM_DGAM_RAMB_REGION_12_13 0x0e06
#define mmCM1_CM_DGAM_RAMB_REGION_12_13_BASE_IDX 2
#define mmCM1_CM_DGAM_RAMB_REGION_14_15 0x0e07
#define mmCM1_CM_DGAM_RAMB_REGION_14_15_BASE_IDX 2
#define mmCM1_CM_RGAM_CONTROL 0x0e08
#define mmCM1_CM_RGAM_CONTROL_BASE_IDX 2
#define mmCM1_CM_RGAM_LUT_INDEX 0x0e09
#define mmCM1_CM_RGAM_LUT_INDEX_BASE_IDX 2
#define mmCM1_CM_RGAM_LUT_DATA 0x0e0a
#define mmCM1_CM_RGAM_LUT_DATA_BASE_IDX 2
#define mmCM1_CM_RGAM_LUT_WRITE_EN_MASK 0x0e0b
#define mmCM1_CM_RGAM_LUT_WRITE_EN_MASK_BASE_IDX 2
#define mmCM1_CM_RGAM_RAMA_START_CNTL_B 0x0e0c
#define mmCM1_CM_RGAM_RAMA_START_CNTL_B_BASE_IDX 2
#define mmCM1_CM_RGAM_RAMA_START_CNTL_G 0x0e0d
#define mmCM1_CM_RGAM_RAMA_START_CNTL_G_BASE_IDX 2
#define mmCM1_CM_RGAM_RAMA_START_CNTL_R 0x0e0e
#define mmCM1_CM_RGAM_RAMA_START_CNTL_R_BASE_IDX 2
#define mmCM1_CM_RGAM_RAMA_SLOPE_CNTL_B 0x0e0f
#define mmCM1_CM_RGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2
#define mmCM1_CM_RGAM_RAMA_SLOPE_CNTL_G 0x0e10
#define mmCM1_CM_RGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2
#define mmCM1_CM_RGAM_RAMA_SLOPE_CNTL_R 0x0e11
#define mmCM1_CM_RGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2
#define mmCM1_CM_RGAM_RAMA_END_CNTL1_B 0x0e12
#define mmCM1_CM_RGAM_RAMA_END_CNTL1_B_BASE_IDX 2
#define mmCM1_CM_RGAM_RAMA_END_CNTL2_B 0x0e13
#define mmCM1_CM_RGAM_RAMA_END_CNTL2_B_BASE_IDX 2
#define mmCM1_CM_RGAM_RAMA_END_CNTL1_G 0x0e14
#define mmCM1_CM_RGAM_RAMA_END_CNTL1_G_BASE_IDX 2
#define mmCM1_CM_RGAM_RAMA_END_CNTL2_G 0x0e15
#define mmCM1_CM_RGAM_RAMA_END_CNTL2_G_BASE_IDX 2
#define mmCM1_CM_RGAM_RAMA_END_CNTL1_R 0x0e16
#define mmCM1_CM_RGAM_RAMA_END_CNTL1_R_BASE_IDX 2
#define mmCM1_CM_RGAM_RAMA_END_CNTL2_R 0x0e17
#define mmCM1_CM_RGAM_RAMA_END_CNTL2_R_BASE_IDX 2
#define mmCM1_CM_RGAM_RAMA_REGION_0_1 0x0e18
#define mmCM1_CM_RGAM_RAMA_REGION_0_1_BASE_IDX 2
#define mmCM1_CM_RGAM_RAMA_REGION_2_3 0x0e19
#define mmCM1_CM_RGAM_RAMA_REGION_2_3_BASE_IDX 2
#define mmCM1_CM_RGAM_RAMA_REGION_4_5 0x0e1a
#define mmCM1_CM_RGAM_RAMA_REGION_4_5_BASE_IDX 2
#define mmCM1_CM_RGAM_RAMA_REGION_6_7 0x0e1b
#define mmCM1_CM_RGAM_RAMA_REGION_6_7_BASE_IDX 2
#define mmCM1_CM_RGAM_RAMA_REGION_8_9 0x0e1c
#define mmCM1_CM_RGAM_RAMA_REGION_8_9_BASE_IDX 2
#define mmCM1_CM_RGAM_RAMA_REGION_10_11 0x0e1d
#define mmCM1_CM_RGAM_RAMA_REGION_10_11_BASE_IDX 2
#define mmCM1_CM_RGAM_RAMA_REGION_12_13 0x0e1e
#define mmCM1_CM_RGAM_RAMA_REGION_12_13_BASE_IDX 2
#define mmCM1_CM_RGAM_RAMA_REGION_14_15 0x0e1f
#define mmCM1_CM_RGAM_RAMA_REGION_14_15_BASE_IDX 2
#define mmCM1_CM_RGAM_RAMA_REGION_16_17 0x0e20
#define mmCM1_CM_RGAM_RAMA_REGION_16_17_BASE_IDX 2
#define mmCM1_CM_RGAM_RAMA_REGION_18_19 0x0e21
#define mmCM1_CM_RGAM_RAMA_REGION_18_19_BASE_IDX 2
#define mmCM1_CM_RGAM_RAMA_REGION_20_21 0x0e22
#define mmCM1_CM_RGAM_RAMA_REGION_20_21_BASE_IDX 2
#define mmCM1_CM_RGAM_RAMA_REGION_22_23 0x0e23
#define mmCM1_CM_RGAM_RAMA_REGION_22_23_BASE_IDX 2
#define mmCM1_CM_RGAM_RAMA_REGION_24_25 0x0e24
#define mmCM1_CM_RGAM_RAMA_REGION_24_25_BASE_IDX 2
#define mmCM1_CM_RGAM_RAMA_REGION_26_27 0x0e25
#define mmCM1_CM_RGAM_RAMA_REGION_26_27_BASE_IDX 2
#define mmCM1_CM_RGAM_RAMA_REGION_28_29 0x0e26
#define mmCM1_CM_RGAM_RAMA_REGION_28_29_BASE_IDX 2
#define mmCM1_CM_RGAM_RAMA_REGION_30_31 0x0e27
#define mmCM1_CM_RGAM_RAMA_REGION_30_31_BASE_IDX 2
#define mmCM1_CM_RGAM_RAMA_REGION_32_33 0x0e28
#define mmCM1_CM_RGAM_RAMA_REGION_32_33_BASE_IDX 2
#define mmCM1_CM_RGAM_RAMB_START_CNTL_B 0x0e29
#define mmCM1_CM_RGAM_RAMB_START_CNTL_B_BASE_IDX 2
#define mmCM1_CM_RGAM_RAMB_START_CNTL_G 0x0e2a
#define mmCM1_CM_RGAM_RAMB_START_CNTL_G_BASE_IDX 2
#define mmCM1_CM_RGAM_RAMB_START_CNTL_R 0x0e2b
#define mmCM1_CM_RGAM_RAMB_START_CNTL_R_BASE_IDX 2
#define mmCM1_CM_RGAM_RAMB_SLOPE_CNTL_B 0x0e2c
#define mmCM1_CM_RGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2
#define mmCM1_CM_RGAM_RAMB_SLOPE_CNTL_G 0x0e2d
#define mmCM1_CM_RGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2
#define mmCM1_CM_RGAM_RAMB_SLOPE_CNTL_R 0x0e2e
#define mmCM1_CM_RGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2
#define mmCM1_CM_RGAM_RAMB_END_CNTL1_B 0x0e2f
#define mmCM1_CM_RGAM_RAMB_END_CNTL1_B_BASE_IDX 2
#define mmCM1_CM_RGAM_RAMB_END_CNTL2_B 0x0e30
#define mmCM1_CM_RGAM_RAMB_END_CNTL2_B_BASE_IDX 2
#define mmCM1_CM_RGAM_RAMB_END_CNTL1_G 0x0e31
#define mmCM1_CM_RGAM_RAMB_END_CNTL1_G_BASE_IDX 2
#define mmCM1_CM_RGAM_RAMB_END_CNTL2_G 0x0e32
#define mmCM1_CM_RGAM_RAMB_END_CNTL2_G_BASE_IDX 2
#define mmCM1_CM_RGAM_RAMB_END_CNTL1_R 0x0e33
#define mmCM1_CM_RGAM_RAMB_END_CNTL1_R_BASE_IDX 2
#define mmCM1_CM_RGAM_RAMB_END_CNTL2_R 0x0e34
#define mmCM1_CM_RGAM_RAMB_END_CNTL2_R_BASE_IDX 2
#define mmCM1_CM_RGAM_RAMB_REGION_0_1 0x0e35
#define mmCM1_CM_RGAM_RAMB_REGION_0_1_BASE_IDX 2
#define mmCM1_CM_RGAM_RAMB_REGION_2_3 0x0e36
#define mmCM1_CM_RGAM_RAMB_REGION_2_3_BASE_IDX 2
#define mmCM1_CM_RGAM_RAMB_REGION_4_5 0x0e37
#define mmCM1_CM_RGAM_RAMB_REGION_4_5_BASE_IDX 2
#define mmCM1_CM_RGAM_RAMB_REGION_6_7 0x0e38
#define mmCM1_CM_RGAM_RAMB_REGION_6_7_BASE_IDX 2
#define mmCM1_CM_RGAM_RAMB_REGION_8_9 0x0e39
#define mmCM1_CM_RGAM_RAMB_REGION_8_9_BASE_IDX 2
#define mmCM1_CM_RGAM_RAMB_REGION_10_11 0x0e3a
#define mmCM1_CM_RGAM_RAMB_REGION_10_11_BASE_IDX 2
#define mmCM1_CM_RGAM_RAMB_REGION_12_13 0x0e3b
#define mmCM1_CM_RGAM_RAMB_REGION_12_13_BASE_IDX 2
#define mmCM1_CM_RGAM_RAMB_REGION_14_15 0x0e3c
#define mmCM1_CM_RGAM_RAMB_REGION_14_15_BASE_IDX 2
#define mmCM1_CM_RGAM_RAMB_REGION_16_17 0x0e3d
#define mmCM1_CM_RGAM_RAMB_REGION_16_17_BASE_IDX 2
#define mmCM1_CM_RGAM_RAMB_REGION_18_19 0x0e3e
#define mmCM1_CM_RGAM_RAMB_REGION_18_19_BASE_IDX 2
#define mmCM1_CM_RGAM_RAMB_REGION_20_21 0x0e3f
#define mmCM1_CM_RGAM_RAMB_REGION_20_21_BASE_IDX 2
#define mmCM1_CM_RGAM_RAMB_REGION_22_23 0x0e40
#define mmCM1_CM_RGAM_RAMB_REGION_22_23_BASE_IDX 2
#define mmCM1_CM_RGAM_RAMB_REGION_24_25 0x0e41
#define mmCM1_CM_RGAM_RAMB_REGION_24_25_BASE_IDX 2
#define mmCM1_CM_RGAM_RAMB_REGION_26_27 0x0e42
#define mmCM1_CM_RGAM_RAMB_REGION_26_27_BASE_IDX 2
#define mmCM1_CM_RGAM_RAMB_REGION_28_29 0x0e43
#define mmCM1_CM_RGAM_RAMB_REGION_28_29_BASE_IDX 2
#define mmCM1_CM_RGAM_RAMB_REGION_30_31 0x0e44
#define mmCM1_CM_RGAM_RAMB_REGION_30_31_BASE_IDX 2
#define mmCM1_CM_RGAM_RAMB_REGION_32_33 0x0e45
#define mmCM1_CM_RGAM_RAMB_REGION_32_33_BASE_IDX 2
#define mmCM1_CM_HDR_MULT_COEF 0x0e46
#define mmCM1_CM_HDR_MULT_COEF_BASE_IDX 2
#define mmCM1_CM_RANGE_CLAMP_CONTROL_R 0x0e47
#define mmCM1_CM_RANGE_CLAMP_CONTROL_R_BASE_IDX 2
#define mmCM1_CM_RANGE_CLAMP_CONTROL_G 0x0e48
#define mmCM1_CM_RANGE_CLAMP_CONTROL_G_BASE_IDX 2
#define mmCM1_CM_RANGE_CLAMP_CONTROL_B 0x0e49
#define mmCM1_CM_RANGE_CLAMP_CONTROL_B_BASE_IDX 2
#define mmCM1_CM_DENORM_CONTROL 0x0e4a
#define mmCM1_CM_DENORM_CONTROL_BASE_IDX 2
#define mmCM1_CM_CMOUT_CONTROL 0x0e4b
#define mmCM1_CM_CMOUT_CONTROL_BASE_IDX 2
#define mmCM1_CM_CMOUT_RANDOM_SEEDS 0x0e4c
#define mmCM1_CM_CMOUT_RANDOM_SEEDS_BASE_IDX 2
#define mmCM1_CM_MEM_PWR_CTRL 0x0e4d
#define mmCM1_CM_MEM_PWR_CTRL_BASE_IDX 2
#define mmCM1_CM_MEM_PWR_STATUS 0x0e4e
#define mmCM1_CM_MEM_PWR_STATUS_BASE_IDX 2
#define mmCM1_CM_TEST_DEBUG_INDEX 0x0e50
#define mmCM1_CM_TEST_DEBUG_INDEX_BASE_IDX 2
#define mmCM1_CM_TEST_DEBUG_DATA 0x0e51
#define mmCM1_CM_TEST_DEBUG_DATA_BASE_IDX 2
// addressBlock: dce_dc_dpp1_dispdec_dpp_dcperfmon_dc_perfmon_dispdec
// base address: 0x399c
#define mmDC_PERFMON13_PERFCOUNTER_CNTL 0x0e67
#define mmDC_PERFMON13_PERFCOUNTER_CNTL_BASE_IDX 2
#define mmDC_PERFMON13_PERFCOUNTER_CNTL2 0x0e68
#define mmDC_PERFMON13_PERFCOUNTER_CNTL2_BASE_IDX 2
#define mmDC_PERFMON13_PERFCOUNTER_STATE 0x0e69
#define mmDC_PERFMON13_PERFCOUNTER_STATE_BASE_IDX 2
#define mmDC_PERFMON13_PERFMON_CNTL 0x0e6a
#define mmDC_PERFMON13_PERFMON_CNTL_BASE_IDX 2
#define mmDC_PERFMON13_PERFMON_CNTL2 0x0e6b
#define mmDC_PERFMON13_PERFMON_CNTL2_BASE_IDX 2
#define mmDC_PERFMON13_PERFMON_CVALUE_INT_MISC 0x0e6c
#define mmDC_PERFMON13_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
#define mmDC_PERFMON13_PERFMON_CVALUE_LOW 0x0e6d
#define mmDC_PERFMON13_PERFMON_CVALUE_LOW_BASE_IDX 2
#define mmDC_PERFMON13_PERFMON_HI 0x0e6e
#define mmDC_PERFMON13_PERFMON_HI_BASE_IDX 2
#define mmDC_PERFMON13_PERFMON_LOW 0x0e6f
#define mmDC_PERFMON13_PERFMON_LOW_BASE_IDX 2
// addressBlock: dce_dc_dpp2_dispdec_dpp_top_dispdec
// base address: 0x8d8
#define mmDPP_TOP2_DPP_CONTROL 0x0e73
#define mmDPP_TOP2_DPP_CONTROL_BASE_IDX 2
#define mmDPP_TOP2_DPP_SOFT_RESET 0x0e74
#define mmDPP_TOP2_DPP_SOFT_RESET_BASE_IDX 2
#define mmDPP_TOP2_DPP_CRC_VAL_R_G 0x0e75
#define mmDPP_TOP2_DPP_CRC_VAL_R_G_BASE_IDX 2
#define mmDPP_TOP2_DPP_CRC_VAL_B_A 0x0e76
#define mmDPP_TOP2_DPP_CRC_VAL_B_A_BASE_IDX 2
#define mmDPP_TOP2_DPP_CRC_CTRL 0x0e77
#define mmDPP_TOP2_DPP_CRC_CTRL_BASE_IDX 2
#define mmDPP_TOP2_HOST_READ_CONTROL 0x0e78
#define mmDPP_TOP2_HOST_READ_CONTROL_BASE_IDX 2
// addressBlock: dce_dc_dpp2_dispdec_cnvc_cfg_dispdec
// base address: 0x8d8
#define mmCNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT 0x0e7d
#define mmCNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX 2
#define mmCNVC_CFG2_FORMAT_CONTROL 0x0e7e
#define mmCNVC_CFG2_FORMAT_CONTROL_BASE_IDX 2
#define mmCNVC_CFG2_FCNV_FP_SCALE_BIAS 0x0e7f
#define mmCNVC_CFG2_FCNV_FP_SCALE_BIAS_BASE_IDX 2
#define mmCNVC_CFG2_DENORM_CONTROL 0x0e80
#define mmCNVC_CFG2_DENORM_CONTROL_BASE_IDX 2
#define mmCNVC_CFG2_COLOR_KEYER_CONTROL 0x0e82
#define mmCNVC_CFG2_COLOR_KEYER_CONTROL_BASE_IDX 2
#define mmCNVC_CFG2_COLOR_KEYER_ALPHA 0x0e83
#define mmCNVC_CFG2_COLOR_KEYER_ALPHA_BASE_IDX 2
#define mmCNVC_CFG2_COLOR_KEYER_RED 0x0e84
#define mmCNVC_CFG2_COLOR_KEYER_RED_BASE_IDX 2
#define mmCNVC_CFG2_COLOR_KEYER_GREEN 0x0e85
#define mmCNVC_CFG2_COLOR_KEYER_GREEN_BASE_IDX 2
#define mmCNVC_CFG2_COLOR_KEYER_BLUE 0x0e86
#define mmCNVC_CFG2_COLOR_KEYER_BLUE_BASE_IDX 2
// addressBlock: dce_dc_dpp2_dispdec_cnvc_cur_dispdec
// base address: 0x8d8
#define mmCNVC_CUR2_CURSOR0_CONTROL 0x0e8e
#define mmCNVC_CUR2_CURSOR0_CONTROL_BASE_IDX 2
#define mmCNVC_CUR2_CURSOR0_COLOR0 0x0e8f
#define mmCNVC_CUR2_CURSOR0_COLOR0_BASE_IDX 2
#define mmCNVC_CUR2_CURSOR0_COLOR1 0x0e90
#define mmCNVC_CUR2_CURSOR0_COLOR1_BASE_IDX 2
#define mmCNVC_CUR2_CURSOR0_FP_SCALE_BIAS 0x0e91
#define mmCNVC_CUR2_CURSOR0_FP_SCALE_BIAS_BASE_IDX 2
// addressBlock: dce_dc_dpp2_dispdec_dscl_dispdec
// base address: 0x8d8
#define mmDSCL2_SCL_COEF_RAM_TAP_SELECT 0x0e98
#define mmDSCL2_SCL_COEF_RAM_TAP_SELECT_BASE_IDX 2
#define mmDSCL2_SCL_COEF_RAM_TAP_DATA 0x0e99
#define mmDSCL2_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2
#define mmDSCL2_SCL_MODE 0x0e9a
#define mmDSCL2_SCL_MODE_BASE_IDX 2
#define mmDSCL2_SCL_TAP_CONTROL 0x0e9b
#define mmDSCL2_SCL_TAP_CONTROL_BASE_IDX 2
#define mmDSCL2_DSCL_CONTROL 0x0e9c
#define mmDSCL2_DSCL_CONTROL_BASE_IDX 2
#define mmDSCL2_DSCL_2TAP_CONTROL 0x0e9d
#define mmDSCL2_DSCL_2TAP_CONTROL_BASE_IDX 2
#define mmDSCL2_SCL_MANUAL_REPLICATE_CONTROL 0x0e9e
#define mmDSCL2_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2
#define mmDSCL2_SCL_HORZ_FILTER_SCALE_RATIO 0x0e9f
#define mmDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2
#define mmDSCL2_SCL_HORZ_FILTER_INIT 0x0ea0
#define mmDSCL2_SCL_HORZ_FILTER_INIT_BASE_IDX 2
#define mmDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C 0x0ea1
#define mmDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2
#define mmDSCL2_SCL_HORZ_FILTER_INIT_C 0x0ea2
#define mmDSCL2_SCL_HORZ_FILTER_INIT_C_BASE_IDX 2
#define mmDSCL2_SCL_VERT_FILTER_SCALE_RATIO 0x0ea3
#define mmDSCL2_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2
#define mmDSCL2_SCL_VERT_FILTER_INIT 0x0ea4
#define mmDSCL2_SCL_VERT_FILTER_INIT_BASE_IDX 2
#define mmDSCL2_SCL_VERT_FILTER_INIT_BOT 0x0ea5
#define mmDSCL2_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2
#define mmDSCL2_SCL_VERT_FILTER_SCALE_RATIO_C 0x0ea6
#define mmDSCL2_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2
#define mmDSCL2_SCL_VERT_FILTER_INIT_C 0x0ea7
#define mmDSCL2_SCL_VERT_FILTER_INIT_C_BASE_IDX 2
#define mmDSCL2_SCL_VERT_FILTER_INIT_BOT_C 0x0ea8
#define mmDSCL2_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX 2
#define mmDSCL2_SCL_BLACK_OFFSET 0x0ea9
#define mmDSCL2_SCL_BLACK_OFFSET_BASE_IDX 2
#define mmDSCL2_DSCL_UPDATE 0x0eaa
#define mmDSCL2_DSCL_UPDATE_BASE_IDX 2
#define mmDSCL2_DSCL_AUTOCAL 0x0eab
#define mmDSCL2_DSCL_AUTOCAL_BASE_IDX 2
#define mmDSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT 0x0eac
#define mmDSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2
#define mmDSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM 0x0ead
#define mmDSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2
#define mmDSCL2_OTG_H_BLANK 0x0eae
#define mmDSCL2_OTG_H_BLANK_BASE_IDX 2
#define mmDSCL2_OTG_V_BLANK 0x0eaf
#define mmDSCL2_OTG_V_BLANK_BASE_IDX 2
#define mmDSCL2_RECOUT_START 0x0eb0
#define mmDSCL2_RECOUT_START_BASE_IDX 2
#define mmDSCL2_RECOUT_SIZE 0x0eb1
#define mmDSCL2_RECOUT_SIZE_BASE_IDX 2
#define mmDSCL2_MPC_SIZE 0x0eb2
#define mmDSCL2_MPC_SIZE_BASE_IDX 2
#define mmDSCL2_LB_DATA_FORMAT 0x0eb3
#define mmDSCL2_LB_DATA_FORMAT_BASE_IDX 2
#define mmDSCL2_LB_MEMORY_CTRL 0x0eb4
#define mmDSCL2_LB_MEMORY_CTRL_BASE_IDX 2
#define mmDSCL2_LB_V_COUNTER 0x0eb5
#define mmDSCL2_LB_V_COUNTER_BASE_IDX 2
#define mmDSCL2_DSCL_MEM_PWR_CTRL 0x0eb6
#define mmDSCL2_DSCL_MEM_PWR_CTRL_BASE_IDX 2
#define mmDSCL2_DSCL_MEM_PWR_STATUS 0x0eb7
#define mmDSCL2_DSCL_MEM_PWR_STATUS_BASE_IDX 2
#define mmDSCL2_OBUF_CONTROL 0x0eb8
#define mmDSCL2_OBUF_CONTROL_BASE_IDX 2
#define mmDSCL2_OBUF_MEM_PWR_CTRL 0x0eb9
#define mmDSCL2_OBUF_MEM_PWR_CTRL_BASE_IDX 2
// addressBlock: dce_dc_dpp2_dispdec_cm_dispdec
// base address: 0x8d8
#define mmCM2_CM_CONTROL 0x0ec8
#define mmCM2_CM_CONTROL_BASE_IDX 2
#define mmCM2_CM_COMA_C11_C12 0x0ec9
#define mmCM2_CM_COMA_C11_C12_BASE_IDX 2
#define mmCM2_CM_COMA_C13_C14 0x0eca
#define mmCM2_CM_COMA_C13_C14_BASE_IDX 2
#define mmCM2_CM_COMA_C21_C22 0x0ecb
#define mmCM2_CM_COMA_C21_C22_BASE_IDX 2
#define mmCM2_CM_COMA_C23_C24 0x0ecc
#define mmCM2_CM_COMA_C23_C24_BASE_IDX 2
#define mmCM2_CM_COMA_C31_C32 0x0ecd
#define mmCM2_CM_COMA_C31_C32_BASE_IDX 2
#define mmCM2_CM_COMA_C33_C34 0x0ece
#define mmCM2_CM_COMA_C33_C34_BASE_IDX 2
#define mmCM2_CM_COMB_C11_C12 0x0ecf
#define mmCM2_CM_COMB_C11_C12_BASE_IDX 2
#define mmCM2_CM_COMB_C13_C14 0x0ed0
#define mmCM2_CM_COMB_C13_C14_BASE_IDX 2
#define mmCM2_CM_COMB_C21_C22 0x0ed1
#define mmCM2_CM_COMB_C21_C22_BASE_IDX 2
#define mmCM2_CM_COMB_C23_C24 0x0ed2
#define mmCM2_CM_COMB_C23_C24_BASE_IDX 2
#define mmCM2_CM_COMB_C31_C32 0x0ed3
#define mmCM2_CM_COMB_C31_C32_BASE_IDX 2
#define mmCM2_CM_COMB_C33_C34 0x0ed4
#define mmCM2_CM_COMB_C33_C34_BASE_IDX 2
#define mmCM2_CM_IGAM_CONTROL 0x0ed5
#define mmCM2_CM_IGAM_CONTROL_BASE_IDX 2
#define mmCM2_CM_IGAM_LUT_RW_CONTROL 0x0ed6
#define mmCM2_CM_IGAM_LUT_RW_CONTROL_BASE_IDX 2
#define mmCM2_CM_IGAM_LUT_RW_INDEX 0x0ed7
#define mmCM2_CM_IGAM_LUT_RW_INDEX_BASE_IDX 2
#define mmCM2_CM_IGAM_LUT_SEQ_COLOR 0x0ed8
#define mmCM2_CM_IGAM_LUT_SEQ_COLOR_BASE_IDX 2
#define mmCM2_CM_IGAM_LUT_30_COLOR 0x0ed9
#define mmCM2_CM_IGAM_LUT_30_COLOR_BASE_IDX 2
#define mmCM2_CM_IGAM_LUT_PWL_DATA 0x0eda
#define mmCM2_CM_IGAM_LUT_PWL_DATA_BASE_IDX 2
#define mmCM2_CM_IGAM_LUT_AUTOFILL 0x0edb
#define mmCM2_CM_IGAM_LUT_AUTOFILL_BASE_IDX 2
#define mmCM2_CM_IGAM_LUT_BW_OFFSET_BLUE 0x0edc
#define mmCM2_CM_IGAM_LUT_BW_OFFSET_BLUE_BASE_IDX 2
#define mmCM2_CM_IGAM_LUT_BW_OFFSET_GREEN 0x0edd
#define mmCM2_CM_IGAM_LUT_BW_OFFSET_GREEN_BASE_IDX 2
#define mmCM2_CM_IGAM_LUT_BW_OFFSET_RED 0x0ede
#define mmCM2_CM_IGAM_LUT_BW_OFFSET_RED_BASE_IDX 2
#define mmCM2_CM_ICSC_CONTROL 0x0edf
#define mmCM2_CM_ICSC_CONTROL_BASE_IDX 2
#define mmCM2_CM_ICSC_C11_C12 0x0ee0
#define mmCM2_CM_ICSC_C11_C12_BASE_IDX 2
#define mmCM2_CM_ICSC_C13_C14 0x0ee1
#define mmCM2_CM_ICSC_C13_C14_BASE_IDX 2
#define mmCM2_CM_ICSC_C21_C22 0x0ee2
#define mmCM2_CM_ICSC_C21_C22_BASE_IDX 2
#define mmCM2_CM_ICSC_C23_C24 0x0ee3
#define mmCM2_CM_ICSC_C23_C24_BASE_IDX 2
#define mmCM2_CM_ICSC_C31_C32 0x0ee4
#define mmCM2_CM_ICSC_C31_C32_BASE_IDX 2
#define mmCM2_CM_ICSC_C33_C34 0x0ee5
#define mmCM2_CM_ICSC_C33_C34_BASE_IDX 2
#define mmCM2_CM_GAMUT_REMAP_CONTROL 0x0ee6
#define mmCM2_CM_GAMUT_REMAP_CONTROL_BASE_IDX 2
#define mmCM2_CM_GAMUT_REMAP_C11_C12 0x0ee7
#define mmCM2_CM_GAMUT_REMAP_C11_C12_BASE_IDX 2
#define mmCM2_CM_GAMUT_REMAP_C13_C14 0x0ee8
#define mmCM2_CM_GAMUT_REMAP_C13_C14_BASE_IDX 2
#define mmCM2_CM_GAMUT_REMAP_C21_C22 0x0ee9
#define mmCM2_CM_GAMUT_REMAP_C21_C22_BASE_IDX 2
#define mmCM2_CM_GAMUT_REMAP_C23_C24 0x0eea
#define mmCM2_CM_GAMUT_REMAP_C23_C24_BASE_IDX 2
#define mmCM2_CM_GAMUT_REMAP_C31_C32 0x0eeb
#define mmCM2_CM_GAMUT_REMAP_C31_C32_BASE_IDX 2
#define mmCM2_CM_GAMUT_REMAP_C33_C34 0x0eec
#define mmCM2_CM_GAMUT_REMAP_C33_C34_BASE_IDX 2
#define mmCM2_CM_OCSC_CONTROL 0x0eed
#define mmCM2_CM_OCSC_CONTROL_BASE_IDX 2
#define mmCM2_CM_OCSC_C11_C12 0x0eee
#define mmCM2_CM_OCSC_C11_C12_BASE_IDX 2
#define mmCM2_CM_OCSC_C13_C14 0x0eef
#define mmCM2_CM_OCSC_C13_C14_BASE_IDX 2
#define mmCM2_CM_OCSC_C21_C22 0x0ef0
#define mmCM2_CM_OCSC_C21_C22_BASE_IDX 2
#define mmCM2_CM_OCSC_C23_C24 0x0ef1
#define mmCM2_CM_OCSC_C23_C24_BASE_IDX 2
#define mmCM2_CM_OCSC_C31_C32 0x0ef2
#define mmCM2_CM_OCSC_C31_C32_BASE_IDX 2
#define mmCM2_CM_OCSC_C33_C34 0x0ef3
#define mmCM2_CM_OCSC_C33_C34_BASE_IDX 2
#define mmCM2_CM_BNS_VALUES_R 0x0ef4
#define mmCM2_CM_BNS_VALUES_R_BASE_IDX 2
#define mmCM2_CM_BNS_VALUES_G 0x0ef5
#define mmCM2_CM_BNS_VALUES_G_BASE_IDX 2
#define mmCM2_CM_BNS_VALUES_B 0x0ef6
#define mmCM2_CM_BNS_VALUES_B_BASE_IDX 2
#define mmCM2_CM_DGAM_CONTROL 0x0ef7
#define mmCM2_CM_DGAM_CONTROL_BASE_IDX 2
#define mmCM2_CM_DGAM_LUT_INDEX 0x0ef8
#define mmCM2_CM_DGAM_LUT_INDEX_BASE_IDX 2
#define mmCM2_CM_DGAM_LUT_DATA 0x0ef9
#define mmCM2_CM_DGAM_LUT_DATA_BASE_IDX 2
#define mmCM2_CM_DGAM_LUT_WRITE_EN_MASK 0x0efa
#define mmCM2_CM_DGAM_LUT_WRITE_EN_MASK_BASE_IDX 2
#define mmCM2_CM_DGAM_RAMA_START_CNTL_B 0x0efb
#define mmCM2_CM_DGAM_RAMA_START_CNTL_B_BASE_IDX 2
#define mmCM2_CM_DGAM_RAMA_START_CNTL_G 0x0efc
#define mmCM2_CM_DGAM_RAMA_START_CNTL_G_BASE_IDX 2
#define mmCM2_CM_DGAM_RAMA_START_CNTL_R 0x0efd
#define mmCM2_CM_DGAM_RAMA_START_CNTL_R_BASE_IDX 2
#define mmCM2_CM_DGAM_RAMA_SLOPE_CNTL_B 0x0efe
#define mmCM2_CM_DGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2
#define mmCM2_CM_DGAM_RAMA_SLOPE_CNTL_G 0x0eff
#define mmCM2_CM_DGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2
#define mmCM2_CM_DGAM_RAMA_SLOPE_CNTL_R 0x0f00
#define mmCM2_CM_DGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2
#define mmCM2_CM_DGAM_RAMA_END_CNTL1_B 0x0f01
#define mmCM2_CM_DGAM_RAMA_END_CNTL1_B_BASE_IDX 2
#define mmCM2_CM_DGAM_RAMA_END_CNTL2_B 0x0f02
#define mmCM2_CM_DGAM_RAMA_END_CNTL2_B_BASE_IDX 2
#define mmCM2_CM_DGAM_RAMA_END_CNTL1_G 0x0f03
#define mmCM2_CM_DGAM_RAMA_END_CNTL1_G_BASE_IDX 2
#define mmCM2_CM_DGAM_RAMA_END_CNTL2_G 0x0f04
#define mmCM2_CM_DGAM_RAMA_END_CNTL2_G_BASE_IDX 2
#define mmCM2_CM_DGAM_RAMA_END_CNTL1_R 0x0f05
#define mmCM2_CM_DGAM_RAMA_END_CNTL1_R_BASE_IDX 2
#define mmCM2_CM_DGAM_RAMA_END_CNTL2_R 0x0f06
#define mmCM2_CM_DGAM_RAMA_END_CNTL2_R_BASE_IDX 2
#define mmCM2_CM_DGAM_RAMA_REGION_0_1 0x0f07
#define mmCM2_CM_DGAM_RAMA_REGION_0_1_BASE_IDX 2
#define mmCM2_CM_DGAM_RAMA_REGION_2_3 0x0f08
#define mmCM2_CM_DGAM_RAMA_REGION_2_3_BASE_IDX 2
#define mmCM2_CM_DGAM_RAMA_REGION_4_5 0x0f09
#define mmCM2_CM_DGAM_RAMA_REGION_4_5_BASE_IDX 2
#define mmCM2_CM_DGAM_RAMA_REGION_6_7 0x0f0a
#define mmCM2_CM_DGAM_RAMA_REGION_6_7_BASE_IDX 2
#define mmCM2_CM_DGAM_RAMA_REGION_8_9 0x0f0b
#define mmCM2_CM_DGAM_RAMA_REGION_8_9_BASE_IDX 2
#define mmCM2_CM_DGAM_RAMA_REGION_10_11 0x0f0c
#define mmCM2_CM_DGAM_RAMA_REGION_10_11_BASE_IDX 2
#define mmCM2_CM_DGAM_RAMA_REGION_12_13 0x0f0d
#define mmCM2_CM_DGAM_RAMA_REGION_12_13_BASE_IDX 2
#define mmCM2_CM_DGAM_RAMA_REGION_14_15 0x0f0e
#define mmCM2_CM_DGAM_RAMA_REGION_14_15_BASE_IDX 2
#define mmCM2_CM_DGAM_RAMB_START_CNTL_B 0x0f0f
#define mmCM2_CM_DGAM_RAMB_START_CNTL_B_BASE_IDX 2
#define mmCM2_CM_DGAM_RAMB_START_CNTL_G 0x0f10
#define mmCM2_CM_DGAM_RAMB_START_CNTL_G_BASE_IDX 2
#define mmCM2_CM_DGAM_RAMB_START_CNTL_R 0x0f11
#define mmCM2_CM_DGAM_RAMB_START_CNTL_R_BASE_IDX 2
#define mmCM2_CM_DGAM_RAMB_SLOPE_CNTL_B 0x0f12
#define mmCM2_CM_DGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2
#define mmCM2_CM_DGAM_RAMB_SLOPE_CNTL_G 0x0f13
#define mmCM2_CM_DGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2
#define mmCM2_CM_DGAM_RAMB_SLOPE_CNTL_R 0x0f14
#define mmCM2_CM_DGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2
#define mmCM2_CM_DGAM_RAMB_END_CNTL1_B 0x0f15
#define mmCM2_CM_DGAM_RAMB_END_CNTL1_B_BASE_IDX 2
#define mmCM2_CM_DGAM_RAMB_END_CNTL2_B 0x0f16
#define mmCM2_CM_DGAM_RAMB_END_CNTL2_B_BASE_IDX 2
#define mmCM2_CM_DGAM_RAMB_END_CNTL1_G 0x0f17
#define mmCM2_CM_DGAM_RAMB_END_CNTL1_G_BASE_IDX 2
#define mmCM2_CM_DGAM_RAMB_END_CNTL2_G 0x0f18
#define mmCM2_CM_DGAM_RAMB_END_CNTL2_G_BASE_IDX 2
#define mmCM2_CM_DGAM_RAMB_END_CNTL1_R 0x0f19
#define mmCM2_CM_DGAM_RAMB_END_CNTL1_R_BASE_IDX 2
#define mmCM2_CM_DGAM_RAMB_END_CNTL2_R 0x0f1a
#define mmCM2_CM_DGAM_RAMB_END_CNTL2_R_BASE_IDX 2
#define mmCM2_CM_DGAM_RAMB_REGION_0_1 0x0f1b
#define mmCM2_CM_DGAM_RAMB_REGION_0_1_BASE_IDX 2
#define mmCM2_CM_DGAM_RAMB_REGION_2_3 0x0f1c
#define mmCM2_CM_DGAM_RAMB_REGION_2_3_BASE_IDX 2
#define mmCM2_CM_DGAM_RAMB_REGION_4_5 0x0f1d
#define mmCM2_CM_DGAM_RAMB_REGION_4_5_BASE_IDX 2
#define mmCM2_CM_DGAM_RAMB_REGION_6_7 0x0f1e
#define mmCM2_CM_DGAM_RAMB_REGION_6_7_BASE_IDX 2
#define mmCM2_CM_DGAM_RAMB_REGION_8_9 0x0f1f
#define mmCM2_CM_DGAM_RAMB_REGION_8_9_BASE_IDX 2
#define mmCM2_CM_DGAM_RAMB_REGION_10_11 0x0f20
#define mmCM2_CM_DGAM_RAMB_REGION_10_11_BASE_IDX 2
#define mmCM2_CM_DGAM_RAMB_REGION_12_13 0x0f21
#define mmCM2_CM_DGAM_RAMB_REGION_12_13_BASE_IDX 2
#define mmCM2_CM_DGAM_RAMB_REGION_14_15 0x0f22
#define mmCM2_CM_DGAM_RAMB_REGION_14_15_BASE_IDX 2
#define mmCM2_CM_RGAM_CONTROL 0x0f23
#define mmCM2_CM_RGAM_CONTROL_BASE_IDX 2
#define mmCM2_CM_RGAM_LUT_INDEX 0x0f24
#define mmCM2_CM_RGAM_LUT_INDEX_BASE_IDX 2
#define mmCM2_CM_RGAM_LUT_DATA 0x0f25
#define mmCM2_CM_RGAM_LUT_DATA_BASE_IDX 2
#define mmCM2_CM_RGAM_LUT_WRITE_EN_MASK 0x0f26
#define mmCM2_CM_RGAM_LUT_WRITE_EN_MASK_BASE_IDX 2
#define mmCM2_CM_RGAM_RAMA_START_CNTL_B 0x0f27
#define mmCM2_CM_RGAM_RAMA_START_CNTL_B_BASE_IDX 2
#define mmCM2_CM_RGAM_RAMA_START_CNTL_G 0x0f28
#define mmCM2_CM_RGAM_RAMA_START_CNTL_G_BASE_IDX 2
#define mmCM2_CM_RGAM_RAMA_START_CNTL_R 0x0f29
#define mmCM2_CM_RGAM_RAMA_START_CNTL_R_BASE_IDX 2
#define mmCM2_CM_RGAM_RAMA_SLOPE_CNTL_B 0x0f2a
#define mmCM2_CM_RGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2
#define mmCM2_CM_RGAM_RAMA_SLOPE_CNTL_G 0x0f2b
#define mmCM2_CM_RGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2
#define mmCM2_CM_RGAM_RAMA_SLOPE_CNTL_R 0x0f2c
#define mmCM2_CM_RGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2
#define mmCM2_CM_RGAM_RAMA_END_CNTL1_B 0x0f2d
#define mmCM2_CM_RGAM_RAMA_END_CNTL1_B_BASE_IDX 2
#define mmCM2_CM_RGAM_RAMA_END_CNTL2_B 0x0f2e
#define mmCM2_CM_RGAM_RAMA_END_CNTL2_B_BASE_IDX 2
#define mmCM2_CM_RGAM_RAMA_END_CNTL1_G 0x0f2f
#define mmCM2_CM_RGAM_RAMA_END_CNTL1_G_BASE_IDX 2
#define mmCM2_CM_RGAM_RAMA_END_CNTL2_G 0x0f30
#define mmCM2_CM_RGAM_RAMA_END_CNTL2_G_BASE_IDX 2
#define mmCM2_CM_RGAM_RAMA_END_CNTL1_R 0x0f31
#define mmCM2_CM_RGAM_RAMA_END_CNTL1_R_BASE_IDX 2
#define mmCM2_CM_RGAM_RAMA_END_CNTL2_R 0x0f32
#define mmCM2_CM_RGAM_RAMA_END_CNTL2_R_BASE_IDX 2
#define mmCM2_CM_RGAM_RAMA_REGION_0_1 0x0f33
#define mmCM2_CM_RGAM_RAMA_REGION_0_1_BASE_IDX 2
#define mmCM2_CM_RGAM_RAMA_REGION_2_3 0x0f34
#define mmCM2_CM_RGAM_RAMA_REGION_2_3_BASE_IDX 2
#define mmCM2_CM_RGAM_RAMA_REGION_4_5 0x0f35
#define mmCM2_CM_RGAM_RAMA_REGION_4_5_BASE_IDX 2
#define mmCM2_CM_RGAM_RAMA_REGION_6_7 0x0f36
#define mmCM2_CM_RGAM_RAMA_REGION_6_7_BASE_IDX 2
#define mmCM2_CM_RGAM_RAMA_REGION_8_9 0x0f37
#define mmCM2_CM_RGAM_RAMA_REGION_8_9_BASE_IDX 2
#define mmCM2_CM_RGAM_RAMA_REGION_10_11 0x0f38
#define mmCM2_CM_RGAM_RAMA_REGION_10_11_BASE_IDX 2
#define mmCM2_CM_RGAM_RAMA_REGION_12_13 0x0f39
#define mmCM2_CM_RGAM_RAMA_REGION_12_13_BASE_IDX 2
#define mmCM2_CM_RGAM_RAMA_REGION_14_15 0x0f3a
#define mmCM2_CM_RGAM_RAMA_REGION_14_15_BASE_IDX 2
#define mmCM2_CM_RGAM_RAMA_REGION_16_17 0x0f3b
#define mmCM2_CM_RGAM_RAMA_REGION_16_17_BASE_IDX 2
#define mmCM2_CM_RGAM_RAMA_REGION_18_19 0x0f3c
#define mmCM2_CM_RGAM_RAMA_REGION_18_19_BASE_IDX 2
#define mmCM2_CM_RGAM_RAMA_REGION_20_21 0x0f3d
#define mmCM2_CM_RGAM_RAMA_REGION_20_21_BASE_IDX 2
#define mmCM2_CM_RGAM_RAMA_REGION_22_23 0x0f3e
#define mmCM2_CM_RGAM_RAMA_REGION_22_23_BASE_IDX 2
#define mmCM2_CM_RGAM_RAMA_REGION_24_25 0x0f3f
#define mmCM2_CM_RGAM_RAMA_REGION_24_25_BASE_IDX 2
#define mmCM2_CM_RGAM_RAMA_REGION_26_27 0x0f40
#define mmCM2_CM_RGAM_RAMA_REGION_26_27_BASE_IDX 2
#define mmCM2_CM_RGAM_RAMA_REGION_28_29 0x0f41
#define mmCM2_CM_RGAM_RAMA_REGION_28_29_BASE_IDX 2
#define mmCM2_CM_RGAM_RAMA_REGION_30_31 0x0f42
#define mmCM2_CM_RGAM_RAMA_REGION_30_31_BASE_IDX 2
#define mmCM2_CM_RGAM_RAMA_REGION_32_33 0x0f43
#define mmCM2_CM_RGAM_RAMA_REGION_32_33_BASE_IDX 2
#define mmCM2_CM_RGAM_RAMB_START_CNTL_B 0x0f44
#define mmCM2_CM_RGAM_RAMB_START_CNTL_B_BASE_IDX 2
#define mmCM2_CM_RGAM_RAMB_START_CNTL_G 0x0f45
#define mmCM2_CM_RGAM_RAMB_START_CNTL_G_BASE_IDX 2
#define mmCM2_CM_RGAM_RAMB_START_CNTL_R 0x0f46
#define mmCM2_CM_RGAM_RAMB_START_CNTL_R_BASE_IDX 2
#define mmCM2_CM_RGAM_RAMB_SLOPE_CNTL_B 0x0f47
#define mmCM2_CM_RGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2
#define mmCM2_CM_RGAM_RAMB_SLOPE_CNTL_G 0x0f48
#define mmCM2_CM_RGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2
#define mmCM2_CM_RGAM_RAMB_SLOPE_CNTL_R 0x0f49
#define mmCM2_CM_RGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2
#define mmCM2_CM_RGAM_RAMB_END_CNTL1_B 0x0f4a
#define mmCM2_CM_RGAM_RAMB_END_CNTL1_B_BASE_IDX 2
#define mmCM2_CM_RGAM_RAMB_END_CNTL2_B 0x0f4b
#define mmCM2_CM_RGAM_RAMB_END_CNTL2_B_BASE_IDX 2
#define mmCM2_CM_RGAM_RAMB_END_CNTL1_G 0x0f4c
#define mmCM2_CM_RGAM_RAMB_END_CNTL1_G_BASE_IDX 2
#define mmCM2_CM_RGAM_RAMB_END_CNTL2_G 0x0f4d
#define mmCM2_CM_RGAM_RAMB_END_CNTL2_G_BASE_IDX 2
#define mmCM2_CM_RGAM_RAMB_END_CNTL1_R 0x0f4e
#define mmCM2_CM_RGAM_RAMB_END_CNTL1_R_BASE_IDX 2
#define mmCM2_CM_RGAM_RAMB_END_CNTL2_R 0x0f4f
#define mmCM2_CM_RGAM_RAMB_END_CNTL2_R_BASE_IDX 2
#define mmCM2_CM_RGAM_RAMB_REGION_0_1 0x0f50
#define mmCM2_CM_RGAM_RAMB_REGION_0_1_BASE_IDX 2
#define mmCM2_CM_RGAM_RAMB_REGION_2_3 0x0f51
#define mmCM2_CM_RGAM_RAMB_REGION_2_3_BASE_IDX 2
#define mmCM2_CM_RGAM_RAMB_REGION_4_5 0x0f52
#define mmCM2_CM_RGAM_RAMB_REGION_4_5_BASE_IDX 2
#define mmCM2_CM_RGAM_RAMB_REGION_6_7 0x0f53
#define mmCM2_CM_RGAM_RAMB_REGION_6_7_BASE_IDX 2
#define mmCM2_CM_RGAM_RAMB_REGION_8_9 0x0f54
#define mmCM2_CM_RGAM_RAMB_REGION_8_9_BASE_IDX 2
#define mmCM2_CM_RGAM_RAMB_REGION_10_11 0x0f55
#define mmCM2_CM_RGAM_RAMB_REGION_10_11_BASE_IDX 2
#define mmCM2_CM_RGAM_RAMB_REGION_12_13 0x0f56
#define mmCM2_CM_RGAM_RAMB_REGION_12_13_BASE_IDX 2
#define mmCM2_CM_RGAM_RAMB_REGION_14_15 0x0f57
#define mmCM2_CM_RGAM_RAMB_REGION_14_15_BASE_IDX 2
#define mmCM2_CM_RGAM_RAMB_REGION_16_17 0x0f58
#define mmCM2_CM_RGAM_RAMB_REGION_16_17_BASE_IDX 2
#define mmCM2_CM_RGAM_RAMB_REGION_18_19 0x0f59
#define mmCM2_CM_RGAM_RAMB_REGION_18_19_BASE_IDX 2
#define mmCM2_CM_RGAM_RAMB_REGION_20_21 0x0f5a
#define mmCM2_CM_RGAM_RAMB_REGION_20_21_BASE_IDX 2
#define mmCM2_CM_RGAM_RAMB_REGION_22_23 0x0f5b
#define mmCM2_CM_RGAM_RAMB_REGION_22_23_BASE_IDX 2
#define mmCM2_CM_RGAM_RAMB_REGION_24_25 0x0f5c
#define mmCM2_CM_RGAM_RAMB_REGION_24_25_BASE_IDX 2
#define mmCM2_CM_RGAM_RAMB_REGION_26_27 0x0f5d
#define mmCM2_CM_RGAM_RAMB_REGION_26_27_BASE_IDX 2
#define mmCM2_CM_RGAM_RAMB_REGION_28_29 0x0f5e
#define mmCM2_CM_RGAM_RAMB_REGION_28_29_BASE_IDX 2
#define mmCM2_CM_RGAM_RAMB_REGION_30_31 0x0f5f
#define mmCM2_CM_RGAM_RAMB_REGION_30_31_BASE_IDX 2
#define mmCM2_CM_RGAM_RAMB_REGION_32_33 0x0f60
#define mmCM2_CM_RGAM_RAMB_REGION_32_33_BASE_IDX 2
#define mmCM2_CM_HDR_MULT_COEF 0x0f61
#define mmCM2_CM_HDR_MULT_COEF_BASE_IDX 2
#define mmCM2_CM_RANGE_CLAMP_CONTROL_R 0x0f62
#define mmCM2_CM_RANGE_CLAMP_CONTROL_R_BASE_IDX 2
#define mmCM2_CM_RANGE_CLAMP_CONTROL_G 0x0f63
#define mmCM2_CM_RANGE_CLAMP_CONTROL_G_BASE_IDX 2
#define mmCM2_CM_RANGE_CLAMP_CONTROL_B 0x0f64
#define mmCM2_CM_RANGE_CLAMP_CONTROL_B_BASE_IDX 2
#define mmCM2_CM_DENORM_CONTROL 0x0f65
#define mmCM2_CM_DENORM_CONTROL_BASE_IDX 2
#define mmCM2_CM_CMOUT_CONTROL 0x0f66
#define mmCM2_CM_CMOUT_CONTROL_BASE_IDX 2
#define mmCM2_CM_CMOUT_RANDOM_SEEDS 0x0f67
#define mmCM2_CM_CMOUT_RANDOM_SEEDS_BASE_IDX 2
#define mmCM2_CM_MEM_PWR_CTRL 0x0f68
#define mmCM2_CM_MEM_PWR_CTRL_BASE_IDX 2
#define mmCM2_CM_MEM_PWR_STATUS 0x0f69
#define mmCM2_CM_MEM_PWR_STATUS_BASE_IDX 2
#define mmCM2_CM_TEST_DEBUG_INDEX 0x0f6b
#define mmCM2_CM_TEST_DEBUG_INDEX_BASE_IDX 2
#define mmCM2_CM_TEST_DEBUG_DATA 0x0f6c
#define mmCM2_CM_TEST_DEBUG_DATA_BASE_IDX 2
// addressBlock: dce_dc_dpp2_dispdec_dpp_dcperfmon_dc_perfmon_dispdec
// base address: 0x3e08
#define mmDC_PERFMON14_PERFCOUNTER_CNTL 0x0f82
#define mmDC_PERFMON14_PERFCOUNTER_CNTL_BASE_IDX 2
#define mmDC_PERFMON14_PERFCOUNTER_CNTL2 0x0f83
#define mmDC_PERFMON14_PERFCOUNTER_CNTL2_BASE_IDX 2
#define mmDC_PERFMON14_PERFCOUNTER_STATE 0x0f84
#define mmDC_PERFMON14_PERFCOUNTER_STATE_BASE_IDX 2
#define mmDC_PERFMON14_PERFMON_CNTL 0x0f85
#define mmDC_PERFMON14_PERFMON_CNTL_BASE_IDX 2
#define mmDC_PERFMON14_PERFMON_CNTL2 0x0f86
#define mmDC_PERFMON14_PERFMON_CNTL2_BASE_IDX 2
#define mmDC_PERFMON14_PERFMON_CVALUE_INT_MISC 0x0f87
#define mmDC_PERFMON14_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
#define mmDC_PERFMON14_PERFMON_CVALUE_LOW 0x0f88
#define mmDC_PERFMON14_PERFMON_CVALUE_LOW_BASE_IDX 2
#define mmDC_PERFMON14_PERFMON_HI 0x0f89
#define mmDC_PERFMON14_PERFMON_HI_BASE_IDX 2
#define mmDC_PERFMON14_PERFMON_LOW 0x0f8a
#define mmDC_PERFMON14_PERFMON_LOW_BASE_IDX 2
// addressBlock: dce_dc_dpp3_dispdec_dpp_top_dispdec
// base address: 0xd44
#define mmDPP_TOP3_DPP_CONTROL 0x0f8e
#define mmDPP_TOP3_DPP_CONTROL_BASE_IDX 2
#define mmDPP_TOP3_DPP_SOFT_RESET 0x0f8f
#define mmDPP_TOP3_DPP_SOFT_RESET_BASE_IDX 2
#define mmDPP_TOP3_DPP_CRC_VAL_R_G 0x0f90
#define mmDPP_TOP3_DPP_CRC_VAL_R_G_BASE_IDX 2
#define mmDPP_TOP3_DPP_CRC_VAL_B_A 0x0f91
#define mmDPP_TOP3_DPP_CRC_VAL_B_A_BASE_IDX 2
#define mmDPP_TOP3_DPP_CRC_CTRL 0x0f92
#define mmDPP_TOP3_DPP_CRC_CTRL_BASE_IDX 2
#define mmDPP_TOP3_HOST_READ_CONTROL 0x0f93
#define mmDPP_TOP3_HOST_READ_CONTROL_BASE_IDX 2
// addressBlock: dce_dc_dpp3_dispdec_cnvc_cfg_dispdec
// base address: 0xd44
#define mmCNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT 0x0f98
#define mmCNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX 2
#define mmCNVC_CFG3_FORMAT_CONTROL 0x0f99
#define mmCNVC_CFG3_FORMAT_CONTROL_BASE_IDX 2
#define mmCNVC_CFG3_FCNV_FP_SCALE_BIAS 0x0f9a
#define mmCNVC_CFG3_FCNV_FP_SCALE_BIAS_BASE_IDX 2
#define mmCNVC_CFG3_DENORM_CONTROL 0x0f9b
#define mmCNVC_CFG3_DENORM_CONTROL_BASE_IDX 2
#define mmCNVC_CFG3_COLOR_KEYER_CONTROL 0x0f9d
#define mmCNVC_CFG3_COLOR_KEYER_CONTROL_BASE_IDX 2
#define mmCNVC_CFG3_COLOR_KEYER_ALPHA 0x0f9e
#define mmCNVC_CFG3_COLOR_KEYER_ALPHA_BASE_IDX 2
#define mmCNVC_CFG3_COLOR_KEYER_RED 0x0f9f
#define mmCNVC_CFG3_COLOR_KEYER_RED_BASE_IDX 2
#define mmCNVC_CFG3_COLOR_KEYER_GREEN 0x0fa0
#define mmCNVC_CFG3_COLOR_KEYER_GREEN_BASE_IDX 2
#define mmCNVC_CFG3_COLOR_KEYER_BLUE 0x0fa1
#define mmCNVC_CFG3_COLOR_KEYER_BLUE_BASE_IDX 2
// addressBlock: dce_dc_dpp3_dispdec_cnvc_cur_dispdec
// base address: 0xd44
#define mmCNVC_CUR3_CURSOR0_CONTROL 0x0fa9
#define mmCNVC_CUR3_CURSOR0_CONTROL_BASE_IDX 2
#define mmCNVC_CUR3_CURSOR0_COLOR0 0x0faa
#define mmCNVC_CUR3_CURSOR0_COLOR0_BASE_IDX 2
#define mmCNVC_CUR3_CURSOR0_COLOR1 0x0fab
#define mmCNVC_CUR3_CURSOR0_COLOR1_BASE_IDX 2
#define mmCNVC_CUR3_CURSOR0_FP_SCALE_BIAS 0x0fac
#define mmCNVC_CUR3_CURSOR0_FP_SCALE_BIAS_BASE_IDX 2
// addressBlock: dce_dc_dpp3_dispdec_dscl_dispdec
// base address: 0xd44
#define mmDSCL3_SCL_COEF_RAM_TAP_SELECT 0x0fb3
#define mmDSCL3_SCL_COEF_RAM_TAP_SELECT_BASE_IDX 2
#define mmDSCL3_SCL_COEF_RAM_TAP_DATA 0x0fb4
#define mmDSCL3_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2
#define mmDSCL3_SCL_MODE 0x0fb5
#define mmDSCL3_SCL_MODE_BASE_IDX 2
#define mmDSCL3_SCL_TAP_CONTROL 0x0fb6
#define mmDSCL3_SCL_TAP_CONTROL_BASE_IDX 2
#define mmDSCL3_DSCL_CONTROL 0x0fb7
#define mmDSCL3_DSCL_CONTROL_BASE_IDX 2
#define mmDSCL3_DSCL_2TAP_CONTROL 0x0fb8
#define mmDSCL3_DSCL_2TAP_CONTROL_BASE_IDX 2
#define mmDSCL3_SCL_MANUAL_REPLICATE_CONTROL 0x0fb9
#define mmDSCL3_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2
#define mmDSCL3_SCL_HORZ_FILTER_SCALE_RATIO 0x0fba
#define mmDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2
#define mmDSCL3_SCL_HORZ_FILTER_INIT 0x0fbb
#define mmDSCL3_SCL_HORZ_FILTER_INIT_BASE_IDX 2
#define mmDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C 0x0fbc
#define mmDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2
#define mmDSCL3_SCL_HORZ_FILTER_INIT_C 0x0fbd
#define mmDSCL3_SCL_HORZ_FILTER_INIT_C_BASE_IDX 2
#define mmDSCL3_SCL_VERT_FILTER_SCALE_RATIO 0x0fbe
#define mmDSCL3_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2
#define mmDSCL3_SCL_VERT_FILTER_INIT 0x0fbf
#define mmDSCL3_SCL_VERT_FILTER_INIT_BASE_IDX 2
#define mmDSCL3_SCL_VERT_FILTER_INIT_BOT 0x0fc0
#define mmDSCL3_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2
#define mmDSCL3_SCL_VERT_FILTER_SCALE_RATIO_C 0x0fc1
#define mmDSCL3_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2
#define mmDSCL3_SCL_VERT_FILTER_INIT_C 0x0fc2
#define mmDSCL3_SCL_VERT_FILTER_INIT_C_BASE_IDX 2
#define mmDSCL3_SCL_VERT_FILTER_INIT_BOT_C 0x0fc3
#define mmDSCL3_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX 2
#define mmDSCL3_SCL_BLACK_OFFSET 0x0fc4
#define mmDSCL3_SCL_BLACK_OFFSET_BASE_IDX 2
#define mmDSCL3_DSCL_UPDATE 0x0fc5
#define mmDSCL3_DSCL_UPDATE_BASE_IDX 2
#define mmDSCL3_DSCL_AUTOCAL 0x0fc6
#define mmDSCL3_DSCL_AUTOCAL_BASE_IDX 2
#define mmDSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT 0x0fc7
#define mmDSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2
#define mmDSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM 0x0fc8
#define mmDSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2
#define mmDSCL3_OTG_H_BLANK 0x0fc9
#define mmDSCL3_OTG_H_BLANK_BASE_IDX 2
#define mmDSCL3_OTG_V_BLANK 0x0fca
#define mmDSCL3_OTG_V_BLANK_BASE_IDX 2
#define mmDSCL3_RECOUT_START 0x0fcb
#define mmDSCL3_RECOUT_START_BASE_IDX 2
#define mmDSCL3_RECOUT_SIZE 0x0fcc
#define mmDSCL3_RECOUT_SIZE_BASE_IDX 2
#define mmDSCL3_MPC_SIZE 0x0fcd
#define mmDSCL3_MPC_SIZE_BASE_IDX 2
#define mmDSCL3_LB_DATA_FORMAT 0x0fce
#define mmDSCL3_LB_DATA_FORMAT_BASE_IDX 2
#define mmDSCL3_LB_MEMORY_CTRL 0x0fcf
#define mmDSCL3_LB_MEMORY_CTRL_BASE_IDX 2
#define mmDSCL3_LB_V_COUNTER 0x0fd0
#define mmDSCL3_LB_V_COUNTER_BASE_IDX 2
#define mmDSCL3_DSCL_MEM_PWR_CTRL 0x0fd1
#define mmDSCL3_DSCL_MEM_PWR_CTRL_BASE_IDX 2
#define mmDSCL3_DSCL_MEM_PWR_STATUS 0x0fd2
#define mmDSCL3_DSCL_MEM_PWR_STATUS_BASE_IDX 2
#define mmDSCL3_OBUF_CONTROL 0x0fd3
#define mmDSCL3_OBUF_CONTROL_BASE_IDX 2
#define mmDSCL3_OBUF_MEM_PWR_CTRL 0x0fd4
#define mmDSCL3_OBUF_MEM_PWR_CTRL_BASE_IDX 2
// addressBlock: dce_dc_dpp3_dispdec_cm_dispdec
// base address: 0xd44
#define mmCM3_CM_CONTROL 0x0fe3
#define mmCM3_CM_CONTROL_BASE_IDX 2
#define mmCM3_CM_COMA_C11_C12 0x0fe4
#define mmCM3_CM_COMA_C11_C12_BASE_IDX 2
#define mmCM3_CM_COMA_C13_C14 0x0fe5
#define mmCM3_CM_COMA_C13_C14_BASE_IDX 2
#define mmCM3_CM_COMA_C21_C22 0x0fe6
#define mmCM3_CM_COMA_C21_C22_BASE_IDX 2
#define mmCM3_CM_COMA_C23_C24 0x0fe7
#define mmCM3_CM_COMA_C23_C24_BASE_IDX 2
#define mmCM3_CM_COMA_C31_C32 0x0fe8
#define mmCM3_CM_COMA_C31_C32_BASE_IDX 2
#define mmCM3_CM_COMA_C33_C34 0x0fe9
#define mmCM3_CM_COMA_C33_C34_BASE_IDX 2
#define mmCM3_CM_COMB_C11_C12 0x0fea
#define mmCM3_CM_COMB_C11_C12_BASE_IDX 2
#define mmCM3_CM_COMB_C13_C14 0x0feb
#define mmCM3_CM_COMB_C13_C14_BASE_IDX 2
#define mmCM3_CM_COMB_C21_C22 0x0fec
#define mmCM3_CM_COMB_C21_C22_BASE_IDX 2
#define mmCM3_CM_COMB_C23_C24 0x0fed
#define mmCM3_CM_COMB_C23_C24_BASE_IDX 2
#define mmCM3_CM_COMB_C31_C32 0x0fee
#define mmCM3_CM_COMB_C31_C32_BASE_IDX 2
#define mmCM3_CM_COMB_C33_C34 0x0fef
#define mmCM3_CM_COMB_C33_C34_BASE_IDX 2
#define mmCM3_CM_IGAM_CONTROL 0x0ff0
#define mmCM3_CM_IGAM_CONTROL_BASE_IDX 2
#define mmCM3_CM_IGAM_LUT_RW_CONTROL 0x0ff1
#define mmCM3_CM_IGAM_LUT_RW_CONTROL_BASE_IDX 2
#define mmCM3_CM_IGAM_LUT_RW_INDEX 0x0ff2
#define mmCM3_CM_IGAM_LUT_RW_INDEX_BASE_IDX 2
#define mmCM3_CM_IGAM_LUT_SEQ_COLOR 0x0ff3
#define mmCM3_CM_IGAM_LUT_SEQ_COLOR_BASE_IDX 2
#define mmCM3_CM_IGAM_LUT_30_COLOR 0x0ff4
#define mmCM3_CM_IGAM_LUT_30_COLOR_BASE_IDX 2
#define mmCM3_CM_IGAM_LUT_PWL_DATA 0x0ff5
#define mmCM3_CM_IGAM_LUT_PWL_DATA_BASE_IDX 2
#define mmCM3_CM_IGAM_LUT_AUTOFILL 0x0ff6
#define mmCM3_CM_IGAM_LUT_AUTOFILL_BASE_IDX 2
#define mmCM3_CM_IGAM_LUT_BW_OFFSET_BLUE 0x0ff7
#define mmCM3_CM_IGAM_LUT_BW_OFFSET_BLUE_BASE_IDX 2
#define mmCM3_CM_IGAM_LUT_BW_OFFSET_GREEN 0x0ff8
#define mmCM3_CM_IGAM_LUT_BW_OFFSET_GREEN_BASE_IDX 2
#define mmCM3_CM_IGAM_LUT_BW_OFFSET_RED 0x0ff9
#define mmCM3_CM_IGAM_LUT_BW_OFFSET_RED_BASE_IDX 2
#define mmCM3_CM_ICSC_CONTROL 0x0ffa
#define mmCM3_CM_ICSC_CONTROL_BASE_IDX 2
#define mmCM3_CM_ICSC_C11_C12 0x0ffb
#define mmCM3_CM_ICSC_C11_C12_BASE_IDX 2
#define mmCM3_CM_ICSC_C13_C14 0x0ffc
#define mmCM3_CM_ICSC_C13_C14_BASE_IDX 2
#define mmCM3_CM_ICSC_C21_C22 0x0ffd
#define mmCM3_CM_ICSC_C21_C22_BASE_IDX 2
#define mmCM3_CM_ICSC_C23_C24 0x0ffe
#define mmCM3_CM_ICSC_C23_C24_BASE_IDX 2
#define mmCM3_CM_ICSC_C31_C32 0x0fff
#define mmCM3_CM_ICSC_C31_C32_BASE_IDX 2
#define mmCM3_CM_ICSC_C33_C34 0x1000
#define mmCM3_CM_ICSC_C33_C34_BASE_IDX 2
#define mmCM3_CM_GAMUT_REMAP_CONTROL 0x1001
#define mmCM3_CM_GAMUT_REMAP_CONTROL_BASE_IDX 2
#define mmCM3_CM_GAMUT_REMAP_C11_C12 0x1002
#define mmCM3_CM_GAMUT_REMAP_C11_C12_BASE_IDX 2
#define mmCM3_CM_GAMUT_REMAP_C13_C14 0x1003
#define mmCM3_CM_GAMUT_REMAP_C13_C14_BASE_IDX 2
#define mmCM3_CM_GAMUT_REMAP_C21_C22 0x1004
#define mmCM3_CM_GAMUT_REMAP_C21_C22_BASE_IDX 2
#define mmCM3_CM_GAMUT_REMAP_C23_C24 0x1005
#define mmCM3_CM_GAMUT_REMAP_C23_C24_BASE_IDX 2
#define mmCM3_CM_GAMUT_REMAP_C31_C32 0x1006
#define mmCM3_CM_GAMUT_REMAP_C31_C32_BASE_IDX 2
#define mmCM3_CM_GAMUT_REMAP_C33_C34 0x1007
#define mmCM3_CM_GAMUT_REMAP_C33_C34_BASE_IDX 2
#define mmCM3_CM_OCSC_CONTROL 0x1008
#define mmCM3_CM_OCSC_CONTROL_BASE_IDX 2
#define mmCM3_CM_OCSC_C11_C12 0x1009
#define mmCM3_CM_OCSC_C11_C12_BASE_IDX 2
#define mmCM3_CM_OCSC_C13_C14 0x100a
#define mmCM3_CM_OCSC_C13_C14_BASE_IDX 2
#define mmCM3_CM_OCSC_C21_C22 0x100b
#define mmCM3_CM_OCSC_C21_C22_BASE_IDX 2
#define mmCM3_CM_OCSC_C23_C24 0x100c
#define mmCM3_CM_OCSC_C23_C24_BASE_IDX 2
#define mmCM3_CM_OCSC_C31_C32 0x100d
#define mmCM3_CM_OCSC_C31_C32_BASE_IDX 2
#define mmCM3_CM_OCSC_C33_C34 0x100e
#define mmCM3_CM_OCSC_C33_C34_BASE_IDX 2
#define mmCM3_CM_BNS_VALUES_R 0x100f
#define mmCM3_CM_BNS_VALUES_R_BASE_IDX 2
#define mmCM3_CM_BNS_VALUES_G 0x1010
#define mmCM3_CM_BNS_VALUES_G_BASE_IDX 2
#define mmCM3_CM_BNS_VALUES_B 0x1011
#define mmCM3_CM_BNS_VALUES_B_BASE_IDX 2
#define mmCM3_CM_DGAM_CONTROL 0x1012
#define mmCM3_CM_DGAM_CONTROL_BASE_IDX 2
#define mmCM3_CM_DGAM_LUT_INDEX 0x1013
#define mmCM3_CM_DGAM_LUT_INDEX_BASE_IDX 2
#define mmCM3_CM_DGAM_LUT_DATA 0x1014
#define mmCM3_CM_DGAM_LUT_DATA_BASE_IDX 2
#define mmCM3_CM_DGAM_LUT_WRITE_EN_MASK 0x1015
#define mmCM3_CM_DGAM_LUT_WRITE_EN_MASK_BASE_IDX 2
#define mmCM3_CM_DGAM_RAMA_START_CNTL_B 0x1016
#define mmCM3_CM_DGAM_RAMA_START_CNTL_B_BASE_IDX 2
#define mmCM3_CM_DGAM_RAMA_START_CNTL_G 0x1017
#define mmCM3_CM_DGAM_RAMA_START_CNTL_G_BASE_IDX 2
#define mmCM3_CM_DGAM_RAMA_START_CNTL_R 0x1018
#define mmCM3_CM_DGAM_RAMA_START_CNTL_R_BASE_IDX 2
#define mmCM3_CM_DGAM_RAMA_SLOPE_CNTL_B 0x1019
#define mmCM3_CM_DGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2
#define mmCM3_CM_DGAM_RAMA_SLOPE_CNTL_G 0x101a
#define mmCM3_CM_DGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2
#define mmCM3_CM_DGAM_RAMA_SLOPE_CNTL_R 0x101b
#define mmCM3_CM_DGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2
#define mmCM3_CM_DGAM_RAMA_END_CNTL1_B 0x101c
#define mmCM3_CM_DGAM_RAMA_END_CNTL1_B_BASE_IDX 2
#define mmCM3_CM_DGAM_RAMA_END_CNTL2_B 0x101d
#define mmCM3_CM_DGAM_RAMA_END_CNTL2_B_BASE_IDX 2
#define mmCM3_CM_DGAM_RAMA_END_CNTL1_G 0x101e
#define mmCM3_CM_DGAM_RAMA_END_CNTL1_G_BASE_IDX 2
#define mmCM3_CM_DGAM_RAMA_END_CNTL2_G 0x101f
#define mmCM3_CM_DGAM_RAMA_END_CNTL2_G_BASE_IDX 2
#define mmCM3_CM_DGAM_RAMA_END_CNTL1_R 0x1020
#define mmCM3_CM_DGAM_RAMA_END_CNTL1_R_BASE_IDX 2
#define mmCM3_CM_DGAM_RAMA_END_CNTL2_R 0x1021
#define mmCM3_CM_DGAM_RAMA_END_CNTL2_R_BASE_IDX 2
#define mmCM3_CM_DGAM_RAMA_REGION_0_1 0x1022
#define mmCM3_CM_DGAM_RAMA_REGION_0_1_BASE_IDX 2
#define mmCM3_CM_DGAM_RAMA_REGION_2_3 0x1023
#define mmCM3_CM_DGAM_RAMA_REGION_2_3_BASE_IDX 2
#define mmCM3_CM_DGAM_RAMA_REGION_4_5 0x1024
#define mmCM3_CM_DGAM_RAMA_REGION_4_5_BASE_IDX 2
#define mmCM3_CM_DGAM_RAMA_REGION_6_7 0x1025
#define mmCM3_CM_DGAM_RAMA_REGION_6_7_BASE_IDX 2
#define mmCM3_CM_DGAM_RAMA_REGION_8_9 0x1026
#define mmCM3_CM_DGAM_RAMA_REGION_8_9_BASE_IDX 2
#define mmCM3_CM_DGAM_RAMA_REGION_10_11 0x1027
#define mmCM3_CM_DGAM_RAMA_REGION_10_11_BASE_IDX 2
#define mmCM3_CM_DGAM_RAMA_REGION_12_13 0x1028
#define mmCM3_CM_DGAM_RAMA_REGION_12_13_BASE_IDX 2
#define mmCM3_CM_DGAM_RAMA_REGION_14_15 0x1029
#define mmCM3_CM_DGAM_RAMA_REGION_14_15_BASE_IDX 2
#define mmCM3_CM_DGAM_RAMB_START_CNTL_B 0x102a
#define mmCM3_CM_DGAM_RAMB_START_CNTL_B_BASE_IDX 2
#define mmCM3_CM_DGAM_RAMB_START_CNTL_G 0x102b
#define mmCM3_CM_DGAM_RAMB_START_CNTL_G_BASE_IDX 2
#define mmCM3_CM_DGAM_RAMB_START_CNTL_R 0x102c
#define mmCM3_CM_DGAM_RAMB_START_CNTL_R_BASE_IDX 2
#define mmCM3_CM_DGAM_RAMB_SLOPE_CNTL_B 0x102d
#define mmCM3_CM_DGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2
#define mmCM3_CM_DGAM_RAMB_SLOPE_CNTL_G 0x102e
#define mmCM3_CM_DGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2
#define mmCM3_CM_DGAM_RAMB_SLOPE_CNTL_R 0x102f
#define mmCM3_CM_DGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2
#define mmCM3_CM_DGAM_RAMB_END_CNTL1_B 0x1030
#define mmCM3_CM_DGAM_RAMB_END_CNTL1_B_BASE_IDX 2
#define mmCM3_CM_DGAM_RAMB_END_CNTL2_B 0x1031
#define mmCM3_CM_DGAM_RAMB_END_CNTL2_B_BASE_IDX 2
#define mmCM3_CM_DGAM_RAMB_END_CNTL1_G 0x1032
#define mmCM3_CM_DGAM_RAMB_END_CNTL1_G_BASE_IDX 2
#define mmCM3_CM_DGAM_RAMB_END_CNTL2_G 0x1033
#define mmCM3_CM_DGAM_RAMB_END_CNTL2_G_BASE_IDX 2
#define mmCM3_CM_DGAM_RAMB_END_CNTL1_R 0x1034
#define mmCM3_CM_DGAM_RAMB_END_CNTL1_R_BASE_IDX 2
#define mmCM3_CM_DGAM_RAMB_END_CNTL2_R 0x1035
#define mmCM3_CM_DGAM_RAMB_END_CNTL2_R_BASE_IDX 2
#define mmCM3_CM_DGAM_RAMB_REGION_0_1 0x1036
#define mmCM3_CM_DGAM_RAMB_REGION_0_1_BASE_IDX 2
#define mmCM3_CM_DGAM_RAMB_REGION_2_3 0x1037
#define mmCM3_CM_DGAM_RAMB_REGION_2_3_BASE_IDX 2
#define mmCM3_CM_DGAM_RAMB_REGION_4_5 0x1038
#define mmCM3_CM_DGAM_RAMB_REGION_4_5_BASE_IDX 2
#define mmCM3_CM_DGAM_RAMB_REGION_6_7 0x1039
#define mmCM3_CM_DGAM_RAMB_REGION_6_7_BASE_IDX 2
#define mmCM3_CM_DGAM_RAMB_REGION_8_9 0x103a
#define mmCM3_CM_DGAM_RAMB_REGION_8_9_BASE_IDX 2
#define mmCM3_CM_DGAM_RAMB_REGION_10_11 0x103b
#define mmCM3_CM_DGAM_RAMB_REGION_10_11_BASE_IDX 2
#define mmCM3_CM_DGAM_RAMB_REGION_12_13 0x103c
#define mmCM3_CM_DGAM_RAMB_REGION_12_13_BASE_IDX 2
#define mmCM3_CM_DGAM_RAMB_REGION_14_15 0x103d
#define mmCM3_CM_DGAM_RAMB_REGION_14_15_BASE_IDX 2
#define mmCM3_CM_RGAM_CONTROL 0x103e
#define mmCM3_CM_RGAM_CONTROL_BASE_IDX 2
#define mmCM3_CM_RGAM_LUT_INDEX 0x103f
#define mmCM3_CM_RGAM_LUT_INDEX_BASE_IDX 2
#define mmCM3_CM_RGAM_LUT_DATA 0x1040
#define mmCM3_CM_RGAM_LUT_DATA_BASE_IDX 2
#define mmCM3_CM_RGAM_LUT_WRITE_EN_MASK 0x1041
#define mmCM3_CM_RGAM_LUT_WRITE_EN_MASK_BASE_IDX 2
#define mmCM3_CM_RGAM_RAMA_START_CNTL_B 0x1042
#define mmCM3_CM_RGAM_RAMA_START_CNTL_B_BASE_IDX 2
#define mmCM3_CM_RGAM_RAMA_START_CNTL_G 0x1043
#define mmCM3_CM_RGAM_RAMA_START_CNTL_G_BASE_IDX 2
#define mmCM3_CM_RGAM_RAMA_START_CNTL_R 0x1044
#define mmCM3_CM_RGAM_RAMA_START_CNTL_R_BASE_IDX 2
#define mmCM3_CM_RGAM_RAMA_SLOPE_CNTL_B 0x1045
#define mmCM3_CM_RGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2
#define mmCM3_CM_RGAM_RAMA_SLOPE_CNTL_G 0x1046
#define mmCM3_CM_RGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2
#define mmCM3_CM_RGAM_RAMA_SLOPE_CNTL_R 0x1047
#define mmCM3_CM_RGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2
#define mmCM3_CM_RGAM_RAMA_END_CNTL1_B 0x1048
#define mmCM3_CM_RGAM_RAMA_END_CNTL1_B_BASE_IDX 2
#define mmCM3_CM_RGAM_RAMA_END_CNTL2_B 0x1049
#define mmCM3_CM_RGAM_RAMA_END_CNTL2_B_BASE_IDX 2
#define mmCM3_CM_RGAM_RAMA_END_CNTL1_G 0x104a
#define mmCM3_CM_RGAM_RAMA_END_CNTL1_G_BASE_IDX 2
#define mmCM3_CM_RGAM_RAMA_END_CNTL2_G 0x104b
#define mmCM3_CM_RGAM_RAMA_END_CNTL2_G_BASE_IDX 2
#define mmCM3_CM_RGAM_RAMA_END_CNTL1_R 0x104c
#define mmCM3_CM_RGAM_RAMA_END_CNTL1_R_BASE_IDX 2
#define mmCM3_CM_RGAM_RAMA_END_CNTL2_R 0x104d
#define mmCM3_CM_RGAM_RAMA_END_CNTL2_R_BASE_IDX 2
#define mmCM3_CM_RGAM_RAMA_REGION_0_1 0x104e
#define mmCM3_CM_RGAM_RAMA_REGION_0_1_BASE_IDX 2
#define mmCM3_CM_RGAM_RAMA_REGION_2_3 0x104f
#define mmCM3_CM_RGAM_RAMA_REGION_2_3_BASE_IDX 2
#define mmCM3_CM_RGAM_RAMA_REGION_4_5 0x1050
#define mmCM3_CM_RGAM_RAMA_REGION_4_5_BASE_IDX 2
#define mmCM3_CM_RGAM_RAMA_REGION_6_7 0x1051
#define mmCM3_CM_RGAM_RAMA_REGION_6_7_BASE_IDX 2
#define mmCM3_CM_RGAM_RAMA_REGION_8_9 0x1052
#define mmCM3_CM_RGAM_RAMA_REGION_8_9_BASE_IDX 2
#define mmCM3_CM_RGAM_RAMA_REGION_10_11 0x1053
#define mmCM3_CM_RGAM_RAMA_REGION_10_11_BASE_IDX 2
#define mmCM3_CM_RGAM_RAMA_REGION_12_13 0x1054
#define mmCM3_CM_RGAM_RAMA_REGION_12_13_BASE_IDX 2
#define mmCM3_CM_RGAM_RAMA_REGION_14_15 0x1055
#define mmCM3_CM_RGAM_RAMA_REGION_14_15_BASE_IDX 2
#define mmCM3_CM_RGAM_RAMA_REGION_16_17 0x1056
#define mmCM3_CM_RGAM_RAMA_REGION_16_17_BASE_IDX 2
#define mmCM3_CM_RGAM_RAMA_REGION_18_19 0x1057
#define mmCM3_CM_RGAM_RAMA_REGION_18_19_BASE_IDX 2
#define mmCM3_CM_RGAM_RAMA_REGION_20_21 0x1058
#define mmCM3_CM_RGAM_RAMA_REGION_20_21_BASE_IDX 2
#define mmCM3_CM_RGAM_RAMA_REGION_22_23 0x1059
#define mmCM3_CM_RGAM_RAMA_REGION_22_23_BASE_IDX 2
#define mmCM3_CM_RGAM_RAMA_REGION_24_25 0x105a
#define mmCM3_CM_RGAM_RAMA_REGION_24_25_BASE_IDX 2
#define mmCM3_CM_RGAM_RAMA_REGION_26_27 0x105b
#define mmCM3_CM_RGAM_RAMA_REGION_26_27_BASE_IDX 2
#define mmCM3_CM_RGAM_RAMA_REGION_28_29 0x105c
#define mmCM3_CM_RGAM_RAMA_REGION_28_29_BASE_IDX 2
#define mmCM3_CM_RGAM_RAMA_REGION_30_31 0x105d
#define mmCM3_CM_RGAM_RAMA_REGION_30_31_BASE_IDX 2
#define mmCM3_CM_RGAM_RAMA_REGION_32_33 0x105e
#define mmCM3_CM_RGAM_RAMA_REGION_32_33_BASE_IDX 2
#define mmCM3_CM_RGAM_RAMB_START_CNTL_B 0x105f
#define mmCM3_CM_RGAM_RAMB_START_CNTL_B_BASE_IDX 2
#define mmCM3_CM_RGAM_RAMB_START_CNTL_G 0x1060
#define mmCM3_CM_RGAM_RAMB_START_CNTL_G_BASE_IDX 2
#define mmCM3_CM_RGAM_RAMB_START_CNTL_R 0x1061
#define mmCM3_CM_RGAM_RAMB_START_CNTL_R_BASE_IDX 2
#define mmCM3_CM_RGAM_RAMB_SLOPE_CNTL_B 0x1062
#define mmCM3_CM_RGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2
#define mmCM3_CM_RGAM_RAMB_SLOPE_CNTL_G 0x1063
#define mmCM3_CM_RGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2
#define mmCM3_CM_RGAM_RAMB_SLOPE_CNTL_R 0x1064
#define mmCM3_CM_RGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2
#define mmCM3_CM_RGAM_RAMB_END_CNTL1_B 0x1065
#define mmCM3_CM_RGAM_RAMB_END_CNTL1_B_BASE_IDX 2
#define mmCM3_CM_RGAM_RAMB_END_CNTL2_B 0x1066
#define mmCM3_CM_RGAM_RAMB_END_CNTL2_B_BASE_IDX 2
#define mmCM3_CM_RGAM_RAMB_END_CNTL1_G 0x1067
#define mmCM3_CM_RGAM_RAMB_END_CNTL1_G_BASE_IDX 2
#define mmCM3_CM_RGAM_RAMB_END_CNTL2_G 0x1068
#define mmCM3_CM_RGAM_RAMB_END_CNTL2_G_BASE_IDX 2
#define mmCM3_CM_RGAM_RAMB_END_CNTL1_R 0x1069
#define mmCM3_CM_RGAM_RAMB_END_CNTL1_R_BASE_IDX 2
#define mmCM3_CM_RGAM_RAMB_END_CNTL2_R 0x106a
#define mmCM3_CM_RGAM_RAMB_END_CNTL2_R_BASE_IDX 2
#define mmCM3_CM_RGAM_RAMB_REGION_0_1 0x106b
#define mmCM3_CM_RGAM_RAMB_REGION_0_1_BASE_IDX 2
#define mmCM3_CM_RGAM_RAMB_REGION_2_3 0x106c
#define mmCM3_CM_RGAM_RAMB_REGION_2_3_BASE_IDX 2
#define mmCM3_CM_RGAM_RAMB_REGION_4_5 0x106d
#define mmCM3_CM_RGAM_RAMB_REGION_4_5_BASE_IDX 2
#define mmCM3_CM_RGAM_RAMB_REGION_6_7 0x106e
#define mmCM3_CM_RGAM_RAMB_REGION_6_7_BASE_IDX 2
#define mmCM3_CM_RGAM_RAMB_REGION_8_9 0x106f
#define mmCM3_CM_RGAM_RAMB_REGION_8_9_BASE_IDX 2
#define mmCM3_CM_RGAM_RAMB_REGION_10_11 0x1070
#define mmCM3_CM_RGAM_RAMB_REGION_10_11_BASE_IDX 2
#define mmCM3_CM_RGAM_RAMB_REGION_12_13 0x1071
#define mmCM3_CM_RGAM_RAMB_REGION_12_13_BASE_IDX 2
#define mmCM3_CM_RGAM_RAMB_REGION_14_15 0x1072
#define mmCM3_CM_RGAM_RAMB_REGION_14_15_BASE_IDX 2
#define mmCM3_CM_RGAM_RAMB_REGION_16_17 0x1073
#define mmCM3_CM_RGAM_RAMB_REGION_16_17_BASE_IDX 2
#define mmCM3_CM_RGAM_RAMB_REGION_18_19 0x1074
#define mmCM3_CM_RGAM_RAMB_REGION_18_19_BASE_IDX 2
#define mmCM3_CM_RGAM_RAMB_REGION_20_21 0x1075
#define mmCM3_CM_RGAM_RAMB_REGION_20_21_BASE_IDX 2
#define mmCM3_CM_RGAM_RAMB_REGION_22_23 0x1076
#define mmCM3_CM_RGAM_RAMB_REGION_22_23_BASE_IDX 2
#define mmCM3_CM_RGAM_RAMB_REGION_24_25 0x1077
#define mmCM3_CM_RGAM_RAMB_REGION_24_25_BASE_IDX 2
#define mmCM3_CM_RGAM_RAMB_REGION_26_27 0x1078
#define mmCM3_CM_RGAM_RAMB_REGION_26_27_BASE_IDX 2
#define mmCM3_CM_RGAM_RAMB_REGION_28_29 0x1079
#define mmCM3_CM_RGAM_RAMB_REGION_28_29_BASE_IDX 2
#define mmCM3_CM_RGAM_RAMB_REGION_30_31 0x107a
#define mmCM3_CM_RGAM_RAMB_REGION_30_31_BASE_IDX 2
#define mmCM3_CM_RGAM_RAMB_REGION_32_33 0x107b
#define mmCM3_CM_RGAM_RAMB_REGION_32_33_BASE_IDX 2
#define mmCM3_CM_HDR_MULT_COEF 0x107c
#define mmCM3_CM_HDR_MULT_COEF_BASE_IDX 2
#define mmCM3_CM_RANGE_CLAMP_CONTROL_R 0x107d
#define mmCM3_CM_RANGE_CLAMP_CONTROL_R_BASE_IDX 2
#define mmCM3_CM_RANGE_CLAMP_CONTROL_G 0x107e
#define mmCM3_CM_RANGE_CLAMP_CONTROL_G_BASE_IDX 2
#define mmCM3_CM_RANGE_CLAMP_CONTROL_B 0x107f
#define mmCM3_CM_RANGE_CLAMP_CONTROL_B_BASE_IDX 2
#define mmCM3_CM_DENORM_CONTROL 0x1080
#define mmCM3_CM_DENORM_CONTROL_BASE_IDX 2
#define mmCM3_CM_CMOUT_CONTROL 0x1081
#define mmCM3_CM_CMOUT_CONTROL_BASE_IDX 2
#define mmCM3_CM_CMOUT_RANDOM_SEEDS 0x1082
#define mmCM3_CM_CMOUT_RANDOM_SEEDS_BASE_IDX 2
#define mmCM3_CM_MEM_PWR_CTRL 0x1083
#define mmCM3_CM_MEM_PWR_CTRL_BASE_IDX 2
#define mmCM3_CM_MEM_PWR_STATUS 0x1084
#define mmCM3_CM_MEM_PWR_STATUS_BASE_IDX 2
#define mmCM3_CM_TEST_DEBUG_INDEX 0x1086
#define mmCM3_CM_TEST_DEBUG_INDEX_BASE_IDX 2
#define mmCM3_CM_TEST_DEBUG_DATA 0x1087
#define mmCM3_CM_TEST_DEBUG_DATA_BASE_IDX 2
// addressBlock: dce_dc_dpp3_dispdec_dpp_dcperfmon_dc_perfmon_dispdec
// base address: 0x4274
#define mmDC_PERFMON15_PERFCOUNTER_CNTL 0x109d
#define mmDC_PERFMON15_PERFCOUNTER_CNTL_BASE_IDX 2
#define mmDC_PERFMON15_PERFCOUNTER_CNTL2 0x109e
#define mmDC_PERFMON15_PERFCOUNTER_CNTL2_BASE_IDX 2
#define mmDC_PERFMON15_PERFCOUNTER_STATE 0x109f
#define mmDC_PERFMON15_PERFCOUNTER_STATE_BASE_IDX 2
#define mmDC_PERFMON15_PERFMON_CNTL 0x10a0
#define mmDC_PERFMON15_PERFMON_CNTL_BASE_IDX 2
#define mmDC_PERFMON15_PERFMON_CNTL2 0x10a1
#define mmDC_PERFMON15_PERFMON_CNTL2_BASE_IDX 2
#define mmDC_PERFMON15_PERFMON_CVALUE_INT_MISC 0x10a2
#define mmDC_PERFMON15_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
#define mmDC_PERFMON15_PERFMON_CVALUE_LOW 0x10a3
#define mmDC_PERFMON15_PERFMON_CVALUE_LOW_BASE_IDX 2
#define mmDC_PERFMON15_PERFMON_HI 0x10a4
#define mmDC_PERFMON15_PERFMON_HI_BASE_IDX 2
#define mmDC_PERFMON15_PERFMON_LOW 0x10a5
#define mmDC_PERFMON15_PERFMON_LOW_BASE_IDX 2
// addressBlock: dce_dc_mpc_mpcc0_dispdec
// base address: 0x0
#define mmMPCC0_MPCC_TOP_SEL 0x1630
#define mmMPCC0_MPCC_TOP_SEL_BASE_IDX 2
#define mmMPCC0_MPCC_BOT_SEL 0x1631
#define mmMPCC0_MPCC_BOT_SEL_BASE_IDX 2
#define mmMPCC0_MPCC_OPP_ID 0x1632
#define mmMPCC0_MPCC_OPP_ID_BASE_IDX 2
#define mmMPCC0_MPCC_CONTROL 0x1633
#define mmMPCC0_MPCC_CONTROL_BASE_IDX 2
#define mmMPCC0_MPCC_SM_CONTROL 0x1634
#define mmMPCC0_MPCC_SM_CONTROL_BASE_IDX 2
#define mmMPCC0_MPCC_UPDATE_LOCK_SEL 0x1635
#define mmMPCC0_MPCC_UPDATE_LOCK_SEL_BASE_IDX 2
#define mmMPCC0_MPCC_TOP_OFFSET 0x1636
#define mmMPCC0_MPCC_TOP_OFFSET_BASE_IDX 2
#define mmMPCC0_MPCC_BOT_OFFSET 0x1637
#define mmMPCC0_MPCC_BOT_OFFSET_BASE_IDX 2
#define mmMPCC0_MPCC_OFFSET 0x1638
#define mmMPCC0_MPCC_OFFSET_BASE_IDX 2
#define mmMPCC0_MPCC_BG_R_CR 0x1639
#define mmMPCC0_MPCC_BG_R_CR_BASE_IDX 2
#define mmMPCC0_MPCC_BG_G_Y 0x163a
#define mmMPCC0_MPCC_BG_G_Y_BASE_IDX 2
#define mmMPCC0_MPCC_BG_B_CB 0x163b
#define mmMPCC0_MPCC_BG_B_CB_BASE_IDX 2
#define mmMPCC0_MPCC_STALL_STATUS 0x163c
#define mmMPCC0_MPCC_STALL_STATUS_BASE_IDX 2
#define mmMPCC0_MPCC_STATUS 0x163d
#define mmMPCC0_MPCC_STATUS_BASE_IDX 2
// addressBlock: dce_dc_mpc_mpcc1_dispdec
// base address: 0x6c
#define mmMPCC1_MPCC_TOP_SEL 0x164b
#define mmMPCC1_MPCC_TOP_SEL_BASE_IDX 2
#define mmMPCC1_MPCC_BOT_SEL 0x164c
#define mmMPCC1_MPCC_BOT_SEL_BASE_IDX 2
#define mmMPCC1_MPCC_OPP_ID 0x164d
#define mmMPCC1_MPCC_OPP_ID_BASE_IDX 2
#define mmMPCC1_MPCC_CONTROL 0x164e
#define mmMPCC1_MPCC_CONTROL_BASE_IDX 2
#define mmMPCC1_MPCC_SM_CONTROL 0x164f
#define mmMPCC1_MPCC_SM_CONTROL_BASE_IDX 2
#define mmMPCC1_MPCC_UPDATE_LOCK_SEL 0x1650
#define mmMPCC1_MPCC_UPDATE_LOCK_SEL_BASE_IDX 2
#define mmMPCC1_MPCC_TOP_OFFSET 0x1651
#define mmMPCC1_MPCC_TOP_OFFSET_BASE_IDX 2
#define mmMPCC1_MPCC_BOT_OFFSET 0x1652
#define mmMPCC1_MPCC_BOT_OFFSET_BASE_IDX 2
#define mmMPCC1_MPCC_OFFSET 0x1653
#define mmMPCC1_MPCC_OFFSET_BASE_IDX 2
#define mmMPCC1_MPCC_BG_R_CR 0x1654
#define mmMPCC1_MPCC_BG_R_CR_BASE_IDX 2
#define mmMPCC1_MPCC_BG_G_Y 0x1655
#define mmMPCC1_MPCC_BG_G_Y_BASE_IDX 2
#define mmMPCC1_MPCC_BG_B_CB 0x1656
#define mmMPCC1_MPCC_BG_B_CB_BASE_IDX 2
#define mmMPCC1_MPCC_STALL_STATUS 0x1657
#define mmMPCC1_MPCC_STALL_STATUS_BASE_IDX 2
#define mmMPCC1_MPCC_STATUS 0x1658
#define mmMPCC1_MPCC_STATUS_BASE_IDX 2
// addressBlock: dce_dc_mpc_mpcc2_dispdec
// base address: 0xd8
#define mmMPCC2_MPCC_TOP_SEL 0x1666
#define mmMPCC2_MPCC_TOP_SEL_BASE_IDX 2
#define mmMPCC2_MPCC_BOT_SEL 0x1667
#define mmMPCC2_MPCC_BOT_SEL_BASE_IDX 2
#define mmMPCC2_MPCC_OPP_ID 0x1668
#define mmMPCC2_MPCC_OPP_ID_BASE_IDX 2
#define mmMPCC2_MPCC_CONTROL 0x1669
#define mmMPCC2_MPCC_CONTROL_BASE_IDX 2
#define mmMPCC2_MPCC_SM_CONTROL 0x166a
#define mmMPCC2_MPCC_SM_CONTROL_BASE_IDX 2
#define mmMPCC2_MPCC_UPDATE_LOCK_SEL 0x166b
#define mmMPCC2_MPCC_UPDATE_LOCK_SEL_BASE_IDX 2
#define mmMPCC2_MPCC_TOP_OFFSET 0x166c
#define mmMPCC2_MPCC_TOP_OFFSET_BASE_IDX 2
#define mmMPCC2_MPCC_BOT_OFFSET 0x166d
#define mmMPCC2_MPCC_BOT_OFFSET_BASE_IDX 2
#define mmMPCC2_MPCC_OFFSET 0x166e
#define mmMPCC2_MPCC_OFFSET_BASE_IDX 2
#define mmMPCC2_MPCC_BG_R_CR 0x166f
#define mmMPCC2_MPCC_BG_R_CR_BASE_IDX 2
#define mmMPCC2_MPCC_BG_G_Y 0x1670
#define mmMPCC2_MPCC_BG_G_Y_BASE_IDX 2
#define mmMPCC2_MPCC_BG_B_CB 0x1671
#define mmMPCC2_MPCC_BG_B_CB_BASE_IDX 2
#define mmMPCC2_MPCC_STALL_STATUS 0x1672
#define mmMPCC2_MPCC_STALL_STATUS_BASE_IDX 2
#define mmMPCC2_MPCC_STATUS 0x1673
#define mmMPCC2_MPCC_STATUS_BASE_IDX 2
// addressBlock: dce_dc_mpc_mpcc3_dispdec
// base address: 0x144
#define mmMPCC3_MPCC_TOP_SEL 0x1681
#define mmMPCC3_MPCC_TOP_SEL_BASE_IDX 2
#define mmMPCC3_MPCC_BOT_SEL 0x1682
#define mmMPCC3_MPCC_BOT_SEL_BASE_IDX 2
#define mmMPCC3_MPCC_OPP_ID 0x1683
#define mmMPCC3_MPCC_OPP_ID_BASE_IDX 2
#define mmMPCC3_MPCC_CONTROL 0x1684
#define mmMPCC3_MPCC_CONTROL_BASE_IDX 2
#define mmMPCC3_MPCC_SM_CONTROL 0x1685
#define mmMPCC3_MPCC_SM_CONTROL_BASE_IDX 2
#define mmMPCC3_MPCC_UPDATE_LOCK_SEL 0x1686
#define mmMPCC3_MPCC_UPDATE_LOCK_SEL_BASE_IDX 2
#define mmMPCC3_MPCC_TOP_OFFSET 0x1687
#define mmMPCC3_MPCC_TOP_OFFSET_BASE_IDX 2
#define mmMPCC3_MPCC_BOT_OFFSET 0x1688
#define mmMPCC3_MPCC_BOT_OFFSET_BASE_IDX 2
#define mmMPCC3_MPCC_OFFSET 0x1689
#define mmMPCC3_MPCC_OFFSET_BASE_IDX 2
#define mmMPCC3_MPCC_BG_R_CR 0x168a
#define mmMPCC3_MPCC_BG_R_CR_BASE_IDX 2
#define mmMPCC3_MPCC_BG_G_Y 0x168b
#define mmMPCC3_MPCC_BG_G_Y_BASE_IDX 2
#define mmMPCC3_MPCC_BG_B_CB 0x168c
#define mmMPCC3_MPCC_BG_B_CB_BASE_IDX 2
#define mmMPCC3_MPCC_STALL_STATUS 0x168d
#define mmMPCC3_MPCC_STALL_STATUS_BASE_IDX 2
#define mmMPCC3_MPCC_STATUS 0x168e
#define mmMPCC3_MPCC_STATUS_BASE_IDX 2
// addressBlock: dce_dc_mpc_mpc_cfg_dispdec
// base address: 0x0
#define mmMPC_CLOCK_CONTROL 0x1723
#define mmMPC_CLOCK_CONTROL_BASE_IDX 2
#define mmMPC_SOFT_RESET 0x1724
#define mmMPC_SOFT_RESET_BASE_IDX 2
#define mmMPC_CRC_CTRL 0x1725
#define mmMPC_CRC_CTRL_BASE_IDX 2
#define mmMPC_CRC_SEL_CONTROL 0x1726
#define mmMPC_CRC_SEL_CONTROL_BASE_IDX 2
#define mmMPC_CRC_RESULT_AR 0x1727
#define mmMPC_CRC_RESULT_AR_BASE_IDX 2
#define mmMPC_CRC_RESULT_GB 0x1728
#define mmMPC_CRC_RESULT_GB_BASE_IDX 2
#define mmMPC_CRC_RESULT_C 0x1729
#define mmMPC_CRC_RESULT_C_BASE_IDX 2
#define mmMPC_PERFMON_EVENT_CTRL 0x172c
#define mmMPC_PERFMON_EVENT_CTRL_BASE_IDX 2
#define mmMPC_BYPASS_BG_AR 0x172d
#define mmMPC_BYPASS_BG_AR_BASE_IDX 2
#define mmMPC_BYPASS_BG_GB 0x172e
#define mmMPC_BYPASS_BG_GB_BASE_IDX 2
#define mmMPC_OUT0_MUX 0x172f
#define mmMPC_OUT0_MUX_BASE_IDX 2
#define mmMPC_OUT1_MUX 0x1730
#define mmMPC_OUT1_MUX_BASE_IDX 2
#define mmMPC_OUT2_MUX 0x1731
#define mmMPC_OUT2_MUX_BASE_IDX 2
#define mmMPC_OUT3_MUX 0x1732
#define mmMPC_OUT3_MUX_BASE_IDX 2
#define mmMPC_STALL_GRACE_WINDOW 0x1756
#define mmMPC_STALL_GRACE_WINDOW_BASE_IDX 2
#define mmADR_CFG_VUPDATE_LOCK_SET0 0x175b
#define mmADR_CFG_VUPDATE_LOCK_SET0_BASE_IDX 2
#define mmADR_VUPDATE_LOCK_SET0 0x175c
#define mmADR_VUPDATE_LOCK_SET0_BASE_IDX 2
#define mmCUR0_VUPDATE_LOCK_SET0 0x175d
#define mmCUR0_VUPDATE_LOCK_SET0_BASE_IDX 2
#define mmCUR1_VUPDATE_LOCK_SET0 0x175e
#define mmCUR1_VUPDATE_LOCK_SET0_BASE_IDX 2
#define mmADR_CFG_VUPDATE_LOCK_SET1 0x175f
#define mmADR_CFG_VUPDATE_LOCK_SET1_BASE_IDX 2
#define mmADR_VUPDATE_LOCK_SET1 0x1760
#define mmADR_VUPDATE_LOCK_SET1_BASE_IDX 2
#define mmCUR0_VUPDATE_LOCK_SET1 0x1761
#define mmCUR0_VUPDATE_LOCK_SET1_BASE_IDX 2
#define mmCUR1_VUPDATE_LOCK_SET1 0x1762
#define mmCUR1_VUPDATE_LOCK_SET1_BASE_IDX 2
#define mmADR_CFG_VUPDATE_LOCK_SET2 0x1763
#define mmADR_CFG_VUPDATE_LOCK_SET2_BASE_IDX 2
#define mmADR_VUPDATE_LOCK_SET2 0x1764
#define mmADR_VUPDATE_LOCK_SET2_BASE_IDX 2
#define mmCUR0_VUPDATE_LOCK_SET2 0x1765
#define mmCUR0_VUPDATE_LOCK_SET2_BASE_IDX 2
#define mmCUR1_VUPDATE_LOCK_SET2 0x1766
#define mmCUR1_VUPDATE_LOCK_SET2_BASE_IDX 2
#define mmADR_CFG_VUPDATE_LOCK_SET3 0x1767
#define mmADR_CFG_VUPDATE_LOCK_SET3_BASE_IDX 2
#define mmADR_VUPDATE_LOCK_SET3 0x1768
#define mmADR_VUPDATE_LOCK_SET3_BASE_IDX 2
#define mmCUR0_VUPDATE_LOCK_SET3 0x1769
#define mmCUR0_VUPDATE_LOCK_SET3_BASE_IDX 2
#define mmCUR1_VUPDATE_LOCK_SET3 0x176a
#define mmCUR1_VUPDATE_LOCK_SET3_BASE_IDX 2
// addressBlock: dce_dc_mpc_mpc_dcperfmon_dc_perfmon_dispdec
// base address: 0x5e90
#define mmDC_PERFMON16_PERFCOUNTER_CNTL 0x17a4
#define mmDC_PERFMON16_PERFCOUNTER_CNTL_BASE_IDX 2
#define mmDC_PERFMON16_PERFCOUNTER_CNTL2 0x17a5
#define mmDC_PERFMON16_PERFCOUNTER_CNTL2_BASE_IDX 2
#define mmDC_PERFMON16_PERFCOUNTER_STATE 0x17a6
#define mmDC_PERFMON16_PERFCOUNTER_STATE_BASE_IDX 2
#define mmDC_PERFMON16_PERFMON_CNTL 0x17a7
#define mmDC_PERFMON16_PERFMON_CNTL_BASE_IDX 2
#define mmDC_PERFMON16_PERFMON_CNTL2 0x17a8
#define mmDC_PERFMON16_PERFMON_CNTL2_BASE_IDX 2
#define mmDC_PERFMON16_PERFMON_CVALUE_INT_MISC 0x17a9
#define mmDC_PERFMON16_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
#define mmDC_PERFMON16_PERFMON_CVALUE_LOW 0x17aa
#define mmDC_PERFMON16_PERFMON_CVALUE_LOW_BASE_IDX 2
#define mmDC_PERFMON16_PERFMON_HI 0x17ab
#define mmDC_PERFMON16_PERFMON_HI_BASE_IDX 2
#define mmDC_PERFMON16_PERFMON_LOW 0x17ac
#define mmDC_PERFMON16_PERFMON_LOW_BASE_IDX 2
// addressBlock: dce_dc_opp_abm0_dispdec
// base address: 0x0
#define mmABM0_BL1_PWM_AMBIENT_LIGHT_LEVEL 0x17b0
#define mmABM0_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX 2
#define mmABM0_BL1_PWM_USER_LEVEL 0x17b1
#define mmABM0_BL1_PWM_USER_LEVEL_BASE_IDX 2
#define mmABM0_BL1_PWM_TARGET_ABM_LEVEL 0x17b2
#define mmABM0_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX 2
#define mmABM0_BL1_PWM_CURRENT_ABM_LEVEL 0x17b3
#define mmABM0_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX 2
#define mmABM0_BL1_PWM_FINAL_DUTY_CYCLE 0x17b4
#define mmABM0_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX 2
#define mmABM0_BL1_PWM_MINIMUM_DUTY_CYCLE 0x17b5
#define mmABM0_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX 2
#define mmABM0_BL1_PWM_ABM_CNTL 0x17b6
#define mmABM0_BL1_PWM_ABM_CNTL_BASE_IDX 2
#define mmABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE 0x17b7
#define mmABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX 2
#define mmABM0_BL1_PWM_GRP2_REG_LOCK 0x17b8
#define mmABM0_BL1_PWM_GRP2_REG_LOCK_BASE_IDX 2
#define mmABM0_DC_ABM1_CNTL 0x17b9
#define mmABM0_DC_ABM1_CNTL_BASE_IDX 2
#define mmABM0_DC_ABM1_IPCSC_COEFF_SEL 0x17ba
#define mmABM0_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX 2
#define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_0 0x17bb
#define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_0_BASE_IDX 2
#define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_1 0x17bc
#define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_1_BASE_IDX 2
#define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_2 0x17bd
#define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_2_BASE_IDX 2
#define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_3 0x17be
#define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_3_BASE_IDX 2
#define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_4 0x17bf
#define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_4_BASE_IDX 2
#define mmABM0_DC_ABM1_ACE_THRES_12 0x17c0
#define mmABM0_DC_ABM1_ACE_THRES_12_BASE_IDX 2
#define mmABM0_DC_ABM1_ACE_THRES_34 0x17c1
#define mmABM0_DC_ABM1_ACE_THRES_34_BASE_IDX 2
#define mmABM0_DC_ABM1_ACE_CNTL_MISC 0x17c2
#define mmABM0_DC_ABM1_ACE_CNTL_MISC_BASE_IDX 2
#define mmABM0_DC_ABM1_HGLS_REG_READ_PROGRESS 0x17c4
#define mmABM0_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX 2
#define mmABM0_DC_ABM1_HG_MISC_CTRL 0x17c5
#define mmABM0_DC_ABM1_HG_MISC_CTRL_BASE_IDX 2
#define mmABM0_DC_ABM1_LS_SUM_OF_LUMA 0x17c6
#define mmABM0_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX 2
#define mmABM0_DC_ABM1_LS_MIN_MAX_LUMA 0x17c7
#define mmABM0_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX 2
#define mmABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA 0x17c8
#define mmABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX 2
#define mmABM0_DC_ABM1_LS_PIXEL_COUNT 0x17c9
#define mmABM0_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX 2
#define mmABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES 0x17ca
#define mmABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX 2
#define mmABM0_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT 0x17cb
#define mmABM0_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX 2
#define mmABM0_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT 0x17cc
#define mmABM0_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX 2
#define mmABM0_DC_ABM1_HG_SAMPLE_RATE 0x17cd
#define mmABM0_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX 2
#define mmABM0_DC_ABM1_LS_SAMPLE_RATE 0x17ce
#define mmABM0_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX 2
#define mmABM0_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG 0x17cf
#define mmABM0_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX 2
#define mmABM0_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX 0x17d0
#define mmABM0_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX 2
#define mmABM0_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX 0x17d1
#define mmABM0_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX 2
#define mmABM0_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX 0x17d2
#define mmABM0_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX 2
#define mmABM0_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX 0x17d3
#define mmABM0_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX 2
#define mmABM0_DC_ABM1_HG_RESULT_1 0x17d4
#define mmABM0_DC_ABM1_HG_RESULT_1_BASE_IDX 2
#define mmABM0_DC_ABM1_HG_RESULT_2 0x17d5
#define mmABM0_DC_ABM1_HG_RESULT_2_BASE_IDX 2
#define mmABM0_DC_ABM1_HG_RESULT_3 0x17d6
#define mmABM0_DC_ABM1_HG_RESULT_3_BASE_IDX 2
#define mmABM0_DC_ABM1_HG_RESULT_4 0x17d7
#define mmABM0_DC_ABM1_HG_RESULT_4_BASE_IDX 2
#define mmABM0_DC_ABM1_HG_RESULT_5 0x17d8
#define mmABM0_DC_ABM1_HG_RESULT_5_BASE_IDX 2
#define mmABM0_DC_ABM1_HG_RESULT_6 0x17d9
#define mmABM0_DC_ABM1_HG_RESULT_6_BASE_IDX 2
#define mmABM0_DC_ABM1_HG_RESULT_7 0x17da
#define mmABM0_DC_ABM1_HG_RESULT_7_BASE_IDX 2
#define mmABM0_DC_ABM1_HG_RESULT_8 0x17db
#define mmABM0_DC_ABM1_HG_RESULT_8_BASE_IDX 2
#define mmABM0_DC_ABM1_HG_RESULT_9 0x17dc
#define mmABM0_DC_ABM1_HG_RESULT_9_BASE_IDX 2
#define mmABM0_DC_ABM1_HG_RESULT_10 0x17dd
#define mmABM0_DC_ABM1_HG_RESULT_10_BASE_IDX 2
#define mmABM0_DC_ABM1_HG_RESULT_11 0x17de
#define mmABM0_DC_ABM1_HG_RESULT_11_BASE_IDX 2
#define mmABM0_DC_ABM1_HG_RESULT_12 0x17df
#define mmABM0_DC_ABM1_HG_RESULT_12_BASE_IDX 2
#define mmABM0_DC_ABM1_HG_RESULT_13 0x17e0
#define mmABM0_DC_ABM1_HG_RESULT_13_BASE_IDX 2
#define mmABM0_DC_ABM1_HG_RESULT_14 0x17e1
#define mmABM0_DC_ABM1_HG_RESULT_14_BASE_IDX 2
#define mmABM0_DC_ABM1_HG_RESULT_15 0x17e2
#define mmABM0_DC_ABM1_HG_RESULT_15_BASE_IDX 2
#define mmABM0_DC_ABM1_HG_RESULT_16 0x17e3
#define mmABM0_DC_ABM1_HG_RESULT_16_BASE_IDX 2
#define mmABM0_DC_ABM1_HG_RESULT_17 0x17e4
#define mmABM0_DC_ABM1_HG_RESULT_17_BASE_IDX 2
#define mmABM0_DC_ABM1_HG_RESULT_18 0x17e5
#define mmABM0_DC_ABM1_HG_RESULT_18_BASE_IDX 2
#define mmABM0_DC_ABM1_HG_RESULT_19 0x17e6
#define mmABM0_DC_ABM1_HG_RESULT_19_BASE_IDX 2
#define mmABM0_DC_ABM1_HG_RESULT_20 0x17e7
#define mmABM0_DC_ABM1_HG_RESULT_20_BASE_IDX 2
#define mmABM0_DC_ABM1_HG_RESULT_21 0x17e8
#define mmABM0_DC_ABM1_HG_RESULT_21_BASE_IDX 2
#define mmABM0_DC_ABM1_HG_RESULT_22 0x17e9
#define mmABM0_DC_ABM1_HG_RESULT_22_BASE_IDX 2
#define mmABM0_DC_ABM1_HG_RESULT_23 0x17ea
#define mmABM0_DC_ABM1_HG_RESULT_23_BASE_IDX 2
#define mmABM0_DC_ABM1_HG_RESULT_24 0x17eb
#define mmABM0_DC_ABM1_HG_RESULT_24_BASE_IDX 2
#define mmABM0_DC_ABM1_BL_MASTER_LOCK 0x17ec
#define mmABM0_DC_ABM1_BL_MASTER_LOCK_BASE_IDX 2
// addressBlock: dce_dc_opp_abm1_dispdec
// base address: 0x118
#define mmABM1_BL1_PWM_AMBIENT_LIGHT_LEVEL 0x17f6
#define mmABM1_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX 2
#define mmABM1_BL1_PWM_USER_LEVEL 0x17f7
#define mmABM1_BL1_PWM_USER_LEVEL_BASE_IDX 2
#define mmABM1_BL1_PWM_TARGET_ABM_LEVEL 0x17f8
#define mmABM1_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX 2
#define mmABM1_BL1_PWM_CURRENT_ABM_LEVEL 0x17f9
#define mmABM1_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX 2
#define mmABM1_BL1_PWM_FINAL_DUTY_CYCLE 0x17fa
#define mmABM1_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX 2
#define mmABM1_BL1_PWM_MINIMUM_DUTY_CYCLE 0x17fb
#define mmABM1_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX 2
#define mmABM1_BL1_PWM_ABM_CNTL 0x17fc
#define mmABM1_BL1_PWM_ABM_CNTL_BASE_IDX 2
#define mmABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE 0x17fd
#define mmABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX 2
#define mmABM1_BL1_PWM_GRP2_REG_LOCK 0x17fe
#define mmABM1_BL1_PWM_GRP2_REG_LOCK_BASE_IDX 2
#define mmABM1_DC_ABM1_CNTL 0x17ff
#define mmABM1_DC_ABM1_CNTL_BASE_IDX 2
#define mmABM1_DC_ABM1_IPCSC_COEFF_SEL 0x1800
#define mmABM1_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX 2
#define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_0 0x1801
#define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_0_BASE_IDX 2
#define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_1 0x1802
#define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_1_BASE_IDX 2
#define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_2 0x1803
#define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_2_BASE_IDX 2
#define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_3 0x1804
#define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_3_BASE_IDX 2
#define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_4 0x1805
#define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_4_BASE_IDX 2
#define mmABM1_DC_ABM1_ACE_THRES_12 0x1806
#define mmABM1_DC_ABM1_ACE_THRES_12_BASE_IDX 2
#define mmABM1_DC_ABM1_ACE_THRES_34 0x1807
#define mmABM1_DC_ABM1_ACE_THRES_34_BASE_IDX 2
#define mmABM1_DC_ABM1_ACE_CNTL_MISC 0x1808
#define mmABM1_DC_ABM1_ACE_CNTL_MISC_BASE_IDX 2
#define mmABM1_DC_ABM1_HGLS_REG_READ_PROGRESS 0x180a
#define mmABM1_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX 2
#define mmABM1_DC_ABM1_HG_MISC_CTRL 0x180b
#define mmABM1_DC_ABM1_HG_MISC_CTRL_BASE_IDX 2
#define mmABM1_DC_ABM1_LS_SUM_OF_LUMA 0x180c
#define mmABM1_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX 2
#define mmABM1_DC_ABM1_LS_MIN_MAX_LUMA 0x180d
#define mmABM1_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX 2
#define mmABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA 0x180e
#define mmABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX 2
#define mmABM1_DC_ABM1_LS_PIXEL_COUNT 0x180f
#define mmABM1_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX 2
#define mmABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES 0x1810
#define mmABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX 2
#define mmABM1_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT 0x1811
#define mmABM1_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX 2
#define mmABM1_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT 0x1812
#define mmABM1_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX 2
#define mmABM1_DC_ABM1_HG_SAMPLE_RATE 0x1813
#define mmABM1_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX 2
#define mmABM1_DC_ABM1_LS_SAMPLE_RATE 0x1814
#define mmABM1_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX 2
#define mmABM1_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG 0x1815
#define mmABM1_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX 2
#define mmABM1_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX 0x1816
#define mmABM1_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX 2
#define mmABM1_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX 0x1817
#define mmABM1_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX 2
#define mmABM1_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX 0x1818
#define mmABM1_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX 2
#define mmABM1_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX 0x1819
#define mmABM1_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX 2
#define mmABM1_DC_ABM1_HG_RESULT_1 0x181a
#define mmABM1_DC_ABM1_HG_RESULT_1_BASE_IDX 2
#define mmABM1_DC_ABM1_HG_RESULT_2 0x181b
#define mmABM1_DC_ABM1_HG_RESULT_2_BASE_IDX 2
#define mmABM1_DC_ABM1_HG_RESULT_3 0x181c
#define mmABM1_DC_ABM1_HG_RESULT_3_BASE_IDX 2
#define mmABM1_DC_ABM1_HG_RESULT_4 0x181d
#define mmABM1_DC_ABM1_HG_RESULT_4_BASE_IDX 2
#define mmABM1_DC_ABM1_HG_RESULT_5 0x181e
#define mmABM1_DC_ABM1_HG_RESULT_5_BASE_IDX 2
#define mmABM1_DC_ABM1_HG_RESULT_6 0x181f
#define mmABM1_DC_ABM1_HG_RESULT_6_BASE_IDX 2
#define mmABM1_DC_ABM1_HG_RESULT_7 0x1820
#define mmABM1_DC_ABM1_HG_RESULT_7_BASE_IDX 2
#define mmABM1_DC_ABM1_HG_RESULT_8 0x1821
#define mmABM1_DC_ABM1_HG_RESULT_8_BASE_IDX 2
#define mmABM1_DC_ABM1_HG_RESULT_9 0x1822
#define mmABM1_DC_ABM1_HG_RESULT_9_BASE_IDX 2
#define mmABM1_DC_ABM1_HG_RESULT_10 0x1823
#define mmABM1_DC_ABM1_HG_RESULT_10_BASE_IDX 2
#define mmABM1_DC_ABM1_HG_RESULT_11 0x1824
#define mmABM1_DC_ABM1_HG_RESULT_11_BASE_IDX 2
#define mmABM1_DC_ABM1_HG_RESULT_12 0x1825
#define mmABM1_DC_ABM1_HG_RESULT_12_BASE_IDX 2
#define mmABM1_DC_ABM1_HG_RESULT_13 0x1826
#define mmABM1_DC_ABM1_HG_RESULT_13_BASE_IDX 2
#define mmABM1_DC_ABM1_HG_RESULT_14 0x1827
#define mmABM1_DC_ABM1_HG_RESULT_14_BASE_IDX 2
#define mmABM1_DC_ABM1_HG_RESULT_15 0x1828
#define mmABM1_DC_ABM1_HG_RESULT_15_BASE_IDX 2
#define mmABM1_DC_ABM1_HG_RESULT_16 0x1829
#define mmABM1_DC_ABM1_HG_RESULT_16_BASE_IDX 2
#define mmABM1_DC_ABM1_HG_RESULT_17 0x182a
#define mmABM1_DC_ABM1_HG_RESULT_17_BASE_IDX 2
#define mmABM1_DC_ABM1_HG_RESULT_18 0x182b
#define mmABM1_DC_ABM1_HG_RESULT_18_BASE_IDX 2
#define mmABM1_DC_ABM1_HG_RESULT_19 0x182c
#define mmABM1_DC_ABM1_HG_RESULT_19_BASE_IDX 2
#define mmABM1_DC_ABM1_HG_RESULT_20 0x182d
#define mmABM1_DC_ABM1_HG_RESULT_20_BASE_IDX 2
#define mmABM1_DC_ABM1_HG_RESULT_21 0x182e
#define mmABM1_DC_ABM1_HG_RESULT_21_BASE_IDX 2
#define mmABM1_DC_ABM1_HG_RESULT_22 0x182f
#define mmABM1_DC_ABM1_HG_RESULT_22_BASE_IDX 2
#define mmABM1_DC_ABM1_HG_RESULT_23 0x1830
#define mmABM1_DC_ABM1_HG_RESULT_23_BASE_IDX 2
#define mmABM1_DC_ABM1_HG_RESULT_24 0x1831
#define mmABM1_DC_ABM1_HG_RESULT_24_BASE_IDX 2
#define mmABM1_DC_ABM1_BL_MASTER_LOCK 0x1832
#define mmABM1_DC_ABM1_BL_MASTER_LOCK_BASE_IDX 2
// addressBlock: dce_dc_opp_fmt0_dispdec
// base address: 0x0
#define mmFMT0_FMT_CLAMP_COMPONENT_R 0x183c
#define mmFMT0_FMT_CLAMP_COMPONENT_R_BASE_IDX 2
#define mmFMT0_FMT_CLAMP_COMPONENT_G 0x183d
#define mmFMT0_FMT_CLAMP_COMPONENT_G_BASE_IDX 2
#define mmFMT0_FMT_CLAMP_COMPONENT_B 0x183e
#define mmFMT0_FMT_CLAMP_COMPONENT_B_BASE_IDX 2
#define mmFMT0_FMT_DYNAMIC_EXP_CNTL 0x183f
#define mmFMT0_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2
#define mmFMT0_FMT_CONTROL 0x1840
#define mmFMT0_FMT_CONTROL_BASE_IDX 2
#define mmFMT0_FMT_BIT_DEPTH_CONTROL 0x1841
#define mmFMT0_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2
#define mmFMT0_FMT_DITHER_RAND_R_SEED 0x1842
#define mmFMT0_FMT_DITHER_RAND_R_SEED_BASE_IDX 2
#define mmFMT0_FMT_DITHER_RAND_G_SEED 0x1843
#define mmFMT0_FMT_DITHER_RAND_G_SEED_BASE_IDX 2
#define mmFMT0_FMT_DITHER_RAND_B_SEED 0x1844
#define mmFMT0_FMT_DITHER_RAND_B_SEED_BASE_IDX 2
#define mmFMT0_FMT_CLAMP_CNTL 0x1848
#define mmFMT0_FMT_CLAMP_CNTL_BASE_IDX 2
#define mmFMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x1849
#define mmFMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2
#define mmFMT0_FMT_MAP420_MEMORY_CONTROL 0x184a
#define mmFMT0_FMT_MAP420_MEMORY_CONTROL_BASE_IDX 2
// addressBlock: dce_dc_opp_oppbuf0_dispdec
// base address: 0x0
#define mmOPPBUF0_OPPBUF_CONTROL 0x1884
#define mmOPPBUF0_OPPBUF_CONTROL_BASE_IDX 2
#define mmOPPBUF0_OPPBUF_3D_PARAMETERS_0 0x1885
#define mmOPPBUF0_OPPBUF_3D_PARAMETERS_0_BASE_IDX 2
#define mmOPPBUF0_OPPBUF_3D_PARAMETERS_1 0x1886
#define mmOPPBUF0_OPPBUF_3D_PARAMETERS_1_BASE_IDX 2
// addressBlock: dce_dc_opp_opp_pipe0_dispdec
// base address: 0x0
#define mmOPP_PIPE0_OPP_PIPE_CONTROL 0x188c
#define mmOPP_PIPE0_OPP_PIPE_CONTROL_BASE_IDX 2
// addressBlock: dce_dc_opp_opp_pipe_crc0_dispdec
// base address: 0x0
#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL 0x1891
#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL_BASE_IDX 2
#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_MASK 0x1892
#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_MASK_BASE_IDX 2
#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0 0x1893
#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0_BASE_IDX 2
#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1 0x1894
#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1_BASE_IDX 2
#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2 0x1895
#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2_BASE_IDX 2
// addressBlock: dce_dc_opp_fmt1_dispdec
// base address: 0x168
#define mmFMT1_FMT_CLAMP_COMPONENT_R 0x1896
#define mmFMT1_FMT_CLAMP_COMPONENT_R_BASE_IDX 2
#define mmFMT1_FMT_CLAMP_COMPONENT_G 0x1897
#define mmFMT1_FMT_CLAMP_COMPONENT_G_BASE_IDX 2
#define mmFMT1_FMT_CLAMP_COMPONENT_B 0x1898
#define mmFMT1_FMT_CLAMP_COMPONENT_B_BASE_IDX 2
#define mmFMT1_FMT_DYNAMIC_EXP_CNTL 0x1899
#define mmFMT1_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2
#define mmFMT1_FMT_CONTROL 0x189a
#define mmFMT1_FMT_CONTROL_BASE_IDX 2
#define mmFMT1_FMT_BIT_DEPTH_CONTROL 0x189b
#define mmFMT1_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2
#define mmFMT1_FMT_DITHER_RAND_R_SEED 0x189c
#define mmFMT1_FMT_DITHER_RAND_R_SEED_BASE_IDX 2
#define mmFMT1_FMT_DITHER_RAND_G_SEED 0x189d
#define mmFMT1_FMT_DITHER_RAND_G_SEED_BASE_IDX 2
#define mmFMT1_FMT_DITHER_RAND_B_SEED 0x189e
#define mmFMT1_FMT_DITHER_RAND_B_SEED_BASE_IDX 2
#define mmFMT1_FMT_CLAMP_CNTL 0x18a2
#define mmFMT1_FMT_CLAMP_CNTL_BASE_IDX 2
#define mmFMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x18a3
#define mmFMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2
#define mmFMT1_FMT_MAP420_MEMORY_CONTROL 0x18a4
#define mmFMT1_FMT_MAP420_MEMORY_CONTROL_BASE_IDX 2
// addressBlock: dce_dc_opp_oppbuf1_dispdec
// base address: 0x168
#define mmOPPBUF1_OPPBUF_CONTROL 0x18de
#define mmOPPBUF1_OPPBUF_CONTROL_BASE_IDX 2
#define mmOPPBUF1_OPPBUF_3D_PARAMETERS_0 0x18df
#define mmOPPBUF1_OPPBUF_3D_PARAMETERS_0_BASE_IDX 2
#define mmOPPBUF1_OPPBUF_3D_PARAMETERS_1 0x18e0
#define mmOPPBUF1_OPPBUF_3D_PARAMETERS_1_BASE_IDX 2
// addressBlock: dce_dc_opp_opp_pipe1_dispdec
// base address: 0x168
#define mmOPP_PIPE1_OPP_PIPE_CONTROL 0x18e6
#define mmOPP_PIPE1_OPP_PIPE_CONTROL_BASE_IDX 2
// addressBlock: dce_dc_opp_opp_pipe_crc1_dispdec
// base address: 0x168
#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL 0x18eb
#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL_BASE_IDX 2
#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_MASK 0x18ec
#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_MASK_BASE_IDX 2
#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0 0x18ed
#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0_BASE_IDX 2
#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1 0x18ee
#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1_BASE_IDX 2
#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2 0x18ef
#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2_BASE_IDX 2
// addressBlock: dce_dc_opp_fmt2_dispdec
// base address: 0x2d0
#define mmFMT2_FMT_CLAMP_COMPONENT_R 0x18f0
#define mmFMT2_FMT_CLAMP_COMPONENT_R_BASE_IDX 2
#define mmFMT2_FMT_CLAMP_COMPONENT_G 0x18f1
#define mmFMT2_FMT_CLAMP_COMPONENT_G_BASE_IDX 2
#define mmFMT2_FMT_CLAMP_COMPONENT_B 0x18f2
#define mmFMT2_FMT_CLAMP_COMPONENT_B_BASE_IDX 2
#define mmFMT2_FMT_DYNAMIC_EXP_CNTL 0x18f3
#define mmFMT2_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2
#define mmFMT2_FMT_CONTROL 0x18f4
#define mmFMT2_FMT_CONTROL_BASE_IDX 2
#define mmFMT2_FMT_BIT_DEPTH_CONTROL 0x18f5
#define mmFMT2_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2
#define mmFMT2_FMT_DITHER_RAND_R_SEED 0x18f6
#define mmFMT2_FMT_DITHER_RAND_R_SEED_BASE_IDX 2
#define mmFMT2_FMT_DITHER_RAND_G_SEED 0x18f7
#define mmFMT2_FMT_DITHER_RAND_G_SEED_BASE_IDX 2
#define mmFMT2_FMT_DITHER_RAND_B_SEED 0x18f8
#define mmFMT2_FMT_DITHER_RAND_B_SEED_BASE_IDX 2
#define mmFMT2_FMT_CLAMP_CNTL 0x18fc
#define mmFMT2_FMT_CLAMP_CNTL_BASE_IDX 2
#define mmFMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x18fd
#define mmFMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2
#define mmFMT2_FMT_MAP420_MEMORY_CONTROL 0x18fe
#define mmFMT2_FMT_MAP420_MEMORY_CONTROL_BASE_IDX 2
// addressBlock: dce_dc_opp_oppbuf2_dispdec
// base address: 0x2d0
#define mmOPPBUF2_OPPBUF_CONTROL 0x1938
#define mmOPPBUF2_OPPBUF_CONTROL_BASE_IDX 2
#define mmOPPBUF2_OPPBUF_3D_PARAMETERS_0 0x1939
#define mmOPPBUF2_OPPBUF_3D_PARAMETERS_0_BASE_IDX 2
#define mmOPPBUF2_OPPBUF_3D_PARAMETERS_1 0x193a
#define mmOPPBUF2_OPPBUF_3D_PARAMETERS_1_BASE_IDX 2
// addressBlock: dce_dc_opp_opp_pipe2_dispdec
// base address: 0x2d0
#define mmOPP_PIPE2_OPP_PIPE_CONTROL 0x1940
#define mmOPP_PIPE2_OPP_PIPE_CONTROL_BASE_IDX 2
// addressBlock: dce_dc_opp_opp_pipe_crc2_dispdec
// base address: 0x2d0
#define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL 0x1945
#define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL_BASE_IDX 2
#define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_MASK 0x1946
#define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_MASK_BASE_IDX 2
#define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0 0x1947
#define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0_BASE_IDX 2
#define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1 0x1948
#define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1_BASE_IDX 2
#define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT2 0x1949
#define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT2_BASE_IDX 2
// addressBlock: dce_dc_opp_fmt3_dispdec
// base address: 0x438
#define mmFMT3_FMT_CLAMP_COMPONENT_R 0x194a
#define mmFMT3_FMT_CLAMP_COMPONENT_R_BASE_IDX 2
#define mmFMT3_FMT_CLAMP_COMPONENT_G 0x194b
#define mmFMT3_FMT_CLAMP_COMPONENT_G_BASE_IDX 2
#define mmFMT3_FMT_CLAMP_COMPONENT_B 0x194c
#define mmFMT3_FMT_CLAMP_COMPONENT_B_BASE_IDX 2
#define mmFMT3_FMT_DYNAMIC_EXP_CNTL 0x194d
#define mmFMT3_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2
#define mmFMT3_FMT_CONTROL 0x194e
#define mmFMT3_FMT_CONTROL_BASE_IDX 2
#define mmFMT3_FMT_BIT_DEPTH_CONTROL 0x194f
#define mmFMT3_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2
#define mmFMT3_FMT_DITHER_RAND_R_SEED 0x1950
#define mmFMT3_FMT_DITHER_RAND_R_SEED_BASE_IDX 2
#define mmFMT3_FMT_DITHER_RAND_G_SEED 0x1951
#define mmFMT3_FMT_DITHER_RAND_G_SEED_BASE_IDX 2
#define mmFMT3_FMT_DITHER_RAND_B_SEED 0x1952
#define mmFMT3_FMT_DITHER_RAND_B_SEED_BASE_IDX 2
#define mmFMT3_FMT_CLAMP_CNTL 0x1956
#define mmFMT3_FMT_CLAMP_CNTL_BASE_IDX 2
#define mmFMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x1957
#define mmFMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2
#define mmFMT3_FMT_MAP420_MEMORY_CONTROL 0x1958
#define mmFMT3_FMT_MAP420_MEMORY_CONTROL_BASE_IDX 2
// addressBlock: dce_dc_opp_oppbuf3_dispdec
// base address: 0x438
#define mmOPPBUF3_OPPBUF_CONTROL 0x1992
#define mmOPPBUF3_OPPBUF_CONTROL_BASE_IDX 2
#define mmOPPBUF3_OPPBUF_3D_PARAMETERS_0 0x1993
#define mmOPPBUF3_OPPBUF_3D_PARAMETERS_0_BASE_IDX 2
#define mmOPPBUF3_OPPBUF_3D_PARAMETERS_1 0x1994
#define mmOPPBUF3_OPPBUF_3D_PARAMETERS_1_BASE_IDX 2
// addressBlock: dce_dc_opp_opp_pipe3_dispdec
// base address: 0x438
#define mmOPP_PIPE3_OPP_PIPE_CONTROL 0x199a
#define mmOPP_PIPE3_OPP_PIPE_CONTROL_BASE_IDX 2
// addressBlock: dce_dc_opp_opp_pipe_crc3_dispdec
// base address: 0x438
#define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL 0x199f
#define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL_BASE_IDX 2
#define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_MASK 0x19a0
#define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_MASK_BASE_IDX 2
#define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0 0x19a1
#define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0_BASE_IDX 2
#define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1 0x19a2
#define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1_BASE_IDX 2
#define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT2 0x19a3
#define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT2_BASE_IDX 2
// addressBlock: dce_dc_opp_fmt4_dispdec
// base address: 0x5a0
#define mmFMT4_FMT_CLAMP_COMPONENT_R 0x19a4
#define mmFMT4_FMT_CLAMP_COMPONENT_R_BASE_IDX 2
#define mmFMT4_FMT_CLAMP_COMPONENT_G 0x19a5
#define mmFMT4_FMT_CLAMP_COMPONENT_G_BASE_IDX 2
#define mmFMT4_FMT_CLAMP_COMPONENT_B 0x19a6
#define mmFMT4_FMT_CLAMP_COMPONENT_B_BASE_IDX 2
#define mmFMT4_FMT_DYNAMIC_EXP_CNTL 0x19a7
#define mmFMT4_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2
#define mmFMT4_FMT_CONTROL 0x19a8
#define mmFMT4_FMT_CONTROL_BASE_IDX 2
#define mmFMT4_FMT_BIT_DEPTH_CONTROL 0x19a9
#define mmFMT4_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2
#define mmFMT4_FMT_DITHER_RAND_R_SEED 0x19aa
#define mmFMT4_FMT_DITHER_RAND_R_SEED_BASE_IDX 2
#define mmFMT4_FMT_DITHER_RAND_G_SEED 0x19ab
#define mmFMT4_FMT_DITHER_RAND_G_SEED_BASE_IDX 2
#define mmFMT4_FMT_DITHER_RAND_B_SEED 0x19ac
#define mmFMT4_FMT_DITHER_RAND_B_SEED_BASE_IDX 2
#define mmFMT4_FMT_CLAMP_CNTL 0x19b0
#define mmFMT4_FMT_CLAMP_CNTL_BASE_IDX 2
#define mmFMT4_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x19b1
#define mmFMT4_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2
#define mmFMT4_FMT_MAP420_MEMORY_CONTROL 0x19b2
#define mmFMT4_FMT_MAP420_MEMORY_CONTROL_BASE_IDX 2
// addressBlock: dce_dc_opp_oppbuf4_dispdec
// base address: 0x5a0
#define mmOPPBUF4_OPPBUF_CONTROL 0x19ec
#define mmOPPBUF4_OPPBUF_CONTROL_BASE_IDX 2
#define mmOPPBUF4_OPPBUF_3D_PARAMETERS_0 0x19ed
#define mmOPPBUF4_OPPBUF_3D_PARAMETERS_0_BASE_IDX 2
#define mmOPPBUF4_OPPBUF_3D_PARAMETERS_1 0x19ee
#define mmOPPBUF4_OPPBUF_3D_PARAMETERS_1_BASE_IDX 2
// addressBlock: dce_dc_opp_opp_pipe4_dispdec
// base address: 0x5a0
#define mmOPP_PIPE4_OPP_PIPE_CONTROL 0x19f4
#define mmOPP_PIPE4_OPP_PIPE_CONTROL_BASE_IDX 2
// addressBlock: dce_dc_opp_opp_pipe_crc4_dispdec
// base address: 0x5a0
#define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL 0x19f9
#define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL_BASE_IDX 2
#define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_MASK 0x19fa
#define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_MASK_BASE_IDX 2
#define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT0 0x19fb
#define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT0_BASE_IDX 2
#define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT1 0x19fc
#define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT1_BASE_IDX 2
#define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT2 0x19fd
#define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT2_BASE_IDX 2
// addressBlock: dce_dc_opp_fmt5_dispdec
// base address: 0x708
#define mmFMT5_FMT_CLAMP_COMPONENT_R 0x19fe
#define mmFMT5_FMT_CLAMP_COMPONENT_R_BASE_IDX 2
#define mmFMT5_FMT_CLAMP_COMPONENT_G 0x19ff
#define mmFMT5_FMT_CLAMP_COMPONENT_G_BASE_IDX 2
#define mmFMT5_FMT_CLAMP_COMPONENT_B 0x1a00
#define mmFMT5_FMT_CLAMP_COMPONENT_B_BASE_IDX 2
#define mmFMT5_FMT_DYNAMIC_EXP_CNTL 0x1a01
#define mmFMT5_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2
#define mmFMT5_FMT_CONTROL 0x1a02
#define mmFMT5_FMT_CONTROL_BASE_IDX 2
#define mmFMT5_FMT_BIT_DEPTH_CONTROL 0x1a03
#define mmFMT5_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2
#define mmFMT5_FMT_DITHER_RAND_R_SEED 0x1a04
#define mmFMT5_FMT_DITHER_RAND_R_SEED_BASE_IDX 2
#define mmFMT5_FMT_DITHER_RAND_G_SEED 0x1a05
#define mmFMT5_FMT_DITHER_RAND_G_SEED_BASE_IDX 2
#define mmFMT5_FMT_DITHER_RAND_B_SEED 0x1a06
#define mmFMT5_FMT_DITHER_RAND_B_SEED_BASE_IDX 2
#define mmFMT5_FMT_CLAMP_CNTL 0x1a0a
#define mmFMT5_FMT_CLAMP_CNTL_BASE_IDX 2
#define mmFMT5_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x1a0b
#define mmFMT5_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2
#define mmFMT5_FMT_MAP420_MEMORY_CONTROL 0x1a0c
#define mmFMT5_FMT_MAP420_MEMORY_CONTROL_BASE_IDX 2
// addressBlock: dce_dc_opp_oppbuf5_dispdec
// base address: 0x708
#define mmOPPBUF5_OPPBUF_CONTROL 0x1a46
#define mmOPPBUF5_OPPBUF_CONTROL_BASE_IDX 2
#define mmOPPBUF5_OPPBUF_3D_PARAMETERS_0 0x1a47
#define mmOPPBUF5_OPPBUF_3D_PARAMETERS_0_BASE_IDX 2
#define mmOPPBUF5_OPPBUF_3D_PARAMETERS_1 0x1a48
#define mmOPPBUF5_OPPBUF_3D_PARAMETERS_1_BASE_IDX 2
// addressBlock: dce_dc_opp_opp_pipe5_dispdec
// base address: 0x708
#define mmOPP_PIPE5_OPP_PIPE_CONTROL 0x1a4e
#define mmOPP_PIPE5_OPP_PIPE_CONTROL_BASE_IDX 2
// addressBlock: dce_dc_opp_opp_pipe_crc5_dispdec
// base address: 0x708
#define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL 0x1a53
#define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL_BASE_IDX 2
#define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_MASK 0x1a54
#define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_MASK_BASE_IDX 2
#define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT0 0x1a55
#define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT0_BASE_IDX 2
#define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT1 0x1a56
#define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT1_BASE_IDX 2
#define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT2 0x1a57
#define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT2_BASE_IDX 2
// addressBlock: dce_dc_opp_opp_top_dispdec
// base address: 0x0
#define mmOPP_TOP_CLK_CONTROL 0x1a5e
#define mmOPP_TOP_CLK_CONTROL_BASE_IDX 2
// addressBlock: dce_dc_opp_opp_dcperfmon_dc_perfmon_dispdec
// base address: 0x6af8
#define mmDC_PERFMON17_PERFCOUNTER_CNTL 0x1abe
#define mmDC_PERFMON17_PERFCOUNTER_CNTL_BASE_IDX 2
#define mmDC_PERFMON17_PERFCOUNTER_CNTL2 0x1abf
#define mmDC_PERFMON17_PERFCOUNTER_CNTL2_BASE_IDX 2
#define mmDC_PERFMON17_PERFCOUNTER_STATE 0x1ac0
#define mmDC_PERFMON17_PERFCOUNTER_STATE_BASE_IDX 2
#define mmDC_PERFMON17_PERFMON_CNTL 0x1ac1
#define mmDC_PERFMON17_PERFMON_CNTL_BASE_IDX 2
#define mmDC_PERFMON17_PERFMON_CNTL2 0x1ac2
#define mmDC_PERFMON17_PERFMON_CNTL2_BASE_IDX 2
#define mmDC_PERFMON17_PERFMON_CVALUE_INT_MISC 0x1ac3
#define mmDC_PERFMON17_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
#define mmDC_PERFMON17_PERFMON_CVALUE_LOW 0x1ac4
#define mmDC_PERFMON17_PERFMON_CVALUE_LOW_BASE_IDX 2
#define mmDC_PERFMON17_PERFMON_HI 0x1ac5
#define mmDC_PERFMON17_PERFMON_HI_BASE_IDX 2
#define mmDC_PERFMON17_PERFMON_LOW 0x1ac6
#define mmDC_PERFMON17_PERFMON_LOW_BASE_IDX 2
// addressBlock: dce_dc_optc_odm0_dispdec
// base address: 0x0
#define mmODM0_OPTC_INPUT_GLOBAL_CONTROL 0x1aca
#define mmODM0_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX 2
#define mmODM0_OPTC_DATA_SOURCE_SELECT 0x1acb
#define mmODM0_OPTC_DATA_SOURCE_SELECT_BASE_IDX 2
#define mmODM0_OPTC_INPUT_CLOCK_CONTROL 0x1acd
#define mmODM0_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX 2
#define mmODM0_OPTC_INPUT_SPARE_REGISTER 0x1acf
#define mmODM0_OPTC_INPUT_SPARE_REGISTER_BASE_IDX 2
// addressBlock: dce_dc_optc_odm1_dispdec
// base address: 0x40
#define mmODM1_OPTC_INPUT_GLOBAL_CONTROL 0x1ada
#define mmODM1_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX 2
#define mmODM1_OPTC_DATA_SOURCE_SELECT 0x1adb
#define mmODM1_OPTC_DATA_SOURCE_SELECT_BASE_IDX 2
#define mmODM1_OPTC_INPUT_CLOCK_CONTROL 0x1add
#define mmODM1_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX 2
#define mmODM1_OPTC_INPUT_SPARE_REGISTER 0x1adf
#define mmODM1_OPTC_INPUT_SPARE_REGISTER_BASE_IDX 2
// addressBlock: dce_dc_optc_odm2_dispdec
// base address: 0x80
#define mmODM2_OPTC_INPUT_GLOBAL_CONTROL 0x1aea
#define mmODM2_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX 2
#define mmODM2_OPTC_DATA_SOURCE_SELECT 0x1aeb
#define mmODM2_OPTC_DATA_SOURCE_SELECT_BASE_IDX 2
#define mmODM2_OPTC_INPUT_CLOCK_CONTROL 0x1aed
#define mmODM2_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX 2
#define mmODM2_OPTC_INPUT_SPARE_REGISTER 0x1aef
#define mmODM2_OPTC_INPUT_SPARE_REGISTER_BASE_IDX 2
// addressBlock: dce_dc_optc_odm3_dispdec
// base address: 0xc0
#define mmODM3_OPTC_INPUT_GLOBAL_CONTROL 0x1afa
#define mmODM3_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX 2
#define mmODM3_OPTC_DATA_SOURCE_SELECT 0x1afb
#define mmODM3_OPTC_DATA_SOURCE_SELECT_BASE_IDX 2
#define mmODM3_OPTC_INPUT_CLOCK_CONTROL 0x1afd
#define mmODM3_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX 2
#define mmODM3_OPTC_INPUT_SPARE_REGISTER 0x1aff
#define mmODM3_OPTC_INPUT_SPARE_REGISTER_BASE_IDX 2
// addressBlock: dce_dc_optc_odm4_dispdec
// base address: 0x100
#define mmODM4_OPTC_INPUT_GLOBAL_CONTROL 0x1b0a
#define mmODM4_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX 2
#define mmODM4_OPTC_DATA_SOURCE_SELECT 0x1b0b
#define mmODM4_OPTC_DATA_SOURCE_SELECT_BASE_IDX 2
#define mmODM4_OPTC_INPUT_CLOCK_CONTROL 0x1b0d
#define mmODM4_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX 2
#define mmODM4_OPTC_INPUT_SPARE_REGISTER 0x1b0f
#define mmODM4_OPTC_INPUT_SPARE_REGISTER_BASE_IDX 2
// addressBlock: dce_dc_optc_odm5_dispdec
// base address: 0x140
#define mmODM5_OPTC_INPUT_GLOBAL_CONTROL 0x1b1a
#define mmODM5_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX 2
#define mmODM5_OPTC_DATA_SOURCE_SELECT 0x1b1b
#define mmODM5_OPTC_DATA_SOURCE_SELECT_BASE_IDX 2
#define mmODM5_OPTC_INPUT_CLOCK_CONTROL 0x1b1d
#define mmODM5_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX 2
#define mmODM5_OPTC_INPUT_SPARE_REGISTER 0x1b1f
#define mmODM5_OPTC_INPUT_SPARE_REGISTER_BASE_IDX 2
// addressBlock: dce_dc_optc_otg0_dispdec
// base address: 0x0
#define mmOTG0_OTG_H_TOTAL 0x1b2a
#define mmOTG0_OTG_H_TOTAL_BASE_IDX 2
#define mmOTG0_OTG_H_BLANK_START_END 0x1b2b
#define mmOTG0_OTG_H_BLANK_START_END_BASE_IDX 2
#define mmOTG0_OTG_H_SYNC_A 0x1b2c
#define mmOTG0_OTG_H_SYNC_A_BASE_IDX 2
#define mmOTG0_OTG_H_SYNC_A_CNTL 0x1b2d
#define mmOTG0_OTG_H_SYNC_A_CNTL_BASE_IDX 2
#define mmOTG0_OTG_H_TIMING_CNTL 0x1b2e
#define mmOTG0_OTG_H_TIMING_CNTL_BASE_IDX 2
#define mmOTG0_OTG_V_TOTAL 0x1b2f
#define mmOTG0_OTG_V_TOTAL_BASE_IDX 2
#define mmOTG0_OTG_V_TOTAL_MIN 0x1b30
#define mmOTG0_OTG_V_TOTAL_MIN_BASE_IDX 2
#define mmOTG0_OTG_V_TOTAL_MAX 0x1b31
#define mmOTG0_OTG_V_TOTAL_MAX_BASE_IDX 2
#define mmOTG0_OTG_V_TOTAL_MID 0x1b32
#define mmOTG0_OTG_V_TOTAL_MID_BASE_IDX 2
#define mmOTG0_OTG_V_TOTAL_CONTROL 0x1b33
#define mmOTG0_OTG_V_TOTAL_CONTROL_BASE_IDX 2
#define mmOTG0_OTG_V_TOTAL_INT_STATUS 0x1b34
#define mmOTG0_OTG_V_TOTAL_INT_STATUS_BASE_IDX 2
#define mmOTG0_OTG_VSYNC_NOM_INT_STATUS 0x1b35
#define mmOTG0_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX 2
#define mmOTG0_OTG_V_BLANK_START_END 0x1b36
#define mmOTG0_OTG_V_BLANK_START_END_BASE_IDX 2
#define mmOTG0_OTG_V_SYNC_A 0x1b37
#define mmOTG0_OTG_V_SYNC_A_BASE_IDX 2
#define mmOTG0_OTG_V_SYNC_A_CNTL 0x1b38
#define mmOTG0_OTG_V_SYNC_A_CNTL_BASE_IDX 2
#define mmOTG0_OTG_TRIGA_CNTL 0x1b39
#define mmOTG0_OTG_TRIGA_CNTL_BASE_IDX 2
#define mmOTG0_OTG_TRIGA_MANUAL_TRIG 0x1b3a
#define mmOTG0_OTG_TRIGA_MANUAL_TRIG_BASE_IDX 2
#define mmOTG0_OTG_TRIGB_CNTL 0x1b3b
#define mmOTG0_OTG_TRIGB_CNTL_BASE_IDX 2
#define mmOTG0_OTG_TRIGB_MANUAL_TRIG 0x1b3c
#define mmOTG0_OTG_TRIGB_MANUAL_TRIG_BASE_IDX 2
#define mmOTG0_OTG_FORCE_COUNT_NOW_CNTL 0x1b3d
#define mmOTG0_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX 2
#define mmOTG0_OTG_FLOW_CONTROL 0x1b3e
#define mmOTG0_OTG_FLOW_CONTROL_BASE_IDX 2
#define mmOTG0_OTG_STEREO_FORCE_NEXT_EYE 0x1b3f
#define mmOTG0_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX 2
#define mmOTG0_OTG_AVSYNC_COUNTER 0x1b40
#define mmOTG0_OTG_AVSYNC_COUNTER_BASE_IDX 2
#define mmOTG0_OTG_CONTROL 0x1b41
#define mmOTG0_OTG_CONTROL_BASE_IDX 2
#define mmOTG0_OTG_BLANK_CONTROL 0x1b42
#define mmOTG0_OTG_BLANK_CONTROL_BASE_IDX 2
#define mmOTG0_OTG_PIPE_ABORT_CONTROL 0x1b43
#define mmOTG0_OTG_PIPE_ABORT_CONTROL_BASE_IDX 2
#define mmOTG0_OTG_INTERLACE_CONTROL 0x1b44
#define mmOTG0_OTG_INTERLACE_CONTROL_BASE_IDX 2
#define mmOTG0_OTG_INTERLACE_STATUS 0x1b45
#define mmOTG0_OTG_INTERLACE_STATUS_BASE_IDX 2
#define mmOTG0_OTG_FIELD_INDICATION_CONTROL 0x1b46
#define mmOTG0_OTG_FIELD_INDICATION_CONTROL_BASE_IDX 2
#define mmOTG0_OTG_PIXEL_DATA_READBACK0 0x1b47
#define mmOTG0_OTG_PIXEL_DATA_READBACK0_BASE_IDX 2
#define mmOTG0_OTG_PIXEL_DATA_READBACK1 0x1b48
#define mmOTG0_OTG_PIXEL_DATA_READBACK1_BASE_IDX 2
#define mmOTG0_OTG_STATUS 0x1b49
#define mmOTG0_OTG_STATUS_BASE_IDX 2
#define mmOTG0_OTG_STATUS_POSITION 0x1b4a
#define mmOTG0_OTG_STATUS_POSITION_BASE_IDX 2
#define mmOTG0_OTG_NOM_VERT_POSITION 0x1b4b
#define mmOTG0_OTG_NOM_VERT_POSITION_BASE_IDX 2
#define mmOTG0_OTG_STATUS_FRAME_COUNT 0x1b4c
#define mmOTG0_OTG_STATUS_FRAME_COUNT_BASE_IDX 2
#define mmOTG0_OTG_STATUS_VF_COUNT 0x1b4d
#define mmOTG0_OTG_STATUS_VF_COUNT_BASE_IDX 2
#define mmOTG0_OTG_STATUS_HV_COUNT 0x1b4e
#define mmOTG0_OTG_STATUS_HV_COUNT_BASE_IDX 2
#define mmOTG0_OTG_COUNT_CONTROL 0x1b4f
#define mmOTG0_OTG_COUNT_CONTROL_BASE_IDX 2
#define mmOTG0_OTG_COUNT_RESET 0x1b50
#define mmOTG0_OTG_COUNT_RESET_BASE_IDX 2
#define mmOTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1b51
#define mmOTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2
#define mmOTG0_OTG_VERT_SYNC_CONTROL 0x1b52
#define mmOTG0_OTG_VERT_SYNC_CONTROL_BASE_IDX 2
#define mmOTG0_OTG_STEREO_STATUS 0x1b53
#define mmOTG0_OTG_STEREO_STATUS_BASE_IDX 2
#define mmOTG0_OTG_STEREO_CONTROL 0x1b54
#define mmOTG0_OTG_STEREO_CONTROL_BASE_IDX 2
#define mmOTG0_OTG_SNAPSHOT_STATUS 0x1b55
#define mmOTG0_OTG_SNAPSHOT_STATUS_BASE_IDX 2
#define mmOTG0_OTG_SNAPSHOT_CONTROL 0x1b56
#define mmOTG0_OTG_SNAPSHOT_CONTROL_BASE_IDX 2
#define mmOTG0_OTG_SNAPSHOT_POSITION 0x1b57
#define mmOTG0_OTG_SNAPSHOT_POSITION_BASE_IDX 2
#define mmOTG0_OTG_SNAPSHOT_FRAME 0x1b58
#define mmOTG0_OTG_SNAPSHOT_FRAME_BASE_IDX 2
#define mmOTG0_OTG_INTERRUPT_CONTROL 0x1b59
#define mmOTG0_OTG_INTERRUPT_CONTROL_BASE_IDX 2
#define mmOTG0_OTG_UPDATE_LOCK 0x1b5a
#define mmOTG0_OTG_UPDATE_LOCK_BASE_IDX 2
#define mmOTG0_OTG_DOUBLE_BUFFER_CONTROL 0x1b5b
#define mmOTG0_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX 2
#define mmOTG0_OTG_TEST_PATTERN_CONTROL 0x1b5c
#define mmOTG0_OTG_TEST_PATTERN_CONTROL_BASE_IDX 2
#define mmOTG0_OTG_TEST_PATTERN_PARAMETERS 0x1b5d
#define mmOTG0_OTG_TEST_PATTERN_PARAMETERS_BASE_IDX 2
#define mmOTG0_OTG_TEST_PATTERN_COLOR 0x1b5e
#define mmOTG0_OTG_TEST_PATTERN_COLOR_BASE_IDX 2
#define mmOTG0_OTG_MASTER_EN 0x1b5f
#define mmOTG0_OTG_MASTER_EN_BASE_IDX 2
#define mmOTG0_OTG_BLANK_DATA_COLOR 0x1b61
#define mmOTG0_OTG_BLANK_DATA_COLOR_BASE_IDX 2
#define mmOTG0_OTG_BLANK_DATA_COLOR_EXT 0x1b62
#define mmOTG0_OTG_BLANK_DATA_COLOR_EXT_BASE_IDX 2
#define mmOTG0_OTG_BLACK_COLOR 0x1b63
#define mmOTG0_OTG_BLACK_COLOR_BASE_IDX 2
#define mmOTG0_OTG_BLACK_COLOR_EXT 0x1b64
#define mmOTG0_OTG_BLACK_COLOR_EXT_BASE_IDX 2
#define mmOTG0_OTG_VERTICAL_INTERRUPT0_POSITION 0x1b65
#define mmOTG0_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2
#define mmOTG0_OTG_VERTICAL_INTERRUPT0_CONTROL 0x1b66
#define mmOTG0_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2
#define mmOTG0_OTG_VERTICAL_INTERRUPT1_POSITION 0x1b67
#define mmOTG0_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2
#define mmOTG0_OTG_VERTICAL_INTERRUPT1_CONTROL 0x1b68
#define mmOTG0_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2
#define mmOTG0_OTG_VERTICAL_INTERRUPT2_POSITION 0x1b69
#define mmOTG0_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2
#define mmOTG0_OTG_VERTICAL_INTERRUPT2_CONTROL 0x1b6a
#define mmOTG0_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2
#define mmOTG0_OTG_CRC_CNTL 0x1b6b
#define mmOTG0_OTG_CRC_CNTL_BASE_IDX 2
#define mmOTG0_OTG_CRC0_WINDOWA_X_CONTROL 0x1b6c
#define mmOTG0_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2
#define mmOTG0_OTG_CRC0_WINDOWA_Y_CONTROL 0x1b6d
#define mmOTG0_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2
#define mmOTG0_OTG_CRC0_WINDOWB_X_CONTROL 0x1b6e
#define mmOTG0_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2
#define mmOTG0_OTG_CRC0_WINDOWB_Y_CONTROL 0x1b6f
#define mmOTG0_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2
#define mmOTG0_OTG_CRC0_DATA_RG 0x1b70
#define mmOTG0_OTG_CRC0_DATA_RG_BASE_IDX 2
#define mmOTG0_OTG_CRC0_DATA_B 0x1b71
#define mmOTG0_OTG_CRC0_DATA_B_BASE_IDX 2
#define mmOTG0_OTG_CRC1_WINDOWA_X_CONTROL 0x1b72
#define mmOTG0_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2
#define mmOTG0_OTG_CRC1_WINDOWA_Y_CONTROL 0x1b73
#define mmOTG0_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2
#define mmOTG0_OTG_CRC1_WINDOWB_X_CONTROL 0x1b74
#define mmOTG0_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2
#define mmOTG0_OTG_CRC1_WINDOWB_Y_CONTROL 0x1b75
#define mmOTG0_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2
#define mmOTG0_OTG_CRC1_DATA_RG 0x1b76
#define mmOTG0_OTG_CRC1_DATA_RG_BASE_IDX 2
#define mmOTG0_OTG_CRC1_DATA_B 0x1b77
#define mmOTG0_OTG_CRC1_DATA_B_BASE_IDX 2
#define mmOTG0_OTG_CRC2_DATA_RG 0x1b78
#define mmOTG0_OTG_CRC2_DATA_RG_BASE_IDX 2
#define mmOTG0_OTG_CRC2_DATA_B 0x1b79
#define mmOTG0_OTG_CRC2_DATA_B_BASE_IDX 2
#define mmOTG0_OTG_CRC3_DATA_RG 0x1b7a
#define mmOTG0_OTG_CRC3_DATA_RG_BASE_IDX 2
#define mmOTG0_OTG_CRC3_DATA_B 0x1b7b
#define mmOTG0_OTG_CRC3_DATA_B_BASE_IDX 2
#define mmOTG0_OTG_CRC_SIG_RED_GREEN_MASK 0x1b7c
#define mmOTG0_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2
#define mmOTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK 0x1b7d
#define mmOTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2
#define mmOTG0_OTG_STATIC_SCREEN_CONTROL 0x1b84
#define mmOTG0_OTG_STATIC_SCREEN_CONTROL_BASE_IDX 2
#define mmOTG0_OTG_3D_STRUCTURE_CONTROL 0x1b85
#define mmOTG0_OTG_3D_STRUCTURE_CONTROL_BASE_IDX 2
#define mmOTG0_OTG_GSL_VSYNC_GAP 0x1b86
#define mmOTG0_OTG_GSL_VSYNC_GAP_BASE_IDX 2
#define mmOTG0_OTG_MASTER_UPDATE_MODE 0x1b87
#define mmOTG0_OTG_MASTER_UPDATE_MODE_BASE_IDX 2
#define mmOTG0_OTG_CLOCK_CONTROL 0x1b88
#define mmOTG0_OTG_CLOCK_CONTROL_BASE_IDX 2
#define mmOTG0_OTG_VSTARTUP_PARAM 0x1b89
#define mmOTG0_OTG_VSTARTUP_PARAM_BASE_IDX 2
#define mmOTG0_OTG_VUPDATE_PARAM 0x1b8a
#define mmOTG0_OTG_VUPDATE_PARAM_BASE_IDX 2
#define mmOTG0_OTG_VREADY_PARAM 0x1b8b
#define mmOTG0_OTG_VREADY_PARAM_BASE_IDX 2
#define mmOTG0_OTG_GLOBAL_SYNC_STATUS 0x1b8c
#define mmOTG0_OTG_GLOBAL_SYNC_STATUS_BASE_IDX 2
#define mmOTG0_OTG_MASTER_UPDATE_LOCK 0x1b8d
#define mmOTG0_OTG_MASTER_UPDATE_LOCK_BASE_IDX 2
#define mmOTG0_OTG_GSL_CONTROL 0x1b8e
#define mmOTG0_OTG_GSL_CONTROL_BASE_IDX 2
#define mmOTG0_OTG_GSL_WINDOW_X 0x1b8f
#define mmOTG0_OTG_GSL_WINDOW_X_BASE_IDX 2
#define mmOTG0_OTG_GSL_WINDOW_Y 0x1b90
#define mmOTG0_OTG_GSL_WINDOW_Y_BASE_IDX 2
#define mmOTG0_OTG_VUPDATE_KEEPOUT 0x1b91
#define mmOTG0_OTG_VUPDATE_KEEPOUT_BASE_IDX 2
#define mmOTG0_OTG_GLOBAL_CONTROL0 0x1b92
#define mmOTG0_OTG_GLOBAL_CONTROL0_BASE_IDX 2
#define mmOTG0_OTG_GLOBAL_CONTROL1 0x1b93
#define mmOTG0_OTG_GLOBAL_CONTROL1_BASE_IDX 2
#define mmOTG0_OTG_GLOBAL_CONTROL2 0x1b94
#define mmOTG0_OTG_GLOBAL_CONTROL2_BASE_IDX 2
#define mmOTG0_OTG_GLOBAL_CONTROL3 0x1b95
#define mmOTG0_OTG_GLOBAL_CONTROL3_BASE_IDX 2
#define mmOTG0_OTG_TRIG_MANUAL_CONTROL 0x1b96
#define mmOTG0_OTG_TRIG_MANUAL_CONTROL_BASE_IDX 2
#define mmOTG0_OTG_MANUAL_FLOW_CONTROL 0x1b97
#define mmOTG0_OTG_MANUAL_FLOW_CONTROL_BASE_IDX 2
#define mmOTG0_OTG_RANGE_TIMING_INT_STATUS 0x1b98
#define mmOTG0_OTG_RANGE_TIMING_INT_STATUS_BASE_IDX 2
#define mmOTG0_OTG_DRR_CONTROL 0x1b99
#define mmOTG0_OTG_DRR_CONTROL_BASE_IDX 2
#define mmOTG0_OTG_REQUEST_CONTROL 0x1b9a
#define mmOTG0_OTG_REQUEST_CONTROL_BASE_IDX 2
#define mmOTG0_OTG_SPARE_REGISTER 0x1b9b
#define mmOTG0_OTG_SPARE_REGISTER_BASE_IDX 2
// addressBlock: dce_dc_optc_otg1_dispdec
// base address: 0x200
#define mmOTG1_OTG_H_TOTAL 0x1baa
#define mmOTG1_OTG_H_TOTAL_BASE_IDX 2
#define mmOTG1_OTG_H_BLANK_START_END 0x1bab
#define mmOTG1_OTG_H_BLANK_START_END_BASE_IDX 2
#define mmOTG1_OTG_H_SYNC_A 0x1bac
#define mmOTG1_OTG_H_SYNC_A_BASE_IDX 2
#define mmOTG1_OTG_H_SYNC_A_CNTL 0x1bad
#define mmOTG1_OTG_H_SYNC_A_CNTL_BASE_IDX 2
#define mmOTG1_OTG_H_TIMING_CNTL 0x1bae
#define mmOTG1_OTG_H_TIMING_CNTL_BASE_IDX 2
#define mmOTG1_OTG_V_TOTAL 0x1baf
#define mmOTG1_OTG_V_TOTAL_BASE_IDX 2
#define mmOTG1_OTG_V_TOTAL_MIN 0x1bb0
#define mmOTG1_OTG_V_TOTAL_MIN_BASE_IDX 2
#define mmOTG1_OTG_V_TOTAL_MAX 0x1bb1
#define mmOTG1_OTG_V_TOTAL_MAX_BASE_IDX 2
#define mmOTG1_OTG_V_TOTAL_MID 0x1bb2
#define mmOTG1_OTG_V_TOTAL_MID_BASE_IDX 2
#define mmOTG1_OTG_V_TOTAL_CONTROL 0x1bb3
#define mmOTG1_OTG_V_TOTAL_CONTROL_BASE_IDX 2
#define mmOTG1_OTG_V_TOTAL_INT_STATUS 0x1bb4
#define mmOTG1_OTG_V_TOTAL_INT_STATUS_BASE_IDX 2
#define mmOTG1_OTG_VSYNC_NOM_INT_STATUS 0x1bb5
#define mmOTG1_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX 2
#define mmOTG1_OTG_V_BLANK_START_END 0x1bb6
#define mmOTG1_OTG_V_BLANK_START_END_BASE_IDX 2
#define mmOTG1_OTG_V_SYNC_A 0x1bb7
#define mmOTG1_OTG_V_SYNC_A_BASE_IDX 2
#define mmOTG1_OTG_V_SYNC_A_CNTL 0x1bb8
#define mmOTG1_OTG_V_SYNC_A_CNTL_BASE_IDX 2
#define mmOTG1_OTG_TRIGA_CNTL 0x1bb9
#define mmOTG1_OTG_TRIGA_CNTL_BASE_IDX 2
#define mmOTG1_OTG_TRIGA_MANUAL_TRIG 0x1bba
#define mmOTG1_OTG_TRIGA_MANUAL_TRIG_BASE_IDX 2
#define mmOTG1_OTG_TRIGB_CNTL 0x1bbb
#define mmOTG1_OTG_TRIGB_CNTL_BASE_IDX 2
#define mmOTG1_OTG_TRIGB_MANUAL_TRIG 0x1bbc
#define mmOTG1_OTG_TRIGB_MANUAL_TRIG_BASE_IDX 2
#define mmOTG1_OTG_FORCE_COUNT_NOW_CNTL 0x1bbd
#define mmOTG1_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX 2
#define mmOTG1_OTG_FLOW_CONTROL 0x1bbe
#define mmOTG1_OTG_FLOW_CONTROL_BASE_IDX 2
#define mmOTG1_OTG_STEREO_FORCE_NEXT_EYE 0x1bbf
#define mmOTG1_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX 2
#define mmOTG1_OTG_AVSYNC_COUNTER 0x1bc0
#define mmOTG1_OTG_AVSYNC_COUNTER_BASE_IDX 2
#define mmOTG1_OTG_CONTROL 0x1bc1
#define mmOTG1_OTG_CONTROL_BASE_IDX 2
#define mmOTG1_OTG_BLANK_CONTROL 0x1bc2
#define mmOTG1_OTG_BLANK_CONTROL_BASE_IDX 2
#define mmOTG1_OTG_PIPE_ABORT_CONTROL 0x1bc3
#define mmOTG1_OTG_PIPE_ABORT_CONTROL_BASE_IDX 2
#define mmOTG1_OTG_INTERLACE_CONTROL 0x1bc4
#define mmOTG1_OTG_INTERLACE_CONTROL_BASE_IDX 2
#define mmOTG1_OTG_INTERLACE_STATUS 0x1bc5
#define mmOTG1_OTG_INTERLACE_STATUS_BASE_IDX 2
#define mmOTG1_OTG_FIELD_INDICATION_CONTROL 0x1bc6
#define mmOTG1_OTG_FIELD_INDICATION_CONTROL_BASE_IDX 2
#define mmOTG1_OTG_PIXEL_DATA_READBACK0 0x1bc7
#define mmOTG1_OTG_PIXEL_DATA_READBACK0_BASE_IDX 2
#define mmOTG1_OTG_PIXEL_DATA_READBACK1 0x1bc8
#define mmOTG1_OTG_PIXEL_DATA_READBACK1_BASE_IDX 2
#define mmOTG1_OTG_STATUS 0x1bc9
#define mmOTG1_OTG_STATUS_BASE_IDX 2
#define mmOTG1_OTG_STATUS_POSITION 0x1bca
#define mmOTG1_OTG_STATUS_POSITION_BASE_IDX 2
#define mmOTG1_OTG_NOM_VERT_POSITION 0x1bcb
#define mmOTG1_OTG_NOM_VERT_POSITION_BASE_IDX 2
#define mmOTG1_OTG_STATUS_FRAME_COUNT 0x1bcc
#define mmOTG1_OTG_STATUS_FRAME_COUNT_BASE_IDX 2
#define mmOTG1_OTG_STATUS_VF_COUNT 0x1bcd
#define mmOTG1_OTG_STATUS_VF_COUNT_BASE_IDX 2
#define mmOTG1_OTG_STATUS_HV_COUNT 0x1bce
#define mmOTG1_OTG_STATUS_HV_COUNT_BASE_IDX 2
#define mmOTG1_OTG_COUNT_CONTROL 0x1bcf
#define mmOTG1_OTG_COUNT_CONTROL_BASE_IDX 2
#define mmOTG1_OTG_COUNT_RESET 0x1bd0
#define mmOTG1_OTG_COUNT_RESET_BASE_IDX 2
#define mmOTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1bd1
#define mmOTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2
#define mmOTG1_OTG_VERT_SYNC_CONTROL 0x1bd2
#define mmOTG1_OTG_VERT_SYNC_CONTROL_BASE_IDX 2
#define mmOTG1_OTG_STEREO_STATUS 0x1bd3
#define mmOTG1_OTG_STEREO_STATUS_BASE_IDX 2
#define mmOTG1_OTG_STEREO_CONTROL 0x1bd4
#define mmOTG1_OTG_STEREO_CONTROL_BASE_IDX 2
#define mmOTG1_OTG_SNAPSHOT_STATUS 0x1bd5
#define mmOTG1_OTG_SNAPSHOT_STATUS_BASE_IDX 2
#define mmOTG1_OTG_SNAPSHOT_CONTROL 0x1bd6
#define mmOTG1_OTG_SNAPSHOT_CONTROL_BASE_IDX 2
#define mmOTG1_OTG_SNAPSHOT_POSITION 0x1bd7
#define mmOTG1_OTG_SNAPSHOT_POSITION_BASE_IDX 2
#define mmOTG1_OTG_SNAPSHOT_FRAME 0x1bd8
#define mmOTG1_OTG_SNAPSHOT_FRAME_BASE_IDX 2
#define mmOTG1_OTG_INTERRUPT_CONTROL 0x1bd9
#define mmOTG1_OTG_INTERRUPT_CONTROL_BASE_IDX 2
#define mmOTG1_OTG_UPDATE_LOCK 0x1bda
#define mmOTG1_OTG_UPDATE_LOCK_BASE_IDX 2
#define mmOTG1_OTG_DOUBLE_BUFFER_CONTROL 0x1bdb
#define mmOTG1_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX 2
#define mmOTG1_OTG_TEST_PATTERN_CONTROL 0x1bdc
#define mmOTG1_OTG_TEST_PATTERN_CONTROL_BASE_IDX 2
#define mmOTG1_OTG_TEST_PATTERN_PARAMETERS 0x1bdd
#define mmOTG1_OTG_TEST_PATTERN_PARAMETERS_BASE_IDX 2
#define mmOTG1_OTG_TEST_PATTERN_COLOR 0x1bde
#define mmOTG1_OTG_TEST_PATTERN_COLOR_BASE_IDX 2
#define mmOTG1_OTG_MASTER_EN 0x1bdf
#define mmOTG1_OTG_MASTER_EN_BASE_IDX 2
#define mmOTG1_OTG_BLANK_DATA_COLOR 0x1be1
#define mmOTG1_OTG_BLANK_DATA_COLOR_BASE_IDX 2
#define mmOTG1_OTG_BLANK_DATA_COLOR_EXT 0x1be2
#define mmOTG1_OTG_BLANK_DATA_COLOR_EXT_BASE_IDX 2
#define mmOTG1_OTG_BLACK_COLOR 0x1be3
#define mmOTG1_OTG_BLACK_COLOR_BASE_IDX 2
#define mmOTG1_OTG_BLACK_COLOR_EXT 0x1be4
#define mmOTG1_OTG_BLACK_COLOR_EXT_BASE_IDX 2
#define mmOTG1_OTG_VERTICAL_INTERRUPT0_POSITION 0x1be5
#define mmOTG1_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2
#define mmOTG1_OTG_VERTICAL_INTERRUPT0_CONTROL 0x1be6
#define mmOTG1_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2
#define mmOTG1_OTG_VERTICAL_INTERRUPT1_POSITION 0x1be7
#define mmOTG1_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2
#define mmOTG1_OTG_VERTICAL_INTERRUPT1_CONTROL 0x1be8
#define mmOTG1_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2
#define mmOTG1_OTG_VERTICAL_INTERRUPT2_POSITION 0x1be9
#define mmOTG1_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2
#define mmOTG1_OTG_VERTICAL_INTERRUPT2_CONTROL 0x1bea
#define mmOTG1_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2
#define mmOTG1_OTG_CRC_CNTL 0x1beb
#define mmOTG1_OTG_CRC_CNTL_BASE_IDX 2
#define mmOTG1_OTG_CRC0_WINDOWA_X_CONTROL 0x1bec
#define mmOTG1_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2
#define mmOTG1_OTG_CRC0_WINDOWA_Y_CONTROL 0x1bed
#define mmOTG1_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2
#define mmOTG1_OTG_CRC0_WINDOWB_X_CONTROL 0x1bee
#define mmOTG1_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2
#define mmOTG1_OTG_CRC0_WINDOWB_Y_CONTROL 0x1bef
#define mmOTG1_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2
#define mmOTG1_OTG_CRC0_DATA_RG 0x1bf0
#define mmOTG1_OTG_CRC0_DATA_RG_BASE_IDX 2
#define mmOTG1_OTG_CRC0_DATA_B 0x1bf1
#define mmOTG1_OTG_CRC0_DATA_B_BASE_IDX 2
#define mmOTG1_OTG_CRC1_WINDOWA_X_CONTROL 0x1bf2
#define mmOTG1_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2
#define mmOTG1_OTG_CRC1_WINDOWA_Y_CONTROL 0x1bf3
#define mmOTG1_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2
#define mmOTG1_OTG_CRC1_WINDOWB_X_CONTROL 0x1bf4
#define mmOTG1_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2
#define mmOTG1_OTG_CRC1_WINDOWB_Y_CONTROL 0x1bf5
#define mmOTG1_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2
#define mmOTG1_OTG_CRC1_DATA_RG 0x1bf6
#define mmOTG1_OTG_CRC1_DATA_RG_BASE_IDX 2
#define mmOTG1_OTG_CRC1_DATA_B 0x1bf7
#define mmOTG1_OTG_CRC1_DATA_B_BASE_IDX 2
#define mmOTG1_OTG_CRC2_DATA_RG 0x1bf8
#define mmOTG1_OTG_CRC2_DATA_RG_BASE_IDX 2
#define mmOTG1_OTG_CRC2_DATA_B 0x1bf9
#define mmOTG1_OTG_CRC2_DATA_B_BASE_IDX 2
#define mmOTG1_OTG_CRC3_DATA_RG 0x1bfa
#define mmOTG1_OTG_CRC3_DATA_RG_BASE_IDX 2
#define mmOTG1_OTG_CRC3_DATA_B 0x1bfb
#define mmOTG1_OTG_CRC3_DATA_B_BASE_IDX 2
#define mmOTG1_OTG_CRC_SIG_RED_GREEN_MASK 0x1bfc
#define mmOTG1_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2
#define mmOTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK 0x1bfd
#define mmOTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2
#define mmOTG1_OTG_STATIC_SCREEN_CONTROL 0x1c04
#define mmOTG1_OTG_STATIC_SCREEN_CONTROL_BASE_IDX 2
#define mmOTG1_OTG_3D_STRUCTURE_CONTROL 0x1c05
#define mmOTG1_OTG_3D_STRUCTURE_CONTROL_BASE_IDX 2
#define mmOTG1_OTG_GSL_VSYNC_GAP 0x1c06
#define mmOTG1_OTG_GSL_VSYNC_GAP_BASE_IDX 2
#define mmOTG1_OTG_MASTER_UPDATE_MODE 0x1c07
#define mmOTG1_OTG_MASTER_UPDATE_MODE_BASE_IDX 2
#define mmOTG1_OTG_CLOCK_CONTROL 0x1c08
#define mmOTG1_OTG_CLOCK_CONTROL_BASE_IDX 2
#define mmOTG1_OTG_VSTARTUP_PARAM 0x1c09
#define mmOTG1_OTG_VSTARTUP_PARAM_BASE_IDX 2
#define mmOTG1_OTG_VUPDATE_PARAM 0x1c0a
#define mmOTG1_OTG_VUPDATE_PARAM_BASE_IDX 2
#define mmOTG1_OTG_VREADY_PARAM 0x1c0b
#define mmOTG1_OTG_VREADY_PARAM_BASE_IDX 2
#define mmOTG1_OTG_GLOBAL_SYNC_STATUS 0x1c0c
#define mmOTG1_OTG_GLOBAL_SYNC_STATUS_BASE_IDX 2
#define mmOTG1_OTG_MASTER_UPDATE_LOCK 0x1c0d
#define mmOTG1_OTG_MASTER_UPDATE_LOCK_BASE_IDX 2
#define mmOTG1_OTG_GSL_CONTROL 0x1c0e
#define mmOTG1_OTG_GSL_CONTROL_BASE_IDX 2
#define mmOTG1_OTG_GSL_WINDOW_X 0x1c0f
#define mmOTG1_OTG_GSL_WINDOW_X_BASE_IDX 2
#define mmOTG1_OTG_GSL_WINDOW_Y 0x1c10
#define mmOTG1_OTG_GSL_WINDOW_Y_BASE_IDX 2
#define mmOTG1_OTG_VUPDATE_KEEPOUT 0x1c11
#define mmOTG1_OTG_VUPDATE_KEEPOUT_BASE_IDX 2
#define mmOTG1_OTG_GLOBAL_CONTROL0 0x1c12
#define mmOTG1_OTG_GLOBAL_CONTROL0_BASE_IDX 2
#define mmOTG1_OTG_GLOBAL_CONTROL1 0x1c13
#define mmOTG1_OTG_GLOBAL_CONTROL1_BASE_IDX 2
#define mmOTG1_OTG_GLOBAL_CONTROL2 0x1c14
#define mmOTG1_OTG_GLOBAL_CONTROL2_BASE_IDX 2
#define mmOTG1_OTG_GLOBAL_CONTROL3 0x1c15
#define mmOTG1_OTG_GLOBAL_CONTROL3_BASE_IDX 2
#define mmOTG1_OTG_TRIG_MANUAL_CONTROL 0x1c16
#define mmOTG1_OTG_TRIG_MANUAL_CONTROL_BASE_IDX 2
#define mmOTG1_OTG_MANUAL_FLOW_CONTROL 0x1c17
#define mmOTG1_OTG_MANUAL_FLOW_CONTROL_BASE_IDX 2
#define mmOTG1_OTG_RANGE_TIMING_INT_STATUS 0x1c18
#define mmOTG1_OTG_RANGE_TIMING_INT_STATUS_BASE_IDX 2
#define mmOTG1_OTG_DRR_CONTROL 0x1c19
#define mmOTG1_OTG_DRR_CONTROL_BASE_IDX 2
#define mmOTG1_OTG_REQUEST_CONTROL 0x1c1a
#define mmOTG1_OTG_REQUEST_CONTROL_BASE_IDX 2
#define mmOTG1_OTG_SPARE_REGISTER 0x1c1b
#define mmOTG1_OTG_SPARE_REGISTER_BASE_IDX 2
// addressBlock: dce_dc_optc_otg2_dispdec
// base address: 0x400
#define mmOTG2_OTG_H_TOTAL 0x1c2a
#define mmOTG2_OTG_H_TOTAL_BASE_IDX 2
#define mmOTG2_OTG_H_BLANK_START_END 0x1c2b
#define mmOTG2_OTG_H_BLANK_START_END_BASE_IDX 2
#define mmOTG2_OTG_H_SYNC_A 0x1c2c
#define mmOTG2_OTG_H_SYNC_A_BASE_IDX 2
#define mmOTG2_OTG_H_SYNC_A_CNTL 0x1c2d
#define mmOTG2_OTG_H_SYNC_A_CNTL_BASE_IDX 2
#define mmOTG2_OTG_H_TIMING_CNTL 0x1c2e
#define mmOTG2_OTG_H_TIMING_CNTL_BASE_IDX 2
#define mmOTG2_OTG_V_TOTAL 0x1c2f
#define mmOTG2_OTG_V_TOTAL_BASE_IDX 2
#define mmOTG2_OTG_V_TOTAL_MIN 0x1c30
#define mmOTG2_OTG_V_TOTAL_MIN_BASE_IDX 2
#define mmOTG2_OTG_V_TOTAL_MAX 0x1c31
#define mmOTG2_OTG_V_TOTAL_MAX_BASE_IDX 2
#define mmOTG2_OTG_V_TOTAL_MID 0x1c32
#define mmOTG2_OTG_V_TOTAL_MID_BASE_IDX 2
#define mmOTG2_OTG_V_TOTAL_CONTROL 0x1c33
#define mmOTG2_OTG_V_TOTAL_CONTROL_BASE_IDX 2
#define mmOTG2_OTG_V_TOTAL_INT_STATUS 0x1c34
#define mmOTG2_OTG_V_TOTAL_INT_STATUS_BASE_IDX 2
#define mmOTG2_OTG_VSYNC_NOM_INT_STATUS 0x1c35
#define mmOTG2_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX 2
#define mmOTG2_OTG_V_BLANK_START_END 0x1c36
#define mmOTG2_OTG_V_BLANK_START_END_BASE_IDX 2
#define mmOTG2_OTG_V_SYNC_A 0x1c37
#define mmOTG2_OTG_V_SYNC_A_BASE_IDX 2
#define mmOTG2_OTG_V_SYNC_A_CNTL 0x1c38
#define mmOTG2_OTG_V_SYNC_A_CNTL_BASE_IDX 2
#define mmOTG2_OTG_TRIGA_CNTL 0x1c39
#define mmOTG2_OTG_TRIGA_CNTL_BASE_IDX 2
#define mmOTG2_OTG_TRIGA_MANUAL_TRIG 0x1c3a
#define mmOTG2_OTG_TRIGA_MANUAL_TRIG_BASE_IDX 2
#define mmOTG2_OTG_TRIGB_CNTL 0x1c3b
#define mmOTG2_OTG_TRIGB_CNTL_BASE_IDX 2
#define mmOTG2_OTG_TRIGB_MANUAL_TRIG 0x1c3c
#define mmOTG2_OTG_TRIGB_MANUAL_TRIG_BASE_IDX 2
#define mmOTG2_OTG_FORCE_COUNT_NOW_CNTL 0x1c3d
#define mmOTG2_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX 2
#define mmOTG2_OTG_FLOW_CONTROL 0x1c3e
#define mmOTG2_OTG_FLOW_CONTROL_BASE_IDX 2
#define mmOTG2_OTG_STEREO_FORCE_NEXT_EYE 0x1c3f
#define mmOTG2_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX 2
#define mmOTG2_OTG_AVSYNC_COUNTER 0x1c40
#define mmOTG2_OTG_AVSYNC_COUNTER_BASE_IDX 2
#define mmOTG2_OTG_CONTROL 0x1c41
#define mmOTG2_OTG_CONTROL_BASE_IDX 2
#define mmOTG2_OTG_BLANK_CONTROL 0x1c42
#define mmOTG2_OTG_BLANK_CONTROL_BASE_IDX 2
#define mmOTG2_OTG_PIPE_ABORT_CONTROL 0x1c43
#define mmOTG2_OTG_PIPE_ABORT_CONTROL_BASE_IDX 2
#define mmOTG2_OTG_INTERLACE_CONTROL 0x1c44
#define mmOTG2_OTG_INTERLACE_CONTROL_BASE_IDX 2
#define mmOTG2_OTG_INTERLACE_STATUS 0x1c45
#define mmOTG2_OTG_INTERLACE_STATUS_BASE_IDX 2
#define mmOTG2_OTG_FIELD_INDICATION_CONTROL 0x1c46
#define mmOTG2_OTG_FIELD_INDICATION_CONTROL_BASE_IDX 2
#define mmOTG2_OTG_PIXEL_DATA_READBACK0 0x1c47
#define mmOTG2_OTG_PIXEL_DATA_READBACK0_BASE_IDX 2
#define mmOTG2_OTG_PIXEL_DATA_READBACK1 0x1c48
#define mmOTG2_OTG_PIXEL_DATA_READBACK1_BASE_IDX 2
#define mmOTG2_OTG_STATUS 0x1c49
#define mmOTG2_OTG_STATUS_BASE_IDX 2
#define mmOTG2_OTG_STATUS_POSITION 0x1c4a
#define mmOTG2_OTG_STATUS_POSITION_BASE_IDX 2
#define mmOTG2_OTG_NOM_VERT_POSITION 0x1c4b
#define mmOTG2_OTG_NOM_VERT_POSITION_BASE_IDX 2
#define mmOTG2_OTG_STATUS_FRAME_COUNT 0x1c4c
#define mmOTG2_OTG_STATUS_FRAME_COUNT_BASE_IDX 2
#define mmOTG2_OTG_STATUS_VF_COUNT 0x1c4d
#define mmOTG2_OTG_STATUS_VF_COUNT_BASE_IDX 2
#define mmOTG2_OTG_STATUS_HV_COUNT 0x1c4e
#define mmOTG2_OTG_STATUS_HV_COUNT_BASE_IDX 2
#define mmOTG2_OTG_COUNT_CONTROL 0x1c4f
#define mmOTG2_OTG_COUNT_CONTROL_BASE_IDX 2
#define mmOTG2_OTG_COUNT_RESET 0x1c50
#define mmOTG2_OTG_COUNT_RESET_BASE_IDX 2
#define mmOTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1c51
#define mmOTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2
#define mmOTG2_OTG_VERT_SYNC_CONTROL 0x1c52
#define mmOTG2_OTG_VERT_SYNC_CONTROL_BASE_IDX 2
#define mmOTG2_OTG_STEREO_STATUS 0x1c53
#define mmOTG2_OTG_STEREO_STATUS_BASE_IDX 2
#define mmOTG2_OTG_STEREO_CONTROL 0x1c54
#define mmOTG2_OTG_STEREO_CONTROL_BASE_IDX 2
#define mmOTG2_OTG_SNAPSHOT_STATUS 0x1c55
#define mmOTG2_OTG_SNAPSHOT_STATUS_BASE_IDX 2
#define mmOTG2_OTG_SNAPSHOT_CONTROL 0x1c56
#define mmOTG2_OTG_SNAPSHOT_CONTROL_BASE_IDX 2
#define mmOTG2_OTG_SNAPSHOT_POSITION 0x1c57
#define mmOTG2_OTG_SNAPSHOT_POSITION_BASE_IDX 2
#define mmOTG2_OTG_SNAPSHOT_FRAME 0x1c58
#define mmOTG2_OTG_SNAPSHOT_FRAME_BASE_IDX 2
#define mmOTG2_OTG_INTERRUPT_CONTROL 0x1c59
#define mmOTG2_OTG_INTERRUPT_CONTROL_BASE_IDX 2
#define mmOTG2_OTG_UPDATE_LOCK 0x1c5a
#define mmOTG2_OTG_UPDATE_LOCK_BASE_IDX 2
#define mmOTG2_OTG_DOUBLE_BUFFER_CONTROL 0x1c5b
#define mmOTG2_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX 2
#define mmOTG2_OTG_TEST_PATTERN_CONTROL 0x1c5c
#define mmOTG2_OTG_TEST_PATTERN_CONTROL_BASE_IDX 2
#define mmOTG2_OTG_TEST_PATTERN_PARAMETERS 0x1c5d
#define mmOTG2_OTG_TEST_PATTERN_PARAMETERS_BASE_IDX 2
#define mmOTG2_OTG_TEST_PATTERN_COLOR 0x1c5e
#define mmOTG2_OTG_TEST_PATTERN_COLOR_BASE_IDX 2
#define mmOTG2_OTG_MASTER_EN 0x1c5f
#define mmOTG2_OTG_MASTER_EN_BASE_IDX 2
#define mmOTG2_OTG_BLANK_DATA_COLOR 0x1c61
#define mmOTG2_OTG_BLANK_DATA_COLOR_BASE_IDX 2
#define mmOTG2_OTG_BLANK_DATA_COLOR_EXT 0x1c62
#define mmOTG2_OTG_BLANK_DATA_COLOR_EXT_BASE_IDX 2
#define mmOTG2_OTG_BLACK_COLOR 0x1c63
#define mmOTG2_OTG_BLACK_COLOR_BASE_IDX 2
#define mmOTG2_OTG_BLACK_COLOR_EXT 0x1c64
#define mmOTG2_OTG_BLACK_COLOR_EXT_BASE_IDX 2
#define mmOTG2_OTG_VERTICAL_INTERRUPT0_POSITION 0x1c65
#define mmOTG2_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2
#define mmOTG2_OTG_VERTICAL_INTERRUPT0_CONTROL 0x1c66
#define mmOTG2_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2
#define mmOTG2_OTG_VERTICAL_INTERRUPT1_POSITION 0x1c67
#define mmOTG2_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2
#define mmOTG2_OTG_VERTICAL_INTERRUPT1_CONTROL 0x1c68
#define mmOTG2_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2
#define mmOTG2_OTG_VERTICAL_INTERRUPT2_POSITION 0x1c69
#define mmOTG2_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2
#define mmOTG2_OTG_VERTICAL_INTERRUPT2_CONTROL 0x1c6a
#define mmOTG2_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2
#define mmOTG2_OTG_CRC_CNTL 0x1c6b
#define mmOTG2_OTG_CRC_CNTL_BASE_IDX 2
#define mmOTG2_OTG_CRC0_WINDOWA_X_CONTROL 0x1c6c
#define mmOTG2_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2
#define mmOTG2_OTG_CRC0_WINDOWA_Y_CONTROL 0x1c6d
#define mmOTG2_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2
#define mmOTG2_OTG_CRC0_WINDOWB_X_CONTROL 0x1c6e
#define mmOTG2_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2
#define mmOTG2_OTG_CRC0_WINDOWB_Y_CONTROL 0x1c6f
#define mmOTG2_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2
#define mmOTG2_OTG_CRC0_DATA_RG 0x1c70
#define mmOTG2_OTG_CRC0_DATA_RG_BASE_IDX 2
#define mmOTG2_OTG_CRC0_DATA_B 0x1c71
#define mmOTG2_OTG_CRC0_DATA_B_BASE_IDX 2
#define mmOTG2_OTG_CRC1_WINDOWA_X_CONTROL 0x1c72
#define mmOTG2_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2
#define mmOTG2_OTG_CRC1_WINDOWA_Y_CONTROL 0x1c73
#define mmOTG2_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2
#define mmOTG2_OTG_CRC1_WINDOWB_X_CONTROL 0x1c74
#define mmOTG2_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2
#define mmOTG2_OTG_CRC1_WINDOWB_Y_CONTROL 0x1c75
#define mmOTG2_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2
#define mmOTG2_OTG_CRC1_DATA_RG 0x1c76
#define mmOTG2_OTG_CRC1_DATA_RG_BASE_IDX 2
#define mmOTG2_OTG_CRC1_DATA_B 0x1c77
#define mmOTG2_OTG_CRC1_DATA_B_BASE_IDX 2
#define mmOTG2_OTG_CRC2_DATA_RG 0x1c78
#define mmOTG2_OTG_CRC2_DATA_RG_BASE_IDX 2
#define mmOTG2_OTG_CRC2_DATA_B 0x1c79
#define mmOTG2_OTG_CRC2_DATA_B_BASE_IDX 2
#define mmOTG2_OTG_CRC3_DATA_RG 0x1c7a
#define mmOTG2_OTG_CRC3_DATA_RG_BASE_IDX 2
#define mmOTG2_OTG_CRC3_DATA_B 0x1c7b
#define mmOTG2_OTG_CRC3_DATA_B_BASE_IDX 2
#define mmOTG2_OTG_CRC_SIG_RED_GREEN_MASK 0x1c7c
#define mmOTG2_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2
#define mmOTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK 0x1c7d
#define mmOTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2
#define mmOTG2_OTG_STATIC_SCREEN_CONTROL 0x1c84
#define mmOTG2_OTG_STATIC_SCREEN_CONTROL_BASE_IDX 2
#define mmOTG2_OTG_3D_STRUCTURE_CONTROL 0x1c85
#define mmOTG2_OTG_3D_STRUCTURE_CONTROL_BASE_IDX 2
#define mmOTG2_OTG_GSL_VSYNC_GAP 0x1c86
#define mmOTG2_OTG_GSL_VSYNC_GAP_BASE_IDX 2
#define mmOTG2_OTG_MASTER_UPDATE_MODE 0x1c87
#define mmOTG2_OTG_MASTER_UPDATE_MODE_BASE_IDX 2
#define mmOTG2_OTG_CLOCK_CONTROL 0x1c88
#define mmOTG2_OTG_CLOCK_CONTROL_BASE_IDX 2
#define mmOTG2_OTG_VSTARTUP_PARAM 0x1c89
#define mmOTG2_OTG_VSTARTUP_PARAM_BASE_IDX 2
#define mmOTG2_OTG_VUPDATE_PARAM 0x1c8a
#define mmOTG2_OTG_VUPDATE_PARAM_BASE_IDX 2
#define mmOTG2_OTG_VREADY_PARAM 0x1c8b
#define mmOTG2_OTG_VREADY_PARAM_BASE_IDX 2
#define mmOTG2_OTG_GLOBAL_SYNC_STATUS 0x1c8c
#define mmOTG2_OTG_GLOBAL_SYNC_STATUS_BASE_IDX 2
#define mmOTG2_OTG_MASTER_UPDATE_LOCK 0x1c8d
#define mmOTG2_OTG_MASTER_UPDATE_LOCK_BASE_IDX 2
#define mmOTG2_OTG_GSL_CONTROL 0x1c8e
#define mmOTG2_OTG_GSL_CONTROL_BASE_IDX 2
#define mmOTG2_OTG_GSL_WINDOW_X 0x1c8f
#define mmOTG2_OTG_GSL_WINDOW_X_BASE_IDX 2
#define mmOTG2_OTG_GSL_WINDOW_Y 0x1c90
#define mmOTG2_OTG_GSL_WINDOW_Y_BASE_IDX 2
#define mmOTG2_OTG_VUPDATE_KEEPOUT 0x1c91
#define mmOTG2_OTG_VUPDATE_KEEPOUT_BASE_IDX 2
#define mmOTG2_OTG_GLOBAL_CONTROL0 0x1c92
#define mmOTG2_OTG_GLOBAL_CONTROL0_BASE_IDX 2
#define mmOTG2_OTG_GLOBAL_CONTROL1 0x1c93
#define mmOTG2_OTG_GLOBAL_CONTROL1_BASE_IDX 2
#define mmOTG2_OTG_GLOBAL_CONTROL2 0x1c94
#define mmOTG2_OTG_GLOBAL_CONTROL2_BASE_IDX 2
#define mmOTG2_OTG_GLOBAL_CONTROL3 0x1c95
#define mmOTG2_OTG_GLOBAL_CONTROL3_BASE_IDX 2
#define mmOTG2_OTG_TRIG_MANUAL_CONTROL 0x1c96
#define mmOTG2_OTG_TRIG_MANUAL_CONTROL_BASE_IDX 2
#define mmOTG2_OTG_MANUAL_FLOW_CONTROL 0x1c97
#define mmOTG2_OTG_MANUAL_FLOW_CONTROL_BASE_IDX 2
#define mmOTG2_OTG_RANGE_TIMING_INT_STATUS 0x1c98
#define mmOTG2_OTG_RANGE_TIMING_INT_STATUS_BASE_IDX 2
#define mmOTG2_OTG_DRR_CONTROL 0x1c99
#define mmOTG2_OTG_DRR_CONTROL_BASE_IDX 2
#define mmOTG2_OTG_REQUEST_CONTROL 0x1c9a
#define mmOTG2_OTG_REQUEST_CONTROL_BASE_IDX 2
#define mmOTG2_OTG_SPARE_REGISTER 0x1c9b
#define mmOTG2_OTG_SPARE_REGISTER_BASE_IDX 2
// addressBlock: dce_dc_optc_otg3_dispdec
// base address: 0x600
#define mmOTG3_OTG_H_TOTAL 0x1caa
#define mmOTG3_OTG_H_TOTAL_BASE_IDX 2
#define mmOTG3_OTG_H_BLANK_START_END 0x1cab
#define mmOTG3_OTG_H_BLANK_START_END_BASE_IDX 2
#define mmOTG3_OTG_H_SYNC_A 0x1cac
#define mmOTG3_OTG_H_SYNC_A_BASE_IDX 2
#define mmOTG3_OTG_H_SYNC_A_CNTL 0x1cad
#define mmOTG3_OTG_H_SYNC_A_CNTL_BASE_IDX 2
#define mmOTG3_OTG_H_TIMING_CNTL 0x1cae
#define mmOTG3_OTG_H_TIMING_CNTL_BASE_IDX 2
#define mmOTG3_OTG_V_TOTAL 0x1caf
#define mmOTG3_OTG_V_TOTAL_BASE_IDX 2
#define mmOTG3_OTG_V_TOTAL_MIN 0x1cb0
#define mmOTG3_OTG_V_TOTAL_MIN_BASE_IDX 2
#define mmOTG3_OTG_V_TOTAL_MAX 0x1cb1
#define mmOTG3_OTG_V_TOTAL_MAX_BASE_IDX 2
#define mmOTG3_OTG_V_TOTAL_MID 0x1cb2
#define mmOTG3_OTG_V_TOTAL_MID_BASE_IDX 2
#define mmOTG3_OTG_V_TOTAL_CONTROL 0x1cb3
#define mmOTG3_OTG_V_TOTAL_CONTROL_BASE_IDX 2
#define mmOTG3_OTG_V_TOTAL_INT_STATUS 0x1cb4
#define mmOTG3_OTG_V_TOTAL_INT_STATUS_BASE_IDX 2
#define mmOTG3_OTG_VSYNC_NOM_INT_STATUS 0x1cb5
#define mmOTG3_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX 2
#define mmOTG3_OTG_V_BLANK_START_END 0x1cb6
#define mmOTG3_OTG_V_BLANK_START_END_BASE_IDX 2
#define mmOTG3_OTG_V_SYNC_A 0x1cb7
#define mmOTG3_OTG_V_SYNC_A_BASE_IDX 2
#define mmOTG3_OTG_V_SYNC_A_CNTL 0x1cb8
#define mmOTG3_OTG_V_SYNC_A_CNTL_BASE_IDX 2
#define mmOTG3_OTG_TRIGA_CNTL 0x1cb9
#define mmOTG3_OTG_TRIGA_CNTL_BASE_IDX 2
#define mmOTG3_OTG_TRIGA_MANUAL_TRIG 0x1cba
#define mmOTG3_OTG_TRIGA_MANUAL_TRIG_BASE_IDX 2
#define mmOTG3_OTG_TRIGB_CNTL 0x1cbb
#define mmOTG3_OTG_TRIGB_CNTL_BASE_IDX 2
#define mmOTG3_OTG_TRIGB_MANUAL_TRIG 0x1cbc
#define mmOTG3_OTG_TRIGB_MANUAL_TRIG_BASE_IDX 2
#define mmOTG3_OTG_FORCE_COUNT_NOW_CNTL 0x1cbd
#define mmOTG3_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX 2
#define mmOTG3_OTG_FLOW_CONTROL 0x1cbe
#define mmOTG3_OTG_FLOW_CONTROL_BASE_IDX 2
#define mmOTG3_OTG_STEREO_FORCE_NEXT_EYE 0x1cbf
#define mmOTG3_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX 2
#define mmOTG3_OTG_AVSYNC_COUNTER 0x1cc0
#define mmOTG3_OTG_AVSYNC_COUNTER_BASE_IDX 2
#define mmOTG3_OTG_CONTROL 0x1cc1
#define mmOTG3_OTG_CONTROL_BASE_IDX 2
#define mmOTG3_OTG_BLANK_CONTROL 0x1cc2
#define mmOTG3_OTG_BLANK_CONTROL_BASE_IDX 2
#define mmOTG3_OTG_PIPE_ABORT_CONTROL 0x1cc3
#define mmOTG3_OTG_PIPE_ABORT_CONTROL_BASE_IDX 2
#define mmOTG3_OTG_INTERLACE_CONTROL 0x1cc4
#define mmOTG3_OTG_INTERLACE_CONTROL_BASE_IDX 2
#define mmOTG3_OTG_INTERLACE_STATUS 0x1cc5
#define mmOTG3_OTG_INTERLACE_STATUS_BASE_IDX 2
#define mmOTG3_OTG_FIELD_INDICATION_CONTROL 0x1cc6
#define mmOTG3_OTG_FIELD_INDICATION_CONTROL_BASE_IDX 2
#define mmOTG3_OTG_PIXEL_DATA_READBACK0 0x1cc7
#define mmOTG3_OTG_PIXEL_DATA_READBACK0_BASE_IDX 2
#define mmOTG3_OTG_PIXEL_DATA_READBACK1 0x1cc8
#define mmOTG3_OTG_PIXEL_DATA_READBACK1_BASE_IDX 2
#define mmOTG3_OTG_STATUS 0x1cc9
#define mmOTG3_OTG_STATUS_BASE_IDX 2
#define mmOTG3_OTG_STATUS_POSITION 0x1cca
#define mmOTG3_OTG_STATUS_POSITION_BASE_IDX 2
#define mmOTG3_OTG_NOM_VERT_POSITION 0x1ccb
#define mmOTG3_OTG_NOM_VERT_POSITION_BASE_IDX 2
#define mmOTG3_OTG_STATUS_FRAME_COUNT 0x1ccc
#define mmOTG3_OTG_STATUS_FRAME_COUNT_BASE_IDX 2
#define mmOTG3_OTG_STATUS_VF_COUNT 0x1ccd
#define mmOTG3_OTG_STATUS_VF_COUNT_BASE_IDX 2
#define mmOTG3_OTG_STATUS_HV_COUNT 0x1cce
#define mmOTG3_OTG_STATUS_HV_COUNT_BASE_IDX 2
#define mmOTG3_OTG_COUNT_CONTROL 0x1ccf
#define mmOTG3_OTG_COUNT_CONTROL_BASE_IDX 2
#define mmOTG3_OTG_COUNT_RESET 0x1cd0
#define mmOTG3_OTG_COUNT_RESET_BASE_IDX 2
#define mmOTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1cd1
#define mmOTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2
#define mmOTG3_OTG_VERT_SYNC_CONTROL 0x1cd2
#define mmOTG3_OTG_VERT_SYNC_CONTROL_BASE_IDX 2
#define mmOTG3_OTG_STEREO_STATUS 0x1cd3
#define mmOTG3_OTG_STEREO_STATUS_BASE_IDX 2
#define mmOTG3_OTG_STEREO_CONTROL 0x1cd4
#define mmOTG3_OTG_STEREO_CONTROL_BASE_IDX 2
#define mmOTG3_OTG_SNAPSHOT_STATUS 0x1cd5
#define mmOTG3_OTG_SNAPSHOT_STATUS_BASE_IDX 2
#define mmOTG3_OTG_SNAPSHOT_CONTROL 0x1cd6
#define mmOTG3_OTG_SNAPSHOT_CONTROL_BASE_IDX 2
#define mmOTG3_OTG_SNAPSHOT_POSITION 0x1cd7
#define mmOTG3_OTG_SNAPSHOT_POSITION_BASE_IDX 2
#define mmOTG3_OTG_SNAPSHOT_FRAME 0x1cd8
#define mmOTG3_OTG_SNAPSHOT_FRAME_BASE_IDX 2
#define mmOTG3_OTG_INTERRUPT_CONTROL 0x1cd9
#define mmOTG3_OTG_INTERRUPT_CONTROL_BASE_IDX 2
#define mmOTG3_OTG_UPDATE_LOCK 0x1cda
#define mmOTG3_OTG_UPDATE_LOCK_BASE_IDX 2
#define mmOTG3_OTG_DOUBLE_BUFFER_CONTROL 0x1cdb
#define mmOTG3_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX 2
#define mmOTG3_OTG_TEST_PATTERN_CONTROL 0x1cdc
#define mmOTG3_OTG_TEST_PATTERN_CONTROL_BASE_IDX 2
#define mmOTG3_OTG_TEST_PATTERN_PARAMETERS 0x1cdd
#define mmOTG3_OTG_TEST_PATTERN_PARAMETERS_BASE_IDX 2
#define mmOTG3_OTG_TEST_PATTERN_COLOR 0x1cde
#define mmOTG3_OTG_TEST_PATTERN_COLOR_BASE_IDX 2
#define mmOTG3_OTG_MASTER_EN 0x1cdf
#define mmOTG3_OTG_MASTER_EN_BASE_IDX 2
#define mmOTG3_OTG_BLANK_DATA_COLOR 0x1ce1
#define mmOTG3_OTG_BLANK_DATA_COLOR_BASE_IDX 2
#define mmOTG3_OTG_BLANK_DATA_COLOR_EXT 0x1ce2
#define mmOTG3_OTG_BLANK_DATA_COLOR_EXT_BASE_IDX 2
#define mmOTG3_OTG_BLACK_COLOR 0x1ce3
#define mmOTG3_OTG_BLACK_COLOR_BASE_IDX 2
#define mmOTG3_OTG_BLACK_COLOR_EXT 0x1ce4
#define mmOTG3_OTG_BLACK_COLOR_EXT_BASE_IDX 2
#define mmOTG3_OTG_VERTICAL_INTERRUPT0_POSITION 0x1ce5
#define mmOTG3_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2
#define mmOTG3_OTG_VERTICAL_INTERRUPT0_CONTROL 0x1ce6
#define mmOTG3_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2
#define mmOTG3_OTG_VERTICAL_INTERRUPT1_POSITION 0x1ce7
#define mmOTG3_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2
#define mmOTG3_OTG_VERTICAL_INTERRUPT1_CONTROL 0x1ce8
#define mmOTG3_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2
#define mmOTG3_OTG_VERTICAL_INTERRUPT2_POSITION 0x1ce9
#define mmOTG3_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2
#define mmOTG3_OTG_VERTICAL_INTERRUPT2_CONTROL 0x1cea
#define mmOTG3_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2
#define mmOTG3_OTG_CRC_CNTL 0x1ceb
#define mmOTG3_OTG_CRC_CNTL_BASE_IDX 2
#define mmOTG3_OTG_CRC0_WINDOWA_X_CONTROL 0x1cec
#define mmOTG3_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2
#define mmOTG3_OTG_CRC0_WINDOWA_Y_CONTROL 0x1ced
#define mmOTG3_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2
#define mmOTG3_OTG_CRC0_WINDOWB_X_CONTROL 0x1cee
#define mmOTG3_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2
#define mmOTG3_OTG_CRC0_WINDOWB_Y_CONTROL 0x1cef
#define mmOTG3_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2
#define mmOTG3_OTG_CRC0_DATA_RG 0x1cf0
#define mmOTG3_OTG_CRC0_DATA_RG_BASE_IDX 2
#define mmOTG3_OTG_CRC0_DATA_B 0x1cf1
#define mmOTG3_OTG_CRC0_DATA_B_BASE_IDX 2
#define mmOTG3_OTG_CRC1_WINDOWA_X_CONTROL 0x1cf2
#define mmOTG3_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2
#define mmOTG3_OTG_CRC1_WINDOWA_Y_CONTROL 0x1cf3
#define mmOTG3_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2
#define mmOTG3_OTG_CRC1_WINDOWB_X_CONTROL 0x1cf4
#define mmOTG3_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2
#define mmOTG3_OTG_CRC1_WINDOWB_Y_CONTROL 0x1cf5
#define mmOTG3_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2
#define mmOTG3_OTG_CRC1_DATA_RG 0x1cf6
#define mmOTG3_OTG_CRC1_DATA_RG_BASE_IDX 2
#define mmOTG3_OTG_CRC1_DATA_B 0x1cf7
#define mmOTG3_OTG_CRC1_DATA_B_BASE_IDX 2
#define mmOTG3_OTG_CRC2_DATA_RG 0x1cf8
#define mmOTG3_OTG_CRC2_DATA_RG_BASE_IDX 2
#define mmOTG3_OTG_CRC2_DATA_B 0x1cf9
#define mmOTG3_OTG_CRC2_DATA_B_BASE_IDX 2
#define mmOTG3_OTG_CRC3_DATA_RG 0x1cfa
#define mmOTG3_OTG_CRC3_DATA_RG_BASE_IDX 2
#define mmOTG3_OTG_CRC3_DATA_B 0x1cfb
#define mmOTG3_OTG_CRC3_DATA_B_BASE_IDX 2
#define mmOTG3_OTG_CRC_SIG_RED_GREEN_MASK 0x1cfc
#define mmOTG3_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2
#define mmOTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK 0x1cfd
#define mmOTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2
#define mmOTG3_OTG_STATIC_SCREEN_CONTROL 0x1d04
#define mmOTG3_OTG_STATIC_SCREEN_CONTROL_BASE_IDX 2
#define mmOTG3_OTG_3D_STRUCTURE_CONTROL 0x1d05
#define mmOTG3_OTG_3D_STRUCTURE_CONTROL_BASE_IDX 2
#define mmOTG3_OTG_GSL_VSYNC_GAP 0x1d06
#define mmOTG3_OTG_GSL_VSYNC_GAP_BASE_IDX 2
#define mmOTG3_OTG_MASTER_UPDATE_MODE 0x1d07
#define mmOTG3_OTG_MASTER_UPDATE_MODE_BASE_IDX 2
#define mmOTG3_OTG_CLOCK_CONTROL 0x1d08
#define mmOTG3_OTG_CLOCK_CONTROL_BASE_IDX 2
#define mmOTG3_OTG_VSTARTUP_PARAM 0x1d09
#define mmOTG3_OTG_VSTARTUP_PARAM_BASE_IDX 2
#define mmOTG3_OTG_VUPDATE_PARAM 0x1d0a
#define mmOTG3_OTG_VUPDATE_PARAM_BASE_IDX 2
#define mmOTG3_OTG_VREADY_PARAM 0x1d0b
#define mmOTG3_OTG_VREADY_PARAM_BASE_IDX 2
#define mmOTG3_OTG_GLOBAL_SYNC_STATUS 0x1d0c
#define mmOTG3_OTG_GLOBAL_SYNC_STATUS_BASE_IDX 2
#define mmOTG3_OTG_MASTER_UPDATE_LOCK 0x1d0d
#define mmOTG3_OTG_MASTER_UPDATE_LOCK_BASE_IDX 2
#define mmOTG3_OTG_GSL_CONTROL 0x1d0e
#define mmOTG3_OTG_GSL_CONTROL_BASE_IDX 2
#define mmOTG3_OTG_GSL_WINDOW_X 0x1d0f
#define mmOTG3_OTG_GSL_WINDOW_X_BASE_IDX 2
#define mmOTG3_OTG_GSL_WINDOW_Y 0x1d10
#define mmOTG3_OTG_GSL_WINDOW_Y_BASE_IDX 2
#define mmOTG3_OTG_VUPDATE_KEEPOUT 0x1d11
#define mmOTG3_OTG_VUPDATE_KEEPOUT_BASE_IDX 2
#define mmOTG3_OTG_GLOBAL_CONTROL0 0x1d12
#define mmOTG3_OTG_GLOBAL_CONTROL0_BASE_IDX 2
#define mmOTG3_OTG_GLOBAL_CONTROL1 0x1d13
#define mmOTG3_OTG_GLOBAL_CONTROL1_BASE_IDX 2
#define mmOTG3_OTG_GLOBAL_CONTROL2 0x1d14
#define mmOTG3_OTG_GLOBAL_CONTROL2_BASE_IDX 2
#define mmOTG3_OTG_GLOBAL_CONTROL3 0x1d15
#define mmOTG3_OTG_GLOBAL_CONTROL3_BASE_IDX 2
#define mmOTG3_OTG_TRIG_MANUAL_CONTROL 0x1d16
#define mmOTG3_OTG_TRIG_MANUAL_CONTROL_BASE_IDX 2
#define mmOTG3_OTG_MANUAL_FLOW_CONTROL 0x1d17
#define mmOTG3_OTG_MANUAL_FLOW_CONTROL_BASE_IDX 2
#define mmOTG3_OTG_RANGE_TIMING_INT_STATUS 0x1d18
#define mmOTG3_OTG_RANGE_TIMING_INT_STATUS_BASE_IDX 2
#define mmOTG3_OTG_DRR_CONTROL 0x1d19
#define mmOTG3_OTG_DRR_CONTROL_BASE_IDX 2
#define mmOTG3_OTG_REQUEST_CONTROL 0x1d1a
#define mmOTG3_OTG_REQUEST_CONTROL_BASE_IDX 2
#define mmOTG3_OTG_SPARE_REGISTER 0x1d1b
#define mmOTG3_OTG_SPARE_REGISTER_BASE_IDX 2
// addressBlock: dce_dc_optc_otg4_dispdec
// base address: 0x800
#define mmOTG4_OTG_H_TOTAL 0x1d2a
#define mmOTG4_OTG_H_TOTAL_BASE_IDX 2
#define mmOTG4_OTG_H_BLANK_START_END 0x1d2b
#define mmOTG4_OTG_H_BLANK_START_END_BASE_IDX 2
#define mmOTG4_OTG_H_SYNC_A 0x1d2c
#define mmOTG4_OTG_H_SYNC_A_BASE_IDX 2
#define mmOTG4_OTG_H_SYNC_A_CNTL 0x1d2d
#define mmOTG4_OTG_H_SYNC_A_CNTL_BASE_IDX 2
#define mmOTG4_OTG_H_TIMING_CNTL 0x1d2e
#define mmOTG4_OTG_H_TIMING_CNTL_BASE_IDX 2
#define mmOTG4_OTG_V_TOTAL 0x1d2f
#define mmOTG4_OTG_V_TOTAL_BASE_IDX 2
#define mmOTG4_OTG_V_TOTAL_MIN 0x1d30
#define mmOTG4_OTG_V_TOTAL_MIN_BASE_IDX 2
#define mmOTG4_OTG_V_TOTAL_MAX 0x1d31
#define mmOTG4_OTG_V_TOTAL_MAX_BASE_IDX 2
#define mmOTG4_OTG_V_TOTAL_MID 0x1d32
#define mmOTG4_OTG_V_TOTAL_MID_BASE_IDX 2
#define mmOTG4_OTG_V_TOTAL_CONTROL 0x1d33
#define mmOTG4_OTG_V_TOTAL_CONTROL_BASE_IDX 2
#define mmOTG4_OTG_V_TOTAL_INT_STATUS 0x1d34
#define mmOTG4_OTG_V_TOTAL_INT_STATUS_BASE_IDX 2
#define mmOTG4_OTG_VSYNC_NOM_INT_STATUS 0x1d35
#define mmOTG4_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX 2
#define mmOTG4_OTG_V_BLANK_START_END 0x1d36
#define mmOTG4_OTG_V_BLANK_START_END_BASE_IDX 2
#define mmOTG4_OTG_V_SYNC_A 0x1d37
#define mmOTG4_OTG_V_SYNC_A_BASE_IDX 2
#define mmOTG4_OTG_V_SYNC_A_CNTL 0x1d38
#define mmOTG4_OTG_V_SYNC_A_CNTL_BASE_IDX 2
#define mmOTG4_OTG_TRIGA_CNTL 0x1d39
#define mmOTG4_OTG_TRIGA_CNTL_BASE_IDX 2
#define mmOTG4_OTG_TRIGA_MANUAL_TRIG 0x1d3a
#define mmOTG4_OTG_TRIGA_MANUAL_TRIG_BASE_IDX 2
#define mmOTG4_OTG_TRIGB_CNTL 0x1d3b
#define mmOTG4_OTG_TRIGB_CNTL_BASE_IDX 2
#define mmOTG4_OTG_TRIGB_MANUAL_TRIG 0x1d3c
#define mmOTG4_OTG_TRIGB_MANUAL_TRIG_BASE_IDX 2
#define mmOTG4_OTG_FORCE_COUNT_NOW_CNTL 0x1d3d
#define mmOTG4_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX 2
#define mmOTG4_OTG_FLOW_CONTROL 0x1d3e
#define mmOTG4_OTG_FLOW_CONTROL_BASE_IDX 2
#define mmOTG4_OTG_STEREO_FORCE_NEXT_EYE 0x1d3f
#define mmOTG4_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX 2
#define mmOTG4_OTG_AVSYNC_COUNTER 0x1d40
#define mmOTG4_OTG_AVSYNC_COUNTER_BASE_IDX 2
#define mmOTG4_OTG_CONTROL 0x1d41
#define mmOTG4_OTG_CONTROL_BASE_IDX 2
#define mmOTG4_OTG_BLANK_CONTROL 0x1d42
#define mmOTG4_OTG_BLANK_CONTROL_BASE_IDX 2
#define mmOTG4_OTG_PIPE_ABORT_CONTROL 0x1d43
#define mmOTG4_OTG_PIPE_ABORT_CONTROL_BASE_IDX 2
#define mmOTG4_OTG_INTERLACE_CONTROL 0x1d44
#define mmOTG4_OTG_INTERLACE_CONTROL_BASE_IDX 2
#define mmOTG4_OTG_INTERLACE_STATUS 0x1d45
#define mmOTG4_OTG_INTERLACE_STATUS_BASE_IDX 2
#define mmOTG4_OTG_FIELD_INDICATION_CONTROL 0x1d46
#define mmOTG4_OTG_FIELD_INDICATION_CONTROL_BASE_IDX 2
#define mmOTG4_OTG_PIXEL_DATA_READBACK0 0x1d47
#define mmOTG4_OTG_PIXEL_DATA_READBACK0_BASE_IDX 2
#define mmOTG4_OTG_PIXEL_DATA_READBACK1 0x1d48
#define mmOTG4_OTG_PIXEL_DATA_READBACK1_BASE_IDX 2
#define mmOTG4_OTG_STATUS 0x1d49
#define mmOTG4_OTG_STATUS_BASE_IDX 2
#define mmOTG4_OTG_STATUS_POSITION 0x1d4a
#define mmOTG4_OTG_STATUS_POSITION_BASE_IDX 2
#define mmOTG4_OTG_NOM_VERT_POSITION 0x1d4b
#define mmOTG4_OTG_NOM_VERT_POSITION_BASE_IDX 2
#define mmOTG4_OTG_STATUS_FRAME_COUNT 0x1d4c
#define mmOTG4_OTG_STATUS_FRAME_COUNT_BASE_IDX 2
#define mmOTG4_OTG_STATUS_VF_COUNT 0x1d4d
#define mmOTG4_OTG_STATUS_VF_COUNT_BASE_IDX 2
#define mmOTG4_OTG_STATUS_HV_COUNT 0x1d4e
#define mmOTG4_OTG_STATUS_HV_COUNT_BASE_IDX 2
#define mmOTG4_OTG_COUNT_CONTROL 0x1d4f
#define mmOTG4_OTG_COUNT_CONTROL_BASE_IDX 2
#define mmOTG4_OTG_COUNT_RESET 0x1d50
#define mmOTG4_OTG_COUNT_RESET_BASE_IDX 2
#define mmOTG4_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1d51
#define mmOTG4_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2
#define mmOTG4_OTG_VERT_SYNC_CONTROL 0x1d52
#define mmOTG4_OTG_VERT_SYNC_CONTROL_BASE_IDX 2
#define mmOTG4_OTG_STEREO_STATUS 0x1d53
#define mmOTG4_OTG_STEREO_STATUS_BASE_IDX 2
#define mmOTG4_OTG_STEREO_CONTROL 0x1d54
#define mmOTG4_OTG_STEREO_CONTROL_BASE_IDX 2
#define mmOTG4_OTG_SNAPSHOT_STATUS 0x1d55
#define mmOTG4_OTG_SNAPSHOT_STATUS_BASE_IDX 2
#define mmOTG4_OTG_SNAPSHOT_CONTROL 0x1d56
#define mmOTG4_OTG_SNAPSHOT_CONTROL_BASE_IDX 2
#define mmOTG4_OTG_SNAPSHOT_POSITION 0x1d57
#define mmOTG4_OTG_SNAPSHOT_POSITION_BASE_IDX 2
#define mmOTG4_OTG_SNAPSHOT_FRAME 0x1d58
#define mmOTG4_OTG_SNAPSHOT_FRAME_BASE_IDX 2
#define mmOTG4_OTG_INTERRUPT_CONTROL 0x1d59
#define mmOTG4_OTG_INTERRUPT_CONTROL_BASE_IDX 2
#define mmOTG4_OTG_UPDATE_LOCK 0x1d5a
#define mmOTG4_OTG_UPDATE_LOCK_BASE_IDX 2
#define mmOTG4_OTG_DOUBLE_BUFFER_CONTROL 0x1d5b
#define mmOTG4_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX 2
#define mmOTG4_OTG_TEST_PATTERN_CONTROL 0x1d5c
#define mmOTG4_OTG_TEST_PATTERN_CONTROL_BASE_IDX 2
#define mmOTG4_OTG_TEST_PATTERN_PARAMETERS 0x1d5d
#define mmOTG4_OTG_TEST_PATTERN_PARAMETERS_BASE_IDX 2
#define mmOTG4_OTG_TEST_PATTERN_COLOR 0x1d5e
#define mmOTG4_OTG_TEST_PATTERN_COLOR_BASE_IDX 2
#define mmOTG4_OTG_MASTER_EN 0x1d5f
#define mmOTG4_OTG_MASTER_EN_BASE_IDX 2
#define mmOTG4_OTG_BLANK_DATA_COLOR 0x1d61
#define mmOTG4_OTG_BLANK_DATA_COLOR_BASE_IDX 2
#define mmOTG4_OTG_BLANK_DATA_COLOR_EXT 0x1d62
#define mmOTG4_OTG_BLANK_DATA_COLOR_EXT_BASE_IDX 2
#define mmOTG4_OTG_BLACK_COLOR 0x1d63
#define mmOTG4_OTG_BLACK_COLOR_BASE_IDX 2
#define mmOTG4_OTG_BLACK_COLOR_EXT 0x1d64
#define mmOTG4_OTG_BLACK_COLOR_EXT_BASE_IDX 2
#define mmOTG4_OTG_VERTICAL_INTERRUPT0_POSITION 0x1d65
#define mmOTG4_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2
#define mmOTG4_OTG_VERTICAL_INTERRUPT0_CONTROL 0x1d66
#define mmOTG4_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2
#define mmOTG4_OTG_VERTICAL_INTERRUPT1_POSITION 0x1d67
#define mmOTG4_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2
#define mmOTG4_OTG_VERTICAL_INTERRUPT1_CONTROL 0x1d68
#define mmOTG4_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2
#define mmOTG4_OTG_VERTICAL_INTERRUPT2_POSITION 0x1d69
#define mmOTG4_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2
#define mmOTG4_OTG_VERTICAL_INTERRUPT2_CONTROL 0x1d6a
#define mmOTG4_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2
#define mmOTG4_OTG_CRC_CNTL 0x1d6b
#define mmOTG4_OTG_CRC_CNTL_BASE_IDX 2
#define mmOTG4_OTG_CRC0_WINDOWA_X_CONTROL 0x1d6c
#define mmOTG4_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2
#define mmOTG4_OTG_CRC0_WINDOWA_Y_CONTROL 0x1d6d
#define mmOTG4_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2
#define mmOTG4_OTG_CRC0_WINDOWB_X_CONTROL 0x1d6e
#define mmOTG4_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2
#define mmOTG4_OTG_CRC0_WINDOWB_Y_CONTROL 0x1d6f
#define mmOTG4_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2
#define mmOTG4_OTG_CRC0_DATA_RG 0x1d70
#define mmOTG4_OTG_CRC0_DATA_RG_BASE_IDX 2
#define mmOTG4_OTG_CRC0_DATA_B 0x1d71
#define mmOTG4_OTG_CRC0_DATA_B_BASE_IDX 2
#define mmOTG4_OTG_CRC1_WINDOWA_X_CONTROL 0x1d72
#define mmOTG4_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2
#define mmOTG4_OTG_CRC1_WINDOWA_Y_CONTROL 0x1d73
#define mmOTG4_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2
#define mmOTG4_OTG_CRC1_WINDOWB_X_CONTROL 0x1d74
#define mmOTG4_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2
#define mmOTG4_OTG_CRC1_WINDOWB_Y_CONTROL 0x1d75
#define mmOTG4_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2
#define mmOTG4_OTG_CRC1_DATA_RG 0x1d76
#define mmOTG4_OTG_CRC1_DATA_RG_BASE_IDX 2
#define mmOTG4_OTG_CRC1_DATA_B 0x1d77
#define mmOTG4_OTG_CRC1_DATA_B_BASE_IDX 2
#define mmOTG4_OTG_CRC2_DATA_RG 0x1d78
#define mmOTG4_OTG_CRC2_DATA_RG_BASE_IDX 2
#define mmOTG4_OTG_CRC2_DATA_B 0x1d79
#define mmOTG4_OTG_CRC2_DATA_B_BASE_IDX 2
#define mmOTG4_OTG_CRC3_DATA_RG 0x1d7a
#define mmOTG4_OTG_CRC3_DATA_RG_BASE_IDX 2
#define mmOTG4_OTG_CRC3_DATA_B 0x1d7b
#define mmOTG4_OTG_CRC3_DATA_B_BASE_IDX 2
#define mmOTG4_OTG_CRC_SIG_RED_GREEN_MASK 0x1d7c
#define mmOTG4_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2
#define mmOTG4_OTG_CRC_SIG_BLUE_CONTROL_MASK 0x1d7d
#define mmOTG4_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2
#define mmOTG4_OTG_STATIC_SCREEN_CONTROL 0x1d84
#define mmOTG4_OTG_STATIC_SCREEN_CONTROL_BASE_IDX 2
#define mmOTG4_OTG_3D_STRUCTURE_CONTROL 0x1d85
#define mmOTG4_OTG_3D_STRUCTURE_CONTROL_BASE_IDX 2
#define mmOTG4_OTG_GSL_VSYNC_GAP 0x1d86
#define mmOTG4_OTG_GSL_VSYNC_GAP_BASE_IDX 2
#define mmOTG4_OTG_MASTER_UPDATE_MODE 0x1d87
#define mmOTG4_OTG_MASTER_UPDATE_MODE_BASE_IDX 2
#define mmOTG4_OTG_CLOCK_CONTROL 0x1d88
#define mmOTG4_OTG_CLOCK_CONTROL_BASE_IDX 2
#define mmOTG4_OTG_VSTARTUP_PARAM 0x1d89
#define mmOTG4_OTG_VSTARTUP_PARAM_BASE_IDX 2
#define mmOTG4_OTG_VUPDATE_PARAM 0x1d8a
#define mmOTG4_OTG_VUPDATE_PARAM_BASE_IDX 2
#define mmOTG4_OTG_VREADY_PARAM 0x1d8b
#define mmOTG4_OTG_VREADY_PARAM_BASE_IDX 2
#define mmOTG4_OTG_GLOBAL_SYNC_STATUS 0x1d8c
#define mmOTG4_OTG_GLOBAL_SYNC_STATUS_BASE_IDX 2
#define mmOTG4_OTG_MASTER_UPDATE_LOCK 0x1d8d
#define mmOTG4_OTG_MASTER_UPDATE_LOCK_BASE_IDX 2
#define mmOTG4_OTG_GSL_CONTROL 0x1d8e
#define mmOTG4_OTG_GSL_CONTROL_BASE_IDX 2
#define mmOTG4_OTG_GSL_WINDOW_X 0x1d8f
#define mmOTG4_OTG_GSL_WINDOW_X_BASE_IDX 2
#define mmOTG4_OTG_GSL_WINDOW_Y 0x1d90
#define mmOTG4_OTG_GSL_WINDOW_Y_BASE_IDX 2
#define mmOTG4_OTG_VUPDATE_KEEPOUT 0x1d91
#define mmOTG4_OTG_VUPDATE_KEEPOUT_BASE_IDX 2
#define mmOTG4_OTG_GLOBAL_CONTROL0 0x1d92
#define mmOTG4_OTG_GLOBAL_CONTROL0_BASE_IDX 2
#define mmOTG4_OTG_GLOBAL_CONTROL1 0x1d93
#define mmOTG4_OTG_GLOBAL_CONTROL1_BASE_IDX 2
#define mmOTG4_OTG_GLOBAL_CONTROL2 0x1d94
#define mmOTG4_OTG_GLOBAL_CONTROL2_BASE_IDX 2
#define mmOTG4_OTG_GLOBAL_CONTROL3 0x1d95
#define mmOTG4_OTG_GLOBAL_CONTROL3_BASE_IDX 2
#define mmOTG4_OTG_TRIG_MANUAL_CONTROL 0x1d96
#define mmOTG4_OTG_TRIG_MANUAL_CONTROL_BASE_IDX 2
#define mmOTG4_OTG_MANUAL_FLOW_CONTROL 0x1d97
#define mmOTG4_OTG_MANUAL_FLOW_CONTROL_BASE_IDX 2
#define mmOTG4_OTG_RANGE_TIMING_INT_STATUS 0x1d98
#define mmOTG4_OTG_RANGE_TIMING_INT_STATUS_BASE_IDX 2
#define mmOTG4_OTG_DRR_CONTROL 0x1d99
#define mmOTG4_OTG_DRR_CONTROL_BASE_IDX 2
#define mmOTG4_OTG_REQUEST_CONTROL 0x1d9a
#define mmOTG4_OTG_REQUEST_CONTROL_BASE_IDX 2
#define mmOTG4_OTG_SPARE_REGISTER 0x1d9b
#define mmOTG4_OTG_SPARE_REGISTER_BASE_IDX 2
// addressBlock: dce_dc_optc_otg5_dispdec
// base address: 0xa00
#define mmOTG5_OTG_H_TOTAL 0x1daa
#define mmOTG5_OTG_H_TOTAL_BASE_IDX 2
#define mmOTG5_OTG_H_BLANK_START_END 0x1dab
#define mmOTG5_OTG_H_BLANK_START_END_BASE_IDX 2
#define mmOTG5_OTG_H_SYNC_A 0x1dac
#define mmOTG5_OTG_H_SYNC_A_BASE_IDX 2
#define mmOTG5_OTG_H_SYNC_A_CNTL 0x1dad
#define mmOTG5_OTG_H_SYNC_A_CNTL_BASE_IDX 2
#define mmOTG5_OTG_H_TIMING_CNTL 0x1dae
#define mmOTG5_OTG_H_TIMING_CNTL_BASE_IDX 2
#define mmOTG5_OTG_V_TOTAL 0x1daf
#define mmOTG5_OTG_V_TOTAL_BASE_IDX 2
#define mmOTG5_OTG_V_TOTAL_MIN 0x1db0
#define mmOTG5_OTG_V_TOTAL_MIN_BASE_IDX 2
#define mmOTG5_OTG_V_TOTAL_MAX 0x1db1
#define mmOTG5_OTG_V_TOTAL_MAX_BASE_IDX 2
#define mmOTG5_OTG_V_TOTAL_MID 0x1db2
#define mmOTG5_OTG_V_TOTAL_MID_BASE_IDX 2
#define mmOTG5_OTG_V_TOTAL_CONTROL 0x1db3
#define mmOTG5_OTG_V_TOTAL_CONTROL_BASE_IDX 2
#define mmOTG5_OTG_V_TOTAL_INT_STATUS 0x1db4
#define mmOTG5_OTG_V_TOTAL_INT_STATUS_BASE_IDX 2
#define mmOTG5_OTG_VSYNC_NOM_INT_STATUS 0x1db5
#define mmOTG5_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX 2
#define mmOTG5_OTG_V_BLANK_START_END 0x1db6
#define mmOTG5_OTG_V_BLANK_START_END_BASE_IDX 2
#define mmOTG5_OTG_V_SYNC_A 0x1db7
#define mmOTG5_OTG_V_SYNC_A_BASE_IDX 2
#define mmOTG5_OTG_V_SYNC_A_CNTL 0x1db8
#define mmOTG5_OTG_V_SYNC_A_CNTL_BASE_IDX 2
#define mmOTG5_OTG_TRIGA_CNTL 0x1db9
#define mmOTG5_OTG_TRIGA_CNTL_BASE_IDX 2
#define mmOTG5_OTG_TRIGA_MANUAL_TRIG 0x1dba
#define mmOTG5_OTG_TRIGA_MANUAL_TRIG_BASE_IDX 2
#define mmOTG5_OTG_TRIGB_CNTL 0x1dbb
#define mmOTG5_OTG_TRIGB_CNTL_BASE_IDX 2
#define mmOTG5_OTG_TRIGB_MANUAL_TRIG 0x1dbc
#define mmOTG5_OTG_TRIGB_MANUAL_TRIG_BASE_IDX 2
#define mmOTG5_OTG_FORCE_COUNT_NOW_CNTL 0x1dbd
#define mmOTG5_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX 2
#define mmOTG5_OTG_FLOW_CONTROL 0x1dbe
#define mmOTG5_OTG_FLOW_CONTROL_BASE_IDX 2
#define mmOTG5_OTG_STEREO_FORCE_NEXT_EYE 0x1dbf
#define mmOTG5_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX 2
#define mmOTG5_OTG_AVSYNC_COUNTER 0x1dc0
#define mmOTG5_OTG_AVSYNC_COUNTER_BASE_IDX 2
#define mmOTG5_OTG_CONTROL 0x1dc1
#define mmOTG5_OTG_CONTROL_BASE_IDX 2
#define mmOTG5_OTG_BLANK_CONTROL 0x1dc2
#define mmOTG5_OTG_BLANK_CONTROL_BASE_IDX 2
#define mmOTG5_OTG_PIPE_ABORT_CONTROL 0x1dc3
#define mmOTG5_OTG_PIPE_ABORT_CONTROL_BASE_IDX 2
#define mmOTG5_OTG_INTERLACE_CONTROL 0x1dc4
#define mmOTG5_OTG_INTERLACE_CONTROL_BASE_IDX 2
#define mmOTG5_OTG_INTERLACE_STATUS 0x1dc5
#define mmOTG5_OTG_INTERLACE_STATUS_BASE_IDX 2
#define mmOTG5_OTG_FIELD_INDICATION_CONTROL 0x1dc6
#define mmOTG5_OTG_FIELD_INDICATION_CONTROL_BASE_IDX 2
#define mmOTG5_OTG_PIXEL_DATA_READBACK0 0x1dc7
#define mmOTG5_OTG_PIXEL_DATA_READBACK0_BASE_IDX 2
#define mmOTG5_OTG_PIXEL_DATA_READBACK1 0x1dc8
#define mmOTG5_OTG_PIXEL_DATA_READBACK1_BASE_IDX 2
#define mmOTG5_OTG_STATUS 0x1dc9
#define mmOTG5_OTG_STATUS_BASE_IDX 2
#define mmOTG5_OTG_STATUS_POSITION 0x1dca
#define mmOTG5_OTG_STATUS_POSITION_BASE_IDX 2
#define mmOTG5_OTG_NOM_VERT_POSITION 0x1dcb
#define mmOTG5_OTG_NOM_VERT_POSITION_BASE_IDX 2
#define mmOTG5_OTG_STATUS_FRAME_COUNT 0x1dcc
#define mmOTG5_OTG_STATUS_FRAME_COUNT_BASE_IDX 2
#define mmOTG5_OTG_STATUS_VF_COUNT 0x1dcd
#define mmOTG5_OTG_STATUS_VF_COUNT_BASE_IDX 2
#define mmOTG5_OTG_STATUS_HV_COUNT 0x1dce
#define mmOTG5_OTG_STATUS_HV_COUNT_BASE_IDX 2
#define mmOTG5_OTG_COUNT_CONTROL 0x1dcf
#define mmOTG5_OTG_COUNT_CONTROL_BASE_IDX 2
#define mmOTG5_OTG_COUNT_RESET 0x1dd0
#define mmOTG5_OTG_COUNT_RESET_BASE_IDX 2
#define mmOTG5_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1dd1
#define mmOTG5_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2
#define mmOTG5_OTG_VERT_SYNC_CONTROL 0x1dd2
#define mmOTG5_OTG_VERT_SYNC_CONTROL_BASE_IDX 2
#define mmOTG5_OTG_STEREO_STATUS 0x1dd3
#define mmOTG5_OTG_STEREO_STATUS_BASE_IDX 2
#define mmOTG5_OTG_STEREO_CONTROL 0x1dd4
#define mmOTG5_OTG_STEREO_CONTROL_BASE_IDX 2
#define mmOTG5_OTG_SNAPSHOT_STATUS 0x1dd5
#define mmOTG5_OTG_SNAPSHOT_STATUS_BASE_IDX 2
#define mmOTG5_OTG_SNAPSHOT_CONTROL 0x1dd6
#define mmOTG5_OTG_SNAPSHOT_CONTROL_BASE_IDX 2
#define mmOTG5_OTG_SNAPSHOT_POSITION 0x1dd7
#define mmOTG5_OTG_SNAPSHOT_POSITION_BASE_IDX 2
#define mmOTG5_OTG_SNAPSHOT_FRAME 0x1dd8
#define mmOTG5_OTG_SNAPSHOT_FRAME_BASE_IDX 2
#define mmOTG5_OTG_INTERRUPT_CONTROL 0x1dd9
#define mmOTG5_OTG_INTERRUPT_CONTROL_BASE_IDX 2
#define mmOTG5_OTG_UPDATE_LOCK 0x1dda
#define mmOTG5_OTG_UPDATE_LOCK_BASE_IDX 2
#define mmOTG5_OTG_DOUBLE_BUFFER_CONTROL 0x1ddb
#define mmOTG5_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX 2
#define mmOTG5_OTG_TEST_PATTERN_CONTROL 0x1ddc
#define mmOTG5_OTG_TEST_PATTERN_CONTROL_BASE_IDX 2
#define mmOTG5_OTG_TEST_PATTERN_PARAMETERS 0x1ddd
#define mmOTG5_OTG_TEST_PATTERN_PARAMETERS_BASE_IDX 2
#define mmOTG5_OTG_TEST_PATTERN_COLOR 0x1dde
#define mmOTG5_OTG_TEST_PATTERN_COLOR_BASE_IDX 2
#define mmOTG5_OTG_MASTER_EN 0x1ddf
#define mmOTG5_OTG_MASTER_EN_BASE_IDX 2
#define mmOTG5_OTG_BLANK_DATA_COLOR 0x1de1
#define mmOTG5_OTG_BLANK_DATA_COLOR_BASE_IDX 2
#define mmOTG5_OTG_BLANK_DATA_COLOR_EXT 0x1de2
#define mmOTG5_OTG_BLANK_DATA_COLOR_EXT_BASE_IDX 2
#define mmOTG5_OTG_BLACK_COLOR 0x1de3
#define mmOTG5_OTG_BLACK_COLOR_BASE_IDX 2
#define mmOTG5_OTG_BLACK_COLOR_EXT 0x1de4
#define mmOTG5_OTG_BLACK_COLOR_EXT_BASE_IDX 2
#define mmOTG5_OTG_VERTICAL_INTERRUPT0_POSITION 0x1de5
#define mmOTG5_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2
#define mmOTG5_OTG_VERTICAL_INTERRUPT0_CONTROL 0x1de6
#define mmOTG5_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2
#define mmOTG5_OTG_VERTICAL_INTERRUPT1_POSITION 0x1de7
#define mmOTG5_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2
#define mmOTG5_OTG_VERTICAL_INTERRUPT1_CONTROL 0x1de8
#define mmOTG5_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2
#define mmOTG5_OTG_VERTICAL_INTERRUPT2_POSITION 0x1de9
#define mmOTG5_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2
#define mmOTG5_OTG_VERTICAL_INTERRUPT2_CONTROL 0x1dea
#define mmOTG5_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2
#define mmOTG5_OTG_CRC_CNTL 0x1deb
#define mmOTG5_OTG_CRC_CNTL_BASE_IDX 2
#define mmOTG5_OTG_CRC0_WINDOWA_X_CONTROL 0x1dec
#define mmOTG5_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2
#define mmOTG5_OTG_CRC0_WINDOWA_Y_CONTROL 0x1ded
#define mmOTG5_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2
#define mmOTG5_OTG_CRC0_WINDOWB_X_CONTROL 0x1dee
#define mmOTG5_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2
#define mmOTG5_OTG_CRC0_WINDOWB_Y_CONTROL 0x1def
#define mmOTG5_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2
#define mmOTG5_OTG_CRC0_DATA_RG 0x1df0
#define mmOTG5_OTG_CRC0_DATA_RG_BASE_IDX 2
#define mmOTG5_OTG_CRC0_DATA_B 0x1df1
#define mmOTG5_OTG_CRC0_DATA_B_BASE_IDX 2
#define mmOTG5_OTG_CRC1_WINDOWA_X_CONTROL 0x1df2
#define mmOTG5_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2
#define mmOTG5_OTG_CRC1_WINDOWA_Y_CONTROL 0x1df3
#define mmOTG5_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2
#define mmOTG5_OTG_CRC1_WINDOWB_X_CONTROL 0x1df4
#define mmOTG5_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2
#define mmOTG5_OTG_CRC1_WINDOWB_Y_CONTROL 0x1df5
#define mmOTG5_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2
#define mmOTG5_OTG_CRC1_DATA_RG 0x1df6
#define mmOTG5_OTG_CRC1_DATA_RG_BASE_IDX 2
#define mmOTG5_OTG_CRC1_DATA_B 0x1df7
#define mmOTG5_OTG_CRC1_DATA_B_BASE_IDX 2
#define mmOTG5_OTG_CRC2_DATA_RG 0x1df8
#define mmOTG5_OTG_CRC2_DATA_RG_BASE_IDX 2
#define mmOTG5_OTG_CRC2_DATA_B 0x1df9
#define mmOTG5_OTG_CRC2_DATA_B_BASE_IDX 2
#define mmOTG5_OTG_CRC3_DATA_RG 0x1dfa
#define mmOTG5_OTG_CRC3_DATA_RG_BASE_IDX 2
#define mmOTG5_OTG_CRC3_DATA_B 0x1dfb
#define mmOTG5_OTG_CRC3_DATA_B_BASE_IDX 2
#define mmOTG5_OTG_CRC_SIG_RED_GREEN_MASK 0x1dfc
#define mmOTG5_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2
#define mmOTG5_OTG_CRC_SIG_BLUE_CONTROL_MASK 0x1dfd
#define mmOTG5_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2
#define mmOTG5_OTG_STATIC_SCREEN_CONTROL 0x1e04
#define mmOTG5_OTG_STATIC_SCREEN_CONTROL_BASE_IDX 2
#define mmOTG5_OTG_3D_STRUCTURE_CONTROL 0x1e05
#define mmOTG5_OTG_3D_STRUCTURE_CONTROL_BASE_IDX 2
#define mmOTG5_OTG_GSL_VSYNC_GAP 0x1e06
#define mmOTG5_OTG_GSL_VSYNC_GAP_BASE_IDX 2
#define mmOTG5_OTG_MASTER_UPDATE_MODE 0x1e07
#define mmOTG5_OTG_MASTER_UPDATE_MODE_BASE_IDX 2
#define mmOTG5_OTG_CLOCK_CONTROL 0x1e08
#define mmOTG5_OTG_CLOCK_CONTROL_BASE_IDX 2
#define mmOTG5_OTG_VSTARTUP_PARAM 0x1e09
#define mmOTG5_OTG_VSTARTUP_PARAM_BASE_IDX 2
#define mmOTG5_OTG_VUPDATE_PARAM 0x1e0a
#define mmOTG5_OTG_VUPDATE_PARAM_BASE_IDX 2
#define mmOTG5_OTG_VREADY_PARAM 0x1e0b
#define mmOTG5_OTG_VREADY_PARAM_BASE_IDX 2
#define mmOTG5_OTG_GLOBAL_SYNC_STATUS 0x1e0c
#define mmOTG5_OTG_GLOBAL_SYNC_STATUS_BASE_IDX 2
#define mmOTG5_OTG_MASTER_UPDATE_LOCK 0x1e0d
#define mmOTG5_OTG_MASTER_UPDATE_LOCK_BASE_IDX 2
#define mmOTG5_OTG_GSL_CONTROL 0x1e0e
#define mmOTG5_OTG_GSL_CONTROL_BASE_IDX 2
#define mmOTG5_OTG_GSL_WINDOW_X 0x1e0f
#define mmOTG5_OTG_GSL_WINDOW_X_BASE_IDX 2
#define mmOTG5_OTG_GSL_WINDOW_Y 0x1e10
#define mmOTG5_OTG_GSL_WINDOW_Y_BASE_IDX 2
#define mmOTG5_OTG_VUPDATE_KEEPOUT 0x1e11
#define mmOTG5_OTG_VUPDATE_KEEPOUT_BASE_IDX 2
#define mmOTG5_OTG_GLOBAL_CONTROL0 0x1e12
#define mmOTG5_OTG_GLOBAL_CONTROL0_BASE_IDX 2
#define mmOTG5_OTG_GLOBAL_CONTROL1 0x1e13
#define mmOTG5_OTG_GLOBAL_CONTROL1_BASE_IDX 2
#define mmOTG5_OTG_GLOBAL_CONTROL2 0x1e14
#define mmOTG5_OTG_GLOBAL_CONTROL2_BASE_IDX 2
#define mmOTG5_OTG_GLOBAL_CONTROL3 0x1e15
#define mmOTG5_OTG_GLOBAL_CONTROL3_BASE_IDX 2
#define mmOTG5_OTG_TRIG_MANUAL_CONTROL 0x1e16
#define mmOTG5_OTG_TRIG_MANUAL_CONTROL_BASE_IDX 2
#define mmOTG5_OTG_MANUAL_FLOW_CONTROL 0x1e17
#define mmOTG5_OTG_MANUAL_FLOW_CONTROL_BASE_IDX 2
#define mmOTG5_OTG_RANGE_TIMING_INT_STATUS 0x1e18
#define mmOTG5_OTG_RANGE_TIMING_INT_STATUS_BASE_IDX 2
#define mmOTG5_OTG_DRR_CONTROL 0x1e19
#define mmOTG5_OTG_DRR_CONTROL_BASE_IDX 2
#define mmOTG5_OTG_REQUEST_CONTROL 0x1e1a
#define mmOTG5_OTG_REQUEST_CONTROL_BASE_IDX 2
#define mmOTG5_OTG_SPARE_REGISTER 0x1e1b
#define mmOTG5_OTG_SPARE_REGISTER_BASE_IDX 2
// addressBlock: dce_dc_optc_optc_misc_dispdec
// base address: 0x0
#define mmDWB_SOURCE_SELECT 0x1e2a
#define mmDWB_SOURCE_SELECT_BASE_IDX 2
#define mmGSL_SOURCE_SELECT 0x1e2b
#define mmGSL_SOURCE_SELECT_BASE_IDX 2
#define mmOPTC_CLOCK_CONTROL 0x1e2c
#define mmOPTC_CLOCK_CONTROL_BASE_IDX 2
#define mmOPTC_MISC_SPARE_REGISTER 0x1e2d
#define mmOPTC_MISC_SPARE_REGISTER_BASE_IDX 2
// addressBlock: dce_dc_optc_optc_dcperfmon_dc_perfmon_dispdec
// base address: 0x79a8
#define mmDC_PERFMON18_PERFCOUNTER_CNTL 0x1e6a
#define mmDC_PERFMON18_PERFCOUNTER_CNTL_BASE_IDX 2
#define mmDC_PERFMON18_PERFCOUNTER_CNTL2 0x1e6b
#define mmDC_PERFMON18_PERFCOUNTER_CNTL2_BASE_IDX 2
#define mmDC_PERFMON18_PERFCOUNTER_STATE 0x1e6c
#define mmDC_PERFMON18_PERFCOUNTER_STATE_BASE_IDX 2
#define mmDC_PERFMON18_PERFMON_CNTL 0x1e6d
#define mmDC_PERFMON18_PERFMON_CNTL_BASE_IDX 2
#define mmDC_PERFMON18_PERFMON_CNTL2 0x1e6e
#define mmDC_PERFMON18_PERFMON_CNTL2_BASE_IDX 2
#define mmDC_PERFMON18_PERFMON_CVALUE_INT_MISC 0x1e6f
#define mmDC_PERFMON18_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
#define mmDC_PERFMON18_PERFMON_CVALUE_LOW 0x1e70
#define mmDC_PERFMON18_PERFMON_CVALUE_LOW_BASE_IDX 2
#define mmDC_PERFMON18_PERFMON_HI 0x1e71
#define mmDC_PERFMON18_PERFMON_HI_BASE_IDX 2
#define mmDC_PERFMON18_PERFMON_LOW 0x1e72
#define mmDC_PERFMON18_PERFMON_LOW_BASE_IDX 2
// addressBlock: dce_dc_dio_dac_dispdec
// base address: 0x0
#define mmDAC_ENABLE 0x1e76
#define mmDAC_ENABLE_BASE_IDX 2
#define mmDAC_SOURCE_SELECT 0x1e77
#define mmDAC_SOURCE_SELECT_BASE_IDX 2
#define mmDAC_CRC_EN 0x1e78
#define mmDAC_CRC_EN_BASE_IDX 2
#define mmDAC_CRC_CONTROL 0x1e79
#define mmDAC_CRC_CONTROL_BASE_IDX 2
#define mmDAC_CRC_SIG_RGB_MASK 0x1e7a
#define mmDAC_CRC_SIG_RGB_MASK_BASE_IDX 2
#define mmDAC_CRC_SIG_CONTROL_MASK 0x1e7b
#define mmDAC_CRC_SIG_CONTROL_MASK_BASE_IDX 2
#define mmDAC_CRC_SIG_RGB 0x1e7c
#define mmDAC_CRC_SIG_RGB_BASE_IDX 2
#define mmDAC_CRC_SIG_CONTROL 0x1e7d
#define mmDAC_CRC_SIG_CONTROL_BASE_IDX 2
#define mmDAC_SYNC_TRISTATE_CONTROL 0x1e7e
#define mmDAC_SYNC_TRISTATE_CONTROL_BASE_IDX 2
#define mmDAC_STEREOSYNC_SELECT 0x1e7f
#define mmDAC_STEREOSYNC_SELECT_BASE_IDX 2
#define mmDAC_AUTODETECT_CONTROL 0x1e80
#define mmDAC_AUTODETECT_CONTROL_BASE_IDX 2
#define mmDAC_AUTODETECT_CONTROL2 0x1e81
#define mmDAC_AUTODETECT_CONTROL2_BASE_IDX 2
#define mmDAC_AUTODETECT_CONTROL3 0x1e82
#define mmDAC_AUTODETECT_CONTROL3_BASE_IDX 2
#define mmDAC_AUTODETECT_STATUS 0x1e83
#define mmDAC_AUTODETECT_STATUS_BASE_IDX 2
#define mmDAC_AUTODETECT_INT_CONTROL 0x1e84
#define mmDAC_AUTODETECT_INT_CONTROL_BASE_IDX 2
#define mmDAC_FORCE_OUTPUT_CNTL 0x1e85
#define mmDAC_FORCE_OUTPUT_CNTL_BASE_IDX 2
#define mmDAC_FORCE_DATA 0x1e86
#define mmDAC_FORCE_DATA_BASE_IDX 2
#define mmDAC_POWERDOWN 0x1e87
#define mmDAC_POWERDOWN_BASE_IDX 2
#define mmDAC_CONTROL 0x1e88
#define mmDAC_CONTROL_BASE_IDX 2
#define mmDAC_COMPARATOR_ENABLE 0x1e89
#define mmDAC_COMPARATOR_ENABLE_BASE_IDX 2
#define mmDAC_COMPARATOR_OUTPUT 0x1e8a
#define mmDAC_COMPARATOR_OUTPUT_BASE_IDX 2
#define mmDAC_PWR_CNTL 0x1e8b
#define mmDAC_PWR_CNTL_BASE_IDX 2
#define mmDAC_DFT_CONFIG 0x1e8c
#define mmDAC_DFT_CONFIG_BASE_IDX 2
#define mmDAC_FIFO_STATUS 0x1e8d
#define mmDAC_FIFO_STATUS_BASE_IDX 2
// addressBlock: dce_dc_dio_dout_i2c_dispdec
// base address: 0x0
#define mmDC_I2C_CONTROL 0x1e98
#define mmDC_I2C_CONTROL_BASE_IDX 2
#define mmDC_I2C_ARBITRATION 0x1e99
#define mmDC_I2C_ARBITRATION_BASE_IDX 2
#define mmDC_I2C_INTERRUPT_CONTROL 0x1e9a
#define mmDC_I2C_INTERRUPT_CONTROL_BASE_IDX 2
#define mmDC_I2C_SW_STATUS 0x1e9b
#define mmDC_I2C_SW_STATUS_BASE_IDX 2
#define mmDC_I2C_DDC1_HW_STATUS 0x1e9c
#define mmDC_I2C_DDC1_HW_STATUS_BASE_IDX 2
#define mmDC_I2C_DDC2_HW_STATUS 0x1e9d
#define mmDC_I2C_DDC2_HW_STATUS_BASE_IDX 2
#define mmDC_I2C_DDC3_HW_STATUS 0x1e9e
#define mmDC_I2C_DDC3_HW_STATUS_BASE_IDX 2
#define mmDC_I2C_DDC4_HW_STATUS 0x1e9f
#define mmDC_I2C_DDC4_HW_STATUS_BASE_IDX 2
#define mmDC_I2C_DDC5_HW_STATUS 0x1ea0
#define mmDC_I2C_DDC5_HW_STATUS_BASE_IDX 2
#define mmDC_I2C_DDC6_HW_STATUS 0x1ea1
#define mmDC_I2C_DDC6_HW_STATUS_BASE_IDX 2
#define mmDC_I2C_DDC1_SPEED 0x1ea2
#define mmDC_I2C_DDC1_SPEED_BASE_IDX 2
#define mmDC_I2C_DDC1_SETUP 0x1ea3
#define mmDC_I2C_DDC1_SETUP_BASE_IDX 2
#define mmDC_I2C_DDC2_SPEED 0x1ea4
#define mmDC_I2C_DDC2_SPEED_BASE_IDX 2
#define mmDC_I2C_DDC2_SETUP 0x1ea5
#define mmDC_I2C_DDC2_SETUP_BASE_IDX 2
#define mmDC_I2C_DDC3_SPEED 0x1ea6
#define mmDC_I2C_DDC3_SPEED_BASE_IDX 2
#define mmDC_I2C_DDC3_SETUP 0x1ea7
#define mmDC_I2C_DDC3_SETUP_BASE_IDX 2
#define mmDC_I2C_DDC4_SPEED 0x1ea8
#define mmDC_I2C_DDC4_SPEED_BASE_IDX 2
#define mmDC_I2C_DDC4_SETUP 0x1ea9
#define mmDC_I2C_DDC4_SETUP_BASE_IDX 2
#define mmDC_I2C_DDC5_SPEED 0x1eaa
#define mmDC_I2C_DDC5_SPEED_BASE_IDX 2
#define mmDC_I2C_DDC5_SETUP 0x1eab
#define mmDC_I2C_DDC5_SETUP_BASE_IDX 2
#define mmDC_I2C_DDC6_SPEED 0x1eac
#define mmDC_I2C_DDC6_SPEED_BASE_IDX 2
#define mmDC_I2C_DDC6_SETUP 0x1ead
#define mmDC_I2C_DDC6_SETUP_BASE_IDX 2
#define mmDC_I2C_TRANSACTION0 0x1eae
#define mmDC_I2C_TRANSACTION0_BASE_IDX 2
#define mmDC_I2C_TRANSACTION1 0x1eaf
#define mmDC_I2C_TRANSACTION1_BASE_IDX 2
#define mmDC_I2C_TRANSACTION2 0x1eb0
#define mmDC_I2C_TRANSACTION2_BASE_IDX 2
#define mmDC_I2C_TRANSACTION3 0x1eb1
#define mmDC_I2C_TRANSACTION3_BASE_IDX 2
#define mmDC_I2C_DATA 0x1eb2
#define mmDC_I2C_DATA_BASE_IDX 2
#define mmDC_I2C_DDCVGA_HW_STATUS 0x1eb3
#define mmDC_I2C_DDCVGA_HW_STATUS_BASE_IDX 2
#define mmDC_I2C_DDCVGA_SPEED 0x1eb4
#define mmDC_I2C_DDCVGA_SPEED_BASE_IDX 2
#define mmDC_I2C_DDCVGA_SETUP 0x1eb5
#define mmDC_I2C_DDCVGA_SETUP_BASE_IDX 2
#define mmDC_I2C_EDID_DETECT_CTRL 0x1eb6
#define mmDC_I2C_EDID_DETECT_CTRL_BASE_IDX 2
#define mmDC_I2C_READ_REQUEST_INTERRUPT 0x1eb7
#define mmDC_I2C_READ_REQUEST_INTERRUPT_BASE_IDX 2
// addressBlock: dce_dc_dio_generic_i2c_dispdec
// base address: 0x0
#define mmGENERIC_I2C_CONTROL 0x1eb8
#define mmGENERIC_I2C_CONTROL_BASE_IDX 2
#define mmGENERIC_I2C_INTERRUPT_CONTROL 0x1eb9
#define mmGENERIC_I2C_INTERRUPT_CONTROL_BASE_IDX 2
#define mmGENERIC_I2C_STATUS 0x1eba
#define mmGENERIC_I2C_STATUS_BASE_IDX 2
#define mmGENERIC_I2C_SPEED 0x1ebb
#define mmGENERIC_I2C_SPEED_BASE_IDX 2
#define mmGENERIC_I2C_SETUP 0x1ebc
#define mmGENERIC_I2C_SETUP_BASE_IDX 2
#define mmGENERIC_I2C_TRANSACTION 0x1ebd
#define mmGENERIC_I2C_TRANSACTION_BASE_IDX 2
#define mmGENERIC_I2C_DATA 0x1ebe
#define mmGENERIC_I2C_DATA_BASE_IDX 2
#define mmGENERIC_I2C_PIN_SELECTION 0x1ebf
#define mmGENERIC_I2C_PIN_SELECTION_BASE_IDX 2
// addressBlock: dce_dc_dio_dio_misc_dispdec
// base address: 0x0
#define mmDIO_SCRATCH0 0x1eca
#define mmDIO_SCRATCH0_BASE_IDX 2
#define mmDIO_SCRATCH1 0x1ecb
#define mmDIO_SCRATCH1_BASE_IDX 2
#define mmDIO_SCRATCH2 0x1ecc
#define mmDIO_SCRATCH2_BASE_IDX 2
#define mmDIO_SCRATCH3 0x1ecd
#define mmDIO_SCRATCH3_BASE_IDX 2
#define mmDIO_SCRATCH4 0x1ece
#define mmDIO_SCRATCH4_BASE_IDX 2
#define mmDIO_SCRATCH5 0x1ecf
#define mmDIO_SCRATCH5_BASE_IDX 2
#define mmDIO_SCRATCH6 0x1ed0
#define mmDIO_SCRATCH6_BASE_IDX 2
#define mmDIO_SCRATCH7 0x1ed1
#define mmDIO_SCRATCH7_BASE_IDX 2
#define mmDCE_VCE_CONTROL 0x1ed2
#define mmDCE_VCE_CONTROL_BASE_IDX 2
#define mmDIO_MEM_PWR_STATUS 0x1edd
#define mmDIO_MEM_PWR_STATUS_BASE_IDX 2
#define mmDIO_MEM_PWR_CTRL 0x1ede
#define mmDIO_MEM_PWR_CTRL_BASE_IDX 2
#define mmDIO_MEM_PWR_CTRL2 0x1edf
#define mmDIO_MEM_PWR_CTRL2_BASE_IDX 2
#define mmDIO_CLK_CNTL 0x1ee0
#define mmDIO_CLK_CNTL_BASE_IDX 2
#define mmDIO_POWER_MANAGEMENT_CNTL 0x1ee4
#define mmDIO_POWER_MANAGEMENT_CNTL_BASE_IDX 2
#define mmDIO_STEREOSYNC_SEL 0x1eea
#define mmDIO_STEREOSYNC_SEL_BASE_IDX 2
#define mmDIO_SOFT_RESET 0x1eed
#define mmDIO_SOFT_RESET_BASE_IDX 2
#define mmDIG_SOFT_RESET 0x1eee
#define mmDIG_SOFT_RESET_BASE_IDX 2
#define mmDIO_MEM_PWR_STATUS1 0x1ef0
#define mmDIO_MEM_PWR_STATUS1_BASE_IDX 2
#define mmDIO_CLK_CNTL2 0x1ef2
#define mmDIO_CLK_CNTL2_BASE_IDX 2
#define mmDIO_CLK_CNTL3 0x1ef3
#define mmDIO_CLK_CNTL3_BASE_IDX 2
#define mmDIO_HDMI_RXSTATUS_TIMER_CONTROL 0x1eff
#define mmDIO_HDMI_RXSTATUS_TIMER_CONTROL_BASE_IDX 2
#define mmDIO_PSP_INTERRUPT_STATUS 0x1f00
#define mmDIO_PSP_INTERRUPT_STATUS_BASE_IDX 2
#define mmDIO_PSP_INTERRUPT_CLEAR 0x1f01
#define mmDIO_PSP_INTERRUPT_CLEAR_BASE_IDX 2
#define mmDIO_GENERIC_INTERRUPT_MESSAGE 0x1f02
#define mmDIO_GENERIC_INTERRUPT_MESSAGE_BASE_IDX 2
#define mmDIO_GENERIC_INTERRUPT_CLEAR 0x1f03
#define mmDIO_GENERIC_INTERRUPT_CLEAR_BASE_IDX 2
// addressBlock: dce_dc_dio_hpd0_dispdec
// base address: 0x0
#define mmHPD0_DC_HPD_INT_STATUS 0x1f14
#define mmHPD0_DC_HPD_INT_STATUS_BASE_IDX 2
#define mmHPD0_DC_HPD_INT_CONTROL 0x1f15
#define mmHPD0_DC_HPD_INT_CONTROL_BASE_IDX 2
#define mmHPD0_DC_HPD_CONTROL 0x1f16
#define mmHPD0_DC_HPD_CONTROL_BASE_IDX 2
#define mmHPD0_DC_HPD_FAST_TRAIN_CNTL 0x1f17
#define mmHPD0_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2
#define mmHPD0_DC_HPD_TOGGLE_FILT_CNTL 0x1f18
#define mmHPD0_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2
// addressBlock: dce_dc_dio_hpd1_dispdec
// base address: 0x20
#define mmHPD1_DC_HPD_INT_STATUS 0x1f1c
#define mmHPD1_DC_HPD_INT_STATUS_BASE_IDX 2
#define mmHPD1_DC_HPD_INT_CONTROL 0x1f1d
#define mmHPD1_DC_HPD_INT_CONTROL_BASE_IDX 2
#define mmHPD1_DC_HPD_CONTROL 0x1f1e
#define mmHPD1_DC_HPD_CONTROL_BASE_IDX 2
#define mmHPD1_DC_HPD_FAST_TRAIN_CNTL 0x1f1f
#define mmHPD1_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2
#define mmHPD1_DC_HPD_TOGGLE_FILT_CNTL 0x1f20
#define mmHPD1_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2
// addressBlock: dce_dc_dio_hpd2_dispdec
// base address: 0x40
#define mmHPD2_DC_HPD_INT_STATUS 0x1f24
#define mmHPD2_DC_HPD_INT_STATUS_BASE_IDX 2
#define mmHPD2_DC_HPD_INT_CONTROL 0x1f25
#define mmHPD2_DC_HPD_INT_CONTROL_BASE_IDX 2
#define mmHPD2_DC_HPD_CONTROL 0x1f26
#define mmHPD2_DC_HPD_CONTROL_BASE_IDX 2
#define mmHPD2_DC_HPD_FAST_TRAIN_CNTL 0x1f27
#define mmHPD2_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2
#define mmHPD2_DC_HPD_TOGGLE_FILT_CNTL 0x1f28
#define mmHPD2_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2
// addressBlock: dce_dc_dio_hpd3_dispdec
// base address: 0x60
#define mmHPD3_DC_HPD_INT_STATUS 0x1f2c
#define mmHPD3_DC_HPD_INT_STATUS_BASE_IDX 2
#define mmHPD3_DC_HPD_INT_CONTROL 0x1f2d
#define mmHPD3_DC_HPD_INT_CONTROL_BASE_IDX 2
#define mmHPD3_DC_HPD_CONTROL 0x1f2e
#define mmHPD3_DC_HPD_CONTROL_BASE_IDX 2
#define mmHPD3_DC_HPD_FAST_TRAIN_CNTL 0x1f2f
#define mmHPD3_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2
#define mmHPD3_DC_HPD_TOGGLE_FILT_CNTL 0x1f30
#define mmHPD3_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2
// addressBlock: dce_dc_dio_hpd4_dispdec
// base address: 0x80
#define mmHPD4_DC_HPD_INT_STATUS 0x1f34
#define mmHPD4_DC_HPD_INT_STATUS_BASE_IDX 2
#define mmHPD4_DC_HPD_INT_CONTROL 0x1f35
#define mmHPD4_DC_HPD_INT_CONTROL_BASE_IDX 2
#define mmHPD4_DC_HPD_CONTROL 0x1f36
#define mmHPD4_DC_HPD_CONTROL_BASE_IDX 2
#define mmHPD4_DC_HPD_FAST_TRAIN_CNTL 0x1f37
#define mmHPD4_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2
#define mmHPD4_DC_HPD_TOGGLE_FILT_CNTL 0x1f38
#define mmHPD4_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2
// addressBlock: dce_dc_dio_hpd5_dispdec
// base address: 0xa0
#define mmHPD5_DC_HPD_INT_STATUS 0x1f3c
#define mmHPD5_DC_HPD_INT_STATUS_BASE_IDX 2
#define mmHPD5_DC_HPD_INT_CONTROL 0x1f3d
#define mmHPD5_DC_HPD_INT_CONTROL_BASE_IDX 2
#define mmHPD5_DC_HPD_CONTROL 0x1f3e
#define mmHPD5_DC_HPD_CONTROL_BASE_IDX 2
#define mmHPD5_DC_HPD_FAST_TRAIN_CNTL 0x1f3f
#define mmHPD5_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2
#define mmHPD5_DC_HPD_TOGGLE_FILT_CNTL 0x1f40
#define mmHPD5_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2
// addressBlock: dce_dc_dio_dio_dcperfmon_dc_perfmon_dispdec
// base address: 0x7d10
#define mmDC_PERFMON19_PERFCOUNTER_CNTL 0x1f44
#define mmDC_PERFMON19_PERFCOUNTER_CNTL_BASE_IDX 2
#define mmDC_PERFMON19_PERFCOUNTER_CNTL2 0x1f45
#define mmDC_PERFMON19_PERFCOUNTER_CNTL2_BASE_IDX 2
#define mmDC_PERFMON19_PERFCOUNTER_STATE 0x1f46
#define mmDC_PERFMON19_PERFCOUNTER_STATE_BASE_IDX 2
#define mmDC_PERFMON19_PERFMON_CNTL 0x1f47
#define mmDC_PERFMON19_PERFMON_CNTL_BASE_IDX 2
#define mmDC_PERFMON19_PERFMON_CNTL2 0x1f48
#define mmDC_PERFMON19_PERFMON_CNTL2_BASE_IDX 2
#define mmDC_PERFMON19_PERFMON_CVALUE_INT_MISC 0x1f49
#define mmDC_PERFMON19_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
#define mmDC_PERFMON19_PERFMON_CVALUE_LOW 0x1f4a
#define mmDC_PERFMON19_PERFMON_CVALUE_LOW_BASE_IDX 2
#define mmDC_PERFMON19_PERFMON_HI 0x1f4b
#define mmDC_PERFMON19_PERFMON_HI_BASE_IDX 2
#define mmDC_PERFMON19_PERFMON_LOW 0x1f4c
#define mmDC_PERFMON19_PERFMON_LOW_BASE_IDX 2
// addressBlock: dce_dc_dio_dp_aux0_dispdec
// base address: 0x0
#define mmDP_AUX0_AUX_CONTROL 0x1f50
#define mmDP_AUX0_AUX_CONTROL_BASE_IDX 2
#define mmDP_AUX0_AUX_SW_CONTROL 0x1f51
#define mmDP_AUX0_AUX_SW_CONTROL_BASE_IDX 2
#define mmDP_AUX0_AUX_ARB_CONTROL 0x1f52
#define mmDP_AUX0_AUX_ARB_CONTROL_BASE_IDX 2
#define mmDP_AUX0_AUX_INTERRUPT_CONTROL 0x1f53
#define mmDP_AUX0_AUX_INTERRUPT_CONTROL_BASE_IDX 2
#define mmDP_AUX0_AUX_SW_STATUS 0x1f54
#define mmDP_AUX0_AUX_SW_STATUS_BASE_IDX 2
#define mmDP_AUX0_AUX_LS_STATUS 0x1f55
#define mmDP_AUX0_AUX_LS_STATUS_BASE_IDX 2
#define mmDP_AUX0_AUX_SW_DATA 0x1f56
#define mmDP_AUX0_AUX_SW_DATA_BASE_IDX 2
#define mmDP_AUX0_AUX_LS_DATA 0x1f57
#define mmDP_AUX0_AUX_LS_DATA_BASE_IDX 2
#define mmDP_AUX0_AUX_DPHY_TX_REF_CONTROL 0x1f58
#define mmDP_AUX0_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2
#define mmDP_AUX0_AUX_DPHY_TX_CONTROL 0x1f59
#define mmDP_AUX0_AUX_DPHY_TX_CONTROL_BASE_IDX 2
#define mmDP_AUX0_AUX_DPHY_RX_CONTROL0 0x1f5a
#define mmDP_AUX0_AUX_DPHY_RX_CONTROL0_BASE_IDX 2
#define mmDP_AUX0_AUX_DPHY_RX_CONTROL1 0x1f5b
#define mmDP_AUX0_AUX_DPHY_RX_CONTROL1_BASE_IDX 2
#define mmDP_AUX0_AUX_DPHY_TX_STATUS 0x1f5c
#define mmDP_AUX0_AUX_DPHY_TX_STATUS_BASE_IDX 2
#define mmDP_AUX0_AUX_DPHY_RX_STATUS 0x1f5d
#define mmDP_AUX0_AUX_DPHY_RX_STATUS_BASE_IDX 2
#define mmDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL 0x1f5f
#define mmDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2
#define mmDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1f60
#define mmDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2
#define mmDP_AUX0_AUX_GTC_SYNC_STATUS 0x1f61
#define mmDP_AUX0_AUX_GTC_SYNC_STATUS_BASE_IDX 2
// addressBlock: dce_dc_dio_dp_aux1_dispdec
// base address: 0x70
#define mmDP_AUX1_AUX_CONTROL 0x1f6c
#define mmDP_AUX1_AUX_CONTROL_BASE_IDX 2
#define mmDP_AUX1_AUX_SW_CONTROL 0x1f6d
#define mmDP_AUX1_AUX_SW_CONTROL_BASE_IDX 2
#define mmDP_AUX1_AUX_ARB_CONTROL 0x1f6e
#define mmDP_AUX1_AUX_ARB_CONTROL_BASE_IDX 2
#define mmDP_AUX1_AUX_INTERRUPT_CONTROL 0x1f6f
#define mmDP_AUX1_AUX_INTERRUPT_CONTROL_BASE_IDX 2
#define mmDP_AUX1_AUX_SW_STATUS 0x1f70
#define mmDP_AUX1_AUX_SW_STATUS_BASE_IDX 2
#define mmDP_AUX1_AUX_LS_STATUS 0x1f71
#define mmDP_AUX1_AUX_LS_STATUS_BASE_IDX 2
#define mmDP_AUX1_AUX_SW_DATA 0x1f72
#define mmDP_AUX1_AUX_SW_DATA_BASE_IDX 2
#define mmDP_AUX1_AUX_LS_DATA 0x1f73
#define mmDP_AUX1_AUX_LS_DATA_BASE_IDX 2
#define mmDP_AUX1_AUX_DPHY_TX_REF_CONTROL 0x1f74
#define mmDP_AUX1_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2
#define mmDP_AUX1_AUX_DPHY_TX_CONTROL 0x1f75
#define mmDP_AUX1_AUX_DPHY_TX_CONTROL_BASE_IDX 2
#define mmDP_AUX1_AUX_DPHY_RX_CONTROL0 0x1f76
#define mmDP_AUX1_AUX_DPHY_RX_CONTROL0_BASE_IDX 2
#define mmDP_AUX1_AUX_DPHY_RX_CONTROL1 0x1f77
#define mmDP_AUX1_AUX_DPHY_RX_CONTROL1_BASE_IDX 2
#define mmDP_AUX1_AUX_DPHY_TX_STATUS 0x1f78
#define mmDP_AUX1_AUX_DPHY_TX_STATUS_BASE_IDX 2
#define mmDP_AUX1_AUX_DPHY_RX_STATUS 0x1f79
#define mmDP_AUX1_AUX_DPHY_RX_STATUS_BASE_IDX 2
#define mmDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL 0x1f7b
#define mmDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2
#define mmDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1f7c
#define mmDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2
#define mmDP_AUX1_AUX_GTC_SYNC_STATUS 0x1f7d
#define mmDP_AUX1_AUX_GTC_SYNC_STATUS_BASE_IDX 2
// addressBlock: dce_dc_dio_dp_aux2_dispdec
// base address: 0xe0
#define mmDP_AUX2_AUX_CONTROL 0x1f88
#define mmDP_AUX2_AUX_CONTROL_BASE_IDX 2
#define mmDP_AUX2_AUX_SW_CONTROL 0x1f89
#define mmDP_AUX2_AUX_SW_CONTROL_BASE_IDX 2
#define mmDP_AUX2_AUX_ARB_CONTROL 0x1f8a
#define mmDP_AUX2_AUX_ARB_CONTROL_BASE_IDX 2
#define mmDP_AUX2_AUX_INTERRUPT_CONTROL 0x1f8b
#define mmDP_AUX2_AUX_INTERRUPT_CONTROL_BASE_IDX 2
#define mmDP_AUX2_AUX_SW_STATUS 0x1f8c
#define mmDP_AUX2_AUX_SW_STATUS_BASE_IDX 2
#define mmDP_AUX2_AUX_LS_STATUS 0x1f8d
#define mmDP_AUX2_AUX_LS_STATUS_BASE_IDX 2
#define mmDP_AUX2_AUX_SW_DATA 0x1f8e
#define mmDP_AUX2_AUX_SW_DATA_BASE_IDX 2
#define mmDP_AUX2_AUX_LS_DATA 0x1f8f
#define mmDP_AUX2_AUX_LS_DATA_BASE_IDX 2
#define mmDP_AUX2_AUX_DPHY_TX_REF_CONTROL 0x1f90
#define mmDP_AUX2_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2
#define mmDP_AUX2_AUX_DPHY_TX_CONTROL 0x1f91
#define mmDP_AUX2_AUX_DPHY_TX_CONTROL_BASE_IDX 2
#define mmDP_AUX2_AUX_DPHY_RX_CONTROL0 0x1f92
#define mmDP_AUX2_AUX_DPHY_RX_CONTROL0_BASE_IDX 2
#define mmDP_AUX2_AUX_DPHY_RX_CONTROL1 0x1f93
#define mmDP_AUX2_AUX_DPHY_RX_CONTROL1_BASE_IDX 2
#define mmDP_AUX2_AUX_DPHY_TX_STATUS 0x1f94
#define mmDP_AUX2_AUX_DPHY_TX_STATUS_BASE_IDX 2
#define mmDP_AUX2_AUX_DPHY_RX_STATUS 0x1f95
#define mmDP_AUX2_AUX_DPHY_RX_STATUS_BASE_IDX 2
#define mmDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL 0x1f97
#define mmDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2
#define mmDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1f98
#define mmDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2
#define mmDP_AUX2_AUX_GTC_SYNC_STATUS 0x1f99
#define mmDP_AUX2_AUX_GTC_SYNC_STATUS_BASE_IDX 2
// addressBlock: dce_dc_dio_dp_aux3_dispdec
// base address: 0x150
#define mmDP_AUX3_AUX_CONTROL 0x1fa4
#define mmDP_AUX3_AUX_CONTROL_BASE_IDX 2
#define mmDP_AUX3_AUX_SW_CONTROL 0x1fa5
#define mmDP_AUX3_AUX_SW_CONTROL_BASE_IDX 2
#define mmDP_AUX3_AUX_ARB_CONTROL 0x1fa6
#define mmDP_AUX3_AUX_ARB_CONTROL_BASE_IDX 2
#define mmDP_AUX3_AUX_INTERRUPT_CONTROL 0x1fa7
#define mmDP_AUX3_AUX_INTERRUPT_CONTROL_BASE_IDX 2
#define mmDP_AUX3_AUX_SW_STATUS 0x1fa8
#define mmDP_AUX3_AUX_SW_STATUS_BASE_IDX 2
#define mmDP_AUX3_AUX_LS_STATUS 0x1fa9
#define mmDP_AUX3_AUX_LS_STATUS_BASE_IDX 2
#define mmDP_AUX3_AUX_SW_DATA 0x1faa
#define mmDP_AUX3_AUX_SW_DATA_BASE_IDX 2
#define mmDP_AUX3_AUX_LS_DATA 0x1fab
#define mmDP_AUX3_AUX_LS_DATA_BASE_IDX 2
#define mmDP_AUX3_AUX_DPHY_TX_REF_CONTROL 0x1fac
#define mmDP_AUX3_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2
#define mmDP_AUX3_AUX_DPHY_TX_CONTROL 0x1fad
#define mmDP_AUX3_AUX_DPHY_TX_CONTROL_BASE_IDX 2
#define mmDP_AUX3_AUX_DPHY_RX_CONTROL0 0x1fae
#define mmDP_AUX3_AUX_DPHY_RX_CONTROL0_BASE_IDX 2
#define mmDP_AUX3_AUX_DPHY_RX_CONTROL1 0x1faf
#define mmDP_AUX3_AUX_DPHY_RX_CONTROL1_BASE_IDX 2
#define mmDP_AUX3_AUX_DPHY_TX_STATUS 0x1fb0
#define mmDP_AUX3_AUX_DPHY_TX_STATUS_BASE_IDX 2
#define mmDP_AUX3_AUX_DPHY_RX_STATUS 0x1fb1
#define mmDP_AUX3_AUX_DPHY_RX_STATUS_BASE_IDX 2
#define mmDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL 0x1fb3
#define mmDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2
#define mmDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1fb4
#define mmDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2
#define mmDP_AUX3_AUX_GTC_SYNC_STATUS 0x1fb5
#define mmDP_AUX3_AUX_GTC_SYNC_STATUS_BASE_IDX 2
// addressBlock: dce_dc_dio_dp_aux4_dispdec
// base address: 0x1c0
#define mmDP_AUX4_AUX_CONTROL 0x1fc0
#define mmDP_AUX4_AUX_CONTROL_BASE_IDX 2
#define mmDP_AUX4_AUX_SW_CONTROL 0x1fc1
#define mmDP_AUX4_AUX_SW_CONTROL_BASE_IDX 2
#define mmDP_AUX4_AUX_ARB_CONTROL 0x1fc2
#define mmDP_AUX4_AUX_ARB_CONTROL_BASE_IDX 2
#define mmDP_AUX4_AUX_INTERRUPT_CONTROL 0x1fc3
#define mmDP_AUX4_AUX_INTERRUPT_CONTROL_BASE_IDX 2
#define mmDP_AUX4_AUX_SW_STATUS 0x1fc4
#define mmDP_AUX4_AUX_SW_STATUS_BASE_IDX 2
#define mmDP_AUX4_AUX_LS_STATUS 0x1fc5
#define mmDP_AUX4_AUX_LS_STATUS_BASE_IDX 2
#define mmDP_AUX4_AUX_SW_DATA 0x1fc6
#define mmDP_AUX4_AUX_SW_DATA_BASE_IDX 2
#define mmDP_AUX4_AUX_LS_DATA 0x1fc7
#define mmDP_AUX4_AUX_LS_DATA_BASE_IDX 2
#define mmDP_AUX4_AUX_DPHY_TX_REF_CONTROL 0x1fc8
#define mmDP_AUX4_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2
#define mmDP_AUX4_AUX_DPHY_TX_CONTROL 0x1fc9
#define mmDP_AUX4_AUX_DPHY_TX_CONTROL_BASE_IDX 2
#define mmDP_AUX4_AUX_DPHY_RX_CONTROL0 0x1fca
#define mmDP_AUX4_AUX_DPHY_RX_CONTROL0_BASE_IDX 2
#define mmDP_AUX4_AUX_DPHY_RX_CONTROL1 0x1fcb
#define mmDP_AUX4_AUX_DPHY_RX_CONTROL1_BASE_IDX 2
#define mmDP_AUX4_AUX_DPHY_TX_STATUS 0x1fcc
#define mmDP_AUX4_AUX_DPHY_TX_STATUS_BASE_IDX 2
#define mmDP_AUX4_AUX_DPHY_RX_STATUS 0x1fcd
#define mmDP_AUX4_AUX_DPHY_RX_STATUS_BASE_IDX 2
#define mmDP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL 0x1fcf
#define mmDP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2
#define mmDP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1fd0
#define mmDP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2
#define mmDP_AUX4_AUX_GTC_SYNC_STATUS 0x1fd1
#define mmDP_AUX4_AUX_GTC_SYNC_STATUS_BASE_IDX 2
// addressBlock: dce_dc_dio_dp_aux5_dispdec
// base address: 0x230
#define mmDP_AUX5_AUX_CONTROL 0x1fdc
#define mmDP_AUX5_AUX_CONTROL_BASE_IDX 2
#define mmDP_AUX5_AUX_SW_CONTROL 0x1fdd
#define mmDP_AUX5_AUX_SW_CONTROL_BASE_IDX 2
#define mmDP_AUX5_AUX_ARB_CONTROL 0x1fde
#define mmDP_AUX5_AUX_ARB_CONTROL_BASE_IDX 2
#define mmDP_AUX5_AUX_INTERRUPT_CONTROL 0x1fdf
#define mmDP_AUX5_AUX_INTERRUPT_CONTROL_BASE_IDX 2
#define mmDP_AUX5_AUX_SW_STATUS 0x1fe0
#define mmDP_AUX5_AUX_SW_STATUS_BASE_IDX 2
#define mmDP_AUX5_AUX_LS_STATUS 0x1fe1
#define mmDP_AUX5_AUX_LS_STATUS_BASE_IDX 2
#define mmDP_AUX5_AUX_SW_DATA 0x1fe2
#define mmDP_AUX5_AUX_SW_DATA_BASE_IDX 2
#define mmDP_AUX5_AUX_LS_DATA 0x1fe3
#define mmDP_AUX5_AUX_LS_DATA_BASE_IDX 2
#define mmDP_AUX5_AUX_DPHY_TX_REF_CONTROL 0x1fe4
#define mmDP_AUX5_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2
#define mmDP_AUX5_AUX_DPHY_TX_CONTROL 0x1fe5
#define mmDP_AUX5_AUX_DPHY_TX_CONTROL_BASE_IDX 2
#define mmDP_AUX5_AUX_DPHY_RX_CONTROL0 0x1fe6
#define mmDP_AUX5_AUX_DPHY_RX_CONTROL0_BASE_IDX 2
#define mmDP_AUX5_AUX_DPHY_RX_CONTROL1 0x1fe7
#define mmDP_AUX5_AUX_DPHY_RX_CONTROL1_BASE_IDX 2
#define mmDP_AUX5_AUX_DPHY_TX_STATUS 0x1fe8
#define mmDP_AUX5_AUX_DPHY_TX_STATUS_BASE_IDX 2
#define mmDP_AUX5_AUX_DPHY_RX_STATUS 0x1fe9
#define mmDP_AUX5_AUX_DPHY_RX_STATUS_BASE_IDX 2
#define mmDP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL 0x1feb
#define mmDP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2
#define mmDP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1fec
#define mmDP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2
#define mmDP_AUX5_AUX_GTC_SYNC_STATUS 0x1fed
#define mmDP_AUX5_AUX_GTC_SYNC_STATUS_BASE_IDX 2
// addressBlock: dce_dc_dio_dp_aux6_dispdec
// base address: 0x2a0
#define mmDP_AUX6_AUX_CONTROL 0x1ff8
#define mmDP_AUX6_AUX_CONTROL_BASE_IDX 2
#define mmDP_AUX6_AUX_SW_CONTROL 0x1ff9
#define mmDP_AUX6_AUX_SW_CONTROL_BASE_IDX 2
#define mmDP_AUX6_AUX_ARB_CONTROL 0x1ffa
#define mmDP_AUX6_AUX_ARB_CONTROL_BASE_IDX 2
#define mmDP_AUX6_AUX_INTERRUPT_CONTROL 0x1ffb
#define mmDP_AUX6_AUX_INTERRUPT_CONTROL_BASE_IDX 2
#define mmDP_AUX6_AUX_SW_STATUS 0x1ffc
#define mmDP_AUX6_AUX_SW_STATUS_BASE_IDX 2
#define mmDP_AUX6_AUX_LS_STATUS 0x1ffd
#define mmDP_AUX6_AUX_LS_STATUS_BASE_IDX 2
#define mmDP_AUX6_AUX_SW_DATA 0x1ffe
#define mmDP_AUX6_AUX_SW_DATA_BASE_IDX 2
#define mmDP_AUX6_AUX_LS_DATA 0x1fff
#define mmDP_AUX6_AUX_LS_DATA_BASE_IDX 2
#define mmDP_AUX6_AUX_DPHY_TX_REF_CONTROL 0x2000
#define mmDP_AUX6_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2
#define mmDP_AUX6_AUX_DPHY_TX_CONTROL 0x2001
#define mmDP_AUX6_AUX_DPHY_TX_CONTROL_BASE_IDX 2
#define mmDP_AUX6_AUX_DPHY_RX_CONTROL0 0x2002
#define mmDP_AUX6_AUX_DPHY_RX_CONTROL0_BASE_IDX 2
#define mmDP_AUX6_AUX_DPHY_RX_CONTROL1 0x2003
#define mmDP_AUX6_AUX_DPHY_RX_CONTROL1_BASE_IDX 2
#define mmDP_AUX6_AUX_DPHY_TX_STATUS 0x2004
#define mmDP_AUX6_AUX_DPHY_TX_STATUS_BASE_IDX 2
#define mmDP_AUX6_AUX_DPHY_RX_STATUS 0x2005
#define mmDP_AUX6_AUX_DPHY_RX_STATUS_BASE_IDX 2
#define mmDP_AUX6_AUX_GTC_SYNC_ERROR_CONTROL 0x2007
#define mmDP_AUX6_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2
#define mmDP_AUX6_AUX_GTC_SYNC_CONTROLLER_STATUS 0x2008
#define mmDP_AUX6_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2
#define mmDP_AUX6_AUX_GTC_SYNC_STATUS 0x2009
#define mmDP_AUX6_AUX_GTC_SYNC_STATUS_BASE_IDX 2
// addressBlock: dce_dc_dio_dig0_dispdec
// base address: 0x0
#define mmDIG0_DIG_FE_CNTL 0x2068
#define mmDIG0_DIG_FE_CNTL_BASE_IDX 2
#define mmDIG0_DIG_OUTPUT_CRC_CNTL 0x2069
#define mmDIG0_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2
#define mmDIG0_DIG_OUTPUT_CRC_RESULT 0x206a
#define mmDIG0_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2
#define mmDIG0_DIG_CLOCK_PATTERN 0x206b
#define mmDIG0_DIG_CLOCK_PATTERN_BASE_IDX 2
#define mmDIG0_DIG_TEST_PATTERN 0x206c
#define mmDIG0_DIG_TEST_PATTERN_BASE_IDX 2
#define mmDIG0_DIG_RANDOM_PATTERN_SEED 0x206d
#define mmDIG0_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2
#define mmDIG0_DIG_FIFO_STATUS 0x206e
#define mmDIG0_DIG_FIFO_STATUS_BASE_IDX 2
#define mmDIG0_HDMI_CONTROL 0x2071
#define mmDIG0_HDMI_CONTROL_BASE_IDX 2
#define mmDIG0_HDMI_STATUS 0x2072
#define mmDIG0_HDMI_STATUS_BASE_IDX 2
#define mmDIG0_HDMI_AUDIO_PACKET_CONTROL 0x2073
#define mmDIG0_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2
#define mmDIG0_HDMI_ACR_PACKET_CONTROL 0x2074
#define mmDIG0_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2
#define mmDIG0_HDMI_VBI_PACKET_CONTROL 0x2075
#define mmDIG0_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2
#define mmDIG0_HDMI_INFOFRAME_CONTROL0 0x2076
#define mmDIG0_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2
#define mmDIG0_HDMI_INFOFRAME_CONTROL1 0x2077
#define mmDIG0_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2
#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL0 0x2078
#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2
#define mmDIG0_AFMT_INTERRUPT_STATUS 0x2079
#define mmDIG0_AFMT_INTERRUPT_STATUS_BASE_IDX 2
#define mmDIG0_HDMI_GC 0x207b
#define mmDIG0_HDMI_GC_BASE_IDX 2
#define mmDIG0_AFMT_AUDIO_PACKET_CONTROL2 0x207c
#define mmDIG0_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2
#define mmDIG0_AFMT_ISRC1_0 0x207d
#define mmDIG0_AFMT_ISRC1_0_BASE_IDX 2
#define mmDIG0_AFMT_ISRC1_1 0x207e
#define mmDIG0_AFMT_ISRC1_1_BASE_IDX 2
#define mmDIG0_AFMT_ISRC1_2 0x207f
#define mmDIG0_AFMT_ISRC1_2_BASE_IDX 2
#define mmDIG0_AFMT_ISRC1_3 0x2080
#define mmDIG0_AFMT_ISRC1_3_BASE_IDX 2
#define mmDIG0_AFMT_ISRC1_4 0x2081
#define mmDIG0_AFMT_ISRC1_4_BASE_IDX 2
#define mmDIG0_AFMT_ISRC2_0 0x2082
#define mmDIG0_AFMT_ISRC2_0_BASE_IDX 2
#define mmDIG0_AFMT_ISRC2_1 0x2083
#define mmDIG0_AFMT_ISRC2_1_BASE_IDX 2
#define mmDIG0_AFMT_ISRC2_2 0x2084
#define mmDIG0_AFMT_ISRC2_2_BASE_IDX 2
#define mmDIG0_AFMT_ISRC2_3 0x2085
#define mmDIG0_AFMT_ISRC2_3_BASE_IDX 2
#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL2 0x2086
#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2
#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL3 0x2087
#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2
#define mmDIG0_HDMI_DB_CONTROL 0x2088
#define mmDIG0_HDMI_DB_CONTROL_BASE_IDX 2
#define mmDIG0_AFMT_MPEG_INFO0 0x208a
#define mmDIG0_AFMT_MPEG_INFO0_BASE_IDX 2
#define mmDIG0_AFMT_MPEG_INFO1 0x208b
#define mmDIG0_AFMT_MPEG_INFO1_BASE_IDX 2
#define mmDIG0_AFMT_GENERIC_HDR 0x208c
#define mmDIG0_AFMT_GENERIC_HDR_BASE_IDX 2
#define mmDIG0_AFMT_GENERIC_0 0x208d
#define mmDIG0_AFMT_GENERIC_0_BASE_IDX 2
#define mmDIG0_AFMT_GENERIC_1 0x208e
#define mmDIG0_AFMT_GENERIC_1_BASE_IDX 2
#define mmDIG0_AFMT_GENERIC_2 0x208f
#define mmDIG0_AFMT_GENERIC_2_BASE_IDX 2
#define mmDIG0_AFMT_GENERIC_3 0x2090
#define mmDIG0_AFMT_GENERIC_3_BASE_IDX 2
#define mmDIG0_AFMT_GENERIC_4 0x2091
#define mmDIG0_AFMT_GENERIC_4_BASE_IDX 2
#define mmDIG0_AFMT_GENERIC_5 0x2092
#define mmDIG0_AFMT_GENERIC_5_BASE_IDX 2
#define mmDIG0_AFMT_GENERIC_6 0x2093
#define mmDIG0_AFMT_GENERIC_6_BASE_IDX 2
#define mmDIG0_AFMT_GENERIC_7 0x2094
#define mmDIG0_AFMT_GENERIC_7_BASE_IDX 2
#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL1 0x2095
#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2
#define mmDIG0_HDMI_ACR_32_0 0x2096
#define mmDIG0_HDMI_ACR_32_0_BASE_IDX 2
#define mmDIG0_HDMI_ACR_32_1 0x2097
#define mmDIG0_HDMI_ACR_32_1_BASE_IDX 2
#define mmDIG0_HDMI_ACR_44_0 0x2098
#define mmDIG0_HDMI_ACR_44_0_BASE_IDX 2
#define mmDIG0_HDMI_ACR_44_1 0x2099
#define mmDIG0_HDMI_ACR_44_1_BASE_IDX 2
#define mmDIG0_HDMI_ACR_48_0 0x209a
#define mmDIG0_HDMI_ACR_48_0_BASE_IDX 2
#define mmDIG0_HDMI_ACR_48_1 0x209b
#define mmDIG0_HDMI_ACR_48_1_BASE_IDX 2
#define mmDIG0_HDMI_ACR_STATUS_0 0x209c
#define mmDIG0_HDMI_ACR_STATUS_0_BASE_IDX 2
#define mmDIG0_HDMI_ACR_STATUS_1 0x209d
#define mmDIG0_HDMI_ACR_STATUS_1_BASE_IDX 2
#define mmDIG0_AFMT_AUDIO_INFO0 0x209e
#define mmDIG0_AFMT_AUDIO_INFO0_BASE_IDX 2
#define mmDIG0_AFMT_AUDIO_INFO1 0x209f
#define mmDIG0_AFMT_AUDIO_INFO1_BASE_IDX 2
#define mmDIG0_AFMT_60958_0 0x20a0
#define mmDIG0_AFMT_60958_0_BASE_IDX 2
#define mmDIG0_AFMT_60958_1 0x20a1
#define mmDIG0_AFMT_60958_1_BASE_IDX 2
#define mmDIG0_AFMT_AUDIO_CRC_CONTROL 0x20a2
#define mmDIG0_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2
#define mmDIG0_AFMT_RAMP_CONTROL0 0x20a3
#define mmDIG0_AFMT_RAMP_CONTROL0_BASE_IDX 2
#define mmDIG0_AFMT_RAMP_CONTROL1 0x20a4
#define mmDIG0_AFMT_RAMP_CONTROL1_BASE_IDX 2
#define mmDIG0_AFMT_RAMP_CONTROL2 0x20a5
#define mmDIG0_AFMT_RAMP_CONTROL2_BASE_IDX 2
#define mmDIG0_AFMT_RAMP_CONTROL3 0x20a6
#define mmDIG0_AFMT_RAMP_CONTROL3_BASE_IDX 2
#define mmDIG0_AFMT_60958_2 0x20a7
#define mmDIG0_AFMT_60958_2_BASE_IDX 2
#define mmDIG0_AFMT_AUDIO_CRC_RESULT 0x20a8
#define mmDIG0_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2
#define mmDIG0_AFMT_STATUS 0x20a9
#define mmDIG0_AFMT_STATUS_BASE_IDX 2
#define mmDIG0_AFMT_AUDIO_PACKET_CONTROL 0x20aa
#define mmDIG0_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2
#define mmDIG0_AFMT_VBI_PACKET_CONTROL 0x20ab
#define mmDIG0_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2
#define mmDIG0_AFMT_INFOFRAME_CONTROL0 0x20ac
#define mmDIG0_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2
#define mmDIG0_AFMT_AUDIO_SRC_CONTROL 0x20ad
#define mmDIG0_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2
#define mmDIG0_DIG_BE_CNTL 0x20af
#define mmDIG0_DIG_BE_CNTL_BASE_IDX 2
#define mmDIG0_DIG_BE_EN_CNTL 0x20b0
#define mmDIG0_DIG_BE_EN_CNTL_BASE_IDX 2
#define mmDIG0_TMDS_CNTL 0x20d3
#define mmDIG0_TMDS_CNTL_BASE_IDX 2
#define mmDIG0_TMDS_CONTROL_CHAR 0x20d4
#define mmDIG0_TMDS_CONTROL_CHAR_BASE_IDX 2
#define mmDIG0_TMDS_CONTROL0_FEEDBACK 0x20d5
#define mmDIG0_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2
#define mmDIG0_TMDS_STEREOSYNC_CTL_SEL 0x20d6
#define mmDIG0_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2
#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_0_1 0x20d7
#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2
#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_2_3 0x20d8
#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2
#define mmDIG0_TMDS_CTL_BITS 0x20da
#define mmDIG0_TMDS_CTL_BITS_BASE_IDX 2
#define mmDIG0_TMDS_DCBALANCER_CONTROL 0x20db
#define mmDIG0_TMDS_DCBALANCER_CONTROL_BASE_IDX 2
#define mmDIG0_TMDS_CTL0_1_GEN_CNTL 0x20dd
#define mmDIG0_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2
#define mmDIG0_TMDS_CTL2_3_GEN_CNTL 0x20de
#define mmDIG0_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2
#define mmDIG0_DIG_VERSION 0x20e0
#define mmDIG0_DIG_VERSION_BASE_IDX 2
#define mmDIG0_DIG_LANE_ENABLE 0x20e1
#define mmDIG0_DIG_LANE_ENABLE_BASE_IDX 2
#define mmDIG0_AFMT_CNTL 0x20e6
#define mmDIG0_AFMT_CNTL_BASE_IDX 2
#define mmDIG0_AFMT_VBI_PACKET_CONTROL1 0x20e7
#define mmDIG0_AFMT_VBI_PACKET_CONTROL1_BASE_IDX 2
// addressBlock: dce_dc_dio_dp0_dispdec
// base address: 0x0
#define mmDP0_DP_LINK_CNTL 0x2108
#define mmDP0_DP_LINK_CNTL_BASE_IDX 2
#define mmDP0_DP_PIXEL_FORMAT 0x2109
#define mmDP0_DP_PIXEL_FORMAT_BASE_IDX 2
#define mmDP0_DP_MSA_COLORIMETRY 0x210a
#define mmDP0_DP_MSA_COLORIMETRY_BASE_IDX 2
#define mmDP0_DP_CONFIG 0x210b
#define mmDP0_DP_CONFIG_BASE_IDX 2
#define mmDP0_DP_VID_STREAM_CNTL 0x210c
#define mmDP0_DP_VID_STREAM_CNTL_BASE_IDX 2
#define mmDP0_DP_STEER_FIFO 0x210d
#define mmDP0_DP_STEER_FIFO_BASE_IDX 2
#define mmDP0_DP_MSA_MISC 0x210e
#define mmDP0_DP_MSA_MISC_BASE_IDX 2
#define mmDP0_DP_VID_TIMING 0x2110
#define mmDP0_DP_VID_TIMING_BASE_IDX 2
#define mmDP0_DP_VID_N 0x2111
#define mmDP0_DP_VID_N_BASE_IDX 2
#define mmDP0_DP_VID_M 0x2112
#define mmDP0_DP_VID_M_BASE_IDX 2
#define mmDP0_DP_LINK_FRAMING_CNTL 0x2113
#define mmDP0_DP_LINK_FRAMING_CNTL_BASE_IDX 2
#define mmDP0_DP_HBR2_EYE_PATTERN 0x2114
#define mmDP0_DP_HBR2_EYE_PATTERN_BASE_IDX 2
#define mmDP0_DP_VID_MSA_VBID 0x2115
#define mmDP0_DP_VID_MSA_VBID_BASE_IDX 2
#define mmDP0_DP_VID_INTERRUPT_CNTL 0x2116
#define mmDP0_DP_VID_INTERRUPT_CNTL_BASE_IDX 2
#define mmDP0_DP_DPHY_CNTL 0x2117
#define mmDP0_DP_DPHY_CNTL_BASE_IDX 2
#define mmDP0_DP_DPHY_TRAINING_PATTERN_SEL 0x2118
#define mmDP0_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2
#define mmDP0_DP_DPHY_SYM0 0x2119
#define mmDP0_DP_DPHY_SYM0_BASE_IDX 2
#define mmDP0_DP_DPHY_SYM1 0x211a
#define mmDP0_DP_DPHY_SYM1_BASE_IDX 2
#define mmDP0_DP_DPHY_SYM2 0x211b
#define mmDP0_DP_DPHY_SYM2_BASE_IDX 2
#define mmDP0_DP_DPHY_8B10B_CNTL 0x211c
#define mmDP0_DP_DPHY_8B10B_CNTL_BASE_IDX 2
#define mmDP0_DP_DPHY_PRBS_CNTL 0x211d
#define mmDP0_DP_DPHY_PRBS_CNTL_BASE_IDX 2
#define mmDP0_DP_DPHY_SCRAM_CNTL 0x211e
#define mmDP0_DP_DPHY_SCRAM_CNTL_BASE_IDX 2
#define mmDP0_DP_DPHY_CRC_EN 0x211f
#define mmDP0_DP_DPHY_CRC_EN_BASE_IDX 2
#define mmDP0_DP_DPHY_CRC_CNTL 0x2120
#define mmDP0_DP_DPHY_CRC_CNTL_BASE_IDX 2
#define mmDP0_DP_DPHY_CRC_RESULT 0x2121
#define mmDP0_DP_DPHY_CRC_RESULT_BASE_IDX 2
#define mmDP0_DP_DPHY_CRC_MST_CNTL 0x2122
#define mmDP0_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2
#define mmDP0_DP_DPHY_CRC_MST_STATUS 0x2123
#define mmDP0_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2
#define mmDP0_DP_DPHY_FAST_TRAINING 0x2124
#define mmDP0_DP_DPHY_FAST_TRAINING_BASE_IDX 2
#define mmDP0_DP_DPHY_FAST_TRAINING_STATUS 0x2125
#define mmDP0_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2
#define mmDP0_DP_SEC_CNTL 0x212b
#define mmDP0_DP_SEC_CNTL_BASE_IDX 2
#define mmDP0_DP_SEC_CNTL1 0x212c
#define mmDP0_DP_SEC_CNTL1_BASE_IDX 2
#define mmDP0_DP_SEC_FRAMING1 0x212d
#define mmDP0_DP_SEC_FRAMING1_BASE_IDX 2
#define mmDP0_DP_SEC_FRAMING2 0x212e
#define mmDP0_DP_SEC_FRAMING2_BASE_IDX 2
#define mmDP0_DP_SEC_FRAMING3 0x212f
#define mmDP0_DP_SEC_FRAMING3_BASE_IDX 2
#define mmDP0_DP_SEC_FRAMING4 0x2130
#define mmDP0_DP_SEC_FRAMING4_BASE_IDX 2
#define mmDP0_DP_SEC_AUD_N 0x2131
#define mmDP0_DP_SEC_AUD_N_BASE_IDX 2
#define mmDP0_DP_SEC_AUD_N_READBACK 0x2132
#define mmDP0_DP_SEC_AUD_N_READBACK_BASE_IDX 2
#define mmDP0_DP_SEC_AUD_M 0x2133
#define mmDP0_DP_SEC_AUD_M_BASE_IDX 2
#define mmDP0_DP_SEC_AUD_M_READBACK 0x2134
#define mmDP0_DP_SEC_AUD_M_READBACK_BASE_IDX 2
#define mmDP0_DP_SEC_TIMESTAMP 0x2135
#define mmDP0_DP_SEC_TIMESTAMP_BASE_IDX 2
#define mmDP0_DP_SEC_PACKET_CNTL 0x2136
#define mmDP0_DP_SEC_PACKET_CNTL_BASE_IDX 2
#define mmDP0_DP_MSE_RATE_CNTL 0x2137
#define mmDP0_DP_MSE_RATE_CNTL_BASE_IDX 2
#define mmDP0_DP_MSE_RATE_UPDATE 0x2139
#define mmDP0_DP_MSE_RATE_UPDATE_BASE_IDX 2
#define mmDP0_DP_MSE_SAT0 0x213a
#define mmDP0_DP_MSE_SAT0_BASE_IDX 2
#define mmDP0_DP_MSE_SAT1 0x213b
#define mmDP0_DP_MSE_SAT1_BASE_IDX 2
#define mmDP0_DP_MSE_SAT2 0x213c
#define mmDP0_DP_MSE_SAT2_BASE_IDX 2
#define mmDP0_DP_MSE_SAT_UPDATE 0x213d
#define mmDP0_DP_MSE_SAT_UPDATE_BASE_IDX 2
#define mmDP0_DP_MSE_LINK_TIMING 0x213e
#define mmDP0_DP_MSE_LINK_TIMING_BASE_IDX 2
#define mmDP0_DP_MSE_MISC_CNTL 0x213f
#define mmDP0_DP_MSE_MISC_CNTL_BASE_IDX 2
#define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL 0x2144
#define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2
#define mmDP0_DP_DPHY_HBR2_PATTERN_CONTROL 0x2145
#define mmDP0_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2
#define mmDP0_DP_MSE_SAT0_STATUS 0x2147
#define mmDP0_DP_MSE_SAT0_STATUS_BASE_IDX 2
#define mmDP0_DP_MSE_SAT1_STATUS 0x2148
#define mmDP0_DP_MSE_SAT1_STATUS_BASE_IDX 2
#define mmDP0_DP_MSE_SAT2_STATUS 0x2149
#define mmDP0_DP_MSE_SAT2_STATUS_BASE_IDX 2
#define mmDP0_DP_MSA_TIMING_PARAM1 0x214c
#define mmDP0_DP_MSA_TIMING_PARAM1_BASE_IDX 2
#define mmDP0_DP_MSA_TIMING_PARAM2 0x214d
#define mmDP0_DP_MSA_TIMING_PARAM2_BASE_IDX 2
#define mmDP0_DP_MSA_TIMING_PARAM3 0x214e
#define mmDP0_DP_MSA_TIMING_PARAM3_BASE_IDX 2
#define mmDP0_DP_MSA_TIMING_PARAM4 0x214f
#define mmDP0_DP_MSA_TIMING_PARAM4_BASE_IDX 2
#define mmDP0_DP_MSO_CNTL 0x2150
#define mmDP0_DP_MSO_CNTL_BASE_IDX 2
#define mmDP0_DP_MSO_CNTL1 0x2151
#define mmDP0_DP_MSO_CNTL1_BASE_IDX 2
#define mmDP0_DP_DSC_CNTL 0x2152
#define mmDP0_DP_DSC_CNTL_BASE_IDX 2
#define mmDP0_DP_SEC_CNTL2 0x2153
#define mmDP0_DP_SEC_CNTL2_BASE_IDX 2
#define mmDP0_DP_SEC_CNTL3 0x2154
#define mmDP0_DP_SEC_CNTL3_BASE_IDX 2
#define mmDP0_DP_SEC_CNTL4 0x2155
#define mmDP0_DP_SEC_CNTL4_BASE_IDX 2
#define mmDP0_DP_SEC_CNTL5 0x2156
#define mmDP0_DP_SEC_CNTL5_BASE_IDX 2
#define mmDP0_DP_SEC_CNTL6 0x2157
#define mmDP0_DP_SEC_CNTL6_BASE_IDX 2
#define mmDP0_DP_SEC_CNTL7 0x2158
#define mmDP0_DP_SEC_CNTL7_BASE_IDX 2
#define mmDP0_DP_DB_CNTL 0x2159
#define mmDP0_DP_DB_CNTL_BASE_IDX 2
#define mmDP0_DP_MSA_VBID_MISC 0x215a
#define mmDP0_DP_MSA_VBID_MISC_BASE_IDX 2
// addressBlock: dce_dc_dio_dig1_dispdec
// base address: 0x400
#define mmDIG1_DIG_FE_CNTL 0x2168
#define mmDIG1_DIG_FE_CNTL_BASE_IDX 2
#define mmDIG1_DIG_OUTPUT_CRC_CNTL 0x2169
#define mmDIG1_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2
#define mmDIG1_DIG_OUTPUT_CRC_RESULT 0x216a
#define mmDIG1_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2
#define mmDIG1_DIG_CLOCK_PATTERN 0x216b
#define mmDIG1_DIG_CLOCK_PATTERN_BASE_IDX 2
#define mmDIG1_DIG_TEST_PATTERN 0x216c
#define mmDIG1_DIG_TEST_PATTERN_BASE_IDX 2
#define mmDIG1_DIG_RANDOM_PATTERN_SEED 0x216d
#define mmDIG1_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2
#define mmDIG1_DIG_FIFO_STATUS 0x216e
#define mmDIG1_DIG_FIFO_STATUS_BASE_IDX 2
#define mmDIG1_HDMI_CONTROL 0x2171
#define mmDIG1_HDMI_CONTROL_BASE_IDX 2
#define mmDIG1_HDMI_STATUS 0x2172
#define mmDIG1_HDMI_STATUS_BASE_IDX 2
#define mmDIG1_HDMI_AUDIO_PACKET_CONTROL 0x2173
#define mmDIG1_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2
#define mmDIG1_HDMI_ACR_PACKET_CONTROL 0x2174
#define mmDIG1_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2
#define mmDIG1_HDMI_VBI_PACKET_CONTROL 0x2175
#define mmDIG1_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2
#define mmDIG1_HDMI_INFOFRAME_CONTROL0 0x2176
#define mmDIG1_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2
#define mmDIG1_HDMI_INFOFRAME_CONTROL1 0x2177
#define mmDIG1_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2
#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL0 0x2178
#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2
#define mmDIG1_AFMT_INTERRUPT_STATUS 0x2179
#define mmDIG1_AFMT_INTERRUPT_STATUS_BASE_IDX 2
#define mmDIG1_HDMI_GC 0x217b
#define mmDIG1_HDMI_GC_BASE_IDX 2
#define mmDIG1_AFMT_AUDIO_PACKET_CONTROL2 0x217c
#define mmDIG1_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2
#define mmDIG1_AFMT_ISRC1_0 0x217d
#define mmDIG1_AFMT_ISRC1_0_BASE_IDX 2
#define mmDIG1_AFMT_ISRC1_1 0x217e
#define mmDIG1_AFMT_ISRC1_1_BASE_IDX 2
#define mmDIG1_AFMT_ISRC1_2 0x217f
#define mmDIG1_AFMT_ISRC1_2_BASE_IDX 2
#define mmDIG1_AFMT_ISRC1_3 0x2180
#define mmDIG1_AFMT_ISRC1_3_BASE_IDX 2
#define mmDIG1_AFMT_ISRC1_4 0x2181
#define mmDIG1_AFMT_ISRC1_4_BASE_IDX 2
#define mmDIG1_AFMT_ISRC2_0 0x2182
#define mmDIG1_AFMT_ISRC2_0_BASE_IDX 2
#define mmDIG1_AFMT_ISRC2_1 0x2183
#define mmDIG1_AFMT_ISRC2_1_BASE_IDX 2
#define mmDIG1_AFMT_ISRC2_2 0x2184
#define mmDIG1_AFMT_ISRC2_2_BASE_IDX 2
#define mmDIG1_AFMT_ISRC2_3 0x2185
#define mmDIG1_AFMT_ISRC2_3_BASE_IDX 2
#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL2 0x2186
#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2
#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL3 0x2187
#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2
#define mmDIG1_HDMI_DB_CONTROL 0x2188
#define mmDIG1_HDMI_DB_CONTROL_BASE_IDX 2
#define mmDIG1_AFMT_MPEG_INFO0 0x218a
#define mmDIG1_AFMT_MPEG_INFO0_BASE_IDX 2
#define mmDIG1_AFMT_MPEG_INFO1 0x218b
#define mmDIG1_AFMT_MPEG_INFO1_BASE_IDX 2
#define mmDIG1_AFMT_GENERIC_HDR 0x218c
#define mmDIG1_AFMT_GENERIC_HDR_BASE_IDX 2
#define mmDIG1_AFMT_GENERIC_0 0x218d
#define mmDIG1_AFMT_GENERIC_0_BASE_IDX 2
#define mmDIG1_AFMT_GENERIC_1 0x218e
#define mmDIG1_AFMT_GENERIC_1_BASE_IDX 2
#define mmDIG1_AFMT_GENERIC_2 0x218f
#define mmDIG1_AFMT_GENERIC_2_BASE_IDX 2
#define mmDIG1_AFMT_GENERIC_3 0x2190
#define mmDIG1_AFMT_GENERIC_3_BASE_IDX 2
#define mmDIG1_AFMT_GENERIC_4 0x2191
#define mmDIG1_AFMT_GENERIC_4_BASE_IDX 2
#define mmDIG1_AFMT_GENERIC_5 0x2192
#define mmDIG1_AFMT_GENERIC_5_BASE_IDX 2
#define mmDIG1_AFMT_GENERIC_6 0x2193
#define mmDIG1_AFMT_GENERIC_6_BASE_IDX 2
#define mmDIG1_AFMT_GENERIC_7 0x2194
#define mmDIG1_AFMT_GENERIC_7_BASE_IDX 2
#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL1 0x2195
#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2
#define mmDIG1_HDMI_ACR_32_0 0x2196
#define mmDIG1_HDMI_ACR_32_0_BASE_IDX 2
#define mmDIG1_HDMI_ACR_32_1 0x2197
#define mmDIG1_HDMI_ACR_32_1_BASE_IDX 2
#define mmDIG1_HDMI_ACR_44_0 0x2198
#define mmDIG1_HDMI_ACR_44_0_BASE_IDX 2
#define mmDIG1_HDMI_ACR_44_1 0x2199
#define mmDIG1_HDMI_ACR_44_1_BASE_IDX 2
#define mmDIG1_HDMI_ACR_48_0 0x219a
#define mmDIG1_HDMI_ACR_48_0_BASE_IDX 2
#define mmDIG1_HDMI_ACR_48_1 0x219b
#define mmDIG1_HDMI_ACR_48_1_BASE_IDX 2
#define mmDIG1_HDMI_ACR_STATUS_0 0x219c
#define mmDIG1_HDMI_ACR_STATUS_0_BASE_IDX 2
#define mmDIG1_HDMI_ACR_STATUS_1 0x219d
#define mmDIG1_HDMI_ACR_STATUS_1_BASE_IDX 2
#define mmDIG1_AFMT_AUDIO_INFO0 0x219e
#define mmDIG1_AFMT_AUDIO_INFO0_BASE_IDX 2
#define mmDIG1_AFMT_AUDIO_INFO1 0x219f
#define mmDIG1_AFMT_AUDIO_INFO1_BASE_IDX 2
#define mmDIG1_AFMT_60958_0 0x21a0
#define mmDIG1_AFMT_60958_0_BASE_IDX 2
#define mmDIG1_AFMT_60958_1 0x21a1
#define mmDIG1_AFMT_60958_1_BASE_IDX 2
#define mmDIG1_AFMT_AUDIO_CRC_CONTROL 0x21a2
#define mmDIG1_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2
#define mmDIG1_AFMT_RAMP_CONTROL0 0x21a3
#define mmDIG1_AFMT_RAMP_CONTROL0_BASE_IDX 2
#define mmDIG1_AFMT_RAMP_CONTROL1 0x21a4
#define mmDIG1_AFMT_RAMP_CONTROL1_BASE_IDX 2
#define mmDIG1_AFMT_RAMP_CONTROL2 0x21a5
#define mmDIG1_AFMT_RAMP_CONTROL2_BASE_IDX 2
#define mmDIG1_AFMT_RAMP_CONTROL3 0x21a6
#define mmDIG1_AFMT_RAMP_CONTROL3_BASE_IDX 2
#define mmDIG1_AFMT_60958_2 0x21a7
#define mmDIG1_AFMT_60958_2_BASE_IDX 2
#define mmDIG1_AFMT_AUDIO_CRC_RESULT 0x21a8
#define mmDIG1_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2
#define mmDIG1_AFMT_STATUS 0x21a9
#define mmDIG1_AFMT_STATUS_BASE_IDX 2
#define mmDIG1_AFMT_AUDIO_PACKET_CONTROL 0x21aa
#define mmDIG1_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2
#define mmDIG1_AFMT_VBI_PACKET_CONTROL 0x21ab
#define mmDIG1_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2
#define mmDIG1_AFMT_INFOFRAME_CONTROL0 0x21ac
#define mmDIG1_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2
#define mmDIG1_AFMT_AUDIO_SRC_CONTROL 0x21ad
#define mmDIG1_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2
#define mmDIG1_DIG_BE_CNTL 0x21af
#define mmDIG1_DIG_BE_CNTL_BASE_IDX 2
#define mmDIG1_DIG_BE_EN_CNTL 0x21b0
#define mmDIG1_DIG_BE_EN_CNTL_BASE_IDX 2
#define mmDIG1_TMDS_CNTL 0x21d3
#define mmDIG1_TMDS_CNTL_BASE_IDX 2
#define mmDIG1_TMDS_CONTROL_CHAR 0x21d4
#define mmDIG1_TMDS_CONTROL_CHAR_BASE_IDX 2
#define mmDIG1_TMDS_CONTROL0_FEEDBACK 0x21d5
#define mmDIG1_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2
#define mmDIG1_TMDS_STEREOSYNC_CTL_SEL 0x21d6
#define mmDIG1_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2
#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_0_1 0x21d7
#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2
#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_2_3 0x21d8
#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2
#define mmDIG1_TMDS_CTL_BITS 0x21da
#define mmDIG1_TMDS_CTL_BITS_BASE_IDX 2
#define mmDIG1_TMDS_DCBALANCER_CONTROL 0x21db
#define mmDIG1_TMDS_DCBALANCER_CONTROL_BASE_IDX 2
#define mmDIG1_TMDS_CTL0_1_GEN_CNTL 0x21dd
#define mmDIG1_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2
#define mmDIG1_TMDS_CTL2_3_GEN_CNTL 0x21de
#define mmDIG1_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2
#define mmDIG1_DIG_VERSION 0x21e0
#define mmDIG1_DIG_VERSION_BASE_IDX 2
#define mmDIG1_DIG_LANE_ENABLE 0x21e1
#define mmDIG1_DIG_LANE_ENABLE_BASE_IDX 2
#define mmDIG1_AFMT_CNTL 0x21e6
#define mmDIG1_AFMT_CNTL_BASE_IDX 2
#define mmDIG1_AFMT_VBI_PACKET_CONTROL1 0x21e7
#define mmDIG1_AFMT_VBI_PACKET_CONTROL1_BASE_IDX 2
// addressBlock: dce_dc_dio_dp1_dispdec
// base address: 0x400
#define mmDP1_DP_LINK_CNTL 0x2208
#define mmDP1_DP_LINK_CNTL_BASE_IDX 2
#define mmDP1_DP_PIXEL_FORMAT 0x2209
#define mmDP1_DP_PIXEL_FORMAT_BASE_IDX 2
#define mmDP1_DP_MSA_COLORIMETRY 0x220a
#define mmDP1_DP_MSA_COLORIMETRY_BASE_IDX 2
#define mmDP1_DP_CONFIG 0x220b
#define mmDP1_DP_CONFIG_BASE_IDX 2
#define mmDP1_DP_VID_STREAM_CNTL 0x220c
#define mmDP1_DP_VID_STREAM_CNTL_BASE_IDX 2
#define mmDP1_DP_STEER_FIFO 0x220d
#define mmDP1_DP_STEER_FIFO_BASE_IDX 2
#define mmDP1_DP_MSA_MISC 0x220e
#define mmDP1_DP_MSA_MISC_BASE_IDX 2
#define mmDP1_DP_VID_TIMING 0x2210
#define mmDP1_DP_VID_TIMING_BASE_IDX 2
#define mmDP1_DP_VID_N 0x2211
#define mmDP1_DP_VID_N_BASE_IDX 2
#define mmDP1_DP_VID_M 0x2212
#define mmDP1_DP_VID_M_BASE_IDX 2
#define mmDP1_DP_LINK_FRAMING_CNTL 0x2213
#define mmDP1_DP_LINK_FRAMING_CNTL_BASE_IDX 2
#define mmDP1_DP_HBR2_EYE_PATTERN 0x2214
#define mmDP1_DP_HBR2_EYE_PATTERN_BASE_IDX 2
#define mmDP1_DP_VID_MSA_VBID 0x2215
#define mmDP1_DP_VID_MSA_VBID_BASE_IDX 2
#define mmDP1_DP_VID_INTERRUPT_CNTL 0x2216
#define mmDP1_DP_VID_INTERRUPT_CNTL_BASE_IDX 2
#define mmDP1_DP_DPHY_CNTL 0x2217
#define mmDP1_DP_DPHY_CNTL_BASE_IDX 2
#define mmDP1_DP_DPHY_TRAINING_PATTERN_SEL 0x2218
#define mmDP1_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2
#define mmDP1_DP_DPHY_SYM0 0x2219
#define mmDP1_DP_DPHY_SYM0_BASE_IDX 2
#define mmDP1_DP_DPHY_SYM1 0x221a
#define mmDP1_DP_DPHY_SYM1_BASE_IDX 2
#define mmDP1_DP_DPHY_SYM2 0x221b
#define mmDP1_DP_DPHY_SYM2_BASE_IDX 2
#define mmDP1_DP_DPHY_8B10B_CNTL 0x221c
#define mmDP1_DP_DPHY_8B10B_CNTL_BASE_IDX 2
#define mmDP1_DP_DPHY_PRBS_CNTL 0x221d
#define mmDP1_DP_DPHY_PRBS_CNTL_BASE_IDX 2
#define mmDP1_DP_DPHY_SCRAM_CNTL 0x221e
#define mmDP1_DP_DPHY_SCRAM_CNTL_BASE_IDX 2
#define mmDP1_DP_DPHY_CRC_EN 0x221f
#define mmDP1_DP_DPHY_CRC_EN_BASE_IDX 2
#define mmDP1_DP_DPHY_CRC_CNTL 0x2220
#define mmDP1_DP_DPHY_CRC_CNTL_BASE_IDX 2
#define mmDP1_DP_DPHY_CRC_RESULT 0x2221
#define mmDP1_DP_DPHY_CRC_RESULT_BASE_IDX 2
#define mmDP1_DP_DPHY_CRC_MST_CNTL 0x2222
#define mmDP1_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2
#define mmDP1_DP_DPHY_CRC_MST_STATUS 0x2223
#define mmDP1_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2
#define mmDP1_DP_DPHY_FAST_TRAINING 0x2224
#define mmDP1_DP_DPHY_FAST_TRAINING_BASE_IDX 2
#define mmDP1_DP_DPHY_FAST_TRAINING_STATUS 0x2225
#define mmDP1_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2
#define mmDP1_DP_SEC_CNTL 0x222b
#define mmDP1_DP_SEC_CNTL_BASE_IDX 2
#define mmDP1_DP_SEC_CNTL1 0x222c
#define mmDP1_DP_SEC_CNTL1_BASE_IDX 2
#define mmDP1_DP_SEC_FRAMING1 0x222d
#define mmDP1_DP_SEC_FRAMING1_BASE_IDX 2
#define mmDP1_DP_SEC_FRAMING2 0x222e
#define mmDP1_DP_SEC_FRAMING2_BASE_IDX 2
#define mmDP1_DP_SEC_FRAMING3 0x222f
#define mmDP1_DP_SEC_FRAMING3_BASE_IDX 2
#define mmDP1_DP_SEC_FRAMING4 0x2230
#define mmDP1_DP_SEC_FRAMING4_BASE_IDX 2
#define mmDP1_DP_SEC_AUD_N 0x2231
#define mmDP1_DP_SEC_AUD_N_BASE_IDX 2
#define mmDP1_DP_SEC_AUD_N_READBACK 0x2232
#define mmDP1_DP_SEC_AUD_N_READBACK_BASE_IDX 2
#define mmDP1_DP_SEC_AUD_M 0x2233
#define mmDP1_DP_SEC_AUD_M_BASE_IDX 2
#define mmDP1_DP_SEC_AUD_M_READBACK 0x2234
#define mmDP1_DP_SEC_AUD_M_READBACK_BASE_IDX 2
#define mmDP1_DP_SEC_TIMESTAMP 0x2235
#define mmDP1_DP_SEC_TIMESTAMP_BASE_IDX 2
#define mmDP1_DP_SEC_PACKET_CNTL 0x2236
#define mmDP1_DP_SEC_PACKET_CNTL_BASE_IDX 2
#define mmDP1_DP_MSE_RATE_CNTL 0x2237
#define mmDP1_DP_MSE_RATE_CNTL_BASE_IDX 2
#define mmDP1_DP_MSE_RATE_UPDATE 0x2239
#define mmDP1_DP_MSE_RATE_UPDATE_BASE_IDX 2
#define mmDP1_DP_MSE_SAT0 0x223a
#define mmDP1_DP_MSE_SAT0_BASE_IDX 2
#define mmDP1_DP_MSE_SAT1 0x223b
#define mmDP1_DP_MSE_SAT1_BASE_IDX 2
#define mmDP1_DP_MSE_SAT2 0x223c
#define mmDP1_DP_MSE_SAT2_BASE_IDX 2
#define mmDP1_DP_MSE_SAT_UPDATE 0x223d
#define mmDP1_DP_MSE_SAT_UPDATE_BASE_IDX 2
#define mmDP1_DP_MSE_LINK_TIMING 0x223e
#define mmDP1_DP_MSE_LINK_TIMING_BASE_IDX 2
#define mmDP1_DP_MSE_MISC_CNTL 0x223f
#define mmDP1_DP_MSE_MISC_CNTL_BASE_IDX 2
#define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL 0x2244
#define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2
#define mmDP1_DP_DPHY_HBR2_PATTERN_CONTROL 0x2245
#define mmDP1_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2
#define mmDP1_DP_MSE_SAT0_STATUS 0x2247
#define mmDP1_DP_MSE_SAT0_STATUS_BASE_IDX 2
#define mmDP1_DP_MSE_SAT1_STATUS 0x2248
#define mmDP1_DP_MSE_SAT1_STATUS_BASE_IDX 2
#define mmDP1_DP_MSE_SAT2_STATUS 0x2249
#define mmDP1_DP_MSE_SAT2_STATUS_BASE_IDX 2
#define mmDP1_DP_MSA_TIMING_PARAM1 0x224c
#define mmDP1_DP_MSA_TIMING_PARAM1_BASE_IDX 2
#define mmDP1_DP_MSA_TIMING_PARAM2 0x224d
#define mmDP1_DP_MSA_TIMING_PARAM2_BASE_IDX 2
#define mmDP1_DP_MSA_TIMING_PARAM3 0x224e
#define mmDP1_DP_MSA_TIMING_PARAM3_BASE_IDX 2
#define mmDP1_DP_MSA_TIMING_PARAM4 0x224f
#define mmDP1_DP_MSA_TIMING_PARAM4_BASE_IDX 2
#define mmDP1_DP_MSO_CNTL 0x2250
#define mmDP1_DP_MSO_CNTL_BASE_IDX 2
#define mmDP1_DP_MSO_CNTL1 0x2251
#define mmDP1_DP_MSO_CNTL1_BASE_IDX 2
#define mmDP1_DP_DSC_CNTL 0x2252
#define mmDP1_DP_DSC_CNTL_BASE_IDX 2
#define mmDP1_DP_SEC_CNTL2 0x2253
#define mmDP1_DP_SEC_CNTL2_BASE_IDX 2
#define mmDP1_DP_SEC_CNTL3 0x2254
#define mmDP1_DP_SEC_CNTL3_BASE_IDX 2
#define mmDP1_DP_SEC_CNTL4 0x2255
#define mmDP1_DP_SEC_CNTL4_BASE_IDX 2
#define mmDP1_DP_SEC_CNTL5 0x2256
#define mmDP1_DP_SEC_CNTL5_BASE_IDX 2
#define mmDP1_DP_SEC_CNTL6 0x2257
#define mmDP1_DP_SEC_CNTL6_BASE_IDX 2
#define mmDP1_DP_SEC_CNTL7 0x2258
#define mmDP1_DP_SEC_CNTL7_BASE_IDX 2
#define mmDP1_DP_DB_CNTL 0x2259
#define mmDP1_DP_DB_CNTL_BASE_IDX 2
#define mmDP1_DP_MSA_VBID_MISC 0x225a
#define mmDP1_DP_MSA_VBID_MISC_BASE_IDX 2
// addressBlock: dce_dc_dio_dig2_dispdec
// base address: 0x800
#define mmDIG2_DIG_FE_CNTL 0x2268
#define mmDIG2_DIG_FE_CNTL_BASE_IDX 2
#define mmDIG2_DIG_OUTPUT_CRC_CNTL 0x2269
#define mmDIG2_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2
#define mmDIG2_DIG_OUTPUT_CRC_RESULT 0x226a
#define mmDIG2_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2
#define mmDIG2_DIG_CLOCK_PATTERN 0x226b
#define mmDIG2_DIG_CLOCK_PATTERN_BASE_IDX 2
#define mmDIG2_DIG_TEST_PATTERN 0x226c
#define mmDIG2_DIG_TEST_PATTERN_BASE_IDX 2
#define mmDIG2_DIG_RANDOM_PATTERN_SEED 0x226d
#define mmDIG2_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2
#define mmDIG2_DIG_FIFO_STATUS 0x226e
#define mmDIG2_DIG_FIFO_STATUS_BASE_IDX 2
#define mmDIG2_HDMI_CONTROL 0x2271
#define mmDIG2_HDMI_CONTROL_BASE_IDX 2
#define mmDIG2_HDMI_STATUS 0x2272
#define mmDIG2_HDMI_STATUS_BASE_IDX 2
#define mmDIG2_HDMI_AUDIO_PACKET_CONTROL 0x2273
#define mmDIG2_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2
#define mmDIG2_HDMI_ACR_PACKET_CONTROL 0x2274
#define mmDIG2_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2
#define mmDIG2_HDMI_VBI_PACKET_CONTROL 0x2275
#define mmDIG2_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2
#define mmDIG2_HDMI_INFOFRAME_CONTROL0 0x2276
#define mmDIG2_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2
#define mmDIG2_HDMI_INFOFRAME_CONTROL1 0x2277
#define mmDIG2_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2
#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL0 0x2278
#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2
#define mmDIG2_AFMT_INTERRUPT_STATUS 0x2279
#define mmDIG2_AFMT_INTERRUPT_STATUS_BASE_IDX 2
#define mmDIG2_HDMI_GC 0x227b
#define mmDIG2_HDMI_GC_BASE_IDX 2
#define mmDIG2_AFMT_AUDIO_PACKET_CONTROL2 0x227c
#define mmDIG2_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2
#define mmDIG2_AFMT_ISRC1_0 0x227d
#define mmDIG2_AFMT_ISRC1_0_BASE_IDX 2
#define mmDIG2_AFMT_ISRC1_1 0x227e
#define mmDIG2_AFMT_ISRC1_1_BASE_IDX 2
#define mmDIG2_AFMT_ISRC1_2 0x227f
#define mmDIG2_AFMT_ISRC1_2_BASE_IDX 2
#define mmDIG2_AFMT_ISRC1_3 0x2280
#define mmDIG2_AFMT_ISRC1_3_BASE_IDX 2
#define mmDIG2_AFMT_ISRC1_4 0x2281
#define mmDIG2_AFMT_ISRC1_4_BASE_IDX 2
#define mmDIG2_AFMT_ISRC2_0 0x2282
#define mmDIG2_AFMT_ISRC2_0_BASE_IDX 2
#define mmDIG2_AFMT_ISRC2_1 0x2283
#define mmDIG2_AFMT_ISRC2_1_BASE_IDX 2
#define mmDIG2_AFMT_ISRC2_2 0x2284
#define mmDIG2_AFMT_ISRC2_2_BASE_IDX 2
#define mmDIG2_AFMT_ISRC2_3 0x2285
#define mmDIG2_AFMT_ISRC2_3_BASE_IDX 2
#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL2 0x2286
#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2
#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL3 0x2287
#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2
#define mmDIG2_HDMI_DB_CONTROL 0x2288
#define mmDIG2_HDMI_DB_CONTROL_BASE_IDX 2
#define mmDIG2_AFMT_MPEG_INFO0 0x228a
#define mmDIG2_AFMT_MPEG_INFO0_BASE_IDX 2
#define mmDIG2_AFMT_MPEG_INFO1 0x228b
#define mmDIG2_AFMT_MPEG_INFO1_BASE_IDX 2
#define mmDIG2_AFMT_GENERIC_HDR 0x228c
#define mmDIG2_AFMT_GENERIC_HDR_BASE_IDX 2
#define mmDIG2_AFMT_GENERIC_0 0x228d
#define mmDIG2_AFMT_GENERIC_0_BASE_IDX 2
#define mmDIG2_AFMT_GENERIC_1 0x228e
#define mmDIG2_AFMT_GENERIC_1_BASE_IDX 2
#define mmDIG2_AFMT_GENERIC_2 0x228f
#define mmDIG2_AFMT_GENERIC_2_BASE_IDX 2
#define mmDIG2_AFMT_GENERIC_3 0x2290
#define mmDIG2_AFMT_GENERIC_3_BASE_IDX 2
#define mmDIG2_AFMT_GENERIC_4 0x2291
#define mmDIG2_AFMT_GENERIC_4_BASE_IDX 2
#define mmDIG2_AFMT_GENERIC_5 0x2292
#define mmDIG2_AFMT_GENERIC_5_BASE_IDX 2
#define mmDIG2_AFMT_GENERIC_6 0x2293
#define mmDIG2_AFMT_GENERIC_6_BASE_IDX 2
#define mmDIG2_AFMT_GENERIC_7 0x2294
#define mmDIG2_AFMT_GENERIC_7_BASE_IDX 2
#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL1 0x2295
#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2
#define mmDIG2_HDMI_ACR_32_0 0x2296
#define mmDIG2_HDMI_ACR_32_0_BASE_IDX 2
#define mmDIG2_HDMI_ACR_32_1 0x2297
#define mmDIG2_HDMI_ACR_32_1_BASE_IDX 2
#define mmDIG2_HDMI_ACR_44_0 0x2298
#define mmDIG2_HDMI_ACR_44_0_BASE_IDX 2
#define mmDIG2_HDMI_ACR_44_1 0x2299
#define mmDIG2_HDMI_ACR_44_1_BASE_IDX 2
#define mmDIG2_HDMI_ACR_48_0 0x229a
#define mmDIG2_HDMI_ACR_48_0_BASE_IDX 2
#define mmDIG2_HDMI_ACR_48_1 0x229b
#define mmDIG2_HDMI_ACR_48_1_BASE_IDX 2
#define mmDIG2_HDMI_ACR_STATUS_0 0x229c
#define mmDIG2_HDMI_ACR_STATUS_0_BASE_IDX 2
#define mmDIG2_HDMI_ACR_STATUS_1 0x229d
#define mmDIG2_HDMI_ACR_STATUS_1_BASE_IDX 2
#define mmDIG2_AFMT_AUDIO_INFO0 0x229e
#define mmDIG2_AFMT_AUDIO_INFO0_BASE_IDX 2
#define mmDIG2_AFMT_AUDIO_INFO1 0x229f
#define mmDIG2_AFMT_AUDIO_INFO1_BASE_IDX 2
#define mmDIG2_AFMT_60958_0 0x22a0
#define mmDIG2_AFMT_60958_0_BASE_IDX 2
#define mmDIG2_AFMT_60958_1 0x22a1
#define mmDIG2_AFMT_60958_1_BASE_IDX 2
#define mmDIG2_AFMT_AUDIO_CRC_CONTROL 0x22a2
#define mmDIG2_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2
#define mmDIG2_AFMT_RAMP_CONTROL0 0x22a3
#define mmDIG2_AFMT_RAMP_CONTROL0_BASE_IDX 2
#define mmDIG2_AFMT_RAMP_CONTROL1 0x22a4
#define mmDIG2_AFMT_RAMP_CONTROL1_BASE_IDX 2
#define mmDIG2_AFMT_RAMP_CONTROL2 0x22a5
#define mmDIG2_AFMT_RAMP_CONTROL2_BASE_IDX 2
#define mmDIG2_AFMT_RAMP_CONTROL3 0x22a6
#define mmDIG2_AFMT_RAMP_CONTROL3_BASE_IDX 2
#define mmDIG2_AFMT_60958_2 0x22a7
#define mmDIG2_AFMT_60958_2_BASE_IDX 2
#define mmDIG2_AFMT_AUDIO_CRC_RESULT 0x22a8
#define mmDIG2_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2
#define mmDIG2_AFMT_STATUS 0x22a9
#define mmDIG2_AFMT_STATUS_BASE_IDX 2
#define mmDIG2_AFMT_AUDIO_PACKET_CONTROL 0x22aa
#define mmDIG2_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2
#define mmDIG2_AFMT_VBI_PACKET_CONTROL 0x22ab
#define mmDIG2_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2
#define mmDIG2_AFMT_INFOFRAME_CONTROL0 0x22ac
#define mmDIG2_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2
#define mmDIG2_AFMT_AUDIO_SRC_CONTROL 0x22ad
#define mmDIG2_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2
#define mmDIG2_DIG_BE_CNTL 0x22af
#define mmDIG2_DIG_BE_CNTL_BASE_IDX 2
#define mmDIG2_DIG_BE_EN_CNTL 0x22b0
#define mmDIG2_DIG_BE_EN_CNTL_BASE_IDX 2
#define mmDIG2_TMDS_CNTL 0x22d3
#define mmDIG2_TMDS_CNTL_BASE_IDX 2
#define mmDIG2_TMDS_CONTROL_CHAR 0x22d4
#define mmDIG2_TMDS_CONTROL_CHAR_BASE_IDX 2
#define mmDIG2_TMDS_CONTROL0_FEEDBACK 0x22d5
#define mmDIG2_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2
#define mmDIG2_TMDS_STEREOSYNC_CTL_SEL 0x22d6
#define mmDIG2_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2
#define mmDIG2_TMDS_SYNC_CHAR_PATTERN_0_1 0x22d7
#define mmDIG2_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2
#define mmDIG2_TMDS_SYNC_CHAR_PATTERN_2_3 0x22d8
#define mmDIG2_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2
#define mmDIG2_TMDS_CTL_BITS 0x22da
#define mmDIG2_TMDS_CTL_BITS_BASE_IDX 2
#define mmDIG2_TMDS_DCBALANCER_CONTROL 0x22db
#define mmDIG2_TMDS_DCBALANCER_CONTROL_BASE_IDX 2
#define mmDIG2_TMDS_CTL0_1_GEN_CNTL 0x22dd
#define mmDIG2_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2
#define mmDIG2_TMDS_CTL2_3_GEN_CNTL 0x22de
#define mmDIG2_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2
#define mmDIG2_DIG_VERSION 0x22e0
#define mmDIG2_DIG_VERSION_BASE_IDX 2
#define mmDIG2_DIG_LANE_ENABLE 0x22e1
#define mmDIG2_DIG_LANE_ENABLE_BASE_IDX 2
#define mmDIG2_AFMT_CNTL 0x22e6
#define mmDIG2_AFMT_CNTL_BASE_IDX 2
#define mmDIG2_AFMT_VBI_PACKET_CONTROL1 0x22e7
#define mmDIG2_AFMT_VBI_PACKET_CONTROL1_BASE_IDX 2
// addressBlock: dce_dc_dio_dp2_dispdec
// base address: 0x800
#define mmDP2_DP_LINK_CNTL 0x2308
#define mmDP2_DP_LINK_CNTL_BASE_IDX 2
#define mmDP2_DP_PIXEL_FORMAT 0x2309
#define mmDP2_DP_PIXEL_FORMAT_BASE_IDX 2
#define mmDP2_DP_MSA_COLORIMETRY 0x230a
#define mmDP2_DP_MSA_COLORIMETRY_BASE_IDX 2
#define mmDP2_DP_CONFIG 0x230b
#define mmDP2_DP_CONFIG_BASE_IDX 2
#define mmDP2_DP_VID_STREAM_CNTL 0x230c
#define mmDP2_DP_VID_STREAM_CNTL_BASE_IDX 2
#define mmDP2_DP_STEER_FIFO 0x230d
#define mmDP2_DP_STEER_FIFO_BASE_IDX 2
#define mmDP2_DP_MSA_MISC 0x230e
#define mmDP2_DP_MSA_MISC_BASE_IDX 2
#define mmDP2_DP_VID_TIMING 0x2310
#define mmDP2_DP_VID_TIMING_BASE_IDX 2
#define mmDP2_DP_VID_N 0x2311
#define mmDP2_DP_VID_N_BASE_IDX 2
#define mmDP2_DP_VID_M 0x2312
#define mmDP2_DP_VID_M_BASE_IDX 2
#define mmDP2_DP_LINK_FRAMING_CNTL 0x2313
#define mmDP2_DP_LINK_FRAMING_CNTL_BASE_IDX 2
#define mmDP2_DP_HBR2_EYE_PATTERN 0x2314
#define mmDP2_DP_HBR2_EYE_PATTERN_BASE_IDX 2
#define mmDP2_DP_VID_MSA_VBID 0x2315
#define mmDP2_DP_VID_MSA_VBID_BASE_IDX 2
#define mmDP2_DP_VID_INTERRUPT_CNTL 0x2316
#define mmDP2_DP_VID_INTERRUPT_CNTL_BASE_IDX 2
#define mmDP2_DP_DPHY_CNTL 0x2317
#define mmDP2_DP_DPHY_CNTL_BASE_IDX 2
#define mmDP2_DP_DPHY_TRAINING_PATTERN_SEL 0x2318
#define mmDP2_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2
#define mmDP2_DP_DPHY_SYM0 0x2319
#define mmDP2_DP_DPHY_SYM0_BASE_IDX 2
#define mmDP2_DP_DPHY_SYM1 0x231a
#define mmDP2_DP_DPHY_SYM1_BASE_IDX 2
#define mmDP2_DP_DPHY_SYM2 0x231b
#define mmDP2_DP_DPHY_SYM2_BASE_IDX 2
#define mmDP2_DP_DPHY_8B10B_CNTL 0x231c
#define mmDP2_DP_DPHY_8B10B_CNTL_BASE_IDX 2
#define mmDP2_DP_DPHY_PRBS_CNTL 0x231d
#define mmDP2_DP_DPHY_PRBS_CNTL_BASE_IDX 2
#define mmDP2_DP_DPHY_SCRAM_CNTL 0x231e
#define mmDP2_DP_DPHY_SCRAM_CNTL_BASE_IDX 2
#define mmDP2_DP_DPHY_CRC_EN 0x231f
#define mmDP2_DP_DPHY_CRC_EN_BASE_IDX 2
#define mmDP2_DP_DPHY_CRC_CNTL 0x2320
#define mmDP2_DP_DPHY_CRC_CNTL_BASE_IDX 2
#define mmDP2_DP_DPHY_CRC_RESULT 0x2321
#define mmDP2_DP_DPHY_CRC_RESULT_BASE_IDX 2
#define mmDP2_DP_DPHY_CRC_MST_CNTL 0x2322
#define mmDP2_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2
#define mmDP2_DP_DPHY_CRC_MST_STATUS 0x2323
#define mmDP2_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2
#define mmDP2_DP_DPHY_FAST_TRAINING 0x2324
#define mmDP2_DP_DPHY_FAST_TRAINING_BASE_IDX 2
#define mmDP2_DP_DPHY_FAST_TRAINING_STATUS 0x2325
#define mmDP2_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2
#define mmDP2_DP_SEC_CNTL 0x232b
#define mmDP2_DP_SEC_CNTL_BASE_IDX 2
#define mmDP2_DP_SEC_CNTL1 0x232c
#define mmDP2_DP_SEC_CNTL1_BASE_IDX 2
#define mmDP2_DP_SEC_FRAMING1 0x232d
#define mmDP2_DP_SEC_FRAMING1_BASE_IDX 2
#define mmDP2_DP_SEC_FRAMING2 0x232e
#define mmDP2_DP_SEC_FRAMING2_BASE_IDX 2
#define mmDP2_DP_SEC_FRAMING3 0x232f
#define mmDP2_DP_SEC_FRAMING3_BASE_IDX 2
#define mmDP2_DP_SEC_FRAMING4 0x2330
#define mmDP2_DP_SEC_FRAMING4_BASE_IDX 2
#define mmDP2_DP_SEC_AUD_N 0x2331
#define mmDP2_DP_SEC_AUD_N_BASE_IDX 2
#define mmDP2_DP_SEC_AUD_N_READBACK 0x2332
#define mmDP2_DP_SEC_AUD_N_READBACK_BASE_IDX 2
#define mmDP2_DP_SEC_AUD_M 0x2333
#define mmDP2_DP_SEC_AUD_M_BASE_IDX 2
#define mmDP2_DP_SEC_AUD_M_READBACK 0x2334
#define mmDP2_DP_SEC_AUD_M_READBACK_BASE_IDX 2
#define mmDP2_DP_SEC_TIMESTAMP 0x2335
#define mmDP2_DP_SEC_TIMESTAMP_BASE_IDX 2
#define mmDP2_DP_SEC_PACKET_CNTL 0x2336
#define mmDP2_DP_SEC_PACKET_CNTL_BASE_IDX 2
#define mmDP2_DP_MSE_RATE_CNTL 0x2337
#define mmDP2_DP_MSE_RATE_CNTL_BASE_IDX 2
#define mmDP2_DP_MSE_RATE_UPDATE 0x2339
#define mmDP2_DP_MSE_RATE_UPDATE_BASE_IDX 2
#define mmDP2_DP_MSE_SAT0 0x233a
#define mmDP2_DP_MSE_SAT0_BASE_IDX 2
#define mmDP2_DP_MSE_SAT1 0x233b
#define mmDP2_DP_MSE_SAT1_BASE_IDX 2
#define mmDP2_DP_MSE_SAT2 0x233c
#define mmDP2_DP_MSE_SAT2_BASE_IDX 2
#define mmDP2_DP_MSE_SAT_UPDATE 0x233d
#define mmDP2_DP_MSE_SAT_UPDATE_BASE_IDX 2
#define mmDP2_DP_MSE_LINK_TIMING 0x233e
#define mmDP2_DP_MSE_LINK_TIMING_BASE_IDX 2
#define mmDP2_DP_MSE_MISC_CNTL 0x233f
#define mmDP2_DP_MSE_MISC_CNTL_BASE_IDX 2
#define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL 0x2344
#define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2
#define mmDP2_DP_DPHY_HBR2_PATTERN_CONTROL 0x2345
#define mmDP2_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2
#define mmDP2_DP_MSE_SAT0_STATUS 0x2347
#define mmDP2_DP_MSE_SAT0_STATUS_BASE_IDX 2
#define mmDP2_DP_MSE_SAT1_STATUS 0x2348
#define mmDP2_DP_MSE_SAT1_STATUS_BASE_IDX 2
#define mmDP2_DP_MSE_SAT2_STATUS 0x2349
#define mmDP2_DP_MSE_SAT2_STATUS_BASE_IDX 2
#define mmDP2_DP_MSA_TIMING_PARAM1 0x234c
#define mmDP2_DP_MSA_TIMING_PARAM1_BASE_IDX 2
#define mmDP2_DP_MSA_TIMING_PARAM2 0x234d
#define mmDP2_DP_MSA_TIMING_PARAM2_BASE_IDX 2
#define mmDP2_DP_MSA_TIMING_PARAM3 0x234e
#define mmDP2_DP_MSA_TIMING_PARAM3_BASE_IDX 2
#define mmDP2_DP_MSA_TIMING_PARAM4 0x234f
#define mmDP2_DP_MSA_TIMING_PARAM4_BASE_IDX 2
#define mmDP2_DP_MSO_CNTL 0x2350
#define mmDP2_DP_MSO_CNTL_BASE_IDX 2
#define mmDP2_DP_MSO_CNTL1 0x2351
#define mmDP2_DP_MSO_CNTL1_BASE_IDX 2
#define mmDP2_DP_DSC_CNTL 0x2352
#define mmDP2_DP_DSC_CNTL_BASE_IDX 2
#define mmDP2_DP_SEC_CNTL2 0x2353
#define mmDP2_DP_SEC_CNTL2_BASE_IDX 2
#define mmDP2_DP_SEC_CNTL3 0x2354
#define mmDP2_DP_SEC_CNTL3_BASE_IDX 2
#define mmDP2_DP_SEC_CNTL4 0x2355
#define mmDP2_DP_SEC_CNTL4_BASE_IDX 2
#define mmDP2_DP_SEC_CNTL5 0x2356
#define mmDP2_DP_SEC_CNTL5_BASE_IDX 2
#define mmDP2_DP_SEC_CNTL6 0x2357
#define mmDP2_DP_SEC_CNTL6_BASE_IDX 2
#define mmDP2_DP_SEC_CNTL7 0x2358
#define mmDP2_DP_SEC_CNTL7_BASE_IDX 2
#define mmDP2_DP_DB_CNTL 0x2359
#define mmDP2_DP_DB_CNTL_BASE_IDX 2
#define mmDP2_DP_MSA_VBID_MISC 0x235a
#define mmDP2_DP_MSA_VBID_MISC_BASE_IDX 2
// addressBlock: dce_dc_dio_dig3_dispdec
// base address: 0xc00
#define mmDIG3_DIG_FE_CNTL 0x2368
#define mmDIG3_DIG_FE_CNTL_BASE_IDX 2
#define mmDIG3_DIG_OUTPUT_CRC_CNTL 0x2369
#define mmDIG3_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2
#define mmDIG3_DIG_OUTPUT_CRC_RESULT 0x236a
#define mmDIG3_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2
#define mmDIG3_DIG_CLOCK_PATTERN 0x236b
#define mmDIG3_DIG_CLOCK_PATTERN_BASE_IDX 2
#define mmDIG3_DIG_TEST_PATTERN 0x236c
#define mmDIG3_DIG_TEST_PATTERN_BASE_IDX 2
#define mmDIG3_DIG_RANDOM_PATTERN_SEED 0x236d
#define mmDIG3_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2
#define mmDIG3_DIG_FIFO_STATUS 0x236e
#define mmDIG3_DIG_FIFO_STATUS_BASE_IDX 2
#define mmDIG3_HDMI_CONTROL 0x2371
#define mmDIG3_HDMI_CONTROL_BASE_IDX 2
#define mmDIG3_HDMI_STATUS 0x2372
#define mmDIG3_HDMI_STATUS_BASE_IDX 2
#define mmDIG3_HDMI_AUDIO_PACKET_CONTROL 0x2373
#define mmDIG3_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2
#define mmDIG3_HDMI_ACR_PACKET_CONTROL 0x2374
#define mmDIG3_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2
#define mmDIG3_HDMI_VBI_PACKET_CONTROL 0x2375
#define mmDIG3_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2
#define mmDIG3_HDMI_INFOFRAME_CONTROL0 0x2376
#define mmDIG3_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2
#define mmDIG3_HDMI_INFOFRAME_CONTROL1 0x2377
#define mmDIG3_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2
#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL0 0x2378
#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2
#define mmDIG3_AFMT_INTERRUPT_STATUS 0x2379
#define mmDIG3_AFMT_INTERRUPT_STATUS_BASE_IDX 2
#define mmDIG3_HDMI_GC 0x237b
#define mmDIG3_HDMI_GC_BASE_IDX 2
#define mmDIG3_AFMT_AUDIO_PACKET_CONTROL2 0x237c
#define mmDIG3_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2
#define mmDIG3_AFMT_ISRC1_0 0x237d
#define mmDIG3_AFMT_ISRC1_0_BASE_IDX 2
#define mmDIG3_AFMT_ISRC1_1 0x237e
#define mmDIG3_AFMT_ISRC1_1_BASE_IDX 2
#define mmDIG3_AFMT_ISRC1_2 0x237f
#define mmDIG3_AFMT_ISRC1_2_BASE_IDX 2
#define mmDIG3_AFMT_ISRC1_3 0x2380
#define mmDIG3_AFMT_ISRC1_3_BASE_IDX 2
#define mmDIG3_AFMT_ISRC1_4 0x2381
#define mmDIG3_AFMT_ISRC1_4_BASE_IDX 2
#define mmDIG3_AFMT_ISRC2_0 0x2382
#define mmDIG3_AFMT_ISRC2_0_BASE_IDX 2
#define mmDIG3_AFMT_ISRC2_1 0x2383
#define mmDIG3_AFMT_ISRC2_1_BASE_IDX 2
#define mmDIG3_AFMT_ISRC2_2 0x2384
#define mmDIG3_AFMT_ISRC2_2_BASE_IDX 2
#define mmDIG3_AFMT_ISRC2_3 0x2385
#define mmDIG3_AFMT_ISRC2_3_BASE_IDX 2
#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL2 0x2386
#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2
#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL3 0x2387
#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2
#define mmDIG3_HDMI_DB_CONTROL 0x2388
#define mmDIG3_HDMI_DB_CONTROL_BASE_IDX 2
#define mmDIG3_AFMT_MPEG_INFO0 0x238a
#define mmDIG3_AFMT_MPEG_INFO0_BASE_IDX 2
#define mmDIG3_AFMT_MPEG_INFO1 0x238b
#define mmDIG3_AFMT_MPEG_INFO1_BASE_IDX 2
#define mmDIG3_AFMT_GENERIC_HDR 0x238c
#define mmDIG3_AFMT_GENERIC_HDR_BASE_IDX 2
#define mmDIG3_AFMT_GENERIC_0 0x238d
#define mmDIG3_AFMT_GENERIC_0_BASE_IDX 2
#define mmDIG3_AFMT_GENERIC_1 0x238e
#define mmDIG3_AFMT_GENERIC_1_BASE_IDX 2
#define mmDIG3_AFMT_GENERIC_2 0x238f
#define mmDIG3_AFMT_GENERIC_2_BASE_IDX 2
#define mmDIG3_AFMT_GENERIC_3 0x2390
#define mmDIG3_AFMT_GENERIC_3_BASE_IDX 2
#define mmDIG3_AFMT_GENERIC_4 0x2391
#define mmDIG3_AFMT_GENERIC_4_BASE_IDX 2
#define mmDIG3_AFMT_GENERIC_5 0x2392
#define mmDIG3_AFMT_GENERIC_5_BASE_IDX 2
#define mmDIG3_AFMT_GENERIC_6 0x2393
#define mmDIG3_AFMT_GENERIC_6_BASE_IDX 2
#define mmDIG3_AFMT_GENERIC_7 0x2394
#define mmDIG3_AFMT_GENERIC_7_BASE_IDX 2
#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL1 0x2395
#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2
#define mmDIG3_HDMI_ACR_32_0 0x2396
#define mmDIG3_HDMI_ACR_32_0_BASE_IDX 2
#define mmDIG3_HDMI_ACR_32_1 0x2397
#define mmDIG3_HDMI_ACR_32_1_BASE_IDX 2
#define mmDIG3_HDMI_ACR_44_0 0x2398
#define mmDIG3_HDMI_ACR_44_0_BASE_IDX 2
#define mmDIG3_HDMI_ACR_44_1 0x2399
#define mmDIG3_HDMI_ACR_44_1_BASE_IDX 2
#define mmDIG3_HDMI_ACR_48_0 0x239a
#define mmDIG3_HDMI_ACR_48_0_BASE_IDX 2
#define mmDIG3_HDMI_ACR_48_1 0x239b
#define mmDIG3_HDMI_ACR_48_1_BASE_IDX 2
#define mmDIG3_HDMI_ACR_STATUS_0 0x239c
#define mmDIG3_HDMI_ACR_STATUS_0_BASE_IDX 2
#define mmDIG3_HDMI_ACR_STATUS_1 0x239d
#define mmDIG3_HDMI_ACR_STATUS_1_BASE_IDX 2
#define mmDIG3_AFMT_AUDIO_INFO0 0x239e
#define mmDIG3_AFMT_AUDIO_INFO0_BASE_IDX 2
#define mmDIG3_AFMT_AUDIO_INFO1 0x239f
#define mmDIG3_AFMT_AUDIO_INFO1_BASE_IDX 2
#define mmDIG3_AFMT_60958_0 0x23a0
#define mmDIG3_AFMT_60958_0_BASE_IDX 2
#define mmDIG3_AFMT_60958_1 0x23a1
#define mmDIG3_AFMT_60958_1_BASE_IDX 2
#define mmDIG3_AFMT_AUDIO_CRC_CONTROL 0x23a2
#define mmDIG3_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2
#define mmDIG3_AFMT_RAMP_CONTROL0 0x23a3
#define mmDIG3_AFMT_RAMP_CONTROL0_BASE_IDX 2
#define mmDIG3_AFMT_RAMP_CONTROL1 0x23a4
#define mmDIG3_AFMT_RAMP_CONTROL1_BASE_IDX 2
#define mmDIG3_AFMT_RAMP_CONTROL2 0x23a5
#define mmDIG3_AFMT_RAMP_CONTROL2_BASE_IDX 2
#define mmDIG3_AFMT_RAMP_CONTROL3 0x23a6
#define mmDIG3_AFMT_RAMP_CONTROL3_BASE_IDX 2
#define mmDIG3_AFMT_60958_2 0x23a7
#define mmDIG3_AFMT_60958_2_BASE_IDX 2
#define mmDIG3_AFMT_AUDIO_CRC_RESULT 0x23a8
#define mmDIG3_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2
#define mmDIG3_AFMT_STATUS 0x23a9
#define mmDIG3_AFMT_STATUS_BASE_IDX 2
#define mmDIG3_AFMT_AUDIO_PACKET_CONTROL 0x23aa
#define mmDIG3_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2
#define mmDIG3_AFMT_VBI_PACKET_CONTROL 0x23ab
#define mmDIG3_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2
#define mmDIG3_AFMT_INFOFRAME_CONTROL0 0x23ac
#define mmDIG3_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2
#define mmDIG3_AFMT_AUDIO_SRC_CONTROL 0x23ad
#define mmDIG3_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2
#define mmDIG3_DIG_BE_CNTL 0x23af
#define mmDIG3_DIG_BE_CNTL_BASE_IDX 2
#define mmDIG3_DIG_BE_EN_CNTL 0x23b0
#define mmDIG3_DIG_BE_EN_CNTL_BASE_IDX 2
#define mmDIG3_TMDS_CNTL 0x23d3
#define mmDIG3_TMDS_CNTL_BASE_IDX 2
#define mmDIG3_TMDS_CONTROL_CHAR 0x23d4
#define mmDIG3_TMDS_CONTROL_CHAR_BASE_IDX 2
#define mmDIG3_TMDS_CONTROL0_FEEDBACK 0x23d5
#define mmDIG3_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2
#define mmDIG3_TMDS_STEREOSYNC_CTL_SEL 0x23d6
#define mmDIG3_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2
#define mmDIG3_TMDS_SYNC_CHAR_PATTERN_0_1 0x23d7
#define mmDIG3_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2
#define mmDIG3_TMDS_SYNC_CHAR_PATTERN_2_3 0x23d8
#define mmDIG3_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2
#define mmDIG3_TMDS_CTL_BITS 0x23da
#define mmDIG3_TMDS_CTL_BITS_BASE_IDX 2
#define mmDIG3_TMDS_DCBALANCER_CONTROL 0x23db
#define mmDIG3_TMDS_DCBALANCER_CONTROL_BASE_IDX 2
#define mmDIG3_TMDS_CTL0_1_GEN_CNTL 0x23dd
#define mmDIG3_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2
#define mmDIG3_TMDS_CTL2_3_GEN_CNTL 0x23de
#define mmDIG3_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2
#define mmDIG3_DIG_VERSION 0x23e0
#define mmDIG3_DIG_VERSION_BASE_IDX 2
#define mmDIG3_DIG_LANE_ENABLE 0x23e1
#define mmDIG3_DIG_LANE_ENABLE_BASE_IDX 2
#define mmDIG3_AFMT_CNTL 0x23e6
#define mmDIG3_AFMT_CNTL_BASE_IDX 2
#define mmDIG3_AFMT_VBI_PACKET_CONTROL1 0x23e7
#define mmDIG3_AFMT_VBI_PACKET_CONTROL1_BASE_IDX 2
// addressBlock: dce_dc_dio_dp3_dispdec
// base address: 0xc00
#define mmDP3_DP_LINK_CNTL 0x2408
#define mmDP3_DP_LINK_CNTL_BASE_IDX 2
#define mmDP3_DP_PIXEL_FORMAT 0x2409
#define mmDP3_DP_PIXEL_FORMAT_BASE_IDX 2
#define mmDP3_DP_MSA_COLORIMETRY 0x240a
#define mmDP3_DP_MSA_COLORIMETRY_BASE_IDX 2
#define mmDP3_DP_CONFIG 0x240b
#define mmDP3_DP_CONFIG_BASE_IDX 2
#define mmDP3_DP_VID_STREAM_CNTL 0x240c
#define mmDP3_DP_VID_STREAM_CNTL_BASE_IDX 2
#define mmDP3_DP_STEER_FIFO 0x240d
#define mmDP3_DP_STEER_FIFO_BASE_IDX 2
#define mmDP3_DP_MSA_MISC 0x240e
#define mmDP3_DP_MSA_MISC_BASE_IDX 2
#define mmDP3_DP_VID_TIMING 0x2410
#define mmDP3_DP_VID_TIMING_BASE_IDX 2
#define mmDP3_DP_VID_N 0x2411
#define mmDP3_DP_VID_N_BASE_IDX 2
#define mmDP3_DP_VID_M 0x2412
#define mmDP3_DP_VID_M_BASE_IDX 2
#define mmDP3_DP_LINK_FRAMING_CNTL 0x2413
#define mmDP3_DP_LINK_FRAMING_CNTL_BASE_IDX 2
#define mmDP3_DP_HBR2_EYE_PATTERN 0x2414
#define mmDP3_DP_HBR2_EYE_PATTERN_BASE_IDX 2
#define mmDP3_DP_VID_MSA_VBID 0x2415
#define mmDP3_DP_VID_MSA_VBID_BASE_IDX 2
#define mmDP3_DP_VID_INTERRUPT_CNTL 0x2416
#define mmDP3_DP_VID_INTERRUPT_CNTL_BASE_IDX 2
#define mmDP3_DP_DPHY_CNTL 0x2417
#define mmDP3_DP_DPHY_CNTL_BASE_IDX 2
#define mmDP3_DP_DPHY_TRAINING_PATTERN_SEL 0x2418
#define mmDP3_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2
#define mmDP3_DP_DPHY_SYM0 0x2419
#define mmDP3_DP_DPHY_SYM0_BASE_IDX 2
#define mmDP3_DP_DPHY_SYM1 0x241a
#define mmDP3_DP_DPHY_SYM1_BASE_IDX 2
#define mmDP3_DP_DPHY_SYM2 0x241b
#define mmDP3_DP_DPHY_SYM2_BASE_IDX 2
#define mmDP3_DP_DPHY_8B10B_CNTL 0x241c
#define mmDP3_DP_DPHY_8B10B_CNTL_BASE_IDX 2
#define mmDP3_DP_DPHY_PRBS_CNTL 0x241d
#define mmDP3_DP_DPHY_PRBS_CNTL_BASE_IDX 2
#define mmDP3_DP_DPHY_SCRAM_CNTL 0x241e
#define mmDP3_DP_DPHY_SCRAM_CNTL_BASE_IDX 2
#define mmDP3_DP_DPHY_CRC_EN 0x241f
#define mmDP3_DP_DPHY_CRC_EN_BASE_IDX 2
#define mmDP3_DP_DPHY_CRC_CNTL 0x2420
#define mmDP3_DP_DPHY_CRC_CNTL_BASE_IDX 2
#define mmDP3_DP_DPHY_CRC_RESULT 0x2421
#define mmDP3_DP_DPHY_CRC_RESULT_BASE_IDX 2
#define mmDP3_DP_DPHY_CRC_MST_CNTL 0x2422
#define mmDP3_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2
#define mmDP3_DP_DPHY_CRC_MST_STATUS 0x2423
#define mmDP3_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2
#define mmDP3_DP_DPHY_FAST_TRAINING 0x2424
#define mmDP3_DP_DPHY_FAST_TRAINING_BASE_IDX 2
#define mmDP3_DP_DPHY_FAST_TRAINING_STATUS 0x2425
#define mmDP3_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2
#define mmDP3_DP_SEC_CNTL 0x242b
#define mmDP3_DP_SEC_CNTL_BASE_IDX 2
#define mmDP3_DP_SEC_CNTL1 0x242c
#define mmDP3_DP_SEC_CNTL1_BASE_IDX 2
#define mmDP3_DP_SEC_FRAMING1 0x242d
#define mmDP3_DP_SEC_FRAMING1_BASE_IDX 2
#define mmDP3_DP_SEC_FRAMING2 0x242e
#define mmDP3_DP_SEC_FRAMING2_BASE_IDX 2
#define mmDP3_DP_SEC_FRAMING3 0x242f
#define mmDP3_DP_SEC_FRAMING3_BASE_IDX 2
#define mmDP3_DP_SEC_FRAMING4 0x2430
#define mmDP3_DP_SEC_FRAMING4_BASE_IDX 2
#define mmDP3_DP_SEC_AUD_N 0x2431
#define mmDP3_DP_SEC_AUD_N_BASE_IDX 2
#define mmDP3_DP_SEC_AUD_N_READBACK 0x2432
#define mmDP3_DP_SEC_AUD_N_READBACK_BASE_IDX 2
#define mmDP3_DP_SEC_AUD_M 0x2433
#define mmDP3_DP_SEC_AUD_M_BASE_IDX 2
#define mmDP3_DP_SEC_AUD_M_READBACK 0x2434
#define mmDP3_DP_SEC_AUD_M_READBACK_BASE_IDX 2
#define mmDP3_DP_SEC_TIMESTAMP 0x2435
#define mmDP3_DP_SEC_TIMESTAMP_BASE_IDX 2
#define mmDP3_DP_SEC_PACKET_CNTL 0x2436
#define mmDP3_DP_SEC_PACKET_CNTL_BASE_IDX 2
#define mmDP3_DP_MSE_RATE_CNTL 0x2437
#define mmDP3_DP_MSE_RATE_CNTL_BASE_IDX 2
#define mmDP3_DP_MSE_RATE_UPDATE 0x2439
#define mmDP3_DP_MSE_RATE_UPDATE_BASE_IDX 2
#define mmDP3_DP_MSE_SAT0 0x243a
#define mmDP3_DP_MSE_SAT0_BASE_IDX 2
#define mmDP3_DP_MSE_SAT1 0x243b
#define mmDP3_DP_MSE_SAT1_BASE_IDX 2
#define mmDP3_DP_MSE_SAT2 0x243c
#define mmDP3_DP_MSE_SAT2_BASE_IDX 2
#define mmDP3_DP_MSE_SAT_UPDATE 0x243d
#define mmDP3_DP_MSE_SAT_UPDATE_BASE_IDX 2
#define mmDP3_DP_MSE_LINK_TIMING 0x243e
#define mmDP3_DP_MSE_LINK_TIMING_BASE_IDX 2
#define mmDP3_DP_MSE_MISC_CNTL 0x243f
#define mmDP3_DP_MSE_MISC_CNTL_BASE_IDX 2
#define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL 0x2444
#define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2
#define mmDP3_DP_DPHY_HBR2_PATTERN_CONTROL 0x2445
#define mmDP3_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2
#define mmDP3_DP_MSE_SAT0_STATUS 0x2447
#define mmDP3_DP_MSE_SAT0_STATUS_BASE_IDX 2
#define mmDP3_DP_MSE_SAT1_STATUS 0x2448
#define mmDP3_DP_MSE_SAT1_STATUS_BASE_IDX 2
#define mmDP3_DP_MSE_SAT2_STATUS 0x2449
#define mmDP3_DP_MSE_SAT2_STATUS_BASE_IDX 2
#define mmDP3_DP_MSA_TIMING_PARAM1 0x244c
#define mmDP3_DP_MSA_TIMING_PARAM1_BASE_IDX 2
#define mmDP3_DP_MSA_TIMING_PARAM2 0x244d
#define mmDP3_DP_MSA_TIMING_PARAM2_BASE_IDX 2
#define mmDP3_DP_MSA_TIMING_PARAM3 0x244e
#define mmDP3_DP_MSA_TIMING_PARAM3_BASE_IDX 2
#define mmDP3_DP_MSA_TIMING_PARAM4 0x244f
#define mmDP3_DP_MSA_TIMING_PARAM4_BASE_IDX 2
#define mmDP3_DP_MSO_CNTL 0x2450
#define mmDP3_DP_MSO_CNTL_BASE_IDX 2
#define mmDP3_DP_MSO_CNTL1 0x2451
#define mmDP3_DP_MSO_CNTL1_BASE_IDX 2
#define mmDP3_DP_DSC_CNTL 0x2452
#define mmDP3_DP_DSC_CNTL_BASE_IDX 2
#define mmDP3_DP_SEC_CNTL2 0x2453
#define mmDP3_DP_SEC_CNTL2_BASE_IDX 2
#define mmDP3_DP_SEC_CNTL3 0x2454
#define mmDP3_DP_SEC_CNTL3_BASE_IDX 2
#define mmDP3_DP_SEC_CNTL4 0x2455
#define mmDP3_DP_SEC_CNTL4_BASE_IDX 2
#define mmDP3_DP_SEC_CNTL5 0x2456
#define mmDP3_DP_SEC_CNTL5_BASE_IDX 2
#define mmDP3_DP_SEC_CNTL6 0x2457
#define mmDP3_DP_SEC_CNTL6_BASE_IDX 2
#define mmDP3_DP_SEC_CNTL7 0x2458
#define mmDP3_DP_SEC_CNTL7_BASE_IDX 2
#define mmDP3_DP_DB_CNTL 0x2459
#define mmDP3_DP_DB_CNTL_BASE_IDX 2
#define mmDP3_DP_MSA_VBID_MISC 0x245a
#define mmDP3_DP_MSA_VBID_MISC_BASE_IDX 2
// addressBlock: dce_dc_dio_dig4_dispdec
// base address: 0x1000
#define mmDIG4_DIG_FE_CNTL 0x2468
#define mmDIG4_DIG_FE_CNTL_BASE_IDX 2
#define mmDIG4_DIG_OUTPUT_CRC_CNTL 0x2469
#define mmDIG4_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2
#define mmDIG4_DIG_OUTPUT_CRC_RESULT 0x246a
#define mmDIG4_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2
#define mmDIG4_DIG_CLOCK_PATTERN 0x246b
#define mmDIG4_DIG_CLOCK_PATTERN_BASE_IDX 2
#define mmDIG4_DIG_TEST_PATTERN 0x246c
#define mmDIG4_DIG_TEST_PATTERN_BASE_IDX 2
#define mmDIG4_DIG_RANDOM_PATTERN_SEED 0x246d
#define mmDIG4_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2
#define mmDIG4_DIG_FIFO_STATUS 0x246e
#define mmDIG4_DIG_FIFO_STATUS_BASE_IDX 2
#define mmDIG4_HDMI_CONTROL 0x2471
#define mmDIG4_HDMI_CONTROL_BASE_IDX 2
#define mmDIG4_HDMI_STATUS 0x2472
#define mmDIG4_HDMI_STATUS_BASE_IDX 2
#define mmDIG4_HDMI_AUDIO_PACKET_CONTROL 0x2473
#define mmDIG4_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2
#define mmDIG4_HDMI_ACR_PACKET_CONTROL 0x2474
#define mmDIG4_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2
#define mmDIG4_HDMI_VBI_PACKET_CONTROL 0x2475
#define mmDIG4_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2
#define mmDIG4_HDMI_INFOFRAME_CONTROL0 0x2476
#define mmDIG4_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2
#define mmDIG4_HDMI_INFOFRAME_CONTROL1 0x2477
#define mmDIG4_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2
#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL0 0x2478
#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2
#define mmDIG4_AFMT_INTERRUPT_STATUS 0x2479
#define mmDIG4_AFMT_INTERRUPT_STATUS_BASE_IDX 2
#define mmDIG4_HDMI_GC 0x247b
#define mmDIG4_HDMI_GC_BASE_IDX 2
#define mmDIG4_AFMT_AUDIO_PACKET_CONTROL2 0x247c
#define mmDIG4_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2
#define mmDIG4_AFMT_ISRC1_0 0x247d
#define mmDIG4_AFMT_ISRC1_0_BASE_IDX 2
#define mmDIG4_AFMT_ISRC1_1 0x247e
#define mmDIG4_AFMT_ISRC1_1_BASE_IDX 2
#define mmDIG4_AFMT_ISRC1_2 0x247f
#define mmDIG4_AFMT_ISRC1_2_BASE_IDX 2
#define mmDIG4_AFMT_ISRC1_3 0x2480
#define mmDIG4_AFMT_ISRC1_3_BASE_IDX 2
#define mmDIG4_AFMT_ISRC1_4 0x2481
#define mmDIG4_AFMT_ISRC1_4_BASE_IDX 2
#define mmDIG4_AFMT_ISRC2_0 0x2482
#define mmDIG4_AFMT_ISRC2_0_BASE_IDX 2
#define mmDIG4_AFMT_ISRC2_1 0x2483
#define mmDIG4_AFMT_ISRC2_1_BASE_IDX 2
#define mmDIG4_AFMT_ISRC2_2 0x2484
#define mmDIG4_AFMT_ISRC2_2_BASE_IDX 2
#define mmDIG4_AFMT_ISRC2_3 0x2485
#define mmDIG4_AFMT_ISRC2_3_BASE_IDX 2
#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL2 0x2486
#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2
#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL3 0x2487
#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2
#define mmDIG4_HDMI_DB_CONTROL 0x2488
#define mmDIG4_HDMI_DB_CONTROL_BASE_IDX 2
#define mmDIG4_AFMT_MPEG_INFO0 0x248a
#define mmDIG4_AFMT_MPEG_INFO0_BASE_IDX 2
#define mmDIG4_AFMT_MPEG_INFO1 0x248b
#define mmDIG4_AFMT_MPEG_INFO1_BASE_IDX 2
#define mmDIG4_AFMT_GENERIC_HDR 0x248c
#define mmDIG4_AFMT_GENERIC_HDR_BASE_IDX 2
#define mmDIG4_AFMT_GENERIC_0 0x248d
#define mmDIG4_AFMT_GENERIC_0_BASE_IDX 2
#define mmDIG4_AFMT_GENERIC_1 0x248e
#define mmDIG4_AFMT_GENERIC_1_BASE_IDX 2
#define mmDIG4_AFMT_GENERIC_2 0x248f
#define mmDIG4_AFMT_GENERIC_2_BASE_IDX 2
#define mmDIG4_AFMT_GENERIC_3 0x2490
#define mmDIG4_AFMT_GENERIC_3_BASE_IDX 2
#define mmDIG4_AFMT_GENERIC_4 0x2491
#define mmDIG4_AFMT_GENERIC_4_BASE_IDX 2
#define mmDIG4_AFMT_GENERIC_5 0x2492
#define mmDIG4_AFMT_GENERIC_5_BASE_IDX 2
#define mmDIG4_AFMT_GENERIC_6 0x2493
#define mmDIG4_AFMT_GENERIC_6_BASE_IDX 2
#define mmDIG4_AFMT_GENERIC_7 0x2494
#define mmDIG4_AFMT_GENERIC_7_BASE_IDX 2
#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL1 0x2495
#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2
#define mmDIG4_HDMI_ACR_32_0 0x2496
#define mmDIG4_HDMI_ACR_32_0_BASE_IDX 2
#define mmDIG4_HDMI_ACR_32_1 0x2497
#define mmDIG4_HDMI_ACR_32_1_BASE_IDX 2
#define mmDIG4_HDMI_ACR_44_0 0x2498
#define mmDIG4_HDMI_ACR_44_0_BASE_IDX 2
#define mmDIG4_HDMI_ACR_44_1 0x2499
#define mmDIG4_HDMI_ACR_44_1_BASE_IDX 2
#define mmDIG4_HDMI_ACR_48_0 0x249a
#define mmDIG4_HDMI_ACR_48_0_BASE_IDX 2
#define mmDIG4_HDMI_ACR_48_1 0x249b
#define mmDIG4_HDMI_ACR_48_1_BASE_IDX 2
#define mmDIG4_HDMI_ACR_STATUS_0 0x249c
#define mmDIG4_HDMI_ACR_STATUS_0_BASE_IDX 2
#define mmDIG4_HDMI_ACR_STATUS_1 0x249d
#define mmDIG4_HDMI_ACR_STATUS_1_BASE_IDX 2
#define mmDIG4_AFMT_AUDIO_INFO0 0x249e
#define mmDIG4_AFMT_AUDIO_INFO0_BASE_IDX 2
#define mmDIG4_AFMT_AUDIO_INFO1 0x249f
#define mmDIG4_AFMT_AUDIO_INFO1_BASE_IDX 2
#define mmDIG4_AFMT_60958_0 0x24a0
#define mmDIG4_AFMT_60958_0_BASE_IDX 2
#define mmDIG4_AFMT_60958_1 0x24a1
#define mmDIG4_AFMT_60958_1_BASE_IDX 2
#define mmDIG4_AFMT_AUDIO_CRC_CONTROL 0x24a2
#define mmDIG4_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2
#define mmDIG4_AFMT_RAMP_CONTROL0 0x24a3
#define mmDIG4_AFMT_RAMP_CONTROL0_BASE_IDX 2
#define mmDIG4_AFMT_RAMP_CONTROL1 0x24a4
#define mmDIG4_AFMT_RAMP_CONTROL1_BASE_IDX 2
#define mmDIG4_AFMT_RAMP_CONTROL2 0x24a5
#define mmDIG4_AFMT_RAMP_CONTROL2_BASE_IDX 2
#define mmDIG4_AFMT_RAMP_CONTROL3 0x24a6
#define mmDIG4_AFMT_RAMP_CONTROL3_BASE_IDX 2
#define mmDIG4_AFMT_60958_2 0x24a7
#define mmDIG4_AFMT_60958_2_BASE_IDX 2
#define mmDIG4_AFMT_AUDIO_CRC_RESULT 0x24a8
#define mmDIG4_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2
#define mmDIG4_AFMT_STATUS 0x24a9
#define mmDIG4_AFMT_STATUS_BASE_IDX 2
#define mmDIG4_AFMT_AUDIO_PACKET_CONTROL 0x24aa
#define mmDIG4_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2
#define mmDIG4_AFMT_VBI_PACKET_CONTROL 0x24ab
#define mmDIG4_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2
#define mmDIG4_AFMT_INFOFRAME_CONTROL0 0x24ac
#define mmDIG4_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2
#define mmDIG4_AFMT_AUDIO_SRC_CONTROL 0x24ad
#define mmDIG4_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2
#define mmDIG4_DIG_BE_CNTL 0x24af
#define mmDIG4_DIG_BE_CNTL_BASE_IDX 2
#define mmDIG4_DIG_BE_EN_CNTL 0x24b0
#define mmDIG4_DIG_BE_EN_CNTL_BASE_IDX 2
#define mmDIG4_TMDS_CNTL 0x24d3
#define mmDIG4_TMDS_CNTL_BASE_IDX 2
#define mmDIG4_TMDS_CONTROL_CHAR 0x24d4
#define mmDIG4_TMDS_CONTROL_CHAR_BASE_IDX 2
#define mmDIG4_TMDS_CONTROL0_FEEDBACK 0x24d5
#define mmDIG4_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2
#define mmDIG4_TMDS_STEREOSYNC_CTL_SEL 0x24d6
#define mmDIG4_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2
#define mmDIG4_TMDS_SYNC_CHAR_PATTERN_0_1 0x24d7
#define mmDIG4_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2
#define mmDIG4_TMDS_SYNC_CHAR_PATTERN_2_3 0x24d8
#define mmDIG4_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2
#define mmDIG4_TMDS_CTL_BITS 0x24da
#define mmDIG4_TMDS_CTL_BITS_BASE_IDX 2
#define mmDIG4_TMDS_DCBALANCER_CONTROL 0x24db
#define mmDIG4_TMDS_DCBALANCER_CONTROL_BASE_IDX 2
#define mmDIG4_TMDS_CTL0_1_GEN_CNTL 0x24dd
#define mmDIG4_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2
#define mmDIG4_TMDS_CTL2_3_GEN_CNTL 0x24de
#define mmDIG4_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2
#define mmDIG4_DIG_VERSION 0x24e0
#define mmDIG4_DIG_VERSION_BASE_IDX 2
#define mmDIG4_DIG_LANE_ENABLE 0x24e1
#define mmDIG4_DIG_LANE_ENABLE_BASE_IDX 2
#define mmDIG4_AFMT_CNTL 0x24e6
#define mmDIG4_AFMT_CNTL_BASE_IDX 2
#define mmDIG4_AFMT_VBI_PACKET_CONTROL1 0x24e7
#define mmDIG4_AFMT_VBI_PACKET_CONTROL1_BASE_IDX 2
// addressBlock: dce_dc_dio_dp4_dispdec
// base address: 0x1000
#define mmDP4_DP_LINK_CNTL 0x2508
#define mmDP4_DP_LINK_CNTL_BASE_IDX 2
#define mmDP4_DP_PIXEL_FORMAT 0x2509
#define mmDP4_DP_PIXEL_FORMAT_BASE_IDX 2
#define mmDP4_DP_MSA_COLORIMETRY 0x250a
#define mmDP4_DP_MSA_COLORIMETRY_BASE_IDX 2
#define mmDP4_DP_CONFIG 0x250b
#define mmDP4_DP_CONFIG_BASE_IDX 2
#define mmDP4_DP_VID_STREAM_CNTL 0x250c
#define mmDP4_DP_VID_STREAM_CNTL_BASE_IDX 2
#define mmDP4_DP_STEER_FIFO 0x250d
#define mmDP4_DP_STEER_FIFO_BASE_IDX 2
#define mmDP4_DP_MSA_MISC 0x250e
#define mmDP4_DP_MSA_MISC_BASE_IDX 2
#define mmDP4_DP_VID_TIMING 0x2510
#define mmDP4_DP_VID_TIMING_BASE_IDX 2
#define mmDP4_DP_VID_N 0x2511
#define mmDP4_DP_VID_N_BASE_IDX 2
#define mmDP4_DP_VID_M 0x2512
#define mmDP4_DP_VID_M_BASE_IDX 2
#define mmDP4_DP_LINK_FRAMING_CNTL 0x2513
#define mmDP4_DP_LINK_FRAMING_CNTL_BASE_IDX 2
#define mmDP4_DP_HBR2_EYE_PATTERN 0x2514
#define mmDP4_DP_HBR2_EYE_PATTERN_BASE_IDX 2
#define mmDP4_DP_VID_MSA_VBID 0x2515
#define mmDP4_DP_VID_MSA_VBID_BASE_IDX 2
#define mmDP4_DP_VID_INTERRUPT_CNTL 0x2516
#define mmDP4_DP_VID_INTERRUPT_CNTL_BASE_IDX 2
#define mmDP4_DP_DPHY_CNTL 0x2517
#define mmDP4_DP_DPHY_CNTL_BASE_IDX 2
#define mmDP4_DP_DPHY_TRAINING_PATTERN_SEL 0x2518
#define mmDP4_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2
#define mmDP4_DP_DPHY_SYM0 0x2519
#define mmDP4_DP_DPHY_SYM0_BASE_IDX 2
#define mmDP4_DP_DPHY_SYM1 0x251a
#define mmDP4_DP_DPHY_SYM1_BASE_IDX 2
#define mmDP4_DP_DPHY_SYM2 0x251b
#define mmDP4_DP_DPHY_SYM2_BASE_IDX 2
#define mmDP4_DP_DPHY_8B10B_CNTL 0x251c
#define mmDP4_DP_DPHY_8B10B_CNTL_BASE_IDX 2
#define mmDP4_DP_DPHY_PRBS_CNTL 0x251d
#define mmDP4_DP_DPHY_PRBS_CNTL_BASE_IDX 2
#define mmDP4_DP_DPHY_SCRAM_CNTL 0x251e
#define mmDP4_DP_DPHY_SCRAM_CNTL_BASE_IDX 2
#define mmDP4_DP_DPHY_CRC_EN 0x251f
#define mmDP4_DP_DPHY_CRC_EN_BASE_IDX 2
#define mmDP4_DP_DPHY_CRC_CNTL 0x2520
#define mmDP4_DP_DPHY_CRC_CNTL_BASE_IDX 2
#define mmDP4_DP_DPHY_CRC_RESULT 0x2521
#define mmDP4_DP_DPHY_CRC_RESULT_BASE_IDX 2
#define mmDP4_DP_DPHY_CRC_MST_CNTL 0x2522
#define mmDP4_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2
#define mmDP4_DP_DPHY_CRC_MST_STATUS 0x2523
#define mmDP4_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2
#define mmDP4_DP_DPHY_FAST_TRAINING 0x2524
#define mmDP4_DP_DPHY_FAST_TRAINING_BASE_IDX 2
#define mmDP4_DP_DPHY_FAST_TRAINING_STATUS 0x2525
#define mmDP4_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2
#define mmDP4_DP_SEC_CNTL 0x252b
#define mmDP4_DP_SEC_CNTL_BASE_IDX 2
#define mmDP4_DP_SEC_CNTL1 0x252c
#define mmDP4_DP_SEC_CNTL1_BASE_IDX 2
#define mmDP4_DP_SEC_FRAMING1 0x252d
#define mmDP4_DP_SEC_FRAMING1_BASE_IDX 2
#define mmDP4_DP_SEC_FRAMING2 0x252e
#define mmDP4_DP_SEC_FRAMING2_BASE_IDX 2
#define mmDP4_DP_SEC_FRAMING3 0x252f
#define mmDP4_DP_SEC_FRAMING3_BASE_IDX 2
#define mmDP4_DP_SEC_FRAMING4 0x2530
#define mmDP4_DP_SEC_FRAMING4_BASE_IDX 2
#define mmDP4_DP_SEC_AUD_N 0x2531
#define mmDP4_DP_SEC_AUD_N_BASE_IDX 2
#define mmDP4_DP_SEC_AUD_N_READBACK 0x2532
#define mmDP4_DP_SEC_AUD_N_READBACK_BASE_IDX 2
#define mmDP4_DP_SEC_AUD_M 0x2533
#define mmDP4_DP_SEC_AUD_M_BASE_IDX 2
#define mmDP4_DP_SEC_AUD_M_READBACK 0x2534
#define mmDP4_DP_SEC_AUD_M_READBACK_BASE_IDX 2
#define mmDP4_DP_SEC_TIMESTAMP 0x2535
#define mmDP4_DP_SEC_TIMESTAMP_BASE_IDX 2
#define mmDP4_DP_SEC_PACKET_CNTL 0x2536
#define mmDP4_DP_SEC_PACKET_CNTL_BASE_IDX 2
#define mmDP4_DP_MSE_RATE_CNTL 0x2537
#define mmDP4_DP_MSE_RATE_CNTL_BASE_IDX 2
#define mmDP4_DP_MSE_RATE_UPDATE 0x2539
#define mmDP4_DP_MSE_RATE_UPDATE_BASE_IDX 2
#define mmDP4_DP_MSE_SAT0 0x253a
#define mmDP4_DP_MSE_SAT0_BASE_IDX 2
#define mmDP4_DP_MSE_SAT1 0x253b
#define mmDP4_DP_MSE_SAT1_BASE_IDX 2
#define mmDP4_DP_MSE_SAT2 0x253c
#define mmDP4_DP_MSE_SAT2_BASE_IDX 2
#define mmDP4_DP_MSE_SAT_UPDATE 0x253d
#define mmDP4_DP_MSE_SAT_UPDATE_BASE_IDX 2
#define mmDP4_DP_MSE_LINK_TIMING 0x253e
#define mmDP4_DP_MSE_LINK_TIMING_BASE_IDX 2
#define mmDP4_DP_MSE_MISC_CNTL 0x253f
#define mmDP4_DP_MSE_MISC_CNTL_BASE_IDX 2
#define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL 0x2544
#define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2
#define mmDP4_DP_DPHY_HBR2_PATTERN_CONTROL 0x2545
#define mmDP4_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2
#define mmDP4_DP_MSE_SAT0_STATUS 0x2547
#define mmDP4_DP_MSE_SAT0_STATUS_BASE_IDX 2
#define mmDP4_DP_MSE_SAT1_STATUS 0x2548
#define mmDP4_DP_MSE_SAT1_STATUS_BASE_IDX 2
#define mmDP4_DP_MSE_SAT2_STATUS 0x2549
#define mmDP4_DP_MSE_SAT2_STATUS_BASE_IDX 2
#define mmDP4_DP_MSA_TIMING_PARAM1 0x254c
#define mmDP4_DP_MSA_TIMING_PARAM1_BASE_IDX 2
#define mmDP4_DP_MSA_TIMING_PARAM2 0x254d
#define mmDP4_DP_MSA_TIMING_PARAM2_BASE_IDX 2
#define mmDP4_DP_MSA_TIMING_PARAM3 0x254e
#define mmDP4_DP_MSA_TIMING_PARAM3_BASE_IDX 2
#define mmDP4_DP_MSA_TIMING_PARAM4 0x254f
#define mmDP4_DP_MSA_TIMING_PARAM4_BASE_IDX 2
#define mmDP4_DP_MSO_CNTL 0x2550
#define mmDP4_DP_MSO_CNTL_BASE_IDX 2
#define mmDP4_DP_MSO_CNTL1 0x2551
#define mmDP4_DP_MSO_CNTL1_BASE_IDX 2
#define mmDP4_DP_DSC_CNTL 0x2552
#define mmDP4_DP_DSC_CNTL_BASE_IDX 2
#define mmDP4_DP_SEC_CNTL2 0x2553
#define mmDP4_DP_SEC_CNTL2_BASE_IDX 2
#define mmDP4_DP_SEC_CNTL3 0x2554
#define mmDP4_DP_SEC_CNTL3_BASE_IDX 2
#define mmDP4_DP_SEC_CNTL4 0x2555
#define mmDP4_DP_SEC_CNTL4_BASE_IDX 2
#define mmDP4_DP_SEC_CNTL5 0x2556
#define mmDP4_DP_SEC_CNTL5_BASE_IDX 2
#define mmDP4_DP_SEC_CNTL6 0x2557
#define mmDP4_DP_SEC_CNTL6_BASE_IDX 2
#define mmDP4_DP_SEC_CNTL7 0x2558
#define mmDP4_DP_SEC_CNTL7_BASE_IDX 2
#define mmDP4_DP_DB_CNTL 0x2559
#define mmDP4_DP_DB_CNTL_BASE_IDX 2
#define mmDP4_DP_MSA_VBID_MISC 0x255a
#define mmDP4_DP_MSA_VBID_MISC_BASE_IDX 2
// addressBlock: dce_dc_dio_dig5_dispdec
// base address: 0x1400
#define mmDIG5_DIG_FE_CNTL 0x2568
#define mmDIG5_DIG_FE_CNTL_BASE_IDX 2
#define mmDIG5_DIG_OUTPUT_CRC_CNTL 0x2569
#define mmDIG5_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2
#define mmDIG5_DIG_OUTPUT_CRC_RESULT 0x256a
#define mmDIG5_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2
#define mmDIG5_DIG_CLOCK_PATTERN 0x256b
#define mmDIG5_DIG_CLOCK_PATTERN_BASE_IDX 2
#define mmDIG5_DIG_TEST_PATTERN 0x256c
#define mmDIG5_DIG_TEST_PATTERN_BASE_IDX 2
#define mmDIG5_DIG_RANDOM_PATTERN_SEED 0x256d
#define mmDIG5_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2
#define mmDIG5_DIG_FIFO_STATUS 0x256e
#define mmDIG5_DIG_FIFO_STATUS_BASE_IDX 2
#define mmDIG5_HDMI_CONTROL 0x2571
#define mmDIG5_HDMI_CONTROL_BASE_IDX 2
#define mmDIG5_HDMI_STATUS 0x2572
#define mmDIG5_HDMI_STATUS_BASE_IDX 2
#define mmDIG5_HDMI_AUDIO_PACKET_CONTROL 0x2573
#define mmDIG5_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2
#define mmDIG5_HDMI_ACR_PACKET_CONTROL 0x2574
#define mmDIG5_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2
#define mmDIG5_HDMI_VBI_PACKET_CONTROL 0x2575
#define mmDIG5_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2
#define mmDIG5_HDMI_INFOFRAME_CONTROL0 0x2576
#define mmDIG5_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2
#define mmDIG5_HDMI_INFOFRAME_CONTROL1 0x2577
#define mmDIG5_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2
#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL0 0x2578
#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2
#define mmDIG5_AFMT_INTERRUPT_STATUS 0x2579
#define mmDIG5_AFMT_INTERRUPT_STATUS_BASE_IDX 2
#define mmDIG5_HDMI_GC 0x257b
#define mmDIG5_HDMI_GC_BASE_IDX 2
#define mmDIG5_AFMT_AUDIO_PACKET_CONTROL2 0x257c
#define mmDIG5_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2
#define mmDIG5_AFMT_ISRC1_0 0x257d
#define mmDIG5_AFMT_ISRC1_0_BASE_IDX 2
#define mmDIG5_AFMT_ISRC1_1 0x257e
#define mmDIG5_AFMT_ISRC1_1_BASE_IDX 2
#define mmDIG5_AFMT_ISRC1_2 0x257f
#define mmDIG5_AFMT_ISRC1_2_BASE_IDX 2
#define mmDIG5_AFMT_ISRC1_3 0x2580
#define mmDIG5_AFMT_ISRC1_3_BASE_IDX 2
#define mmDIG5_AFMT_ISRC1_4 0x2581
#define mmDIG5_AFMT_ISRC1_4_BASE_IDX 2
#define mmDIG5_AFMT_ISRC2_0 0x2582
#define mmDIG5_AFMT_ISRC2_0_BASE_IDX 2
#define mmDIG5_AFMT_ISRC2_1 0x2583
#define mmDIG5_AFMT_ISRC2_1_BASE_IDX 2
#define mmDIG5_AFMT_ISRC2_2 0x2584
#define mmDIG5_AFMT_ISRC2_2_BASE_IDX 2
#define mmDIG5_AFMT_ISRC2_3 0x2585
#define mmDIG5_AFMT_ISRC2_3_BASE_IDX 2
#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL2 0x2586
#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2
#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL3 0x2587
#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2
#define mmDIG5_HDMI_DB_CONTROL 0x2588
#define mmDIG5_HDMI_DB_CONTROL_BASE_IDX 2
#define mmDIG5_AFMT_MPEG_INFO0 0x258a
#define mmDIG5_AFMT_MPEG_INFO0_BASE_IDX 2
#define mmDIG5_AFMT_MPEG_INFO1 0x258b
#define mmDIG5_AFMT_MPEG_INFO1_BASE_IDX 2
#define mmDIG5_AFMT_GENERIC_HDR 0x258c
#define mmDIG5_AFMT_GENERIC_HDR_BASE_IDX 2
#define mmDIG5_AFMT_GENERIC_0 0x258d
#define mmDIG5_AFMT_GENERIC_0_BASE_IDX 2
#define mmDIG5_AFMT_GENERIC_1 0x258e
#define mmDIG5_AFMT_GENERIC_1_BASE_IDX 2
#define mmDIG5_AFMT_GENERIC_2 0x258f
#define mmDIG5_AFMT_GENERIC_2_BASE_IDX 2
#define mmDIG5_AFMT_GENERIC_3 0x2590
#define mmDIG5_AFMT_GENERIC_3_BASE_IDX 2
#define mmDIG5_AFMT_GENERIC_4 0x2591
#define mmDIG5_AFMT_GENERIC_4_BASE_IDX 2
#define mmDIG5_AFMT_GENERIC_5 0x2592
#define mmDIG5_AFMT_GENERIC_5_BASE_IDX 2
#define mmDIG5_AFMT_GENERIC_6 0x2593
#define mmDIG5_AFMT_GENERIC_6_BASE_IDX 2
#define mmDIG5_AFMT_GENERIC_7 0x2594
#define mmDIG5_AFMT_GENERIC_7_BASE_IDX 2
#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL1 0x2595
#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2
#define mmDIG5_HDMI_ACR_32_0 0x2596
#define mmDIG5_HDMI_ACR_32_0_BASE_IDX 2
#define mmDIG5_HDMI_ACR_32_1 0x2597
#define mmDIG5_HDMI_ACR_32_1_BASE_IDX 2
#define mmDIG5_HDMI_ACR_44_0 0x2598
#define mmDIG5_HDMI_ACR_44_0_BASE_IDX 2
#define mmDIG5_HDMI_ACR_44_1 0x2599
#define mmDIG5_HDMI_ACR_44_1_BASE_IDX 2
#define mmDIG5_HDMI_ACR_48_0 0x259a
#define mmDIG5_HDMI_ACR_48_0_BASE_IDX 2
#define mmDIG5_HDMI_ACR_48_1 0x259b
#define mmDIG5_HDMI_ACR_48_1_BASE_IDX 2
#define mmDIG5_HDMI_ACR_STATUS_0 0x259c
#define mmDIG5_HDMI_ACR_STATUS_0_BASE_IDX 2
#define mmDIG5_HDMI_ACR_STATUS_1 0x259d
#define mmDIG5_HDMI_ACR_STATUS_1_BASE_IDX 2
#define mmDIG5_AFMT_AUDIO_INFO0 0x259e
#define mmDIG5_AFMT_AUDIO_INFO0_BASE_IDX 2
#define mmDIG5_AFMT_AUDIO_INFO1 0x259f
#define mmDIG5_AFMT_AUDIO_INFO1_BASE_IDX 2
#define mmDIG5_AFMT_60958_0 0x25a0
#define mmDIG5_AFMT_60958_0_BASE_IDX 2
#define mmDIG5_AFMT_60958_1 0x25a1
#define mmDIG5_AFMT_60958_1_BASE_IDX 2
#define mmDIG5_AFMT_AUDIO_CRC_CONTROL 0x25a2
#define mmDIG5_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2
#define mmDIG5_AFMT_RAMP_CONTROL0 0x25a3
#define mmDIG5_AFMT_RAMP_CONTROL0_BASE_IDX 2
#define mmDIG5_AFMT_RAMP_CONTROL1 0x25a4
#define mmDIG5_AFMT_RAMP_CONTROL1_BASE_IDX 2
#define mmDIG5_AFMT_RAMP_CONTROL2 0x25a5
#define mmDIG5_AFMT_RAMP_CONTROL2_BASE_IDX 2
#define mmDIG5_AFMT_RAMP_CONTROL3 0x25a6
#define mmDIG5_AFMT_RAMP_CONTROL3_BASE_IDX 2
#define mmDIG5_AFMT_60958_2 0x25a7
#define mmDIG5_AFMT_60958_2_BASE_IDX 2
#define mmDIG5_AFMT_AUDIO_CRC_RESULT 0x25a8
#define mmDIG5_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2
#define mmDIG5_AFMT_STATUS 0x25a9
#define mmDIG5_AFMT_STATUS_BASE_IDX 2
#define mmDIG5_AFMT_AUDIO_PACKET_CONTROL 0x25aa
#define mmDIG5_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2
#define mmDIG5_AFMT_VBI_PACKET_CONTROL 0x25ab
#define mmDIG5_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2
#define mmDIG5_AFMT_INFOFRAME_CONTROL0 0x25ac
#define mmDIG5_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2
#define mmDIG5_AFMT_AUDIO_SRC_CONTROL 0x25ad
#define mmDIG5_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2
#define mmDIG5_DIG_BE_CNTL 0x25af
#define mmDIG5_DIG_BE_CNTL_BASE_IDX 2
#define mmDIG5_DIG_BE_EN_CNTL 0x25b0
#define mmDIG5_DIG_BE_EN_CNTL_BASE_IDX 2
#define mmDIG5_TMDS_CNTL 0x25d3
#define mmDIG5_TMDS_CNTL_BASE_IDX 2
#define mmDIG5_TMDS_CONTROL_CHAR 0x25d4
#define mmDIG5_TMDS_CONTROL_CHAR_BASE_IDX 2
#define mmDIG5_TMDS_CONTROL0_FEEDBACK 0x25d5
#define mmDIG5_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2
#define mmDIG5_TMDS_STEREOSYNC_CTL_SEL 0x25d6
#define mmDIG5_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2
#define mmDIG5_TMDS_SYNC_CHAR_PATTERN_0_1 0x25d7
#define mmDIG5_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2
#define mmDIG5_TMDS_SYNC_CHAR_PATTERN_2_3 0x25d8
#define mmDIG5_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2
#define mmDIG5_TMDS_CTL_BITS 0x25da
#define mmDIG5_TMDS_CTL_BITS_BASE_IDX 2
#define mmDIG5_TMDS_DCBALANCER_CONTROL 0x25db
#define mmDIG5_TMDS_DCBALANCER_CONTROL_BASE_IDX 2
#define mmDIG5_TMDS_CTL0_1_GEN_CNTL 0x25dd
#define mmDIG5_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2
#define mmDIG5_TMDS_CTL2_3_GEN_CNTL 0x25de
#define mmDIG5_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2
#define mmDIG5_DIG_VERSION 0x25e0
#define mmDIG5_DIG_VERSION_BASE_IDX 2
#define mmDIG5_DIG_LANE_ENABLE 0x25e1
#define mmDIG5_DIG_LANE_ENABLE_BASE_IDX 2
#define mmDIG5_AFMT_CNTL 0x25e6
#define mmDIG5_AFMT_CNTL_BASE_IDX 2
#define mmDIG5_AFMT_VBI_PACKET_CONTROL1 0x25e7
#define mmDIG5_AFMT_VBI_PACKET_CONTROL1_BASE_IDX 2
// addressBlock: dce_dc_dio_dp5_dispdec
// base address: 0x1400
#define mmDP5_DP_LINK_CNTL 0x2608
#define mmDP5_DP_LINK_CNTL_BASE_IDX 2
#define mmDP5_DP_PIXEL_FORMAT 0x2609
#define mmDP5_DP_PIXEL_FORMAT_BASE_IDX 2
#define mmDP5_DP_MSA_COLORIMETRY 0x260a
#define mmDP5_DP_MSA_COLORIMETRY_BASE_IDX 2
#define mmDP5_DP_CONFIG 0x260b
#define mmDP5_DP_CONFIG_BASE_IDX 2
#define mmDP5_DP_VID_STREAM_CNTL 0x260c
#define mmDP5_DP_VID_STREAM_CNTL_BASE_IDX 2
#define mmDP5_DP_STEER_FIFO 0x260d
#define mmDP5_DP_STEER_FIFO_BASE_IDX 2
#define mmDP5_DP_MSA_MISC 0x260e
#define mmDP5_DP_MSA_MISC_BASE_IDX 2
#define mmDP5_DP_VID_TIMING 0x2610
#define mmDP5_DP_VID_TIMING_BASE_IDX 2
#define mmDP5_DP_VID_N 0x2611
#define mmDP5_DP_VID_N_BASE_IDX 2
#define mmDP5_DP_VID_M 0x2612
#define mmDP5_DP_VID_M_BASE_IDX 2
#define mmDP5_DP_LINK_FRAMING_CNTL 0x2613
#define mmDP5_DP_LINK_FRAMING_CNTL_BASE_IDX 2
#define mmDP5_DP_HBR2_EYE_PATTERN 0x2614
#define mmDP5_DP_HBR2_EYE_PATTERN_BASE_IDX 2
#define mmDP5_DP_VID_MSA_VBID 0x2615
#define mmDP5_DP_VID_MSA_VBID_BASE_IDX 2
#define mmDP5_DP_VID_INTERRUPT_CNTL 0x2616
#define mmDP5_DP_VID_INTERRUPT_CNTL_BASE_IDX 2
#define mmDP5_DP_DPHY_CNTL 0x2617
#define mmDP5_DP_DPHY_CNTL_BASE_IDX 2
#define mmDP5_DP_DPHY_TRAINING_PATTERN_SEL 0x2618
#define mmDP5_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2
#define mmDP5_DP_DPHY_SYM0 0x2619
#define mmDP5_DP_DPHY_SYM0_BASE_IDX 2
#define mmDP5_DP_DPHY_SYM1 0x261a
#define mmDP5_DP_DPHY_SYM1_BASE_IDX 2
#define mmDP5_DP_DPHY_SYM2 0x261b
#define mmDP5_DP_DPHY_SYM2_BASE_IDX 2
#define mmDP5_DP_DPHY_8B10B_CNTL 0x261c
#define mmDP5_DP_DPHY_8B10B_CNTL_BASE_IDX 2
#define mmDP5_DP_DPHY_PRBS_CNTL 0x261d
#define mmDP5_DP_DPHY_PRBS_CNTL_BASE_IDX 2
#define mmDP5_DP_DPHY_SCRAM_CNTL 0x261e
#define mmDP5_DP_DPHY_SCRAM_CNTL_BASE_IDX 2
#define mmDP5_DP_DPHY_CRC_EN 0x261f
#define mmDP5_DP_DPHY_CRC_EN_BASE_IDX 2
#define mmDP5_DP_DPHY_CRC_CNTL 0x2620
#define mmDP5_DP_DPHY_CRC_CNTL_BASE_IDX 2
#define mmDP5_DP_DPHY_CRC_RESULT 0x2621
#define mmDP5_DP_DPHY_CRC_RESULT_BASE_IDX 2
#define mmDP5_DP_DPHY_CRC_MST_CNTL 0x2622
#define mmDP5_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2
#define mmDP5_DP_DPHY_CRC_MST_STATUS 0x2623
#define mmDP5_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2
#define mmDP5_DP_DPHY_FAST_TRAINING 0x2624
#define mmDP5_DP_DPHY_FAST_TRAINING_BASE_IDX 2
#define mmDP5_DP_DPHY_FAST_TRAINING_STATUS 0x2625
#define mmDP5_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2
#define mmDP5_DP_SEC_CNTL 0x262b
#define mmDP5_DP_SEC_CNTL_BASE_IDX 2
#define mmDP5_DP_SEC_CNTL1 0x262c
#define mmDP5_DP_SEC_CNTL1_BASE_IDX 2
#define mmDP5_DP_SEC_FRAMING1 0x262d
#define mmDP5_DP_SEC_FRAMING1_BASE_IDX 2
#define mmDP5_DP_SEC_FRAMING2 0x262e
#define mmDP5_DP_SEC_FRAMING2_BASE_IDX 2
#define mmDP5_DP_SEC_FRAMING3 0x262f
#define mmDP5_DP_SEC_FRAMING3_BASE_IDX 2
#define mmDP5_DP_SEC_FRAMING4 0x2630
#define mmDP5_DP_SEC_FRAMING4_BASE_IDX 2
#define mmDP5_DP_SEC_AUD_N 0x2631
#define mmDP5_DP_SEC_AUD_N_BASE_IDX 2
#define mmDP5_DP_SEC_AUD_N_READBACK 0x2632
#define mmDP5_DP_SEC_AUD_N_READBACK_BASE_IDX 2
#define mmDP5_DP_SEC_AUD_M 0x2633
#define mmDP5_DP_SEC_AUD_M_BASE_IDX 2
#define mmDP5_DP_SEC_AUD_M_READBACK 0x2634
#define mmDP5_DP_SEC_AUD_M_READBACK_BASE_IDX 2
#define mmDP5_DP_SEC_TIMESTAMP 0x2635
#define mmDP5_DP_SEC_TIMESTAMP_BASE_IDX 2
#define mmDP5_DP_SEC_PACKET_CNTL 0x2636
#define mmDP5_DP_SEC_PACKET_CNTL_BASE_IDX 2
#define mmDP5_DP_MSE_RATE_CNTL 0x2637
#define mmDP5_DP_MSE_RATE_CNTL_BASE_IDX 2
#define mmDP5_DP_MSE_RATE_UPDATE 0x2639
#define mmDP5_DP_MSE_RATE_UPDATE_BASE_IDX 2
#define mmDP5_DP_MSE_SAT0 0x263a
#define mmDP5_DP_MSE_SAT0_BASE_IDX 2
#define mmDP5_DP_MSE_SAT1 0x263b
#define mmDP5_DP_MSE_SAT1_BASE_IDX 2
#define mmDP5_DP_MSE_SAT2 0x263c
#define mmDP5_DP_MSE_SAT2_BASE_IDX 2
#define mmDP5_DP_MSE_SAT_UPDATE 0x263d
#define mmDP5_DP_MSE_SAT_UPDATE_BASE_IDX 2
#define mmDP5_DP_MSE_LINK_TIMING 0x263e
#define mmDP5_DP_MSE_LINK_TIMING_BASE_IDX 2
#define mmDP5_DP_MSE_MISC_CNTL 0x263f
#define mmDP5_DP_MSE_MISC_CNTL_BASE_IDX 2
#define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL 0x2644
#define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2
#define mmDP5_DP_DPHY_HBR2_PATTERN_CONTROL 0x2645
#define mmDP5_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2
#define mmDP5_DP_MSE_SAT0_STATUS 0x2647
#define mmDP5_DP_MSE_SAT0_STATUS_BASE_IDX 2
#define mmDP5_DP_MSE_SAT1_STATUS 0x2648
#define mmDP5_DP_MSE_SAT1_STATUS_BASE_IDX 2
#define mmDP5_DP_MSE_SAT2_STATUS 0x2649
#define mmDP5_DP_MSE_SAT2_STATUS_BASE_IDX 2
#define mmDP5_DP_MSA_TIMING_PARAM1 0x264c
#define mmDP5_DP_MSA_TIMING_PARAM1_BASE_IDX 2
#define mmDP5_DP_MSA_TIMING_PARAM2 0x264d
#define mmDP5_DP_MSA_TIMING_PARAM2_BASE_IDX 2
#define mmDP5_DP_MSA_TIMING_PARAM3 0x264e
#define mmDP5_DP_MSA_TIMING_PARAM3_BASE_IDX 2
#define mmDP5_DP_MSA_TIMING_PARAM4 0x264f
#define mmDP5_DP_MSA_TIMING_PARAM4_BASE_IDX 2
#define mmDP5_DP_MSO_CNTL 0x2650
#define mmDP5_DP_MSO_CNTL_BASE_IDX 2
#define mmDP5_DP_MSO_CNTL1 0x2651
#define mmDP5_DP_MSO_CNTL1_BASE_IDX 2
#define mmDP5_DP_DSC_CNTL 0x2652
#define mmDP5_DP_DSC_CNTL_BASE_IDX 2
#define mmDP5_DP_SEC_CNTL2 0x2653
#define mmDP5_DP_SEC_CNTL2_BASE_IDX 2
#define mmDP5_DP_SEC_CNTL3 0x2654
#define mmDP5_DP_SEC_CNTL3_BASE_IDX 2
#define mmDP5_DP_SEC_CNTL4 0x2655
#define mmDP5_DP_SEC_CNTL4_BASE_IDX 2
#define mmDP5_DP_SEC_CNTL5 0x2656
#define mmDP5_DP_SEC_CNTL5_BASE_IDX 2
#define mmDP5_DP_SEC_CNTL6 0x2657
#define mmDP5_DP_SEC_CNTL6_BASE_IDX 2
#define mmDP5_DP_SEC_CNTL7 0x2658
#define mmDP5_DP_SEC_CNTL7_BASE_IDX 2
#define mmDP5_DP_DB_CNTL 0x2659
#define mmDP5_DP_DB_CNTL_BASE_IDX 2
#define mmDP5_DP_MSA_VBID_MISC 0x265a
#define mmDP5_DP_MSA_VBID_MISC_BASE_IDX 2
// addressBlock: dce_dc_dio_dig6_dispdec
// base address: 0x1800
#define mmDIG6_DIG_FE_CNTL 0x2668
#define mmDIG6_DIG_FE_CNTL_BASE_IDX 2
#define mmDIG6_DIG_OUTPUT_CRC_CNTL 0x2669
#define mmDIG6_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2
#define mmDIG6_DIG_OUTPUT_CRC_RESULT 0x266a
#define mmDIG6_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2
#define mmDIG6_DIG_CLOCK_PATTERN 0x266b
#define mmDIG6_DIG_CLOCK_PATTERN_BASE_IDX 2
#define mmDIG6_DIG_TEST_PATTERN 0x266c
#define mmDIG6_DIG_TEST_PATTERN_BASE_IDX 2
#define mmDIG6_DIG_RANDOM_PATTERN_SEED 0x266d
#define mmDIG6_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2
#define mmDIG6_DIG_FIFO_STATUS 0x266e
#define mmDIG6_DIG_FIFO_STATUS_BASE_IDX 2
#define mmDIG6_HDMI_CONTROL 0x2671
#define mmDIG6_HDMI_CONTROL_BASE_IDX 2
#define mmDIG6_HDMI_STATUS 0x2672
#define mmDIG6_HDMI_STATUS_BASE_IDX 2
#define mmDIG6_HDMI_AUDIO_PACKET_CONTROL 0x2673
#define mmDIG6_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2
#define mmDIG6_HDMI_ACR_PACKET_CONTROL 0x2674
#define mmDIG6_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2
#define mmDIG6_HDMI_VBI_PACKET_CONTROL 0x2675
#define mmDIG6_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2
#define mmDIG6_HDMI_INFOFRAME_CONTROL0 0x2676
#define mmDIG6_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2
#define mmDIG6_HDMI_INFOFRAME_CONTROL1 0x2677
#define mmDIG6_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2
#define mmDIG6_HDMI_GENERIC_PACKET_CONTROL0 0x2678
#define mmDIG6_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2
#define mmDIG6_AFMT_INTERRUPT_STATUS 0x2679
#define mmDIG6_AFMT_INTERRUPT_STATUS_BASE_IDX 2
#define mmDIG6_HDMI_GC 0x267b
#define mmDIG6_HDMI_GC_BASE_IDX 2
#define mmDIG6_AFMT_AUDIO_PACKET_CONTROL2 0x267c
#define mmDIG6_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2
#define mmDIG6_AFMT_ISRC1_0 0x267d
#define mmDIG6_AFMT_ISRC1_0_BASE_IDX 2
#define mmDIG6_AFMT_ISRC1_1 0x267e
#define mmDIG6_AFMT_ISRC1_1_BASE_IDX 2
#define mmDIG6_AFMT_ISRC1_2 0x267f
#define mmDIG6_AFMT_ISRC1_2_BASE_IDX 2
#define mmDIG6_AFMT_ISRC1_3 0x2680
#define mmDIG6_AFMT_ISRC1_3_BASE_IDX 2
#define mmDIG6_AFMT_ISRC1_4 0x2681
#define mmDIG6_AFMT_ISRC1_4_BASE_IDX 2
#define mmDIG6_AFMT_ISRC2_0 0x2682
#define mmDIG6_AFMT_ISRC2_0_BASE_IDX 2
#define mmDIG6_AFMT_ISRC2_1 0x2683
#define mmDIG6_AFMT_ISRC2_1_BASE_IDX 2
#define mmDIG6_AFMT_ISRC2_2 0x2684
#define mmDIG6_AFMT_ISRC2_2_BASE_IDX 2
#define mmDIG6_AFMT_ISRC2_3 0x2685
#define mmDIG6_AFMT_ISRC2_3_BASE_IDX 2
#define mmDIG6_HDMI_GENERIC_PACKET_CONTROL2 0x2686
#define mmDIG6_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2
#define mmDIG6_HDMI_GENERIC_PACKET_CONTROL3 0x2687
#define mmDIG6_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2
#define mmDIG6_HDMI_DB_CONTROL 0x2688
#define mmDIG6_HDMI_DB_CONTROL_BASE_IDX 2
#define mmDIG6_AFMT_MPEG_INFO0 0x268a
#define mmDIG6_AFMT_MPEG_INFO0_BASE_IDX 2
#define mmDIG6_AFMT_MPEG_INFO1 0x268b
#define mmDIG6_AFMT_MPEG_INFO1_BASE_IDX 2
#define mmDIG6_AFMT_GENERIC_HDR 0x268c
#define mmDIG6_AFMT_GENERIC_HDR_BASE_IDX 2
#define mmDIG6_AFMT_GENERIC_0 0x268d
#define mmDIG6_AFMT_GENERIC_0_BASE_IDX 2
#define mmDIG6_AFMT_GENERIC_1 0x268e
#define mmDIG6_AFMT_GENERIC_1_BASE_IDX 2
#define mmDIG6_AFMT_GENERIC_2 0x268f
#define mmDIG6_AFMT_GENERIC_2_BASE_IDX 2
#define mmDIG6_AFMT_GENERIC_3 0x2690
#define mmDIG6_AFMT_GENERIC_3_BASE_IDX 2
#define mmDIG6_AFMT_GENERIC_4 0x2691
#define mmDIG6_AFMT_GENERIC_4_BASE_IDX 2
#define mmDIG6_AFMT_GENERIC_5 0x2692
#define mmDIG6_AFMT_GENERIC_5_BASE_IDX 2
#define mmDIG6_AFMT_GENERIC_6 0x2693
#define mmDIG6_AFMT_GENERIC_6_BASE_IDX 2
#define mmDIG6_AFMT_GENERIC_7 0x2694
#define mmDIG6_AFMT_GENERIC_7_BASE_IDX 2
#define mmDIG6_HDMI_GENERIC_PACKET_CONTROL1 0x2695
#define mmDIG6_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2
#define mmDIG6_HDMI_ACR_32_0 0x2696
#define mmDIG6_HDMI_ACR_32_0_BASE_IDX 2
#define mmDIG6_HDMI_ACR_32_1 0x2697
#define mmDIG6_HDMI_ACR_32_1_BASE_IDX 2
#define mmDIG6_HDMI_ACR_44_0 0x2698
#define mmDIG6_HDMI_ACR_44_0_BASE_IDX 2
#define mmDIG6_HDMI_ACR_44_1 0x2699
#define mmDIG6_HDMI_ACR_44_1_BASE_IDX 2
#define mmDIG6_HDMI_ACR_48_0 0x269a
#define mmDIG6_HDMI_ACR_48_0_BASE_IDX 2
#define mmDIG6_HDMI_ACR_48_1 0x269b
#define mmDIG6_HDMI_ACR_48_1_BASE_IDX 2
#define mmDIG6_HDMI_ACR_STATUS_0 0x269c
#define mmDIG6_HDMI_ACR_STATUS_0_BASE_IDX 2
#define mmDIG6_HDMI_ACR_STATUS_1 0x269d
#define mmDIG6_HDMI_ACR_STATUS_1_BASE_IDX 2
#define mmDIG6_AFMT_AUDIO_INFO0 0x269e
#define mmDIG6_AFMT_AUDIO_INFO0_BASE_IDX 2
#define mmDIG6_AFMT_AUDIO_INFO1 0x269f
#define mmDIG6_AFMT_AUDIO_INFO1_BASE_IDX 2
#define mmDIG6_AFMT_60958_0 0x26a0
#define mmDIG6_AFMT_60958_0_BASE_IDX 2
#define mmDIG6_AFMT_60958_1 0x26a1
#define mmDIG6_AFMT_60958_1_BASE_IDX 2
#define mmDIG6_AFMT_AUDIO_CRC_CONTROL 0x26a2
#define mmDIG6_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2
#define mmDIG6_AFMT_RAMP_CONTROL0 0x26a3
#define mmDIG6_AFMT_RAMP_CONTROL0_BASE_IDX 2
#define mmDIG6_AFMT_RAMP_CONTROL1 0x26a4
#define mmDIG6_AFMT_RAMP_CONTROL1_BASE_IDX 2
#define mmDIG6_AFMT_RAMP_CONTROL2 0x26a5
#define mmDIG6_AFMT_RAMP_CONTROL2_BASE_IDX 2
#define mmDIG6_AFMT_RAMP_CONTROL3 0x26a6
#define mmDIG6_AFMT_RAMP_CONTROL3_BASE_IDX 2
#define mmDIG6_AFMT_60958_2 0x26a7
#define mmDIG6_AFMT_60958_2_BASE_IDX 2
#define mmDIG6_AFMT_AUDIO_CRC_RESULT 0x26a8
#define mmDIG6_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2
#define mmDIG6_AFMT_STATUS 0x26a9
#define mmDIG6_AFMT_STATUS_BASE_IDX 2
#define mmDIG6_AFMT_AUDIO_PACKET_CONTROL 0x26aa
#define mmDIG6_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2
#define mmDIG6_AFMT_VBI_PACKET_CONTROL 0x26ab
#define mmDIG6_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2
#define mmDIG6_AFMT_INFOFRAME_CONTROL0 0x26ac
#define mmDIG6_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2
#define mmDIG6_AFMT_AUDIO_SRC_CONTROL 0x26ad
#define mmDIG6_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2
#define mmDIG6_DIG_BE_CNTL 0x26af
#define mmDIG6_DIG_BE_CNTL_BASE_IDX 2
#define mmDIG6_DIG_BE_EN_CNTL 0x26b0
#define mmDIG6_DIG_BE_EN_CNTL_BASE_IDX 2
#define mmDIG6_TMDS_CNTL 0x26d3
#define mmDIG6_TMDS_CNTL_BASE_IDX 2
#define mmDIG6_TMDS_CONTROL_CHAR 0x26d4
#define mmDIG6_TMDS_CONTROL_CHAR_BASE_IDX 2
#define mmDIG6_TMDS_CONTROL0_FEEDBACK 0x26d5
#define mmDIG6_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2
#define mmDIG6_TMDS_STEREOSYNC_CTL_SEL 0x26d6
#define mmDIG6_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2
#define mmDIG6_TMDS_SYNC_CHAR_PATTERN_0_1 0x26d7
#define mmDIG6_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2
#define mmDIG6_TMDS_SYNC_CHAR_PATTERN_2_3 0x26d8
#define mmDIG6_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2
#define mmDIG6_TMDS_CTL_BITS 0x26da
#define mmDIG6_TMDS_CTL_BITS_BASE_IDX 2
#define mmDIG6_TMDS_DCBALANCER_CONTROL 0x26db
#define mmDIG6_TMDS_DCBALANCER_CONTROL_BASE_IDX 2
#define mmDIG6_TMDS_CTL0_1_GEN_CNTL 0x26dd
#define mmDIG6_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2
#define mmDIG6_TMDS_CTL2_3_GEN_CNTL 0x26de
#define mmDIG6_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2
#define mmDIG6_DIG_VERSION 0x26e0
#define mmDIG6_DIG_VERSION_BASE_IDX 2
#define mmDIG6_DIG_LANE_ENABLE 0x26e1
#define mmDIG6_DIG_LANE_ENABLE_BASE_IDX 2
#define mmDIG6_AFMT_CNTL 0x26e6
#define mmDIG6_AFMT_CNTL_BASE_IDX 2
#define mmDIG6_AFMT_VBI_PACKET_CONTROL1 0x26e7
#define mmDIG6_AFMT_VBI_PACKET_CONTROL1_BASE_IDX 2
// addressBlock: dce_dc_dio_dp6_dispdec
// base address: 0x1800
#define mmDP6_DP_LINK_CNTL 0x2708
#define mmDP6_DP_LINK_CNTL_BASE_IDX 2
#define mmDP6_DP_PIXEL_FORMAT 0x2709
#define mmDP6_DP_PIXEL_FORMAT_BASE_IDX 2
#define mmDP6_DP_MSA_COLORIMETRY 0x270a
#define mmDP6_DP_MSA_COLORIMETRY_BASE_IDX 2
#define mmDP6_DP_CONFIG 0x270b
#define mmDP6_DP_CONFIG_BASE_IDX 2
#define mmDP6_DP_VID_STREAM_CNTL 0x270c
#define mmDP6_DP_VID_STREAM_CNTL_BASE_IDX 2
#define mmDP6_DP_STEER_FIFO 0x270d
#define mmDP6_DP_STEER_FIFO_BASE_IDX 2
#define mmDP6_DP_MSA_MISC 0x270e
#define mmDP6_DP_MSA_MISC_BASE_IDX 2
#define mmDP6_DP_VID_TIMING 0x2710
#define mmDP6_DP_VID_TIMING_BASE_IDX 2
#define mmDP6_DP_VID_N 0x2711
#define mmDP6_DP_VID_N_BASE_IDX 2
#define mmDP6_DP_VID_M 0x2712
#define mmDP6_DP_VID_M_BASE_IDX 2
#define mmDP6_DP_LINK_FRAMING_CNTL 0x2713
#define mmDP6_DP_LINK_FRAMING_CNTL_BASE_IDX 2
#define mmDP6_DP_HBR2_EYE_PATTERN 0x2714
#define mmDP6_DP_HBR2_EYE_PATTERN_BASE_IDX 2
#define mmDP6_DP_VID_MSA_VBID 0x2715
#define mmDP6_DP_VID_MSA_VBID_BASE_IDX 2
#define mmDP6_DP_VID_INTERRUPT_CNTL 0x2716
#define mmDP6_DP_VID_INTERRUPT_CNTL_BASE_IDX 2
#define mmDP6_DP_DPHY_CNTL 0x2717
#define mmDP6_DP_DPHY_CNTL_BASE_IDX 2
#define mmDP6_DP_DPHY_TRAINING_PATTERN_SEL 0x2718
#define mmDP6_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2
#define mmDP6_DP_DPHY_SYM0 0x2719
#define mmDP6_DP_DPHY_SYM0_BASE_IDX 2
#define mmDP6_DP_DPHY_SYM1 0x271a
#define mmDP6_DP_DPHY_SYM1_BASE_IDX 2
#define mmDP6_DP_DPHY_SYM2 0x271b
#define mmDP6_DP_DPHY_SYM2_BASE_IDX 2
#define mmDP6_DP_DPHY_8B10B_CNTL 0x271c
#define mmDP6_DP_DPHY_8B10B_CNTL_BASE_IDX 2
#define mmDP6_DP_DPHY_PRBS_CNTL 0x271d
#define mmDP6_DP_DPHY_PRBS_CNTL_BASE_IDX 2
#define mmDP6_DP_DPHY_SCRAM_CNTL 0x271e
#define mmDP6_DP_DPHY_SCRAM_CNTL_BASE_IDX 2
#define mmDP6_DP_DPHY_CRC_EN 0x271f
#define mmDP6_DP_DPHY_CRC_EN_BASE_IDX 2
#define mmDP6_DP_DPHY_CRC_CNTL 0x2720
#define mmDP6_DP_DPHY_CRC_CNTL_BASE_IDX 2
#define mmDP6_DP_DPHY_CRC_RESULT 0x2721
#define mmDP6_DP_DPHY_CRC_RESULT_BASE_IDX 2
#define mmDP6_DP_DPHY_CRC_MST_CNTL 0x2722
#define mmDP6_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2
#define mmDP6_DP_DPHY_CRC_MST_STATUS 0x2723
#define mmDP6_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2
#define mmDP6_DP_DPHY_FAST_TRAINING 0x2724
#define mmDP6_DP_DPHY_FAST_TRAINING_BASE_IDX 2
#define mmDP6_DP_DPHY_FAST_TRAINING_STATUS 0x2725
#define mmDP6_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2
#define mmDP6_DP_SEC_CNTL 0x272b
#define mmDP6_DP_SEC_CNTL_BASE_IDX 2
#define mmDP6_DP_SEC_CNTL1 0x272c
#define mmDP6_DP_SEC_CNTL1_BASE_IDX 2
#define mmDP6_DP_SEC_FRAMING1 0x272d
#define mmDP6_DP_SEC_FRAMING1_BASE_IDX 2
#define mmDP6_DP_SEC_FRAMING2 0x272e
#define mmDP6_DP_SEC_FRAMING2_BASE_IDX 2
#define mmDP6_DP_SEC_FRAMING3 0x272f
#define mmDP6_DP_SEC_FRAMING3_BASE_IDX 2
#define mmDP6_DP_SEC_FRAMING4 0x2730
#define mmDP6_DP_SEC_FRAMING4_BASE_IDX 2
#define mmDP6_DP_SEC_AUD_N 0x2731
#define mmDP6_DP_SEC_AUD_N_BASE_IDX 2
#define mmDP6_DP_SEC_AUD_N_READBACK 0x2732
#define mmDP6_DP_SEC_AUD_N_READBACK_BASE_IDX 2
#define mmDP6_DP_SEC_AUD_M 0x2733
#define mmDP6_DP_SEC_AUD_M_BASE_IDX 2
#define mmDP6_DP_SEC_AUD_M_READBACK 0x2734
#define mmDP6_DP_SEC_AUD_M_READBACK_BASE_IDX 2
#define mmDP6_DP_SEC_TIMESTAMP 0x2735
#define mmDP6_DP_SEC_TIMESTAMP_BASE_IDX 2
#define mmDP6_DP_SEC_PACKET_CNTL 0x2736
#define mmDP6_DP_SEC_PACKET_CNTL_BASE_IDX 2
#define mmDP6_DP_MSE_RATE_CNTL 0x2737
#define mmDP6_DP_MSE_RATE_CNTL_BASE_IDX 2
#define mmDP6_DP_MSE_RATE_UPDATE 0x2739
#define mmDP6_DP_MSE_RATE_UPDATE_BASE_IDX 2
#define mmDP6_DP_MSE_SAT0 0x273a
#define mmDP6_DP_MSE_SAT0_BASE_IDX 2
#define mmDP6_DP_MSE_SAT1 0x273b
#define mmDP6_DP_MSE_SAT1_BASE_IDX 2
#define mmDP6_DP_MSE_SAT2 0x273c
#define mmDP6_DP_MSE_SAT2_BASE_IDX 2
#define mmDP6_DP_MSE_SAT_UPDATE 0x273d
#define mmDP6_DP_MSE_SAT_UPDATE_BASE_IDX 2
#define mmDP6_DP_MSE_LINK_TIMING 0x273e
#define mmDP6_DP_MSE_LINK_TIMING_BASE_IDX 2
#define mmDP6_DP_MSE_MISC_CNTL 0x273f
#define mmDP6_DP_MSE_MISC_CNTL_BASE_IDX 2
#define mmDP6_DP_DPHY_BS_SR_SWAP_CNTL 0x2744
#define mmDP6_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2
#define mmDP6_DP_DPHY_HBR2_PATTERN_CONTROL 0x2745
#define mmDP6_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2
#define mmDP6_DP_MSE_SAT0_STATUS 0x2747
#define mmDP6_DP_MSE_SAT0_STATUS_BASE_IDX 2
#define mmDP6_DP_MSE_SAT1_STATUS 0x2748
#define mmDP6_DP_MSE_SAT1_STATUS_BASE_IDX 2
#define mmDP6_DP_MSE_SAT2_STATUS 0x2749
#define mmDP6_DP_MSE_SAT2_STATUS_BASE_IDX 2
#define mmDP6_DP_MSA_TIMING_PARAM1 0x274c
#define mmDP6_DP_MSA_TIMING_PARAM1_BASE_IDX 2
#define mmDP6_DP_MSA_TIMING_PARAM2 0x274d
#define mmDP6_DP_MSA_TIMING_PARAM2_BASE_IDX 2
#define mmDP6_DP_MSA_TIMING_PARAM3 0x274e
#define mmDP6_DP_MSA_TIMING_PARAM3_BASE_IDX 2
#define mmDP6_DP_MSA_TIMING_PARAM4 0x274f
#define mmDP6_DP_MSA_TIMING_PARAM4_BASE_IDX 2
#define mmDP6_DP_MSO_CNTL 0x2750
#define mmDP6_DP_MSO_CNTL_BASE_IDX 2
#define mmDP6_DP_MSO_CNTL1 0x2751
#define mmDP6_DP_MSO_CNTL1_BASE_IDX 2
#define mmDP6_DP_DSC_CNTL 0x2752
#define mmDP6_DP_DSC_CNTL_BASE_IDX 2
#define mmDP6_DP_SEC_CNTL2 0x2753
#define mmDP6_DP_SEC_CNTL2_BASE_IDX 2
#define mmDP6_DP_SEC_CNTL3 0x2754
#define mmDP6_DP_SEC_CNTL3_BASE_IDX 2
#define mmDP6_DP_SEC_CNTL4 0x2755
#define mmDP6_DP_SEC_CNTL4_BASE_IDX 2
#define mmDP6_DP_SEC_CNTL5 0x2756
#define mmDP6_DP_SEC_CNTL5_BASE_IDX 2
#define mmDP6_DP_SEC_CNTL6 0x2757
#define mmDP6_DP_SEC_CNTL6_BASE_IDX 2
#define mmDP6_DP_SEC_CNTL7 0x2758
#define mmDP6_DP_SEC_CNTL7_BASE_IDX 2
#define mmDP6_DP_DB_CNTL 0x2759
#define mmDP6_DP_DB_CNTL_BASE_IDX 2
#define mmDP6_DP_MSA_VBID_MISC 0x275a
#define mmDP6_DP_MSA_VBID_MISC_BASE_IDX 2
// addressBlock: dce_dc_dcio_dcio_dispdec
// base address: 0x0
#define mmDC_GENERICA 0x2868
#define mmDC_GENERICA_BASE_IDX 2
#define mmDC_GENERICB 0x2869
#define mmDC_GENERICB_BASE_IDX 2
#define mmDC_REF_CLK_CNTL 0x286b
#define mmDC_REF_CLK_CNTL_BASE_IDX 2
#define mmDC_GPIO_DEBUG 0x286c
#define mmDC_GPIO_DEBUG_BASE_IDX 2
#define mmUNIPHYA_LINK_CNTL 0x286d
#define mmUNIPHYA_LINK_CNTL_BASE_IDX 2
#define mmUNIPHYA_CHANNEL_XBAR_CNTL 0x286e
#define mmUNIPHYA_CHANNEL_XBAR_CNTL_BASE_IDX 2
#define mmUNIPHYB_LINK_CNTL 0x286f
#define mmUNIPHYB_LINK_CNTL_BASE_IDX 2
#define mmUNIPHYB_CHANNEL_XBAR_CNTL 0x2870
#define mmUNIPHYB_CHANNEL_XBAR_CNTL_BASE_IDX 2
#define mmUNIPHYC_LINK_CNTL 0x2871
#define mmUNIPHYC_LINK_CNTL_BASE_IDX 2
#define mmUNIPHYC_CHANNEL_XBAR_CNTL 0x2872
#define mmUNIPHYC_CHANNEL_XBAR_CNTL_BASE_IDX 2
#define mmUNIPHYD_LINK_CNTL 0x2873
#define mmUNIPHYD_LINK_CNTL_BASE_IDX 2
#define mmUNIPHYD_CHANNEL_XBAR_CNTL 0x2874
#define mmUNIPHYD_CHANNEL_XBAR_CNTL_BASE_IDX 2
#define mmUNIPHYE_LINK_CNTL 0x2875
#define mmUNIPHYE_LINK_CNTL_BASE_IDX 2
#define mmUNIPHYE_CHANNEL_XBAR_CNTL 0x2876
#define mmUNIPHYE_CHANNEL_XBAR_CNTL_BASE_IDX 2
#define mmUNIPHYF_LINK_CNTL 0x2877
#define mmUNIPHYF_LINK_CNTL_BASE_IDX 2
#define mmUNIPHYF_CHANNEL_XBAR_CNTL 0x2878
#define mmUNIPHYF_CHANNEL_XBAR_CNTL_BASE_IDX 2
#define mmUNIPHYG_LINK_CNTL 0x2879
#define mmUNIPHYG_LINK_CNTL_BASE_IDX 2
#define mmUNIPHYG_CHANNEL_XBAR_CNTL 0x287a
#define mmUNIPHYG_CHANNEL_XBAR_CNTL_BASE_IDX 2
#define mmDCIO_WRCMD_DELAY 0x287e
#define mmDCIO_WRCMD_DELAY_BASE_IDX 2
#define mmDC_PINSTRAPS 0x2880
#define mmDC_PINSTRAPS_BASE_IDX 2
#define mmDC_DVODATA_CONFIG 0x2882
#define mmDC_DVODATA_CONFIG_BASE_IDX 2
#define mmLVTMA_PWRSEQ_CNTL 0x2883
#define mmLVTMA_PWRSEQ_CNTL_BASE_IDX 2
#define mmLVTMA_PWRSEQ_STATE 0x2884
#define mmLVTMA_PWRSEQ_STATE_BASE_IDX 2
#define mmLVTMA_PWRSEQ_REF_DIV 0x2885
#define mmLVTMA_PWRSEQ_REF_DIV_BASE_IDX 2
#define mmLVTMA_PWRSEQ_DELAY1 0x2886
#define mmLVTMA_PWRSEQ_DELAY1_BASE_IDX 2
#define mmLVTMA_PWRSEQ_DELAY2 0x2887
#define mmLVTMA_PWRSEQ_DELAY2_BASE_IDX 2
#define mmBL_PWM_CNTL 0x2888
#define mmBL_PWM_CNTL_BASE_IDX 2
#define mmBL_PWM_CNTL2 0x2889
#define mmBL_PWM_CNTL2_BASE_IDX 2
#define mmBL_PWM_PERIOD_CNTL 0x288a
#define mmBL_PWM_PERIOD_CNTL_BASE_IDX 2
#define mmBL_PWM_GRP1_REG_LOCK 0x288b
#define mmBL_PWM_GRP1_REG_LOCK_BASE_IDX 2
#define mmDCIO_GSL_GENLK_PAD_CNTL 0x288c
#define mmDCIO_GSL_GENLK_PAD_CNTL_BASE_IDX 2
#define mmDCIO_GSL_SWAPLOCK_PAD_CNTL 0x288d
#define mmDCIO_GSL_SWAPLOCK_PAD_CNTL_BASE_IDX 2
#define mmDCIO_CLOCK_CNTL 0x2895
#define mmDCIO_CLOCK_CNTL_BASE_IDX 2
#define mmDIO_OTG_EXT_VSYNC_CNTL 0x2898
#define mmDIO_OTG_EXT_VSYNC_CNTL_BASE_IDX 2
#define mmDCIO_SOFT_RESET 0x289e
#define mmDCIO_SOFT_RESET_BASE_IDX 2
#define mmDCIO_DPHY_SEL 0x289f
#define mmDCIO_DPHY_SEL_BASE_IDX 2
#define mmUNIPHY_IMPCAL_LINKA 0x28a0
#define mmUNIPHY_IMPCAL_LINKA_BASE_IDX 2
#define mmUNIPHY_IMPCAL_LINKB 0x28a1
#define mmUNIPHY_IMPCAL_LINKB_BASE_IDX 2
#define mmUNIPHY_IMPCAL_PERIOD 0x28a2
#define mmUNIPHY_IMPCAL_PERIOD_BASE_IDX 2
#define mmAUXP_IMPCAL 0x28a3
#define mmAUXP_IMPCAL_BASE_IDX 2
#define mmAUXN_IMPCAL 0x28a4
#define mmAUXN_IMPCAL_BASE_IDX 2
#define mmDCIO_IMPCAL_CNTL 0x28a5
#define mmDCIO_IMPCAL_CNTL_BASE_IDX 2
#define mmUNIPHY_IMPCAL_PSW_AB 0x28a6
#define mmUNIPHY_IMPCAL_PSW_AB_BASE_IDX 2
#define mmUNIPHY_IMPCAL_LINKC 0x28a7
#define mmUNIPHY_IMPCAL_LINKC_BASE_IDX 2
#define mmUNIPHY_IMPCAL_LINKD 0x28a8
#define mmUNIPHY_IMPCAL_LINKD_BASE_IDX 2
#define mmDCIO_IMPCAL_CNTL_CD 0x28a9
#define mmDCIO_IMPCAL_CNTL_CD_BASE_IDX 2
#define mmUNIPHY_IMPCAL_PSW_CD 0x28aa
#define mmUNIPHY_IMPCAL_PSW_CD_BASE_IDX 2
#define mmUNIPHY_IMPCAL_LINKE 0x28ab
#define mmUNIPHY_IMPCAL_LINKE_BASE_IDX 2
#define mmUNIPHY_IMPCAL_LINKF 0x28ac
#define mmUNIPHY_IMPCAL_LINKF_BASE_IDX 2
#define mmDCIO_IMPCAL_CNTL_EF 0x28ad
#define mmDCIO_IMPCAL_CNTL_EF_BASE_IDX 2
#define mmUNIPHY_IMPCAL_PSW_EF 0x28ae
#define mmUNIPHY_IMPCAL_PSW_EF_BASE_IDX 2
#define mmDCIO_DPCS_TX_INTERRUPT 0x28b3
#define mmDCIO_DPCS_TX_INTERRUPT_BASE_IDX 2
#define mmDCIO_DPCS_RX_INTERRUPT 0x28b4
#define mmDCIO_DPCS_RX_INTERRUPT_BASE_IDX 2
#define mmDCIO_SEMAPHORE0 0x28b5
#define mmDCIO_SEMAPHORE0_BASE_IDX 2
#define mmDCIO_SEMAPHORE1 0x28b6
#define mmDCIO_SEMAPHORE1_BASE_IDX 2
#define mmDCIO_SEMAPHORE2 0x28b7
#define mmDCIO_SEMAPHORE2_BASE_IDX 2
#define mmDCIO_SEMAPHORE3 0x28b8
#define mmDCIO_SEMAPHORE3_BASE_IDX 2
#define mmDCIO_SEMAPHORE4 0x28b9
#define mmDCIO_SEMAPHORE4_BASE_IDX 2
#define mmDCIO_SEMAPHORE5 0x28ba
#define mmDCIO_SEMAPHORE5_BASE_IDX 2
#define mmDCIO_SEMAPHORE6 0x28bb
#define mmDCIO_SEMAPHORE6_BASE_IDX 2
#define mmDCIO_SEMAPHORE7 0x28bc
#define mmDCIO_SEMAPHORE7_BASE_IDX 2
#define mmDCIO_USBC_FLIP_EN_SEL 0x28bd
#define mmDCIO_USBC_FLIP_EN_SEL_BASE_IDX 2
// addressBlock: dce_dc_dcio_dcio_chip_dispdec
// base address: 0x0
#define mmDC_GPIO_GENERIC_MASK 0x28c8
#define mmDC_GPIO_GENERIC_MASK_BASE_IDX 2
#define mmDC_GPIO_GENERIC_A 0x28c9
#define mmDC_GPIO_GENERIC_A_BASE_IDX 2
#define mmDC_GPIO_GENERIC_EN 0x28ca
#define mmDC_GPIO_GENERIC_EN_BASE_IDX 2
#define mmDC_GPIO_GENERIC_Y 0x28cb
#define mmDC_GPIO_GENERIC_Y_BASE_IDX 2
#define mmDC_GPIO_DVODATA_MASK 0x28cc
#define mmDC_GPIO_DVODATA_MASK_BASE_IDX 2
#define mmDC_GPIO_DVODATA_A 0x28cd
#define mmDC_GPIO_DVODATA_A_BASE_IDX 2
#define mmDC_GPIO_DVODATA_EN 0x28ce
#define mmDC_GPIO_DVODATA_EN_BASE_IDX 2
#define mmDC_GPIO_DVODATA_Y 0x28cf
#define mmDC_GPIO_DVODATA_Y_BASE_IDX 2
#define mmDC_GPIO_DDC1_MASK 0x28d0
#define mmDC_GPIO_DDC1_MASK_BASE_IDX 2
#define mmDC_GPIO_DDC1_A 0x28d1
#define mmDC_GPIO_DDC1_A_BASE_IDX 2
#define mmDC_GPIO_DDC1_EN 0x28d2
#define mmDC_GPIO_DDC1_EN_BASE_IDX 2
#define mmDC_GPIO_DDC1_Y 0x28d3
#define mmDC_GPIO_DDC1_Y_BASE_IDX 2
#define mmDC_GPIO_DDC2_MASK 0x28d4
#define mmDC_GPIO_DDC2_MASK_BASE_IDX 2
#define mmDC_GPIO_DDC2_A 0x28d5
#define mmDC_GPIO_DDC2_A_BASE_IDX 2
#define mmDC_GPIO_DDC2_EN 0x28d6
#define mmDC_GPIO_DDC2_EN_BASE_IDX 2
#define mmDC_GPIO_DDC2_Y 0x28d7
#define mmDC_GPIO_DDC2_Y_BASE_IDX 2
#define mmDC_GPIO_DDC3_MASK 0x28d8
#define mmDC_GPIO_DDC3_MASK_BASE_IDX 2
#define mmDC_GPIO_DDC3_A 0x28d9
#define mmDC_GPIO_DDC3_A_BASE_IDX 2
#define mmDC_GPIO_DDC3_EN 0x28da
#define mmDC_GPIO_DDC3_EN_BASE_IDX 2
#define mmDC_GPIO_DDC3_Y 0x28db
#define mmDC_GPIO_DDC3_Y_BASE_IDX 2
#define mmDC_GPIO_DDC4_MASK 0x28dc
#define mmDC_GPIO_DDC4_MASK_BASE_IDX 2
#define mmDC_GPIO_DDC4_A 0x28dd
#define mmDC_GPIO_DDC4_A_BASE_IDX 2
#define mmDC_GPIO_DDC4_EN 0x28de
#define mmDC_GPIO_DDC4_EN_BASE_IDX 2
#define mmDC_GPIO_DDC4_Y 0x28df
#define mmDC_GPIO_DDC4_Y_BASE_IDX 2
#define mmDC_GPIO_DDC5_MASK 0x28e0
#define mmDC_GPIO_DDC5_MASK_BASE_IDX 2
#define mmDC_GPIO_DDC5_A 0x28e1
#define mmDC_GPIO_DDC5_A_BASE_IDX 2
#define mmDC_GPIO_DDC5_EN 0x28e2
#define mmDC_GPIO_DDC5_EN_BASE_IDX 2
#define mmDC_GPIO_DDC5_Y 0x28e3
#define mmDC_GPIO_DDC5_Y_BASE_IDX 2
#define mmDC_GPIO_DDC6_MASK 0x28e4
#define mmDC_GPIO_DDC6_MASK_BASE_IDX 2
#define mmDC_GPIO_DDC6_A 0x28e5
#define mmDC_GPIO_DDC6_A_BASE_IDX 2
#define mmDC_GPIO_DDC6_EN 0x28e6
#define mmDC_GPIO_DDC6_EN_BASE_IDX 2
#define mmDC_GPIO_DDC6_Y 0x28e7
#define mmDC_GPIO_DDC6_Y_BASE_IDX 2
#define mmDC_GPIO_DDCVGA_MASK 0x28e8
#define mmDC_GPIO_DDCVGA_MASK_BASE_IDX 2
#define mmDC_GPIO_DDCVGA_A 0x28e9
#define mmDC_GPIO_DDCVGA_A_BASE_IDX 2
#define mmDC_GPIO_DDCVGA_EN 0x28ea
#define mmDC_GPIO_DDCVGA_EN_BASE_IDX 2
#define mmDC_GPIO_DDCVGA_Y 0x28eb
#define mmDC_GPIO_DDCVGA_Y_BASE_IDX 2
#define mmDC_GPIO_SYNCA_MASK 0x28ec
#define mmDC_GPIO_SYNCA_MASK_BASE_IDX 2
#define mmDC_GPIO_SYNCA_A 0x28ed
#define mmDC_GPIO_SYNCA_A_BASE_IDX 2
#define mmDC_GPIO_SYNCA_EN 0x28ee
#define mmDC_GPIO_SYNCA_EN_BASE_IDX 2
#define mmDC_GPIO_SYNCA_Y 0x28ef
#define mmDC_GPIO_SYNCA_Y_BASE_IDX 2
#define mmDC_GPIO_GENLK_MASK 0x28f0
#define mmDC_GPIO_GENLK_MASK_BASE_IDX 2
#define mmDC_GPIO_GENLK_A 0x28f1
#define mmDC_GPIO_GENLK_A_BASE_IDX 2
#define mmDC_GPIO_GENLK_EN 0x28f2
#define mmDC_GPIO_GENLK_EN_BASE_IDX 2
#define mmDC_GPIO_GENLK_Y 0x28f3
#define mmDC_GPIO_GENLK_Y_BASE_IDX 2
#define mmDC_GPIO_HPD_MASK 0x28f4
#define mmDC_GPIO_HPD_MASK_BASE_IDX 2
#define mmDC_GPIO_HPD_A 0x28f5
#define mmDC_GPIO_HPD_A_BASE_IDX 2
#define mmDC_GPIO_HPD_EN 0x28f6
#define mmDC_GPIO_HPD_EN_BASE_IDX 2
#define mmDC_GPIO_HPD_Y 0x28f7
#define mmDC_GPIO_HPD_Y_BASE_IDX 2
#define mmDC_GPIO_PWRSEQ_MASK 0x28f8
#define mmDC_GPIO_PWRSEQ_MASK_BASE_IDX 2
#define mmDC_GPIO_PWRSEQ_A 0x28f9
#define mmDC_GPIO_PWRSEQ_A_BASE_IDX 2
#define mmDC_GPIO_PWRSEQ_EN 0x28fa
#define mmDC_GPIO_PWRSEQ_EN_BASE_IDX 2
#define mmDC_GPIO_PWRSEQ_Y 0x28fb
#define mmDC_GPIO_PWRSEQ_Y_BASE_IDX 2
#define mmDC_GPIO_PAD_STRENGTH_1 0x28fc
#define mmDC_GPIO_PAD_STRENGTH_1_BASE_IDX 2
#define mmDC_GPIO_PAD_STRENGTH_2 0x28fd
#define mmDC_GPIO_PAD_STRENGTH_2_BASE_IDX 2
#define mmPHY_AUX_CNTL 0x28ff
#define mmPHY_AUX_CNTL_BASE_IDX 2
#define mmDC_GPIO_I2CPAD_MASK 0x2900
#define mmDC_GPIO_I2CPAD_MASK_BASE_IDX 2
#define mmDC_GPIO_I2CPAD_A 0x2901
#define mmDC_GPIO_I2CPAD_A_BASE_IDX 2
#define mmDC_GPIO_I2CPAD_EN 0x2902
#define mmDC_GPIO_I2CPAD_EN_BASE_IDX 2
#define mmDC_GPIO_I2CPAD_Y 0x2903
#define mmDC_GPIO_I2CPAD_Y_BASE_IDX 2
#define mmDC_GPIO_I2CPAD_STRENGTH 0x2904
#define mmDC_GPIO_I2CPAD_STRENGTH_BASE_IDX 2
#define mmDVO_STRENGTH_CONTROL 0x2905
#define mmDVO_STRENGTH_CONTROL_BASE_IDX 2
#define mmDVO_VREF_CONTROL 0x2906
#define mmDVO_VREF_CONTROL_BASE_IDX 2
#define mmDVO_SKEW_ADJUST 0x2907
#define mmDVO_SKEW_ADJUST_BASE_IDX 2
#define mmDC_GPIO_I2S_SPDIF_MASK 0x2910
#define mmDC_GPIO_I2S_SPDIF_MASK_BASE_IDX 2
#define mmDC_GPIO_I2S_SPDIF_A 0x2911
#define mmDC_GPIO_I2S_SPDIF_A_BASE_IDX 2
#define mmDC_GPIO_I2S_SPDIF_EN 0x2912
#define mmDC_GPIO_I2S_SPDIF_EN_BASE_IDX 2
#define mmDC_GPIO_I2S_SPDIF_Y 0x2913
#define mmDC_GPIO_I2S_SPDIF_Y_BASE_IDX 2
#define mmDC_GPIO_I2S_SPDIF_STRENGTH 0x2914
#define mmDC_GPIO_I2S_SPDIF_STRENGTH_BASE_IDX 2
#define mmDC_GPIO_TX12_EN 0x2915
#define mmDC_GPIO_TX12_EN_BASE_IDX 2
#define mmDC_GPIO_AUX_CTRL_0 0x2916
#define mmDC_GPIO_AUX_CTRL_0_BASE_IDX 2
#define mmDC_GPIO_AUX_CTRL_1 0x2917
#define mmDC_GPIO_AUX_CTRL_1_BASE_IDX 2
#define mmDC_GPIO_AUX_CTRL_2 0x2918
#define mmDC_GPIO_AUX_CTRL_2_BASE_IDX 2
#define mmDC_GPIO_RXEN 0x2919
#define mmDC_GPIO_RXEN_BASE_IDX 2
#define mmDC_GPIO_PULLUPEN 0x291a
#define mmDC_GPIO_PULLUPEN_BASE_IDX 2
// addressBlock: dce_dc_dcio_dcio_dac_dispdec
// base address: 0x0
#define mmDAC_MACRO_CNTL_RESERVED0 0x2920
#define mmDAC_MACRO_CNTL_RESERVED0_BASE_IDX 2
#define mmDAC_MACRO_CNTL_RESERVED1 0x2921
#define mmDAC_MACRO_CNTL_RESERVED1_BASE_IDX 2
#define mmDAC_MACRO_CNTL_RESERVED2 0x2922
#define mmDAC_MACRO_CNTL_RESERVED2_BASE_IDX 2
#define mmDAC_MACRO_CNTL_RESERVED3 0x2923
#define mmDAC_MACRO_CNTL_RESERVED3_BASE_IDX 2
// addressBlock: dce_dc_dcio_dcio_uniphy0_dispdec
// base address: 0x0
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED0 0x2928
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED1 0x2929
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED2 0x292a
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED3 0x292b
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED4 0x292c
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED5 0x292d
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED6 0x292e
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED7 0x292f
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED8 0x2930
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED9 0x2931
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED10 0x2932
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED11 0x2933
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED12 0x2934
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED13 0x2935
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED14 0x2936
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED15 0x2937
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED16 0x2938
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED17 0x2939
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED18 0x293a
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED19 0x293b
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED20 0x293c
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED21 0x293d
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED22 0x293e
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED23 0x293f
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED24 0x2940
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED25 0x2941
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED26 0x2942
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED27 0x2943
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED28 0x2944
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED29 0x2945
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED30 0x2946
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED31 0x2947
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED32 0x2948
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED33 0x2949
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED34 0x294a
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED35 0x294b
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED36 0x294c
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED37 0x294d
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED38 0x294e
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED39 0x294f
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED40 0x2950
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED41 0x2951
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED42 0x2952
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED43 0x2953
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED44 0x2954
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED45 0x2955
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED46 0x2956
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED47 0x2957
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED48 0x2958
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED49 0x2959
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED50 0x295a
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED51 0x295b
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED52 0x295c
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED53 0x295d
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED54 0x295e
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED55 0x295f
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED56 0x2960
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED57 0x2961
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED58 0x2962
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED58_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED59 0x2963
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED59_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED60 0x2964
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED60_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED61 0x2965
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED61_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED62 0x2966
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED62_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED63 0x2967
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED63_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED64 0x2968
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED64_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED65 0x2969
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED65_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED66 0x296a
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED66_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED67 0x296b
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED67_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED68 0x296c
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED68_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED69 0x296d
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED69_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED70 0x296e
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED70_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED71 0x296f
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED71_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED72 0x2970
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED72_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED73 0x2971
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED73_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED74 0x2972
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED74_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED75 0x2973
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED75_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED76 0x2974
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED76_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED77 0x2975
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED77_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED78 0x2976
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED78_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED79 0x2977
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED79_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED80 0x2978
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED80_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED81 0x2979
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED81_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED82 0x297a
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED82_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED83 0x297b
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED83_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED84 0x297c
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED84_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED85 0x297d
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED85_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED86 0x297e
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED86_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED87 0x297f
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED87_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED88 0x2980
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED88_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED89 0x2981
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED89_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED90 0x2982
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED90_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED91 0x2983
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED91_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED92 0x2984
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED92_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED93 0x2985
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED93_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED94 0x2986
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED94_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED95 0x2987
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED95_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED96 0x2988
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED96_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED97 0x2989
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED97_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED98 0x298a
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED98_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED99 0x298b
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED99_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED100 0x298c
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED100_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED101 0x298d
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED101_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED102 0x298e
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED102_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED103 0x298f
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED103_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED104 0x2990
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED104_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED105 0x2991
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED105_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED106 0x2992
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED106_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED107 0x2993
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED107_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED108 0x2994
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED108_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED109 0x2995
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED109_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED110 0x2996
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED110_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED111 0x2997
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED111_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED112 0x2998
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED112_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED113 0x2999
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED113_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED114 0x299a
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED114_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED115 0x299b
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED115_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED116 0x299c
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED116_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED117 0x299d
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED117_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED118 0x299e
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED118_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED119 0x299f
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED119_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED120 0x29a0
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED120_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED121 0x29a1
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED121_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED122 0x29a2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED122_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED123 0x29a3
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED123_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED124 0x29a4
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED124_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED125 0x29a5
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED125_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED126 0x29a6
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED126_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED127 0x29a7
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED127_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED128 0x29a8
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED128_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED129 0x29a9
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED129_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED130 0x29aa
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED130_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED131 0x29ab
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED131_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED132 0x29ac
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED132_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED133 0x29ad
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED133_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED134 0x29ae
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED134_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED135 0x29af
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED135_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED136 0x29b0
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED136_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED137 0x29b1
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED137_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED138 0x29b2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED138_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED139 0x29b3
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED139_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED140 0x29b4
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED140_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED141 0x29b5
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED141_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED142 0x29b6
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED142_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED143 0x29b7
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED143_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED144 0x29b8
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED144_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED145 0x29b9
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED145_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED146 0x29ba
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED146_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED147 0x29bb
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED147_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED148 0x29bc
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED148_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED149 0x29bd
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED149_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED150 0x29be
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED150_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED151 0x29bf
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED151_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED152 0x29c0
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED152_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED153 0x29c1
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED153_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED154 0x29c2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED154_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED155 0x29c3
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED155_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED156 0x29c4
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED156_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED157 0x29c5
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED157_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED158 0x29c6
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED158_BASE_IDX 2
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED159 0x29c7
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED159_BASE_IDX 2
// addressBlock: dce_dc_combophy_dc_combophycmregs0_dispdec
// base address: 0x0
#define mmDC_COMBOPHYCMREGS0_COMMON_FUSE1 0x2928
#define mmDC_COMBOPHYCMREGS0_COMMON_FUSE1_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS0_COMMON_FUSE2 0x2929
#define mmDC_COMBOPHYCMREGS0_COMMON_FUSE2_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS0_COMMON_FUSE3 0x292a
#define mmDC_COMBOPHYCMREGS0_COMMON_FUSE3_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS0_COMMON_MAR_DEEMPH_NOM 0x292b
#define mmDC_COMBOPHYCMREGS0_COMMON_MAR_DEEMPH_NOM_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS0_COMMON_LANE_PWRMGMT 0x292c
#define mmDC_COMBOPHYCMREGS0_COMMON_LANE_PWRMGMT_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS0_COMMON_TXCNTRL 0x292d
#define mmDC_COMBOPHYCMREGS0_COMMON_TXCNTRL_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS0_COMMON_TMDP 0x292e
#define mmDC_COMBOPHYCMREGS0_COMMON_TMDP_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS0_COMMON_LANE_RESETS 0x292f
#define mmDC_COMBOPHYCMREGS0_COMMON_LANE_RESETS_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS0_COMMON_ZCALCODE_CTRL 0x2930
#define mmDC_COMBOPHYCMREGS0_COMMON_ZCALCODE_CTRL_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU1 0x2931
#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU1_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU2 0x2932
#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU2_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU3 0x2933
#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU3_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU4 0x2934
#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU4_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU5 0x2935
#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU5_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU6 0x2936
#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU6_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU7 0x2937
#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU7_BASE_IDX 2
// addressBlock: dce_dc_combophy_dc_combophytxregs0_dispdec
// base address: 0x0
#define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE0 0x2948
#define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE0 0x2949
#define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0 0x294a
#define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE0 0x294b
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE0 0x294c
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE0 0x294d
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE0 0x294e
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE0 0x294f
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE0 0x2950
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE0 0x2951
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE0 0x2952
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE0 0x2953
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE0 0x2954
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE0 0x2955
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE0 0x2956
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE0 0x2957
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE1 0x2958
#define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE1 0x2959
#define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1 0x295a
#define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE1 0x295b
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE1 0x295c
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE1 0x295d
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE1 0x295e
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE1 0x295f
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE1 0x2960
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE1 0x2961
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE1 0x2962
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE1 0x2963
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE1 0x2964
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE1 0x2965
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE1 0x2966
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE1 0x2967
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE2 0x2968
#define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE2 0x2969
#define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2 0x296a
#define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE2 0x296b
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE2 0x296c
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE2 0x296d
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE2 0x296e
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE2 0x296f
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE2 0x2970
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE2 0x2971
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE2 0x2972
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE2 0x2973
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE2 0x2974
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE2 0x2975
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE2 0x2976
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE2 0x2977
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE3 0x2978
#define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE3 0x2979
#define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3 0x297a
#define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE3 0x297b
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE3 0x297c
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE3 0x297d
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE3 0x297e
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE3 0x297f
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE3 0x2980
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE3 0x2981
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE3 0x2982
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE3 0x2983
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE3 0x2984
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE3 0x2985
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE3 0x2986
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE3 0x2987
#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE3_BASE_IDX 2
// addressBlock: dce_dc_combophy_dc_combophypllregs0_dispdec
// base address: 0x0
#define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL0 0x2988
#define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL0_BASE_IDX 2
#define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL1 0x2989
#define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL1_BASE_IDX 2
#define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL2 0x298a
#define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL2_BASE_IDX 2
#define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL3 0x298b
#define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL3_BASE_IDX 2
#define mmDC_COMBOPHYPLLREGS0_BW_CTRL_COARSE 0x298c
#define mmDC_COMBOPHYPLLREGS0_BW_CTRL_COARSE_BASE_IDX 2
#define mmDC_COMBOPHYPLLREGS0_BW_CTRL_FINE 0x298d
#define mmDC_COMBOPHYPLLREGS0_BW_CTRL_FINE_BASE_IDX 2
#define mmDC_COMBOPHYPLLREGS0_CAL_CTRL 0x298e
#define mmDC_COMBOPHYPLLREGS0_CAL_CTRL_BASE_IDX 2
#define mmDC_COMBOPHYPLLREGS0_LOOP_CTRL 0x298f
#define mmDC_COMBOPHYPLLREGS0_LOOP_CTRL_BASE_IDX 2
#define mmDC_COMBOPHYPLLREGS0_VREG_CFG 0x2991
#define mmDC_COMBOPHYPLLREGS0_VREG_CFG_BASE_IDX 2
#define mmDC_COMBOPHYPLLREGS0_OBSERVE0 0x2992
#define mmDC_COMBOPHYPLLREGS0_OBSERVE0_BASE_IDX 2
#define mmDC_COMBOPHYPLLREGS0_OBSERVE1 0x2993
#define mmDC_COMBOPHYPLLREGS0_OBSERVE1_BASE_IDX 2
#define mmDC_COMBOPHYPLLREGS0_DFT_OUT 0x2994
#define mmDC_COMBOPHYPLLREGS0_DFT_OUT_BASE_IDX 2
#define mmDC_COMBOPHYPLLREGS0_PLL_WRAP_CNTRL1 0x29c6
#define mmDC_COMBOPHYPLLREGS0_PLL_WRAP_CNTRL1_BASE_IDX 2
#define mmDC_COMBOPHYPLLREGS0_PLL_WRAP_CNTRL 0x29c7
#define mmDC_COMBOPHYPLLREGS0_PLL_WRAP_CNTRL_BASE_IDX 2
// addressBlock: dce_dc_dcio_dcio_uniphy1_dispdec
// base address: 0x360
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0 0x2a00
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1 0x2a01
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2 0x2a02
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3 0x2a03
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4 0x2a04
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5 0x2a05
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6 0x2a06
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7 0x2a07
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8 0x2a08
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9 0x2a09
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10 0x2a0a
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11 0x2a0b
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12 0x2a0c
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13 0x2a0d
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14 0x2a0e
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15 0x2a0f
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16 0x2a10
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17 0x2a11
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18 0x2a12
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19 0x2a13
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20 0x2a14
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21 0x2a15
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22 0x2a16
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23 0x2a17
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24 0x2a18
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25 0x2a19
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26 0x2a1a
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27 0x2a1b
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28 0x2a1c
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29 0x2a1d
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30 0x2a1e
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31 0x2a1f
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32 0x2a20
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33 0x2a21
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34 0x2a22
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35 0x2a23
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36 0x2a24
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37 0x2a25
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38 0x2a26
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39 0x2a27
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40 0x2a28
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41 0x2a29
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42 0x2a2a
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43 0x2a2b
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44 0x2a2c
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45 0x2a2d
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46 0x2a2e
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47 0x2a2f
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48 0x2a30
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49 0x2a31
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50 0x2a32
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51 0x2a33
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52 0x2a34
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53 0x2a35
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54 0x2a36
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55 0x2a37
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56 0x2a38
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57 0x2a39
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED58 0x2a3a
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED58_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED59 0x2a3b
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED59_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED60 0x2a3c
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED60_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED61 0x2a3d
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED61_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED62 0x2a3e
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED62_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED63 0x2a3f
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED63_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED64 0x2a40
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED64_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED65 0x2a41
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED65_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED66 0x2a42
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED66_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED67 0x2a43
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED67_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED68 0x2a44
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED68_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED69 0x2a45
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED69_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED70 0x2a46
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED70_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED71 0x2a47
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED71_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED72 0x2a48
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED72_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED73 0x2a49
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED73_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED74 0x2a4a
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED74_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED75 0x2a4b
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED75_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED76 0x2a4c
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED76_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED77 0x2a4d
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED77_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED78 0x2a4e
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED78_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED79 0x2a4f
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED79_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED80 0x2a50
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED80_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED81 0x2a51
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED81_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED82 0x2a52
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED82_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED83 0x2a53
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED83_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED84 0x2a54
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED84_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED85 0x2a55
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED85_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED86 0x2a56
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED86_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED87 0x2a57
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED87_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED88 0x2a58
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED88_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED89 0x2a59
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED89_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED90 0x2a5a
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED90_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED91 0x2a5b
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED91_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED92 0x2a5c
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED92_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED93 0x2a5d
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED93_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED94 0x2a5e
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED94_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED95 0x2a5f
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED95_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED96 0x2a60
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED96_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED97 0x2a61
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED97_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED98 0x2a62
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED98_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED99 0x2a63
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED99_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED100 0x2a64
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED100_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED101 0x2a65
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED101_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED102 0x2a66
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED102_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED103 0x2a67
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED103_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED104 0x2a68
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED104_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED105 0x2a69
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED105_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED106 0x2a6a
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED106_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED107 0x2a6b
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED107_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED108 0x2a6c
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED108_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED109 0x2a6d
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED109_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED110 0x2a6e
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED110_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED111 0x2a6f
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED111_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED112 0x2a70
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED112_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED113 0x2a71
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED113_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED114 0x2a72
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED114_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED115 0x2a73
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED115_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED116 0x2a74
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED116_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED117 0x2a75
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED117_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED118 0x2a76
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED118_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED119 0x2a77
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED119_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED120 0x2a78
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED120_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED121 0x2a79
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED121_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED122 0x2a7a
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED122_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED123 0x2a7b
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED123_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED124 0x2a7c
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED124_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED125 0x2a7d
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED125_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED126 0x2a7e
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED126_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED127 0x2a7f
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED127_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED128 0x2a80
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED128_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED129 0x2a81
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED129_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED130 0x2a82
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED130_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED131 0x2a83
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED131_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED132 0x2a84
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED132_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED133 0x2a85
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED133_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED134 0x2a86
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED134_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED135 0x2a87
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED135_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED136 0x2a88
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED136_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED137 0x2a89
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED137_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED138 0x2a8a
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED138_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED139 0x2a8b
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED139_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED140 0x2a8c
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED140_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED141 0x2a8d
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED141_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED142 0x2a8e
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED142_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED143 0x2a8f
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED143_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED144 0x2a90
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED144_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED145 0x2a91
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED145_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED146 0x2a92
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED146_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED147 0x2a93
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED147_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED148 0x2a94
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED148_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED149 0x2a95
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED149_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED150 0x2a96
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED150_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED151 0x2a97
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED151_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED152 0x2a98
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED152_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED153 0x2a99
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED153_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED154 0x2a9a
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED154_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED155 0x2a9b
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED155_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED156 0x2a9c
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED156_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED157 0x2a9d
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED157_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED158 0x2a9e
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED158_BASE_IDX 2
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED159 0x2a9f
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED159_BASE_IDX 2
// addressBlock: dce_dc_combophy_dc_combophycmregs1_dispdec
// base address: 0x360
#define mmDC_COMBOPHYCMREGS1_COMMON_FUSE1 0x2a00
#define mmDC_COMBOPHYCMREGS1_COMMON_FUSE1_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS1_COMMON_FUSE2 0x2a01
#define mmDC_COMBOPHYCMREGS1_COMMON_FUSE2_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS1_COMMON_FUSE3 0x2a02
#define mmDC_COMBOPHYCMREGS1_COMMON_FUSE3_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS1_COMMON_MAR_DEEMPH_NOM 0x2a03
#define mmDC_COMBOPHYCMREGS1_COMMON_MAR_DEEMPH_NOM_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS1_COMMON_LANE_PWRMGMT 0x2a04
#define mmDC_COMBOPHYCMREGS1_COMMON_LANE_PWRMGMT_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS1_COMMON_TXCNTRL 0x2a05
#define mmDC_COMBOPHYCMREGS1_COMMON_TXCNTRL_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS1_COMMON_TMDP 0x2a06
#define mmDC_COMBOPHYCMREGS1_COMMON_TMDP_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS1_COMMON_LANE_RESETS 0x2a07
#define mmDC_COMBOPHYCMREGS1_COMMON_LANE_RESETS_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS1_COMMON_ZCALCODE_CTRL 0x2a08
#define mmDC_COMBOPHYCMREGS1_COMMON_ZCALCODE_CTRL_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU1 0x2a09
#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU1_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU2 0x2a0a
#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU2_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU3 0x2a0b
#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU3_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU4 0x2a0c
#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU4_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU5 0x2a0d
#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU5_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU6 0x2a0e
#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU6_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU7 0x2a0f
#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU7_BASE_IDX 2
// addressBlock: dce_dc_combophy_dc_combophytxregs1_dispdec
// base address: 0x360
#define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE0 0x2a20
#define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE0 0x2a21
#define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0 0x2a22
#define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE0 0x2a23
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE0 0x2a24
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE0 0x2a25
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE0 0x2a26
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE0 0x2a27
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE0 0x2a28
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE0 0x2a29
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE0 0x2a2a
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE0 0x2a2b
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE0 0x2a2c
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE0 0x2a2d
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE0 0x2a2e
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE0 0x2a2f
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE1 0x2a30
#define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE1 0x2a31
#define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1 0x2a32
#define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE1 0x2a33
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE1 0x2a34
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE1 0x2a35
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE1 0x2a36
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE1 0x2a37
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE1 0x2a38
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE1 0x2a39
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE1 0x2a3a
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE1 0x2a3b
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE1 0x2a3c
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE1 0x2a3d
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE1 0x2a3e
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE1 0x2a3f
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE2 0x2a40
#define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE2 0x2a41
#define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2 0x2a42
#define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE2 0x2a43
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE2 0x2a44
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE2 0x2a45
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE2 0x2a46
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE2 0x2a47
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE2 0x2a48
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE2 0x2a49
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE2 0x2a4a
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE2 0x2a4b
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE2 0x2a4c
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE2 0x2a4d
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE2 0x2a4e
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE2 0x2a4f
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE3 0x2a50
#define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE3 0x2a51
#define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3 0x2a52
#define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE3 0x2a53
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE3 0x2a54
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE3 0x2a55
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE3 0x2a56
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE3 0x2a57
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE3 0x2a58
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE3 0x2a59
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE3 0x2a5a
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE3 0x2a5b
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE3 0x2a5c
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE3 0x2a5d
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE3 0x2a5e
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE3 0x2a5f
#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE3_BASE_IDX 2
// addressBlock: dce_dc_combophy_dc_combophypllregs1_dispdec
// base address: 0x360
#define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL0 0x2a60
#define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL0_BASE_IDX 2
#define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL1 0x2a61
#define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL1_BASE_IDX 2
#define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL2 0x2a62
#define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL2_BASE_IDX 2
#define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL3 0x2a63
#define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL3_BASE_IDX 2
#define mmDC_COMBOPHYPLLREGS1_BW_CTRL_COARSE 0x2a64
#define mmDC_COMBOPHYPLLREGS1_BW_CTRL_COARSE_BASE_IDX 2
#define mmDC_COMBOPHYPLLREGS1_BW_CTRL_FINE 0x2a65
#define mmDC_COMBOPHYPLLREGS1_BW_CTRL_FINE_BASE_IDX 2
#define mmDC_COMBOPHYPLLREGS1_CAL_CTRL 0x2a66
#define mmDC_COMBOPHYPLLREGS1_CAL_CTRL_BASE_IDX 2
#define mmDC_COMBOPHYPLLREGS1_LOOP_CTRL 0x2a67
#define mmDC_COMBOPHYPLLREGS1_LOOP_CTRL_BASE_IDX 2
#define mmDC_COMBOPHYPLLREGS1_VREG_CFG 0x2a69
#define mmDC_COMBOPHYPLLREGS1_VREG_CFG_BASE_IDX 2
#define mmDC_COMBOPHYPLLREGS1_OBSERVE0 0x2a6a
#define mmDC_COMBOPHYPLLREGS1_OBSERVE0_BASE_IDX 2
#define mmDC_COMBOPHYPLLREGS1_OBSERVE1 0x2a6b
#define mmDC_COMBOPHYPLLREGS1_OBSERVE1_BASE_IDX 2
#define mmDC_COMBOPHYPLLREGS1_DFT_OUT 0x2a6c
#define mmDC_COMBOPHYPLLREGS1_DFT_OUT_BASE_IDX 2
#define mmDC_COMBOPHYPLLREGS1_PLL_WRAP_CNTRL1 0x2a9e
#define mmDC_COMBOPHYPLLREGS1_PLL_WRAP_CNTRL1_BASE_IDX 2
#define mmDC_COMBOPHYPLLREGS1_PLL_WRAP_CNTRL 0x2a9f
#define mmDC_COMBOPHYPLLREGS1_PLL_WRAP_CNTRL_BASE_IDX 2
// addressBlock: dce_dc_dcio_dcio_uniphy2_dispdec
// base address: 0x6c0
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0 0x2ad8
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1 0x2ad9
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2 0x2ada
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3 0x2adb
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4 0x2adc
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5 0x2add
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6 0x2ade
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7 0x2adf
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8 0x2ae0
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9 0x2ae1
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10 0x2ae2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11 0x2ae3
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12 0x2ae4
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13 0x2ae5
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14 0x2ae6
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15 0x2ae7
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16 0x2ae8
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17 0x2ae9
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18 0x2aea
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19 0x2aeb
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20 0x2aec
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21 0x2aed
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22 0x2aee
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23 0x2aef
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24 0x2af0
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25 0x2af1
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26 0x2af2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27 0x2af3
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28 0x2af4
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29 0x2af5
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30 0x2af6
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31 0x2af7
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32 0x2af8
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33 0x2af9
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34 0x2afa
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35 0x2afb
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36 0x2afc
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37 0x2afd
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38 0x2afe
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39 0x2aff
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40 0x2b00
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41 0x2b01
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42 0x2b02
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43 0x2b03
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44 0x2b04
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45 0x2b05
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46 0x2b06
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47 0x2b07
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48 0x2b08
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49 0x2b09
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50 0x2b0a
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51 0x2b0b
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52 0x2b0c
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53 0x2b0d
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54 0x2b0e
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55 0x2b0f
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56 0x2b10
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57 0x2b11
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED58 0x2b12
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED58_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED59 0x2b13
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED59_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED60 0x2b14
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED60_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED61 0x2b15
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED61_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED62 0x2b16
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED62_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED63 0x2b17
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED63_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED64 0x2b18
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED64_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED65 0x2b19
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED65_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED66 0x2b1a
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED66_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED67 0x2b1b
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED67_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED68 0x2b1c
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED68_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED69 0x2b1d
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED69_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED70 0x2b1e
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED70_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED71 0x2b1f
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED71_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED72 0x2b20
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED72_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED73 0x2b21
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED73_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED74 0x2b22
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED74_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED75 0x2b23
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED75_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED76 0x2b24
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED76_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED77 0x2b25
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED77_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED78 0x2b26
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED78_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED79 0x2b27
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED79_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED80 0x2b28
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED80_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED81 0x2b29
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED81_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED82 0x2b2a
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED82_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED83 0x2b2b
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED83_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED84 0x2b2c
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED84_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED85 0x2b2d
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED85_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED86 0x2b2e
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED86_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED87 0x2b2f
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED87_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED88 0x2b30
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED88_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED89 0x2b31
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED89_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED90 0x2b32
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED90_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED91 0x2b33
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED91_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED92 0x2b34
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED92_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED93 0x2b35
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED93_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED94 0x2b36
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED94_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED95 0x2b37
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED95_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED96 0x2b38
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED96_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED97 0x2b39
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED97_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED98 0x2b3a
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED98_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED99 0x2b3b
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED99_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED100 0x2b3c
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED100_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED101 0x2b3d
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED101_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED102 0x2b3e
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED102_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED103 0x2b3f
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED103_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED104 0x2b40
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED104_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED105 0x2b41
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED105_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED106 0x2b42
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED106_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED107 0x2b43
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED107_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED108 0x2b44
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED108_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED109 0x2b45
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED109_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED110 0x2b46
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED110_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED111 0x2b47
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED111_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED112 0x2b48
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED112_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED113 0x2b49
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED113_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED114 0x2b4a
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED114_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED115 0x2b4b
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED115_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED116 0x2b4c
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED116_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED117 0x2b4d
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED117_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED118 0x2b4e
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED118_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED119 0x2b4f
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED119_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED120 0x2b50
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED120_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED121 0x2b51
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED121_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED122 0x2b52
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED122_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED123 0x2b53
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED123_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED124 0x2b54
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED124_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED125 0x2b55
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED125_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED126 0x2b56
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED126_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED127 0x2b57
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED127_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED128 0x2b58
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED128_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED129 0x2b59
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED129_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED130 0x2b5a
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED130_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED131 0x2b5b
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED131_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED132 0x2b5c
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED132_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED133 0x2b5d
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED133_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED134 0x2b5e
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED134_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED135 0x2b5f
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED135_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED136 0x2b60
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED136_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED137 0x2b61
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED137_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED138 0x2b62
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED138_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED139 0x2b63
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED139_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED140 0x2b64
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED140_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED141 0x2b65
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED141_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED142 0x2b66
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED142_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED143 0x2b67
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED143_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED144 0x2b68
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED144_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED145 0x2b69
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED145_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED146 0x2b6a
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED146_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED147 0x2b6b
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED147_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED148 0x2b6c
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED148_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED149 0x2b6d
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED149_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED150 0x2b6e
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED150_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED151 0x2b6f
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED151_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED152 0x2b70
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED152_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED153 0x2b71
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED153_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED154 0x2b72
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED154_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED155 0x2b73
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED155_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED156 0x2b74
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED156_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED157 0x2b75
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED157_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED158 0x2b76
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED158_BASE_IDX 2
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED159 0x2b77
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED159_BASE_IDX 2
// addressBlock: dce_dc_combophy_dc_combophycmregs2_dispdec
// base address: 0x6c0
#define mmDC_COMBOPHYCMREGS2_COMMON_FUSE1 0x2ad8
#define mmDC_COMBOPHYCMREGS2_COMMON_FUSE1_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS2_COMMON_FUSE2 0x2ad9
#define mmDC_COMBOPHYCMREGS2_COMMON_FUSE2_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS2_COMMON_FUSE3 0x2ada
#define mmDC_COMBOPHYCMREGS2_COMMON_FUSE3_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS2_COMMON_MAR_DEEMPH_NOM 0x2adb
#define mmDC_COMBOPHYCMREGS2_COMMON_MAR_DEEMPH_NOM_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS2_COMMON_LANE_PWRMGMT 0x2adc
#define mmDC_COMBOPHYCMREGS2_COMMON_LANE_PWRMGMT_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS2_COMMON_TXCNTRL 0x2add
#define mmDC_COMBOPHYCMREGS2_COMMON_TXCNTRL_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS2_COMMON_TMDP 0x2ade
#define mmDC_COMBOPHYCMREGS2_COMMON_TMDP_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS2_COMMON_LANE_RESETS 0x2adf
#define mmDC_COMBOPHYCMREGS2_COMMON_LANE_RESETS_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS2_COMMON_ZCALCODE_CTRL 0x2ae0
#define mmDC_COMBOPHYCMREGS2_COMMON_ZCALCODE_CTRL_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU1 0x2ae1
#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU1_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU2 0x2ae2
#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU2_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU3 0x2ae3
#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU3_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU4 0x2ae4
#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU4_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU5 0x2ae5
#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU5_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU6 0x2ae6
#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU6_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU7 0x2ae7
#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU7_BASE_IDX 2
// addressBlock: dce_dc_combophy_dc_combophytxregs2_dispdec
// base address: 0x6c0
#define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE0 0x2af8
#define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE0 0x2af9
#define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0 0x2afa
#define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE0 0x2afb
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE0 0x2afc
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE0 0x2afd
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE0 0x2afe
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE0 0x2aff
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE0 0x2b00
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE0 0x2b01
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE0 0x2b02
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE0 0x2b03
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE0 0x2b04
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE0 0x2b05
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE0 0x2b06
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE0 0x2b07
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE1 0x2b08
#define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE1 0x2b09
#define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1 0x2b0a
#define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE1 0x2b0b
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE1 0x2b0c
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE1 0x2b0d
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE1 0x2b0e
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE1 0x2b0f
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE1 0x2b10
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE1 0x2b11
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE1 0x2b12
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE1 0x2b13
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE1 0x2b14
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE1 0x2b15
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE1 0x2b16
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE1 0x2b17
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE2 0x2b18
#define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE2 0x2b19
#define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2 0x2b1a
#define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE2 0x2b1b
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE2 0x2b1c
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE2 0x2b1d
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE2 0x2b1e
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE2 0x2b1f
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE2 0x2b20
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE2 0x2b21
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE2 0x2b22
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE2 0x2b23
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE2 0x2b24
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE2 0x2b25
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE2 0x2b26
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE2 0x2b27
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE3 0x2b28
#define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE3 0x2b29
#define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3 0x2b2a
#define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE3 0x2b2b
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE3 0x2b2c
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE3 0x2b2d
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE3 0x2b2e
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE3 0x2b2f
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE3 0x2b30
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE3 0x2b31
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE3 0x2b32
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE3 0x2b33
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE3 0x2b34
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE3 0x2b35
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE3 0x2b36
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE3 0x2b37
#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE3_BASE_IDX 2
// addressBlock: dce_dc_combophy_dc_combophypllregs2_dispdec
// base address: 0x6c0
#define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL0 0x2b38
#define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL0_BASE_IDX 2
#define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL1 0x2b39
#define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL1_BASE_IDX 2
#define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL2 0x2b3a
#define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL2_BASE_IDX 2
#define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL3 0x2b3b
#define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL3_BASE_IDX 2
#define mmDC_COMBOPHYPLLREGS2_BW_CTRL_COARSE 0x2b3c
#define mmDC_COMBOPHYPLLREGS2_BW_CTRL_COARSE_BASE_IDX 2
#define mmDC_COMBOPHYPLLREGS2_BW_CTRL_FINE 0x2b3d
#define mmDC_COMBOPHYPLLREGS2_BW_CTRL_FINE_BASE_IDX 2
#define mmDC_COMBOPHYPLLREGS2_CAL_CTRL 0x2b3e
#define mmDC_COMBOPHYPLLREGS2_CAL_CTRL_BASE_IDX 2
#define mmDC_COMBOPHYPLLREGS2_LOOP_CTRL 0x2b3f
#define mmDC_COMBOPHYPLLREGS2_LOOP_CTRL_BASE_IDX 2
#define mmDC_COMBOPHYPLLREGS2_VREG_CFG 0x2b41
#define mmDC_COMBOPHYPLLREGS2_VREG_CFG_BASE_IDX 2
#define mmDC_COMBOPHYPLLREGS2_OBSERVE0 0x2b42
#define mmDC_COMBOPHYPLLREGS2_OBSERVE0_BASE_IDX 2
#define mmDC_COMBOPHYPLLREGS2_OBSERVE1 0x2b43
#define mmDC_COMBOPHYPLLREGS2_OBSERVE1_BASE_IDX 2
#define mmDC_COMBOPHYPLLREGS2_DFT_OUT 0x2b44
#define mmDC_COMBOPHYPLLREGS2_DFT_OUT_BASE_IDX 2
#define mmDC_COMBOPHYPLLREGS2_PLL_WRAP_CNTRL1 0x2b76
#define mmDC_COMBOPHYPLLREGS2_PLL_WRAP_CNTRL1_BASE_IDX 2
#define mmDC_COMBOPHYPLLREGS2_PLL_WRAP_CNTRL 0x2b77
#define mmDC_COMBOPHYPLLREGS2_PLL_WRAP_CNTRL_BASE_IDX 2
// addressBlock: dce_dc_dcio_dcio_uniphy3_dispdec
// base address: 0xa20
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0 0x2bb0
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1 0x2bb1
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2 0x2bb2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3 0x2bb3
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4 0x2bb4
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5 0x2bb5
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6 0x2bb6
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7 0x2bb7
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8 0x2bb8
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9 0x2bb9
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10 0x2bba
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11 0x2bbb
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12 0x2bbc
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13 0x2bbd
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14 0x2bbe
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15 0x2bbf
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16 0x2bc0
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17 0x2bc1
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18 0x2bc2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19 0x2bc3
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20 0x2bc4
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21 0x2bc5
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22 0x2bc6
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23 0x2bc7
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24 0x2bc8
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25 0x2bc9
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26 0x2bca
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27 0x2bcb
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28 0x2bcc
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29 0x2bcd
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30 0x2bce
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31 0x2bcf
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32 0x2bd0
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33 0x2bd1
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34 0x2bd2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35 0x2bd3
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36 0x2bd4
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37 0x2bd5
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38 0x2bd6
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39 0x2bd7
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40 0x2bd8
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41 0x2bd9
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42 0x2bda
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43 0x2bdb
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44 0x2bdc
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45 0x2bdd
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46 0x2bde
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47 0x2bdf
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48 0x2be0
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49 0x2be1
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50 0x2be2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51 0x2be3
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52 0x2be4
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53 0x2be5
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54 0x2be6
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55 0x2be7
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56 0x2be8
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57 0x2be9
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED58 0x2bea
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED58_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED59 0x2beb
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED59_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED60 0x2bec
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED60_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED61 0x2bed
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED61_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED62 0x2bee
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED62_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED63 0x2bef
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED63_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED64 0x2bf0
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED64_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED65 0x2bf1
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED65_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED66 0x2bf2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED66_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED67 0x2bf3
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED67_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED68 0x2bf4
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED68_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED69 0x2bf5
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED69_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED70 0x2bf6
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED70_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED71 0x2bf7
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED71_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED72 0x2bf8
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED72_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED73 0x2bf9
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED73_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED74 0x2bfa
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED74_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED75 0x2bfb
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED75_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED76 0x2bfc
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED76_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED77 0x2bfd
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED77_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED78 0x2bfe
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED78_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED79 0x2bff
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED79_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED80 0x2c00
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED80_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED81 0x2c01
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED81_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED82 0x2c02
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED82_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED83 0x2c03
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED83_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED84 0x2c04
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED84_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED85 0x2c05
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED85_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED86 0x2c06
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED86_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED87 0x2c07
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED87_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED88 0x2c08
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED88_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED89 0x2c09
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED89_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED90 0x2c0a
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED90_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED91 0x2c0b
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED91_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED92 0x2c0c
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED92_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED93 0x2c0d
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED93_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED94 0x2c0e
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED94_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED95 0x2c0f
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED95_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED96 0x2c10
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED96_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED97 0x2c11
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED97_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED98 0x2c12
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED98_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED99 0x2c13
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED99_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED100 0x2c14
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED100_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED101 0x2c15
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED101_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED102 0x2c16
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED102_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED103 0x2c17
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED103_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED104 0x2c18
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED104_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED105 0x2c19
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED105_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED106 0x2c1a
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED106_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED107 0x2c1b
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED107_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED108 0x2c1c
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED108_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED109 0x2c1d
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED109_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED110 0x2c1e
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED110_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED111 0x2c1f
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED111_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED112 0x2c20
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED112_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED113 0x2c21
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED113_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED114 0x2c22
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED114_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED115 0x2c23
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED115_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED116 0x2c24
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED116_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED117 0x2c25
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED117_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED118 0x2c26
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED118_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED119 0x2c27
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED119_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED120 0x2c28
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED120_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED121 0x2c29
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED121_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED122 0x2c2a
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED122_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED123 0x2c2b
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED123_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED124 0x2c2c
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED124_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED125 0x2c2d
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED125_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED126 0x2c2e
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED126_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED127 0x2c2f
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED127_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED128 0x2c30
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED128_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED129 0x2c31
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED129_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED130 0x2c32
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED130_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED131 0x2c33
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED131_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED132 0x2c34
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED132_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED133 0x2c35
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED133_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED134 0x2c36
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED134_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED135 0x2c37
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED135_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED136 0x2c38
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED136_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED137 0x2c39
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED137_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED138 0x2c3a
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED138_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED139 0x2c3b
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED139_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED140 0x2c3c
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED140_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED141 0x2c3d
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED141_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED142 0x2c3e
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED142_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED143 0x2c3f
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED143_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED144 0x2c40
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED144_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED145 0x2c41
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED145_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED146 0x2c42
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED146_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED147 0x2c43
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED147_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED148 0x2c44
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED148_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED149 0x2c45
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED149_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED150 0x2c46
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED150_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED151 0x2c47
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED151_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED152 0x2c48
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED152_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED153 0x2c49
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED153_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED154 0x2c4a
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED154_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED155 0x2c4b
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED155_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED156 0x2c4c
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED156_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED157 0x2c4d
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED157_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED158 0x2c4e
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED158_BASE_IDX 2
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED159 0x2c4f
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED159_BASE_IDX 2
// addressBlock: dce_dc_combophy_dc_combophycmregs3_dispdec
// base address: 0xa20
#define mmDC_COMBOPHYCMREGS3_COMMON_FUSE1 0x2bb0
#define mmDC_COMBOPHYCMREGS3_COMMON_FUSE1_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS3_COMMON_FUSE2 0x2bb1
#define mmDC_COMBOPHYCMREGS3_COMMON_FUSE2_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS3_COMMON_FUSE3 0x2bb2
#define mmDC_COMBOPHYCMREGS3_COMMON_FUSE3_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS3_COMMON_MAR_DEEMPH_NOM 0x2bb3
#define mmDC_COMBOPHYCMREGS3_COMMON_MAR_DEEMPH_NOM_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS3_COMMON_LANE_PWRMGMT 0x2bb4
#define mmDC_COMBOPHYCMREGS3_COMMON_LANE_PWRMGMT_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS3_COMMON_TXCNTRL 0x2bb5
#define mmDC_COMBOPHYCMREGS3_COMMON_TXCNTRL_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS3_COMMON_TMDP 0x2bb6
#define mmDC_COMBOPHYCMREGS3_COMMON_TMDP_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS3_COMMON_LANE_RESETS 0x2bb7
#define mmDC_COMBOPHYCMREGS3_COMMON_LANE_RESETS_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS3_COMMON_ZCALCODE_CTRL 0x2bb8
#define mmDC_COMBOPHYCMREGS3_COMMON_ZCALCODE_CTRL_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU1 0x2bb9
#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU1_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU2 0x2bba
#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU2_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU3 0x2bbb
#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU3_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU4 0x2bbc
#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU4_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU5 0x2bbd
#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU5_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU6 0x2bbe
#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU6_BASE_IDX 2
#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU7 0x2bbf
#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU7_BASE_IDX 2
// addressBlock: dce_dc_combophy_dc_combophytxregs3_dispdec
// base address: 0xa20
#define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE0 0x2bd0
#define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE0 0x2bd1
#define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0 0x2bd2
#define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE0 0x2bd3
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE0 0x2bd4
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE0 0x2bd5
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE0 0x2bd6
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE0 0x2bd7
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE0 0x2bd8
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE0 0x2bd9
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE0 0x2bda
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE0 0x2bdb
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE0 0x2bdc
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE0 0x2bdd
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE0 0x2bde
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE0 0x2bdf
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE0_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE1 0x2be0
#define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE1 0x2be1
#define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1 0x2be2
#define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE1 0x2be3
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE1 0x2be4
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE1 0x2be5
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE1 0x2be6
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE1 0x2be7
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE1 0x2be8
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE1 0x2be9
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE1 0x2bea
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE1 0x2beb
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE1 0x2bec
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE1 0x2bed
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE1 0x2bee
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE1 0x2bef
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE1_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE2 0x2bf0
#define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE2 0x2bf1
#define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2 0x2bf2
#define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE2 0x2bf3
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE2 0x2bf4
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE2 0x2bf5
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE2 0x2bf6
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE2 0x2bf7
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE2 0x2bf8
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE2 0x2bf9
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE2 0x2bfa
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE2 0x2bfb
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE2 0x2bfc
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE2 0x2bfd
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE2 0x2bfe
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE2 0x2bff
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE2_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE3 0x2c00
#define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE3 0x2c01
#define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3 0x2c02
#define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE3 0x2c03
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE3 0x2c04
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE3 0x2c05
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE3 0x2c06
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE3 0x2c07
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE3 0x2c08
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE3 0x2c09
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE3 0x2c0a
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE3 0x2c0b
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE3 0x2c0c
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE3 0x2c0d
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE3 0x2c0e
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE3_BASE_IDX 2
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE3 0x2c0f
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE3_BASE_IDX 2
// addressBlock: dce_dc_combophy_dc_combophypllregs3_dispdec
// base address: 0xa20
#define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL0 0x2c10
#define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL0_BASE_IDX 2
#define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL1 0x2c11
#define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL1_BASE_IDX 2
#define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL2 0x2c12
#define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL2_BASE_IDX 2
#define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL3 0x2c13
#define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL3_BASE_IDX 2
#define mmDC_COMBOPHYPLLREGS3_BW_CTRL_COARSE 0x2c14
#define mmDC_COMBOPHYPLLREGS3_BW_CTRL_COARSE_BASE_IDX 2
#define mmDC_COMBOPHYPLLREGS3_BW_CTRL_FINE 0x2c15
#define mmDC_COMBOPHYPLLREGS3_BW_CTRL_FINE_BASE_IDX 2
#define mmDC_COMBOPHYPLLREGS3_CAL_CTRL 0x2c16
#define mmDC_COMBOPHYPLLREGS3_CAL_CTRL_BASE_IDX 2
#define mmDC_COMBOPHYPLLREGS3_LOOP_CTRL 0x2c17
#define mmDC_COMBOPHYPLLREGS3_LOOP_CTRL_BASE_IDX 2
#define mmDC_COMBOPHYPLLREGS3_VREG_CFG 0x2c19
#define mmDC_COMBOPHYPLLREGS3_VREG_CFG_BASE_IDX 2
#define mmDC_COMBOPHYPLLREGS3_OBSERVE0 0x2c1a
#define mmDC_COMBOPHYPLLREGS3_OBSERVE0_BASE_IDX 2
#define mmDC_COMBOPHYPLLREGS3_OBSERVE1 0x2c1b
#define mmDC_COMBOPHYPLLREGS3_OBSERVE1_BASE_IDX 2
#define mmDC_COMBOPHYPLLREGS3_DFT_OUT 0x2c1c
#define mmDC_COMBOPHYPLLREGS3_DFT_OUT_BASE_IDX 2
#define mmDC_COMBOPHYPLLREGS3_PLL_WRAP_CNTRL1 0x2c4e
#define mmDC_COMBOPHYPLLREGS3_PLL_WRAP_CNTRL1_BASE_IDX 2
#define mmDC_COMBOPHYPLLREGS3_PLL_WRAP_CNTRL 0x2c4f
#define mmDC_COMBOPHYPLLREGS3_PLL_WRAP_CNTRL_BASE_IDX 2
// addressBlock: dce_dc_dcio_dcio_zcal_dispdec
// base address: 0x0
#define mmZCAL_MACRO_CNTL_RESERVED0 0x2fe8
#define mmZCAL_MACRO_CNTL_RESERVED0_BASE_IDX 2
#define mmZCAL_MACRO_CNTL_RESERVED1 0x2fe9
#define mmZCAL_MACRO_CNTL_RESERVED1_BASE_IDX 2
#define mmZCAL_MACRO_CNTL_RESERVED2 0x2fea
#define mmZCAL_MACRO_CNTL_RESERVED2_BASE_IDX 2
#define mmZCAL_MACRO_CNTL_RESERVED3 0x2feb
#define mmZCAL_MACRO_CNTL_RESERVED3_BASE_IDX 2
#define mmZCAL_MACRO_CNTL_RESERVED4 0x2fec
#define mmZCAL_MACRO_CNTL_RESERVED4_BASE_IDX 2
// addressBlock: dce_dc_zcal_dc_zcalregs_dispdec
// base address: 0x0
#define mmCOMP_EN_CTL 0x2fe8
#define mmCOMP_EN_CTL_BASE_IDX 2
#define mmCOMP_EN_DFX 0x2fe9
#define mmCOMP_EN_DFX_BASE_IDX 2
#define mmZCAL_FUSES 0x2fea
#define mmZCAL_FUSES_BASE_IDX 2
// addressBlock: vga_vgaseqind
// base address: 0x0
#define ixSEQ00 0x0000
#define ixSEQ01 0x0001
#define ixSEQ02 0x0002
#define ixSEQ03 0x0003
#define ixSEQ04 0x0004
// addressBlock: vga_vgacrtind
// base address: 0x0
#define ixCRT00 0x0000
#define ixCRT01 0x0001
#define ixCRT02 0x0002
#define ixCRT03 0x0003
#define ixCRT04 0x0004
#define ixCRT05 0x0005
#define ixCRT06 0x0006
#define ixCRT07 0x0007
#define ixCRT08 0x0008
#define ixCRT09 0x0009
#define ixCRT0A 0x000a
#define ixCRT0B 0x000b
#define ixCRT0C 0x000c
#define ixCRT0D 0x000d
#define ixCRT0E 0x000e
#define ixCRT0F 0x000f
#define ixCRT10 0x0010
#define ixCRT11 0x0011
#define ixCRT12 0x0012
#define ixCRT13 0x0013
#define ixCRT14 0x0014
#define ixCRT15 0x0015
#define ixCRT16 0x0016
#define ixCRT17 0x0017
#define ixCRT18 0x0018
#define ixCRT1E 0x001e
#define ixCRT1F 0x001f
#define ixCRT22 0x0022
// addressBlock: vga_vgagrphind
// base address: 0x0
#define ixGRA00 0x0000
#define ixGRA01 0x0001
#define ixGRA02 0x0002
#define ixGRA03 0x0003
#define ixGRA04 0x0004
#define ixGRA05 0x0005
#define ixGRA06 0x0006
#define ixGRA07 0x0007
#define ixGRA08 0x0008
// addressBlock: vga_vgaattrind
// base address: 0x0
#define ixATTR00 0x0000
#define ixATTR01 0x0001
#define ixATTR02 0x0002
#define ixATTR03 0x0003
#define ixATTR04 0x0004
#define ixATTR05 0x0005
#define ixATTR06 0x0006
#define ixATTR07 0x0007
#define ixATTR08 0x0008
#define ixATTR09 0x0009
#define ixATTR0A 0x000a
#define ixATTR0B 0x000b
#define ixATTR0C 0x000c
#define ixATTR0D 0x000d
#define ixATTR0E 0x000e
#define ixATTR0F 0x000f
#define ixATTR10 0x0010
#define ixATTR11 0x0011
#define ixATTR12 0x0012
#define ixATTR13 0x0013
#define ixATTR14 0x0014
// base address: 0x0
// base address: 0x0
// base address: 0x0
// base address: 0x0
// base address: 0x0
// base address: 0x0
// base address: 0x0
// base address: 0x0
// base address: 0x0
// base address: 0x0
// base address: 0x0
// base address: 0x0
// base address: 0x0
// base address: 0x0
// base address: 0x0
// base address: 0x0
// base address: 0x0
// base address: 0x0
// base address: 0x0
// base address: 0x0
// base address: 0x0
// base address: 0x0
// base address: 0x0
// base address: 0x0
// base address: 0x0
// base address: 0x0
// base address: 0x0
// base address: 0x0
// base address: 0x0
// base address: 0x0
// base address: 0x0
// base address: 0x0
// base address: 0x0
// base address: 0x0
// base address: 0x0
// addressBlock: azendpoint_f2codecind
// base address: 0x0
#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x2200
#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x2706
#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x270d
#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2 0x270e
#define ixAZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL 0x2724
#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3 0x273e
#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x2770
#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x2771
#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x2f09
#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x2f0a
#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x2f0b
#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY 0x3702
#define ixAZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x3707
#define ixAZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x3708
#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x3709
#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x371c
#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2 0x371d
#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3 0x371e
#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4 0x371f
#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION 0x3770
#define ixAZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION 0x3771
#define ixAZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO 0x3772
#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR 0x3776
#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA 0x3776
#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE 0x3777
#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE 0x3778
#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE 0x3779
#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE 0x377a
#define ixAZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC 0x377b
#define ixAZALIA_F2_CODEC_PIN_CONTROL_HBR 0x377c
#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX 0x3780
#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA 0x3781
#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE 0x3785
#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE 0x3786
#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE 0x3787
#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE 0x3788
#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x3789
#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x378a
#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x378b
#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x378c
#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x378d
#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x378e
#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x378f
#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x3790
#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x3791
#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x3792
#define ixAZALIA_F2_CODEC_PIN_ASSOCIATION_INFO 0x3793
#define ixAZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x3797
#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x3798
#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB 0x3799
#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x379a
#define ixAZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE 0x379b
#define ixAZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x379c
#define ixAZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x379d
#define ixAZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x379e
#define ixAZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x3f09
#define ixAZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES 0x3f0c
#define ixAZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH 0x3f0e
// addressBlock: azendpoint_descriptorind
// base address: 0x0
#define ixAUDIO_DESCRIPTOR0 0x0001
#define ixAUDIO_DESCRIPTOR1 0x0002
#define ixAUDIO_DESCRIPTOR2 0x0003
#define ixAUDIO_DESCRIPTOR3 0x0004
#define ixAUDIO_DESCRIPTOR4 0x0005
#define ixAUDIO_DESCRIPTOR5 0x0006
#define ixAUDIO_DESCRIPTOR6 0x0007
#define ixAUDIO_DESCRIPTOR7 0x0008
#define ixAUDIO_DESCRIPTOR8 0x0009
#define ixAUDIO_DESCRIPTOR9 0x000a
#define ixAUDIO_DESCRIPTOR10 0x000b
#define ixAUDIO_DESCRIPTOR11 0x000c
#define ixAUDIO_DESCRIPTOR12 0x000d
#define ixAUDIO_DESCRIPTOR13 0x000e
// addressBlock: azendpoint_sinkinfoind
// base address: 0x0
#define ixAZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID 0x0000
#define ixAZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID 0x0001
#define ixAZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN 0x0002
#define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID0 0x0003
#define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID1 0x0004
#define ixSINK_DESCRIPTION0 0x0005
#define ixSINK_DESCRIPTION1 0x0006
#define ixSINK_DESCRIPTION2 0x0007
#define ixSINK_DESCRIPTION3 0x0008
#define ixSINK_DESCRIPTION4 0x0009
#define ixSINK_DESCRIPTION5 0x000a
#define ixSINK_DESCRIPTION6 0x000b
#define ixSINK_DESCRIPTION7 0x000c
#define ixSINK_DESCRIPTION8 0x000d
#define ixSINK_DESCRIPTION9 0x000e
#define ixSINK_DESCRIPTION10 0x000f
#define ixSINK_DESCRIPTION11 0x0010
#define ixSINK_DESCRIPTION12 0x0011
#define ixSINK_DESCRIPTION13 0x0012
#define ixSINK_DESCRIPTION14 0x0013
#define ixSINK_DESCRIPTION15 0x0014
#define ixSINK_DESCRIPTION16 0x0015
#define ixSINK_DESCRIPTION17 0x0016
// addressBlock: azf0controller_azinputcrc0resultind
// base address: 0x0
#define ixAZALIA_INPUT_CRC0_CHANNEL0 0x0000
#define ixAZALIA_INPUT_CRC0_CHANNEL1 0x0001
#define ixAZALIA_INPUT_CRC0_CHANNEL2 0x0002
#define ixAZALIA_INPUT_CRC0_CHANNEL3 0x0003
#define ixAZALIA_INPUT_CRC0_CHANNEL4 0x0004
#define ixAZALIA_INPUT_CRC0_CHANNEL5 0x0005
#define ixAZALIA_INPUT_CRC0_CHANNEL6 0x0006
#define ixAZALIA_INPUT_CRC0_CHANNEL7 0x0007
// addressBlock: azf0controller_azinputcrc1resultind
// base address: 0x0
#define ixAZALIA_INPUT_CRC1_CHANNEL0 0x0000
#define ixAZALIA_INPUT_CRC1_CHANNEL1 0x0001
#define ixAZALIA_INPUT_CRC1_CHANNEL2 0x0002
#define ixAZALIA_INPUT_CRC1_CHANNEL3 0x0003
#define ixAZALIA_INPUT_CRC1_CHANNEL4 0x0004
#define ixAZALIA_INPUT_CRC1_CHANNEL5 0x0005
#define ixAZALIA_INPUT_CRC1_CHANNEL6 0x0006
#define ixAZALIA_INPUT_CRC1_CHANNEL7 0x0007
// addressBlock: azf0controller_azcrc0resultind
// base address: 0x0
#define ixAZALIA_CRC0_CHANNEL0 0x0000
#define ixAZALIA_CRC0_CHANNEL1 0x0001
#define ixAZALIA_CRC0_CHANNEL2 0x0002
#define ixAZALIA_CRC0_CHANNEL3 0x0003
#define ixAZALIA_CRC0_CHANNEL4 0x0004
#define ixAZALIA_CRC0_CHANNEL5 0x0005
#define ixAZALIA_CRC0_CHANNEL6 0x0006
#define ixAZALIA_CRC0_CHANNEL7 0x0007
// addressBlock: azf0controller_azcrc1resultind
// base address: 0x0
#define ixAZALIA_CRC1_CHANNEL0 0x0000
#define ixAZALIA_CRC1_CHANNEL1 0x0001
#define ixAZALIA_CRC1_CHANNEL2 0x0002
#define ixAZALIA_CRC1_CHANNEL3 0x0003
#define ixAZALIA_CRC1_CHANNEL4 0x0004
#define ixAZALIA_CRC1_CHANNEL5 0x0005
#define ixAZALIA_CRC1_CHANNEL6 0x0006
#define ixAZALIA_CRC1_CHANNEL7 0x0007
// addressBlock: azinputendpoint_f2codecind
// base address: 0x0
#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x6200
#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x6706
#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x670d
#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x6f09
#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x6f0a
#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x6f0b
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x7707
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x7708
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE 0x7709
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x771c
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2 0x771d
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3 0x771e
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4 0x771f
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x7771
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE 0x7777
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE 0x7778
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE 0x7779
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE 0x777a
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR 0x777c
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE 0x7785
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE 0x7786
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE 0x7787
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE 0x7788
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x7798
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB 0x7799
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x779a
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x779b
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x779c
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L 0x779d
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H 0x779e
#define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x7f09
#define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x7f0c
// addressBlock: azroot_f2codecind
// base address: 0x0
#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID 0x0f00
#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID 0x0f02
#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT 0x0f04
#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE 0x1705
#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID 0x1720
#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2 0x1721
#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3 0x1722
#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4 0x1723
#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION 0x1770
#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESET 0x17ff
#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT 0x1f04
#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE 0x1f05
#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES 0x1f0a
#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS 0x1f0b
#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES 0x1f0f
// addressBlock: azf0stream0_streamind
// base address: 0x0
#define ixAZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL 0x0000
#define ixAZF0STREAM0_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
#define ixAZF0STREAM0_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
#define ixAZF0STREAM0_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
#define ixAZF0STREAM0_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
// addressBlock: azf0stream1_streamind
// base address: 0x0
#define ixAZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL 0x0000
#define ixAZF0STREAM1_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
#define ixAZF0STREAM1_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
#define ixAZF0STREAM1_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
#define ixAZF0STREAM1_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
// addressBlock: azf0stream2_streamind
// base address: 0x0
#define ixAZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL 0x0000
#define ixAZF0STREAM2_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
#define ixAZF0STREAM2_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
#define ixAZF0STREAM2_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
#define ixAZF0STREAM2_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
// addressBlock: azf0stream3_streamind
// base address: 0x0
#define ixAZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL 0x0000
#define ixAZF0STREAM3_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
#define ixAZF0STREAM3_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
#define ixAZF0STREAM3_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
#define ixAZF0STREAM3_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
// addressBlock: azf0stream4_streamind
// base address: 0x0
#define ixAZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL 0x0000
#define ixAZF0STREAM4_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
#define ixAZF0STREAM4_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
#define ixAZF0STREAM4_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
#define ixAZF0STREAM4_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
// addressBlock: azf0stream5_streamind
// base address: 0x0
#define ixAZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL 0x0000
#define ixAZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
#define ixAZF0STREAM5_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
#define ixAZF0STREAM5_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
#define ixAZF0STREAM5_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
// addressBlock: azf0stream6_streamind
// base address: 0x0
#define ixAZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL 0x0000
#define ixAZF0STREAM6_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
#define ixAZF0STREAM6_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
#define ixAZF0STREAM6_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
#define ixAZF0STREAM6_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
// addressBlock: azf0stream7_streamind
// base address: 0x0
#define ixAZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL 0x0000
#define ixAZF0STREAM7_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
#define ixAZF0STREAM7_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
#define ixAZF0STREAM7_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
#define ixAZF0STREAM7_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
// addressBlock: azf0stream8_streamind
// base address: 0x0
#define ixAZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL 0x0000
#define ixAZF0STREAM8_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
#define ixAZF0STREAM8_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
#define ixAZF0STREAM8_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
#define ixAZF0STREAM8_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
// addressBlock: azf0stream9_streamind
// base address: 0x0
#define ixAZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL 0x0000
#define ixAZF0STREAM9_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
#define ixAZF0STREAM9_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
#define ixAZF0STREAM9_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
#define ixAZF0STREAM9_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
// addressBlock: azf0stream10_streamind
// base address: 0x0
#define ixAZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL 0x0000
#define ixAZF0STREAM10_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
#define ixAZF0STREAM10_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
#define ixAZF0STREAM10_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
#define ixAZF0STREAM10_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
// addressBlock: azf0stream11_streamind
// base address: 0x0
#define ixAZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL 0x0000
#define ixAZF0STREAM11_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
#define ixAZF0STREAM11_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
#define ixAZF0STREAM11_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
#define ixAZF0STREAM11_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
// addressBlock: azf0stream12_streamind
// base address: 0x0
#define ixAZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL 0x0000
#define ixAZF0STREAM12_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
#define ixAZF0STREAM12_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
#define ixAZF0STREAM12_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
#define ixAZF0STREAM12_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
// addressBlock: azf0stream13_streamind
// base address: 0x0
#define ixAZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL 0x0000
#define ixAZF0STREAM13_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
#define ixAZF0STREAM13_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
#define ixAZF0STREAM13_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
#define ixAZF0STREAM13_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
// addressBlock: azf0stream14_streamind
// base address: 0x0
#define ixAZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL 0x0000
#define ixAZF0STREAM14_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
#define ixAZF0STREAM14_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
#define ixAZF0STREAM14_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
#define ixAZF0STREAM14_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
// addressBlock: azf0stream15_streamind
// base address: 0x0
#define ixAZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL 0x0000
#define ixAZF0STREAM15_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
#define ixAZF0STREAM15_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
#define ixAZF0STREAM15_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
#define ixAZF0STREAM15_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
// addressBlock: azf0endpoint0_endpointind
// base address: 0x0
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058
#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059
#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a
#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b
#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c
#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d
#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e
#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f
#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060
#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a
#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b
#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c
#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d
#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e
// addressBlock: azf0endpoint1_endpointind
// base address: 0x0
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058
#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059
#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a
#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b
#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c
#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d
#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e
#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f
#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060
#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a
#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b
#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c
#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d
#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e
// addressBlock: azf0endpoint2_endpointind
// base address: 0x0
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058
#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059
#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a
#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b
#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c
#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d
#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e
#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f
#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060
#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a
#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b
#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c
#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d
#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e
// addressBlock: azf0endpoint3_endpointind
// base address: 0x0
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058
#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059
#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a
#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b
#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c
#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d
#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e
#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f
#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060
#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a
#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b
#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c
#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d
#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e
// addressBlock: azf0endpoint4_endpointind
// base address: 0x0
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058
#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059
#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a
#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b
#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c
#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d
#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e
#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f
#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060
#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a
#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b
#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c
#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d
#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e
// addressBlock: azf0endpoint5_endpointind
// base address: 0x0
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058
#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059
#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a
#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b
#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c
#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d
#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e
#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f
#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060
#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a
#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b
#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c
#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d
#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e
// addressBlock: azf0endpoint6_endpointind
// base address: 0x0
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058
#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059
#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a
#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b
#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c
#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d
#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e
#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f
#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060
#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a
#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b
#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c
#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d
#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e
// addressBlock: azf0endpoint7_endpointind
// base address: 0x0
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058
#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059
#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a
#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b
#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c
#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d
#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e
#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f
#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060
#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a
#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b
#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c
#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d
#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e
// addressBlock: azf0inputendpoint0_inputendpointind
// base address: 0x0
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068
// addressBlock: azf0inputendpoint1_inputendpointind
// base address: 0x0
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068
// addressBlock: azf0inputendpoint2_inputendpointind
// base address: 0x0
#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021
#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023
#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024
#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037
#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038
#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053
#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065
#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067
#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068
// addressBlock: azf0inputendpoint3_inputendpointind
// base address: 0x0
#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021
#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023
#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024
#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037
#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038
#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053
#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065
#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067
#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068
// addressBlock: azf0inputendpoint4_inputendpointind
// base address: 0x0
#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021
#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023
#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024
#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037
#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038
#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053
#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065
#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067
#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068
// addressBlock: azf0inputendpoint5_inputendpointind
// base address: 0x0
#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021
#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023
#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024
#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037
#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038
#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053
#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065
#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067
#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068
// addressBlock: azf0inputendpoint6_inputendpointind
// base address: 0x0
#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021
#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023
#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024
#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037
#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038
#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053
#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065
#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067
#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068
// addressBlock: azf0inputendpoint7_inputendpointind
// base address: 0x0
#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021
#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023
#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024
#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037
#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038
#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053
#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065
#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067
#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068
#endif
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