/*
* Copyright (C) 2021 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef _dcn_2_0_3_OFFSET_HEADER
#define _dcn_2_0_3_OFFSET_HEADER
// addressBlock: dce_dc_dccg_dccg_dispdec
// base address: 0x0
#define mmPHYPLLA_PIXCLK_RESYNC_CNTL 0x0040
#define mmPHYPLLA_PIXCLK_RESYNC_CNTL_BASE_IDX 1
#define mmPHYPLLB_PIXCLK_RESYNC_CNTL 0x0041
#define mmPHYPLLB_PIXCLK_RESYNC_CNTL_BASE_IDX 1
#define mmDP_DTO_DBUF_EN 0x0044
#define mmDP_DTO_DBUF_EN_BASE_IDX 1
#define mmDPREFCLK_CGTT_BLK_CTRL_REG 0x0048
#define mmDPREFCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1
#define mmREFCLK_CNTL 0x0049
#define mmREFCLK_CNTL_BASE_IDX 1
#define mmREFCLK_CGTT_BLK_CTRL_REG 0x004b
#define mmREFCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1
#define mmDCCG_PERFMON_CNTL2 0x004e
#define mmDCCG_PERFMON_CNTL2_BASE_IDX 1
#define mmDCCG_DS_DTO_INCR 0x0053
#define mmDCCG_DS_DTO_INCR_BASE_IDX 1
#define mmDCCG_DS_DTO_MODULO 0x0054
#define mmDCCG_DS_DTO_MODULO_BASE_IDX 1
#define mmDCCG_DS_CNTL 0x0055
#define mmDCCG_DS_CNTL_BASE_IDX 1
#define mmDCCG_DS_HW_CAL_INTERVAL 0x0056
#define mmDCCG_DS_HW_CAL_INTERVAL_BASE_IDX 1
#define mmDPREFCLK_CNTL 0x0058
#define mmDPREFCLK_CNTL_BASE_IDX 1
#define mmDCE_VERSION 0x005e
#define mmDCE_VERSION_BASE_IDX 1
#define mmDCCG_GTC_CNTL 0x0060
#define mmDCCG_GTC_CNTL_BASE_IDX 1
#define mmDCCG_GTC_DTO_INCR 0x0061
#define mmDCCG_GTC_DTO_INCR_BASE_IDX 1
#define mmDCCG_GTC_DTO_MODULO 0x0062
#define mmDCCG_GTC_DTO_MODULO_BASE_IDX 1
#define mmDCCG_GTC_CURRENT 0x0063
#define mmDCCG_GTC_CURRENT_BASE_IDX 1
#define mmDSCCLK0_DTO_PARAM 0x006c
#define mmDSCCLK0_DTO_PARAM_BASE_IDX 1
#define mmMILLISECOND_TIME_BASE_DIV 0x0070
#define mmMILLISECOND_TIME_BASE_DIV_BASE_IDX 1
#define mmDISPCLK_FREQ_CHANGE_CNTL 0x0071
#define mmDISPCLK_FREQ_CHANGE_CNTL_BASE_IDX 1
#define mmDC_MEM_GLOBAL_PWR_REQ_CNTL 0x0072
#define mmDC_MEM_GLOBAL_PWR_REQ_CNTL_BASE_IDX 1
#define mmDCCG_PERFMON_CNTL 0x0073
#define mmDCCG_PERFMON_CNTL_BASE_IDX 1
#define mmDCCG_GATE_DISABLE_CNTL 0x0074
#define mmDCCG_GATE_DISABLE_CNTL_BASE_IDX 1
#define mmDISPCLK_CGTT_BLK_CTRL_REG 0x0075
#define mmDISPCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1
#define mmSOCCLK_CGTT_BLK_CTRL_REG 0x0076
#define mmSOCCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1
#define mmDCCG_CAC_STATUS 0x0077
#define mmDCCG_CAC_STATUS_BASE_IDX 1
#define mmMICROSECOND_TIME_BASE_DIV 0x007b
#define mmMICROSECOND_TIME_BASE_DIV_BASE_IDX 1
#define mmDCCG_GATE_DISABLE_CNTL2 0x007c
#define mmDCCG_GATE_DISABLE_CNTL2_BASE_IDX 1
#define mmSYMCLK_CGTT_BLK_CTRL_REG 0x007d
#define mmSYMCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1
#define mmDCCG_DISP_CNTL_REG 0x007f
#define mmDCCG_DISP_CNTL_REG_BASE_IDX 1
#define mmOTG0_PIXEL_RATE_CNTL 0x0080
#define mmOTG0_PIXEL_RATE_CNTL_BASE_IDX 1
#define mmDP_DTO0_PHASE 0x0081
#define mmDP_DTO0_PHASE_BASE_IDX 1
#define mmDP_DTO0_MODULO 0x0082
#define mmDP_DTO0_MODULO_BASE_IDX 1
#define mmOTG0_PHYPLL_PIXEL_RATE_CNTL 0x0083
#define mmOTG0_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1
#define mmOTG1_PIXEL_RATE_CNTL 0x0084
#define mmOTG1_PIXEL_RATE_CNTL_BASE_IDX 1
#define mmDP_DTO1_PHASE 0x0085
#define mmDP_DTO1_PHASE_BASE_IDX 1
#define mmDP_DTO1_MODULO 0x0086
#define mmDP_DTO1_MODULO_BASE_IDX 1
#define mmOTG1_PHYPLL_PIXEL_RATE_CNTL 0x0087
#define mmOTG1_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1
#define mmDPPCLK_CGTT_BLK_CTRL_REG 0x0098
#define mmDPPCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1
#define mmDPPCLK0_DTO_PARAM 0x0099
#define mmDPPCLK0_DTO_PARAM_BASE_IDX 1
#define mmDPPCLK1_DTO_PARAM 0x009a
#define mmDPPCLK1_DTO_PARAM_BASE_IDX 1
#define mmDPPCLK2_DTO_PARAM 0x009b
#define mmDPPCLK2_DTO_PARAM_BASE_IDX 1
#define mmDPPCLK3_DTO_PARAM 0x009c
#define mmDPPCLK3_DTO_PARAM_BASE_IDX 1
#define mmDCCG_CAC_STATUS2 0x009f
#define mmDCCG_CAC_STATUS2_BASE_IDX 1
#define mmSYMCLKA_CLOCK_ENABLE 0x00a0
#define mmSYMCLKA_CLOCK_ENABLE_BASE_IDX 1
#define mmSYMCLKB_CLOCK_ENABLE 0x00a1
#define mmSYMCLKB_CLOCK_ENABLE_BASE_IDX 1
#define mmDCCG_SOFT_RESET 0x00a6
#define mmDCCG_SOFT_RESET_BASE_IDX 1
#define mmDSCCLK_DTO_CTRL 0x00a7
#define mmDSCCLK_DTO_CTRL_BASE_IDX 1
#define mmDCCG_AUDIO_DTO_SOURCE 0x00ab
#define mmDCCG_AUDIO_DTO_SOURCE_BASE_IDX 1
#define mmDCCG_AUDIO_DTO0_PHASE 0x00ac
#define mmDCCG_AUDIO_DTO0_PHASE_BASE_IDX 1
#define mmDCCG_AUDIO_DTO0_MODULE 0x00ad
#define mmDCCG_AUDIO_DTO0_MODULE_BASE_IDX 1
#define mmDCCG_AUDIO_DTO1_PHASE 0x00ae
#define mmDCCG_AUDIO_DTO1_PHASE_BASE_IDX 1
#define mmDCCG_AUDIO_DTO1_MODULE 0x00af
#define mmDCCG_AUDIO_DTO1_MODULE_BASE_IDX 1
#define mmDCCG_VSYNC_OTG0_LATCH_VALUE 0x00b0
#define mmDCCG_VSYNC_OTG0_LATCH_VALUE_BASE_IDX 1
#define mmDCCG_VSYNC_OTG1_LATCH_VALUE 0x00b1
#define mmDCCG_VSYNC_OTG1_LATCH_VALUE_BASE_IDX 1
#define mmDCCG_VSYNC_OTG2_LATCH_VALUE 0x00b2
#define mmDCCG_VSYNC_OTG2_LATCH_VALUE_BASE_IDX 1
#define mmDCCG_VSYNC_OTG3_LATCH_VALUE 0x00b3
#define mmDCCG_VSYNC_OTG3_LATCH_VALUE_BASE_IDX 1
#define mmDCCG_VSYNC_OTG4_LATCH_VALUE 0x00b4
#define mmDCCG_VSYNC_OTG4_LATCH_VALUE_BASE_IDX 1
#define mmDCCG_VSYNC_OTG5_LATCH_VALUE 0x00b5
#define mmDCCG_VSYNC_OTG5_LATCH_VALUE_BASE_IDX 1
#define mmDPPCLK_DTO_CTRL 0x00b6
#define mmDPPCLK_DTO_CTRL_BASE_IDX 1
#define mmDCCG_VSYNC_CNT_CTRL 0x00b8
#define mmDCCG_VSYNC_CNT_CTRL_BASE_IDX 1
#define mmDCCG_VSYNC_CNT_INT_CTRL 0x00b9
#define mmDCCG_VSYNC_CNT_INT_CTRL_BASE_IDX 1
// addressBlock: dce_dc_dccg_dccg_dfs_dispdec
// base address: 0x0
#define mmDENTIST_DISPCLK_CNTL 0x0064
#define mmDENTIST_DISPCLK_CNTL_BASE_IDX 1
// addressBlock: dce_dc_dmu_rbbmif_dispdec
// base address: 0x0
#define mmRBBMIF_TIMEOUT 0x005b
#define mmRBBMIF_TIMEOUT_BASE_IDX 2
#define mmRBBMIF_STATUS 0x005c
#define mmRBBMIF_STATUS_BASE_IDX 2
#define mmRBBMIF_STATUS_2 0x005d
#define mmRBBMIF_STATUS_2_BASE_IDX 2
#define mmRBBMIF_INT_STATUS 0x005e
#define mmRBBMIF_INT_STATUS_BASE_IDX 2
#define mmRBBMIF_TIMEOUT_DIS 0x005f
#define mmRBBMIF_TIMEOUT_DIS_BASE_IDX 2
#define mmRBBMIF_TIMEOUT_DIS_2 0x0060
#define mmRBBMIF_TIMEOUT_DIS_2_BASE_IDX 2
#define mmRBBMIF_STATUS_FLAG 0x0061
#define mmRBBMIF_STATUS_FLAG_BASE_IDX 2
// addressBlock: dce_dc_hda_az_misc_dispdec
// base address: 0x0
#define mmAZ_CLOCK_CNTL 0x0372
#define mmAZ_CLOCK_CNTL_BASE_IDX 2
// addressBlock: dce_dc_hda_azf0endpoint0_dispdec
// base address: 0x0
#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x0386
#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2
#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA 0x0387
#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2
// addressBlock: dce_dc_hda_azf0endpoint1_dispdec
// base address: 0x18
#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x038c
#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2
#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA 0x038d
#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2
// addressBlock: dce_dc_hda_azf0controller_dispdec
// base address: 0x0
#define mmAZALIA_CONTROLLER_CLOCK_GATING 0x03c2
#define mmAZALIA_CONTROLLER_CLOCK_GATING_BASE_IDX 2
#define mmAZALIA_AUDIO_DTO 0x03c3
#define mmAZALIA_AUDIO_DTO_BASE_IDX 2
#define mmAZALIA_AUDIO_DTO_CONTROL 0x03c4
#define mmAZALIA_AUDIO_DTO_CONTROL_BASE_IDX 2
#define mmAZALIA_SOCCLK_CONTROL 0x03c5
#define mmAZALIA_SOCCLK_CONTROL_BASE_IDX 2
#define mmAZALIA_UNDERFLOW_FILLER_SAMPLE 0x03c6
#define mmAZALIA_UNDERFLOW_FILLER_SAMPLE_BASE_IDX 2
#define mmAZALIA_DATA_DMA_CONTROL 0x03c7
#define mmAZALIA_DATA_DMA_CONTROL_BASE_IDX 2
#define mmAZALIA_BDL_DMA_CONTROL 0x03c8
#define mmAZALIA_BDL_DMA_CONTROL_BASE_IDX 2
#define mmAZALIA_RIRB_AND_DP_CONTROL 0x03c9
#define mmAZALIA_RIRB_AND_DP_CONTROL_BASE_IDX 2
#define mmAZALIA_CORB_DMA_CONTROL 0x03ca
#define mmAZALIA_CORB_DMA_CONTROL_BASE_IDX 2
#define mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER 0x03d1
#define mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER_BASE_IDX 2
#define mmAZALIA_CYCLIC_BUFFER_SYNC 0x03d2
#define mmAZALIA_CYCLIC_BUFFER_SYNC_BASE_IDX 2
#define mmAZALIA_GLOBAL_CAPABILITIES 0x03d3
#define mmAZALIA_GLOBAL_CAPABILITIES_BASE_IDX 2
#define mmAZALIA_OUTPUT_PAYLOAD_CAPABILITY 0x03d4
#define mmAZALIA_OUTPUT_PAYLOAD_CAPABILITY_BASE_IDX 2
#define mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL 0x03d5
#define mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL_BASE_IDX 2
#define mmAZALIA_INPUT_PAYLOAD_CAPABILITY 0x03d6
#define mmAZALIA_INPUT_PAYLOAD_CAPABILITY_BASE_IDX 2
#define mmAZALIA_INPUT_CRC0_CONTROL0 0x03d9
#define mmAZALIA_INPUT_CRC0_CONTROL0_BASE_IDX 2
#define mmAZALIA_INPUT_CRC0_CONTROL1 0x03da
#define mmAZALIA_INPUT_CRC0_CONTROL1_BASE_IDX 2
#define mmAZALIA_INPUT_CRC0_CONTROL2 0x03db
#define mmAZALIA_INPUT_CRC0_CONTROL2_BASE_IDX 2
#define mmAZALIA_INPUT_CRC0_CONTROL3 0x03dc
#define mmAZALIA_INPUT_CRC0_CONTROL3_BASE_IDX 2
#define mmAZALIA_INPUT_CRC0_RESULT 0x03dd
#define mmAZALIA_INPUT_CRC0_RESULT_BASE_IDX 2
#define mmAZALIA_INPUT_CRC1_CONTROL0 0x03de
#define mmAZALIA_INPUT_CRC1_CONTROL0_BASE_IDX 2
#define mmAZALIA_INPUT_CRC1_CONTROL1 0x03df
#define mmAZALIA_INPUT_CRC1_CONTROL1_BASE_IDX 2
#define mmAZALIA_INPUT_CRC1_CONTROL2 0x03e0
#define mmAZALIA_INPUT_CRC1_CONTROL2_BASE_IDX 2
#define mmAZALIA_INPUT_CRC1_CONTROL3 0x03e1
#define mmAZALIA_INPUT_CRC1_CONTROL3_BASE_IDX 2
#define mmAZALIA_INPUT_CRC1_RESULT 0x03e2
#define mmAZALIA_INPUT_CRC1_RESULT_BASE_IDX 2
#define mmAZALIA_MEM_PWR_CTRL 0x03ee
#define mmAZALIA_MEM_PWR_CTRL_BASE_IDX 2
#define mmAZALIA_MEM_PWR_STATUS 0x03ef
#define mmAZALIA_MEM_PWR_STATUS_BASE_IDX 2
// addressBlock: dce_dc_hda_azf0root_dispdec
// base address: 0x0
#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID 0x0406
#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_BASE_IDX 2
#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID 0x0407
#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID_BASE_IDX 2
#define mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL 0x0408
#define mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL_BASE_IDX 2
#define mmAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL 0x0409
#define mmAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL_BASE_IDX 2
#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE 0x040a
#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_BASE_IDX 2
#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES 0x040b
#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES_BASE_IDX 2
#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS 0x040c
#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_BASE_IDX 2
#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES 0x040d
#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES_BASE_IDX 2
#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE 0x040e
#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE_BASE_IDX 2
#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET 0x040f
#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET_BASE_IDX 2
#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID 0x0410
#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_BASE_IDX 2
#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION 0x0411
#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION_BASE_IDX 2
#define mmREG_DC_AUDIO_PORT_CONNECTIVITY 0x041c
#define mmREG_DC_AUDIO_PORT_CONNECTIVITY_BASE_IDX 2
#define mmREG_DC_AUDIO_INPUT_PORT_CONNECTIVITY 0x041d
#define mmREG_DC_AUDIO_INPUT_PORT_CONNECTIVITY_BASE_IDX 2
// addressBlock: dce_dc_hda_azf0inputendpoint0_dispdec
// base address: 0x0
#define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x043a
#define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2
#define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x043b
#define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2
// addressBlock: dce_dc_hda_azf0inputendpoint1_dispdec
// base address: 0x10
#define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x043e
#define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2
#define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x043f
#define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2
// addressBlock: dce_dc_dchubbub_hubbub_ret_path_dispdec
// base address: 0x0
#define mmDCHUBBUB_RET_PATH_DCC_CFG 0x04cf
#define mmDCHUBBUB_RET_PATH_DCC_CFG_BASE_IDX 2
#define mmDCHUBBUB_RET_PATH_DCC_CFG0_0 0x04d0
#define mmDCHUBBUB_RET_PATH_DCC_CFG0_0_BASE_IDX 2
#define mmDCHUBBUB_RET_PATH_DCC_CFG0_1 0x04d1
#define mmDCHUBBUB_RET_PATH_DCC_CFG0_1_BASE_IDX 2
#define mmDCHUBBUB_RET_PATH_DCC_CFG1_0 0x04d2
#define mmDCHUBBUB_RET_PATH_DCC_CFG1_0_BASE_IDX 2
#define mmDCHUBBUB_RET_PATH_DCC_CFG1_1 0x04d3
#define mmDCHUBBUB_RET_PATH_DCC_CFG1_1_BASE_IDX 2
#define mmDCHUBBUB_RET_PATH_DCC_CFG2_0 0x04d4
#define mmDCHUBBUB_RET_PATH_DCC_CFG2_0_BASE_IDX 2
#define mmDCHUBBUB_RET_PATH_DCC_CFG2_1 0x04d5
#define mmDCHUBBUB_RET_PATH_DCC_CFG2_1_BASE_IDX 2
#define mmDCHUBBUB_RET_PATH_DCC_CFG3_0 0x04d6
#define mmDCHUBBUB_RET_PATH_DCC_CFG3_0_BASE_IDX 2
#define mmDCHUBBUB_RET_PATH_DCC_CFG3_1 0x04d7
#define mmDCHUBBUB_RET_PATH_DCC_CFG3_1_BASE_IDX 2
#define mmDCHUBBUB_RET_PATH_DCC_CFG4_0 0x04d8
#define mmDCHUBBUB_RET_PATH_DCC_CFG4_0_BASE_IDX 2
#define mmDCHUBBUB_RET_PATH_DCC_CFG4_1 0x04d9
#define mmDCHUBBUB_RET_PATH_DCC_CFG4_1_BASE_IDX 2
#define mmDCHUBBUB_RET_PATH_DCC_CFG5_0 0x04da
#define mmDCHUBBUB_RET_PATH_DCC_CFG5_0_BASE_IDX 2
#define mmDCHUBBUB_RET_PATH_DCC_CFG5_1 0x04db
#define mmDCHUBBUB_RET_PATH_DCC_CFG5_1_BASE_IDX 2
#define mmDCHUBBUB_RET_PATH_DCC_CFG6_0 0x04dc
#define mmDCHUBBUB_RET_PATH_DCC_CFG6_0_BASE_IDX 2
#define mmDCHUBBUB_RET_PATH_DCC_CFG6_1 0x04dd
#define mmDCHUBBUB_RET_PATH_DCC_CFG6_1_BASE_IDX 2
#define mmDCHUBBUB_RET_PATH_DCC_CFG7_0 0x04de
#define mmDCHUBBUB_RET_PATH_DCC_CFG7_0_BASE_IDX 2
#define mmDCHUBBUB_RET_PATH_DCC_CFG7_1 0x04df
#define mmDCHUBBUB_RET_PATH_DCC_CFG7_1_BASE_IDX 2
#define mmDCHUBBUB_RET_PATH_MEM_PWR_CTRL 0x04ef
#define mmDCHUBBUB_RET_PATH_MEM_PWR_CTRL_BASE_IDX 2
#define mmDCHUBBUB_RET_PATH_MEM_PWR_STATUS 0x04f0
#define mmDCHUBBUB_RET_PATH_MEM_PWR_STATUS_BASE_IDX 2
#define mmDCHUBBUB_CRC_CTRL 0x04f1
#define mmDCHUBBUB_CRC_CTRL_BASE_IDX 2
#define mmDCHUBBUB_CRC0_VAL_R_G 0x04f2
#define mmDCHUBBUB_CRC0_VAL_R_G_BASE_IDX 2
#define mmDCHUBBUB_CRC0_VAL_B_A 0x04f3
#define mmDCHUBBUB_CRC0_VAL_B_A_BASE_IDX 2
#define mmDCHUBBUB_CRC1_VAL_R_G 0x04f4
#define mmDCHUBBUB_CRC1_VAL_R_G_BASE_IDX 2
#define mmDCHUBBUB_CRC1_VAL_B_A 0x04f5
#define mmDCHUBBUB_CRC1_VAL_B_A_BASE_IDX 2
// addressBlock: dce_dc_dchubbub_hubbub_dispdec
// base address: 0x0
#define mmDCHUBBUB_ARB_DF_REQ_OUTSTAND 0x0505
#define mmDCHUBBUB_ARB_DF_REQ_OUTSTAND_BASE_IDX 2
#define mmDCHUBBUB_ARB_SAT_LEVEL 0x0506
#define mmDCHUBBUB_ARB_SAT_LEVEL_BASE_IDX 2
#define mmDCHUBBUB_ARB_QOS_FORCE 0x0507
#define mmDCHUBBUB_ARB_QOS_FORCE_BASE_IDX 2
#define mmDCHUBBUB_ARB_DRAM_STATE_CNTL 0x0508
#define mmDCHUBBUB_ARB_DRAM_STATE_CNTL_BASE_IDX 2
#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A 0x0509
#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A_BASE_IDX 2
#define mmDCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A 0x050a
#define mmDCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A_BASE_IDX 2
#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A 0x050d
#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A_BASE_IDX 2
#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B 0x050e
#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B_BASE_IDX 2
#define mmDCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B 0x050f
#define mmDCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B_BASE_IDX 2
#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B 0x0512
#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B_BASE_IDX 2
#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C 0x0513
#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C_BASE_IDX 2
#define mmDCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C 0x0514
#define mmDCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C_BASE_IDX 2
#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C 0x0517
#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C_BASE_IDX 2
#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D 0x0518
#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D_BASE_IDX 2
#define mmDCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D 0x0519
#define mmDCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D_BASE_IDX 2
#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D 0x051c
#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D_BASE_IDX 2
#define mmDCHUBBUB_ARB_WATERMARK_CHANGE_CNTL 0x051d
#define mmDCHUBBUB_ARB_WATERMARK_CHANGE_CNTL_BASE_IDX 2
#define mmDCHUBBUB_ARB_TIMEOUT_ENABLE 0x051e
#define mmDCHUBBUB_ARB_TIMEOUT_ENABLE_BASE_IDX 2
#define mmDCHUBBUB_GLOBAL_TIMER_CNTL 0x051f
#define mmDCHUBBUB_GLOBAL_TIMER_CNTL_BASE_IDX 2
#define mmVTG0_CONTROL 0x0528
#define mmVTG0_CONTROL_BASE_IDX 2
#define mmVTG1_CONTROL 0x0529
#define mmVTG1_CONTROL_BASE_IDX 2
#define mmDCHUBBUB_SOFT_RESET 0x052e
#define mmDCHUBBUB_SOFT_RESET_BASE_IDX 2
#define mmDCHUBBUB_CLOCK_CNTL 0x052f
#define mmDCHUBBUB_CLOCK_CNTL_BASE_IDX 2
#define mmDCFCLK_CNTL 0x0530
#define mmDCFCLK_CNTL_BASE_IDX 2
#define mmDCHUBBUB_VLINE_SNAPSHOT 0x0533
#define mmDCHUBBUB_VLINE_SNAPSHOT_BASE_IDX 2
#define mmDCHUBBUB_CTRL_STATUS 0x0534
#define mmDCHUBBUB_CTRL_STATUS_BASE_IDX 2
#define mmDCHUBBUB_TIMEOUT_DETECTION_CTRL1 0x053a
#define mmDCHUBBUB_TIMEOUT_DETECTION_CTRL1_BASE_IDX 2
#define mmDCHUBBUB_TIMEOUT_DETECTION_CTRL2 0x053b
#define mmDCHUBBUB_TIMEOUT_DETECTION_CTRL2_BASE_IDX 2
#define mmDCHUBBUB_TIMEOUT_INTERRUPT_STATUS 0x053c
#define mmDCHUBBUB_TIMEOUT_INTERRUPT_STATUS_BASE_IDX 2
#define mmDCHUBBUB_TEST_DEBUG_INDEX 0x053d
#define mmDCHUBBUB_TEST_DEBUG_INDEX_BASE_IDX 2
#define mmDCHUBBUB_TEST_DEBUG_DATA 0x053e
#define mmDCHUBBUB_TEST_DEBUG_DATA_BASE_IDX 2
#define mmFMON_CTRL 0x0548
#define mmFMON_CTRL_BASE_IDX 2
// addressBlock: dce_dc_dcbubp0_dispdec_hubp_dispdec
// base address: 0x0
#define mmHUBP0_DCSURF_SURFACE_CONFIG 0x05e5
#define mmHUBP0_DCSURF_SURFACE_CONFIG_BASE_IDX 2
#define mmHUBP0_DCSURF_ADDR_CONFIG 0x05e6
#define mmHUBP0_DCSURF_ADDR_CONFIG_BASE_IDX 2
#define mmHUBP0_DCSURF_TILING_CONFIG 0x05e7
#define mmHUBP0_DCSURF_TILING_CONFIG_BASE_IDX 2
#define mmHUBP0_DCSURF_PRI_VIEWPORT_START 0x05e9
#define mmHUBP0_DCSURF_PRI_VIEWPORT_START_BASE_IDX 2
#define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION 0x05ea
#define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2
#define mmHUBP0_DCSURF_PRI_VIEWPORT_START_C 0x05eb
#define mmHUBP0_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX 2
#define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C 0x05ec
#define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX 2
#define mmHUBP0_DCSURF_SEC_VIEWPORT_START 0x05ed
#define mmHUBP0_DCSURF_SEC_VIEWPORT_START_BASE_IDX 2
#define mmHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION 0x05ee
#define mmHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX 2
#define mmHUBP0_DCSURF_SEC_VIEWPORT_START_C 0x05ef
#define mmHUBP0_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX 2
#define mmHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C 0x05f0
#define mmHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX 2
#define mmHUBP0_DCHUBP_REQ_SIZE_CONFIG 0x05f1
#define mmHUBP0_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX 2
#define mmHUBP0_DCHUBP_REQ_SIZE_CONFIG_C 0x05f2
#define mmHUBP0_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX 2
#define mmHUBP0_DCHUBP_CNTL 0x05f3
#define mmHUBP0_DCHUBP_CNTL_BASE_IDX 2
#define mmHUBP0_HUBP_CLK_CNTL 0x05f4
#define mmHUBP0_HUBP_CLK_CNTL_BASE_IDX 2
#define mmHUBP0_HUBPREQ_DEBUG_DB 0x05f6
#define mmHUBP0_HUBPREQ_DEBUG_DB_BASE_IDX 2
#define mmHUBP0_HUBPREQ_DEBUG 0x05f7
#define mmHUBP0_HUBPREQ_DEBUG_BASE_IDX 2
#define mmHUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK 0x05fb
#define mmHUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX 2
#define mmHUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK 0x05fc
#define mmHUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX 2
// addressBlock: dce_dc_dcbubp0_dispdec_hubpreq_dispdec
// base address: 0x0
#define mmHUBPREQ0_DCSURF_SURFACE_PITCH 0x0607
#define mmHUBPREQ0_DCSURF_SURFACE_PITCH_BASE_IDX 2
#define mmHUBPREQ0_DCSURF_SURFACE_PITCH_C 0x0608
#define mmHUBPREQ0_DCSURF_SURFACE_PITCH_C_BASE_IDX 2
#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS 0x060a
#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2
#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0x060b
#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0x060c
#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2
#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x060d
#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS 0x060e
#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2
#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0x060f
#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0x0610
#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2
#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x0611
#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS 0x0612
#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX 2
#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH 0x0613
#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2
#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C 0x0614
#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX 2
#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0x0615
#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS 0x0616
#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX 2
#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH 0x0617
#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2
#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C 0x0618
#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX 2
#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0x0619
#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
#define mmHUBPREQ0_DCSURF_SURFACE_CONTROL 0x061a
#define mmHUBPREQ0_DCSURF_SURFACE_CONTROL_BASE_IDX 2
#define mmHUBPREQ0_DCSURF_FLIP_CONTROL 0x061b
#define mmHUBPREQ0_DCSURF_FLIP_CONTROL_BASE_IDX 2
#define mmHUBPREQ0_DCSURF_FLIP_CONTROL2 0x061c
#define mmHUBPREQ0_DCSURF_FLIP_CONTROL2_BASE_IDX 2
#define mmHUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT 0x0620
#define mmHUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX 2
#define mmHUBPREQ0_DCSURF_SURFACE_INUSE 0x0621
#define mmHUBPREQ0_DCSURF_SURFACE_INUSE_BASE_IDX 2
#define mmHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH 0x0622
#define mmHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX 2
#define mmHUBPREQ0_DCSURF_SURFACE_INUSE_C 0x0623
#define mmHUBPREQ0_DCSURF_SURFACE_INUSE_C_BASE_IDX 2
#define mmHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C 0x0624
#define mmHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX 2
#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE 0x0625
#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX 2
#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0x0626
#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX 2
#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C 0x0627
#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX 2
#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0x0628
#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX 2
#define mmHUBPREQ0_DCN_EXPANSION_MODE 0x062c
#define mmHUBPREQ0_DCN_EXPANSION_MODE_BASE_IDX 2
#define mmHUBPREQ0_DCN_TTU_QOS_WM 0x062d
#define mmHUBPREQ0_DCN_TTU_QOS_WM_BASE_IDX 2
#define mmHUBPREQ0_DCN_GLOBAL_TTU_CNTL 0x062e
#define mmHUBPREQ0_DCN_GLOBAL_TTU_CNTL_BASE_IDX 2
#define mmHUBPREQ0_DCN_SURF0_TTU_CNTL0 0x062f
#define mmHUBPREQ0_DCN_SURF0_TTU_CNTL0_BASE_IDX 2
#define mmHUBPREQ0_DCN_SURF0_TTU_CNTL1 0x0630
#define mmHUBPREQ0_DCN_SURF0_TTU_CNTL1_BASE_IDX 2
#define mmHUBPREQ0_DCN_SURF1_TTU_CNTL0 0x0631
#define mmHUBPREQ0_DCN_SURF1_TTU_CNTL0_BASE_IDX 2
#define mmHUBPREQ0_DCN_SURF1_TTU_CNTL1 0x0632
#define mmHUBPREQ0_DCN_SURF1_TTU_CNTL1_BASE_IDX 2
#define mmHUBPREQ0_DCN_CUR0_TTU_CNTL0 0x0633
#define mmHUBPREQ0_DCN_CUR0_TTU_CNTL0_BASE_IDX 2
#define mmHUBPREQ0_DCN_CUR0_TTU_CNTL1 0x0634
#define mmHUBPREQ0_DCN_CUR0_TTU_CNTL1_BASE_IDX 2
#define mmHUBPREQ0_BLANK_OFFSET_0 0x0646
#define mmHUBPREQ0_BLANK_OFFSET_0_BASE_IDX 2
#define mmHUBPREQ0_BLANK_OFFSET_1 0x0647
#define mmHUBPREQ0_BLANK_OFFSET_1_BASE_IDX 2
#define mmHUBPREQ0_DST_DIMENSIONS 0x0648
#define mmHUBPREQ0_DST_DIMENSIONS_BASE_IDX 2
#define mmHUBPREQ0_DST_AFTER_SCALER 0x0649
#define mmHUBPREQ0_DST_AFTER_SCALER_BASE_IDX 2
#define mmHUBPREQ0_PREFETCH_SETTINGS 0x064a
#define mmHUBPREQ0_PREFETCH_SETTINGS_BASE_IDX 2
#define mmHUBPREQ0_PREFETCH_SETTINGS_C 0x064b
#define mmHUBPREQ0_PREFETCH_SETTINGS_C_BASE_IDX 2
#define mmHUBPREQ0_VBLANK_PARAMETERS_0 0x064c
#define mmHUBPREQ0_VBLANK_PARAMETERS_0_BASE_IDX 2
#define mmHUBPREQ0_VBLANK_PARAMETERS_1 0x064d
#define mmHUBPREQ0_VBLANK_PARAMETERS_1_BASE_IDX 2
#define mmHUBPREQ0_VBLANK_PARAMETERS_2 0x064e
#define mmHUBPREQ0_VBLANK_PARAMETERS_2_BASE_IDX 2
#define mmHUBPREQ0_VBLANK_PARAMETERS_3 0x064f
#define mmHUBPREQ0_VBLANK_PARAMETERS_3_BASE_IDX 2
#define mmHUBPREQ0_VBLANK_PARAMETERS_4 0x0650
#define mmHUBPREQ0_VBLANK_PARAMETERS_4_BASE_IDX 2
#define mmHUBPREQ0_FLIP_PARAMETERS_0 0x0651
#define mmHUBPREQ0_FLIP_PARAMETERS_0_BASE_IDX 2
#define mmHUBPREQ0_FLIP_PARAMETERS_2 0x0653
#define mmHUBPREQ0_FLIP_PARAMETERS_2_BASE_IDX 2
#define mmHUBPREQ0_NOM_PARAMETERS_4 0x0658
#define mmHUBPREQ0_NOM_PARAMETERS_4_BASE_IDX 2
#define mmHUBPREQ0_NOM_PARAMETERS_5 0x0659
#define mmHUBPREQ0_NOM_PARAMETERS_5_BASE_IDX 2
#define mmHUBPREQ0_NOM_PARAMETERS_6 0x065a
#define mmHUBPREQ0_NOM_PARAMETERS_6_BASE_IDX 2
#define mmHUBPREQ0_NOM_PARAMETERS_7 0x065b
#define mmHUBPREQ0_NOM_PARAMETERS_7_BASE_IDX 2
#define mmHUBPREQ0_PER_LINE_DELIVERY_PRE 0x065c
#define mmHUBPREQ0_PER_LINE_DELIVERY_PRE_BASE_IDX 2
#define mmHUBPREQ0_PER_LINE_DELIVERY 0x065d
#define mmHUBPREQ0_PER_LINE_DELIVERY_BASE_IDX 2
#define mmHUBPREQ0_CURSOR_SETTINGS 0x065e
#define mmHUBPREQ0_CURSOR_SETTINGS_BASE_IDX 2
#define mmHUBPREQ0_REF_FREQ_TO_PIX_FREQ 0x065f
#define mmHUBPREQ0_REF_FREQ_TO_PIX_FREQ_BASE_IDX 2
#define mmHUBPREQ0_DST_Y_DELTA_DRQ_LIMIT 0x0660
#define mmHUBPREQ0_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX 2
#define mmHUBPREQ0_HUBPREQ_MEM_PWR_CTRL 0x0661
#define mmHUBPREQ0_HUBPREQ_MEM_PWR_CTRL_BASE_IDX 2
#define mmHUBPREQ0_HUBPREQ_MEM_PWR_STATUS 0x0662
#define mmHUBPREQ0_HUBPREQ_MEM_PWR_STATUS_BASE_IDX 2
// addressBlock: dce_dc_dcbubp0_dispdec_hubpret_dispdec
// base address: 0x0
#define mmHUBPRET0_HUBPRET_CONTROL 0x066a
#define mmHUBPRET0_HUBPRET_CONTROL_BASE_IDX 2
#define mmHUBPRET0_HUBPRET_MEM_PWR_CTRL 0x066b
#define mmHUBPRET0_HUBPRET_MEM_PWR_CTRL_BASE_IDX 2
#define mmHUBPRET0_HUBPRET_MEM_PWR_STATUS 0x066c
#define mmHUBPRET0_HUBPRET_MEM_PWR_STATUS_BASE_IDX 2
#define mmHUBPRET0_HUBPRET_READ_LINE_CTRL0 0x066d
#define mmHUBPRET0_HUBPRET_READ_LINE_CTRL0_BASE_IDX 2
#define mmHUBPRET0_HUBPRET_READ_LINE_CTRL1 0x066e
#define mmHUBPRET0_HUBPRET_READ_LINE_CTRL1_BASE_IDX 2
#define mmHUBPRET0_HUBPRET_READ_LINE0 0x066f
#define mmHUBPRET0_HUBPRET_READ_LINE0_BASE_IDX 2
#define mmHUBPRET0_HUBPRET_READ_LINE1 0x0670
#define mmHUBPRET0_HUBPRET_READ_LINE1_BASE_IDX 2
#define mmHUBPRET0_HUBPRET_INTERRUPT 0x0671
#define mmHUBPRET0_HUBPRET_INTERRUPT_BASE_IDX 2
#define mmHUBPRET0_HUBPRET_READ_LINE_VALUE 0x0672
#define mmHUBPRET0_HUBPRET_READ_LINE_VALUE_BASE_IDX 2
#define mmHUBPRET0_HUBPRET_READ_LINE_STATUS 0x0673
#define mmHUBPRET0_HUBPRET_READ_LINE_STATUS_BASE_IDX 2
// addressBlock: dce_dc_dcbubp0_dispdec_cursor0_dispdec
// base address: 0x0
#define mmCURSOR0_0_CURSOR_CONTROL 0x0678
#define mmCURSOR0_0_CURSOR_CONTROL_BASE_IDX 2
#define mmCURSOR0_0_CURSOR_SURFACE_ADDRESS 0x0679
#define mmCURSOR0_0_CURSOR_SURFACE_ADDRESS_BASE_IDX 2
#define mmCURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH 0x067a
#define mmCURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX 2
#define mmCURSOR0_0_CURSOR_SIZE 0x067b
#define mmCURSOR0_0_CURSOR_SIZE_BASE_IDX 2
#define mmCURSOR0_0_CURSOR_POSITION 0x067c
#define mmCURSOR0_0_CURSOR_POSITION_BASE_IDX 2
#define mmCURSOR0_0_CURSOR_HOT_SPOT 0x067d
#define mmCURSOR0_0_CURSOR_HOT_SPOT_BASE_IDX 2
#define mmCURSOR0_0_CURSOR_STEREO_CONTROL 0x067e
#define mmCURSOR0_0_CURSOR_STEREO_CONTROL_BASE_IDX 2
#define mmCURSOR0_0_CURSOR_DST_OFFSET 0x067f
#define mmCURSOR0_0_CURSOR_DST_OFFSET_BASE_IDX 2
#define mmCURSOR0_0_CURSOR_MEM_PWR_CTRL 0x0680
#define mmCURSOR0_0_CURSOR_MEM_PWR_CTRL_BASE_IDX 2
#define mmCURSOR0_0_CURSOR_MEM_PWR_STATUS 0x0681
#define mmCURSOR0_0_CURSOR_MEM_PWR_STATUS_BASE_IDX 2
#define mmCURSOR0_0_DMDATA_ADDRESS_HIGH 0x0682
#define mmCURSOR0_0_DMDATA_ADDRESS_HIGH_BASE_IDX 2
#define mmCURSOR0_0_DMDATA_ADDRESS_LOW 0x0683
#define mmCURSOR0_0_DMDATA_ADDRESS_LOW_BASE_IDX 2
#define mmCURSOR0_0_DMDATA_CNTL 0x0684
#define mmCURSOR0_0_DMDATA_CNTL_BASE_IDX 2
#define mmCURSOR0_0_DMDATA_QOS_CNTL 0x0685
#define mmCURSOR0_0_DMDATA_QOS_CNTL_BASE_IDX 2
#define mmCURSOR0_0_DMDATA_STATUS 0x0686
#define mmCURSOR0_0_DMDATA_STATUS_BASE_IDX 2
#define mmCURSOR0_0_DMDATA_SW_CNTL 0x0687
#define mmCURSOR0_0_DMDATA_SW_CNTL_BASE_IDX 2
#define mmCURSOR0_0_DMDATA_SW_DATA 0x0688
#define mmCURSOR0_0_DMDATA_SW_DATA_BASE_IDX 2
// addressBlock: dce_dc_dcbubp1_dispdec_hubp_dispdec
// base address: 0x370
#define mmHUBP1_DCSURF_SURFACE_CONFIG 0x06c1
#define mmHUBP1_DCSURF_SURFACE_CONFIG_BASE_IDX 2
#define mmHUBP1_DCSURF_ADDR_CONFIG 0x06c2
#define mmHUBP1_DCSURF_ADDR_CONFIG_BASE_IDX 2
#define mmHUBP1_DCSURF_TILING_CONFIG 0x06c3
#define mmHUBP1_DCSURF_TILING_CONFIG_BASE_IDX 2
#define mmHUBP1_DCSURF_PRI_VIEWPORT_START 0x06c5
#define mmHUBP1_DCSURF_PRI_VIEWPORT_START_BASE_IDX 2
#define mmHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION 0x06c6
#define mmHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2
#define mmHUBP1_DCSURF_PRI_VIEWPORT_START_C 0x06c7
#define mmHUBP1_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX 2
#define mmHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C 0x06c8
#define mmHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX 2
#define mmHUBP1_DCSURF_SEC_VIEWPORT_START 0x06c9
#define mmHUBP1_DCSURF_SEC_VIEWPORT_START_BASE_IDX 2
#define mmHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION 0x06ca
#define mmHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX 2
#define mmHUBP1_DCSURF_SEC_VIEWPORT_START_C 0x06cb
#define mmHUBP1_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX 2
#define mmHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C 0x06cc
#define mmHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX 2
#define mmHUBP1_DCHUBP_REQ_SIZE_CONFIG 0x06cd
#define mmHUBP1_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX 2
#define mmHUBP1_DCHUBP_REQ_SIZE_CONFIG_C 0x06ce
#define mmHUBP1_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX 2
#define mmHUBP1_DCHUBP_CNTL 0x06cf
#define mmHUBP1_DCHUBP_CNTL_BASE_IDX 2
#define mmHUBP1_HUBP_CLK_CNTL 0x06d0
#define mmHUBP1_HUBP_CLK_CNTL_BASE_IDX 2
#define mmHUBP1_HUBPREQ_DEBUG_DB 0x06d2
#define mmHUBP1_HUBPREQ_DEBUG_DB_BASE_IDX 2
#define mmHUBP1_HUBPREQ_DEBUG 0x06d3
#define mmHUBP1_HUBPREQ_DEBUG_BASE_IDX 2
#define mmHUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK 0x06d7
#define mmHUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX 2
#define mmHUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK 0x06d8
#define mmHUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX 2
// addressBlock: dce_dc_dcbubp1_dispdec_hubpreq_dispdec
// base address: 0x370
#define mmHUBPREQ1_DCSURF_SURFACE_PITCH 0x06e3
#define mmHUBPREQ1_DCSURF_SURFACE_PITCH_BASE_IDX 2
#define mmHUBPREQ1_DCSURF_SURFACE_PITCH_C 0x06e4
#define mmHUBPREQ1_DCSURF_SURFACE_PITCH_C_BASE_IDX 2
#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS 0x06e6
#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2
#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0x06e7
#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0x06e8
#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2
#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x06e9
#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS 0x06ea
#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2
#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0x06eb
#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0x06ec
#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2
#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x06ed
#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS 0x06ee
#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX 2
#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH 0x06ef
#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2
#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C 0x06f0
#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX 2
#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0x06f1
#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS 0x06f2
#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX 2
#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH 0x06f3
#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2
#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C 0x06f4
#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX 2
#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0x06f5
#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
#define mmHUBPREQ1_DCSURF_SURFACE_CONTROL 0x06f6
#define mmHUBPREQ1_DCSURF_SURFACE_CONTROL_BASE_IDX 2
#define mmHUBPREQ1_DCSURF_FLIP_CONTROL 0x06f7
#define mmHUBPREQ1_DCSURF_FLIP_CONTROL_BASE_IDX 2
#define mmHUBPREQ1_DCSURF_FLIP_CONTROL2 0x06f8
#define mmHUBPREQ1_DCSURF_FLIP_CONTROL2_BASE_IDX 2
#define mmHUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT 0x06fc
#define mmHUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX 2
#define mmHUBPREQ1_DCSURF_SURFACE_INUSE 0x06fd
#define mmHUBPREQ1_DCSURF_SURFACE_INUSE_BASE_IDX 2
#define mmHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH 0x06fe
#define mmHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX 2
#define mmHUBPREQ1_DCSURF_SURFACE_INUSE_C 0x06ff
#define mmHUBPREQ1_DCSURF_SURFACE_INUSE_C_BASE_IDX 2
#define mmHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C 0x0700
#define mmHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX 2
#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE 0x0701
#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX 2
#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0x0702
#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX 2
#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C 0x0703
#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX 2
#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0x0704
#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX 2
#define mmHUBPREQ1_DCN_EXPANSION_MODE 0x0708
#define mmHUBPREQ1_DCN_EXPANSION_MODE_BASE_IDX 2
#define mmHUBPREQ1_DCN_TTU_QOS_WM 0x0709
#define mmHUBPREQ1_DCN_TTU_QOS_WM_BASE_IDX 2
#define mmHUBPREQ1_DCN_GLOBAL_TTU_CNTL 0x070a
#define mmHUBPREQ1_DCN_GLOBAL_TTU_CNTL_BASE_IDX 2
#define mmHUBPREQ1_DCN_SURF0_TTU_CNTL0 0x070b
#define mmHUBPREQ1_DCN_SURF0_TTU_CNTL0_BASE_IDX 2
#define mmHUBPREQ1_DCN_SURF0_TTU_CNTL1 0x070c
#define mmHUBPREQ1_DCN_SURF0_TTU_CNTL1_BASE_IDX 2
#define mmHUBPREQ1_DCN_SURF1_TTU_CNTL0 0x070d
#define mmHUBPREQ1_DCN_SURF1_TTU_CNTL0_BASE_IDX 2
#define mmHUBPREQ1_DCN_SURF1_TTU_CNTL1 0x070e
#define mmHUBPREQ1_DCN_SURF1_TTU_CNTL1_BASE_IDX 2
#define mmHUBPREQ1_DCN_CUR0_TTU_CNTL0 0x070f
#define mmHUBPREQ1_DCN_CUR0_TTU_CNTL0_BASE_IDX 2
#define mmHUBPREQ1_DCN_CUR0_TTU_CNTL1 0x0710
#define mmHUBPREQ1_DCN_CUR0_TTU_CNTL1_BASE_IDX 2
#define mmHUBPREQ1_DCN_CUR1_TTU_CNTL0 0x0711
#define mmHUBPREQ1_DCN_CUR1_TTU_CNTL0_BASE_IDX 2
#define mmHUBPREQ1_DCN_CUR1_TTU_CNTL1 0x0712
#define mmHUBPREQ1_DCN_CUR1_TTU_CNTL1_BASE_IDX 2
#define mmHUBPREQ1_BLANK_OFFSET_0 0x0722
#define mmHUBPREQ1_BLANK_OFFSET_0_BASE_IDX 2
#define mmHUBPREQ1_BLANK_OFFSET_1 0x0723
#define mmHUBPREQ1_BLANK_OFFSET_1_BASE_IDX 2
#define mmHUBPREQ1_DST_DIMENSIONS 0x0724
#define mmHUBPREQ1_DST_DIMENSIONS_BASE_IDX 2
#define mmHUBPREQ1_DST_AFTER_SCALER 0x0725
#define mmHUBPREQ1_DST_AFTER_SCALER_BASE_IDX 2
#define mmHUBPREQ1_PREFETCH_SETTINGS 0x0726
#define mmHUBPREQ1_PREFETCH_SETTINGS_BASE_IDX 2
#define mmHUBPREQ1_PREFETCH_SETTINGS_C 0x0727
#define mmHUBPREQ1_PREFETCH_SETTINGS_C_BASE_IDX 2
#define mmHUBPREQ1_VBLANK_PARAMETERS_0 0x0728
#define mmHUBPREQ1_VBLANK_PARAMETERS_0_BASE_IDX 2
#define mmHUBPREQ1_VBLANK_PARAMETERS_1 0x0729
#define mmHUBPREQ1_VBLANK_PARAMETERS_1_BASE_IDX 2
#define mmHUBPREQ1_VBLANK_PARAMETERS_2 0x072a
#define mmHUBPREQ1_VBLANK_PARAMETERS_2_BASE_IDX 2
#define mmHUBPREQ1_VBLANK_PARAMETERS_3 0x072b
#define mmHUBPREQ1_VBLANK_PARAMETERS_3_BASE_IDX 2
#define mmHUBPREQ1_VBLANK_PARAMETERS_4 0x072c
#define mmHUBPREQ1_VBLANK_PARAMETERS_4_BASE_IDX 2
#define mmHUBPREQ1_FLIP_PARAMETERS_0 0x072d
#define mmHUBPREQ1_FLIP_PARAMETERS_0_BASE_IDX 2
#define mmHUBPREQ1_FLIP_PARAMETERS_2 0x072f
#define mmHUBPREQ1_FLIP_PARAMETERS_2_BASE_IDX 2
#define mmHUBPREQ1_NOM_PARAMETERS_4 0x0734
#define mmHUBPREQ1_NOM_PARAMETERS_4_BASE_IDX 2
#define mmHUBPREQ1_NOM_PARAMETERS_5 0x0735
#define mmHUBPREQ1_NOM_PARAMETERS_5_BASE_IDX 2
#define mmHUBPREQ1_NOM_PARAMETERS_6 0x0736
#define mmHUBPREQ1_NOM_PARAMETERS_6_BASE_IDX 2
#define mmHUBPREQ1_NOM_PARAMETERS_7 0x0737
#define mmHUBPREQ1_NOM_PARAMETERS_7_BASE_IDX 2
#define mmHUBPREQ1_PER_LINE_DELIVERY_PRE 0x0738
#define mmHUBPREQ1_PER_LINE_DELIVERY_PRE_BASE_IDX 2
#define mmHUBPREQ1_PER_LINE_DELIVERY 0x0739
#define mmHUBPREQ1_PER_LINE_DELIVERY_BASE_IDX 2
#define mmHUBPREQ1_CURSOR_SETTINGS 0x073a
#define mmHUBPREQ1_CURSOR_SETTINGS_BASE_IDX 2
#define mmHUBPREQ1_REF_FREQ_TO_PIX_FREQ 0x073b
#define mmHUBPREQ1_REF_FREQ_TO_PIX_FREQ_BASE_IDX 2
#define mmHUBPREQ1_DST_Y_DELTA_DRQ_LIMIT 0x073c
#define mmHUBPREQ1_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX 2
#define mmHUBPREQ1_HUBPREQ_MEM_PWR_CTRL 0x073d
#define mmHUBPREQ1_HUBPREQ_MEM_PWR_CTRL_BASE_IDX 2
#define mmHUBPREQ1_HUBPREQ_MEM_PWR_STATUS 0x073e
#define mmHUBPREQ1_HUBPREQ_MEM_PWR_STATUS_BASE_IDX 2
// addressBlock: dce_dc_dcbubp1_dispdec_hubpret_dispdec
// base address: 0x370
#define mmHUBPRET1_HUBPRET_CONTROL 0x0746
#define mmHUBPRET1_HUBPRET_CONTROL_BASE_IDX 2
#define mmHUBPRET1_HUBPRET_MEM_PWR_CTRL 0x0747
#define mmHUBPRET1_HUBPRET_MEM_PWR_CTRL_BASE_IDX 2
#define mmHUBPRET1_HUBPRET_MEM_PWR_STATUS 0x0748
#define mmHUBPRET1_HUBPRET_MEM_PWR_STATUS_BASE_IDX 2
#define mmHUBPRET1_HUBPRET_READ_LINE_CTRL0 0x0749
#define mmHUBPRET1_HUBPRET_READ_LINE_CTRL0_BASE_IDX 2
#define mmHUBPRET1_HUBPRET_READ_LINE_CTRL1 0x074a
#define mmHUBPRET1_HUBPRET_READ_LINE_CTRL1_BASE_IDX 2
#define mmHUBPRET1_HUBPRET_READ_LINE0 0x074b
#define mmHUBPRET1_HUBPRET_READ_LINE0_BASE_IDX 2
#define mmHUBPRET1_HUBPRET_READ_LINE1 0x074c
#define mmHUBPRET1_HUBPRET_READ_LINE1_BASE_IDX 2
#define mmHUBPRET1_HUBPRET_INTERRUPT 0x074d
#define mmHUBPRET1_HUBPRET_INTERRUPT_BASE_IDX 2
#define mmHUBPRET1_HUBPRET_READ_LINE_VALUE 0x074e
#define mmHUBPRET1_HUBPRET_READ_LINE_VALUE_BASE_IDX 2
#define mmHUBPRET1_HUBPRET_READ_LINE_STATUS 0x074f
#define mmHUBPRET1_HUBPRET_READ_LINE_STATUS_BASE_IDX 2
// addressBlock: dce_dc_dcbubp1_dispdec_cursor0_dispdec
// base address: 0x370
#define mmCURSOR0_1_CURSOR_CONTROL 0x0754
#define mmCURSOR0_1_CURSOR_CONTROL_BASE_IDX 2
#define mmCURSOR0_1_CURSOR_SURFACE_ADDRESS 0x0755
#define mmCURSOR0_1_CURSOR_SURFACE_ADDRESS_BASE_IDX 2
#define mmCURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH 0x0756
#define mmCURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX 2
#define mmCURSOR0_1_CURSOR_SIZE 0x0757
#define mmCURSOR0_1_CURSOR_SIZE_BASE_IDX 2
#define mmCURSOR0_1_CURSOR_POSITION 0x0758
#define mmCURSOR0_1_CURSOR_POSITION_BASE_IDX 2
#define mmCURSOR0_1_CURSOR_HOT_SPOT 0x0759
#define mmCURSOR0_1_CURSOR_HOT_SPOT_BASE_IDX 2
#define mmCURSOR0_1_CURSOR_STEREO_CONTROL 0x075a
#define mmCURSOR0_1_CURSOR_STEREO_CONTROL_BASE_IDX 2
#define mmCURSOR0_1_CURSOR_DST_OFFSET 0x075b
#define mmCURSOR0_1_CURSOR_DST_OFFSET_BASE_IDX 2
#define mmCURSOR0_1_CURSOR_MEM_PWR_CTRL 0x075c
#define mmCURSOR0_1_CURSOR_MEM_PWR_CTRL_BASE_IDX 2
#define mmCURSOR0_1_CURSOR_MEM_PWR_STATUS 0x075d
#define mmCURSOR0_1_CURSOR_MEM_PWR_STATUS_BASE_IDX 2
#define mmCURSOR0_1_DMDATA_ADDRESS_HIGH 0x075e
#define mmCURSOR0_1_DMDATA_ADDRESS_HIGH_BASE_IDX 2
#define mmCURSOR0_1_DMDATA_ADDRESS_LOW 0x075f
#define mmCURSOR0_1_DMDATA_ADDRESS_LOW_BASE_IDX 2
#define mmCURSOR0_1_DMDATA_CNTL 0x0760
#define mmCURSOR0_1_DMDATA_CNTL_BASE_IDX 2
#define mmCURSOR0_1_DMDATA_QOS_CNTL 0x0761
#define mmCURSOR0_1_DMDATA_QOS_CNTL_BASE_IDX 2
#define mmCURSOR0_1_DMDATA_STATUS 0x0762
#define mmCURSOR0_1_DMDATA_STATUS_BASE_IDX 2
#define mmCURSOR0_1_DMDATA_SW_CNTL 0x0763
#define mmCURSOR0_1_DMDATA_SW_CNTL_BASE_IDX 2
#define mmCURSOR0_1_DMDATA_SW_DATA 0x0764
#define mmCURSOR0_1_DMDATA_SW_DATA_BASE_IDX 2
// addressBlock: dce_dc_dcbubp2_dispdec_hubp_dispdec
// base address: 0x6e0
#define mmHUBP2_DCSURF_SURFACE_CONFIG 0x079d
#define mmHUBP2_DCSURF_SURFACE_CONFIG_BASE_IDX 2
#define mmHUBP2_DCSURF_ADDR_CONFIG 0x079e
#define mmHUBP2_DCSURF_ADDR_CONFIG_BASE_IDX 2
#define mmHUBP2_DCSURF_TILING_CONFIG 0x079f
#define mmHUBP2_DCSURF_TILING_CONFIG_BASE_IDX 2
#define mmHUBP2_DCSURF_PRI_VIEWPORT_START 0x07a1
#define mmHUBP2_DCSURF_PRI_VIEWPORT_START_BASE_IDX 2
#define mmHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION 0x07a2
#define mmHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2
#define mmHUBP2_DCSURF_PRI_VIEWPORT_START_C 0x07a3
#define mmHUBP2_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX 2
#define mmHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C 0x07a4
#define mmHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX 2
#define mmHUBP2_DCSURF_SEC_VIEWPORT_START 0x07a5
#define mmHUBP2_DCSURF_SEC_VIEWPORT_START_BASE_IDX 2
#define mmHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION 0x07a6
#define mmHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX 2
#define mmHUBP2_DCSURF_SEC_VIEWPORT_START_C 0x07a7
#define mmHUBP2_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX 2
#define mmHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C 0x07a8
#define mmHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX 2
#define mmHUBP2_DCHUBP_REQ_SIZE_CONFIG 0x07a9
#define mmHUBP2_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX 2
#define mmHUBP2_DCHUBP_REQ_SIZE_CONFIG_C 0x07aa
#define mmHUBP2_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX 2
#define mmHUBP2_DCHUBP_CNTL 0x07ab
#define mmHUBP2_DCHUBP_CNTL_BASE_IDX 2
#define mmHUBP2_HUBP_CLK_CNTL 0x07ac
#define mmHUBP2_HUBP_CLK_CNTL_BASE_IDX 2
#define mmHUBP2_HUBPREQ_DEBUG_DB 0x07ae
#define mmHUBP2_HUBPREQ_DEBUG_DB_BASE_IDX 2
#define mmHUBP2_HUBPREQ_DEBUG 0x07af
#define mmHUBP2_HUBPREQ_DEBUG_BASE_IDX 2
#define mmHUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK 0x07b3
#define mmHUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX 2
#define mmHUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK 0x07b4
#define mmHUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX 2
// addressBlock: dce_dc_dcbubp2_dispdec_hubpreq_dispdec
// base address: 0x6e0
#define mmHUBPREQ2_DCSURF_SURFACE_PITCH 0x07bf
#define mmHUBPREQ2_DCSURF_SURFACE_PITCH_BASE_IDX 2
#define mmHUBPREQ2_DCSURF_SURFACE_PITCH_C 0x07c0
#define mmHUBPREQ2_DCSURF_SURFACE_PITCH_C_BASE_IDX 2
#define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS 0x07c2
#define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2
#define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0x07c3
#define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
#define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0x07c4
#define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2
#define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x07c5
#define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
#define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS 0x07c6
#define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2
#define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0x07c7
#define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
#define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0x07c8
#define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2
#define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x07c9
#define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
#define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS 0x07ca
#define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX 2
#define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH 0x07cb
#define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2
#define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C 0x07cc
#define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX 2
#define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0x07cd
#define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
#define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS 0x07ce
#define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX 2
#define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH 0x07cf
#define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2
#define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C 0x07d0
#define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX 2
#define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0x07d1
#define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
#define mmHUBPREQ2_DCSURF_SURFACE_CONTROL 0x07d2
#define mmHUBPREQ2_DCSURF_SURFACE_CONTROL_BASE_IDX 2
#define mmHUBPREQ2_DCSURF_FLIP_CONTROL 0x07d3
#define mmHUBPREQ2_DCSURF_FLIP_CONTROL_BASE_IDX 2
#define mmHUBPREQ2_DCSURF_FLIP_CONTROL2 0x07d4
#define mmHUBPREQ2_DCSURF_FLIP_CONTROL2_BASE_IDX 2
#define mmHUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT 0x07d8
#define mmHUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX 2
#define mmHUBPREQ2_DCSURF_SURFACE_INUSE 0x07d9
#define mmHUBPREQ2_DCSURF_SURFACE_INUSE_BASE_IDX 2
#define mmHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH 0x07da
#define mmHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX 2
#define mmHUBPREQ2_DCSURF_SURFACE_INUSE_C 0x07db
#define mmHUBPREQ2_DCSURF_SURFACE_INUSE_C_BASE_IDX 2
#define mmHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C 0x07dc
#define mmHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX 2
#define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE 0x07dd
#define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX 2
#define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0x07de
#define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX 2
#define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C 0x07df
#define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX 2
#define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0x07e0
#define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX 2
#define mmHUBPREQ2_DCN_EXPANSION_MODE 0x07e4
#define mmHUBPREQ2_DCN_EXPANSION_MODE_BASE_IDX 2
#define mmHUBPREQ2_DCN_TTU_QOS_WM 0x07e5
#define mmHUBPREQ2_DCN_TTU_QOS_WM_BASE_IDX 2
#define mmHUBPREQ2_DCN_GLOBAL_TTU_CNTL 0x07e6
#define mmHUBPREQ2_DCN_GLOBAL_TTU_CNTL_BASE_IDX 2
#define mmHUBPREQ2_DCN_SURF0_TTU_CNTL0 0x07e7
#define mmHUBPREQ2_DCN_SURF0_TTU_CNTL0_BASE_IDX 2
#define mmHUBPREQ2_DCN_SURF0_TTU_CNTL1 0x07e8
#define mmHUBPREQ2_DCN_SURF0_TTU_CNTL1_BASE_IDX 2
#define mmHUBPREQ2_DCN_SURF1_TTU_CNTL0 0x07e9
#define mmHUBPREQ2_DCN_SURF1_TTU_CNTL0_BASE_IDX 2
#define mmHUBPREQ2_DCN_SURF1_TTU_CNTL1 0x07ea
#define mmHUBPREQ2_DCN_SURF1_TTU_CNTL1_BASE_IDX 2
#define mmHUBPREQ2_DCN_CUR0_TTU_CNTL0 0x07eb
#define mmHUBPREQ2_DCN_CUR0_TTU_CNTL0_BASE_IDX 2
#define mmHUBPREQ2_DCN_CUR0_TTU_CNTL1 0x07ec
#define mmHUBPREQ2_DCN_CUR0_TTU_CNTL1_BASE_IDX 2
#define mmHUBPREQ2_DCN_CUR1_TTU_CNTL0 0x07ed
#define mmHUBPREQ2_DCN_CUR1_TTU_CNTL0_BASE_IDX 2
#define mmHUBPREQ2_DCN_CUR1_TTU_CNTL1 0x07ee
#define mmHUBPREQ2_DCN_CUR1_TTU_CNTL1_BASE_IDX 2
#define mmHUBPREQ2_BLANK_OFFSET_0 0x07fe
#define mmHUBPREQ2_BLANK_OFFSET_0_BASE_IDX 2
#define mmHUBPREQ2_BLANK_OFFSET_1 0x07ff
#define mmHUBPREQ2_BLANK_OFFSET_1_BASE_IDX 2
#define mmHUBPREQ2_DST_DIMENSIONS 0x0800
#define mmHUBPREQ2_DST_DIMENSIONS_BASE_IDX 2
#define mmHUBPREQ2_DST_AFTER_SCALER 0x0801
#define mmHUBPREQ2_DST_AFTER_SCALER_BASE_IDX 2
#define mmHUBPREQ2_PREFETCH_SETTINGS 0x0802
#define mmHUBPREQ2_PREFETCH_SETTINGS_BASE_IDX 2
#define mmHUBPREQ2_PREFETCH_SETTINGS_C 0x0803
#define mmHUBPREQ2_PREFETCH_SETTINGS_C_BASE_IDX 2
#define mmHUBPREQ2_VBLANK_PARAMETERS_0 0x0804
#define mmHUBPREQ2_VBLANK_PARAMETERS_0_BASE_IDX 2
#define mmHUBPREQ2_VBLANK_PARAMETERS_1 0x0805
#define mmHUBPREQ2_VBLANK_PARAMETERS_1_BASE_IDX 2
#define mmHUBPREQ2_VBLANK_PARAMETERS_2 0x0806
#define mmHUBPREQ2_VBLANK_PARAMETERS_2_BASE_IDX 2
#define mmHUBPREQ2_VBLANK_PARAMETERS_3 0x0807
#define mmHUBPREQ2_VBLANK_PARAMETERS_3_BASE_IDX 2
#define mmHUBPREQ2_VBLANK_PARAMETERS_4 0x0808
#define mmHUBPREQ2_VBLANK_PARAMETERS_4_BASE_IDX 2
#define mmHUBPREQ2_FLIP_PARAMETERS_0 0x0809
#define mmHUBPREQ2_FLIP_PARAMETERS_0_BASE_IDX 2
#define mmHUBPREQ2_FLIP_PARAMETERS_2 0x080b
#define mmHUBPREQ2_FLIP_PARAMETERS_2_BASE_IDX 2
#define mmHUBPREQ2_NOM_PARAMETERS_4 0x0810
#define mmHUBPREQ2_NOM_PARAMETERS_4_BASE_IDX 2
#define mmHUBPREQ2_NOM_PARAMETERS_5 0x0811
#define mmHUBPREQ2_NOM_PARAMETERS_5_BASE_IDX 2
#define mmHUBPREQ2_NOM_PARAMETERS_6 0x0812
#define mmHUBPREQ2_NOM_PARAMETERS_6_BASE_IDX 2
#define mmHUBPREQ2_NOM_PARAMETERS_7 0x0813
#define mmHUBPREQ2_NOM_PARAMETERS_7_BASE_IDX 2
#define mmHUBPREQ2_PER_LINE_DELIVERY_PRE 0x0814
#define mmHUBPREQ2_PER_LINE_DELIVERY_PRE_BASE_IDX 2
#define mmHUBPREQ2_PER_LINE_DELIVERY 0x0815
#define mmHUBPREQ2_PER_LINE_DELIVERY_BASE_IDX 2
#define mmHUBPREQ2_CURSOR_SETTINGS 0x0816
#define mmHUBPREQ2_CURSOR_SETTINGS_BASE_IDX 2
#define mmHUBPREQ2_REF_FREQ_TO_PIX_FREQ 0x0817
#define mmHUBPREQ2_REF_FREQ_TO_PIX_FREQ_BASE_IDX 2
#define mmHUBPREQ2_DST_Y_DELTA_DRQ_LIMIT 0x0818
#define mmHUBPREQ2_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX 2
#define mmHUBPREQ2_HUBPREQ_MEM_PWR_CTRL 0x0819
#define mmHUBPREQ2_HUBPREQ_MEM_PWR_CTRL_BASE_IDX 2
#define mmHUBPREQ2_HUBPREQ_MEM_PWR_STATUS 0x081a
#define mmHUBPREQ2_HUBPREQ_MEM_PWR_STATUS_BASE_IDX 2
// addressBlock: dce_dc_dcbubp2_dispdec_hubpret_dispdec
// base address: 0x6e0
#define mmHUBPRET2_HUBPRET_CONTROL 0x0822
#define mmHUBPRET2_HUBPRET_CONTROL_BASE_IDX 2
#define mmHUBPRET2_HUBPRET_MEM_PWR_CTRL 0x0823
#define mmHUBPRET2_HUBPRET_MEM_PWR_CTRL_BASE_IDX 2
#define mmHUBPRET2_HUBPRET_MEM_PWR_STATUS 0x0824
#define mmHUBPRET2_HUBPRET_MEM_PWR_STATUS_BASE_IDX 2
#define mmHUBPRET2_HUBPRET_READ_LINE_CTRL0 0x0825
#define mmHUBPRET2_HUBPRET_READ_LINE_CTRL0_BASE_IDX 2
#define mmHUBPRET2_HUBPRET_READ_LINE_CTRL1 0x0826
#define mmHUBPRET2_HUBPRET_READ_LINE_CTRL1_BASE_IDX 2
#define mmHUBPRET2_HUBPRET_READ_LINE0 0x0827
#define mmHUBPRET2_HUBPRET_READ_LINE0_BASE_IDX 2
#define mmHUBPRET2_HUBPRET_READ_LINE1 0x0828
#define mmHUBPRET2_HUBPRET_READ_LINE1_BASE_IDX 2
#define mmHUBPRET2_HUBPRET_INTERRUPT 0x0829
#define mmHUBPRET2_HUBPRET_INTERRUPT_BASE_IDX 2
#define mmHUBPRET2_HUBPRET_READ_LINE_VALUE 0x082a
#define mmHUBPRET2_HUBPRET_READ_LINE_VALUE_BASE_IDX 2
#define mmHUBPRET2_HUBPRET_READ_LINE_STATUS 0x082b
#define mmHUBPRET2_HUBPRET_READ_LINE_STATUS_BASE_IDX 2
// addressBlock: dce_dc_dcbubp2_dispdec_cursor0_dispdec
// base address: 0x6e0
#define mmCURSOR0_2_CURSOR_CONTROL 0x0830
#define mmCURSOR0_2_CURSOR_CONTROL_BASE_IDX 2
#define mmCURSOR0_2_CURSOR_SURFACE_ADDRESS 0x0831
#define mmCURSOR0_2_CURSOR_SURFACE_ADDRESS_BASE_IDX 2
#define mmCURSOR0_2_CURSOR_SURFACE_ADDRESS_HIGH 0x0832
#define mmCURSOR0_2_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX 2
#define mmCURSOR0_2_CURSOR_SIZE 0x0833
#define mmCURSOR0_2_CURSOR_SIZE_BASE_IDX 2
#define mmCURSOR0_2_CURSOR_POSITION 0x0834
#define mmCURSOR0_2_CURSOR_POSITION_BASE_IDX 2
#define mmCURSOR0_2_CURSOR_HOT_SPOT 0x0835
#define mmCURSOR0_2_CURSOR_HOT_SPOT_BASE_IDX 2
#define mmCURSOR0_2_CURSOR_STEREO_CONTROL 0x0836
#define mmCURSOR0_2_CURSOR_STEREO_CONTROL_BASE_IDX 2
#define mmCURSOR0_2_CURSOR_DST_OFFSET 0x0837
#define mmCURSOR0_2_CURSOR_DST_OFFSET_BASE_IDX 2
#define mmCURSOR0_2_CURSOR_MEM_PWR_CTRL 0x0838
#define mmCURSOR0_2_CURSOR_MEM_PWR_CTRL_BASE_IDX 2
#define mmCURSOR0_2_CURSOR_MEM_PWR_STATUS 0x0839
#define mmCURSOR0_2_CURSOR_MEM_PWR_STATUS_BASE_IDX 2
#define mmCURSOR0_2_DMDATA_ADDRESS_HIGH 0x083a
#define mmCURSOR0_2_DMDATA_ADDRESS_HIGH_BASE_IDX 2
#define mmCURSOR0_2_DMDATA_ADDRESS_LOW 0x083b
#define mmCURSOR0_2_DMDATA_ADDRESS_LOW_BASE_IDX 2
#define mmCURSOR0_2_DMDATA_CNTL 0x083c
#define mmCURSOR0_2_DMDATA_CNTL_BASE_IDX 2
#define mmCURSOR0_2_DMDATA_QOS_CNTL 0x083d
#define mmCURSOR0_2_DMDATA_QOS_CNTL_BASE_IDX 2
#define mmCURSOR0_2_DMDATA_STATUS 0x083e
#define mmCURSOR0_2_DMDATA_STATUS_BASE_IDX 2
#define mmCURSOR0_2_DMDATA_SW_CNTL 0x083f
#define mmCURSOR0_2_DMDATA_SW_CNTL_BASE_IDX 2
#define mmCURSOR0_2_DMDATA_SW_DATA 0x0840
#define mmCURSOR0_2_DMDATA_SW_DATA_BASE_IDX 2
// addressBlock: dce_dc_dcbubp3_dispdec_hubp_dispdec
// base address: 0xa50
#define mmHUBP3_DCSURF_SURFACE_CONFIG 0x0879
#define mmHUBP3_DCSURF_SURFACE_CONFIG_BASE_IDX 2
#define mmHUBP3_DCSURF_ADDR_CONFIG 0x087a
#define mmHUBP3_DCSURF_ADDR_CONFIG_BASE_IDX 2
#define mmHUBP3_DCSURF_TILING_CONFIG 0x087b
#define mmHUBP3_DCSURF_TILING_CONFIG_BASE_IDX 2
#define mmHUBP3_DCSURF_PRI_VIEWPORT_START 0x087d
#define mmHUBP3_DCSURF_PRI_VIEWPORT_START_BASE_IDX 2
#define mmHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION 0x087e
#define mmHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2
#define mmHUBP3_DCSURF_PRI_VIEWPORT_START_C 0x087f
#define mmHUBP3_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX 2
#define mmHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C 0x0880
#define mmHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX 2
#define mmHUBP3_DCSURF_SEC_VIEWPORT_START 0x0881
#define mmHUBP3_DCSURF_SEC_VIEWPORT_START_BASE_IDX 2
#define mmHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION 0x0882
#define mmHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX 2
#define mmHUBP3_DCSURF_SEC_VIEWPORT_START_C 0x0883
#define mmHUBP3_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX 2
#define mmHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C 0x0884
#define mmHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX 2
#define mmHUBP3_DCHUBP_REQ_SIZE_CONFIG 0x0885
#define mmHUBP3_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX 2
#define mmHUBP3_DCHUBP_REQ_SIZE_CONFIG_C 0x0886
#define mmHUBP3_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX 2
#define mmHUBP3_DCHUBP_CNTL 0x0887
#define mmHUBP3_DCHUBP_CNTL_BASE_IDX 2
#define mmHUBP3_HUBP_CLK_CNTL 0x0888
#define mmHUBP3_HUBP_CLK_CNTL_BASE_IDX 2
#define mmHUBP3_HUBPREQ_DEBUG_DB 0x088a
#define mmHUBP3_HUBPREQ_DEBUG_DB_BASE_IDX 2
#define mmHUBP3_HUBPREQ_DEBUG 0x088b
#define mmHUBP3_HUBPREQ_DEBUG_BASE_IDX 2
#define mmHUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK 0x088f
#define mmHUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX 2
#define mmHUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK 0x0890
#define mmHUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX 2
// addressBlock: dce_dc_dcbubp3_dispdec_hubpreq_dispdec
// base address: 0xa50
#define mmHUBPREQ3_DCSURF_SURFACE_PITCH 0x089b
#define mmHUBPREQ3_DCSURF_SURFACE_PITCH_BASE_IDX 2
#define mmHUBPREQ3_DCSURF_SURFACE_PITCH_C 0x089c
#define mmHUBPREQ3_DCSURF_SURFACE_PITCH_C_BASE_IDX 2
#define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS 0x089e
#define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2
#define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0x089f
#define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
#define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0x08a0
#define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2
#define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x08a1
#define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
#define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS 0x08a2
#define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2
#define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0x08a3
#define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
#define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0x08a4
#define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2
#define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x08a5
#define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
#define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS 0x08a6
#define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX 2
#define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH 0x08a7
#define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2
#define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C 0x08a8
#define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX 2
#define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0x08a9
#define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
#define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS 0x08aa
#define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX 2
#define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH 0x08ab
#define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2
#define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C 0x08ac
#define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX 2
#define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0x08ad
#define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
#define mmHUBPREQ3_DCSURF_SURFACE_CONTROL 0x08ae
#define mmHUBPREQ3_DCSURF_SURFACE_CONTROL_BASE_IDX 2
#define mmHUBPREQ3_DCSURF_FLIP_CONTROL 0x08af
#define mmHUBPREQ3_DCSURF_FLIP_CONTROL_BASE_IDX 2
#define mmHUBPREQ3_DCSURF_FLIP_CONTROL2 0x08b0
#define mmHUBPREQ3_DCSURF_FLIP_CONTROL2_BASE_IDX 2
#define mmHUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT 0x08b4
#define mmHUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX 2
#define mmHUBPREQ3_DCSURF_SURFACE_INUSE 0x08b5
#define mmHUBPREQ3_DCSURF_SURFACE_INUSE_BASE_IDX 2
#define mmHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH 0x08b6
#define mmHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX 2
#define mmHUBPREQ3_DCSURF_SURFACE_INUSE_C 0x08b7
#define mmHUBPREQ3_DCSURF_SURFACE_INUSE_C_BASE_IDX 2
#define mmHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C 0x08b8
#define mmHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX 2
#define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE 0x08b9
#define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX 2
#define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0x08ba
#define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX 2
#define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C 0x08bb
#define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX 2
#define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0x08bc
#define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX 2
#define mmHUBPREQ3_DCN_EXPANSION_MODE 0x08c0
#define mmHUBPREQ3_DCN_EXPANSION_MODE_BASE_IDX 2
#define mmHUBPREQ3_DCN_TTU_QOS_WM 0x08c1
#define mmHUBPREQ3_DCN_TTU_QOS_WM_BASE_IDX 2
#define mmHUBPREQ3_DCN_GLOBAL_TTU_CNTL 0x08c2
#define mmHUBPREQ3_DCN_GLOBAL_TTU_CNTL_BASE_IDX 2
#define mmHUBPREQ3_DCN_SURF0_TTU_CNTL0 0x08c3
#define mmHUBPREQ3_DCN_SURF0_TTU_CNTL0_BASE_IDX 2
#define mmHUBPREQ3_DCN_SURF0_TTU_CNTL1 0x08c4
#define mmHUBPREQ3_DCN_SURF0_TTU_CNTL1_BASE_IDX 2
#define mmHUBPREQ3_DCN_SURF1_TTU_CNTL0 0x08c5
#define mmHUBPREQ3_DCN_SURF1_TTU_CNTL0_BASE_IDX 2
#define mmHUBPREQ3_DCN_SURF1_TTU_CNTL1 0x08c6
#define mmHUBPREQ3_DCN_SURF1_TTU_CNTL1_BASE_IDX 2
#define mmHUBPREQ3_DCN_CUR0_TTU_CNTL0 0x08c7
#define mmHUBPREQ3_DCN_CUR0_TTU_CNTL0_BASE_IDX 2
#define mmHUBPREQ3_DCN_CUR0_TTU_CNTL1 0x08c8
#define mmHUBPREQ3_DCN_CUR0_TTU_CNTL1_BASE_IDX 2
#define mmHUBPREQ3_BLANK_OFFSET_0 0x08da
#define mmHUBPREQ3_BLANK_OFFSET_0_BASE_IDX 2
#define mmHUBPREQ3_BLANK_OFFSET_1 0x08db
#define mmHUBPREQ3_BLANK_OFFSET_1_BASE_IDX 2
#define mmHUBPREQ3_DST_DIMENSIONS 0x08dc
#define mmHUBPREQ3_DST_DIMENSIONS_BASE_IDX 2
#define mmHUBPREQ3_DST_AFTER_SCALER 0x08dd
#define mmHUBPREQ3_DST_AFTER_SCALER_BASE_IDX 2
#define mmHUBPREQ3_PREFETCH_SETTINGS 0x08de
#define mmHUBPREQ3_PREFETCH_SETTINGS_BASE_IDX 2
#define mmHUBPREQ3_PREFETCH_SETTINGS_C 0x08df
#define mmHUBPREQ3_PREFETCH_SETTINGS_C_BASE_IDX 2
#define mmHUBPREQ3_VBLANK_PARAMETERS_0 0x08e0
#define mmHUBPREQ3_VBLANK_PARAMETERS_0_BASE_IDX 2
#define mmHUBPREQ3_VBLANK_PARAMETERS_1 0x08e1
#define mmHUBPREQ3_VBLANK_PARAMETERS_1_BASE_IDX 2
#define mmHUBPREQ3_VBLANK_PARAMETERS_2 0x08e2
#define mmHUBPREQ3_VBLANK_PARAMETERS_2_BASE_IDX 2
#define mmHUBPREQ3_VBLANK_PARAMETERS_3 0x08e3
#define mmHUBPREQ3_VBLANK_PARAMETERS_3_BASE_IDX 2
#define mmHUBPREQ3_VBLANK_PARAMETERS_4 0x08e4
#define mmHUBPREQ3_VBLANK_PARAMETERS_4_BASE_IDX 2
#define mmHUBPREQ3_FLIP_PARAMETERS_0 0x08e5
#define mmHUBPREQ3_FLIP_PARAMETERS_0_BASE_IDX 2
#define mmHUBPREQ3_FLIP_PARAMETERS_2 0x08e7
#define mmHUBPREQ3_FLIP_PARAMETERS_2_BASE_IDX 2
#define mmHUBPREQ3_NOM_PARAMETERS_4 0x08ec
#define mmHUBPREQ3_NOM_PARAMETERS_4_BASE_IDX 2
#define mmHUBPREQ3_NOM_PARAMETERS_5 0x08ed
#define mmHUBPREQ3_NOM_PARAMETERS_5_BASE_IDX 2
#define mmHUBPREQ3_NOM_PARAMETERS_6 0x08ee
#define mmHUBPREQ3_NOM_PARAMETERS_6_BASE_IDX 2
#define mmHUBPREQ3_NOM_PARAMETERS_7 0x08ef
#define mmHUBPREQ3_NOM_PARAMETERS_7_BASE_IDX 2
#define mmHUBPREQ3_PER_LINE_DELIVERY_PRE 0x08f0
#define mmHUBPREQ3_PER_LINE_DELIVERY_PRE_BASE_IDX 2
#define mmHUBPREQ3_PER_LINE_DELIVERY 0x08f1
#define mmHUBPREQ3_PER_LINE_DELIVERY_BASE_IDX 2
#define mmHUBPREQ3_CURSOR_SETTINGS 0x08f2
#define mmHUBPREQ3_CURSOR_SETTINGS_BASE_IDX 2
#define mmHUBPREQ3_REF_FREQ_TO_PIX_FREQ 0x08f3
#define mmHUBPREQ3_REF_FREQ_TO_PIX_FREQ_BASE_IDX 2
#define mmHUBPREQ3_DST_Y_DELTA_DRQ_LIMIT 0x08f4
#define mmHUBPREQ3_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX 2
#define mmHUBPREQ3_HUBPREQ_MEM_PWR_CTRL 0x08f5
#define mmHUBPREQ3_HUBPREQ_MEM_PWR_CTRL_BASE_IDX 2
#define mmHUBPREQ3_HUBPREQ_MEM_PWR_STATUS 0x08f6
#define mmHUBPREQ3_HUBPREQ_MEM_PWR_STATUS_BASE_IDX 2
// addressBlock: dce_dc_dcbubp3_dispdec_hubpret_dispdec
// base address: 0xa50
#define mmHUBPRET3_HUBPRET_CONTROL 0x08fe
#define mmHUBPRET3_HUBPRET_CONTROL_BASE_IDX 2
#define mmHUBPRET3_HUBPRET_MEM_PWR_CTRL 0x08ff
#define mmHUBPRET3_HUBPRET_MEM_PWR_CTRL_BASE_IDX 2
#define mmHUBPRET3_HUBPRET_MEM_PWR_STATUS 0x0900
#define mmHUBPRET3_HUBPRET_MEM_PWR_STATUS_BASE_IDX 2
#define mmHUBPRET3_HUBPRET_READ_LINE_CTRL0 0x0901
#define mmHUBPRET3_HUBPRET_READ_LINE_CTRL0_BASE_IDX 2
#define mmHUBPRET3_HUBPRET_READ_LINE_CTRL1 0x0902
#define mmHUBPRET3_HUBPRET_READ_LINE_CTRL1_BASE_IDX 2
#define mmHUBPRET3_HUBPRET_READ_LINE0 0x0903
#define mmHUBPRET3_HUBPRET_READ_LINE0_BASE_IDX 2
#define mmHUBPRET3_HUBPRET_READ_LINE1 0x0904
#define mmHUBPRET3_HUBPRET_READ_LINE1_BASE_IDX 2
#define mmHUBPRET3_HUBPRET_INTERRUPT 0x0905
#define mmHUBPRET3_HUBPRET_INTERRUPT_BASE_IDX 2
#define mmHUBPRET3_HUBPRET_READ_LINE_VALUE 0x0906
#define mmHUBPRET3_HUBPRET_READ_LINE_VALUE_BASE_IDX 2
#define mmHUBPRET3_HUBPRET_READ_LINE_STATUS 0x0907
#define mmHUBPRET3_HUBPRET_READ_LINE_STATUS_BASE_IDX 2
// addressBlock: dce_dc_dcbubp3_dispdec_cursor0_dispdec
// base address: 0xa50
#define mmCURSOR0_3_CURSOR_CONTROL 0x090c
#define mmCURSOR0_3_CURSOR_CONTROL_BASE_IDX 2
#define mmCURSOR0_3_CURSOR_SURFACE_ADDRESS 0x090d
#define mmCURSOR0_3_CURSOR_SURFACE_ADDRESS_BASE_IDX 2
#define mmCURSOR0_3_CURSOR_SURFACE_ADDRESS_HIGH 0x090e
#define mmCURSOR0_3_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX 2
#define mmCURSOR0_3_CURSOR_SIZE 0x090f
#define mmCURSOR0_3_CURSOR_SIZE_BASE_IDX 2
#define mmCURSOR0_3_CURSOR_POSITION 0x0910
#define mmCURSOR0_3_CURSOR_POSITION_BASE_IDX 2
#define mmCURSOR0_3_CURSOR_HOT_SPOT 0x0911
#define mmCURSOR0_3_CURSOR_HOT_SPOT_BASE_IDX 2
#define mmCURSOR0_3_CURSOR_STEREO_CONTROL 0x0912
#define mmCURSOR0_3_CURSOR_STEREO_CONTROL_BASE_IDX 2
#define mmCURSOR0_3_CURSOR_DST_OFFSET 0x0913
#define mmCURSOR0_3_CURSOR_DST_OFFSET_BASE_IDX 2
#define mmCURSOR0_3_CURSOR_MEM_PWR_CTRL 0x0914
#define mmCURSOR0_3_CURSOR_MEM_PWR_CTRL_BASE_IDX 2
#define mmCURSOR0_3_CURSOR_MEM_PWR_STATUS 0x0915
#define mmCURSOR0_3_CURSOR_MEM_PWR_STATUS_BASE_IDX 2
#define mmCURSOR0_3_DMDATA_ADDRESS_HIGH 0x0916
#define mmCURSOR0_3_DMDATA_ADDRESS_HIGH_BASE_IDX 2
#define mmCURSOR0_3_DMDATA_ADDRESS_LOW 0x0917
#define mmCURSOR0_3_DMDATA_ADDRESS_LOW_BASE_IDX 2
#define mmCURSOR0_3_DMDATA_CNTL 0x0918
#define mmCURSOR0_3_DMDATA_CNTL_BASE_IDX 2
#define mmCURSOR0_3_DMDATA_QOS_CNTL 0x0919
#define mmCURSOR0_3_DMDATA_QOS_CNTL_BASE_IDX 2
#define mmCURSOR0_3_DMDATA_STATUS 0x091a
#define mmCURSOR0_3_DMDATA_STATUS_BASE_IDX 2
#define mmCURSOR0_3_DMDATA_SW_CNTL 0x091b
#define mmCURSOR0_3_DMDATA_SW_CNTL_BASE_IDX 2
#define mmCURSOR0_3_DMDATA_SW_DATA 0x091c
#define mmCURSOR0_3_DMDATA_SW_DATA_BASE_IDX 2
// addressBlock: dce_dc_dpp0_dispdec_dpp_top_dispdec
// base address: 0x0
#define mmDPP_TOP0_DPP_CONTROL 0x0cc5
#define mmDPP_TOP0_DPP_CONTROL_BASE_IDX 2
#define mmDPP_TOP0_DPP_SOFT_RESET 0x0cc6
#define mmDPP_TOP0_DPP_SOFT_RESET_BASE_IDX 2
#define mmDPP_TOP0_DPP_CRC_VAL_R_G 0x0cc7
#define mmDPP_TOP0_DPP_CRC_VAL_R_G_BASE_IDX 2
#define mmDPP_TOP0_DPP_CRC_VAL_B_A 0x0cc8
#define mmDPP_TOP0_DPP_CRC_VAL_B_A_BASE_IDX 2
#define mmDPP_TOP0_DPP_CRC_CTRL 0x0cc9
#define mmDPP_TOP0_DPP_CRC_CTRL_BASE_IDX 2
#define mmDPP_TOP0_HOST_READ_CONTROL 0x0cca
#define mmDPP_TOP0_HOST_READ_CONTROL_BASE_IDX 2
// addressBlock: dce_dc_dpp0_dispdec_cnvc_cfg_dispdec
// base address: 0x0
#define mmCNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT 0x0ccf
#define mmCNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX 2
#define mmCNVC_CFG0_FORMAT_CONTROL 0x0cd0
#define mmCNVC_CFG0_FORMAT_CONTROL_BASE_IDX 2
#define mmCNVC_CFG0_FCNV_FP_BIAS_R 0x0cd1
#define mmCNVC_CFG0_FCNV_FP_BIAS_R_BASE_IDX 2
#define mmCNVC_CFG0_FCNV_FP_BIAS_G 0x0cd2
#define mmCNVC_CFG0_FCNV_FP_BIAS_G_BASE_IDX 2
#define mmCNVC_CFG0_FCNV_FP_BIAS_B 0x0cd3
#define mmCNVC_CFG0_FCNV_FP_BIAS_B_BASE_IDX 2
#define mmCNVC_CFG0_FCNV_FP_SCALE_R 0x0cd4
#define mmCNVC_CFG0_FCNV_FP_SCALE_R_BASE_IDX 2
#define mmCNVC_CFG0_FCNV_FP_SCALE_G 0x0cd5
#define mmCNVC_CFG0_FCNV_FP_SCALE_G_BASE_IDX 2
#define mmCNVC_CFG0_FCNV_FP_SCALE_B 0x0cd6
#define mmCNVC_CFG0_FCNV_FP_SCALE_B_BASE_IDX 2
#define mmCNVC_CFG0_COLOR_KEYER_CONTROL 0x0cd7
#define mmCNVC_CFG0_COLOR_KEYER_CONTROL_BASE_IDX 2
#define mmCNVC_CFG0_COLOR_KEYER_ALPHA 0x0cd8
#define mmCNVC_CFG0_COLOR_KEYER_ALPHA_BASE_IDX 2
#define mmCNVC_CFG0_COLOR_KEYER_RED 0x0cd9
#define mmCNVC_CFG0_COLOR_KEYER_RED_BASE_IDX 2
#define mmCNVC_CFG0_COLOR_KEYER_GREEN 0x0cda
#define mmCNVC_CFG0_COLOR_KEYER_GREEN_BASE_IDX 2
#define mmCNVC_CFG0_COLOR_KEYER_BLUE 0x0cdb
#define mmCNVC_CFG0_COLOR_KEYER_BLUE_BASE_IDX 2
#define mmCNVC_CFG0_ALPHA_2BIT_LUT 0x0cdd
#define mmCNVC_CFG0_ALPHA_2BIT_LUT_BASE_IDX 2
// addressBlock: dce_dc_dpp0_dispdec_cnvc_cur_dispdec
// base address: 0x0
#define mmCNVC_CUR0_CURSOR0_CONTROL 0x0ce0
#define mmCNVC_CUR0_CURSOR0_CONTROL_BASE_IDX 2
#define mmCNVC_CUR0_CURSOR0_COLOR0 0x0ce1
#define mmCNVC_CUR0_CURSOR0_COLOR0_BASE_IDX 2
#define mmCNVC_CUR0_CURSOR0_COLOR1 0x0ce2
#define mmCNVC_CUR0_CURSOR0_COLOR1_BASE_IDX 2
#define mmCNVC_CUR0_CURSOR0_FP_SCALE_BIAS 0x0ce3
#define mmCNVC_CUR0_CURSOR0_FP_SCALE_BIAS_BASE_IDX 2
// addressBlock: dce_dc_dpp0_dispdec_dscl_dispdec
// base address: 0x0
#define mmDSCL0_SCL_COEF_RAM_TAP_SELECT 0x0cea
#define mmDSCL0_SCL_COEF_RAM_TAP_SELECT_BASE_IDX 2
#define mmDSCL0_SCL_COEF_RAM_TAP_DATA 0x0ceb
#define mmDSCL0_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2
#define mmDSCL0_SCL_MODE 0x0cec
#define mmDSCL0_SCL_MODE_BASE_IDX 2
#define mmDSCL0_SCL_TAP_CONTROL 0x0ced
#define mmDSCL0_SCL_TAP_CONTROL_BASE_IDX 2
#define mmDSCL0_DSCL_CONTROL 0x0cee
#define mmDSCL0_DSCL_CONTROL_BASE_IDX 2
#define mmDSCL0_DSCL_2TAP_CONTROL 0x0cef
#define mmDSCL0_DSCL_2TAP_CONTROL_BASE_IDX 2
#define mmDSCL0_SCL_MANUAL_REPLICATE_CONTROL 0x0cf0
#define mmDSCL0_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2
#define mmDSCL0_SCL_HORZ_FILTER_SCALE_RATIO 0x0cf1
#define mmDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2
#define mmDSCL0_SCL_HORZ_FILTER_INIT 0x0cf2
#define mmDSCL0_SCL_HORZ_FILTER_INIT_BASE_IDX 2
#define mmDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C 0x0cf3
#define mmDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2
#define mmDSCL0_SCL_HORZ_FILTER_INIT_C 0x0cf4
#define mmDSCL0_SCL_HORZ_FILTER_INIT_C_BASE_IDX 2
#define mmDSCL0_SCL_VERT_FILTER_SCALE_RATIO 0x0cf5
#define mmDSCL0_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2
#define mmDSCL0_SCL_VERT_FILTER_INIT 0x0cf6
#define mmDSCL0_SCL_VERT_FILTER_INIT_BASE_IDX 2
#define mmDSCL0_SCL_VERT_FILTER_INIT_BOT 0x0cf7
#define mmDSCL0_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2
#define mmDSCL0_SCL_VERT_FILTER_SCALE_RATIO_C 0x0cf8
#define mmDSCL0_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2
#define mmDSCL0_SCL_VERT_FILTER_INIT_C 0x0cf9
#define mmDSCL0_SCL_VERT_FILTER_INIT_C_BASE_IDX 2
#define mmDSCL0_SCL_VERT_FILTER_INIT_BOT_C 0x0cfa
#define mmDSCL0_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX 2
#define mmDSCL0_SCL_BLACK_OFFSET 0x0cfb
#define mmDSCL0_SCL_BLACK_OFFSET_BASE_IDX 2
#define mmDSCL0_DSCL_UPDATE 0x0cfc
#define mmDSCL0_DSCL_UPDATE_BASE_IDX 2
#define mmDSCL0_DSCL_AUTOCAL 0x0cfd
#define mmDSCL0_DSCL_AUTOCAL_BASE_IDX 2
#define mmDSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT 0x0cfe
#define mmDSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2
#define mmDSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM 0x0cff
#define mmDSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2
#define mmDSCL0_OTG_H_BLANK 0x0d00
#define mmDSCL0_OTG_H_BLANK_BASE_IDX 2
#define mmDSCL0_OTG_V_BLANK 0x0d01
#define mmDSCL0_OTG_V_BLANK_BASE_IDX 2
#define mmDSCL0_RECOUT_START 0x0d02
#define mmDSCL0_RECOUT_START_BASE_IDX 2
#define mmDSCL0_RECOUT_SIZE 0x0d03
#define mmDSCL0_RECOUT_SIZE_BASE_IDX 2
#define mmDSCL0_MPC_SIZE 0x0d04
#define mmDSCL0_MPC_SIZE_BASE_IDX 2
#define mmDSCL0_LB_DATA_FORMAT 0x0d05
#define mmDSCL0_LB_DATA_FORMAT_BASE_IDX 2
#define mmDSCL0_LB_MEMORY_CTRL 0x0d06
#define mmDSCL0_LB_MEMORY_CTRL_BASE_IDX 2
#define mmDSCL0_LB_V_COUNTER 0x0d07
#define mmDSCL0_LB_V_COUNTER_BASE_IDX 2
#define mmDSCL0_DSCL_MEM_PWR_CTRL 0x0d08
#define mmDSCL0_DSCL_MEM_PWR_CTRL_BASE_IDX 2
#define mmDSCL0_DSCL_MEM_PWR_STATUS 0x0d09
#define mmDSCL0_DSCL_MEM_PWR_STATUS_BASE_IDX 2
#define mmDSCL0_OBUF_CONTROL 0x0d0a
#define mmDSCL0_OBUF_CONTROL_BASE_IDX 2
#define mmDSCL0_OBUF_MEM_PWR_CTRL 0x0d0b
#define mmDSCL0_OBUF_MEM_PWR_CTRL_BASE_IDX 2
// addressBlock: dce_dc_dpp0_dispdec_cm_dispdec
// base address: 0x0
#define mmCM0_CM_CONTROL 0x0d1a
#define mmCM0_CM_CONTROL_BASE_IDX 2
#define mmCM0_CM_ICSC_CONTROL 0x0d1b
#define mmCM0_CM_ICSC_CONTROL_BASE_IDX 2
#define mmCM0_CM_ICSC_C11_C12 0x0d1c
#define mmCM0_CM_ICSC_C11_C12_BASE_IDX 2
#define mmCM0_CM_ICSC_C13_C14 0x0d1d
#define mmCM0_CM_ICSC_C13_C14_BASE_IDX 2
#define mmCM0_CM_ICSC_C21_C22 0x0d1e
#define mmCM0_CM_ICSC_C21_C22_BASE_IDX 2
#define mmCM0_CM_ICSC_C23_C24 0x0d1f
#define mmCM0_CM_ICSC_C23_C24_BASE_IDX 2
#define mmCM0_CM_ICSC_C31_C32 0x0d20
#define mmCM0_CM_ICSC_C31_C32_BASE_IDX 2
#define mmCM0_CM_ICSC_C33_C34 0x0d21
#define mmCM0_CM_ICSC_C33_C34_BASE_IDX 2
#define mmCM0_CM_ICSC_B_C11_C12 0x0d22
#define mmCM0_CM_ICSC_B_C11_C12_BASE_IDX 2
#define mmCM0_CM_ICSC_B_C13_C14 0x0d23
#define mmCM0_CM_ICSC_B_C13_C14_BASE_IDX 2
#define mmCM0_CM_ICSC_B_C21_C22 0x0d24
#define mmCM0_CM_ICSC_B_C21_C22_BASE_IDX 2
#define mmCM0_CM_ICSC_B_C23_C24 0x0d25
#define mmCM0_CM_ICSC_B_C23_C24_BASE_IDX 2
#define mmCM0_CM_ICSC_B_C31_C32 0x0d26
#define mmCM0_CM_ICSC_B_C31_C32_BASE_IDX 2
#define mmCM0_CM_ICSC_B_C33_C34 0x0d27
#define mmCM0_CM_ICSC_B_C33_C34_BASE_IDX 2
#define mmCM0_CM_GAMUT_REMAP_CONTROL 0x0d28
#define mmCM0_CM_GAMUT_REMAP_CONTROL_BASE_IDX 2
#define mmCM0_CM_GAMUT_REMAP_C11_C12 0x0d29
#define mmCM0_CM_GAMUT_REMAP_C11_C12_BASE_IDX 2
#define mmCM0_CM_GAMUT_REMAP_C13_C14 0x0d2a
#define mmCM0_CM_GAMUT_REMAP_C13_C14_BASE_IDX 2
#define mmCM0_CM_GAMUT_REMAP_C21_C22 0x0d2b
#define mmCM0_CM_GAMUT_REMAP_C21_C22_BASE_IDX 2
#define mmCM0_CM_GAMUT_REMAP_C23_C24 0x0d2c
#define mmCM0_CM_GAMUT_REMAP_C23_C24_BASE_IDX 2
#define mmCM0_CM_GAMUT_REMAP_C31_C32 0x0d2d
#define mmCM0_CM_GAMUT_REMAP_C31_C32_BASE_IDX 2
#define mmCM0_CM_GAMUT_REMAP_C33_C34 0x0d2e
#define mmCM0_CM_GAMUT_REMAP_C33_C34_BASE_IDX 2
#define mmCM0_CM_GAMUT_REMAP_B_C11_C12 0x0d2f
#define mmCM0_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX 2
#define mmCM0_CM_GAMUT_REMAP_B_C13_C14 0x0d30
#define mmCM0_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX 2
#define mmCM0_CM_GAMUT_REMAP_B_C21_C22 0x0d31
#define mmCM0_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX 2
#define mmCM0_CM_GAMUT_REMAP_B_C23_C24 0x0d32
#define mmCM0_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX 2
#define mmCM0_CM_GAMUT_REMAP_B_C31_C32 0x0d33
#define mmCM0_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX 2
#define mmCM0_CM_GAMUT_REMAP_B_C33_C34 0x0d34
#define mmCM0_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX 2
#define mmCM0_CM_BIAS_CR_R 0x0d35
#define mmCM0_CM_BIAS_CR_R_BASE_IDX 2
#define mmCM0_CM_BIAS_Y_G_CB_B 0x0d36
#define mmCM0_CM_BIAS_Y_G_CB_B_BASE_IDX 2
#define mmCM0_CM_DGAM_CONTROL 0x0d37
#define mmCM0_CM_DGAM_CONTROL_BASE_IDX 2
#define mmCM0_CM_DGAM_LUT_INDEX 0x0d38
#define mmCM0_CM_DGAM_LUT_INDEX_BASE_IDX 2
#define mmCM0_CM_DGAM_LUT_DATA 0x0d39
#define mmCM0_CM_DGAM_LUT_DATA_BASE_IDX 2
#define mmCM0_CM_DGAM_LUT_WRITE_EN_MASK 0x0d3a
#define mmCM0_CM_DGAM_LUT_WRITE_EN_MASK_BASE_IDX 2
#define mmCM0_CM_DGAM_RAMA_START_CNTL_B 0x0d3b
#define mmCM0_CM_DGAM_RAMA_START_CNTL_B_BASE_IDX 2
#define mmCM0_CM_DGAM_RAMA_START_CNTL_G 0x0d3c
#define mmCM0_CM_DGAM_RAMA_START_CNTL_G_BASE_IDX 2
#define mmCM0_CM_DGAM_RAMA_START_CNTL_R 0x0d3d
#define mmCM0_CM_DGAM_RAMA_START_CNTL_R_BASE_IDX 2
#define mmCM0_CM_DGAM_RAMA_SLOPE_CNTL_B 0x0d3e
#define mmCM0_CM_DGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2
#define mmCM0_CM_DGAM_RAMA_SLOPE_CNTL_G 0x0d3f
#define mmCM0_CM_DGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2
#define mmCM0_CM_DGAM_RAMA_SLOPE_CNTL_R 0x0d40
#define mmCM0_CM_DGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2
#define mmCM0_CM_DGAM_RAMA_END_CNTL1_B 0x0d41
#define mmCM0_CM_DGAM_RAMA_END_CNTL1_B_BASE_IDX 2
#define mmCM0_CM_DGAM_RAMA_END_CNTL2_B 0x0d42
#define mmCM0_CM_DGAM_RAMA_END_CNTL2_B_BASE_IDX 2
#define mmCM0_CM_DGAM_RAMA_END_CNTL1_G 0x0d43
#define mmCM0_CM_DGAM_RAMA_END_CNTL1_G_BASE_IDX 2
#define mmCM0_CM_DGAM_RAMA_END_CNTL2_G 0x0d44
#define mmCM0_CM_DGAM_RAMA_END_CNTL2_G_BASE_IDX 2
#define mmCM0_CM_DGAM_RAMA_END_CNTL1_R 0x0d45
#define mmCM0_CM_DGAM_RAMA_END_CNTL1_R_BASE_IDX 2
#define mmCM0_CM_DGAM_RAMA_END_CNTL2_R 0x0d46
#define mmCM0_CM_DGAM_RAMA_END_CNTL2_R_BASE_IDX 2
#define mmCM0_CM_DGAM_RAMA_REGION_0_1 0x0d47
#define mmCM0_CM_DGAM_RAMA_REGION_0_1_BASE_IDX 2
#define mmCM0_CM_DGAM_RAMA_REGION_2_3 0x0d48
#define mmCM0_CM_DGAM_RAMA_REGION_2_3_BASE_IDX 2
#define mmCM0_CM_DGAM_RAMA_REGION_4_5 0x0d49
#define mmCM0_CM_DGAM_RAMA_REGION_4_5_BASE_IDX 2
#define mmCM0_CM_DGAM_RAMA_REGION_6_7 0x0d4a
#define mmCM0_CM_DGAM_RAMA_REGION_6_7_BASE_IDX 2
#define mmCM0_CM_DGAM_RAMA_REGION_8_9 0x0d4b
#define mmCM0_CM_DGAM_RAMA_REGION_8_9_BASE_IDX 2
#define mmCM0_CM_DGAM_RAMA_REGION_10_11 0x0d4c
#define mmCM0_CM_DGAM_RAMA_REGION_10_11_BASE_IDX 2
#define mmCM0_CM_DGAM_RAMA_REGION_12_13 0x0d4d
#define mmCM0_CM_DGAM_RAMA_REGION_12_13_BASE_IDX 2
#define mmCM0_CM_DGAM_RAMA_REGION_14_15 0x0d4e
#define mmCM0_CM_DGAM_RAMA_REGION_14_15_BASE_IDX 2
#define mmCM0_CM_DGAM_RAMB_START_CNTL_B 0x0d4f
#define mmCM0_CM_DGAM_RAMB_START_CNTL_B_BASE_IDX 2
#define mmCM0_CM_DGAM_RAMB_START_CNTL_G 0x0d50
#define mmCM0_CM_DGAM_RAMB_START_CNTL_G_BASE_IDX 2
#define mmCM0_CM_DGAM_RAMB_START_CNTL_R 0x0d51
#define mmCM0_CM_DGAM_RAMB_START_CNTL_R_BASE_IDX 2
#define mmCM0_CM_DGAM_RAMB_SLOPE_CNTL_B 0x0d52
#define mmCM0_CM_DGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2
#define mmCM0_CM_DGAM_RAMB_SLOPE_CNTL_G 0x0d53
#define mmCM0_CM_DGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2
#define mmCM0_CM_DGAM_RAMB_SLOPE_CNTL_R 0x0d54
#define mmCM0_CM_DGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2
#define mmCM0_CM_DGAM_RAMB_END_CNTL1_B 0x0d55
#define mmCM0_CM_DGAM_RAMB_END_CNTL1_B_BASE_IDX 2
#define mmCM0_CM_DGAM_RAMB_END_CNTL2_B 0x0d56
#define mmCM0_CM_DGAM_RAMB_END_CNTL2_B_BASE_IDX 2
#define mmCM0_CM_DGAM_RAMB_END_CNTL1_G 0x0d57
#define mmCM0_CM_DGAM_RAMB_END_CNTL1_G_BASE_IDX 2
#define mmCM0_CM_DGAM_RAMB_END_CNTL2_G 0x0d58
#define mmCM0_CM_DGAM_RAMB_END_CNTL2_G_BASE_IDX 2
#define mmCM0_CM_DGAM_RAMB_END_CNTL1_R 0x0d59
#define mmCM0_CM_DGAM_RAMB_END_CNTL1_R_BASE_IDX 2
#define mmCM0_CM_DGAM_RAMB_END_CNTL2_R 0x0d5a
#define mmCM0_CM_DGAM_RAMB_END_CNTL2_R_BASE_IDX 2
#define mmCM0_CM_DGAM_RAMB_REGION_0_1 0x0d5b
#define mmCM0_CM_DGAM_RAMB_REGION_0_1_BASE_IDX 2
#define mmCM0_CM_DGAM_RAMB_REGION_2_3 0x0d5c
#define mmCM0_CM_DGAM_RAMB_REGION_2_3_BASE_IDX 2
#define mmCM0_CM_DGAM_RAMB_REGION_4_5 0x0d5d
#define mmCM0_CM_DGAM_RAMB_REGION_4_5_BASE_IDX 2
#define mmCM0_CM_DGAM_RAMB_REGION_6_7 0x0d5e
#define mmCM0_CM_DGAM_RAMB_REGION_6_7_BASE_IDX 2
#define mmCM0_CM_DGAM_RAMB_REGION_8_9 0x0d5f
#define mmCM0_CM_DGAM_RAMB_REGION_8_9_BASE_IDX 2
#define mmCM0_CM_DGAM_RAMB_REGION_10_11 0x0d60
#define mmCM0_CM_DGAM_RAMB_REGION_10_11_BASE_IDX 2
#define mmCM0_CM_DGAM_RAMB_REGION_12_13 0x0d61
#define mmCM0_CM_DGAM_RAMB_REGION_12_13_BASE_IDX 2
#define mmCM0_CM_DGAM_RAMB_REGION_14_15 0x0d62
#define mmCM0_CM_DGAM_RAMB_REGION_14_15_BASE_IDX 2
#define mmCM0_CM_BLNDGAM_CONTROL 0x0d63
#define mmCM0_CM_BLNDGAM_CONTROL_BASE_IDX 2
#define mmCM0_CM_BLNDGAM_LUT_INDEX 0x0d64
#define mmCM0_CM_BLNDGAM_LUT_INDEX_BASE_IDX 2
#define mmCM0_CM_BLNDGAM_LUT_DATA 0x0d65
#define mmCM0_CM_BLNDGAM_LUT_DATA_BASE_IDX 2
#define mmCM0_CM_BLNDGAM_LUT_WRITE_EN_MASK 0x0d66
#define mmCM0_CM_BLNDGAM_LUT_WRITE_EN_MASK_BASE_IDX 2
#define mmCM0_CM_BLNDGAM_RAMA_START_CNTL_B 0x0d67
#define mmCM0_CM_BLNDGAM_RAMA_START_CNTL_B_BASE_IDX 2
#define mmCM0_CM_BLNDGAM_RAMA_START_CNTL_G 0x0d68
#define mmCM0_CM_BLNDGAM_RAMA_START_CNTL_G_BASE_IDX 2
#define mmCM0_CM_BLNDGAM_RAMA_START_CNTL_R 0x0d69
#define mmCM0_CM_BLNDGAM_RAMA_START_CNTL_R_BASE_IDX 2
#define mmCM0_CM_BLNDGAM_RAMA_SLOPE_CNTL_B 0x0d6a
#define mmCM0_CM_BLNDGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2
#define mmCM0_CM_BLNDGAM_RAMA_SLOPE_CNTL_G 0x0d6b
#define mmCM0_CM_BLNDGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2
#define mmCM0_CM_BLNDGAM_RAMA_SLOPE_CNTL_R 0x0d6c
#define mmCM0_CM_BLNDGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2
#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL1_B 0x0d6d
#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL1_B_BASE_IDX 2
#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL2_B 0x0d6e
#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL2_B_BASE_IDX 2
#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL1_G 0x0d6f
#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL1_G_BASE_IDX 2
#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL2_G 0x0d70
#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL2_G_BASE_IDX 2
#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL1_R 0x0d71
#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL1_R_BASE_IDX 2
#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL2_R 0x0d72
#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL2_R_BASE_IDX 2
#define mmCM0_CM_BLNDGAM_RAMA_REGION_0_1 0x0d73
#define mmCM0_CM_BLNDGAM_RAMA_REGION_0_1_BASE_IDX 2
#define mmCM0_CM_BLNDGAM_RAMA_REGION_2_3 0x0d74
#define mmCM0_CM_BLNDGAM_RAMA_REGION_2_3_BASE_IDX 2
#define mmCM0_CM_BLNDGAM_RAMA_REGION_4_5 0x0d75
#define mmCM0_CM_BLNDGAM_RAMA_REGION_4_5_BASE_IDX 2
#define mmCM0_CM_BLNDGAM_RAMA_REGION_6_7 0x0d76
#define mmCM0_CM_BLNDGAM_RAMA_REGION_6_7_BASE_IDX 2
#define mmCM0_CM_BLNDGAM_RAMA_REGION_8_9 0x0d77
#define mmCM0_CM_BLNDGAM_RAMA_REGION_8_9_BASE_IDX 2
#define mmCM0_CM_BLNDGAM_RAMA_REGION_10_11 0x0d78
#define mmCM0_CM_BLNDGAM_RAMA_REGION_10_11_BASE_IDX 2
#define mmCM0_CM_BLNDGAM_RAMA_REGION_12_13 0x0d79
#define mmCM0_CM_BLNDGAM_RAMA_REGION_12_13_BASE_IDX 2
#define mmCM0_CM_BLNDGAM_RAMA_REGION_14_15 0x0d7a
#define mmCM0_CM_BLNDGAM_RAMA_REGION_14_15_BASE_IDX 2
#define mmCM0_CM_BLNDGAM_RAMA_REGION_16_17 0x0d7b
#define mmCM0_CM_BLNDGAM_RAMA_REGION_16_17_BASE_IDX 2
#define mmCM0_CM_BLNDGAM_RAMA_REGION_18_19 0x0d7c
#define mmCM0_CM_BLNDGAM_RAMA_REGION_18_19_BASE_IDX 2
#define mmCM0_CM_BLNDGAM_RAMA_REGION_20_21 0x0d7d
#define mmCM0_CM_BLNDGAM_RAMA_REGION_20_21_BASE_IDX 2
#define mmCM0_CM_BLNDGAM_RAMA_REGION_22_23 0x0d7e
#define mmCM0_CM_BLNDGAM_RAMA_REGION_22_23_BASE_IDX 2
#define mmCM0_CM_BLNDGAM_RAMA_REGION_24_25 0x0d7f
#define mmCM0_CM_BLNDGAM_RAMA_REGION_24_25_BASE_IDX 2
#define mmCM0_CM_BLNDGAM_RAMA_REGION_26_27 0x0d80
#define mmCM0_CM_BLNDGAM_RAMA_REGION_26_27_BASE_IDX 2
#define mmCM0_CM_BLNDGAM_RAMA_REGION_28_29 0x0d81
#define mmCM0_CM_BLNDGAM_RAMA_REGION_28_29_BASE_IDX 2
#define mmCM0_CM_BLNDGAM_RAMA_REGION_30_31 0x0d82
#define mmCM0_CM_BLNDGAM_RAMA_REGION_30_31_BASE_IDX 2
#define mmCM0_CM_BLNDGAM_RAMA_REGION_32_33 0x0d83
#define mmCM0_CM_BLNDGAM_RAMA_REGION_32_33_BASE_IDX 2
#define mmCM0_CM_BLNDGAM_RAMB_START_CNTL_B 0x0d84
#define mmCM0_CM_BLNDGAM_RAMB_START_CNTL_B_BASE_IDX 2
#define mmCM0_CM_BLNDGAM_RAMB_START_CNTL_G 0x0d85
#define mmCM0_CM_BLNDGAM_RAMB_START_CNTL_G_BASE_IDX 2
#define mmCM0_CM_BLNDGAM_RAMB_START_CNTL_R 0x0d86
#define mmCM0_CM_BLNDGAM_RAMB_START_CNTL_R_BASE_IDX 2
#define mmCM0_CM_BLNDGAM_RAMB_SLOPE_CNTL_B 0x0d87
#define mmCM0_CM_BLNDGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2
#define mmCM0_CM_BLNDGAM_RAMB_SLOPE_CNTL_G 0x0d88
#define mmCM0_CM_BLNDGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2
#define mmCM0_CM_BLNDGAM_RAMB_SLOPE_CNTL_R 0x0d89
#define mmCM0_CM_BLNDGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2
#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL1_B 0x0d8a
#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL1_B_BASE_IDX 2
#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL2_B 0x0d8b
#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL2_B_BASE_IDX 2
#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL1_G 0x0d8c
#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL1_G_BASE_IDX 2
#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL2_G 0x0d8d
#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL2_G_BASE_IDX 2
#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL1_R 0x0d8e
#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL1_R_BASE_IDX 2
#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL2_R 0x0d8f
#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL2_R_BASE_IDX 2
#define mmCM0_CM_BLNDGAM_RAMB_REGION_0_1 0x0d90
#define mmCM0_CM_BLNDGAM_RAMB_REGION_0_1_BASE_IDX 2
#define mmCM0_CM_BLNDGAM_RAMB_REGION_2_3 0x0d91
#define mmCM0_CM_BLNDGAM_RAMB_REGION_2_3_BASE_IDX 2
#define mmCM0_CM_BLNDGAM_RAMB_REGION_4_5 0x0d92
#define mmCM0_CM_BLNDGAM_RAMB_REGION_4_5_BASE_IDX 2
#define mmCM0_CM_BLNDGAM_RAMB_REGION_6_7 0x0d93
#define mmCM0_CM_BLNDGAM_RAMB_REGION_6_7_BASE_IDX 2
#define mmCM0_CM_BLNDGAM_RAMB_REGION_8_9 0x0d94
#define mmCM0_CM_BLNDGAM_RAMB_REGION_8_9_BASE_IDX 2
#define mmCM0_CM_BLNDGAM_RAMB_REGION_10_11 0x0d95
#define mmCM0_CM_BLNDGAM_RAMB_REGION_10_11_BASE_IDX 2
#define mmCM0_CM_BLNDGAM_RAMB_REGION_12_13 0x0d96
#define mmCM0_CM_BLNDGAM_RAMB_REGION_12_13_BASE_IDX 2
#define mmCM0_CM_BLNDGAM_RAMB_REGION_14_15 0x0d97
#define mmCM0_CM_BLNDGAM_RAMB_REGION_14_15_BASE_IDX 2
#define mmCM0_CM_BLNDGAM_RAMB_REGION_16_17 0x0d98
#define mmCM0_CM_BLNDGAM_RAMB_REGION_16_17_BASE_IDX 2
#define mmCM0_CM_BLNDGAM_RAMB_REGION_18_19 0x0d99
#define mmCM0_CM_BLNDGAM_RAMB_REGION_18_19_BASE_IDX 2
#define mmCM0_CM_BLNDGAM_RAMB_REGION_20_21 0x0d9a
#define mmCM0_CM_BLNDGAM_RAMB_REGION_20_21_BASE_IDX 2
#define mmCM0_CM_BLNDGAM_RAMB_REGION_22_23 0x0d9b
#define mmCM0_CM_BLNDGAM_RAMB_REGION_22_23_BASE_IDX 2
#define mmCM0_CM_BLNDGAM_RAMB_REGION_24_25 0x0d9c
#define mmCM0_CM_BLNDGAM_RAMB_REGION_24_25_BASE_IDX 2
#define mmCM0_CM_BLNDGAM_RAMB_REGION_26_27 0x0d9d
#define mmCM0_CM_BLNDGAM_RAMB_REGION_26_27_BASE_IDX 2
#define mmCM0_CM_BLNDGAM_RAMB_REGION_28_29 0x0d9e
#define mmCM0_CM_BLNDGAM_RAMB_REGION_28_29_BASE_IDX 2
#define mmCM0_CM_BLNDGAM_RAMB_REGION_30_31 0x0d9f
#define mmCM0_CM_BLNDGAM_RAMB_REGION_30_31_BASE_IDX 2
#define mmCM0_CM_BLNDGAM_RAMB_REGION_32_33 0x0da0
#define mmCM0_CM_BLNDGAM_RAMB_REGION_32_33_BASE_IDX 2
#define mmCM0_CM_HDR_MULT_COEF 0x0da1
#define mmCM0_CM_HDR_MULT_COEF_BASE_IDX 2
#define mmCM0_CM_MEM_PWR_CTRL 0x0da2
#define mmCM0_CM_MEM_PWR_CTRL_BASE_IDX 2
#define mmCM0_CM_MEM_PWR_STATUS 0x0da3
#define mmCM0_CM_MEM_PWR_STATUS_BASE_IDX 2
#define mmCM0_CM_DEALPHA 0x0da5
#define mmCM0_CM_DEALPHA_BASE_IDX 2
#define mmCM0_CM_COEF_FORMAT 0x0da6
#define mmCM0_CM_COEF_FORMAT_BASE_IDX 2
#define mmCM0_CM_SHAPER_CONTROL 0x0da7
#define mmCM0_CM_SHAPER_CONTROL_BASE_IDX 2
#define mmCM0_CM_SHAPER_OFFSET_R 0x0da8
#define mmCM0_CM_SHAPER_OFFSET_R_BASE_IDX 2
#define mmCM0_CM_SHAPER_OFFSET_G 0x0da9
#define mmCM0_CM_SHAPER_OFFSET_G_BASE_IDX 2
#define mmCM0_CM_SHAPER_OFFSET_B 0x0daa
#define mmCM0_CM_SHAPER_OFFSET_B_BASE_IDX 2
#define mmCM0_CM_SHAPER_SCALE_R 0x0dab
#define mmCM0_CM_SHAPER_SCALE_R_BASE_IDX 2
#define mmCM0_CM_SHAPER_SCALE_G_B 0x0dac
#define mmCM0_CM_SHAPER_SCALE_G_B_BASE_IDX 2
#define mmCM0_CM_SHAPER_LUT_INDEX 0x0dad
#define mmCM0_CM_SHAPER_LUT_INDEX_BASE_IDX 2
#define mmCM0_CM_SHAPER_LUT_DATA 0x0dae
#define mmCM0_CM_SHAPER_LUT_DATA_BASE_IDX 2
#define mmCM0_CM_SHAPER_LUT_WRITE_EN_MASK 0x0daf
#define mmCM0_CM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX 2
#define mmCM0_CM_SHAPER_RAMA_START_CNTL_B 0x0db0
#define mmCM0_CM_SHAPER_RAMA_START_CNTL_B_BASE_IDX 2
#define mmCM0_CM_SHAPER_RAMA_START_CNTL_G 0x0db1
#define mmCM0_CM_SHAPER_RAMA_START_CNTL_G_BASE_IDX 2
#define mmCM0_CM_SHAPER_RAMA_START_CNTL_R 0x0db2
#define mmCM0_CM_SHAPER_RAMA_START_CNTL_R_BASE_IDX 2
#define mmCM0_CM_SHAPER_RAMA_END_CNTL_B 0x0db3
#define mmCM0_CM_SHAPER_RAMA_END_CNTL_B_BASE_IDX 2
#define mmCM0_CM_SHAPER_RAMA_END_CNTL_G 0x0db4
#define mmCM0_CM_SHAPER_RAMA_END_CNTL_G_BASE_IDX 2
#define mmCM0_CM_SHAPER_RAMA_END_CNTL_R 0x0db5
#define mmCM0_CM_SHAPER_RAMA_END_CNTL_R_BASE_IDX 2
#define mmCM0_CM_SHAPER_RAMA_REGION_0_1 0x0db6
#define mmCM0_CM_SHAPER_RAMA_REGION_0_1_BASE_IDX 2
#define mmCM0_CM_SHAPER_RAMA_REGION_2_3 0x0db7
#define mmCM0_CM_SHAPER_RAMA_REGION_2_3_BASE_IDX 2
#define mmCM0_CM_SHAPER_RAMA_REGION_4_5 0x0db8
#define mmCM0_CM_SHAPER_RAMA_REGION_4_5_BASE_IDX 2
#define mmCM0_CM_SHAPER_RAMA_REGION_6_7 0x0db9
#define mmCM0_CM_SHAPER_RAMA_REGION_6_7_BASE_IDX 2
#define mmCM0_CM_SHAPER_RAMA_REGION_8_9 0x0dba
#define mmCM0_CM_SHAPER_RAMA_REGION_8_9_BASE_IDX 2
#define mmCM0_CM_SHAPER_RAMA_REGION_10_11 0x0dbb
#define mmCM0_CM_SHAPER_RAMA_REGION_10_11_BASE_IDX 2
#define mmCM0_CM_SHAPER_RAMA_REGION_12_13 0x0dbc
#define mmCM0_CM_SHAPER_RAMA_REGION_12_13_BASE_IDX 2
#define mmCM0_CM_SHAPER_RAMA_REGION_14_15 0x0dbd
#define mmCM0_CM_SHAPER_RAMA_REGION_14_15_BASE_IDX 2
#define mmCM0_CM_SHAPER_RAMA_REGION_16_17 0x0dbe
#define mmCM0_CM_SHAPER_RAMA_REGION_16_17_BASE_IDX 2
#define mmCM0_CM_SHAPER_RAMA_REGION_18_19 0x0dbf
#define mmCM0_CM_SHAPER_RAMA_REGION_18_19_BASE_IDX 2
#define mmCM0_CM_SHAPER_RAMA_REGION_20_21 0x0dc0
#define mmCM0_CM_SHAPER_RAMA_REGION_20_21_BASE_IDX 2
#define mmCM0_CM_SHAPER_RAMA_REGION_22_23 0x0dc1
#define mmCM0_CM_SHAPER_RAMA_REGION_22_23_BASE_IDX 2
#define mmCM0_CM_SHAPER_RAMA_REGION_24_25 0x0dc2
#define mmCM0_CM_SHAPER_RAMA_REGION_24_25_BASE_IDX 2
#define mmCM0_CM_SHAPER_RAMA_REGION_26_27 0x0dc3
#define mmCM0_CM_SHAPER_RAMA_REGION_26_27_BASE_IDX 2
#define mmCM0_CM_SHAPER_RAMA_REGION_28_29 0x0dc4
#define mmCM0_CM_SHAPER_RAMA_REGION_28_29_BASE_IDX 2
#define mmCM0_CM_SHAPER_RAMA_REGION_30_31 0x0dc5
#define mmCM0_CM_SHAPER_RAMA_REGION_30_31_BASE_IDX 2
#define mmCM0_CM_SHAPER_RAMA_REGION_32_33 0x0dc6
#define mmCM0_CM_SHAPER_RAMA_REGION_32_33_BASE_IDX 2
#define mmCM0_CM_SHAPER_RAMB_START_CNTL_B 0x0dc7
#define mmCM0_CM_SHAPER_RAMB_START_CNTL_B_BASE_IDX 2
#define mmCM0_CM_SHAPER_RAMB_START_CNTL_G 0x0dc8
#define mmCM0_CM_SHAPER_RAMB_START_CNTL_G_BASE_IDX 2
#define mmCM0_CM_SHAPER_RAMB_START_CNTL_R 0x0dc9
#define mmCM0_CM_SHAPER_RAMB_START_CNTL_R_BASE_IDX 2
#define mmCM0_CM_SHAPER_RAMB_END_CNTL_B 0x0dca
#define mmCM0_CM_SHAPER_RAMB_END_CNTL_B_BASE_IDX 2
#define mmCM0_CM_SHAPER_RAMB_END_CNTL_G 0x0dcb
#define mmCM0_CM_SHAPER_RAMB_END_CNTL_G_BASE_IDX 2
#define mmCM0_CM_SHAPER_RAMB_END_CNTL_R 0x0dcc
#define mmCM0_CM_SHAPER_RAMB_END_CNTL_R_BASE_IDX 2
#define mmCM0_CM_SHAPER_RAMB_REGION_0_1 0x0dcd
#define mmCM0_CM_SHAPER_RAMB_REGION_0_1_BASE_IDX 2
#define mmCM0_CM_SHAPER_RAMB_REGION_2_3 0x0dce
#define mmCM0_CM_SHAPER_RAMB_REGION_2_3_BASE_IDX 2
#define mmCM0_CM_SHAPER_RAMB_REGION_4_5 0x0dcf
#define mmCM0_CM_SHAPER_RAMB_REGION_4_5_BASE_IDX 2
#define mmCM0_CM_SHAPER_RAMB_REGION_6_7 0x0dd0
#define mmCM0_CM_SHAPER_RAMB_REGION_6_7_BASE_IDX 2
#define mmCM0_CM_SHAPER_RAMB_REGION_8_9 0x0dd1
#define mmCM0_CM_SHAPER_RAMB_REGION_8_9_BASE_IDX 2
#define mmCM0_CM_SHAPER_RAMB_REGION_10_11 0x0dd2
#define mmCM0_CM_SHAPER_RAMB_REGION_10_11_BASE_IDX 2
#define mmCM0_CM_SHAPER_RAMB_REGION_12_13 0x0dd3
#define mmCM0_CM_SHAPER_RAMB_REGION_12_13_BASE_IDX 2
#define mmCM0_CM_SHAPER_RAMB_REGION_14_15 0x0dd4
#define mmCM0_CM_SHAPER_RAMB_REGION_14_15_BASE_IDX 2
#define mmCM0_CM_SHAPER_RAMB_REGION_16_17 0x0dd5
#define mmCM0_CM_SHAPER_RAMB_REGION_16_17_BASE_IDX 2
#define mmCM0_CM_SHAPER_RAMB_REGION_18_19 0x0dd6
#define mmCM0_CM_SHAPER_RAMB_REGION_18_19_BASE_IDX 2
#define mmCM0_CM_SHAPER_RAMB_REGION_20_21 0x0dd7
#define mmCM0_CM_SHAPER_RAMB_REGION_20_21_BASE_IDX 2
#define mmCM0_CM_SHAPER_RAMB_REGION_22_23 0x0dd8
#define mmCM0_CM_SHAPER_RAMB_REGION_22_23_BASE_IDX 2
#define mmCM0_CM_SHAPER_RAMB_REGION_24_25 0x0dd9
#define mmCM0_CM_SHAPER_RAMB_REGION_24_25_BASE_IDX 2
#define mmCM0_CM_SHAPER_RAMB_REGION_26_27 0x0dda
#define mmCM0_CM_SHAPER_RAMB_REGION_26_27_BASE_IDX 2
#define mmCM0_CM_SHAPER_RAMB_REGION_28_29 0x0ddb
#define mmCM0_CM_SHAPER_RAMB_REGION_28_29_BASE_IDX 2
#define mmCM0_CM_SHAPER_RAMB_REGION_30_31 0x0ddc
#define mmCM0_CM_SHAPER_RAMB_REGION_30_31_BASE_IDX 2
#define mmCM0_CM_SHAPER_RAMB_REGION_32_33 0x0ddd
#define mmCM0_CM_SHAPER_RAMB_REGION_32_33_BASE_IDX 2
#define mmCM0_CM_MEM_PWR_CTRL2 0x0dde
#define mmCM0_CM_MEM_PWR_CTRL2_BASE_IDX 2
#define mmCM0_CM_MEM_PWR_STATUS2 0x0ddf
#define mmCM0_CM_MEM_PWR_STATUS2_BASE_IDX 2
#define mmCM0_CM_3DLUT_MODE 0x0de0
#define mmCM0_CM_3DLUT_MODE_BASE_IDX 2
#define mmCM0_CM_3DLUT_INDEX 0x0de1
#define mmCM0_CM_3DLUT_INDEX_BASE_IDX 2
#define mmCM0_CM_3DLUT_DATA 0x0de2
#define mmCM0_CM_3DLUT_DATA_BASE_IDX 2
#define mmCM0_CM_3DLUT_DATA_30BIT 0x0de3
#define mmCM0_CM_3DLUT_DATA_30BIT_BASE_IDX 2
#define mmCM0_CM_3DLUT_READ_WRITE_CONTROL 0x0de4
#define mmCM0_CM_3DLUT_READ_WRITE_CONTROL_BASE_IDX 2
#define mmCM0_CM_3DLUT_OUT_NORM_FACTOR 0x0de5
#define mmCM0_CM_3DLUT_OUT_NORM_FACTOR_BASE_IDX 2
#define mmCM0_CM_3DLUT_OUT_OFFSET_R 0x0de6
#define mmCM0_CM_3DLUT_OUT_OFFSET_R_BASE_IDX 2
#define mmCM0_CM_3DLUT_OUT_OFFSET_G 0x0de7
#define mmCM0_CM_3DLUT_OUT_OFFSET_G_BASE_IDX 2
#define mmCM0_CM_3DLUT_OUT_OFFSET_B 0x0de8
#define mmCM0_CM_3DLUT_OUT_OFFSET_B_BASE_IDX 2
#define mmCM0_CM_TEST_DEBUG_INDEX 0x0de9
#define mmCM0_CM_TEST_DEBUG_INDEX_BASE_IDX 2
#define mmCM0_CM_TEST_DEBUG_DATA 0x0dea
#define mmCM0_CM_TEST_DEBUG_DATA_BASE_IDX 2
// addressBlock: dce_dc_dpp1_dispdec_dpp_top_dispdec
// base address: 0x5ac
#define mmDPP_TOP1_DPP_CONTROL 0x0e30
#define mmDPP_TOP1_DPP_CONTROL_BASE_IDX 2
#define mmDPP_TOP1_DPP_SOFT_RESET 0x0e31
#define mmDPP_TOP1_DPP_SOFT_RESET_BASE_IDX 2
#define mmDPP_TOP1_DPP_CRC_VAL_R_G 0x0e32
#define mmDPP_TOP1_DPP_CRC_VAL_R_G_BASE_IDX 2
#define mmDPP_TOP1_DPP_CRC_VAL_B_A 0x0e33
#define mmDPP_TOP1_DPP_CRC_VAL_B_A_BASE_IDX 2
#define mmDPP_TOP1_DPP_CRC_CTRL 0x0e34
#define mmDPP_TOP1_DPP_CRC_CTRL_BASE_IDX 2
#define mmDPP_TOP1_HOST_READ_CONTROL 0x0e35
#define mmDPP_TOP1_HOST_READ_CONTROL_BASE_IDX 2
// addressBlock: dce_dc_dpp1_dispdec_cnvc_cfg_dispdec
// base address: 0x5ac
#define mmCNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT 0x0e3a
#define mmCNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX 2
#define mmCNVC_CFG1_FORMAT_CONTROL 0x0e3b
#define mmCNVC_CFG1_FORMAT_CONTROL_BASE_IDX 2
#define mmCNVC_CFG1_FCNV_FP_BIAS_R 0x0e3c
#define mmCNVC_CFG1_FCNV_FP_BIAS_R_BASE_IDX 2
#define mmCNVC_CFG1_FCNV_FP_BIAS_G 0x0e3d
#define mmCNVC_CFG1_FCNV_FP_BIAS_G_BASE_IDX 2
#define mmCNVC_CFG1_FCNV_FP_BIAS_B 0x0e3e
#define mmCNVC_CFG1_FCNV_FP_BIAS_B_BASE_IDX 2
#define mmCNVC_CFG1_FCNV_FP_SCALE_R 0x0e3f
#define mmCNVC_CFG1_FCNV_FP_SCALE_R_BASE_IDX 2
#define mmCNVC_CFG1_FCNV_FP_SCALE_G 0x0e40
#define mmCNVC_CFG1_FCNV_FP_SCALE_G_BASE_IDX 2
#define mmCNVC_CFG1_FCNV_FP_SCALE_B 0x0e41
#define mmCNVC_CFG1_FCNV_FP_SCALE_B_BASE_IDX 2
#define mmCNVC_CFG1_COLOR_KEYER_CONTROL 0x0e42
#define mmCNVC_CFG1_COLOR_KEYER_CONTROL_BASE_IDX 2
#define mmCNVC_CFG1_COLOR_KEYER_ALPHA 0x0e43
#define mmCNVC_CFG1_COLOR_KEYER_ALPHA_BASE_IDX 2
#define mmCNVC_CFG1_COLOR_KEYER_RED 0x0e44
#define mmCNVC_CFG1_COLOR_KEYER_RED_BASE_IDX 2
#define mmCNVC_CFG1_COLOR_KEYER_GREEN 0x0e45
#define mmCNVC_CFG1_COLOR_KEYER_GREEN_BASE_IDX 2
#define mmCNVC_CFG1_COLOR_KEYER_BLUE 0x0e46
#define mmCNVC_CFG1_COLOR_KEYER_BLUE_BASE_IDX 2
#define mmCNVC_CFG1_ALPHA_2BIT_LUT 0x0e48
#define mmCNVC_CFG1_ALPHA_2BIT_LUT_BASE_IDX 2
// addressBlock: dce_dc_dpp1_dispdec_cnvc_cur_dispdec
// base address: 0x5ac
#define mmCNVC_CUR1_CURSOR0_CONTROL 0x0e4b
#define mmCNVC_CUR1_CURSOR0_CONTROL_BASE_IDX 2
#define mmCNVC_CUR1_CURSOR0_COLOR0 0x0e4c
#define mmCNVC_CUR1_CURSOR0_COLOR0_BASE_IDX 2
#define mmCNVC_CUR1_CURSOR0_COLOR1 0x0e4d
#define mmCNVC_CUR1_CURSOR0_COLOR1_BASE_IDX 2
#define mmCNVC_CUR1_CURSOR0_FP_SCALE_BIAS 0x0e4e
#define mmCNVC_CUR1_CURSOR0_FP_SCALE_BIAS_BASE_IDX 2
// addressBlock: dce_dc_dpp1_dispdec_dscl_dispdec
// base address: 0x5ac
#define mmDSCL1_SCL_COEF_RAM_TAP_SELECT 0x0e55
#define mmDSCL1_SCL_COEF_RAM_TAP_SELECT_BASE_IDX 2
#define mmDSCL1_SCL_COEF_RAM_TAP_DATA 0x0e56
#define mmDSCL1_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2
#define mmDSCL1_SCL_MODE 0x0e57
#define mmDSCL1_SCL_MODE_BASE_IDX 2
#define mmDSCL1_SCL_TAP_CONTROL 0x0e58
#define mmDSCL1_SCL_TAP_CONTROL_BASE_IDX 2
#define mmDSCL1_DSCL_CONTROL 0x0e59
#define mmDSCL1_DSCL_CONTROL_BASE_IDX 2
#define mmDSCL1_DSCL_2TAP_CONTROL 0x0e5a
#define mmDSCL1_DSCL_2TAP_CONTROL_BASE_IDX 2
#define mmDSCL1_SCL_MANUAL_REPLICATE_CONTROL 0x0e5b
#define mmDSCL1_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2
#define mmDSCL1_SCL_HORZ_FILTER_SCALE_RATIO 0x0e5c
#define mmDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2
#define mmDSCL1_SCL_HORZ_FILTER_INIT 0x0e5d
#define mmDSCL1_SCL_HORZ_FILTER_INIT_BASE_IDX 2
#define mmDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C 0x0e5e
#define mmDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2
#define mmDSCL1_SCL_HORZ_FILTER_INIT_C 0x0e5f
#define mmDSCL1_SCL_HORZ_FILTER_INIT_C_BASE_IDX 2
#define mmDSCL1_SCL_VERT_FILTER_SCALE_RATIO 0x0e60
#define mmDSCL1_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2
#define mmDSCL1_SCL_VERT_FILTER_INIT 0x0e61
#define mmDSCL1_SCL_VERT_FILTER_INIT_BASE_IDX 2
#define mmDSCL1_SCL_VERT_FILTER_INIT_BOT 0x0e62
#define mmDSCL1_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2
#define mmDSCL1_SCL_VERT_FILTER_SCALE_RATIO_C 0x0e63
#define mmDSCL1_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2
#define mmDSCL1_SCL_VERT_FILTER_INIT_C 0x0e64
#define mmDSCL1_SCL_VERT_FILTER_INIT_C_BASE_IDX 2
#define mmDSCL1_SCL_VERT_FILTER_INIT_BOT_C 0x0e65
#define mmDSCL1_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX 2
#define mmDSCL1_SCL_BLACK_OFFSET 0x0e66
#define mmDSCL1_SCL_BLACK_OFFSET_BASE_IDX 2
#define mmDSCL1_DSCL_UPDATE 0x0e67
#define mmDSCL1_DSCL_UPDATE_BASE_IDX 2
#define mmDSCL1_DSCL_AUTOCAL 0x0e68
#define mmDSCL1_DSCL_AUTOCAL_BASE_IDX 2
#define mmDSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT 0x0e69
#define mmDSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2
#define mmDSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM 0x0e6a
#define mmDSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2
#define mmDSCL1_OTG_H_BLANK 0x0e6b
#define mmDSCL1_OTG_H_BLANK_BASE_IDX 2
#define mmDSCL1_OTG_V_BLANK 0x0e6c
#define mmDSCL1_OTG_V_BLANK_BASE_IDX 2
#define mmDSCL1_RECOUT_START 0x0e6d
#define mmDSCL1_RECOUT_START_BASE_IDX 2
#define mmDSCL1_RECOUT_SIZE 0x0e6e
#define mmDSCL1_RECOUT_SIZE_BASE_IDX 2
#define mmDSCL1_MPC_SIZE 0x0e6f
#define mmDSCL1_MPC_SIZE_BASE_IDX 2
#define mmDSCL1_LB_DATA_FORMAT 0x0e70
#define mmDSCL1_LB_DATA_FORMAT_BASE_IDX 2
#define mmDSCL1_LB_MEMORY_CTRL 0x0e71
#define mmDSCL1_LB_MEMORY_CTRL_BASE_IDX 2
#define mmDSCL1_LB_V_COUNTER 0x0e72
#define mmDSCL1_LB_V_COUNTER_BASE_IDX 2
#define mmDSCL1_DSCL_MEM_PWR_CTRL 0x0e73
#define mmDSCL1_DSCL_MEM_PWR_CTRL_BASE_IDX 2
#define mmDSCL1_DSCL_MEM_PWR_STATUS 0x0e74
#define mmDSCL1_DSCL_MEM_PWR_STATUS_BASE_IDX 2
#define mmDSCL1_OBUF_CONTROL 0x0e75
#define mmDSCL1_OBUF_CONTROL_BASE_IDX 2
#define mmDSCL1_OBUF_MEM_PWR_CTRL 0x0e76
#define mmDSCL1_OBUF_MEM_PWR_CTRL_BASE_IDX 2
// addressBlock: dce_dc_dpp1_dispdec_cm_dispdec
// base address: 0x5ac
#define mmCM1_CM_CONTROL 0x0e85
#define mmCM1_CM_CONTROL_BASE_IDX 2
#define mmCM1_CM_ICSC_CONTROL 0x0e86
#define mmCM1_CM_ICSC_CONTROL_BASE_IDX 2
#define mmCM1_CM_ICSC_C11_C12 0x0e87
#define mmCM1_CM_ICSC_C11_C12_BASE_IDX 2
#define mmCM1_CM_ICSC_C13_C14 0x0e88
#define mmCM1_CM_ICSC_C13_C14_BASE_IDX 2
#define mmCM1_CM_ICSC_C21_C22 0x0e89
#define mmCM1_CM_ICSC_C21_C22_BASE_IDX 2
#define mmCM1_CM_ICSC_C23_C24 0x0e8a
#define mmCM1_CM_ICSC_C23_C24_BASE_IDX 2
#define mmCM1_CM_ICSC_C31_C32 0x0e8b
#define mmCM1_CM_ICSC_C31_C32_BASE_IDX 2
#define mmCM1_CM_ICSC_C33_C34 0x0e8c
#define mmCM1_CM_ICSC_C33_C34_BASE_IDX 2
#define mmCM1_CM_ICSC_B_C11_C12 0x0e8d
#define mmCM1_CM_ICSC_B_C11_C12_BASE_IDX 2
#define mmCM1_CM_ICSC_B_C13_C14 0x0e8e
#define mmCM1_CM_ICSC_B_C13_C14_BASE_IDX 2
#define mmCM1_CM_ICSC_B_C21_C22 0x0e8f
#define mmCM1_CM_ICSC_B_C21_C22_BASE_IDX 2
#define mmCM1_CM_ICSC_B_C23_C24 0x0e90
#define mmCM1_CM_ICSC_B_C23_C24_BASE_IDX 2
#define mmCM1_CM_ICSC_B_C31_C32 0x0e91
#define mmCM1_CM_ICSC_B_C31_C32_BASE_IDX 2
#define mmCM1_CM_ICSC_B_C33_C34 0x0e92
#define mmCM1_CM_ICSC_B_C33_C34_BASE_IDX 2
#define mmCM1_CM_GAMUT_REMAP_CONTROL 0x0e93
#define mmCM1_CM_GAMUT_REMAP_CONTROL_BASE_IDX 2
#define mmCM1_CM_GAMUT_REMAP_C11_C12 0x0e94
#define mmCM1_CM_GAMUT_REMAP_C11_C12_BASE_IDX 2
#define mmCM1_CM_GAMUT_REMAP_C13_C14 0x0e95
#define mmCM1_CM_GAMUT_REMAP_C13_C14_BASE_IDX 2
#define mmCM1_CM_GAMUT_REMAP_C21_C22 0x0e96
#define mmCM1_CM_GAMUT_REMAP_C21_C22_BASE_IDX 2
#define mmCM1_CM_GAMUT_REMAP_C23_C24 0x0e97
#define mmCM1_CM_GAMUT_REMAP_C23_C24_BASE_IDX 2
#define mmCM1_CM_GAMUT_REMAP_C31_C32 0x0e98
#define mmCM1_CM_GAMUT_REMAP_C31_C32_BASE_IDX 2
#define mmCM1_CM_GAMUT_REMAP_C33_C34 0x0e99
#define mmCM1_CM_GAMUT_REMAP_C33_C34_BASE_IDX 2
#define mmCM1_CM_GAMUT_REMAP_B_C11_C12 0x0e9a
#define mmCM1_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX 2
#define mmCM1_CM_GAMUT_REMAP_B_C13_C14 0x0e9b
#define mmCM1_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX 2
#define mmCM1_CM_GAMUT_REMAP_B_C21_C22 0x0e9c
#define mmCM1_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX 2
#define mmCM1_CM_GAMUT_REMAP_B_C23_C24 0x0e9d
#define mmCM1_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX 2
#define mmCM1_CM_GAMUT_REMAP_B_C31_C32 0x0e9e
#define mmCM1_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX 2
#define mmCM1_CM_GAMUT_REMAP_B_C33_C34 0x0e9f
#define mmCM1_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX 2
#define mmCM1_CM_BIAS_CR_R 0x0ea0
#define mmCM1_CM_BIAS_CR_R_BASE_IDX 2
#define mmCM1_CM_BIAS_Y_G_CB_B 0x0ea1
#define mmCM1_CM_BIAS_Y_G_CB_B_BASE_IDX 2
#define mmCM1_CM_DGAM_CONTROL 0x0ea2
#define mmCM1_CM_DGAM_CONTROL_BASE_IDX 2
#define mmCM1_CM_DGAM_LUT_INDEX 0x0ea3
#define mmCM1_CM_DGAM_LUT_INDEX_BASE_IDX 2
#define mmCM1_CM_DGAM_LUT_DATA 0x0ea4
#define mmCM1_CM_DGAM_LUT_DATA_BASE_IDX 2
#define mmCM1_CM_DGAM_LUT_WRITE_EN_MASK 0x0ea5
#define mmCM1_CM_DGAM_LUT_WRITE_EN_MASK_BASE_IDX 2
#define mmCM1_CM_DGAM_RAMA_START_CNTL_B 0x0ea6
#define mmCM1_CM_DGAM_RAMA_START_CNTL_B_BASE_IDX 2
#define mmCM1_CM_DGAM_RAMA_START_CNTL_G 0x0ea7
#define mmCM1_CM_DGAM_RAMA_START_CNTL_G_BASE_IDX 2
#define mmCM1_CM_DGAM_RAMA_START_CNTL_R 0x0ea8
#define mmCM1_CM_DGAM_RAMA_START_CNTL_R_BASE_IDX 2
#define mmCM1_CM_DGAM_RAMA_SLOPE_CNTL_B 0x0ea9
#define mmCM1_CM_DGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2
#define mmCM1_CM_DGAM_RAMA_SLOPE_CNTL_G 0x0eaa
#define mmCM1_CM_DGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2
#define mmCM1_CM_DGAM_RAMA_SLOPE_CNTL_R 0x0eab
#define mmCM1_CM_DGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2
#define mmCM1_CM_DGAM_RAMA_END_CNTL1_B 0x0eac
#define mmCM1_CM_DGAM_RAMA_END_CNTL1_B_BASE_IDX 2
#define mmCM1_CM_DGAM_RAMA_END_CNTL2_B 0x0ead
#define mmCM1_CM_DGAM_RAMA_END_CNTL2_B_BASE_IDX 2
#define mmCM1_CM_DGAM_RAMA_END_CNTL1_G 0x0eae
#define mmCM1_CM_DGAM_RAMA_END_CNTL1_G_BASE_IDX 2
#define mmCM1_CM_DGAM_RAMA_END_CNTL2_G 0x0eaf
#define mmCM1_CM_DGAM_RAMA_END_CNTL2_G_BASE_IDX 2
#define mmCM1_CM_DGAM_RAMA_END_CNTL1_R 0x0eb0
#define mmCM1_CM_DGAM_RAMA_END_CNTL1_R_BASE_IDX 2
#define mmCM1_CM_DGAM_RAMA_END_CNTL2_R 0x0eb1
#define mmCM1_CM_DGAM_RAMA_END_CNTL2_R_BASE_IDX 2
#define mmCM1_CM_DGAM_RAMA_REGION_0_1 0x0eb2
#define mmCM1_CM_DGAM_RAMA_REGION_0_1_BASE_IDX 2
#define mmCM1_CM_DGAM_RAMA_REGION_2_3 0x0eb3
#define mmCM1_CM_DGAM_RAMA_REGION_2_3_BASE_IDX 2
#define mmCM1_CM_DGAM_RAMA_REGION_4_5 0x0eb4
#define mmCM1_CM_DGAM_RAMA_REGION_4_5_BASE_IDX 2
#define mmCM1_CM_DGAM_RAMA_REGION_6_7 0x0eb5
#define mmCM1_CM_DGAM_RAMA_REGION_6_7_BASE_IDX 2
#define mmCM1_CM_DGAM_RAMA_REGION_8_9 0x0eb6
#define mmCM1_CM_DGAM_RAMA_REGION_8_9_BASE_IDX 2
#define mmCM1_CM_DGAM_RAMA_REGION_10_11 0x0eb7
#define mmCM1_CM_DGAM_RAMA_REGION_10_11_BASE_IDX 2
#define mmCM1_CM_DGAM_RAMA_REGION_12_13 0x0eb8
#define mmCM1_CM_DGAM_RAMA_REGION_12_13_BASE_IDX 2
#define mmCM1_CM_DGAM_RAMA_REGION_14_15 0x0eb9
#define mmCM1_CM_DGAM_RAMA_REGION_14_15_BASE_IDX 2
#define mmCM1_CM_DGAM_RAMB_START_CNTL_B 0x0eba
#define mmCM1_CM_DGAM_RAMB_START_CNTL_B_BASE_IDX 2
#define mmCM1_CM_DGAM_RAMB_START_CNTL_G 0x0ebb
#define mmCM1_CM_DGAM_RAMB_START_CNTL_G_BASE_IDX 2
#define mmCM1_CM_DGAM_RAMB_START_CNTL_R 0x0ebc
#define mmCM1_CM_DGAM_RAMB_START_CNTL_R_BASE_IDX 2
#define mmCM1_CM_DGAM_RAMB_SLOPE_CNTL_B 0x0ebd
#define mmCM1_CM_DGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2
#define mmCM1_CM_DGAM_RAMB_SLOPE_CNTL_G 0x0ebe
#define mmCM1_CM_DGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2
#define mmCM1_CM_DGAM_RAMB_SLOPE_CNTL_R 0x0ebf
#define mmCM1_CM_DGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2
#define mmCM1_CM_DGAM_RAMB_END_CNTL1_B 0x0ec0
#define mmCM1_CM_DGAM_RAMB_END_CNTL1_B_BASE_IDX 2
#define mmCM1_CM_DGAM_RAMB_END_CNTL2_B 0x0ec1
#define mmCM1_CM_DGAM_RAMB_END_CNTL2_B_BASE_IDX 2
#define mmCM1_CM_DGAM_RAMB_END_CNTL1_G 0x0ec2
#define mmCM1_CM_DGAM_RAMB_END_CNTL1_G_BASE_IDX 2
#define mmCM1_CM_DGAM_RAMB_END_CNTL2_G 0x0ec3
#define mmCM1_CM_DGAM_RAMB_END_CNTL2_G_BASE_IDX 2
#define mmCM1_CM_DGAM_RAMB_END_CNTL1_R 0x0ec4
#define mmCM1_CM_DGAM_RAMB_END_CNTL1_R_BASE_IDX 2
#define mmCM1_CM_DGAM_RAMB_END_CNTL2_R 0x0ec5
#define mmCM1_CM_DGAM_RAMB_END_CNTL2_R_BASE_IDX 2
#define mmCM1_CM_DGAM_RAMB_REGION_0_1 0x0ec6
#define mmCM1_CM_DGAM_RAMB_REGION_0_1_BASE_IDX 2
#define mmCM1_CM_DGAM_RAMB_REGION_2_3 0x0ec7
#define mmCM1_CM_DGAM_RAMB_REGION_2_3_BASE_IDX 2
#define mmCM1_CM_DGAM_RAMB_REGION_4_5 0x0ec8
#define mmCM1_CM_DGAM_RAMB_REGION_4_5_BASE_IDX 2
#define mmCM1_CM_DGAM_RAMB_REGION_6_7 0x0ec9
#define mmCM1_CM_DGAM_RAMB_REGION_6_7_BASE_IDX 2
#define mmCM1_CM_DGAM_RAMB_REGION_8_9 0x0eca
#define mmCM1_CM_DGAM_RAMB_REGION_8_9_BASE_IDX 2
#define mmCM1_CM_DGAM_RAMB_REGION_10_11 0x0ecb
#define mmCM1_CM_DGAM_RAMB_REGION_10_11_BASE_IDX 2
#define mmCM1_CM_DGAM_RAMB_REGION_12_13 0x0ecc
#define mmCM1_CM_DGAM_RAMB_REGION_12_13_BASE_IDX 2
#define mmCM1_CM_DGAM_RAMB_REGION_14_15 0x0ecd
#define mmCM1_CM_DGAM_RAMB_REGION_14_15_BASE_IDX 2
#define mmCM1_CM_BLNDGAM_CONTROL 0x0ece
#define mmCM1_CM_BLNDGAM_CONTROL_BASE_IDX 2
#define mmCM1_CM_BLNDGAM_LUT_INDEX 0x0ecf
#define mmCM1_CM_BLNDGAM_LUT_INDEX_BASE_IDX 2
#define mmCM1_CM_BLNDGAM_LUT_DATA 0x0ed0
#define mmCM1_CM_BLNDGAM_LUT_DATA_BASE_IDX 2
#define mmCM1_CM_BLNDGAM_LUT_WRITE_EN_MASK 0x0ed1
#define mmCM1_CM_BLNDGAM_LUT_WRITE_EN_MASK_BASE_IDX 2
#define mmCM1_CM_BLNDGAM_RAMA_START_CNTL_B 0x0ed2
#define mmCM1_CM_BLNDGAM_RAMA_START_CNTL_B_BASE_IDX 2
#define mmCM1_CM_BLNDGAM_RAMA_START_CNTL_G 0x0ed3
#define mmCM1_CM_BLNDGAM_RAMA_START_CNTL_G_BASE_IDX 2
#define mmCM1_CM_BLNDGAM_RAMA_START_CNTL_R 0x0ed4
#define mmCM1_CM_BLNDGAM_RAMA_START_CNTL_R_BASE_IDX 2
#define mmCM1_CM_BLNDGAM_RAMA_SLOPE_CNTL_B 0x0ed5
#define mmCM1_CM_BLNDGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2
#define mmCM1_CM_BLNDGAM_RAMA_SLOPE_CNTL_G 0x0ed6
#define mmCM1_CM_BLNDGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2
#define mmCM1_CM_BLNDGAM_RAMA_SLOPE_CNTL_R 0x0ed7
#define mmCM1_CM_BLNDGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2
#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL1_B 0x0ed8
#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL1_B_BASE_IDX 2
#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL2_B 0x0ed9
#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL2_B_BASE_IDX 2
#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL1_G 0x0eda
#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL1_G_BASE_IDX 2
#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL2_G 0x0edb
#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL2_G_BASE_IDX 2
#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL1_R 0x0edc
#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL1_R_BASE_IDX 2
#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL2_R 0x0edd
#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL2_R_BASE_IDX 2
#define mmCM1_CM_BLNDGAM_RAMA_REGION_0_1 0x0ede
#define mmCM1_CM_BLNDGAM_RAMA_REGION_0_1_BASE_IDX 2
#define mmCM1_CM_BLNDGAM_RAMA_REGION_2_3 0x0edf
#define mmCM1_CM_BLNDGAM_RAMA_REGION_2_3_BASE_IDX 2
#define mmCM1_CM_BLNDGAM_RAMA_REGION_4_5 0x0ee0
#define mmCM1_CM_BLNDGAM_RAMA_REGION_4_5_BASE_IDX 2
#define mmCM1_CM_BLNDGAM_RAMA_REGION_6_7 0x0ee1
#define mmCM1_CM_BLNDGAM_RAMA_REGION_6_7_BASE_IDX 2
#define mmCM1_CM_BLNDGAM_RAMA_REGION_8_9 0x0ee2
#define mmCM1_CM_BLNDGAM_RAMA_REGION_8_9_BASE_IDX 2
#define mmCM1_CM_BLNDGAM_RAMA_REGION_10_11 0x0ee3
#define mmCM1_CM_BLNDGAM_RAMA_REGION_10_11_BASE_IDX 2
#define mmCM1_CM_BLNDGAM_RAMA_REGION_12_13 0x0ee4
#define mmCM1_CM_BLNDGAM_RAMA_REGION_12_13_BASE_IDX 2
#define mmCM1_CM_BLNDGAM_RAMA_REGION_14_15 0x0ee5
#define mmCM1_CM_BLNDGAM_RAMA_REGION_14_15_BASE_IDX 2
#define mmCM1_CM_BLNDGAM_RAMA_REGION_16_17 0x0ee6
#define mmCM1_CM_BLNDGAM_RAMA_REGION_16_17_BASE_IDX 2
#define mmCM1_CM_BLNDGAM_RAMA_REGION_18_19 0x0ee7
#define mmCM1_CM_BLNDGAM_RAMA_REGION_18_19_BASE_IDX 2
#define mmCM1_CM_BLNDGAM_RAMA_REGION_20_21 0x0ee8
#define mmCM1_CM_BLNDGAM_RAMA_REGION_20_21_BASE_IDX 2
#define mmCM1_CM_BLNDGAM_RAMA_REGION_22_23 0x0ee9
#define mmCM1_CM_BLNDGAM_RAMA_REGION_22_23_BASE_IDX 2
#define mmCM1_CM_BLNDGAM_RAMA_REGION_24_25 0x0eea
#define mmCM1_CM_BLNDGAM_RAMA_REGION_24_25_BASE_IDX 2
#define mmCM1_CM_BLNDGAM_RAMA_REGION_26_27 0x0eeb
#define mmCM1_CM_BLNDGAM_RAMA_REGION_26_27_BASE_IDX 2
#define mmCM1_CM_BLNDGAM_RAMA_REGION_28_29 0x0eec
#define mmCM1_CM_BLNDGAM_RAMA_REGION_28_29_BASE_IDX 2
#define mmCM1_CM_BLNDGAM_RAMA_REGION_30_31 0x0eed
#define mmCM1_CM_BLNDGAM_RAMA_REGION_30_31_BASE_IDX 2
#define mmCM1_CM_BLNDGAM_RAMA_REGION_32_33 0x0eee
#define mmCM1_CM_BLNDGAM_RAMA_REGION_32_33_BASE_IDX 2
#define mmCM1_CM_BLNDGAM_RAMB_START_CNTL_B 0x0eef
#define mmCM1_CM_BLNDGAM_RAMB_START_CNTL_B_BASE_IDX 2
#define mmCM1_CM_BLNDGAM_RAMB_START_CNTL_G 0x0ef0
#define mmCM1_CM_BLNDGAM_RAMB_START_CNTL_G_BASE_IDX 2
#define mmCM1_CM_BLNDGAM_RAMB_START_CNTL_R 0x0ef1
#define mmCM1_CM_BLNDGAM_RAMB_START_CNTL_R_BASE_IDX 2
#define mmCM1_CM_BLNDGAM_RAMB_SLOPE_CNTL_B 0x0ef2
#define mmCM1_CM_BLNDGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2
#define mmCM1_CM_BLNDGAM_RAMB_SLOPE_CNTL_G 0x0ef3
#define mmCM1_CM_BLNDGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2
#define mmCM1_CM_BLNDGAM_RAMB_SLOPE_CNTL_R 0x0ef4
#define mmCM1_CM_BLNDGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2
#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL1_B 0x0ef5
#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL1_B_BASE_IDX 2
#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL2_B 0x0ef6
#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL2_B_BASE_IDX 2
#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL1_G 0x0ef7
#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL1_G_BASE_IDX 2
#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL2_G 0x0ef8
#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL2_G_BASE_IDX 2
#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL1_R 0x0ef9
#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL1_R_BASE_IDX 2
#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL2_R 0x0efa
#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL2_R_BASE_IDX 2
#define mmCM1_CM_BLNDGAM_RAMB_REGION_0_1 0x0efb
#define mmCM1_CM_BLNDGAM_RAMB_REGION_0_1_BASE_IDX 2
#define mmCM1_CM_BLNDGAM_RAMB_REGION_2_3 0x0efc
#define mmCM1_CM_BLNDGAM_RAMB_REGION_2_3_BASE_IDX 2
#define mmCM1_CM_BLNDGAM_RAMB_REGION_4_5 0x0efd
#define mmCM1_CM_BLNDGAM_RAMB_REGION_4_5_BASE_IDX 2
#define mmCM1_CM_BLNDGAM_RAMB_REGION_6_7 0x0efe
#define mmCM1_CM_BLNDGAM_RAMB_REGION_6_7_BASE_IDX 2
#define mmCM1_CM_BLNDGAM_RAMB_REGION_8_9 0x0eff
#define mmCM1_CM_BLNDGAM_RAMB_REGION_8_9_BASE_IDX 2
#define mmCM1_CM_BLNDGAM_RAMB_REGION_10_11 0x0f00
#define mmCM1_CM_BLNDGAM_RAMB_REGION_10_11_BASE_IDX 2
#define mmCM1_CM_BLNDGAM_RAMB_REGION_12_13 0x0f01
#define mmCM1_CM_BLNDGAM_RAMB_REGION_12_13_BASE_IDX 2
#define mmCM1_CM_BLNDGAM_RAMB_REGION_14_15 0x0f02
#define mmCM1_CM_BLNDGAM_RAMB_REGION_14_15_BASE_IDX 2
#define mmCM1_CM_BLNDGAM_RAMB_REGION_16_17 0x0f03
#define mmCM1_CM_BLNDGAM_RAMB_REGION_16_17_BASE_IDX 2
#define mmCM1_CM_BLNDGAM_RAMB_REGION_18_19 0x0f04
#define mmCM1_CM_BLNDGAM_RAMB_REGION_18_19_BASE_IDX 2
#define mmCM1_CM_BLNDGAM_RAMB_REGION_20_21 0x0f05
#define mmCM1_CM_BLNDGAM_RAMB_REGION_20_21_BASE_IDX 2
#define mmCM1_CM_BLNDGAM_RAMB_REGION_22_23 0x0f06
#define mmCM1_CM_BLNDGAM_RAMB_REGION_22_23_BASE_IDX 2
#define mmCM1_CM_BLNDGAM_RAMB_REGION_24_25 0x0f07
#define mmCM1_CM_BLNDGAM_RAMB_REGION_24_25_BASE_IDX 2
#define mmCM1_CM_BLNDGAM_RAMB_REGION_26_27 0x0f08
#define mmCM1_CM_BLNDGAM_RAMB_REGION_26_27_BASE_IDX 2
#define mmCM1_CM_BLNDGAM_RAMB_REGION_28_29 0x0f09
#define mmCM1_CM_BLNDGAM_RAMB_REGION_28_29_BASE_IDX 2
#define mmCM1_CM_BLNDGAM_RAMB_REGION_30_31 0x0f0a
#define mmCM1_CM_BLNDGAM_RAMB_REGION_30_31_BASE_IDX 2
#define mmCM1_CM_BLNDGAM_RAMB_REGION_32_33 0x0f0b
#define mmCM1_CM_BLNDGAM_RAMB_REGION_32_33_BASE_IDX 2
#define mmCM1_CM_HDR_MULT_COEF 0x0f0c
#define mmCM1_CM_HDR_MULT_COEF_BASE_IDX 2
#define mmCM1_CM_MEM_PWR_CTRL 0x0f0d
#define mmCM1_CM_MEM_PWR_CTRL_BASE_IDX 2
#define mmCM1_CM_MEM_PWR_STATUS 0x0f0e
#define mmCM1_CM_MEM_PWR_STATUS_BASE_IDX 2
#define mmCM1_CM_DEALPHA 0x0f10
#define mmCM1_CM_DEALPHA_BASE_IDX 2
#define mmCM1_CM_COEF_FORMAT 0x0f11
#define mmCM1_CM_COEF_FORMAT_BASE_IDX 2
#define mmCM1_CM_SHAPER_CONTROL 0x0f12
#define mmCM1_CM_SHAPER_CONTROL_BASE_IDX 2
#define mmCM1_CM_SHAPER_OFFSET_R 0x0f13
#define mmCM1_CM_SHAPER_OFFSET_R_BASE_IDX 2
#define mmCM1_CM_SHAPER_OFFSET_G 0x0f14
#define mmCM1_CM_SHAPER_OFFSET_G_BASE_IDX 2
#define mmCM1_CM_SHAPER_OFFSET_B 0x0f15
#define mmCM1_CM_SHAPER_OFFSET_B_BASE_IDX 2
#define mmCM1_CM_SHAPER_SCALE_R 0x0f16
#define mmCM1_CM_SHAPER_SCALE_R_BASE_IDX 2
#define mmCM1_CM_SHAPER_SCALE_G_B 0x0f17
#define mmCM1_CM_SHAPER_SCALE_G_B_BASE_IDX 2
#define mmCM1_CM_SHAPER_LUT_INDEX 0x0f18
#define mmCM1_CM_SHAPER_LUT_INDEX_BASE_IDX 2
#define mmCM1_CM_SHAPER_LUT_DATA 0x0f19
#define mmCM1_CM_SHAPER_LUT_DATA_BASE_IDX 2
#define mmCM1_CM_SHAPER_LUT_WRITE_EN_MASK 0x0f1a
#define mmCM1_CM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX 2
#define mmCM1_CM_SHAPER_RAMA_START_CNTL_B 0x0f1b
#define mmCM1_CM_SHAPER_RAMA_START_CNTL_B_BASE_IDX 2
#define mmCM1_CM_SHAPER_RAMA_START_CNTL_G 0x0f1c
#define mmCM1_CM_SHAPER_RAMA_START_CNTL_G_BASE_IDX 2
#define mmCM1_CM_SHAPER_RAMA_START_CNTL_R 0x0f1d
#define mmCM1_CM_SHAPER_RAMA_START_CNTL_R_BASE_IDX 2
#define mmCM1_CM_SHAPER_RAMA_END_CNTL_B 0x0f1e
#define mmCM1_CM_SHAPER_RAMA_END_CNTL_B_BASE_IDX 2
#define mmCM1_CM_SHAPER_RAMA_END_CNTL_G 0x0f1f
#define mmCM1_CM_SHAPER_RAMA_END_CNTL_G_BASE_IDX 2
#define mmCM1_CM_SHAPER_RAMA_END_CNTL_R 0x0f20
#define mmCM1_CM_SHAPER_RAMA_END_CNTL_R_BASE_IDX 2
#define mmCM1_CM_SHAPER_RAMA_REGION_0_1 0x0f21
#define mmCM1_CM_SHAPER_RAMA_REGION_0_1_BASE_IDX 2
#define mmCM1_CM_SHAPER_RAMA_REGION_2_3 0x0f22
#define mmCM1_CM_SHAPER_RAMA_REGION_2_3_BASE_IDX 2
#define mmCM1_CM_SHAPER_RAMA_REGION_4_5 0x0f23
#define mmCM1_CM_SHAPER_RAMA_REGION_4_5_BASE_IDX 2
#define mmCM1_CM_SHAPER_RAMA_REGION_6_7 0x0f24
#define mmCM1_CM_SHAPER_RAMA_REGION_6_7_BASE_IDX 2
#define mmCM1_CM_SHAPER_RAMA_REGION_8_9 0x0f25
#define mmCM1_CM_SHAPER_RAMA_REGION_8_9_BASE_IDX 2
#define mmCM1_CM_SHAPER_RAMA_REGION_10_11 0x0f26
#define mmCM1_CM_SHAPER_RAMA_REGION_10_11_BASE_IDX 2
#define mmCM1_CM_SHAPER_RAMA_REGION_12_13 0x0f27
#define mmCM1_CM_SHAPER_RAMA_REGION_12_13_BASE_IDX 2
#define mmCM1_CM_SHAPER_RAMA_REGION_14_15 0x0f28
#define mmCM1_CM_SHAPER_RAMA_REGION_14_15_BASE_IDX 2
#define mmCM1_CM_SHAPER_RAMA_REGION_16_17 0x0f29
#define mmCM1_CM_SHAPER_RAMA_REGION_16_17_BASE_IDX 2
#define mmCM1_CM_SHAPER_RAMA_REGION_18_19 0x0f2a
#define mmCM1_CM_SHAPER_RAMA_REGION_18_19_BASE_IDX 2
#define mmCM1_CM_SHAPER_RAMA_REGION_20_21 0x0f2b
#define mmCM1_CM_SHAPER_RAMA_REGION_20_21_BASE_IDX 2
#define mmCM1_CM_SHAPER_RAMA_REGION_22_23 0x0f2c
#define mmCM1_CM_SHAPER_RAMA_REGION_22_23_BASE_IDX 2
#define mmCM1_CM_SHAPER_RAMA_REGION_24_25 0x0f2d
#define mmCM1_CM_SHAPER_RAMA_REGION_24_25_BASE_IDX 2
#define mmCM1_CM_SHAPER_RAMA_REGION_26_27 0x0f2e
#define mmCM1_CM_SHAPER_RAMA_REGION_26_27_BASE_IDX 2
#define mmCM1_CM_SHAPER_RAMA_REGION_28_29 0x0f2f
#define mmCM1_CM_SHAPER_RAMA_REGION_28_29_BASE_IDX 2
#define mmCM1_CM_SHAPER_RAMA_REGION_30_31 0x0f30
#define mmCM1_CM_SHAPER_RAMA_REGION_30_31_BASE_IDX 2
#define mmCM1_CM_SHAPER_RAMA_REGION_32_33 0x0f31
#define mmCM1_CM_SHAPER_RAMA_REGION_32_33_BASE_IDX 2
#define mmCM1_CM_SHAPER_RAMB_START_CNTL_B 0x0f32
#define mmCM1_CM_SHAPER_RAMB_START_CNTL_B_BASE_IDX 2
#define mmCM1_CM_SHAPER_RAMB_START_CNTL_G 0x0f33
#define mmCM1_CM_SHAPER_RAMB_START_CNTL_G_BASE_IDX 2
#define mmCM1_CM_SHAPER_RAMB_START_CNTL_R 0x0f34
#define mmCM1_CM_SHAPER_RAMB_START_CNTL_R_BASE_IDX 2
#define mmCM1_CM_SHAPER_RAMB_END_CNTL_B 0x0f35
#define mmCM1_CM_SHAPER_RAMB_END_CNTL_B_BASE_IDX 2
#define mmCM1_CM_SHAPER_RAMB_END_CNTL_G 0x0f36
#define mmCM1_CM_SHAPER_RAMB_END_CNTL_G_BASE_IDX 2
#define mmCM1_CM_SHAPER_RAMB_END_CNTL_R 0x0f37
#define mmCM1_CM_SHAPER_RAMB_END_CNTL_R_BASE_IDX 2
#define mmCM1_CM_SHAPER_RAMB_REGION_0_1 0x0f38
#define mmCM1_CM_SHAPER_RAMB_REGION_0_1_BASE_IDX 2
#define mmCM1_CM_SHAPER_RAMB_REGION_2_3 0x0f39
#define mmCM1_CM_SHAPER_RAMB_REGION_2_3_BASE_IDX 2
#define mmCM1_CM_SHAPER_RAMB_REGION_4_5 0x0f3a
#define mmCM1_CM_SHAPER_RAMB_REGION_4_5_BASE_IDX 2
#define mmCM1_CM_SHAPER_RAMB_REGION_6_7 0x0f3b
#define mmCM1_CM_SHAPER_RAMB_REGION_6_7_BASE_IDX 2
#define mmCM1_CM_SHAPER_RAMB_REGION_8_9 0x0f3c
#define mmCM1_CM_SHAPER_RAMB_REGION_8_9_BASE_IDX 2
#define mmCM1_CM_SHAPER_RAMB_REGION_10_11 0x0f3d
#define mmCM1_CM_SHAPER_RAMB_REGION_10_11_BASE_IDX 2
#define mmCM1_CM_SHAPER_RAMB_REGION_12_13 0x0f3e
#define mmCM1_CM_SHAPER_RAMB_REGION_12_13_BASE_IDX 2
#define mmCM1_CM_SHAPER_RAMB_REGION_14_15 0x0f3f
#define mmCM1_CM_SHAPER_RAMB_REGION_14_15_BASE_IDX 2
#define mmCM1_CM_SHAPER_RAMB_REGION_16_17 0x0f40
#define mmCM1_CM_SHAPER_RAMB_REGION_16_17_BASE_IDX 2
#define mmCM1_CM_SHAPER_RAMB_REGION_18_19 0x0f41
#define mmCM1_CM_SHAPER_RAMB_REGION_18_19_BASE_IDX 2
#define mmCM1_CM_SHAPER_RAMB_REGION_20_21 0x0f42
#define mmCM1_CM_SHAPER_RAMB_REGION_20_21_BASE_IDX 2
#define mmCM1_CM_SHAPER_RAMB_REGION_22_23 0x0f43
#define mmCM1_CM_SHAPER_RAMB_REGION_22_23_BASE_IDX 2
#define mmCM1_CM_SHAPER_RAMB_REGION_24_25 0x0f44
#define mmCM1_CM_SHAPER_RAMB_REGION_24_25_BASE_IDX 2
#define mmCM1_CM_SHAPER_RAMB_REGION_26_27 0x0f45
#define mmCM1_CM_SHAPER_RAMB_REGION_26_27_BASE_IDX 2
#define mmCM1_CM_SHAPER_RAMB_REGION_28_29 0x0f46
#define mmCM1_CM_SHAPER_RAMB_REGION_28_29_BASE_IDX 2
#define mmCM1_CM_SHAPER_RAMB_REGION_30_31 0x0f47
#define mmCM1_CM_SHAPER_RAMB_REGION_30_31_BASE_IDX 2
#define mmCM1_CM_SHAPER_RAMB_REGION_32_33 0x0f48
#define mmCM1_CM_SHAPER_RAMB_REGION_32_33_BASE_IDX 2
#define mmCM1_CM_MEM_PWR_CTRL2 0x0f49
#define mmCM1_CM_MEM_PWR_CTRL2_BASE_IDX 2
#define mmCM1_CM_MEM_PWR_STATUS2 0x0f4a
#define mmCM1_CM_MEM_PWR_STATUS2_BASE_IDX 2
#define mmCM1_CM_3DLUT_MODE 0x0f4b
#define mmCM1_CM_3DLUT_MODE_BASE_IDX 2
#define mmCM1_CM_3DLUT_INDEX 0x0f4c
#define mmCM1_CM_3DLUT_INDEX_BASE_IDX 2
#define mmCM1_CM_3DLUT_DATA 0x0f4d
#define mmCM1_CM_3DLUT_DATA_BASE_IDX 2
#define mmCM1_CM_3DLUT_DATA_30BIT 0x0f4e
#define mmCM1_CM_3DLUT_DATA_30BIT_BASE_IDX 2
#define mmCM1_CM_3DLUT_READ_WRITE_CONTROL 0x0f4f
#define mmCM1_CM_3DLUT_READ_WRITE_CONTROL_BASE_IDX 2
#define mmCM1_CM_3DLUT_OUT_NORM_FACTOR 0x0f50
#define mmCM1_CM_3DLUT_OUT_NORM_FACTOR_BASE_IDX 2
#define mmCM1_CM_3DLUT_OUT_OFFSET_R 0x0f51
#define mmCM1_CM_3DLUT_OUT_OFFSET_R_BASE_IDX 2
#define mmCM1_CM_3DLUT_OUT_OFFSET_G 0x0f52
#define mmCM1_CM_3DLUT_OUT_OFFSET_G_BASE_IDX 2
#define mmCM1_CM_3DLUT_OUT_OFFSET_B 0x0f53
#define mmCM1_CM_3DLUT_OUT_OFFSET_B_BASE_IDX 2
#define mmCM1_CM_TEST_DEBUG_INDEX 0x0f54
#define mmCM1_CM_TEST_DEBUG_INDEX_BASE_IDX 2
#define mmCM1_CM_TEST_DEBUG_DATA 0x0f55
#define mmCM1_CM_TEST_DEBUG_DATA_BASE_IDX 2
// addressBlock: dce_dc_dpp2_dispdec_dpp_top_dispdec
// base address: 0xb58
#define mmDPP_TOP2_DPP_CONTROL 0x0f9b
#define mmDPP_TOP2_DPP_CONTROL_BASE_IDX 2
#define mmDPP_TOP2_DPP_SOFT_RESET 0x0f9c
#define mmDPP_TOP2_DPP_SOFT_RESET_BASE_IDX 2
#define mmDPP_TOP2_DPP_CRC_VAL_R_G 0x0f9d
#define mmDPP_TOP2_DPP_CRC_VAL_R_G_BASE_IDX 2
#define mmDPP_TOP2_DPP_CRC_VAL_B_A 0x0f9e
#define mmDPP_TOP2_DPP_CRC_VAL_B_A_BASE_IDX 2
#define mmDPP_TOP2_DPP_CRC_CTRL 0x0f9f
#define mmDPP_TOP2_DPP_CRC_CTRL_BASE_IDX 2
// addressBlock: dce_dc_dpp2_dispdec_cnvc_cfg_dispdec
// base address: 0xb58
#define mmCNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT 0x0fa5
#define mmCNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX 2
#define mmCNVC_CFG2_FORMAT_CONTROL 0x0fa6
#define mmCNVC_CFG2_FORMAT_CONTROL_BASE_IDX 2
#define mmCNVC_CFG2_FCNV_FP_BIAS_R 0x0fa7
#define mmCNVC_CFG2_FCNV_FP_BIAS_R_BASE_IDX 2
#define mmCNVC_CFG2_FCNV_FP_BIAS_G 0x0fa8
#define mmCNVC_CFG2_FCNV_FP_BIAS_G_BASE_IDX 2
#define mmCNVC_CFG2_FCNV_FP_BIAS_B 0x0fa9
#define mmCNVC_CFG2_FCNV_FP_BIAS_B_BASE_IDX 2
#define mmCNVC_CFG2_FCNV_FP_SCALE_R 0x0faa
#define mmCNVC_CFG2_FCNV_FP_SCALE_R_BASE_IDX 2
#define mmCNVC_CFG2_FCNV_FP_SCALE_G 0x0fab
#define mmCNVC_CFG2_FCNV_FP_SCALE_G_BASE_IDX 2
#define mmCNVC_CFG2_FCNV_FP_SCALE_B 0x0fac
#define mmCNVC_CFG2_FCNV_FP_SCALE_B_BASE_IDX 2
#define mmCNVC_CFG2_COLOR_KEYER_CONTROL 0x0fad
#define mmCNVC_CFG2_COLOR_KEYER_CONTROL_BASE_IDX 2
#define mmCNVC_CFG2_COLOR_KEYER_ALPHA 0x0fae
#define mmCNVC_CFG2_COLOR_KEYER_ALPHA_BASE_IDX 2
#define mmCNVC_CFG2_COLOR_KEYER_RED 0x0faf
#define mmCNVC_CFG2_COLOR_KEYER_RED_BASE_IDX 2
#define mmCNVC_CFG2_COLOR_KEYER_GREEN 0x0fb0
#define mmCNVC_CFG2_COLOR_KEYER_GREEN_BASE_IDX 2
#define mmCNVC_CFG2_COLOR_KEYER_BLUE 0x0fb1
#define mmCNVC_CFG2_COLOR_KEYER_BLUE_BASE_IDX 2
#define mmCNVC_CFG2_ALPHA_2BIT_LUT 0x0fb3
#define mmCNVC_CFG2_ALPHA_2BIT_LUT_BASE_IDX 2
// addressBlock: dce_dc_dpp2_dispdec_cnvc_cur_dispdec
// base address: 0xb58
#define mmCNVC_CUR2_CURSOR0_CONTROL 0x0fb6
#define mmCNVC_CUR2_CURSOR0_CONTROL_BASE_IDX 2
#define mmCNVC_CUR2_CURSOR0_COLOR0 0x0fb7
#define mmCNVC_CUR2_CURSOR0_COLOR0_BASE_IDX 2
#define mmCNVC_CUR2_CURSOR0_COLOR1 0x0fb8
#define mmCNVC_CUR2_CURSOR0_COLOR1_BASE_IDX 2
#define mmCNVC_CUR2_CURSOR0_FP_SCALE_BIAS 0x0fb9
#define mmCNVC_CUR2_CURSOR0_FP_SCALE_BIAS_BASE_IDX 2
// addressBlock: dce_dc_dpp2_dispdec_dscl_dispdec
// base address: 0xb58
#define mmDSCL2_SCL_COEF_RAM_TAP_SELECT 0x0fc0
#define mmDSCL2_SCL_COEF_RAM_TAP_SELECT_BASE_IDX 2
#define mmDSCL2_SCL_COEF_RAM_TAP_DATA 0x0fc1
#define mmDSCL2_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2
#define mmDSCL2_SCL_MODE 0x0fc2
#define mmDSCL2_SCL_MODE_BASE_IDX 2
#define mmDSCL2_SCL_TAP_CONTROL 0x0fc3
#define mmDSCL2_SCL_TAP_CONTROL_BASE_IDX 2
#define mmDSCL2_DSCL_CONTROL 0x0fc4
#define mmDSCL2_DSCL_CONTROL_BASE_IDX 2
#define mmDSCL2_DSCL_2TAP_CONTROL 0x0fc5
#define mmDSCL2_DSCL_2TAP_CONTROL_BASE_IDX 2
#define mmDSCL2_SCL_MANUAL_REPLICATE_CONTROL 0x0fc6
#define mmDSCL2_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2
#define mmDSCL2_SCL_HORZ_FILTER_SCALE_RATIO 0x0fc7
#define mmDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2
#define mmDSCL2_SCL_HORZ_FILTER_INIT 0x0fc8
#define mmDSCL2_SCL_HORZ_FILTER_INIT_BASE_IDX 2
#define mmDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C 0x0fc9
#define mmDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2
#define mmDSCL2_SCL_HORZ_FILTER_INIT_C 0x0fca
#define mmDSCL2_SCL_HORZ_FILTER_INIT_C_BASE_IDX 2
#define mmDSCL2_SCL_VERT_FILTER_SCALE_RATIO 0x0fcb
#define mmDSCL2_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2
#define mmDSCL2_SCL_VERT_FILTER_INIT 0x0fcc
#define mmDSCL2_SCL_VERT_FILTER_INIT_BASE_IDX 2
#define mmDSCL2_SCL_VERT_FILTER_INIT_BOT 0x0fcd
#define mmDSCL2_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2
#define mmDSCL2_SCL_VERT_FILTER_SCALE_RATIO_C 0x0fce
#define mmDSCL2_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2
#define mmDSCL2_SCL_VERT_FILTER_INIT_C 0x0fcf
#define mmDSCL2_SCL_VERT_FILTER_INIT_C_BASE_IDX 2
#define mmDSCL2_SCL_VERT_FILTER_INIT_BOT_C 0x0fd0
#define mmDSCL2_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX 2
#define mmDSCL2_SCL_BLACK_OFFSET 0x0fd1
#define mmDSCL2_SCL_BLACK_OFFSET_BASE_IDX 2
#define mmDSCL2_DSCL_UPDATE 0x0fd2
#define mmDSCL2_DSCL_UPDATE_BASE_IDX 2
#define mmDSCL2_DSCL_AUTOCAL 0x0fd3
#define mmDSCL2_DSCL_AUTOCAL_BASE_IDX 2
#define mmDSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT 0x0fd4
#define mmDSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2
#define mmDSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM 0x0fd5
#define mmDSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2
#define mmDSCL2_OTG_H_BLANK 0x0fd6
#define mmDSCL2_OTG_H_BLANK_BASE_IDX 2
#define mmDSCL2_OTG_V_BLANK 0x0fd7
#define mmDSCL2_OTG_V_BLANK_BASE_IDX 2
#define mmDSCL2_RECOUT_START 0x0fd8
#define mmDSCL2_RECOUT_START_BASE_IDX 2
#define mmDSCL2_RECOUT_SIZE 0x0fd9
#define mmDSCL2_RECOUT_SIZE_BASE_IDX 2
#define mmDSCL2_MPC_SIZE 0x0fda
#define mmDSCL2_MPC_SIZE_BASE_IDX 2
#define mmDSCL2_LB_DATA_FORMAT 0x0fdb
#define mmDSCL2_LB_DATA_FORMAT_BASE_IDX 2
#define mmDSCL2_LB_MEMORY_CTRL 0x0fdc
#define mmDSCL2_LB_MEMORY_CTRL_BASE_IDX 2
#define mmDSCL2_LB_V_COUNTER 0x0fdd
#define mmDSCL2_LB_V_COUNTER_BASE_IDX 2
#define mmDSCL2_DSCL_MEM_PWR_CTRL 0x0fde
#define mmDSCL2_DSCL_MEM_PWR_CTRL_BASE_IDX 2
#define mmDSCL2_DSCL_MEM_PWR_STATUS 0x0fdf
#define mmDSCL2_DSCL_MEM_PWR_STATUS_BASE_IDX 2
#define mmDSCL2_OBUF_CONTROL 0x0fe0
#define mmDSCL2_OBUF_CONTROL_BASE_IDX 2
#define mmDSCL2_OBUF_MEM_PWR_CTRL 0x0fe1
#define mmDSCL2_OBUF_MEM_PWR_CTRL_BASE_IDX 2
// addressBlock: dce_dc_dpp2_dispdec_cm_dispdec
// base address: 0xb58
#define mmCM2_CM_CONTROL 0x0ff0
#define mmCM2_CM_CONTROL_BASE_IDX 2
#define mmCM2_CM_ICSC_CONTROL 0x0ff1
#define mmCM2_CM_ICSC_CONTROL_BASE_IDX 2
#define mmCM2_CM_ICSC_C11_C12 0x0ff2
#define mmCM2_CM_ICSC_C11_C12_BASE_IDX 2
#define mmCM2_CM_ICSC_C13_C14 0x0ff3
#define mmCM2_CM_ICSC_C13_C14_BASE_IDX 2
#define mmCM2_CM_ICSC_C21_C22 0x0ff4
#define mmCM2_CM_ICSC_C21_C22_BASE_IDX 2
#define mmCM2_CM_ICSC_C23_C24 0x0ff5
#define mmCM2_CM_ICSC_C23_C24_BASE_IDX 2
#define mmCM2_CM_ICSC_C31_C32 0x0ff6
#define mmCM2_CM_ICSC_C31_C32_BASE_IDX 2
#define mmCM2_CM_ICSC_C33_C34 0x0ff7
#define mmCM2_CM_ICSC_C33_C34_BASE_IDX 2
#define mmCM2_CM_ICSC_B_C11_C12 0x0ff8
#define mmCM2_CM_ICSC_B_C11_C12_BASE_IDX 2
#define mmCM2_CM_ICSC_B_C13_C14 0x0ff9
#define mmCM2_CM_ICSC_B_C13_C14_BASE_IDX 2
#define mmCM2_CM_ICSC_B_C21_C22 0x0ffa
#define mmCM2_CM_ICSC_B_C21_C22_BASE_IDX 2
#define mmCM2_CM_ICSC_B_C23_C24 0x0ffb
#define mmCM2_CM_ICSC_B_C23_C24_BASE_IDX 2
#define mmCM2_CM_ICSC_B_C31_C32 0x0ffc
#define mmCM2_CM_ICSC_B_C31_C32_BASE_IDX 2
#define mmCM2_CM_ICSC_B_C33_C34 0x0ffd
#define mmCM2_CM_ICSC_B_C33_C34_BASE_IDX 2
#define mmCM2_CM_GAMUT_REMAP_CONTROL 0x0ffe
#define mmCM2_CM_GAMUT_REMAP_CONTROL_BASE_IDX 2
#define mmCM2_CM_GAMUT_REMAP_C11_C12 0x0fff
#define mmCM2_CM_GAMUT_REMAP_C11_C12_BASE_IDX 2
#define mmCM2_CM_GAMUT_REMAP_C13_C14 0x1000
#define mmCM2_CM_GAMUT_REMAP_C13_C14_BASE_IDX 2
#define mmCM2_CM_GAMUT_REMAP_C21_C22 0x1001
#define mmCM2_CM_GAMUT_REMAP_C21_C22_BASE_IDX 2
#define mmCM2_CM_GAMUT_REMAP_C23_C24 0x1002
#define mmCM2_CM_GAMUT_REMAP_C23_C24_BASE_IDX 2
#define mmCM2_CM_GAMUT_REMAP_C31_C32 0x1003
#define mmCM2_CM_GAMUT_REMAP_C31_C32_BASE_IDX 2
#define mmCM2_CM_GAMUT_REMAP_C33_C34 0x1004
#define mmCM2_CM_GAMUT_REMAP_C33_C34_BASE_IDX 2
#define mmCM2_CM_GAMUT_REMAP_B_C11_C12 0x1005
#define mmCM2_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX 2
#define mmCM2_CM_GAMUT_REMAP_B_C13_C14 0x1006
#define mmCM2_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX 2
#define mmCM2_CM_GAMUT_REMAP_B_C21_C22 0x1007
#define mmCM2_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX 2
#define mmCM2_CM_GAMUT_REMAP_B_C23_C24 0x1008
#define mmCM2_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX 2
#define mmCM2_CM_GAMUT_REMAP_B_C31_C32 0x1009
#define mmCM2_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX 2
#define mmCM2_CM_GAMUT_REMAP_B_C33_C34 0x100a
#define mmCM2_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX 2
#define mmCM2_CM_BIAS_CR_R 0x100b
#define mmCM2_CM_BIAS_CR_R_BASE_IDX 2
#define mmCM2_CM_BIAS_Y_G_CB_B 0x100c
#define mmCM2_CM_BIAS_Y_G_CB_B_BASE_IDX 2
#define mmCM2_CM_DGAM_CONTROL 0x100d
#define mmCM2_CM_DGAM_CONTROL_BASE_IDX 2
#define mmCM2_CM_DGAM_LUT_INDEX 0x100e
#define mmCM2_CM_DGAM_LUT_INDEX_BASE_IDX 2
#define mmCM2_CM_DGAM_LUT_DATA 0x100f
#define mmCM2_CM_DGAM_LUT_DATA_BASE_IDX 2
#define mmCM2_CM_DGAM_LUT_WRITE_EN_MASK 0x1010
#define mmCM2_CM_DGAM_LUT_WRITE_EN_MASK_BASE_IDX 2
#define mmCM2_CM_DGAM_RAMA_START_CNTL_B 0x1011
#define mmCM2_CM_DGAM_RAMA_START_CNTL_B_BASE_IDX 2
#define mmCM2_CM_DGAM_RAMA_START_CNTL_G 0x1012
#define mmCM2_CM_DGAM_RAMA_START_CNTL_G_BASE_IDX 2
#define mmCM2_CM_DGAM_RAMA_START_CNTL_R 0x1013
#define mmCM2_CM_DGAM_RAMA_START_CNTL_R_BASE_IDX 2
#define mmCM2_CM_DGAM_RAMA_SLOPE_CNTL_B 0x1014
#define mmCM2_CM_DGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2
#define mmCM2_CM_DGAM_RAMA_SLOPE_CNTL_G 0x1015
#define mmCM2_CM_DGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2
#define mmCM2_CM_DGAM_RAMA_SLOPE_CNTL_R 0x1016
#define mmCM2_CM_DGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2
#define mmCM2_CM_DGAM_RAMA_END_CNTL1_B 0x1017
#define mmCM2_CM_DGAM_RAMA_END_CNTL1_B_BASE_IDX 2
#define mmCM2_CM_DGAM_RAMA_END_CNTL2_B 0x1018
#define mmCM2_CM_DGAM_RAMA_END_CNTL2_B_BASE_IDX 2
#define mmCM2_CM_DGAM_RAMA_END_CNTL1_G 0x1019
#define mmCM2_CM_DGAM_RAMA_END_CNTL1_G_BASE_IDX 2
#define mmCM2_CM_DGAM_RAMA_END_CNTL2_G 0x101a
#define mmCM2_CM_DGAM_RAMA_END_CNTL2_G_BASE_IDX 2
#define mmCM2_CM_DGAM_RAMA_END_CNTL1_R 0x101b
#define mmCM2_CM_DGAM_RAMA_END_CNTL1_R_BASE_IDX 2
#define mmCM2_CM_DGAM_RAMA_END_CNTL2_R 0x101c
#define mmCM2_CM_DGAM_RAMA_END_CNTL2_R_BASE_IDX 2
#define mmCM2_CM_DGAM_RAMA_REGION_0_1 0x101d
#define mmCM2_CM_DGAM_RAMA_REGION_0_1_BASE_IDX 2
#define mmCM2_CM_DGAM_RAMA_REGION_2_3 0x101e
#define mmCM2_CM_DGAM_RAMA_REGION_2_3_BASE_IDX 2
#define mmCM2_CM_DGAM_RAMA_REGION_4_5 0x101f
#define mmCM2_CM_DGAM_RAMA_REGION_4_5_BASE_IDX 2
#define mmCM2_CM_DGAM_RAMA_REGION_6_7 0x1020
#define mmCM2_CM_DGAM_RAMA_REGION_6_7_BASE_IDX 2
#define mmCM2_CM_DGAM_RAMA_REGION_8_9 0x1021
#define mmCM2_CM_DGAM_RAMA_REGION_8_9_BASE_IDX 2
#define mmCM2_CM_DGAM_RAMA_REGION_10_11 0x1022
#define mmCM2_CM_DGAM_RAMA_REGION_10_11_BASE_IDX 2
#define mmCM2_CM_DGAM_RAMA_REGION_12_13 0x1023
#define mmCM2_CM_DGAM_RAMA_REGION_12_13_BASE_IDX 2
#define mmCM2_CM_DGAM_RAMA_REGION_14_15 0x1024
#define mmCM2_CM_DGAM_RAMA_REGION_14_15_BASE_IDX 2
#define mmCM2_CM_DGAM_RAMB_START_CNTL_B 0x1025
#define mmCM2_CM_DGAM_RAMB_START_CNTL_B_BASE_IDX 2
#define mmCM2_CM_DGAM_RAMB_START_CNTL_G 0x1026
#define mmCM2_CM_DGAM_RAMB_START_CNTL_G_BASE_IDX 2
#define mmCM2_CM_DGAM_RAMB_START_CNTL_R 0x1027
#define mmCM2_CM_DGAM_RAMB_START_CNTL_R_BASE_IDX 2
#define mmCM2_CM_DGAM_RAMB_SLOPE_CNTL_B 0x1028
#define mmCM2_CM_DGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2
#define mmCM2_CM_DGAM_RAMB_SLOPE_CNTL_G 0x1029
#define mmCM2_CM_DGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2
#define mmCM2_CM_DGAM_RAMB_SLOPE_CNTL_R 0x102a
#define mmCM2_CM_DGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2
#define mmCM2_CM_DGAM_RAMB_END_CNTL1_B 0x102b
#define mmCM2_CM_DGAM_RAMB_END_CNTL1_B_BASE_IDX 2
#define mmCM2_CM_DGAM_RAMB_END_CNTL2_B 0x102c
#define mmCM2_CM_DGAM_RAMB_END_CNTL2_B_BASE_IDX 2
#define mmCM2_CM_DGAM_RAMB_END_CNTL1_G 0x102d
#define mmCM2_CM_DGAM_RAMB_END_CNTL1_G_BASE_IDX 2
#define mmCM2_CM_DGAM_RAMB_END_CNTL2_G 0x102e
#define mmCM2_CM_DGAM_RAMB_END_CNTL2_G_BASE_IDX 2
#define mmCM2_CM_DGAM_RAMB_END_CNTL1_R 0x102f
#define mmCM2_CM_DGAM_RAMB_END_CNTL1_R_BASE_IDX 2
#define mmCM2_CM_DGAM_RAMB_END_CNTL2_R 0x1030
#define mmCM2_CM_DGAM_RAMB_END_CNTL2_R_BASE_IDX 2
#define mmCM2_CM_DGAM_RAMB_REGION_0_1 0x1031
#define mmCM2_CM_DGAM_RAMB_REGION_0_1_BASE_IDX 2
#define mmCM2_CM_DGAM_RAMB_REGION_2_3 0x1032
#define mmCM2_CM_DGAM_RAMB_REGION_2_3_BASE_IDX 2
#define mmCM2_CM_DGAM_RAMB_REGION_4_5 0x1033
#define mmCM2_CM_DGAM_RAMB_REGION_4_5_BASE_IDX 2
#define mmCM2_CM_DGAM_RAMB_REGION_6_7 0x1034
#define mmCM2_CM_DGAM_RAMB_REGION_6_7_BASE_IDX 2
#define mmCM2_CM_DGAM_RAMB_REGION_8_9 0x1035
#define mmCM2_CM_DGAM_RAMB_REGION_8_9_BASE_IDX 2
#define mmCM2_CM_DGAM_RAMB_REGION_10_11 0x1036
#define mmCM2_CM_DGAM_RAMB_REGION_10_11_BASE_IDX 2
#define mmCM2_CM_DGAM_RAMB_REGION_12_13 0x1037
#define mmCM2_CM_DGAM_RAMB_REGION_12_13_BASE_IDX 2
#define mmCM2_CM_DGAM_RAMB_REGION_14_15 0x1038
#define mmCM2_CM_DGAM_RAMB_REGION_14_15_BASE_IDX 2
#define mmCM2_CM_BLNDGAM_CONTROL 0x1039
#define mmCM2_CM_BLNDGAM_CONTROL_BASE_IDX 2
#define mmCM2_CM_BLNDGAM_LUT_INDEX 0x103a
#define mmCM2_CM_BLNDGAM_LUT_INDEX_BASE_IDX 2
#define mmCM2_CM_BLNDGAM_LUT_DATA 0x103b
#define mmCM2_CM_BLNDGAM_LUT_DATA_BASE_IDX 2
#define mmCM2_CM_BLNDGAM_LUT_WRITE_EN_MASK 0x103c
#define mmCM2_CM_BLNDGAM_LUT_WRITE_EN_MASK_BASE_IDX 2
#define mmCM2_CM_BLNDGAM_RAMA_START_CNTL_B 0x103d
#define mmCM2_CM_BLNDGAM_RAMA_START_CNTL_B_BASE_IDX 2
#define mmCM2_CM_BLNDGAM_RAMA_START_CNTL_G 0x103e
#define mmCM2_CM_BLNDGAM_RAMA_START_CNTL_G_BASE_IDX 2
#define mmCM2_CM_BLNDGAM_RAMA_START_CNTL_R 0x103f
#define mmCM2_CM_BLNDGAM_RAMA_START_CNTL_R_BASE_IDX 2
#define mmCM2_CM_BLNDGAM_RAMA_SLOPE_CNTL_B 0x1040
#define mmCM2_CM_BLNDGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2
#define mmCM2_CM_BLNDGAM_RAMA_SLOPE_CNTL_G 0x1041
#define mmCM2_CM_BLNDGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2
#define mmCM2_CM_BLNDGAM_RAMA_SLOPE_CNTL_R 0x1042
#define mmCM2_CM_BLNDGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2
#define mmCM2_CM_BLNDGAM_RAMA_END_CNTL1_B 0x1043
#define mmCM2_CM_BLNDGAM_RAMA_END_CNTL1_B_BASE_IDX 2
#define mmCM2_CM_BLNDGAM_RAMA_END_CNTL2_B 0x1044
#define mmCM2_CM_BLNDGAM_RAMA_END_CNTL2_B_BASE_IDX 2
#define mmCM2_CM_BLNDGAM_RAMA_END_CNTL1_G 0x1045
#define mmCM2_CM_BLNDGAM_RAMA_END_CNTL1_G_BASE_IDX 2
#define mmCM2_CM_BLNDGAM_RAMA_END_CNTL2_G 0x1046
#define mmCM2_CM_BLNDGAM_RAMA_END_CNTL2_G_BASE_IDX 2
#define mmCM2_CM_BLNDGAM_RAMA_END_CNTL1_R 0x1047
#define mmCM2_CM_BLNDGAM_RAMA_END_CNTL1_R_BASE_IDX 2
#define mmCM2_CM_BLNDGAM_RAMA_END_CNTL2_R 0x1048
#define mmCM2_CM_BLNDGAM_RAMA_END_CNTL2_R_BASE_IDX 2
#define mmCM2_CM_BLNDGAM_RAMA_REGION_0_1 0x1049
#define mmCM2_CM_BLNDGAM_RAMA_REGION_0_1_BASE_IDX 2
#define mmCM2_CM_BLNDGAM_RAMA_REGION_2_3 0x104a
#define mmCM2_CM_BLNDGAM_RAMA_REGION_2_3_BASE_IDX 2
#define mmCM2_CM_BLNDGAM_RAMA_REGION_4_5 0x104b
#define mmCM2_CM_BLNDGAM_RAMA_REGION_4_5_BASE_IDX 2
#define mmCM2_CM_BLNDGAM_RAMA_REGION_6_7 0x104c
#define mmCM2_CM_BLNDGAM_RAMA_REGION_6_7_BASE_IDX 2
#define mmCM2_CM_BLNDGAM_RAMA_REGION_8_9 0x104d
#define mmCM2_CM_BLNDGAM_RAMA_REGION_8_9_BASE_IDX 2
#define mmCM2_CM_BLNDGAM_RAMA_REGION_10_11 0x104e
#define mmCM2_CM_BLNDGAM_RAMA_REGION_10_11_BASE_IDX 2
#define mmCM2_CM_BLNDGAM_RAMA_REGION_12_13 0x104f
#define mmCM2_CM_BLNDGAM_RAMA_REGION_12_13_BASE_IDX 2
#define mmCM2_CM_BLNDGAM_RAMA_REGION_14_15 0x1050
#define mmCM2_CM_BLNDGAM_RAMA_REGION_14_15_BASE_IDX 2
#define mmCM2_CM_BLNDGAM_RAMA_REGION_16_17 0x1051
#define mmCM2_CM_BLNDGAM_RAMA_REGION_16_17_BASE_IDX 2
#define mmCM2_CM_BLNDGAM_RAMA_REGION_18_19 0x1052
#define mmCM2_CM_BLNDGAM_RAMA_REGION_18_19_BASE_IDX 2
#define mmCM2_CM_BLNDGAM_RAMA_REGION_20_21 0x1053
#define mmCM2_CM_BLNDGAM_RAMA_REGION_20_21_BASE_IDX 2
#define mmCM2_CM_BLNDGAM_RAMA_REGION_22_23 0x1054
#define mmCM2_CM_BLNDGAM_RAMA_REGION_22_23_BASE_IDX 2
#define mmCM2_CM_BLNDGAM_RAMA_REGION_24_25 0x1055
#define mmCM2_CM_BLNDGAM_RAMA_REGION_24_25_BASE_IDX 2
#define mmCM2_CM_BLNDGAM_RAMA_REGION_26_27 0x1056
#define mmCM2_CM_BLNDGAM_RAMA_REGION_26_27_BASE_IDX 2
#define mmCM2_CM_BLNDGAM_RAMA_REGION_28_29 0x1057
#define mmCM2_CM_BLNDGAM_RAMA_REGION_28_29_BASE_IDX 2
#define mmCM2_CM_BLNDGAM_RAMA_REGION_30_31 0x1058
#define mmCM2_CM_BLNDGAM_RAMA_REGION_30_31_BASE_IDX 2
#define mmCM2_CM_BLNDGAM_RAMA_REGION_32_33 0x1059
#define mmCM2_CM_BLNDGAM_RAMA_REGION_32_33_BASE_IDX 2
#define mmCM2_CM_BLNDGAM_RAMB_START_CNTL_B 0x105a
#define mmCM2_CM_BLNDGAM_RAMB_START_CNTL_B_BASE_IDX 2
#define mmCM2_CM_BLNDGAM_RAMB_START_CNTL_G 0x105b
#define mmCM2_CM_BLNDGAM_RAMB_START_CNTL_G_BASE_IDX 2
#define mmCM2_CM_BLNDGAM_RAMB_START_CNTL_R 0x105c
#define mmCM2_CM_BLNDGAM_RAMB_START_CNTL_R_BASE_IDX 2
#define mmCM2_CM_BLNDGAM_RAMB_SLOPE_CNTL_B 0x105d
#define mmCM2_CM_BLNDGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2
#define mmCM2_CM_BLNDGAM_RAMB_SLOPE_CNTL_G 0x105e
#define mmCM2_CM_BLNDGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2
#define mmCM2_CM_BLNDGAM_RAMB_SLOPE_CNTL_R 0x105f
#define mmCM2_CM_BLNDGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2
#define mmCM2_CM_BLNDGAM_RAMB_END_CNTL1_B 0x1060
#define mmCM2_CM_BLNDGAM_RAMB_END_CNTL1_B_BASE_IDX 2
#define mmCM2_CM_BLNDGAM_RAMB_END_CNTL2_B 0x1061
#define mmCM2_CM_BLNDGAM_RAMB_END_CNTL2_B_BASE_IDX 2
#define mmCM2_CM_BLNDGAM_RAMB_END_CNTL1_G 0x1062
#define mmCM2_CM_BLNDGAM_RAMB_END_CNTL1_G_BASE_IDX 2
#define mmCM2_CM_BLNDGAM_RAMB_END_CNTL2_G 0x1063
#define mmCM2_CM_BLNDGAM_RAMB_END_CNTL2_G_BASE_IDX 2
#define mmCM2_CM_BLNDGAM_RAMB_END_CNTL1_R 0x1064
#define mmCM2_CM_BLNDGAM_RAMB_END_CNTL1_R_BASE_IDX 2
#define mmCM2_CM_BLNDGAM_RAMB_END_CNTL2_R 0x1065
#define mmCM2_CM_BLNDGAM_RAMB_END_CNTL2_R_BASE_IDX 2
#define mmCM2_CM_BLNDGAM_RAMB_REGION_0_1 0x1066
#define mmCM2_CM_BLNDGAM_RAMB_REGION_0_1_BASE_IDX 2
#define mmCM2_CM_BLNDGAM_RAMB_REGION_2_3 0x1067
#define mmCM2_CM_BLNDGAM_RAMB_REGION_2_3_BASE_IDX 2
#define mmCM2_CM_BLNDGAM_RAMB_REGION_4_5 0x1068
#define mmCM2_CM_BLNDGAM_RAMB_REGION_4_5_BASE_IDX 2
#define mmCM2_CM_BLNDGAM_RAMB_REGION_6_7 0x1069
#define mmCM2_CM_BLNDGAM_RAMB_REGION_6_7_BASE_IDX 2
#define mmCM2_CM_BLNDGAM_RAMB_REGION_8_9 0x106a
#define mmCM2_CM_BLNDGAM_RAMB_REGION_8_9_BASE_IDX 2
#define mmCM2_CM_BLNDGAM_RAMB_REGION_10_11 0x106b
#define mmCM2_CM_BLNDGAM_RAMB_REGION_10_11_BASE_IDX 2
#define mmCM2_CM_BLNDGAM_RAMB_REGION_12_13 0x106c
#define mmCM2_CM_BLNDGAM_RAMB_REGION_12_13_BASE_IDX 2
#define mmCM2_CM_BLNDGAM_RAMB_REGION_14_15 0x106d
#define mmCM2_CM_BLNDGAM_RAMB_REGION_14_15_BASE_IDX 2
#define mmCM2_CM_BLNDGAM_RAMB_REGION_16_17 0x106e
#define mmCM2_CM_BLNDGAM_RAMB_REGION_16_17_BASE_IDX 2
#define mmCM2_CM_BLNDGAM_RAMB_REGION_18_19 0x106f
#define mmCM2_CM_BLNDGAM_RAMB_REGION_18_19_BASE_IDX 2
#define mmCM2_CM_BLNDGAM_RAMB_REGION_20_21 0x1070
#define mmCM2_CM_BLNDGAM_RAMB_REGION_20_21_BASE_IDX 2
#define mmCM2_CM_BLNDGAM_RAMB_REGION_22_23 0x1071
#define mmCM2_CM_BLNDGAM_RAMB_REGION_22_23_BASE_IDX 2
#define mmCM2_CM_BLNDGAM_RAMB_REGION_24_25 0x1072
#define mmCM2_CM_BLNDGAM_RAMB_REGION_24_25_BASE_IDX 2
#define mmCM2_CM_BLNDGAM_RAMB_REGION_26_27 0x1073
#define mmCM2_CM_BLNDGAM_RAMB_REGION_26_27_BASE_IDX 2
#define mmCM2_CM_BLNDGAM_RAMB_REGION_28_29 0x1074
#define mmCM2_CM_BLNDGAM_RAMB_REGION_28_29_BASE_IDX 2
#define mmCM2_CM_BLNDGAM_RAMB_REGION_30_31 0x1075
#define mmCM2_CM_BLNDGAM_RAMB_REGION_30_31_BASE_IDX 2
#define mmCM2_CM_BLNDGAM_RAMB_REGION_32_33 0x1076
#define mmCM2_CM_BLNDGAM_RAMB_REGION_32_33_BASE_IDX 2
#define mmCM2_CM_HDR_MULT_COEF 0x1077
#define mmCM2_CM_HDR_MULT_COEF_BASE_IDX 2
#define mmCM2_CM_MEM_PWR_CTRL 0x1078
#define mmCM2_CM_MEM_PWR_CTRL_BASE_IDX 2
#define mmCM2_CM_MEM_PWR_STATUS 0x1079
#define mmCM2_CM_MEM_PWR_STATUS_BASE_IDX 2
#define mmCM2_CM_DEALPHA 0x107b
#define mmCM2_CM_DEALPHA_BASE_IDX 2
#define mmCM2_CM_COEF_FORMAT 0x107c
#define mmCM2_CM_COEF_FORMAT_BASE_IDX 2
#define mmCM2_CM_SHAPER_CONTROL 0x107d
#define mmCM2_CM_SHAPER_CONTROL_BASE_IDX 2
#define mmCM2_CM_SHAPER_OFFSET_R 0x107e
#define mmCM2_CM_SHAPER_OFFSET_R_BASE_IDX 2
#define mmCM2_CM_SHAPER_OFFSET_G 0x107f
#define mmCM2_CM_SHAPER_OFFSET_G_BASE_IDX 2
#define mmCM2_CM_SHAPER_OFFSET_B 0x1080
#define mmCM2_CM_SHAPER_OFFSET_B_BASE_IDX 2
#define mmCM2_CM_SHAPER_SCALE_R 0x1081
#define mmCM2_CM_SHAPER_SCALE_R_BASE_IDX 2
#define mmCM2_CM_SHAPER_SCALE_G_B 0x1082
#define mmCM2_CM_SHAPER_SCALE_G_B_BASE_IDX 2
#define mmCM2_CM_SHAPER_LUT_INDEX 0x1083
#define mmCM2_CM_SHAPER_LUT_INDEX_BASE_IDX 2
#define mmCM2_CM_SHAPER_LUT_DATA 0x1084
#define mmCM2_CM_SHAPER_LUT_DATA_BASE_IDX 2
#define mmCM2_CM_SHAPER_LUT_WRITE_EN_MASK 0x1085
#define mmCM2_CM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX 2
#define mmCM2_CM_SHAPER_RAMA_START_CNTL_B 0x1086
#define mmCM2_CM_SHAPER_RAMA_START_CNTL_B_BASE_IDX 2
#define mmCM2_CM_SHAPER_RAMA_START_CNTL_G 0x1087
#define mmCM2_CM_SHAPER_RAMA_START_CNTL_G_BASE_IDX 2
#define mmCM2_CM_SHAPER_RAMA_START_CNTL_R 0x1088
#define mmCM2_CM_SHAPER_RAMA_START_CNTL_R_BASE_IDX 2
#define mmCM2_CM_SHAPER_RAMA_END_CNTL_B 0x1089
#define mmCM2_CM_SHAPER_RAMA_END_CNTL_B_BASE_IDX 2
#define mmCM2_CM_SHAPER_RAMA_END_CNTL_G 0x108a
#define mmCM2_CM_SHAPER_RAMA_END_CNTL_G_BASE_IDX 2
#define mmCM2_CM_SHAPER_RAMA_END_CNTL_R 0x108b
#define mmCM2_CM_SHAPER_RAMA_END_CNTL_R_BASE_IDX 2
#define mmCM2_CM_SHAPER_RAMA_REGION_0_1 0x108c
#define mmCM2_CM_SHAPER_RAMA_REGION_0_1_BASE_IDX 2
#define mmCM2_CM_SHAPER_RAMA_REGION_2_3 0x108d
#define mmCM2_CM_SHAPER_RAMA_REGION_2_3_BASE_IDX 2
#define mmCM2_CM_SHAPER_RAMA_REGION_4_5 0x108e
#define mmCM2_CM_SHAPER_RAMA_REGION_4_5_BASE_IDX 2
#define mmCM2_CM_SHAPER_RAMA_REGION_6_7 0x108f
#define mmCM2_CM_SHAPER_RAMA_REGION_6_7_BASE_IDX 2
#define mmCM2_CM_SHAPER_RAMA_REGION_8_9 0x1090
#define mmCM2_CM_SHAPER_RAMA_REGION_8_9_BASE_IDX 2
#define mmCM2_CM_SHAPER_RAMA_REGION_10_11 0x1091
#define mmCM2_CM_SHAPER_RAMA_REGION_10_11_BASE_IDX 2
#define mmCM2_CM_SHAPER_RAMA_REGION_12_13 0x1092
#define mmCM2_CM_SHAPER_RAMA_REGION_12_13_BASE_IDX 2
#define mmCM2_CM_SHAPER_RAMA_REGION_14_15 0x1093
#define mmCM2_CM_SHAPER_RAMA_REGION_14_15_BASE_IDX 2
#define mmCM2_CM_SHAPER_RAMA_REGION_16_17 0x1094
#define mmCM2_CM_SHAPER_RAMA_REGION_16_17_BASE_IDX 2
#define mmCM2_CM_SHAPER_RAMA_REGION_18_19 0x1095
#define mmCM2_CM_SHAPER_RAMA_REGION_18_19_BASE_IDX 2
#define mmCM2_CM_SHAPER_RAMA_REGION_20_21 0x1096
#define mmCM2_CM_SHAPER_RAMA_REGION_20_21_BASE_IDX 2
#define mmCM2_CM_SHAPER_RAMA_REGION_22_23 0x1097
#define mmCM2_CM_SHAPER_RAMA_REGION_22_23_BASE_IDX 2
#define mmCM2_CM_SHAPER_RAMA_REGION_24_25 0x1098
#define mmCM2_CM_SHAPER_RAMA_REGION_24_25_BASE_IDX 2
#define mmCM2_CM_SHAPER_RAMA_REGION_26_27 0x1099
#define mmCM2_CM_SHAPER_RAMA_REGION_26_27_BASE_IDX 2
#define mmCM2_CM_SHAPER_RAMA_REGION_28_29 0x109a
#define mmCM2_CM_SHAPER_RAMA_REGION_28_29_BASE_IDX 2
#define mmCM2_CM_SHAPER_RAMA_REGION_30_31 0x109b
#define mmCM2_CM_SHAPER_RAMA_REGION_30_31_BASE_IDX 2
#define mmCM2_CM_SHAPER_RAMA_REGION_32_33 0x109c
#define mmCM2_CM_SHAPER_RAMA_REGION_32_33_BASE_IDX 2
#define mmCM2_CM_SHAPER_RAMB_START_CNTL_B 0x109d
#define mmCM2_CM_SHAPER_RAMB_START_CNTL_B_BASE_IDX 2
#define mmCM2_CM_SHAPER_RAMB_START_CNTL_G 0x109e
#define mmCM2_CM_SHAPER_RAMB_START_CNTL_G_BASE_IDX 2
#define mmCM2_CM_SHAPER_RAMB_START_CNTL_R 0x109f
#define mmCM2_CM_SHAPER_RAMB_START_CNTL_R_BASE_IDX 2
#define mmCM2_CM_SHAPER_RAMB_END_CNTL_B 0x10a0
#define mmCM2_CM_SHAPER_RAMB_END_CNTL_B_BASE_IDX 2
#define mmCM2_CM_SHAPER_RAMB_END_CNTL_G 0x10a1
#define mmCM2_CM_SHAPER_RAMB_END_CNTL_G_BASE_IDX 2
#define mmCM2_CM_SHAPER_RAMB_END_CNTL_R 0x10a2
#define mmCM2_CM_SHAPER_RAMB_END_CNTL_R_BASE_IDX 2
#define mmCM2_CM_SHAPER_RAMB_REGION_0_1 0x10a3
#define mmCM2_CM_SHAPER_RAMB_REGION_0_1_BASE_IDX 2
#define mmCM2_CM_SHAPER_RAMB_REGION_2_3 0x10a4
#define mmCM2_CM_SHAPER_RAMB_REGION_2_3_BASE_IDX 2
#define mmCM2_CM_SHAPER_RAMB_REGION_4_5 0x10a5
#define mmCM2_CM_SHAPER_RAMB_REGION_4_5_BASE_IDX 2
#define mmCM2_CM_SHAPER_RAMB_REGION_6_7 0x10a6
#define mmCM2_CM_SHAPER_RAMB_REGION_6_7_BASE_IDX 2
#define mmCM2_CM_SHAPER_RAMB_REGION_8_9 0x10a7
#define mmCM2_CM_SHAPER_RAMB_REGION_8_9_BASE_IDX 2
#define mmCM2_CM_SHAPER_RAMB_REGION_10_11 0x10a8
#define mmCM2_CM_SHAPER_RAMB_REGION_10_11_BASE_IDX 2
#define mmCM2_CM_SHAPER_RAMB_REGION_12_13 0x10a9
#define mmCM2_CM_SHAPER_RAMB_REGION_12_13_BASE_IDX 2
#define mmCM2_CM_SHAPER_RAMB_REGION_14_15 0x10aa
#define mmCM2_CM_SHAPER_RAMB_REGION_14_15_BASE_IDX 2
#define mmCM2_CM_SHAPER_RAMB_REGION_16_17 0x10ab
#define mmCM2_CM_SHAPER_RAMB_REGION_16_17_BASE_IDX 2
#define mmCM2_CM_SHAPER_RAMB_REGION_18_19 0x10ac
#define mmCM2_CM_SHAPER_RAMB_REGION_18_19_BASE_IDX 2
#define mmCM2_CM_SHAPER_RAMB_REGION_20_21 0x10ad
#define mmCM2_CM_SHAPER_RAMB_REGION_20_21_BASE_IDX 2
#define mmCM2_CM_SHAPER_RAMB_REGION_22_23 0x10ae
#define mmCM2_CM_SHAPER_RAMB_REGION_22_23_BASE_IDX 2
#define mmCM2_CM_SHAPER_RAMB_REGION_24_25 0x10af
#define mmCM2_CM_SHAPER_RAMB_REGION_24_25_BASE_IDX 2
#define mmCM2_CM_SHAPER_RAMB_REGION_26_27 0x10b0
#define mmCM2_CM_SHAPER_RAMB_REGION_26_27_BASE_IDX 2
#define mmCM2_CM_SHAPER_RAMB_REGION_28_29 0x10b1
#define mmCM2_CM_SHAPER_RAMB_REGION_28_29_BASE_IDX 2
#define mmCM2_CM_SHAPER_RAMB_REGION_30_31 0x10b2
#define mmCM2_CM_SHAPER_RAMB_REGION_30_31_BASE_IDX 2
#define mmCM2_CM_SHAPER_RAMB_REGION_32_33 0x10b3
#define mmCM2_CM_SHAPER_RAMB_REGION_32_33_BASE_IDX 2
#define mmCM2_CM_MEM_PWR_CTRL2 0x10b4
#define mmCM2_CM_MEM_PWR_CTRL2_BASE_IDX 2
#define mmCM2_CM_MEM_PWR_STATUS2 0x10b5
#define mmCM2_CM_MEM_PWR_STATUS2_BASE_IDX 2
#define mmCM2_CM_3DLUT_MODE 0x10b6
#define mmCM2_CM_3DLUT_MODE_BASE_IDX 2
#define mmCM2_CM_3DLUT_INDEX 0x10b7
#define mmCM2_CM_3DLUT_INDEX_BASE_IDX 2
#define mmCM2_CM_3DLUT_DATA 0x10b8
#define mmCM2_CM_3DLUT_DATA_BASE_IDX 2
#define mmCM2_CM_3DLUT_DATA_30BIT 0x10b9
#define mmCM2_CM_3DLUT_DATA_30BIT_BASE_IDX 2
#define mmCM2_CM_3DLUT_READ_WRITE_CONTROL 0x10ba
#define mmCM2_CM_3DLUT_READ_WRITE_CONTROL_BASE_IDX 2
#define mmCM2_CM_3DLUT_OUT_NORM_FACTOR 0x10bb
#define mmCM2_CM_3DLUT_OUT_NORM_FACTOR_BASE_IDX 2
#define mmCM2_CM_3DLUT_OUT_OFFSET_R 0x10bc
#define mmCM2_CM_3DLUT_OUT_OFFSET_R_BASE_IDX 2
#define mmCM2_CM_3DLUT_OUT_OFFSET_G 0x10bd
#define mmCM2_CM_3DLUT_OUT_OFFSET_G_BASE_IDX 2
#define mmCM2_CM_3DLUT_OUT_OFFSET_B 0x10be
#define mmCM2_CM_3DLUT_OUT_OFFSET_B_BASE_IDX 2
#define mmCM2_CM_TEST_DEBUG_INDEX 0x10bf
#define mmCM2_CM_TEST_DEBUG_INDEX_BASE_IDX 2
#define mmCM2_CM_TEST_DEBUG_DATA 0x10c0
#define mmCM2_CM_TEST_DEBUG_DATA_BASE_IDX 2
// addressBlock: dce_dc_dpp3_dispdec_dpp_top_dispdec
// base address: 0x1104
#define mmDPP_TOP3_DPP_CONTROL 0x1106
#define mmDPP_TOP3_DPP_CONTROL_BASE_IDX 2
#define mmDPP_TOP3_DPP_SOFT_RESET 0x1107
#define mmDPP_TOP3_DPP_SOFT_RESET_BASE_IDX 2
#define mmDPP_TOP3_DPP_CRC_VAL_R_G 0x1108
#define mmDPP_TOP3_DPP_CRC_VAL_R_G_BASE_IDX 2
#define mmDPP_TOP3_DPP_CRC_VAL_B_A 0x1109
#define mmDPP_TOP3_DPP_CRC_VAL_B_A_BASE_IDX 2
#define mmDPP_TOP3_DPP_CRC_CTRL 0x110a
#define mmDPP_TOP3_DPP_CRC_CTRL_BASE_IDX 2
// addressBlock: dce_dc_dpp3_dispdec_cnvc_cfg_dispdec
// base address: 0x1104
#define mmCNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT 0x1110
#define mmCNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX 2
#define mmCNVC_CFG3_FORMAT_CONTROL 0x1111
#define mmCNVC_CFG3_FORMAT_CONTROL_BASE_IDX 2
#define mmCNVC_CFG3_FCNV_FP_BIAS_R 0x1112
#define mmCNVC_CFG3_FCNV_FP_BIAS_R_BASE_IDX 2
#define mmCNVC_CFG3_FCNV_FP_BIAS_G 0x1113
#define mmCNVC_CFG3_FCNV_FP_BIAS_G_BASE_IDX 2
#define mmCNVC_CFG3_FCNV_FP_BIAS_B 0x1114
#define mmCNVC_CFG3_FCNV_FP_BIAS_B_BASE_IDX 2
#define mmCNVC_CFG3_FCNV_FP_SCALE_R 0x1115
#define mmCNVC_CFG3_FCNV_FP_SCALE_R_BASE_IDX 2
#define mmCNVC_CFG3_FCNV_FP_SCALE_G 0x1116
#define mmCNVC_CFG3_FCNV_FP_SCALE_G_BASE_IDX 2
#define mmCNVC_CFG3_FCNV_FP_SCALE_B 0x1117
#define mmCNVC_CFG3_FCNV_FP_SCALE_B_BASE_IDX 2
#define mmCNVC_CFG3_COLOR_KEYER_CONTROL 0x1118
#define mmCNVC_CFG3_COLOR_KEYER_CONTROL_BASE_IDX 2
#define mmCNVC_CFG3_COLOR_KEYER_ALPHA 0x1119
#define mmCNVC_CFG3_COLOR_KEYER_ALPHA_BASE_IDX 2
#define mmCNVC_CFG3_COLOR_KEYER_RED 0x111a
#define mmCNVC_CFG3_COLOR_KEYER_RED_BASE_IDX 2
#define mmCNVC_CFG3_COLOR_KEYER_GREEN 0x111b
#define mmCNVC_CFG3_COLOR_KEYER_GREEN_BASE_IDX 2
#define mmCNVC_CFG3_COLOR_KEYER_BLUE 0x111c
#define mmCNVC_CFG3_COLOR_KEYER_BLUE_BASE_IDX 2
#define mmCNVC_CFG3_ALPHA_2BIT_LUT 0x111e
#define mmCNVC_CFG3_ALPHA_2BIT_LUT_BASE_IDX 2
// addressBlock: dce_dc_dpp3_dispdec_cnvc_cur_dispdec
// base address: 0x1104
#define mmCNVC_CUR3_CURSOR0_CONTROL 0x1121
#define mmCNVC_CUR3_CURSOR0_CONTROL_BASE_IDX 2
#define mmCNVC_CUR3_CURSOR0_COLOR0 0x1122
#define mmCNVC_CUR3_CURSOR0_COLOR0_BASE_IDX 2
#define mmCNVC_CUR3_CURSOR0_COLOR1 0x1123
#define mmCNVC_CUR3_CURSOR0_COLOR1_BASE_IDX 2
#define mmCNVC_CUR3_CURSOR0_FP_SCALE_BIAS 0x1124
#define mmCNVC_CUR3_CURSOR0_FP_SCALE_BIAS_BASE_IDX 2
// addressBlock: dce_dc_dpp3_dispdec_dscl_dispdec
// base address: 0x1104
#define mmDSCL3_SCL_COEF_RAM_TAP_SELECT 0x112b
#define mmDSCL3_SCL_COEF_RAM_TAP_SELECT_BASE_IDX 2
#define mmDSCL3_SCL_COEF_RAM_TAP_DATA 0x112c
#define mmDSCL3_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2
#define mmDSCL3_SCL_MODE 0x112d
#define mmDSCL3_SCL_MODE_BASE_IDX 2
#define mmDSCL3_SCL_TAP_CONTROL 0x112e
#define mmDSCL3_SCL_TAP_CONTROL_BASE_IDX 2
#define mmDSCL3_DSCL_CONTROL 0x112f
#define mmDSCL3_DSCL_CONTROL_BASE_IDX 2
#define mmDSCL3_DSCL_2TAP_CONTROL 0x1130
#define mmDSCL3_DSCL_2TAP_CONTROL_BASE_IDX 2
#define mmDSCL3_SCL_MANUAL_REPLICATE_CONTROL 0x1131
#define mmDSCL3_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2
#define mmDSCL3_SCL_HORZ_FILTER_SCALE_RATIO 0x1132
#define mmDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2
#define mmDSCL3_SCL_HORZ_FILTER_INIT 0x1133
#define mmDSCL3_SCL_HORZ_FILTER_INIT_BASE_IDX 2
#define mmDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C 0x1134
#define mmDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2
#define mmDSCL3_SCL_HORZ_FILTER_INIT_C 0x1135
#define mmDSCL3_SCL_HORZ_FILTER_INIT_C_BASE_IDX 2
#define mmDSCL3_SCL_VERT_FILTER_SCALE_RATIO 0x1136
#define mmDSCL3_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2
#define mmDSCL3_SCL_VERT_FILTER_INIT 0x1137
#define mmDSCL3_SCL_VERT_FILTER_INIT_BASE_IDX 2
#define mmDSCL3_SCL_VERT_FILTER_INIT_BOT 0x1138
#define mmDSCL3_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2
#define mmDSCL3_SCL_VERT_FILTER_SCALE_RATIO_C 0x1139
#define mmDSCL3_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2
#define mmDSCL3_SCL_VERT_FILTER_INIT_C 0x113a
#define mmDSCL3_SCL_VERT_FILTER_INIT_C_BASE_IDX 2
#define mmDSCL3_SCL_VERT_FILTER_INIT_BOT_C 0x113b
#define mmDSCL3_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX 2
#define mmDSCL3_SCL_BLACK_OFFSET 0x113c
#define mmDSCL3_SCL_BLACK_OFFSET_BASE_IDX 2
#define mmDSCL3_DSCL_UPDATE 0x113d
#define mmDSCL3_DSCL_UPDATE_BASE_IDX 2
#define mmDSCL3_DSCL_AUTOCAL 0x113e
#define mmDSCL3_DSCL_AUTOCAL_BASE_IDX 2
#define mmDSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT 0x113f
#define mmDSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2
#define mmDSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM 0x1140
#define mmDSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2
#define mmDSCL3_OTG_H_BLANK 0x1141
#define mmDSCL3_OTG_H_BLANK_BASE_IDX 2
#define mmDSCL3_OTG_V_BLANK 0x1142
#define mmDSCL3_OTG_V_BLANK_BASE_IDX 2
#define mmDSCL3_RECOUT_START 0x1143
#define mmDSCL3_RECOUT_START_BASE_IDX 2
#define mmDSCL3_RECOUT_SIZE 0x1144
#define mmDSCL3_RECOUT_SIZE_BASE_IDX 2
#define mmDSCL3_MPC_SIZE 0x1145
#define mmDSCL3_MPC_SIZE_BASE_IDX 2
#define mmDSCL3_LB_DATA_FORMAT 0x1146
#define mmDSCL3_LB_DATA_FORMAT_BASE_IDX 2
#define mmDSCL3_LB_MEMORY_CTRL 0x1147
#define mmDSCL3_LB_MEMORY_CTRL_BASE_IDX 2
#define mmDSCL3_LB_V_COUNTER 0x1148
#define mmDSCL3_LB_V_COUNTER_BASE_IDX 2
#define mmDSCL3_DSCL_MEM_PWR_CTRL 0x1149
#define mmDSCL3_DSCL_MEM_PWR_CTRL_BASE_IDX 2
#define mmDSCL3_DSCL_MEM_PWR_STATUS 0x114a
#define mmDSCL3_DSCL_MEM_PWR_STATUS_BASE_IDX 2
#define mmDSCL3_OBUF_CONTROL 0x114b
#define mmDSCL3_OBUF_CONTROL_BASE_IDX 2
#define mmDSCL3_OBUF_MEM_PWR_CTRL 0x114c
#define mmDSCL3_OBUF_MEM_PWR_CTRL_BASE_IDX 2
// addressBlock: dce_dc_dpp3_dispdec_cm_dispdec
// base address: 0x1104
#define mmCM3_CM_CONTROL 0x115b
#define mmCM3_CM_CONTROL_BASE_IDX 2
#define mmCM3_CM_ICSC_CONTROL 0x115c
#define mmCM3_CM_ICSC_CONTROL_BASE_IDX 2
#define mmCM3_CM_ICSC_C11_C12 0x115d
#define mmCM3_CM_ICSC_C11_C12_BASE_IDX 2
#define mmCM3_CM_ICSC_C13_C14 0x115e
#define mmCM3_CM_ICSC_C13_C14_BASE_IDX 2
#define mmCM3_CM_ICSC_C21_C22 0x115f
#define mmCM3_CM_ICSC_C21_C22_BASE_IDX 2
#define mmCM3_CM_ICSC_C23_C24 0x1160
#define mmCM3_CM_ICSC_C23_C24_BASE_IDX 2
#define mmCM3_CM_ICSC_C31_C32 0x1161
#define mmCM3_CM_ICSC_C31_C32_BASE_IDX 2
#define mmCM3_CM_ICSC_C33_C34 0x1162
#define mmCM3_CM_ICSC_C33_C34_BASE_IDX 2
#define mmCM3_CM_ICSC_B_C11_C12 0x1163
#define mmCM3_CM_ICSC_B_C11_C12_BASE_IDX 2
#define mmCM3_CM_ICSC_B_C13_C14 0x1164
#define mmCM3_CM_ICSC_B_C13_C14_BASE_IDX 2
#define mmCM3_CM_ICSC_B_C21_C22 0x1165
#define mmCM3_CM_ICSC_B_C21_C22_BASE_IDX 2
#define mmCM3_CM_ICSC_B_C23_C24 0x1166
#define mmCM3_CM_ICSC_B_C23_C24_BASE_IDX 2
#define mmCM3_CM_ICSC_B_C31_C32 0x1167
#define mmCM3_CM_ICSC_B_C31_C32_BASE_IDX 2
#define mmCM3_CM_ICSC_B_C33_C34 0x1168
#define mmCM3_CM_ICSC_B_C33_C34_BASE_IDX 2
#define mmCM3_CM_GAMUT_REMAP_CONTROL 0x1169
#define mmCM3_CM_GAMUT_REMAP_CONTROL_BASE_IDX 2
#define mmCM3_CM_GAMUT_REMAP_C11_C12 0x116a
#define mmCM3_CM_GAMUT_REMAP_C11_C12_BASE_IDX 2
#define mmCM3_CM_GAMUT_REMAP_C13_C14 0x116b
#define mmCM3_CM_GAMUT_REMAP_C13_C14_BASE_IDX 2
#define mmCM3_CM_GAMUT_REMAP_C21_C22 0x116c
#define mmCM3_CM_GAMUT_REMAP_C21_C22_BASE_IDX 2
#define mmCM3_CM_GAMUT_REMAP_C23_C24 0x116d
#define mmCM3_CM_GAMUT_REMAP_C23_C24_BASE_IDX 2
#define mmCM3_CM_GAMUT_REMAP_C31_C32 0x116e
#define mmCM3_CM_GAMUT_REMAP_C31_C32_BASE_IDX 2
#define mmCM3_CM_GAMUT_REMAP_C33_C34 0x116f
#define mmCM3_CM_GAMUT_REMAP_C33_C34_BASE_IDX 2
#define mmCM3_CM_GAMUT_REMAP_B_C11_C12 0x1170
#define mmCM3_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX 2
#define mmCM3_CM_GAMUT_REMAP_B_C13_C14 0x1171
#define mmCM3_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX 2
#define mmCM3_CM_GAMUT_REMAP_B_C21_C22 0x1172
#define mmCM3_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX 2
#define mmCM3_CM_GAMUT_REMAP_B_C23_C24 0x1173
#define mmCM3_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX 2
#define mmCM3_CM_GAMUT_REMAP_B_C31_C32 0x1174
#define mmCM3_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX 2
#define mmCM3_CM_GAMUT_REMAP_B_C33_C34 0x1175
#define mmCM3_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX 2
#define mmCM3_CM_BIAS_CR_R 0x1176
#define mmCM3_CM_BIAS_CR_R_BASE_IDX 2
#define mmCM3_CM_BIAS_Y_G_CB_B 0x1177
#define mmCM3_CM_BIAS_Y_G_CB_B_BASE_IDX 2
#define mmCM3_CM_DGAM_CONTROL 0x1178
#define mmCM3_CM_DGAM_CONTROL_BASE_IDX 2
#define mmCM3_CM_DGAM_LUT_INDEX 0x1179
#define mmCM3_CM_DGAM_LUT_INDEX_BASE_IDX 2
#define mmCM3_CM_DGAM_LUT_DATA 0x117a
#define mmCM3_CM_DGAM_LUT_DATA_BASE_IDX 2
#define mmCM3_CM_DGAM_LUT_WRITE_EN_MASK 0x117b
#define mmCM3_CM_DGAM_LUT_WRITE_EN_MASK_BASE_IDX 2
#define mmCM3_CM_DGAM_RAMA_START_CNTL_B 0x117c
#define mmCM3_CM_DGAM_RAMA_START_CNTL_B_BASE_IDX 2
#define mmCM3_CM_DGAM_RAMA_START_CNTL_G 0x117d
#define mmCM3_CM_DGAM_RAMA_START_CNTL_G_BASE_IDX 2
#define mmCM3_CM_DGAM_RAMA_START_CNTL_R 0x117e
#define mmCM3_CM_DGAM_RAMA_START_CNTL_R_BASE_IDX 2
#define mmCM3_CM_DGAM_RAMA_SLOPE_CNTL_B 0x117f
#define mmCM3_CM_DGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2
#define mmCM3_CM_DGAM_RAMA_SLOPE_CNTL_G 0x1180
#define mmCM3_CM_DGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2
#define mmCM3_CM_DGAM_RAMA_SLOPE_CNTL_R 0x1181
#define mmCM3_CM_DGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2
#define mmCM3_CM_DGAM_RAMA_END_CNTL1_B 0x1182
#define mmCM3_CM_DGAM_RAMA_END_CNTL1_B_BASE_IDX 2
#define mmCM3_CM_DGAM_RAMA_END_CNTL2_B 0x1183
#define mmCM3_CM_DGAM_RAMA_END_CNTL2_B_BASE_IDX 2
#define mmCM3_CM_DGAM_RAMA_END_CNTL1_G 0x1184
#define mmCM3_CM_DGAM_RAMA_END_CNTL1_G_BASE_IDX 2
#define mmCM3_CM_DGAM_RAMA_END_CNTL2_G 0x1185
#define mmCM3_CM_DGAM_RAMA_END_CNTL2_G_BASE_IDX 2
#define mmCM3_CM_DGAM_RAMA_END_CNTL1_R 0x1186
#define mmCM3_CM_DGAM_RAMA_END_CNTL1_R_BASE_IDX 2
#define mmCM3_CM_DGAM_RAMA_END_CNTL2_R 0x1187
#define mmCM3_CM_DGAM_RAMA_END_CNTL2_R_BASE_IDX 2
#define mmCM3_CM_DGAM_RAMA_REGION_0_1 0x1188
#define mmCM3_CM_DGAM_RAMA_REGION_0_1_BASE_IDX 2
#define mmCM3_CM_DGAM_RAMA_REGION_2_3 0x1189
#define mmCM3_CM_DGAM_RAMA_REGION_2_3_BASE_IDX 2
#define mmCM3_CM_DGAM_RAMA_REGION_4_5 0x118a
#define mmCM3_CM_DGAM_RAMA_REGION_4_5_BASE_IDX 2
#define mmCM3_CM_DGAM_RAMA_REGION_6_7 0x118b
#define mmCM3_CM_DGAM_RAMA_REGION_6_7_BASE_IDX 2
#define mmCM3_CM_DGAM_RAMA_REGION_8_9 0x118c
#define mmCM3_CM_DGAM_RAMA_REGION_8_9_BASE_IDX 2
#define mmCM3_CM_DGAM_RAMA_REGION_10_11 0x118d
#define mmCM3_CM_DGAM_RAMA_REGION_10_11_BASE_IDX 2
#define mmCM3_CM_DGAM_RAMA_REGION_12_13 0x118e
#define mmCM3_CM_DGAM_RAMA_REGION_12_13_BASE_IDX 2
#define mmCM3_CM_DGAM_RAMA_REGION_14_15 0x118f
#define mmCM3_CM_DGAM_RAMA_REGION_14_15_BASE_IDX 2
#define mmCM3_CM_DGAM_RAMB_START_CNTL_B 0x1190
#define mmCM3_CM_DGAM_RAMB_START_CNTL_B_BASE_IDX 2
#define mmCM3_CM_DGAM_RAMB_START_CNTL_G 0x1191
#define mmCM3_CM_DGAM_RAMB_START_CNTL_G_BASE_IDX 2
#define mmCM3_CM_DGAM_RAMB_START_CNTL_R 0x1192
#define mmCM3_CM_DGAM_RAMB_START_CNTL_R_BASE_IDX 2
#define mmCM3_CM_DGAM_RAMB_SLOPE_CNTL_B 0x1193
#define mmCM3_CM_DGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2
#define mmCM3_CM_DGAM_RAMB_SLOPE_CNTL_G 0x1194
#define mmCM3_CM_DGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2
#define mmCM3_CM_DGAM_RAMB_SLOPE_CNTL_R 0x1195
#define mmCM3_CM_DGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2
#define mmCM3_CM_DGAM_RAMB_END_CNTL1_B 0x1196
#define mmCM3_CM_DGAM_RAMB_END_CNTL1_B_BASE_IDX 2
#define mmCM3_CM_DGAM_RAMB_END_CNTL2_B 0x1197
#define mmCM3_CM_DGAM_RAMB_END_CNTL2_B_BASE_IDX 2
#define mmCM3_CM_DGAM_RAMB_END_CNTL1_G 0x1198
#define mmCM3_CM_DGAM_RAMB_END_CNTL1_G_BASE_IDX 2
#define mmCM3_CM_DGAM_RAMB_END_CNTL2_G 0x1199
#define mmCM3_CM_DGAM_RAMB_END_CNTL2_G_BASE_IDX 2
#define mmCM3_CM_DGAM_RAMB_END_CNTL1_R 0x119a
#define mmCM3_CM_DGAM_RAMB_END_CNTL1_R_BASE_IDX 2
#define mmCM3_CM_DGAM_RAMB_END_CNTL2_R 0x119b
#define mmCM3_CM_DGAM_RAMB_END_CNTL2_R_BASE_IDX 2
#define mmCM3_CM_DGAM_RAMB_REGION_0_1 0x119c
#define mmCM3_CM_DGAM_RAMB_REGION_0_1_BASE_IDX 2
#define mmCM3_CM_DGAM_RAMB_REGION_2_3 0x119d
#define mmCM3_CM_DGAM_RAMB_REGION_2_3_BASE_IDX 2
#define mmCM3_CM_DGAM_RAMB_REGION_4_5 0x119e
#define mmCM3_CM_DGAM_RAMB_REGION_4_5_BASE_IDX 2
#define mmCM3_CM_DGAM_RAMB_REGION_6_7 0x119f
#define mmCM3_CM_DGAM_RAMB_REGION_6_7_BASE_IDX 2
#define mmCM3_CM_DGAM_RAMB_REGION_8_9 0x11a0
#define mmCM3_CM_DGAM_RAMB_REGION_8_9_BASE_IDX 2
#define mmCM3_CM_DGAM_RAMB_REGION_10_11 0x11a1
#define mmCM3_CM_DGAM_RAMB_REGION_10_11_BASE_IDX 2
#define mmCM3_CM_DGAM_RAMB_REGION_12_13 0x11a2
#define mmCM3_CM_DGAM_RAMB_REGION_12_13_BASE_IDX 2
#define mmCM3_CM_DGAM_RAMB_REGION_14_15 0x11a3
#define mmCM3_CM_DGAM_RAMB_REGION_14_15_BASE_IDX 2
#define mmCM3_CM_BLNDGAM_CONTROL 0x11a4
#define mmCM3_CM_BLNDGAM_CONTROL_BASE_IDX 2
#define mmCM3_CM_BLNDGAM_LUT_INDEX 0x11a5
#define mmCM3_CM_BLNDGAM_LUT_INDEX_BASE_IDX 2
#define mmCM3_CM_BLNDGAM_LUT_DATA 0x11a6
#define mmCM3_CM_BLNDGAM_LUT_DATA_BASE_IDX 2
#define mmCM3_CM_BLNDGAM_LUT_WRITE_EN_MASK 0x11a7
#define mmCM3_CM_BLNDGAM_LUT_WRITE_EN_MASK_BASE_IDX 2
#define mmCM3_CM_BLNDGAM_RAMA_START_CNTL_B 0x11a8
#define mmCM3_CM_BLNDGAM_RAMA_START_CNTL_B_BASE_IDX 2
#define mmCM3_CM_BLNDGAM_RAMA_START_CNTL_G 0x11a9
#define mmCM3_CM_BLNDGAM_RAMA_START_CNTL_G_BASE_IDX 2
#define mmCM3_CM_BLNDGAM_RAMA_START_CNTL_R 0x11aa
#define mmCM3_CM_BLNDGAM_RAMA_START_CNTL_R_BASE_IDX 2
#define mmCM3_CM_BLNDGAM_RAMA_SLOPE_CNTL_B 0x11ab
#define mmCM3_CM_BLNDGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2
#define mmCM3_CM_BLNDGAM_RAMA_SLOPE_CNTL_G 0x11ac
#define mmCM3_CM_BLNDGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2
#define mmCM3_CM_BLNDGAM_RAMA_SLOPE_CNTL_R 0x11ad
#define mmCM3_CM_BLNDGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2
#define mmCM3_CM_BLNDGAM_RAMA_END_CNTL1_B 0x11ae
#define mmCM3_CM_BLNDGAM_RAMA_END_CNTL1_B_BASE_IDX 2
#define mmCM3_CM_BLNDGAM_RAMA_END_CNTL2_B 0x11af
#define mmCM3_CM_BLNDGAM_RAMA_END_CNTL2_B_BASE_IDX 2
#define mmCM3_CM_BLNDGAM_RAMA_END_CNTL1_G 0x11b0
#define mmCM3_CM_BLNDGAM_RAMA_END_CNTL1_G_BASE_IDX 2
#define mmCM3_CM_BLNDGAM_RAMA_END_CNTL2_G 0x11b1
#define mmCM3_CM_BLNDGAM_RAMA_END_CNTL2_G_BASE_IDX 2
#define mmCM3_CM_BLNDGAM_RAMA_END_CNTL1_R 0x11b2
#define mmCM3_CM_BLNDGAM_RAMA_END_CNTL1_R_BASE_IDX 2
#define mmCM3_CM_BLNDGAM_RAMA_END_CNTL2_R 0x11b3
#define mmCM3_CM_BLNDGAM_RAMA_END_CNTL2_R_BASE_IDX 2
#define mmCM3_CM_BLNDGAM_RAMA_REGION_0_1 0x11b4
#define mmCM3_CM_BLNDGAM_RAMA_REGION_0_1_BASE_IDX 2
#define mmCM3_CM_BLNDGAM_RAMA_REGION_2_3 0x11b5
#define mmCM3_CM_BLNDGAM_RAMA_REGION_2_3_BASE_IDX 2
#define mmCM3_CM_BLNDGAM_RAMA_REGION_4_5 0x11b6
#define mmCM3_CM_BLNDGAM_RAMA_REGION_4_5_BASE_IDX 2
#define mmCM3_CM_BLNDGAM_RAMA_REGION_6_7 0x11b7
#define mmCM3_CM_BLNDGAM_RAMA_REGION_6_7_BASE_IDX 2
#define mmCM3_CM_BLNDGAM_RAMA_REGION_8_9 0x11b8
#define mmCM3_CM_BLNDGAM_RAMA_REGION_8_9_BASE_IDX 2
#define mmCM3_CM_BLNDGAM_RAMA_REGION_10_11 0x11b9
#define mmCM3_CM_BLNDGAM_RAMA_REGION_10_11_BASE_IDX 2
#define mmCM3_CM_BLNDGAM_RAMA_REGION_12_13 0x11ba
#define mmCM3_CM_BLNDGAM_RAMA_REGION_12_13_BASE_IDX 2
#define mmCM3_CM_BLNDGAM_RAMA_REGION_14_15 0x11bb
#define mmCM3_CM_BLNDGAM_RAMA_REGION_14_15_BASE_IDX 2
#define mmCM3_CM_BLNDGAM_RAMA_REGION_16_17 0x11bc
#define mmCM3_CM_BLNDGAM_RAMA_REGION_16_17_BASE_IDX 2
#define mmCM3_CM_BLNDGAM_RAMA_REGION_18_19 0x11bd
#define mmCM3_CM_BLNDGAM_RAMA_REGION_18_19_BASE_IDX 2
#define mmCM3_CM_BLNDGAM_RAMA_REGION_20_21 0x11be
#define mmCM3_CM_BLNDGAM_RAMA_REGION_20_21_BASE_IDX 2
#define mmCM3_CM_BLNDGAM_RAMA_REGION_22_23 0x11bf
#define mmCM3_CM_BLNDGAM_RAMA_REGION_22_23_BASE_IDX 2
#define mmCM3_CM_BLNDGAM_RAMA_REGION_24_25 0x11c0
#define mmCM3_CM_BLNDGAM_RAMA_REGION_24_25_BASE_IDX 2
#define mmCM3_CM_BLNDGAM_RAMA_REGION_26_27 0x11c1
#define mmCM3_CM_BLNDGAM_RAMA_REGION_26_27_BASE_IDX 2
#define mmCM3_CM_BLNDGAM_RAMA_REGION_28_29 0x11c2
#define mmCM3_CM_BLNDGAM_RAMA_REGION_28_29_BASE_IDX 2
#define mmCM3_CM_BLNDGAM_RAMA_REGION_30_31 0x11c3
#define mmCM3_CM_BLNDGAM_RAMA_REGION_30_31_BASE_IDX 2
#define mmCM3_CM_BLNDGAM_RAMA_REGION_32_33 0x11c4
#define mmCM3_CM_BLNDGAM_RAMA_REGION_32_33_BASE_IDX 2
#define mmCM3_CM_BLNDGAM_RAMB_START_CNTL_B 0x11c5
#define mmCM3_CM_BLNDGAM_RAMB_START_CNTL_B_BASE_IDX 2
#define mmCM3_CM_BLNDGAM_RAMB_START_CNTL_G 0x11c6
#define mmCM3_CM_BLNDGAM_RAMB_START_CNTL_G_BASE_IDX 2
#define mmCM3_CM_BLNDGAM_RAMB_START_CNTL_R 0x11c7
#define mmCM3_CM_BLNDGAM_RAMB_START_CNTL_R_BASE_IDX 2
#define mmCM3_CM_BLNDGAM_RAMB_SLOPE_CNTL_B 0x11c8
#define mmCM3_CM_BLNDGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2
#define mmCM3_CM_BLNDGAM_RAMB_SLOPE_CNTL_G 0x11c9
#define mmCM3_CM_BLNDGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2
#define mmCM3_CM_BLNDGAM_RAMB_SLOPE_CNTL_R 0x11ca
#define mmCM3_CM_BLNDGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2
#define mmCM3_CM_BLNDGAM_RAMB_END_CNTL1_B 0x11cb
#define mmCM3_CM_BLNDGAM_RAMB_END_CNTL1_B_BASE_IDX 2
#define mmCM3_CM_BLNDGAM_RAMB_END_CNTL2_B 0x11cc
#define mmCM3_CM_BLNDGAM_RAMB_END_CNTL2_B_BASE_IDX 2
#define mmCM3_CM_BLNDGAM_RAMB_END_CNTL1_G 0x11cd
#define mmCM3_CM_BLNDGAM_RAMB_END_CNTL1_G_BASE_IDX 2
#define mmCM3_CM_BLNDGAM_RAMB_END_CNTL2_G 0x11ce
#define mmCM3_CM_BLNDGAM_RAMB_END_CNTL2_G_BASE_IDX 2
#define mmCM3_CM_BLNDGAM_RAMB_END_CNTL1_R 0x11cf
#define mmCM3_CM_BLNDGAM_RAMB_END_CNTL1_R_BASE_IDX 2
#define mmCM3_CM_BLNDGAM_RAMB_END_CNTL2_R 0x11d0
#define mmCM3_CM_BLNDGAM_RAMB_END_CNTL2_R_BASE_IDX 2
#define mmCM3_CM_BLNDGAM_RAMB_REGION_0_1 0x11d1
#define mmCM3_CM_BLNDGAM_RAMB_REGION_0_1_BASE_IDX 2
#define mmCM3_CM_BLNDGAM_RAMB_REGION_2_3 0x11d2
#define mmCM3_CM_BLNDGAM_RAMB_REGION_2_3_BASE_IDX 2
#define mmCM3_CM_BLNDGAM_RAMB_REGION_4_5 0x11d3
#define mmCM3_CM_BLNDGAM_RAMB_REGION_4_5_BASE_IDX 2
#define mmCM3_CM_BLNDGAM_RAMB_REGION_6_7 0x11d4
#define mmCM3_CM_BLNDGAM_RAMB_REGION_6_7_BASE_IDX 2
#define mmCM3_CM_BLNDGAM_RAMB_REGION_8_9 0x11d5
#define mmCM3_CM_BLNDGAM_RAMB_REGION_8_9_BASE_IDX 2
#define mmCM3_CM_BLNDGAM_RAMB_REGION_10_11 0x11d6
#define mmCM3_CM_BLNDGAM_RAMB_REGION_10_11_BASE_IDX 2
#define mmCM3_CM_BLNDGAM_RAMB_REGION_12_13 0x11d7
#define mmCM3_CM_BLNDGAM_RAMB_REGION_12_13_BASE_IDX 2
#define mmCM3_CM_BLNDGAM_RAMB_REGION_14_15 0x11d8
#define mmCM3_CM_BLNDGAM_RAMB_REGION_14_15_BASE_IDX 2
#define mmCM3_CM_BLNDGAM_RAMB_REGION_16_17 0x11d9
#define mmCM3_CM_BLNDGAM_RAMB_REGION_16_17_BASE_IDX 2
#define mmCM3_CM_BLNDGAM_RAMB_REGION_18_19 0x11da
#define mmCM3_CM_BLNDGAM_RAMB_REGION_18_19_BASE_IDX 2
#define mmCM3_CM_BLNDGAM_RAMB_REGION_20_21 0x11db
#define mmCM3_CM_BLNDGAM_RAMB_REGION_20_21_BASE_IDX 2
#define mmCM3_CM_BLNDGAM_RAMB_REGION_22_23 0x11dc
#define mmCM3_CM_BLNDGAM_RAMB_REGION_22_23_BASE_IDX 2
#define mmCM3_CM_BLNDGAM_RAMB_REGION_24_25 0x11dd
#define mmCM3_CM_BLNDGAM_RAMB_REGION_24_25_BASE_IDX 2
#define mmCM3_CM_BLNDGAM_RAMB_REGION_26_27 0x11de
#define mmCM3_CM_BLNDGAM_RAMB_REGION_26_27_BASE_IDX 2
#define mmCM3_CM_BLNDGAM_RAMB_REGION_28_29 0x11df
#define mmCM3_CM_BLNDGAM_RAMB_REGION_28_29_BASE_IDX 2
#define mmCM3_CM_BLNDGAM_RAMB_REGION_30_31 0x11e0
#define mmCM3_CM_BLNDGAM_RAMB_REGION_30_31_BASE_IDX 2
#define mmCM3_CM_BLNDGAM_RAMB_REGION_32_33 0x11e1
#define mmCM3_CM_BLNDGAM_RAMB_REGION_32_33_BASE_IDX 2
#define mmCM3_CM_HDR_MULT_COEF 0x11e2
#define mmCM3_CM_HDR_MULT_COEF_BASE_IDX 2
#define mmCM3_CM_MEM_PWR_CTRL 0x11e3
#define mmCM3_CM_MEM_PWR_CTRL_BASE_IDX 2
#define mmCM3_CM_MEM_PWR_STATUS 0x11e4
#define mmCM3_CM_MEM_PWR_STATUS_BASE_IDX 2
#define mmCM3_CM_DEALPHA 0x11e6
#define mmCM3_CM_DEALPHA_BASE_IDX 2
#define mmCM3_CM_COEF_FORMAT 0x11e7
#define mmCM3_CM_COEF_FORMAT_BASE_IDX 2
#define mmCM3_CM_SHAPER_CONTROL 0x11e8
#define mmCM3_CM_SHAPER_CONTROL_BASE_IDX 2
#define mmCM3_CM_SHAPER_OFFSET_R 0x11e9
#define mmCM3_CM_SHAPER_OFFSET_R_BASE_IDX 2
#define mmCM3_CM_SHAPER_OFFSET_G 0x11ea
#define mmCM3_CM_SHAPER_OFFSET_G_BASE_IDX 2
#define mmCM3_CM_SHAPER_OFFSET_B 0x11eb
#define mmCM3_CM_SHAPER_OFFSET_B_BASE_IDX 2
#define mmCM3_CM_SHAPER_SCALE_R 0x11ec
#define mmCM3_CM_SHAPER_SCALE_R_BASE_IDX 2
#define mmCM3_CM_SHAPER_SCALE_G_B 0x11ed
#define mmCM3_CM_SHAPER_SCALE_G_B_BASE_IDX 2
#define mmCM3_CM_SHAPER_LUT_INDEX 0x11ee
#define mmCM3_CM_SHAPER_LUT_INDEX_BASE_IDX 2
#define mmCM3_CM_SHAPER_LUT_DATA 0x11ef
#define mmCM3_CM_SHAPER_LUT_DATA_BASE_IDX 2
#define mmCM3_CM_SHAPER_LUT_WRITE_EN_MASK 0x11f0
#define mmCM3_CM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX 2
#define mmCM3_CM_SHAPER_RAMA_START_CNTL_B 0x11f1
#define mmCM3_CM_SHAPER_RAMA_START_CNTL_B_BASE_IDX 2
#define mmCM3_CM_SHAPER_RAMA_START_CNTL_G 0x11f2
#define mmCM3_CM_SHAPER_RAMA_START_CNTL_G_BASE_IDX 2
#define mmCM3_CM_SHAPER_RAMA_START_CNTL_R 0x11f3
#define mmCM3_CM_SHAPER_RAMA_START_CNTL_R_BASE_IDX 2
#define mmCM3_CM_SHAPER_RAMA_END_CNTL_B 0x11f4
#define mmCM3_CM_SHAPER_RAMA_END_CNTL_B_BASE_IDX 2
#define mmCM3_CM_SHAPER_RAMA_END_CNTL_G 0x11f5
#define mmCM3_CM_SHAPER_RAMA_END_CNTL_G_BASE_IDX 2
#define mmCM3_CM_SHAPER_RAMA_END_CNTL_R 0x11f6
#define mmCM3_CM_SHAPER_RAMA_END_CNTL_R_BASE_IDX 2
#define mmCM3_CM_SHAPER_RAMA_REGION_0_1 0x11f7
#define mmCM3_CM_SHAPER_RAMA_REGION_0_1_BASE_IDX 2
#define mmCM3_CM_SHAPER_RAMA_REGION_2_3 0x11f8
#define mmCM3_CM_SHAPER_RAMA_REGION_2_3_BASE_IDX 2
#define mmCM3_CM_SHAPER_RAMA_REGION_4_5 0x11f9
#define mmCM3_CM_SHAPER_RAMA_REGION_4_5_BASE_IDX 2
#define mmCM3_CM_SHAPER_RAMA_REGION_6_7 0x11fa
#define mmCM3_CM_SHAPER_RAMA_REGION_6_7_BASE_IDX 2
#define mmCM3_CM_SHAPER_RAMA_REGION_8_9 0x11fb
#define mmCM3_CM_SHAPER_RAMA_REGION_8_9_BASE_IDX 2
#define mmCM3_CM_SHAPER_RAMA_REGION_10_11 0x11fc
#define mmCM3_CM_SHAPER_RAMA_REGION_10_11_BASE_IDX 2
#define mmCM3_CM_SHAPER_RAMA_REGION_12_13 0x11fd
#define mmCM3_CM_SHAPER_RAMA_REGION_12_13_BASE_IDX 2
#define mmCM3_CM_SHAPER_RAMA_REGION_14_15 0x11fe
#define mmCM3_CM_SHAPER_RAMA_REGION_14_15_BASE_IDX 2
#define mmCM3_CM_SHAPER_RAMA_REGION_16_17 0x11ff
#define mmCM3_CM_SHAPER_RAMA_REGION_16_17_BASE_IDX 2
#define mmCM3_CM_SHAPER_RAMA_REGION_18_19 0x1200
#define mmCM3_CM_SHAPER_RAMA_REGION_18_19_BASE_IDX 2
#define mmCM3_CM_SHAPER_RAMA_REGION_20_21 0x1201
#define mmCM3_CM_SHAPER_RAMA_REGION_20_21_BASE_IDX 2
#define mmCM3_CM_SHAPER_RAMA_REGION_22_23 0x1202
#define mmCM3_CM_SHAPER_RAMA_REGION_22_23_BASE_IDX 2
#define mmCM3_CM_SHAPER_RAMA_REGION_24_25 0x1203
#define mmCM3_CM_SHAPER_RAMA_REGION_24_25_BASE_IDX 2
#define mmCM3_CM_SHAPER_RAMA_REGION_26_27 0x1204
#define mmCM3_CM_SHAPER_RAMA_REGION_26_27_BASE_IDX 2
#define mmCM3_CM_SHAPER_RAMA_REGION_28_29 0x1205
#define mmCM3_CM_SHAPER_RAMA_REGION_28_29_BASE_IDX 2
#define mmCM3_CM_SHAPER_RAMA_REGION_30_31 0x1206
#define mmCM3_CM_SHAPER_RAMA_REGION_30_31_BASE_IDX 2
#define mmCM3_CM_SHAPER_RAMA_REGION_32_33 0x1207
#define mmCM3_CM_SHAPER_RAMA_REGION_32_33_BASE_IDX 2
#define mmCM3_CM_SHAPER_RAMB_START_CNTL_B 0x1208
#define mmCM3_CM_SHAPER_RAMB_START_CNTL_B_BASE_IDX 2
#define mmCM3_CM_SHAPER_RAMB_START_CNTL_G 0x1209
#define mmCM3_CM_SHAPER_RAMB_START_CNTL_G_BASE_IDX 2
#define mmCM3_CM_SHAPER_RAMB_START_CNTL_R 0x120a
#define mmCM3_CM_SHAPER_RAMB_START_CNTL_R_BASE_IDX 2
#define mmCM3_CM_SHAPER_RAMB_END_CNTL_B 0x120b
#define mmCM3_CM_SHAPER_RAMB_END_CNTL_B_BASE_IDX 2
#define mmCM3_CM_SHAPER_RAMB_END_CNTL_G 0x120c
#define mmCM3_CM_SHAPER_RAMB_END_CNTL_G_BASE_IDX 2
#define mmCM3_CM_SHAPER_RAMB_END_CNTL_R 0x120d
#define mmCM3_CM_SHAPER_RAMB_END_CNTL_R_BASE_IDX 2
#define mmCM3_CM_SHAPER_RAMB_REGION_0_1 0x120e
#define mmCM3_CM_SHAPER_RAMB_REGION_0_1_BASE_IDX 2
#define mmCM3_CM_SHAPER_RAMB_REGION_2_3 0x120f
#define mmCM3_CM_SHAPER_RAMB_REGION_2_3_BASE_IDX 2
#define mmCM3_CM_SHAPER_RAMB_REGION_4_5 0x1210
#define mmCM3_CM_SHAPER_RAMB_REGION_4_5_BASE_IDX 2
#define mmCM3_CM_SHAPER_RAMB_REGION_6_7 0x1211
#define mmCM3_CM_SHAPER_RAMB_REGION_6_7_BASE_IDX 2
#define mmCM3_CM_SHAPER_RAMB_REGION_8_9 0x1212
#define mmCM3_CM_SHAPER_RAMB_REGION_8_9_BASE_IDX 2
#define mmCM3_CM_SHAPER_RAMB_REGION_10_11 0x1213
#define mmCM3_CM_SHAPER_RAMB_REGION_10_11_BASE_IDX 2
#define mmCM3_CM_SHAPER_RAMB_REGION_12_13 0x1214
#define mmCM3_CM_SHAPER_RAMB_REGION_12_13_BASE_IDX 2
#define mmCM3_CM_SHAPER_RAMB_REGION_14_15 0x1215
#define mmCM3_CM_SHAPER_RAMB_REGION_14_15_BASE_IDX 2
#define mmCM3_CM_SHAPER_RAMB_REGION_16_17 0x1216
#define mmCM3_CM_SHAPER_RAMB_REGION_16_17_BASE_IDX 2
#define mmCM3_CM_SHAPER_RAMB_REGION_18_19 0x1217
#define mmCM3_CM_SHAPER_RAMB_REGION_18_19_BASE_IDX 2
#define mmCM3_CM_SHAPER_RAMB_REGION_20_21 0x1218
#define mmCM3_CM_SHAPER_RAMB_REGION_20_21_BASE_IDX 2
#define mmCM3_CM_SHAPER_RAMB_REGION_22_23 0x1219
#define mmCM3_CM_SHAPER_RAMB_REGION_22_23_BASE_IDX 2
#define mmCM3_CM_SHAPER_RAMB_REGION_24_25 0x121a
#define mmCM3_CM_SHAPER_RAMB_REGION_24_25_BASE_IDX 2
#define mmCM3_CM_SHAPER_RAMB_REGION_26_27 0x121b
#define mmCM3_CM_SHAPER_RAMB_REGION_26_27_BASE_IDX 2
#define mmCM3_CM_SHAPER_RAMB_REGION_28_29 0x121c
#define mmCM3_CM_SHAPER_RAMB_REGION_28_29_BASE_IDX 2
#define mmCM3_CM_SHAPER_RAMB_REGION_30_31 0x121d
#define mmCM3_CM_SHAPER_RAMB_REGION_30_31_BASE_IDX 2
#define mmCM3_CM_SHAPER_RAMB_REGION_32_33 0x121e
#define mmCM3_CM_SHAPER_RAMB_REGION_32_33_BASE_IDX 2
#define mmCM3_CM_MEM_PWR_CTRL2 0x121f
#define mmCM3_CM_MEM_PWR_CTRL2_BASE_IDX 2
#define mmCM3_CM_MEM_PWR_STATUS2 0x1220
#define mmCM3_CM_MEM_PWR_STATUS2_BASE_IDX 2
#define mmCM3_CM_3DLUT_MODE 0x1221
#define mmCM3_CM_3DLUT_MODE_BASE_IDX 2
#define mmCM3_CM_3DLUT_INDEX 0x1222
#define mmCM3_CM_3DLUT_INDEX_BASE_IDX 2
#define mmCM3_CM_3DLUT_DATA 0x1223
#define mmCM3_CM_3DLUT_DATA_BASE_IDX 2
#define mmCM3_CM_3DLUT_DATA_30BIT 0x1224
#define mmCM3_CM_3DLUT_DATA_30BIT_BASE_IDX 2
#define mmCM3_CM_3DLUT_READ_WRITE_CONTROL 0x1225
#define mmCM3_CM_3DLUT_READ_WRITE_CONTROL_BASE_IDX 2
#define mmCM3_CM_3DLUT_OUT_NORM_FACTOR 0x1226
#define mmCM3_CM_3DLUT_OUT_NORM_FACTOR_BASE_IDX 2
#define mmCM3_CM_3DLUT_OUT_OFFSET_R 0x1227
#define mmCM3_CM_3DLUT_OUT_OFFSET_R_BASE_IDX 2
#define mmCM3_CM_3DLUT_OUT_OFFSET_G 0x1228
#define mmCM3_CM_3DLUT_OUT_OFFSET_G_BASE_IDX 2
#define mmCM3_CM_3DLUT_OUT_OFFSET_B 0x1229
#define mmCM3_CM_3DLUT_OUT_OFFSET_B_BASE_IDX 2
#define mmCM3_CM_TEST_DEBUG_INDEX 0x122a
#define mmCM3_CM_TEST_DEBUG_INDEX_BASE_IDX 2
#define mmCM3_CM_TEST_DEBUG_DATA 0x122b
#define mmCM3_CM_TEST_DEBUG_DATA_BASE_IDX 2
// addressBlock: dce_dc_mpc_mpcc0_dispdec
// base address: 0x0
#define mmMPCC0_MPCC_TOP_SEL 0x1271
#define mmMPCC0_MPCC_TOP_SEL_BASE_IDX 2
#define mmMPCC0_MPCC_BOT_SEL 0x1272
#define mmMPCC0_MPCC_BOT_SEL_BASE_IDX 2
#define mmMPCC0_MPCC_OPP_ID 0x1273
#define mmMPCC0_MPCC_OPP_ID_BASE_IDX 2
#define mmMPCC0_MPCC_CONTROL 0x1274
#define mmMPCC0_MPCC_CONTROL_BASE_IDX 2
#define mmMPCC0_MPCC_SM_CONTROL 0x1275
#define mmMPCC0_MPCC_SM_CONTROL_BASE_IDX 2
#define mmMPCC0_MPCC_UPDATE_LOCK_SEL 0x1276
#define mmMPCC0_MPCC_UPDATE_LOCK_SEL_BASE_IDX 2
#define mmMPCC0_MPCC_TOP_GAIN 0x1277
#define mmMPCC0_MPCC_TOP_GAIN_BASE_IDX 2
#define mmMPCC0_MPCC_BOT_GAIN_INSIDE 0x1278
#define mmMPCC0_MPCC_BOT_GAIN_INSIDE_BASE_IDX 2
#define mmMPCC0_MPCC_BOT_GAIN_OUTSIDE 0x1279
#define mmMPCC0_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX 2
#define mmMPCC0_MPCC_BG_R_CR 0x127a
#define mmMPCC0_MPCC_BG_R_CR_BASE_IDX 2
#define mmMPCC0_MPCC_BG_G_Y 0x127b
#define mmMPCC0_MPCC_BG_G_Y_BASE_IDX 2
#define mmMPCC0_MPCC_BG_B_CB 0x127c
#define mmMPCC0_MPCC_BG_B_CB_BASE_IDX 2
#define mmMPCC0_MPCC_MEM_PWR_CTRL 0x127d
#define mmMPCC0_MPCC_MEM_PWR_CTRL_BASE_IDX 2
#define mmMPCC0_MPCC_STALL_STATUS 0x127e
#define mmMPCC0_MPCC_STALL_STATUS_BASE_IDX 2
#define mmMPCC0_MPCC_STATUS 0x127f
#define mmMPCC0_MPCC_STATUS_BASE_IDX 2
// addressBlock: dce_dc_mpc_mpcc1_dispdec
// base address: 0x6c
#define mmMPCC1_MPCC_TOP_SEL 0x128c
#define mmMPCC1_MPCC_TOP_SEL_BASE_IDX 2
#define mmMPCC1_MPCC_BOT_SEL 0x128d
#define mmMPCC1_MPCC_BOT_SEL_BASE_IDX 2
#define mmMPCC1_MPCC_OPP_ID 0x128e
#define mmMPCC1_MPCC_OPP_ID_BASE_IDX 2
#define mmMPCC1_MPCC_CONTROL 0x128f
#define mmMPCC1_MPCC_CONTROL_BASE_IDX 2
#define mmMPCC1_MPCC_SM_CONTROL 0x1290
#define mmMPCC1_MPCC_SM_CONTROL_BASE_IDX 2
#define mmMPCC1_MPCC_UPDATE_LOCK_SEL 0x1291
#define mmMPCC1_MPCC_UPDATE_LOCK_SEL_BASE_IDX 2
#define mmMPCC1_MPCC_TOP_GAIN 0x1292
#define mmMPCC1_MPCC_TOP_GAIN_BASE_IDX 2
#define mmMPCC1_MPCC_BOT_GAIN_INSIDE 0x1293
#define mmMPCC1_MPCC_BOT_GAIN_INSIDE_BASE_IDX 2
#define mmMPCC1_MPCC_BOT_GAIN_OUTSIDE 0x1294
#define mmMPCC1_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX 2
#define mmMPCC1_MPCC_BG_R_CR 0x1295
#define mmMPCC1_MPCC_BG_R_CR_BASE_IDX 2
#define mmMPCC1_MPCC_BG_G_Y 0x1296
#define mmMPCC1_MPCC_BG_G_Y_BASE_IDX 2
#define mmMPCC1_MPCC_BG_B_CB 0x1297
#define mmMPCC1_MPCC_BG_B_CB_BASE_IDX 2
#define mmMPCC1_MPCC_MEM_PWR_CTRL 0x1298
#define mmMPCC1_MPCC_MEM_PWR_CTRL_BASE_IDX 2
#define mmMPCC1_MPCC_STALL_STATUS 0x1299
#define mmMPCC1_MPCC_STALL_STATUS_BASE_IDX 2
#define mmMPCC1_MPCC_STATUS 0x129a
#define mmMPCC1_MPCC_STATUS_BASE_IDX 2
// addressBlock: dce_dc_mpc_mpcc2_dispdec
// base address: 0xd8
#define mmMPCC2_MPCC_TOP_SEL 0x12a7
#define mmMPCC2_MPCC_TOP_SEL_BASE_IDX 2
#define mmMPCC2_MPCC_BOT_SEL 0x12a8
#define mmMPCC2_MPCC_BOT_SEL_BASE_IDX 2
#define mmMPCC2_MPCC_OPP_ID 0x12a9
#define mmMPCC2_MPCC_OPP_ID_BASE_IDX 2
#define mmMPCC2_MPCC_CONTROL 0x12aa
#define mmMPCC2_MPCC_CONTROL_BASE_IDX 2
#define mmMPCC2_MPCC_SM_CONTROL 0x12ab
#define mmMPCC2_MPCC_SM_CONTROL_BASE_IDX 2
#define mmMPCC2_MPCC_UPDATE_LOCK_SEL 0x12ac
#define mmMPCC2_MPCC_UPDATE_LOCK_SEL_BASE_IDX 2
#define mmMPCC2_MPCC_TOP_GAIN 0x12ad
#define mmMPCC2_MPCC_TOP_GAIN_BASE_IDX 2
#define mmMPCC2_MPCC_BOT_GAIN_INSIDE 0x12ae
#define mmMPCC2_MPCC_BOT_GAIN_INSIDE_BASE_IDX 2
#define mmMPCC2_MPCC_BOT_GAIN_OUTSIDE 0x12af
#define mmMPCC2_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX 2
#define mmMPCC2_MPCC_BG_R_CR 0x12b0
#define mmMPCC2_MPCC_BG_R_CR_BASE_IDX 2
#define mmMPCC2_MPCC_BG_G_Y 0x12b1
#define mmMPCC2_MPCC_BG_G_Y_BASE_IDX 2
#define mmMPCC2_MPCC_BG_B_CB 0x12b2
#define mmMPCC2_MPCC_BG_B_CB_BASE_IDX 2
#define mmMPCC2_MPCC_MEM_PWR_CTRL 0x12b3
#define mmMPCC2_MPCC_MEM_PWR_CTRL_BASE_IDX 2
#define mmMPCC2_MPCC_STALL_STATUS 0x12b4
#define mmMPCC2_MPCC_STALL_STATUS_BASE_IDX 2
#define mmMPCC2_MPCC_STATUS 0x12b5
#define mmMPCC2_MPCC_STATUS_BASE_IDX 2
// addressBlock: dce_dc_mpc_mpcc3_dispdec
// base address: 0x144
#define mmMPCC3_MPCC_TOP_SEL 0x12c2
#define mmMPCC3_MPCC_TOP_SEL_BASE_IDX 2
#define mmMPCC3_MPCC_BOT_SEL 0x12c3
#define mmMPCC3_MPCC_BOT_SEL_BASE_IDX 2
#define mmMPCC3_MPCC_OPP_ID 0x12c4
#define mmMPCC3_MPCC_OPP_ID_BASE_IDX 2
#define mmMPCC3_MPCC_CONTROL 0x12c5
#define mmMPCC3_MPCC_CONTROL_BASE_IDX 2
#define mmMPCC3_MPCC_SM_CONTROL 0x12c6
#define mmMPCC3_MPCC_SM_CONTROL_BASE_IDX 2
#define mmMPCC3_MPCC_UPDATE_LOCK_SEL 0x12c7
#define mmMPCC3_MPCC_UPDATE_LOCK_SEL_BASE_IDX 2
#define mmMPCC3_MPCC_TOP_GAIN 0x12c8
#define mmMPCC3_MPCC_TOP_GAIN_BASE_IDX 2
#define mmMPCC3_MPCC_BOT_GAIN_INSIDE 0x12c9
#define mmMPCC3_MPCC_BOT_GAIN_INSIDE_BASE_IDX 2
#define mmMPCC3_MPCC_BOT_GAIN_OUTSIDE 0x12ca
#define mmMPCC3_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX 2
#define mmMPCC3_MPCC_BG_R_CR 0x12cb
#define mmMPCC3_MPCC_BG_R_CR_BASE_IDX 2
#define mmMPCC3_MPCC_BG_G_Y 0x12cc
#define mmMPCC3_MPCC_BG_G_Y_BASE_IDX 2
#define mmMPCC3_MPCC_BG_B_CB 0x12cd
#define mmMPCC3_MPCC_BG_B_CB_BASE_IDX 2
#define mmMPCC3_MPCC_MEM_PWR_CTRL 0x12ce
#define mmMPCC3_MPCC_MEM_PWR_CTRL_BASE_IDX 2
#define mmMPCC3_MPCC_STALL_STATUS 0x12cf
#define mmMPCC3_MPCC_STALL_STATUS_BASE_IDX 2
#define mmMPCC3_MPCC_STATUS 0x12d0
#define mmMPCC3_MPCC_STATUS_BASE_IDX 2
// addressBlock: dce_dc_mpc_mpcc4_dispdec
// base address: 0x1b0
#define mmMPCC4_MPCC_TOP_SEL 0x12dd
#define mmMPCC4_MPCC_TOP_SEL_BASE_IDX 2
#define mmMPCC4_MPCC_BOT_SEL 0x12de
#define mmMPCC4_MPCC_BOT_SEL_BASE_IDX 2
#define mmMPCC4_MPCC_OPP_ID 0x12df
#define mmMPCC4_MPCC_OPP_ID_BASE_IDX 2
#define mmMPCC4_MPCC_CONTROL 0x12e0
#define mmMPCC4_MPCC_CONTROL_BASE_IDX 2
#define mmMPCC4_MPCC_SM_CONTROL 0x12e1
#define mmMPCC4_MPCC_SM_CONTROL_BASE_IDX 2
#define mmMPCC4_MPCC_UPDATE_LOCK_SEL 0x12e2
#define mmMPCC4_MPCC_UPDATE_LOCK_SEL_BASE_IDX 2
#define mmMPCC4_MPCC_TOP_GAIN 0x12e3
#define mmMPCC4_MPCC_TOP_GAIN_BASE_IDX 2
#define mmMPCC4_MPCC_BOT_GAIN_INSIDE 0x12e4
#define mmMPCC4_MPCC_BOT_GAIN_INSIDE_BASE_IDX 2
#define mmMPCC4_MPCC_BOT_GAIN_OUTSIDE 0x12e5
#define mmMPCC4_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX 2
#define mmMPCC4_MPCC_BG_R_CR 0x12e6
#define mmMPCC4_MPCC_BG_R_CR_BASE_IDX 2
#define mmMPCC4_MPCC_BG_G_Y 0x12e7
#define mmMPCC4_MPCC_BG_G_Y_BASE_IDX 2
#define mmMPCC4_MPCC_BG_B_CB 0x12e8
#define mmMPCC4_MPCC_BG_B_CB_BASE_IDX 2
#define mmMPCC4_MPCC_MEM_PWR_CTRL 0x12e9
#define mmMPCC4_MPCC_MEM_PWR_CTRL_BASE_IDX 2
#define mmMPCC4_MPCC_STALL_STATUS 0x12ea
#define mmMPCC4_MPCC_STALL_STATUS_BASE_IDX 2
#define mmMPCC4_MPCC_STATUS 0x12eb
#define mmMPCC4_MPCC_STATUS_BASE_IDX 2
// addressBlock: dce_dc_mpc_mpc_cfg_dispdec
// base address: 0x0
#define mmMPC_CLOCK_CONTROL 0x1349
#define mmMPC_CLOCK_CONTROL_BASE_IDX 2
#define mmMPC_SOFT_RESET 0x134a
#define mmMPC_SOFT_RESET_BASE_IDX 2
#define mmMPC_CRC_CTRL 0x134b
#define mmMPC_CRC_CTRL_BASE_IDX 2
#define mmMPC_CRC_SEL_CONTROL 0x134c
#define mmMPC_CRC_SEL_CONTROL_BASE_IDX 2
#define mmMPC_CRC_RESULT_AR 0x134d
#define mmMPC_CRC_RESULT_AR_BASE_IDX 2
#define mmMPC_CRC_RESULT_GB 0x134e
#define mmMPC_CRC_RESULT_GB_BASE_IDX 2
#define mmMPC_CRC_RESULT_C 0x134f
#define mmMPC_CRC_RESULT_C_BASE_IDX 2
#define mmMPC_PERFMON_EVENT_CTRL 0x1352
#define mmMPC_PERFMON_EVENT_CTRL_BASE_IDX 2
#define mmMPC_BYPASS_BG_AR 0x1353
#define mmMPC_BYPASS_BG_AR_BASE_IDX 2
#define mmMPC_BYPASS_BG_GB 0x1354
#define mmMPC_BYPASS_BG_GB_BASE_IDX 2
#define mmMPC_STALL_GRACE_WINDOW 0x1355
#define mmMPC_STALL_GRACE_WINDOW_BASE_IDX 2
#define mmMPC_HOST_READ_CONTROL 0x1356
#define mmMPC_HOST_READ_CONTROL_BASE_IDX 2
#define mmADR_CFG_CUR_VUPDATE_LOCK_SET0 0x135d
#define mmADR_CFG_CUR_VUPDATE_LOCK_SET0_BASE_IDX 2
#define mmADR_CFG_VUPDATE_LOCK_SET0 0x135e
#define mmADR_CFG_VUPDATE_LOCK_SET0_BASE_IDX 2
#define mmADR_VUPDATE_LOCK_SET0 0x135f
#define mmADR_VUPDATE_LOCK_SET0_BASE_IDX 2
#define mmCFG_VUPDATE_LOCK_SET0 0x1360
#define mmCFG_VUPDATE_LOCK_SET0_BASE_IDX 2
#define mmCUR_VUPDATE_LOCK_SET0 0x1361
#define mmCUR_VUPDATE_LOCK_SET0_BASE_IDX 2
#define mmADR_CFG_CUR_VUPDATE_LOCK_SET1 0x1362
#define mmADR_CFG_CUR_VUPDATE_LOCK_SET1_BASE_IDX 2
#define mmADR_CFG_VUPDATE_LOCK_SET1 0x1363
#define mmADR_CFG_VUPDATE_LOCK_SET1_BASE_IDX 2
#define mmADR_VUPDATE_LOCK_SET1 0x1364
#define mmADR_VUPDATE_LOCK_SET1_BASE_IDX 2
#define mmCFG_VUPDATE_LOCK_SET1 0x1365
#define mmCFG_VUPDATE_LOCK_SET1_BASE_IDX 2
#define mmCUR_VUPDATE_LOCK_SET1 0x1366
#define mmCUR_VUPDATE_LOCK_SET1_BASE_IDX 2
#define mmADR_CFG_CUR_VUPDATE_LOCK_SET2 0x1367
#define mmADR_CFG_CUR_VUPDATE_LOCK_SET2_BASE_IDX 2
#define mmADR_CFG_VUPDATE_LOCK_SET2 0x1368
#define mmADR_CFG_VUPDATE_LOCK_SET2_BASE_IDX 2
#define mmADR_VUPDATE_LOCK_SET2 0x1369
#define mmADR_VUPDATE_LOCK_SET2_BASE_IDX 2
#define mmCFG_VUPDATE_LOCK_SET2 0x136a
#define mmCFG_VUPDATE_LOCK_SET2_BASE_IDX 2
#define mmCUR_VUPDATE_LOCK_SET2 0x136b
#define mmCUR_VUPDATE_LOCK_SET2_BASE_IDX 2
#define mmADR_CFG_CUR_VUPDATE_LOCK_SET3 0x136c
#define mmADR_CFG_CUR_VUPDATE_LOCK_SET3_BASE_IDX 2
#define mmADR_CFG_VUPDATE_LOCK_SET3 0x136d
#define mmADR_CFG_VUPDATE_LOCK_SET3_BASE_IDX 2
#define mmADR_VUPDATE_LOCK_SET3 0x136e
#define mmADR_VUPDATE_LOCK_SET3_BASE_IDX 2
#define mmCFG_VUPDATE_LOCK_SET3 0x136f
#define mmCFG_VUPDATE_LOCK_SET3_BASE_IDX 2
#define mmCUR_VUPDATE_LOCK_SET3 0x1370
#define mmCUR_VUPDATE_LOCK_SET3_BASE_IDX 2
#define mmMPC_OUT0_MUX 0x1385
#define mmMPC_OUT0_MUX_BASE_IDX 2
#define mmMPC_OUT0_DENORM_CONTROL 0x1386
#define mmMPC_OUT0_DENORM_CONTROL_BASE_IDX 2
#define mmMPC_OUT0_DENORM_CLAMP_G_Y 0x1387
#define mmMPC_OUT0_DENORM_CLAMP_G_Y_BASE_IDX 2
#define mmMPC_OUT0_DENORM_CLAMP_B_CB 0x1388
#define mmMPC_OUT0_DENORM_CLAMP_B_CB_BASE_IDX 2
#define mmMPC_OUT1_MUX 0x1389
#define mmMPC_OUT1_MUX_BASE_IDX 2
#define mmMPC_OUT1_DENORM_CONTROL 0x138a
#define mmMPC_OUT1_DENORM_CONTROL_BASE_IDX 2
#define mmMPC_OUT1_DENORM_CLAMP_G_Y 0x138b
#define mmMPC_OUT1_DENORM_CLAMP_G_Y_BASE_IDX 2
#define mmMPC_OUT1_DENORM_CLAMP_B_CB 0x138c
#define mmMPC_OUT1_DENORM_CLAMP_B_CB_BASE_IDX 2
// addressBlock: dce_dc_mpc_mpcc_ogam0_dispdec
// base address: 0x0
#define mmMPCC_OGAM0_MPCC_OGAM_MODE 0x13ae
#define mmMPCC_OGAM0_MPCC_OGAM_MODE_BASE_IDX 2
#define mmMPCC_OGAM0_MPCC_OGAM_LUT_INDEX 0x13af
#define mmMPCC_OGAM0_MPCC_OGAM_LUT_INDEX_BASE_IDX 2
#define mmMPCC_OGAM0_MPCC_OGAM_LUT_DATA 0x13b0
#define mmMPCC_OGAM0_MPCC_OGAM_LUT_DATA_BASE_IDX 2
#define mmMPCC_OGAM0_MPCC_OGAM_LUT_RAM_CONTROL 0x13b1
#define mmMPCC_OGAM0_MPCC_OGAM_LUT_RAM_CONTROL_BASE_IDX 2
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B 0x13b2
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX 2
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G 0x13b3
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX 2
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R 0x13b4
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX 2
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_SLOPE_CNTL_B 0x13b5
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_SLOPE_CNTL_G 0x13b6
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_SLOPE_CNTL_R 0x13b7
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B 0x13b8
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX 2
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B 0x13b9
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX 2
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G 0x13ba
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX 2
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G 0x13bb
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX 2
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R 0x13bc
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX 2
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R 0x13bd
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX 2
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1 0x13be
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX 2
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3 0x13bf
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX 2
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5 0x13c0
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX 2
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7 0x13c1
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX 2
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9 0x13c2
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX 2
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11 0x13c3
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX 2
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13 0x13c4
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX 2
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15 0x13c5
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX 2
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17 0x13c6
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX 2
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19 0x13c7
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX 2
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21 0x13c8
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX 2
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23 0x13c9
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX 2
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25 0x13ca
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX 2
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27 0x13cb
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX 2
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29 0x13cc
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX 2
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31 0x13cd
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX 2
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33 0x13ce
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX 2
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B 0x13cf
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX 2
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G 0x13d0
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX 2
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R 0x13d1
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX 2
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_SLOPE_CNTL_B 0x13d2
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_SLOPE_CNTL_G 0x13d3
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_SLOPE_CNTL_R 0x13d4
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B 0x13d5
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX 2
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B 0x13d6
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX 2
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G 0x13d7
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX 2
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G 0x13d8
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX 2
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R 0x13d9
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX 2
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R 0x13da
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX 2
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1 0x13db
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX 2
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3 0x13dc
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX 2
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5 0x13dd
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX 2
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7 0x13de
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX 2
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9 0x13df
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX 2
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11 0x13e0
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX 2
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13 0x13e1
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX 2
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15 0x13e2
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX 2
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17 0x13e3
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX 2
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19 0x13e4
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX 2
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21 0x13e5
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX 2
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23 0x13e6
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX 2
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25 0x13e7
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX 2
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27 0x13e8
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX 2
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29 0x13e9
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX 2
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31 0x13ea
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX 2
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33 0x13eb
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX 2
// addressBlock: dce_dc_mpc_mpcc_ogam1_dispdec
// base address: 0x104
#define mmMPCC_OGAM1_MPCC_OGAM_MODE 0x13ef
#define mmMPCC_OGAM1_MPCC_OGAM_MODE_BASE_IDX 2
#define mmMPCC_OGAM1_MPCC_OGAM_LUT_INDEX 0x13f0
#define mmMPCC_OGAM1_MPCC_OGAM_LUT_INDEX_BASE_IDX 2
#define mmMPCC_OGAM1_MPCC_OGAM_LUT_DATA 0x13f1
#define mmMPCC_OGAM1_MPCC_OGAM_LUT_DATA_BASE_IDX 2
#define mmMPCC_OGAM1_MPCC_OGAM_LUT_RAM_CONTROL 0x13f2
#define mmMPCC_OGAM1_MPCC_OGAM_LUT_RAM_CONTROL_BASE_IDX 2
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B 0x13f3
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX 2
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G 0x13f4
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX 2
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R 0x13f5
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX 2
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_SLOPE_CNTL_B 0x13f6
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_SLOPE_CNTL_G 0x13f7
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_SLOPE_CNTL_R 0x13f8
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B 0x13f9
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX 2
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B 0x13fa
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX 2
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G 0x13fb
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX 2
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G 0x13fc
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX 2
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R 0x13fd
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX 2
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R 0x13fe
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX 2
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1 0x13ff
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX 2
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3 0x1400
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX 2
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5 0x1401
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX 2
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7 0x1402
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX 2
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9 0x1403
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX 2
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11 0x1404
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX 2
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13 0x1405
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX 2
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15 0x1406
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX 2
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17 0x1407
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX 2
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19 0x1408
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX 2
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21 0x1409
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX 2
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23 0x140a
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX 2
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25 0x140b
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX 2
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27 0x140c
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX 2
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29 0x140d
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX 2
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31 0x140e
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX 2
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33 0x140f
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX 2
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B 0x1410
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX 2
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G 0x1411
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX 2
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R 0x1412
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX 2
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_SLOPE_CNTL_B 0x1413
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_SLOPE_CNTL_G 0x1414
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_SLOPE_CNTL_R 0x1415
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B 0x1416
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX 2
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B 0x1417
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX 2
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G 0x1418
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX 2
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G 0x1419
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX 2
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R 0x141a
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX 2
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R 0x141b
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX 2
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1 0x141c
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX 2
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3 0x141d
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX 2
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5 0x141e
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX 2
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7 0x141f
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX 2
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9 0x1420
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX 2
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11 0x1421
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX 2
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13 0x1422
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX 2
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15 0x1423
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX 2
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17 0x1424
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX 2
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19 0x1425
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX 2
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21 0x1426
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX 2
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23 0x1427
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX 2
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25 0x1428
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX 2
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27 0x1429
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX 2
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29 0x142a
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX 2
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31 0x142b
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX 2
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33 0x142c
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX 2
// addressBlock: dce_dc_mpc_mpcc_ogam2_dispdec
// base address: 0x208
#define mmMPCC_OGAM2_MPCC_OGAM_MODE 0x1430
#define mmMPCC_OGAM2_MPCC_OGAM_MODE_BASE_IDX 2
#define mmMPCC_OGAM2_MPCC_OGAM_LUT_INDEX 0x1431
#define mmMPCC_OGAM2_MPCC_OGAM_LUT_INDEX_BASE_IDX 2
#define mmMPCC_OGAM2_MPCC_OGAM_LUT_DATA 0x1432
#define mmMPCC_OGAM2_MPCC_OGAM_LUT_DATA_BASE_IDX 2
#define mmMPCC_OGAM2_MPCC_OGAM_LUT_RAM_CONTROL 0x1433
#define mmMPCC_OGAM2_MPCC_OGAM_LUT_RAM_CONTROL_BASE_IDX 2
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B 0x1434
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX 2
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G 0x1435
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX 2
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R 0x1436
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX 2
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_SLOPE_CNTL_B 0x1437
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_SLOPE_CNTL_G 0x1438
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_SLOPE_CNTL_R 0x1439
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_B 0x143a
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX 2
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B 0x143b
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX 2
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_G 0x143c
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX 2
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G 0x143d
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX 2
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_R 0x143e
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX 2
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R 0x143f
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX 2
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1 0x1440
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX 2
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3 0x1441
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX 2
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5 0x1442
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX 2
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7 0x1443
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX 2
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9 0x1444
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX 2
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11 0x1445
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX 2
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13 0x1446
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX 2
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15 0x1447
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX 2
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17 0x1448
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX 2
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19 0x1449
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX 2
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21 0x144a
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX 2
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23 0x144b
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX 2
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25 0x144c
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX 2
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27 0x144d
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX 2
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29 0x144e
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX 2
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31 0x144f
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX 2
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33 0x1450
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX 2
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B 0x1451
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX 2
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G 0x1452
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX 2
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R 0x1453
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX 2
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_SLOPE_CNTL_B 0x1454
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_SLOPE_CNTL_G 0x1455
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_SLOPE_CNTL_R 0x1456
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_B 0x1457
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX 2
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B 0x1458
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX 2
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_G 0x1459
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX 2
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G 0x145a
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX 2
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_R 0x145b
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX 2
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R 0x145c
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX 2
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1 0x145d
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX 2
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3 0x145e
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX 2
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5 0x145f
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX 2
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7 0x1460
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX 2
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9 0x1461
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX 2
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11 0x1462
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX 2
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13 0x1463
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX 2
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15 0x1464
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX 2
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17 0x1465
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX 2
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19 0x1466
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX 2
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21 0x1467
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX 2
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23 0x1468
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX 2
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25 0x1469
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX 2
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27 0x146a
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX 2
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29 0x146b
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX 2
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31 0x146c
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX 2
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33 0x146d
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX 2
// addressBlock: dce_dc_mpc_mpcc_ogam3_dispdec
// base address: 0x30c
#define mmMPCC_OGAM3_MPCC_OGAM_MODE 0x1471
#define mmMPCC_OGAM3_MPCC_OGAM_MODE_BASE_IDX 2
#define mmMPCC_OGAM3_MPCC_OGAM_LUT_INDEX 0x1472
#define mmMPCC_OGAM3_MPCC_OGAM_LUT_INDEX_BASE_IDX 2
#define mmMPCC_OGAM3_MPCC_OGAM_LUT_DATA 0x1473
#define mmMPCC_OGAM3_MPCC_OGAM_LUT_DATA_BASE_IDX 2
#define mmMPCC_OGAM3_MPCC_OGAM_LUT_RAM_CONTROL 0x1474
#define mmMPCC_OGAM3_MPCC_OGAM_LUT_RAM_CONTROL_BASE_IDX 2
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B 0x1475
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX 2
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G 0x1476
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX 2
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R 0x1477
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX 2
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_SLOPE_CNTL_B 0x1478
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_SLOPE_CNTL_G 0x1479
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_SLOPE_CNTL_R 0x147a
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_B 0x147b
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX 2
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B 0x147c
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX 2
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G 0x147d
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX 2
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G 0x147e
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX 2
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_R 0x147f
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX 2
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R 0x1480
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX 2
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1 0x1481
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX 2
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3 0x1482
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX 2
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5 0x1483
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX 2
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7 0x1484
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX 2
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9 0x1485
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX 2
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11 0x1486
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX 2
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13 0x1487
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX 2
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15 0x1488
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX 2
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17 0x1489
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX 2
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19 0x148a
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX 2
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21 0x148b
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX 2
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23 0x148c
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX 2
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25 0x148d
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX 2
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27 0x148e
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX 2
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29 0x148f
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX 2
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31 0x1490
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX 2
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33 0x1491
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX 2
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B 0x1492
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX 2
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G 0x1493
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX 2
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R 0x1494
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX 2
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_SLOPE_CNTL_B 0x1495
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_SLOPE_CNTL_G 0x1496
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_SLOPE_CNTL_R 0x1497
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_B 0x1498
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX 2
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B 0x1499
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX 2
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_G 0x149a
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX 2
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G 0x149b
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX 2
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_R 0x149c
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX 2
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R 0x149d
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX 2
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1 0x149e
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX 2
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3 0x149f
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX 2
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5 0x14a0
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX 2
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7 0x14a1
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX 2
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9 0x14a2
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX 2
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11 0x14a3
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX 2
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13 0x14a4
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX 2
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15 0x14a5
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX 2
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17 0x14a6
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX 2
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19 0x14a7
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX 2
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21 0x14a8
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX 2
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23 0x14a9
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX 2
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25 0x14aa
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX 2
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27 0x14ab
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX 2
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29 0x14ac
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX 2
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31 0x14ad
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX 2
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33 0x14ae
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX 2
// addressBlock: dce_dc_mpc_mpcc_ogam4_dispdec
// base address: 0x410
#define mmMPCC_OGAM4_MPCC_OGAM_MODE 0x14b2
#define mmMPCC_OGAM4_MPCC_OGAM_MODE_BASE_IDX 2
#define mmMPCC_OGAM4_MPCC_OGAM_LUT_INDEX 0x14b3
#define mmMPCC_OGAM4_MPCC_OGAM_LUT_INDEX_BASE_IDX 2
#define mmMPCC_OGAM4_MPCC_OGAM_LUT_DATA 0x14b4
#define mmMPCC_OGAM4_MPCC_OGAM_LUT_DATA_BASE_IDX 2
#define mmMPCC_OGAM4_MPCC_OGAM_LUT_RAM_CONTROL 0x14b5
#define mmMPCC_OGAM4_MPCC_OGAM_LUT_RAM_CONTROL_BASE_IDX 2
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_B 0x14b6
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX 2
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_G 0x14b7
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX 2
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_R 0x14b8
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX 2
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_SLOPE_CNTL_B 0x14b9
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_SLOPE_CNTL_G 0x14ba
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_SLOPE_CNTL_R 0x14bb
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL1_B 0x14bc
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX 2
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_B 0x14bd
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX 2
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL1_G 0x14be
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX 2
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_G 0x14bf
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX 2
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL1_R 0x14c0
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX 2
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_R 0x14c1
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX 2
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_0_1 0x14c2
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX 2
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_2_3 0x14c3
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX 2
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_4_5 0x14c4
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX 2
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_6_7 0x14c5
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX 2
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_8_9 0x14c6
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX 2
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_10_11 0x14c7
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX 2
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_12_13 0x14c8
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX 2
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_14_15 0x14c9
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX 2
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_16_17 0x14ca
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX 2
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_18_19 0x14cb
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX 2
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_20_21 0x14cc
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX 2
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_22_23 0x14cd
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX 2
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_24_25 0x14ce
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX 2
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_26_27 0x14cf
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX 2
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_28_29 0x14d0
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX 2
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_30_31 0x14d1
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX 2
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_32_33 0x14d2
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX 2
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_B 0x14d3
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX 2
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_G 0x14d4
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX 2
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_R 0x14d5
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX 2
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_SLOPE_CNTL_B 0x14d6
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_SLOPE_CNTL_G 0x14d7
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_SLOPE_CNTL_R 0x14d8
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL1_B 0x14d9
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX 2
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_B 0x14da
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX 2
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL1_G 0x14db
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX 2
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_G 0x14dc
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX 2
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL1_R 0x14dd
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX 2
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_R 0x14de
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX 2
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_0_1 0x14df
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX 2
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_2_3 0x14e0
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX 2
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_4_5 0x14e1
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX 2
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_6_7 0x14e2
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX 2
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_8_9 0x14e3
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX 2
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_10_11 0x14e4
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX 2
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_12_13 0x14e5
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX 2
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_14_15 0x14e6
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX 2
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_16_17 0x14e7
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX 2
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_18_19 0x14e8
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX 2
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_20_21 0x14e9
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX 2
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_22_23 0x14ea
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX 2
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_24_25 0x14eb
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX 2
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_26_27 0x14ec
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX 2
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_28_29 0x14ed
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX 2
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_30_31 0x14ee
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX 2
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_32_33 0x14ef
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX 2
// addressBlock: dce_dc_mpc_mpc_ocsc_dispdec
// base address: 0x0
#define mmMPC_OUT_CSC_COEF_FORMAT 0x15b6
#define mmMPC_OUT_CSC_COEF_FORMAT_BASE_IDX 2
#define mmMPC_OUT0_CSC_MODE 0x15b7
#define mmMPC_OUT0_CSC_MODE_BASE_IDX 2
#define mmMPC_OUT0_CSC_C11_C12_A 0x15b8
#define mmMPC_OUT0_CSC_C11_C12_A_BASE_IDX 2
#define mmMPC_OUT0_CSC_C13_C14_A 0x15b9
#define mmMPC_OUT0_CSC_C13_C14_A_BASE_IDX 2
#define mmMPC_OUT0_CSC_C21_C22_A 0x15ba
#define mmMPC_OUT0_CSC_C21_C22_A_BASE_IDX 2
#define mmMPC_OUT0_CSC_C23_C24_A 0x15bb
#define mmMPC_OUT0_CSC_C23_C24_A_BASE_IDX 2
#define mmMPC_OUT0_CSC_C31_C32_A 0x15bc
#define mmMPC_OUT0_CSC_C31_C32_A_BASE_IDX 2
#define mmMPC_OUT0_CSC_C33_C34_A 0x15bd
#define mmMPC_OUT0_CSC_C33_C34_A_BASE_IDX 2
#define mmMPC_OUT0_CSC_C11_C12_B 0x15be
#define mmMPC_OUT0_CSC_C11_C12_B_BASE_IDX 2
#define mmMPC_OUT0_CSC_C13_C14_B 0x15bf
#define mmMPC_OUT0_CSC_C13_C14_B_BASE_IDX 2
#define mmMPC_OUT0_CSC_C21_C22_B 0x15c0
#define mmMPC_OUT0_CSC_C21_C22_B_BASE_IDX 2
#define mmMPC_OUT0_CSC_C23_C24_B 0x15c1
#define mmMPC_OUT0_CSC_C23_C24_B_BASE_IDX 2
#define mmMPC_OUT0_CSC_C31_C32_B 0x15c2
#define mmMPC_OUT0_CSC_C31_C32_B_BASE_IDX 2
#define mmMPC_OUT0_CSC_C33_C34_B 0x15c3
#define mmMPC_OUT0_CSC_C33_C34_B_BASE_IDX 2
#define mmMPC_OUT1_CSC_MODE 0x15c4
#define mmMPC_OUT1_CSC_MODE_BASE_IDX 2
#define mmMPC_OUT1_CSC_C11_C12_A 0x15c5
#define mmMPC_OUT1_CSC_C11_C12_A_BASE_IDX 2
#define mmMPC_OUT1_CSC_C13_C14_A 0x15c6
#define mmMPC_OUT1_CSC_C13_C14_A_BASE_IDX 2
#define mmMPC_OUT1_CSC_C21_C22_A 0x15c7
#define mmMPC_OUT1_CSC_C21_C22_A_BASE_IDX 2
#define mmMPC_OUT1_CSC_C23_C24_A 0x15c8
#define mmMPC_OUT1_CSC_C23_C24_A_BASE_IDX 2
#define mmMPC_OUT1_CSC_C31_C32_A 0x15c9
#define mmMPC_OUT1_CSC_C31_C32_A_BASE_IDX 2
#define mmMPC_OUT1_CSC_C33_C34_A 0x15ca
#define mmMPC_OUT1_CSC_C33_C34_A_BASE_IDX 2
#define mmMPC_OUT1_CSC_C11_C12_B 0x15cb
#define mmMPC_OUT1_CSC_C11_C12_B_BASE_IDX 2
#define mmMPC_OUT1_CSC_C13_C14_B 0x15cc
#define mmMPC_OUT1_CSC_C13_C14_B_BASE_IDX 2
#define mmMPC_OUT1_CSC_C21_C22_B 0x15cd
#define mmMPC_OUT1_CSC_C21_C22_B_BASE_IDX 2
#define mmMPC_OUT1_CSC_C23_C24_B 0x15ce
#define mmMPC_OUT1_CSC_C23_C24_B_BASE_IDX 2
#define mmMPC_OUT1_CSC_C31_C32_B 0x15cf
#define mmMPC_OUT1_CSC_C31_C32_B_BASE_IDX 2
#define mmMPC_OUT1_CSC_C33_C34_B 0x15d0
#define mmMPC_OUT1_CSC_C33_C34_B_BASE_IDX 2
// addressBlock: dce_dc_opp_fmt0_dispdec
// base address: 0x0
#define mmFMT0_FMT_CLAMP_COMPONENT_R 0x183c
#define mmFMT0_FMT_CLAMP_COMPONENT_R_BASE_IDX 2
#define mmFMT0_FMT_CLAMP_COMPONENT_G 0x183d
#define mmFMT0_FMT_CLAMP_COMPONENT_G_BASE_IDX 2
#define mmFMT0_FMT_CLAMP_COMPONENT_B 0x183e
#define mmFMT0_FMT_CLAMP_COMPONENT_B_BASE_IDX 2
#define mmFMT0_FMT_DYNAMIC_EXP_CNTL 0x183f
#define mmFMT0_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2
#define mmFMT0_FMT_CONTROL 0x1840
#define mmFMT0_FMT_CONTROL_BASE_IDX 2
#define mmFMT0_FMT_BIT_DEPTH_CONTROL 0x1841
#define mmFMT0_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2
#define mmFMT0_FMT_DITHER_RAND_R_SEED 0x1842
#define mmFMT0_FMT_DITHER_RAND_R_SEED_BASE_IDX 2
#define mmFMT0_FMT_DITHER_RAND_G_SEED 0x1843
#define mmFMT0_FMT_DITHER_RAND_G_SEED_BASE_IDX 2
#define mmFMT0_FMT_DITHER_RAND_B_SEED 0x1844
#define mmFMT0_FMT_DITHER_RAND_B_SEED_BASE_IDX 2
#define mmFMT0_FMT_CLAMP_CNTL 0x1845
#define mmFMT0_FMT_CLAMP_CNTL_BASE_IDX 2
#define mmFMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x1846
#define mmFMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2
#define mmFMT0_FMT_MAP420_MEMORY_CONTROL 0x1847
#define mmFMT0_FMT_MAP420_MEMORY_CONTROL_BASE_IDX 2
#define mmFMT0_FMT_422_CONTROL 0x1849
#define mmFMT0_FMT_422_CONTROL_BASE_IDX 2
// addressBlock: dce_dc_opp_dpg0_dispdec
// base address: 0x0
#define mmDPG0_DPG_CONTROL 0x1854
#define mmDPG0_DPG_CONTROL_BASE_IDX 2
#define mmDPG0_DPG_RAMP_CONTROL 0x1855
#define mmDPG0_DPG_RAMP_CONTROL_BASE_IDX 2
#define mmDPG0_DPG_DIMENSIONS 0x1856
#define mmDPG0_DPG_DIMENSIONS_BASE_IDX 2
#define mmDPG0_DPG_COLOUR_R_CR 0x1857
#define mmDPG0_DPG_COLOUR_R_CR_BASE_IDX 2
#define mmDPG0_DPG_COLOUR_G_Y 0x1858
#define mmDPG0_DPG_COLOUR_G_Y_BASE_IDX 2
#define mmDPG0_DPG_COLOUR_B_CB 0x1859
#define mmDPG0_DPG_COLOUR_B_CB_BASE_IDX 2
#define mmDPG0_DPG_OFFSET_SEGMENT 0x185a
#define mmDPG0_DPG_OFFSET_SEGMENT_BASE_IDX 2
#define mmDPG0_DPG_STATUS 0x185b
#define mmDPG0_DPG_STATUS_BASE_IDX 2
// addressBlock: dce_dc_opp_oppbuf0_dispdec
// base address: 0x0
#define mmOPPBUF0_OPPBUF_CONTROL 0x1884
#define mmOPPBUF0_OPPBUF_CONTROL_BASE_IDX 2
#define mmOPPBUF0_OPPBUF_3D_PARAMETERS_0 0x1885
#define mmOPPBUF0_OPPBUF_3D_PARAMETERS_0_BASE_IDX 2
#define mmOPPBUF0_OPPBUF_3D_PARAMETERS_1 0x1886
#define mmOPPBUF0_OPPBUF_3D_PARAMETERS_1_BASE_IDX 2
// addressBlock: dce_dc_opp_opp_pipe0_dispdec
// base address: 0x0
#define mmOPP_PIPE0_OPP_PIPE_CONTROL 0x188c
#define mmOPP_PIPE0_OPP_PIPE_CONTROL_BASE_IDX 2
// addressBlock: dce_dc_opp_opp_pipe_crc0_dispdec
// base address: 0x0
#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL 0x1891
#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL_BASE_IDX 2
#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_MASK 0x1892
#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_MASK_BASE_IDX 2
#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0 0x1893
#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0_BASE_IDX 2
#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1 0x1894
#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1_BASE_IDX 2
#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2 0x1895
#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2_BASE_IDX 2
// addressBlock: dce_dc_opp_fmt1_dispdec
// base address: 0x168
#define mmFMT1_FMT_CLAMP_COMPONENT_R 0x1896
#define mmFMT1_FMT_CLAMP_COMPONENT_R_BASE_IDX 2
#define mmFMT1_FMT_CLAMP_COMPONENT_G 0x1897
#define mmFMT1_FMT_CLAMP_COMPONENT_G_BASE_IDX 2
#define mmFMT1_FMT_CLAMP_COMPONENT_B 0x1898
#define mmFMT1_FMT_CLAMP_COMPONENT_B_BASE_IDX 2
#define mmFMT1_FMT_DYNAMIC_EXP_CNTL 0x1899
#define mmFMT1_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2
#define mmFMT1_FMT_CONTROL 0x189a
#define mmFMT1_FMT_CONTROL_BASE_IDX 2
#define mmFMT1_FMT_BIT_DEPTH_CONTROL 0x189b
#define mmFMT1_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2
#define mmFMT1_FMT_DITHER_RAND_R_SEED 0x189c
#define mmFMT1_FMT_DITHER_RAND_R_SEED_BASE_IDX 2
#define mmFMT1_FMT_DITHER_RAND_G_SEED 0x189d
#define mmFMT1_FMT_DITHER_RAND_G_SEED_BASE_IDX 2
#define mmFMT1_FMT_DITHER_RAND_B_SEED 0x189e
#define mmFMT1_FMT_DITHER_RAND_B_SEED_BASE_IDX 2
#define mmFMT1_FMT_CLAMP_CNTL 0x189f
#define mmFMT1_FMT_CLAMP_CNTL_BASE_IDX 2
#define mmFMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x18a0
#define mmFMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2
#define mmFMT1_FMT_MAP420_MEMORY_CONTROL 0x18a1
#define mmFMT1_FMT_MAP420_MEMORY_CONTROL_BASE_IDX 2
#define mmFMT1_FMT_422_CONTROL 0x18a3
#define mmFMT1_FMT_422_CONTROL_BASE_IDX 2
// addressBlock: dce_dc_opp_dpg1_dispdec
// base address: 0x168
#define mmDPG1_DPG_CONTROL 0x18ae
#define mmDPG1_DPG_CONTROL_BASE_IDX 2
#define mmDPG1_DPG_RAMP_CONTROL 0x18af
#define mmDPG1_DPG_RAMP_CONTROL_BASE_IDX 2
#define mmDPG1_DPG_DIMENSIONS 0x18b0
#define mmDPG1_DPG_DIMENSIONS_BASE_IDX 2
#define mmDPG1_DPG_COLOUR_R_CR 0x18b1
#define mmDPG1_DPG_COLOUR_R_CR_BASE_IDX 2
#define mmDPG1_DPG_COLOUR_G_Y 0x18b2
#define mmDPG1_DPG_COLOUR_G_Y_BASE_IDX 2
#define mmDPG1_DPG_COLOUR_B_CB 0x18b3
#define mmDPG1_DPG_COLOUR_B_CB_BASE_IDX 2
#define mmDPG1_DPG_OFFSET_SEGMENT 0x18b4
#define mmDPG1_DPG_OFFSET_SEGMENT_BASE_IDX 2
#define mmDPG1_DPG_STATUS 0x18b5
#define mmDPG1_DPG_STATUS_BASE_IDX 2
// addressBlock: dce_dc_opp_oppbuf1_dispdec
// base address: 0x168
#define mmOPPBUF1_OPPBUF_CONTROL 0x18de
#define mmOPPBUF1_OPPBUF_CONTROL_BASE_IDX 2
#define mmOPPBUF1_OPPBUF_3D_PARAMETERS_0 0x18df
#define mmOPPBUF1_OPPBUF_3D_PARAMETERS_0_BASE_IDX 2
#define mmOPPBUF1_OPPBUF_3D_PARAMETERS_1 0x18e0
#define mmOPPBUF1_OPPBUF_3D_PARAMETERS_1_BASE_IDX 2
// addressBlock: dce_dc_opp_opp_pipe1_dispdec
// base address: 0x168
#define mmOPP_PIPE1_OPP_PIPE_CONTROL 0x18e6
#define mmOPP_PIPE1_OPP_PIPE_CONTROL_BASE_IDX 2
// addressBlock: dce_dc_opp_opp_pipe_crc1_dispdec
// base address: 0x168
#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL 0x18eb
#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL_BASE_IDX 2
#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_MASK 0x18ec
#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_MASK_BASE_IDX 2
#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0 0x18ed
#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0_BASE_IDX 2
#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1 0x18ee
#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1_BASE_IDX 2
#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2 0x18ef
#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2_BASE_IDX 2
// addressBlock: dce_dc_opp_opp_top_dispdec
// base address: 0x0
#define mmOPP_TOP_CLK_CONTROL 0x1a5e
#define mmOPP_TOP_CLK_CONTROL_BASE_IDX 2
// addressBlock: dce_dc_optc_odm0_dispdec
// base address: 0x0
#define mmODM0_OPTC_INPUT_GLOBAL_CONTROL 0x1aca
#define mmODM0_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX 2
#define mmODM0_OPTC_DATA_SOURCE_SELECT 0x1acb
#define mmODM0_OPTC_DATA_SOURCE_SELECT_BASE_IDX 2
#define mmODM0_OPTC_DATA_FORMAT_CONTROL 0x1acc
#define mmODM0_OPTC_DATA_FORMAT_CONTROL_BASE_IDX 2
#define mmODM0_OPTC_BYTES_PER_PIXEL 0x1acd
#define mmODM0_OPTC_BYTES_PER_PIXEL_BASE_IDX 2
#define mmODM0_OPTC_WIDTH_CONTROL 0x1ace
#define mmODM0_OPTC_WIDTH_CONTROL_BASE_IDX 2
#define mmODM0_OPTC_INPUT_CLOCK_CONTROL 0x1acf
#define mmODM0_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX 2
// addressBlock: dce_dc_optc_odm1_dispdec
// base address: 0x40
#define mmODM1_OPTC_INPUT_GLOBAL_CONTROL 0x1ada
#define mmODM1_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX 2
#define mmODM1_OPTC_DATA_SOURCE_SELECT 0x1adb
#define mmODM1_OPTC_DATA_SOURCE_SELECT_BASE_IDX 2
#define mmODM1_OPTC_DATA_FORMAT_CONTROL 0x1adc
#define mmODM1_OPTC_DATA_FORMAT_CONTROL_BASE_IDX 2
#define mmODM1_OPTC_BYTES_PER_PIXEL 0x1add
#define mmODM1_OPTC_BYTES_PER_PIXEL_BASE_IDX 2
#define mmODM1_OPTC_WIDTH_CONTROL 0x1ade
#define mmODM1_OPTC_WIDTH_CONTROL_BASE_IDX 2
#define mmODM1_OPTC_INPUT_CLOCK_CONTROL 0x1adf
#define mmODM1_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX 2
// addressBlock: dce_dc_optc_otg0_dispdec
// base address: 0x0
#define mmOTG0_OTG_H_TOTAL 0x1b2a
#define mmOTG0_OTG_H_TOTAL_BASE_IDX 2
#define mmOTG0_OTG_H_BLANK_START_END 0x1b2b
#define mmOTG0_OTG_H_BLANK_START_END_BASE_IDX 2
#define mmOTG0_OTG_H_SYNC_A 0x1b2c
#define mmOTG0_OTG_H_SYNC_A_BASE_IDX 2
#define mmOTG0_OTG_H_SYNC_A_CNTL 0x1b2d
#define mmOTG0_OTG_H_SYNC_A_CNTL_BASE_IDX 2
#define mmOTG0_OTG_H_TIMING_CNTL 0x1b2e
#define mmOTG0_OTG_H_TIMING_CNTL_BASE_IDX 2
#define mmOTG0_OTG_V_TOTAL 0x1b2f
#define mmOTG0_OTG_V_TOTAL_BASE_IDX 2
#define mmOTG0_OTG_V_TOTAL_MIN 0x1b30
#define mmOTG0_OTG_V_TOTAL_MIN_BASE_IDX 2
#define mmOTG0_OTG_V_TOTAL_MAX 0x1b31
#define mmOTG0_OTG_V_TOTAL_MAX_BASE_IDX 2
#define mmOTG0_OTG_V_TOTAL_MID 0x1b32
#define mmOTG0_OTG_V_TOTAL_MID_BASE_IDX 2
#define mmOTG0_OTG_V_TOTAL_CONTROL 0x1b33
#define mmOTG0_OTG_V_TOTAL_CONTROL_BASE_IDX 2
#define mmOTG0_OTG_V_TOTAL_INT_STATUS 0x1b34
#define mmOTG0_OTG_V_TOTAL_INT_STATUS_BASE_IDX 2
#define mmOTG0_OTG_VSYNC_NOM_INT_STATUS 0x1b35
#define mmOTG0_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX 2
#define mmOTG0_OTG_V_BLANK_START_END 0x1b36
#define mmOTG0_OTG_V_BLANK_START_END_BASE_IDX 2
#define mmOTG0_OTG_V_SYNC_A 0x1b37
#define mmOTG0_OTG_V_SYNC_A_BASE_IDX 2
#define mmOTG0_OTG_V_SYNC_A_CNTL 0x1b38
#define mmOTG0_OTG_V_SYNC_A_CNTL_BASE_IDX 2
#define mmOTG0_OTG_TRIGA_CNTL 0x1b39
#define mmOTG0_OTG_TRIGA_CNTL_BASE_IDX 2
#define mmOTG0_OTG_TRIGA_MANUAL_TRIG 0x1b3a
#define mmOTG0_OTG_TRIGA_MANUAL_TRIG_BASE_IDX 2
#define mmOTG0_OTG_TRIGB_CNTL 0x1b3b
#define mmOTG0_OTG_TRIGB_CNTL_BASE_IDX 2
#define mmOTG0_OTG_TRIGB_MANUAL_TRIG 0x1b3c
#define mmOTG0_OTG_TRIGB_MANUAL_TRIG_BASE_IDX 2
#define mmOTG0_OTG_FORCE_COUNT_NOW_CNTL 0x1b3d
#define mmOTG0_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX 2
#define mmOTG0_OTG_STEREO_FORCE_NEXT_EYE 0x1b3f
#define mmOTG0_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX 2
#define mmOTG0_OTG_CONTROL 0x1b41
#define mmOTG0_OTG_CONTROL_BASE_IDX 2
#define mmOTG0_OTG_BLANK_CONTROL 0x1b42
#define mmOTG0_OTG_BLANK_CONTROL_BASE_IDX 2
#define mmOTG0_OTG_INTERLACE_CONTROL 0x1b44
#define mmOTG0_OTG_INTERLACE_CONTROL_BASE_IDX 2
#define mmOTG0_OTG_INTERLACE_STATUS 0x1b45
#define mmOTG0_OTG_INTERLACE_STATUS_BASE_IDX 2
#define mmOTG0_OTG_PIXEL_DATA_READBACK0 0x1b47
#define mmOTG0_OTG_PIXEL_DATA_READBACK0_BASE_IDX 2
#define mmOTG0_OTG_PIXEL_DATA_READBACK1 0x1b48
#define mmOTG0_OTG_PIXEL_DATA_READBACK1_BASE_IDX 2
#define mmOTG0_OTG_STATUS 0x1b49
#define mmOTG0_OTG_STATUS_BASE_IDX 2
#define mmOTG0_OTG_STATUS_POSITION 0x1b4a
#define mmOTG0_OTG_STATUS_POSITION_BASE_IDX 2
#define mmOTG0_OTG_NOM_VERT_POSITION 0x1b4b
#define mmOTG0_OTG_NOM_VERT_POSITION_BASE_IDX 2
#define mmOTG0_OTG_STATUS_FRAME_COUNT 0x1b4c
#define mmOTG0_OTG_STATUS_FRAME_COUNT_BASE_IDX 2
#define mmOTG0_OTG_STATUS_VF_COUNT 0x1b4d
#define mmOTG0_OTG_STATUS_VF_COUNT_BASE_IDX 2
#define mmOTG0_OTG_STATUS_HV_COUNT 0x1b4e
#define mmOTG0_OTG_STATUS_HV_COUNT_BASE_IDX 2
#define mmOTG0_OTG_COUNT_CONTROL 0x1b4f
#define mmOTG0_OTG_COUNT_CONTROL_BASE_IDX 2
#define mmOTG0_OTG_COUNT_RESET 0x1b50
#define mmOTG0_OTG_COUNT_RESET_BASE_IDX 2
#define mmOTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1b51
#define mmOTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2
#define mmOTG0_OTG_VERT_SYNC_CONTROL 0x1b52
#define mmOTG0_OTG_VERT_SYNC_CONTROL_BASE_IDX 2
#define mmOTG0_OTG_STEREO_STATUS 0x1b53
#define mmOTG0_OTG_STEREO_STATUS_BASE_IDX 2
#define mmOTG0_OTG_STEREO_CONTROL 0x1b54
#define mmOTG0_OTG_STEREO_CONTROL_BASE_IDX 2
#define mmOTG0_OTG_SNAPSHOT_STATUS 0x1b55
#define mmOTG0_OTG_SNAPSHOT_STATUS_BASE_IDX 2
#define mmOTG0_OTG_SNAPSHOT_CONTROL 0x1b56
#define mmOTG0_OTG_SNAPSHOT_CONTROL_BASE_IDX 2
#define mmOTG0_OTG_SNAPSHOT_POSITION 0x1b57
#define mmOTG0_OTG_SNAPSHOT_POSITION_BASE_IDX 2
#define mmOTG0_OTG_SNAPSHOT_FRAME 0x1b58
#define mmOTG0_OTG_SNAPSHOT_FRAME_BASE_IDX 2
#define mmOTG0_OTG_INTERRUPT_CONTROL 0x1b59
#define mmOTG0_OTG_INTERRUPT_CONTROL_BASE_IDX 2
#define mmOTG0_OTG_UPDATE_LOCK 0x1b5a
#define mmOTG0_OTG_UPDATE_LOCK_BASE_IDX 2
#define mmOTG0_OTG_DOUBLE_BUFFER_CONTROL 0x1b5b
#define mmOTG0_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX 2
#define mmOTG0_OTG_MASTER_EN 0x1b5c
#define mmOTG0_OTG_MASTER_EN_BASE_IDX 2
#define mmOTG0_OTG_BLANK_DATA_COLOR 0x1b5e
#define mmOTG0_OTG_BLANK_DATA_COLOR_BASE_IDX 2
#define mmOTG0_OTG_BLANK_DATA_COLOR_EXT 0x1b5f
#define mmOTG0_OTG_BLANK_DATA_COLOR_EXT_BASE_IDX 2
#define mmOTG0_OTG_BLACK_COLOR 0x1b60
#define mmOTG0_OTG_BLACK_COLOR_BASE_IDX 2
#define mmOTG0_OTG_BLACK_COLOR_EXT 0x1b61
#define mmOTG0_OTG_BLACK_COLOR_EXT_BASE_IDX 2
#define mmOTG0_OTG_VERTICAL_INTERRUPT0_POSITION 0x1b62
#define mmOTG0_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2
#define mmOTG0_OTG_VERTICAL_INTERRUPT0_CONTROL 0x1b63
#define mmOTG0_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2
#define mmOTG0_OTG_VERTICAL_INTERRUPT1_POSITION 0x1b64
#define mmOTG0_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2
#define mmOTG0_OTG_VERTICAL_INTERRUPT1_CONTROL 0x1b65
#define mmOTG0_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2
#define mmOTG0_OTG_VERTICAL_INTERRUPT2_POSITION 0x1b66
#define mmOTG0_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2
#define mmOTG0_OTG_VERTICAL_INTERRUPT2_CONTROL 0x1b67
#define mmOTG0_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2
#define mmOTG0_OTG_CRC_CNTL 0x1b68
#define mmOTG0_OTG_CRC_CNTL_BASE_IDX 2
#define mmOTG0_OTG_CRC_CNTL2 0x1b69
#define mmOTG0_OTG_CRC_CNTL2_BASE_IDX 2
#define mmOTG0_OTG_CRC0_WINDOWA_X_CONTROL 0x1b6a
#define mmOTG0_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2
#define mmOTG0_OTG_CRC0_WINDOWA_Y_CONTROL 0x1b6b
#define mmOTG0_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2
#define mmOTG0_OTG_CRC0_WINDOWB_X_CONTROL 0x1b6c
#define mmOTG0_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2
#define mmOTG0_OTG_CRC0_WINDOWB_Y_CONTROL 0x1b6d
#define mmOTG0_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2
#define mmOTG0_OTG_CRC0_DATA_RG 0x1b6e
#define mmOTG0_OTG_CRC0_DATA_RG_BASE_IDX 2
#define mmOTG0_OTG_CRC0_DATA_B 0x1b6f
#define mmOTG0_OTG_CRC0_DATA_B_BASE_IDX 2
#define mmOTG0_OTG_CRC1_WINDOWA_X_CONTROL 0x1b70
#define mmOTG0_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2
#define mmOTG0_OTG_CRC1_WINDOWA_Y_CONTROL 0x1b71
#define mmOTG0_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2
#define mmOTG0_OTG_CRC1_WINDOWB_X_CONTROL 0x1b72
#define mmOTG0_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2
#define mmOTG0_OTG_CRC1_WINDOWB_Y_CONTROL 0x1b73
#define mmOTG0_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2
#define mmOTG0_OTG_CRC1_DATA_RG 0x1b74
#define mmOTG0_OTG_CRC1_DATA_RG_BASE_IDX 2
#define mmOTG0_OTG_CRC1_DATA_B 0x1b75
#define mmOTG0_OTG_CRC1_DATA_B_BASE_IDX 2
#define mmOTG0_OTG_CRC_SIG_RED_GREEN_MASK 0x1b7a
#define mmOTG0_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2
#define mmOTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK 0x1b7b
#define mmOTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2
#define mmOTG0_OTG_STATIC_SCREEN_CONTROL 0x1b82
#define mmOTG0_OTG_STATIC_SCREEN_CONTROL_BASE_IDX 2
#define mmOTG0_OTG_3D_STRUCTURE_CONTROL 0x1b83
#define mmOTG0_OTG_3D_STRUCTURE_CONTROL_BASE_IDX 2
#define mmOTG0_OTG_GSL_VSYNC_GAP 0x1b84
#define mmOTG0_OTG_GSL_VSYNC_GAP_BASE_IDX 2
#define mmOTG0_OTG_MASTER_UPDATE_MODE 0x1b85
#define mmOTG0_OTG_MASTER_UPDATE_MODE_BASE_IDX 2
#define mmOTG0_OTG_CLOCK_CONTROL 0x1b86
#define mmOTG0_OTG_CLOCK_CONTROL_BASE_IDX 2
#define mmOTG0_OTG_VSTARTUP_PARAM 0x1b87
#define mmOTG0_OTG_VSTARTUP_PARAM_BASE_IDX 2
#define mmOTG0_OTG_VUPDATE_PARAM 0x1b88
#define mmOTG0_OTG_VUPDATE_PARAM_BASE_IDX 2
#define mmOTG0_OTG_VREADY_PARAM 0x1b89
#define mmOTG0_OTG_VREADY_PARAM_BASE_IDX 2
#define mmOTG0_OTG_GLOBAL_SYNC_STATUS 0x1b8a
#define mmOTG0_OTG_GLOBAL_SYNC_STATUS_BASE_IDX 2
#define mmOTG0_OTG_MASTER_UPDATE_LOCK 0x1b8b
#define mmOTG0_OTG_MASTER_UPDATE_LOCK_BASE_IDX 2
#define mmOTG0_OTG_GSL_CONTROL 0x1b8c
#define mmOTG0_OTG_GSL_CONTROL_BASE_IDX 2
#define mmOTG0_OTG_GSL_WINDOW_X 0x1b8d
#define mmOTG0_OTG_GSL_WINDOW_X_BASE_IDX 2
#define mmOTG0_OTG_GSL_WINDOW_Y 0x1b8e
#define mmOTG0_OTG_GSL_WINDOW_Y_BASE_IDX 2
#define mmOTG0_OTG_VUPDATE_KEEPOUT 0x1b8f
#define mmOTG0_OTG_VUPDATE_KEEPOUT_BASE_IDX 2
#define mmOTG0_OTG_GLOBAL_CONTROL0 0x1b90
#define mmOTG0_OTG_GLOBAL_CONTROL0_BASE_IDX 2
#define mmOTG0_OTG_GLOBAL_CONTROL1 0x1b91
#define mmOTG0_OTG_GLOBAL_CONTROL1_BASE_IDX 2
#define mmOTG0_OTG_GLOBAL_CONTROL2 0x1b92
#define mmOTG0_OTG_GLOBAL_CONTROL2_BASE_IDX 2
#define mmOTG0_OTG_GLOBAL_CONTROL3 0x1b93
#define mmOTG0_OTG_GLOBAL_CONTROL3_BASE_IDX 2
#define mmOTG0_OTG_TRIG_MANUAL_CONTROL 0x1b94
#define mmOTG0_OTG_TRIG_MANUAL_CONTROL_BASE_IDX 2
#define mmOTG0_OTG_DRR_CONTROL 0x1b97
#define mmOTG0_OTG_DRR_CONTROL_BASE_IDX 2
#define mmOTG0_OTG_DSC_START_POSITION 0x1b99
#define mmOTG0_OTG_DSC_START_POSITION_BASE_IDX 2
// addressBlock: dce_dc_optc_otg1_dispdec
// base address: 0x200
#define mmOTG1_OTG_H_TOTAL 0x1baa
#define mmOTG1_OTG_H_TOTAL_BASE_IDX 2
#define mmOTG1_OTG_H_BLANK_START_END 0x1bab
#define mmOTG1_OTG_H_BLANK_START_END_BASE_IDX 2
#define mmOTG1_OTG_H_SYNC_A 0x1bac
#define mmOTG1_OTG_H_SYNC_A_BASE_IDX 2
#define mmOTG1_OTG_H_SYNC_A_CNTL 0x1bad
#define mmOTG1_OTG_H_SYNC_A_CNTL_BASE_IDX 2
#define mmOTG1_OTG_H_TIMING_CNTL 0x1bae
#define mmOTG1_OTG_H_TIMING_CNTL_BASE_IDX 2
#define mmOTG1_OTG_V_TOTAL 0x1baf
#define mmOTG1_OTG_V_TOTAL_BASE_IDX 2
#define mmOTG1_OTG_V_TOTAL_MIN 0x1bb0
#define mmOTG1_OTG_V_TOTAL_MIN_BASE_IDX 2
#define mmOTG1_OTG_V_TOTAL_MAX 0x1bb1
#define mmOTG1_OTG_V_TOTAL_MAX_BASE_IDX 2
#define mmOTG1_OTG_V_TOTAL_MID 0x1bb2
#define mmOTG1_OTG_V_TOTAL_MID_BASE_IDX 2
#define mmOTG1_OTG_V_TOTAL_CONTROL 0x1bb3
#define mmOTG1_OTG_V_TOTAL_CONTROL_BASE_IDX 2
#define mmOTG1_OTG_V_TOTAL_INT_STATUS 0x1bb4
#define mmOTG1_OTG_V_TOTAL_INT_STATUS_BASE_IDX 2
#define mmOTG1_OTG_VSYNC_NOM_INT_STATUS 0x1bb5
#define mmOTG1_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX 2
#define mmOTG1_OTG_V_BLANK_START_END 0x1bb6
#define mmOTG1_OTG_V_BLANK_START_END_BASE_IDX 2
#define mmOTG1_OTG_V_SYNC_A 0x1bb7
#define mmOTG1_OTG_V_SYNC_A_BASE_IDX 2
#define mmOTG1_OTG_V_SYNC_A_CNTL 0x1bb8
#define mmOTG1_OTG_V_SYNC_A_CNTL_BASE_IDX 2
#define mmOTG1_OTG_TRIGA_CNTL 0x1bb9
#define mmOTG1_OTG_TRIGA_CNTL_BASE_IDX 2
#define mmOTG1_OTG_TRIGA_MANUAL_TRIG 0x1bba
#define mmOTG1_OTG_TRIGA_MANUAL_TRIG_BASE_IDX 2
#define mmOTG1_OTG_TRIGB_CNTL 0x1bbb
#define mmOTG1_OTG_TRIGB_CNTL_BASE_IDX 2
#define mmOTG1_OTG_TRIGB_MANUAL_TRIG 0x1bbc
#define mmOTG1_OTG_TRIGB_MANUAL_TRIG_BASE_IDX 2
#define mmOTG1_OTG_FORCE_COUNT_NOW_CNTL 0x1bbd
#define mmOTG1_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX 2
#define mmOTG1_OTG_STEREO_FORCE_NEXT_EYE 0x1bbf
#define mmOTG1_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX 2
#define mmOTG1_OTG_CONTROL 0x1bc1
#define mmOTG1_OTG_CONTROL_BASE_IDX 2
#define mmOTG1_OTG_BLANK_CONTROL 0x1bc2
#define mmOTG1_OTG_BLANK_CONTROL_BASE_IDX 2
#define mmOTG1_OTG_INTERLACE_CONTROL 0x1bc4
#define mmOTG1_OTG_INTERLACE_CONTROL_BASE_IDX 2
#define mmOTG1_OTG_INTERLACE_STATUS 0x1bc5
#define mmOTG1_OTG_INTERLACE_STATUS_BASE_IDX 2
#define mmOTG1_OTG_PIXEL_DATA_READBACK0 0x1bc7
#define mmOTG1_OTG_PIXEL_DATA_READBACK0_BASE_IDX 2
#define mmOTG1_OTG_PIXEL_DATA_READBACK1 0x1bc8
#define mmOTG1_OTG_PIXEL_DATA_READBACK1_BASE_IDX 2
#define mmOTG1_OTG_STATUS 0x1bc9
#define mmOTG1_OTG_STATUS_BASE_IDX 2
#define mmOTG1_OTG_STATUS_POSITION 0x1bca
#define mmOTG1_OTG_STATUS_POSITION_BASE_IDX 2
#define mmOTG1_OTG_NOM_VERT_POSITION 0x1bcb
#define mmOTG1_OTG_NOM_VERT_POSITION_BASE_IDX 2
#define mmOTG1_OTG_STATUS_FRAME_COUNT 0x1bcc
#define mmOTG1_OTG_STATUS_FRAME_COUNT_BASE_IDX 2
#define mmOTG1_OTG_STATUS_VF_COUNT 0x1bcd
#define mmOTG1_OTG_STATUS_VF_COUNT_BASE_IDX 2
#define mmOTG1_OTG_STATUS_HV_COUNT 0x1bce
#define mmOTG1_OTG_STATUS_HV_COUNT_BASE_IDX 2
#define mmOTG1_OTG_COUNT_CONTROL 0x1bcf
#define mmOTG1_OTG_COUNT_CONTROL_BASE_IDX 2
#define mmOTG1_OTG_COUNT_RESET 0x1bd0
#define mmOTG1_OTG_COUNT_RESET_BASE_IDX 2
#define mmOTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1bd1
#define mmOTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2
#define mmOTG1_OTG_VERT_SYNC_CONTROL 0x1bd2
#define mmOTG1_OTG_VERT_SYNC_CONTROL_BASE_IDX 2
#define mmOTG1_OTG_STEREO_STATUS 0x1bd3
#define mmOTG1_OTG_STEREO_STATUS_BASE_IDX 2
#define mmOTG1_OTG_STEREO_CONTROL 0x1bd4
#define mmOTG1_OTG_STEREO_CONTROL_BASE_IDX 2
#define mmOTG1_OTG_SNAPSHOT_STATUS 0x1bd5
#define mmOTG1_OTG_SNAPSHOT_STATUS_BASE_IDX 2
#define mmOTG1_OTG_SNAPSHOT_CONTROL 0x1bd6
#define mmOTG1_OTG_SNAPSHOT_CONTROL_BASE_IDX 2
#define mmOTG1_OTG_SNAPSHOT_POSITION 0x1bd7
#define mmOTG1_OTG_SNAPSHOT_POSITION_BASE_IDX 2
#define mmOTG1_OTG_SNAPSHOT_FRAME 0x1bd8
#define mmOTG1_OTG_SNAPSHOT_FRAME_BASE_IDX 2
#define mmOTG1_OTG_INTERRUPT_CONTROL 0x1bd9
#define mmOTG1_OTG_INTERRUPT_CONTROL_BASE_IDX 2
#define mmOTG1_OTG_UPDATE_LOCK 0x1bda
#define mmOTG1_OTG_UPDATE_LOCK_BASE_IDX 2
#define mmOTG1_OTG_DOUBLE_BUFFER_CONTROL 0x1bdb
#define mmOTG1_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX 2
#define mmOTG1_OTG_MASTER_EN 0x1bdc
#define mmOTG1_OTG_MASTER_EN_BASE_IDX 2
#define mmOTG1_OTG_BLANK_DATA_COLOR 0x1bde
#define mmOTG1_OTG_BLANK_DATA_COLOR_BASE_IDX 2
#define mmOTG1_OTG_BLANK_DATA_COLOR_EXT 0x1bdf
#define mmOTG1_OTG_BLANK_DATA_COLOR_EXT_BASE_IDX 2
#define mmOTG1_OTG_BLACK_COLOR 0x1be0
#define mmOTG1_OTG_BLACK_COLOR_BASE_IDX 2
#define mmOTG1_OTG_BLACK_COLOR_EXT 0x1be1
#define mmOTG1_OTG_BLACK_COLOR_EXT_BASE_IDX 2
#define mmOTG1_OTG_VERTICAL_INTERRUPT0_POSITION 0x1be2
#define mmOTG1_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2
#define mmOTG1_OTG_VERTICAL_INTERRUPT0_CONTROL 0x1be3
#define mmOTG1_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2
#define mmOTG1_OTG_VERTICAL_INTERRUPT1_POSITION 0x1be4
#define mmOTG1_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2
#define mmOTG1_OTG_VERTICAL_INTERRUPT1_CONTROL 0x1be5
#define mmOTG1_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2
#define mmOTG1_OTG_VERTICAL_INTERRUPT2_POSITION 0x1be6
#define mmOTG1_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2
#define mmOTG1_OTG_VERTICAL_INTERRUPT2_CONTROL 0x1be7
#define mmOTG1_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2
#define mmOTG1_OTG_CRC_CNTL 0x1be8
#define mmOTG1_OTG_CRC_CNTL_BASE_IDX 2
#define mmOTG1_OTG_CRC_CNTL2 0x1be9
#define mmOTG1_OTG_CRC_CNTL2_BASE_IDX 2
#define mmOTG1_OTG_CRC0_WINDOWA_X_CONTROL 0x1bea
#define mmOTG1_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2
#define mmOTG1_OTG_CRC0_WINDOWA_Y_CONTROL 0x1beb
#define mmOTG1_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2
#define mmOTG1_OTG_CRC0_WINDOWB_X_CONTROL 0x1bec
#define mmOTG1_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2
#define mmOTG1_OTG_CRC0_WINDOWB_Y_CONTROL 0x1bed
#define mmOTG1_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2
#define mmOTG1_OTG_CRC0_DATA_RG 0x1bee
#define mmOTG1_OTG_CRC0_DATA_RG_BASE_IDX 2
#define mmOTG1_OTG_CRC0_DATA_B 0x1bef
#define mmOTG1_OTG_CRC0_DATA_B_BASE_IDX 2
#define mmOTG1_OTG_CRC1_WINDOWA_X_CONTROL 0x1bf0
#define mmOTG1_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2
#define mmOTG1_OTG_CRC1_WINDOWA_Y_CONTROL 0x1bf1
#define mmOTG1_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2
#define mmOTG1_OTG_CRC1_WINDOWB_X_CONTROL 0x1bf2
#define mmOTG1_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2
#define mmOTG1_OTG_CRC1_WINDOWB_Y_CONTROL 0x1bf3
#define mmOTG1_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2
#define mmOTG1_OTG_CRC1_DATA_RG 0x1bf4
#define mmOTG1_OTG_CRC1_DATA_RG_BASE_IDX 2
#define mmOTG1_OTG_CRC1_DATA_B 0x1bf5
#define mmOTG1_OTG_CRC1_DATA_B_BASE_IDX 2
#define mmOTG1_OTG_CRC_SIG_RED_GREEN_MASK 0x1bfa
#define mmOTG1_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2
#define mmOTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK 0x1bfb
#define mmOTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2
#define mmOTG1_OTG_STATIC_SCREEN_CONTROL 0x1c02
#define mmOTG1_OTG_STATIC_SCREEN_CONTROL_BASE_IDX 2
#define mmOTG1_OTG_3D_STRUCTURE_CONTROL 0x1c03
#define mmOTG1_OTG_3D_STRUCTURE_CONTROL_BASE_IDX 2
#define mmOTG1_OTG_GSL_VSYNC_GAP 0x1c04
#define mmOTG1_OTG_GSL_VSYNC_GAP_BASE_IDX 2
#define mmOTG1_OTG_MASTER_UPDATE_MODE 0x1c05
#define mmOTG1_OTG_MASTER_UPDATE_MODE_BASE_IDX 2
#define mmOTG1_OTG_CLOCK_CONTROL 0x1c06
#define mmOTG1_OTG_CLOCK_CONTROL_BASE_IDX 2
#define mmOTG1_OTG_VSTARTUP_PARAM 0x1c07
#define mmOTG1_OTG_VSTARTUP_PARAM_BASE_IDX 2
#define mmOTG1_OTG_VUPDATE_PARAM 0x1c08
#define mmOTG1_OTG_VUPDATE_PARAM_BASE_IDX 2
#define mmOTG1_OTG_VREADY_PARAM 0x1c09
#define mmOTG1_OTG_VREADY_PARAM_BASE_IDX 2
#define mmOTG1_OTG_GLOBAL_SYNC_STATUS 0x1c0a
#define mmOTG1_OTG_GLOBAL_SYNC_STATUS_BASE_IDX 2
#define mmOTG1_OTG_MASTER_UPDATE_LOCK 0x1c0b
#define mmOTG1_OTG_MASTER_UPDATE_LOCK_BASE_IDX 2
#define mmOTG1_OTG_GSL_CONTROL 0x1c0c
#define mmOTG1_OTG_GSL_CONTROL_BASE_IDX 2
#define mmOTG1_OTG_GSL_WINDOW_X 0x1c0d
#define mmOTG1_OTG_GSL_WINDOW_X_BASE_IDX 2
#define mmOTG1_OTG_GSL_WINDOW_Y 0x1c0e
#define mmOTG1_OTG_GSL_WINDOW_Y_BASE_IDX 2
#define mmOTG1_OTG_VUPDATE_KEEPOUT 0x1c0f
#define mmOTG1_OTG_VUPDATE_KEEPOUT_BASE_IDX 2
#define mmOTG1_OTG_GLOBAL_CONTROL0 0x1c10
#define mmOTG1_OTG_GLOBAL_CONTROL0_BASE_IDX 2
#define mmOTG1_OTG_GLOBAL_CONTROL1 0x1c11
#define mmOTG1_OTG_GLOBAL_CONTROL1_BASE_IDX 2
#define mmOTG1_OTG_GLOBAL_CONTROL2 0x1c12
#define mmOTG1_OTG_GLOBAL_CONTROL2_BASE_IDX 2
#define mmOTG1_OTG_GLOBAL_CONTROL3 0x1c13
#define mmOTG1_OTG_GLOBAL_CONTROL3_BASE_IDX 2
#define mmOTG1_OTG_TRIG_MANUAL_CONTROL 0x1c14
#define mmOTG1_OTG_TRIG_MANUAL_CONTROL_BASE_IDX 2
#define mmOTG1_OTG_DRR_CONTROL 0x1c17
#define mmOTG1_OTG_DRR_CONTROL_BASE_IDX 2
#define mmOTG1_OTG_DSC_START_POSITION 0x1c19
#define mmOTG1_OTG_DSC_START_POSITION_BASE_IDX 2
// addressBlock: dce_dc_optc_optc_misc_dispdec
// base address: 0x0
#define mmDWB_SOURCE_SELECT 0x1e2a
#define mmDWB_SOURCE_SELECT_BASE_IDX 2
#define mmGSL_SOURCE_SELECT 0x1e2b
#define mmGSL_SOURCE_SELECT_BASE_IDX 2
#define mmOPTC_CLOCK_CONTROL 0x1e2c
#define mmOPTC_CLOCK_CONTROL_BASE_IDX 2
// addressBlock: dce_dc_dio_dout_i2c_dispdec
// base address: 0x0
#define mmDC_I2C_CONTROL 0x1e98
#define mmDC_I2C_CONTROL_BASE_IDX 2
#define mmDC_I2C_ARBITRATION 0x1e99
#define mmDC_I2C_ARBITRATION_BASE_IDX 2
#define mmDC_I2C_INTERRUPT_CONTROL 0x1e9a
#define mmDC_I2C_INTERRUPT_CONTROL_BASE_IDX 2
#define mmDC_I2C_SW_STATUS 0x1e9b
#define mmDC_I2C_SW_STATUS_BASE_IDX 2
#define mmDC_I2C_DDC1_HW_STATUS 0x1e9c
#define mmDC_I2C_DDC1_HW_STATUS_BASE_IDX 2
#define mmDC_I2C_DDC2_HW_STATUS 0x1e9d
#define mmDC_I2C_DDC2_HW_STATUS_BASE_IDX 2
#define mmDC_I2C_DDC1_SPEED 0x1ea2
#define mmDC_I2C_DDC1_SPEED_BASE_IDX 2
#define mmDC_I2C_DDC1_SETUP 0x1ea3
#define mmDC_I2C_DDC1_SETUP_BASE_IDX 2
#define mmDC_I2C_DDC2_SPEED 0x1ea4
#define mmDC_I2C_DDC2_SPEED_BASE_IDX 2
#define mmDC_I2C_DDC2_SETUP 0x1ea5
#define mmDC_I2C_DDC2_SETUP_BASE_IDX 2
#define mmDC_I2C_TRANSACTION0 0x1eae
#define mmDC_I2C_TRANSACTION0_BASE_IDX 2
#define mmDC_I2C_TRANSACTION1 0x1eaf
#define mmDC_I2C_TRANSACTION1_BASE_IDX 2
#define mmDC_I2C_TRANSACTION2 0x1eb0
#define mmDC_I2C_TRANSACTION2_BASE_IDX 2
#define mmDC_I2C_TRANSACTION3 0x1eb1
#define mmDC_I2C_TRANSACTION3_BASE_IDX 2
#define mmDC_I2C_DATA 0x1eb2
#define mmDC_I2C_DATA_BASE_IDX 2
#define mmDC_I2C_EDID_DETECT_CTRL 0x1eb6
#define mmDC_I2C_EDID_DETECT_CTRL_BASE_IDX 2
#define mmDC_I2C_READ_REQUEST_INTERRUPT 0x1eb7
#define mmDC_I2C_READ_REQUEST_INTERRUPT_BASE_IDX 2
// addressBlock: dce_dc_dio_dio_misc_dispdec
// base address: 0x0
#define mmDIO_SCRATCH0 0x1eca
#define mmDIO_SCRATCH0_BASE_IDX 2
#define mmDIO_SCRATCH1 0x1ecb
#define mmDIO_SCRATCH1_BASE_IDX 2
#define mmDIO_SCRATCH2 0x1ecc
#define mmDIO_SCRATCH2_BASE_IDX 2
#define mmDIO_SCRATCH3 0x1ecd
#define mmDIO_SCRATCH3_BASE_IDX 2
#define mmDIO_SCRATCH4 0x1ece
#define mmDIO_SCRATCH4_BASE_IDX 2
#define mmDIO_SCRATCH5 0x1ecf
#define mmDIO_SCRATCH5_BASE_IDX 2
#define mmDIO_SCRATCH6 0x1ed0
#define mmDIO_SCRATCH6_BASE_IDX 2
#define mmDIO_SCRATCH7 0x1ed1
#define mmDIO_SCRATCH7_BASE_IDX 2
#define mmDIO_MEM_PWR_STATUS 0x1edd
#define mmDIO_MEM_PWR_STATUS_BASE_IDX 2
#define mmDIO_MEM_PWR_CTRL 0x1ede
#define mmDIO_MEM_PWR_CTRL_BASE_IDX 2
#define mmDIO_MEM_PWR_CTRL2 0x1edf
#define mmDIO_MEM_PWR_CTRL2_BASE_IDX 2
#define mmDIO_CLK_CNTL 0x1ee0
#define mmDIO_CLK_CNTL_BASE_IDX 2
#define mmDIO_MEM_PWR_CTRL3 0x1ee1
#define mmDIO_MEM_PWR_CTRL3_BASE_IDX 2
#define mmDIO_POWER_MANAGEMENT_CNTL 0x1ee4
#define mmDIO_POWER_MANAGEMENT_CNTL_BASE_IDX 2
#define mmDIG_SOFT_RESET 0x1eee
#define mmDIG_SOFT_RESET_BASE_IDX 2
#define mmDIO_MEM_PWR_STATUS1 0x1ef0
#define mmDIO_MEM_PWR_STATUS1_BASE_IDX 2
#define mmDIO_CLK_CNTL2 0x1ef2
#define mmDIO_CLK_CNTL2_BASE_IDX 2
#define mmDIO_CLK_CNTL3 0x1ef3
#define mmDIO_CLK_CNTL3_BASE_IDX 2
#define mmDIO_HDMI_RXSTATUS_TIMER_CONTROL 0x1eff
#define mmDIO_HDMI_RXSTATUS_TIMER_CONTROL_BASE_IDX 2
#define mmDIO_GENERIC_INTERRUPT_MESSAGE 0x1f02
#define mmDIO_GENERIC_INTERRUPT_MESSAGE_BASE_IDX 2
#define mmDIO_GENERIC_INTERRUPT_CLEAR 0x1f03
#define mmDIO_GENERIC_INTERRUPT_CLEAR_BASE_IDX 2
// addressBlock: dce_dc_dio_hpd0_dispdec
// base address: 0x0
#define mmHPD0_DC_HPD_INT_STATUS 0x1f14
#define mmHPD0_DC_HPD_INT_STATUS_BASE_IDX 2
#define mmHPD0_DC_HPD_INT_CONTROL 0x1f15
#define mmHPD0_DC_HPD_INT_CONTROL_BASE_IDX 2
#define mmHPD0_DC_HPD_CONTROL 0x1f16
#define mmHPD0_DC_HPD_CONTROL_BASE_IDX 2
#define mmHPD0_DC_HPD_FAST_TRAIN_CNTL 0x1f17
#define mmHPD0_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2
#define mmHPD0_DC_HPD_TOGGLE_FILT_CNTL 0x1f18
#define mmHPD0_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2
// addressBlock: dce_dc_dio_hpd1_dispdec
// base address: 0x20
#define mmHPD1_DC_HPD_INT_STATUS 0x1f1c
#define mmHPD1_DC_HPD_INT_STATUS_BASE_IDX 2
#define mmHPD1_DC_HPD_INT_CONTROL 0x1f1d
#define mmHPD1_DC_HPD_INT_CONTROL_BASE_IDX 2
#define mmHPD1_DC_HPD_CONTROL 0x1f1e
#define mmHPD1_DC_HPD_CONTROL_BASE_IDX 2
#define mmHPD1_DC_HPD_FAST_TRAIN_CNTL 0x1f1f
#define mmHPD1_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2
#define mmHPD1_DC_HPD_TOGGLE_FILT_CNTL 0x1f20
#define mmHPD1_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2
// addressBlock: dce_dc_dio_dp_aux0_dispdec
// base address: 0x0
#define mmDP_AUX0_AUX_CONTROL 0x1f50
#define mmDP_AUX0_AUX_CONTROL_BASE_IDX 2
#define mmDP_AUX0_AUX_SW_CONTROL 0x1f51
#define mmDP_AUX0_AUX_SW_CONTROL_BASE_IDX 2
#define mmDP_AUX0_AUX_ARB_CONTROL 0x1f52
#define mmDP_AUX0_AUX_ARB_CONTROL_BASE_IDX 2
#define mmDP_AUX0_AUX_INTERRUPT_CONTROL 0x1f53
#define mmDP_AUX0_AUX_INTERRUPT_CONTROL_BASE_IDX 2
#define mmDP_AUX0_AUX_SW_STATUS 0x1f54
#define mmDP_AUX0_AUX_SW_STATUS_BASE_IDX 2
#define mmDP_AUX0_AUX_LS_STATUS 0x1f55
#define mmDP_AUX0_AUX_LS_STATUS_BASE_IDX 2
#define mmDP_AUX0_AUX_SW_DATA 0x1f56
#define mmDP_AUX0_AUX_SW_DATA_BASE_IDX 2
#define mmDP_AUX0_AUX_LS_DATA 0x1f57
#define mmDP_AUX0_AUX_LS_DATA_BASE_IDX 2
#define mmDP_AUX0_AUX_DPHY_TX_REF_CONTROL 0x1f58
#define mmDP_AUX0_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2
#define mmDP_AUX0_AUX_DPHY_TX_CONTROL 0x1f59
#define mmDP_AUX0_AUX_DPHY_TX_CONTROL_BASE_IDX 2
#define mmDP_AUX0_AUX_DPHY_RX_CONTROL0 0x1f5a
#define mmDP_AUX0_AUX_DPHY_RX_CONTROL0_BASE_IDX 2
#define mmDP_AUX0_AUX_DPHY_RX_CONTROL1 0x1f5b
#define mmDP_AUX0_AUX_DPHY_RX_CONTROL1_BASE_IDX 2
#define mmDP_AUX0_AUX_DPHY_TX_STATUS 0x1f5c
#define mmDP_AUX0_AUX_DPHY_TX_STATUS_BASE_IDX 2
#define mmDP_AUX0_AUX_DPHY_RX_STATUS 0x1f5d
#define mmDP_AUX0_AUX_DPHY_RX_STATUS_BASE_IDX 2
// addressBlock: dce_dc_dio_dp_aux1_dispdec
// base address: 0x70
#define mmDP_AUX1_AUX_CONTROL 0x1f6c
#define mmDP_AUX1_AUX_CONTROL_BASE_IDX 2
#define mmDP_AUX1_AUX_SW_CONTROL 0x1f6d
#define mmDP_AUX1_AUX_SW_CONTROL_BASE_IDX 2
#define mmDP_AUX1_AUX_ARB_CONTROL 0x1f6e
#define mmDP_AUX1_AUX_ARB_CONTROL_BASE_IDX 2
#define mmDP_AUX1_AUX_INTERRUPT_CONTROL 0x1f6f
#define mmDP_AUX1_AUX_INTERRUPT_CONTROL_BASE_IDX 2
#define mmDP_AUX1_AUX_SW_STATUS 0x1f70
#define mmDP_AUX1_AUX_SW_STATUS_BASE_IDX 2
#define mmDP_AUX1_AUX_LS_STATUS 0x1f71
#define mmDP_AUX1_AUX_LS_STATUS_BASE_IDX 2
#define mmDP_AUX1_AUX_SW_DATA 0x1f72
#define mmDP_AUX1_AUX_SW_DATA_BASE_IDX 2
#define mmDP_AUX1_AUX_LS_DATA 0x1f73
#define mmDP_AUX1_AUX_LS_DATA_BASE_IDX 2
#define mmDP_AUX1_AUX_DPHY_TX_REF_CONTROL 0x1f74
#define mmDP_AUX1_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2
#define mmDP_AUX1_AUX_DPHY_TX_CONTROL 0x1f75
#define mmDP_AUX1_AUX_DPHY_TX_CONTROL_BASE_IDX 2
#define mmDP_AUX1_AUX_DPHY_RX_CONTROL0 0x1f76
#define mmDP_AUX1_AUX_DPHY_RX_CONTROL0_BASE_IDX 2
#define mmDP_AUX1_AUX_DPHY_RX_CONTROL1 0x1f77
#define mmDP_AUX1_AUX_DPHY_RX_CONTROL1_BASE_IDX 2
#define mmDP_AUX1_AUX_DPHY_TX_STATUS 0x1f78
#define mmDP_AUX1_AUX_DPHY_TX_STATUS_BASE_IDX 2
#define mmDP_AUX1_AUX_DPHY_RX_STATUS 0x1f79
#define mmDP_AUX1_AUX_DPHY_RX_STATUS_BASE_IDX 2
// addressBlock: dce_dc_dio_dig0_dispdec
// base address: 0x0
#define mmDIG0_DIG_FE_CNTL 0x2068
#define mmDIG0_DIG_FE_CNTL_BASE_IDX 2
#define mmDIG0_DIG_OUTPUT_CRC_CNTL 0x2069
#define mmDIG0_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2
#define mmDIG0_DIG_OUTPUT_CRC_RESULT 0x206a
#define mmDIG0_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2
#define mmDIG0_DIG_CLOCK_PATTERN 0x206b
#define mmDIG0_DIG_CLOCK_PATTERN_BASE_IDX 2
#define mmDIG0_DIG_TEST_PATTERN 0x206c
#define mmDIG0_DIG_TEST_PATTERN_BASE_IDX 2
#define mmDIG0_DIG_RANDOM_PATTERN_SEED 0x206d
#define mmDIG0_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2
#define mmDIG0_DIG_FIFO_STATUS 0x206e
#define mmDIG0_DIG_FIFO_STATUS_BASE_IDX 2
#define mmDIG0_HDMI_METADATA_PACKET_CONTROL 0x206f
#define mmDIG0_HDMI_METADATA_PACKET_CONTROL_BASE_IDX 2
#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL4 0x2070
#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX 2
#define mmDIG0_HDMI_CONTROL 0x2071
#define mmDIG0_HDMI_CONTROL_BASE_IDX 2
#define mmDIG0_HDMI_STATUS 0x2072
#define mmDIG0_HDMI_STATUS_BASE_IDX 2
#define mmDIG0_HDMI_AUDIO_PACKET_CONTROL 0x2073
#define mmDIG0_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2
#define mmDIG0_HDMI_ACR_PACKET_CONTROL 0x2074
#define mmDIG0_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2
#define mmDIG0_HDMI_VBI_PACKET_CONTROL 0x2075
#define mmDIG0_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2
#define mmDIG0_HDMI_INFOFRAME_CONTROL0 0x2076
#define mmDIG0_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2
#define mmDIG0_HDMI_INFOFRAME_CONTROL1 0x2077
#define mmDIG0_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2
#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL0 0x2078
#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2
#define mmDIG0_AFMT_INTERRUPT_STATUS 0x2079
#define mmDIG0_AFMT_INTERRUPT_STATUS_BASE_IDX 2
#define mmDIG0_HDMI_GC 0x207b
#define mmDIG0_HDMI_GC_BASE_IDX 2
#define mmDIG0_AFMT_AUDIO_PACKET_CONTROL2 0x207c
#define mmDIG0_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2
#define mmDIG0_AFMT_ISRC1_0 0x207d
#define mmDIG0_AFMT_ISRC1_0_BASE_IDX 2
#define mmDIG0_AFMT_ISRC1_1 0x207e
#define mmDIG0_AFMT_ISRC1_1_BASE_IDX 2
#define mmDIG0_AFMT_ISRC1_2 0x207f
#define mmDIG0_AFMT_ISRC1_2_BASE_IDX 2
#define mmDIG0_AFMT_ISRC1_3 0x2080
#define mmDIG0_AFMT_ISRC1_3_BASE_IDX 2
#define mmDIG0_AFMT_ISRC1_4 0x2081
#define mmDIG0_AFMT_ISRC1_4_BASE_IDX 2
#define mmDIG0_AFMT_ISRC2_0 0x2082
#define mmDIG0_AFMT_ISRC2_0_BASE_IDX 2
#define mmDIG0_AFMT_ISRC2_1 0x2083
#define mmDIG0_AFMT_ISRC2_1_BASE_IDX 2
#define mmDIG0_AFMT_ISRC2_2 0x2084
#define mmDIG0_AFMT_ISRC2_2_BASE_IDX 2
#define mmDIG0_AFMT_ISRC2_3 0x2085
#define mmDIG0_AFMT_ISRC2_3_BASE_IDX 2
#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL2 0x2086
#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2
#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL3 0x2087
#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2
#define mmDIG0_HDMI_DB_CONTROL 0x2088
#define mmDIG0_HDMI_DB_CONTROL_BASE_IDX 2
#define mmDIG0_DME_CONTROL 0x2089
#define mmDIG0_DME_CONTROL_BASE_IDX 2
#define mmDIG0_AFMT_MPEG_INFO0 0x208a
#define mmDIG0_AFMT_MPEG_INFO0_BASE_IDX 2
#define mmDIG0_AFMT_MPEG_INFO1 0x208b
#define mmDIG0_AFMT_MPEG_INFO1_BASE_IDX 2
#define mmDIG0_AFMT_GENERIC_HDR 0x208c
#define mmDIG0_AFMT_GENERIC_HDR_BASE_IDX 2
#define mmDIG0_AFMT_GENERIC_0 0x208d
#define mmDIG0_AFMT_GENERIC_0_BASE_IDX 2
#define mmDIG0_AFMT_GENERIC_1 0x208e
#define mmDIG0_AFMT_GENERIC_1_BASE_IDX 2
#define mmDIG0_AFMT_GENERIC_2 0x208f
#define mmDIG0_AFMT_GENERIC_2_BASE_IDX 2
#define mmDIG0_AFMT_GENERIC_3 0x2090
#define mmDIG0_AFMT_GENERIC_3_BASE_IDX 2
#define mmDIG0_AFMT_GENERIC_4 0x2091
#define mmDIG0_AFMT_GENERIC_4_BASE_IDX 2
#define mmDIG0_AFMT_GENERIC_5 0x2092
#define mmDIG0_AFMT_GENERIC_5_BASE_IDX 2
#define mmDIG0_AFMT_GENERIC_6 0x2093
#define mmDIG0_AFMT_GENERIC_6_BASE_IDX 2
#define mmDIG0_AFMT_GENERIC_7 0x2094
#define mmDIG0_AFMT_GENERIC_7_BASE_IDX 2
#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL1 0x2095
#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2
#define mmDIG0_HDMI_ACR_32_0 0x2096
#define mmDIG0_HDMI_ACR_32_0_BASE_IDX 2
#define mmDIG0_HDMI_ACR_32_1 0x2097
#define mmDIG0_HDMI_ACR_32_1_BASE_IDX 2
#define mmDIG0_HDMI_ACR_44_0 0x2098
#define mmDIG0_HDMI_ACR_44_0_BASE_IDX 2
#define mmDIG0_HDMI_ACR_44_1 0x2099
#define mmDIG0_HDMI_ACR_44_1_BASE_IDX 2
#define mmDIG0_HDMI_ACR_48_0 0x209a
#define mmDIG0_HDMI_ACR_48_0_BASE_IDX 2
#define mmDIG0_HDMI_ACR_48_1 0x209b
#define mmDIG0_HDMI_ACR_48_1_BASE_IDX 2
#define mmDIG0_HDMI_ACR_STATUS_0 0x209c
#define mmDIG0_HDMI_ACR_STATUS_0_BASE_IDX 2
#define mmDIG0_HDMI_ACR_STATUS_1 0x209d
#define mmDIG0_HDMI_ACR_STATUS_1_BASE_IDX 2
#define mmDIG0_AFMT_AUDIO_INFO0 0x209e
#define mmDIG0_AFMT_AUDIO_INFO0_BASE_IDX 2
#define mmDIG0_AFMT_AUDIO_INFO1 0x209f
#define mmDIG0_AFMT_AUDIO_INFO1_BASE_IDX 2
#define mmDIG0_AFMT_60958_0 0x20a0
#define mmDIG0_AFMT_60958_0_BASE_IDX 2
#define mmDIG0_AFMT_60958_1 0x20a1
#define mmDIG0_AFMT_60958_1_BASE_IDX 2
#define mmDIG0_AFMT_AUDIO_CRC_CONTROL 0x20a2
#define mmDIG0_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2
#define mmDIG0_AFMT_RAMP_CONTROL0 0x20a3
#define mmDIG0_AFMT_RAMP_CONTROL0_BASE_IDX 2
#define mmDIG0_AFMT_RAMP_CONTROL1 0x20a4
#define mmDIG0_AFMT_RAMP_CONTROL1_BASE_IDX 2
#define mmDIG0_AFMT_RAMP_CONTROL2 0x20a5
#define mmDIG0_AFMT_RAMP_CONTROL2_BASE_IDX 2
#define mmDIG0_AFMT_RAMP_CONTROL3 0x20a6
#define mmDIG0_AFMT_RAMP_CONTROL3_BASE_IDX 2
#define mmDIG0_AFMT_60958_2 0x20a7
#define mmDIG0_AFMT_60958_2_BASE_IDX 2
#define mmDIG0_AFMT_AUDIO_CRC_RESULT 0x20a8
#define mmDIG0_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2
#define mmDIG0_AFMT_STATUS 0x20a9
#define mmDIG0_AFMT_STATUS_BASE_IDX 2
#define mmDIG0_AFMT_AUDIO_PACKET_CONTROL 0x20aa
#define mmDIG0_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2
#define mmDIG0_AFMT_VBI_PACKET_CONTROL 0x20ab
#define mmDIG0_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2
#define mmDIG0_AFMT_INFOFRAME_CONTROL0 0x20ac
#define mmDIG0_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2
#define mmDIG0_AFMT_AUDIO_SRC_CONTROL 0x20ad
#define mmDIG0_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2
#define mmDIG0_DIG_BE_CNTL 0x20af
#define mmDIG0_DIG_BE_CNTL_BASE_IDX 2
#define mmDIG0_DIG_BE_EN_CNTL 0x20b0
#define mmDIG0_DIG_BE_EN_CNTL_BASE_IDX 2
#define mmDIG0_TMDS_CNTL 0x20d3
#define mmDIG0_TMDS_CNTL_BASE_IDX 2
#define mmDIG0_TMDS_CONTROL_CHAR 0x20d4
#define mmDIG0_TMDS_CONTROL_CHAR_BASE_IDX 2
#define mmDIG0_TMDS_CONTROL0_FEEDBACK 0x20d5
#define mmDIG0_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2
#define mmDIG0_TMDS_STEREOSYNC_CTL_SEL 0x20d6
#define mmDIG0_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2
#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_0_1 0x20d7
#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2
#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_2_3 0x20d8
#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2
#define mmDIG0_TMDS_CTL_BITS 0x20da
#define mmDIG0_TMDS_CTL_BITS_BASE_IDX 2
#define mmDIG0_TMDS_DCBALANCER_CONTROL 0x20db
#define mmDIG0_TMDS_DCBALANCER_CONTROL_BASE_IDX 2
#define mmDIG0_TMDS_SYNC_DCBALANCE_CHAR 0x20dc
#define mmDIG0_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX 2
#define mmDIG0_TMDS_CTL0_1_GEN_CNTL 0x20dd
#define mmDIG0_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2
#define mmDIG0_TMDS_CTL2_3_GEN_CNTL 0x20de
#define mmDIG0_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2
#define mmDIG0_DIG_VERSION 0x20e0
#define mmDIG0_DIG_VERSION_BASE_IDX 2
#define mmDIG0_DIG_LANE_ENABLE 0x20e1
#define mmDIG0_DIG_LANE_ENABLE_BASE_IDX 2
#define mmDIG0_AFMT_CNTL 0x20e6
#define mmDIG0_AFMT_CNTL_BASE_IDX 2
#define mmDIG0_AFMT_VBI_PACKET_CONTROL1 0x20e7
#define mmDIG0_AFMT_VBI_PACKET_CONTROL1_BASE_IDX 2
#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL5 0x20f6
#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX 2
// addressBlock: dce_dc_dio_dp0_dispdec
// base address: 0x0
#define mmDP0_DP_LINK_CNTL 0x2108
#define mmDP0_DP_LINK_CNTL_BASE_IDX 2
#define mmDP0_DP_PIXEL_FORMAT 0x2109
#define mmDP0_DP_PIXEL_FORMAT_BASE_IDX 2
#define mmDP0_DP_MSA_COLORIMETRY 0x210a
#define mmDP0_DP_MSA_COLORIMETRY_BASE_IDX 2
#define mmDP0_DP_CONFIG 0x210b
#define mmDP0_DP_CONFIG_BASE_IDX 2
#define mmDP0_DP_VID_STREAM_CNTL 0x210c
#define mmDP0_DP_VID_STREAM_CNTL_BASE_IDX 2
#define mmDP0_DP_STEER_FIFO 0x210d
#define mmDP0_DP_STEER_FIFO_BASE_IDX 2
#define mmDP0_DP_MSA_MISC 0x210e
#define mmDP0_DP_MSA_MISC_BASE_IDX 2
#define mmDP0_DP_VID_TIMING 0x2110
#define mmDP0_DP_VID_TIMING_BASE_IDX 2
#define mmDP0_DP_VID_N 0x2111
#define mmDP0_DP_VID_N_BASE_IDX 2
#define mmDP0_DP_VID_M 0x2112
#define mmDP0_DP_VID_M_BASE_IDX 2
#define mmDP0_DP_LINK_FRAMING_CNTL 0x2113
#define mmDP0_DP_LINK_FRAMING_CNTL_BASE_IDX 2
#define mmDP0_DP_HBR2_EYE_PATTERN 0x2114
#define mmDP0_DP_HBR2_EYE_PATTERN_BASE_IDX 2
#define mmDP0_DP_VID_MSA_VBID 0x2115
#define mmDP0_DP_VID_MSA_VBID_BASE_IDX 2
#define mmDP0_DP_VID_INTERRUPT_CNTL 0x2116
#define mmDP0_DP_VID_INTERRUPT_CNTL_BASE_IDX 2
#define mmDP0_DP_DPHY_CNTL 0x2117
#define mmDP0_DP_DPHY_CNTL_BASE_IDX 2
#define mmDP0_DP_DPHY_TRAINING_PATTERN_SEL 0x2118
#define mmDP0_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2
#define mmDP0_DP_DPHY_SYM0 0x2119
#define mmDP0_DP_DPHY_SYM0_BASE_IDX 2
#define mmDP0_DP_DPHY_SYM1 0x211a
#define mmDP0_DP_DPHY_SYM1_BASE_IDX 2
#define mmDP0_DP_DPHY_SYM2 0x211b
#define mmDP0_DP_DPHY_SYM2_BASE_IDX 2
#define mmDP0_DP_DPHY_8B10B_CNTL 0x211c
#define mmDP0_DP_DPHY_8B10B_CNTL_BASE_IDX 2
#define mmDP0_DP_DPHY_PRBS_CNTL 0x211d
#define mmDP0_DP_DPHY_PRBS_CNTL_BASE_IDX 2
#define mmDP0_DP_DPHY_SCRAM_CNTL 0x211e
#define mmDP0_DP_DPHY_SCRAM_CNTL_BASE_IDX 2
#define mmDP0_DP_DPHY_CRC_EN 0x211f
#define mmDP0_DP_DPHY_CRC_EN_BASE_IDX 2
#define mmDP0_DP_DPHY_CRC_CNTL 0x2120
#define mmDP0_DP_DPHY_CRC_CNTL_BASE_IDX 2
#define mmDP0_DP_DPHY_CRC_RESULT 0x2121
#define mmDP0_DP_DPHY_CRC_RESULT_BASE_IDX 2
#define mmDP0_DP_DPHY_CRC_MST_CNTL 0x2122
#define mmDP0_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2
#define mmDP0_DP_DPHY_CRC_MST_STATUS 0x2123
#define mmDP0_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2
#define mmDP0_DP_DPHY_FAST_TRAINING 0x2124
#define mmDP0_DP_DPHY_FAST_TRAINING_BASE_IDX 2
#define mmDP0_DP_DPHY_FAST_TRAINING_STATUS 0x2125
#define mmDP0_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2
#define mmDP0_DP_SEC_CNTL 0x212b
#define mmDP0_DP_SEC_CNTL_BASE_IDX 2
#define mmDP0_DP_SEC_CNTL1 0x212c
#define mmDP0_DP_SEC_CNTL1_BASE_IDX 2
#define mmDP0_DP_SEC_FRAMING1 0x212d
#define mmDP0_DP_SEC_FRAMING1_BASE_IDX 2
#define mmDP0_DP_SEC_FRAMING2 0x212e
#define mmDP0_DP_SEC_FRAMING2_BASE_IDX 2
#define mmDP0_DP_SEC_FRAMING3 0x212f
#define mmDP0_DP_SEC_FRAMING3_BASE_IDX 2
#define mmDP0_DP_SEC_FRAMING4 0x2130
#define mmDP0_DP_SEC_FRAMING4_BASE_IDX 2
#define mmDP0_DP_SEC_AUD_N 0x2131
#define mmDP0_DP_SEC_AUD_N_BASE_IDX 2
#define mmDP0_DP_SEC_AUD_N_READBACK 0x2132
#define mmDP0_DP_SEC_AUD_N_READBACK_BASE_IDX 2
#define mmDP0_DP_SEC_AUD_M 0x2133
#define mmDP0_DP_SEC_AUD_M_BASE_IDX 2
#define mmDP0_DP_SEC_AUD_M_READBACK 0x2134
#define mmDP0_DP_SEC_AUD_M_READBACK_BASE_IDX 2
#define mmDP0_DP_SEC_TIMESTAMP 0x2135
#define mmDP0_DP_SEC_TIMESTAMP_BASE_IDX 2
#define mmDP0_DP_SEC_PACKET_CNTL 0x2136
#define mmDP0_DP_SEC_PACKET_CNTL_BASE_IDX 2
#define mmDP0_DP_MSE_RATE_CNTL 0x2137
#define mmDP0_DP_MSE_RATE_CNTL_BASE_IDX 2
#define mmDP0_DP_MSE_RATE_UPDATE 0x2139
#define mmDP0_DP_MSE_RATE_UPDATE_BASE_IDX 2
#define mmDP0_DP_MSE_SAT0 0x213a
#define mmDP0_DP_MSE_SAT0_BASE_IDX 2
#define mmDP0_DP_MSE_SAT1 0x213b
#define mmDP0_DP_MSE_SAT1_BASE_IDX 2
#define mmDP0_DP_MSE_SAT2 0x213c
#define mmDP0_DP_MSE_SAT2_BASE_IDX 2
#define mmDP0_DP_MSE_SAT_UPDATE 0x213d
#define mmDP0_DP_MSE_SAT_UPDATE_BASE_IDX 2
#define mmDP0_DP_MSE_LINK_TIMING 0x213e
#define mmDP0_DP_MSE_LINK_TIMING_BASE_IDX 2
#define mmDP0_DP_MSE_MISC_CNTL 0x213f
#define mmDP0_DP_MSE_MISC_CNTL_BASE_IDX 2
#define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL 0x2144
#define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2
#define mmDP0_DP_DPHY_HBR2_PATTERN_CONTROL 0x2145
#define mmDP0_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2
#define mmDP0_DP_MSE_SAT0_STATUS 0x2147
#define mmDP0_DP_MSE_SAT0_STATUS_BASE_IDX 2
#define mmDP0_DP_MSE_SAT1_STATUS 0x2148
#define mmDP0_DP_MSE_SAT1_STATUS_BASE_IDX 2
#define mmDP0_DP_MSE_SAT2_STATUS 0x2149
#define mmDP0_DP_MSE_SAT2_STATUS_BASE_IDX 2
#define mmDP0_DP_MSA_TIMING_PARAM1 0x214c
#define mmDP0_DP_MSA_TIMING_PARAM1_BASE_IDX 2
#define mmDP0_DP_MSA_TIMING_PARAM2 0x214d
#define mmDP0_DP_MSA_TIMING_PARAM2_BASE_IDX 2
#define mmDP0_DP_MSA_TIMING_PARAM3 0x214e
#define mmDP0_DP_MSA_TIMING_PARAM3_BASE_IDX 2
#define mmDP0_DP_MSA_TIMING_PARAM4 0x214f
#define mmDP0_DP_MSA_TIMING_PARAM4_BASE_IDX 2
#define mmDP0_DP_DSC_CNTL 0x2152
#define mmDP0_DP_DSC_CNTL_BASE_IDX 2
#define mmDP0_DP_SEC_CNTL2 0x2153
#define mmDP0_DP_SEC_CNTL2_BASE_IDX 2
#define mmDP0_DP_SEC_CNTL3 0x2154
#define mmDP0_DP_SEC_CNTL3_BASE_IDX 2
#define mmDP0_DP_SEC_CNTL4 0x2155
#define mmDP0_DP_SEC_CNTL4_BASE_IDX 2
#define mmDP0_DP_SEC_CNTL5 0x2156
#define mmDP0_DP_SEC_CNTL5_BASE_IDX 2
#define mmDP0_DP_SEC_CNTL6 0x2157
#define mmDP0_DP_SEC_CNTL6_BASE_IDX 2
#define mmDP0_DP_SEC_CNTL7 0x2158
#define mmDP0_DP_SEC_CNTL7_BASE_IDX 2
#define mmDP0_DP_DB_CNTL 0x2159
#define mmDP0_DP_DB_CNTL_BASE_IDX 2
#define mmDP0_DP_MSA_VBID_MISC 0x215a
#define mmDP0_DP_MSA_VBID_MISC_BASE_IDX 2
#define mmDP0_DP_SEC_METADATA_TRANSMISSION 0x215b
#define mmDP0_DP_SEC_METADATA_TRANSMISSION_BASE_IDX 2
#define mmDP0_DP_DSC_BYTES_PER_PIXEL 0x215c
#define mmDP0_DP_DSC_BYTES_PER_PIXEL_BASE_IDX 2
// addressBlock: dce_dc_dio_dig1_dispdec
// base address: 0x400
#define mmDIG1_DIG_FE_CNTL 0x2168
#define mmDIG1_DIG_FE_CNTL_BASE_IDX 2
#define mmDIG1_DIG_OUTPUT_CRC_CNTL 0x2169
#define mmDIG1_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2
#define mmDIG1_DIG_OUTPUT_CRC_RESULT 0x216a
#define mmDIG1_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2
#define mmDIG1_DIG_CLOCK_PATTERN 0x216b
#define mmDIG1_DIG_CLOCK_PATTERN_BASE_IDX 2
#define mmDIG1_DIG_TEST_PATTERN 0x216c
#define mmDIG1_DIG_TEST_PATTERN_BASE_IDX 2
#define mmDIG1_DIG_RANDOM_PATTERN_SEED 0x216d
#define mmDIG1_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2
#define mmDIG1_DIG_FIFO_STATUS 0x216e
#define mmDIG1_DIG_FIFO_STATUS_BASE_IDX 2
#define mmDIG1_HDMI_METADATA_PACKET_CONTROL 0x216f
#define mmDIG1_HDMI_METADATA_PACKET_CONTROL_BASE_IDX 2
#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL4 0x2170
#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX 2
#define mmDIG1_HDMI_CONTROL 0x2171
#define mmDIG1_HDMI_CONTROL_BASE_IDX 2
#define mmDIG1_HDMI_STATUS 0x2172
#define mmDIG1_HDMI_STATUS_BASE_IDX 2
#define mmDIG1_HDMI_AUDIO_PACKET_CONTROL 0x2173
#define mmDIG1_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2
#define mmDIG1_HDMI_ACR_PACKET_CONTROL 0x2174
#define mmDIG1_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2
#define mmDIG1_HDMI_VBI_PACKET_CONTROL 0x2175
#define mmDIG1_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2
#define mmDIG1_HDMI_INFOFRAME_CONTROL0 0x2176
#define mmDIG1_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2
#define mmDIG1_HDMI_INFOFRAME_CONTROL1 0x2177
#define mmDIG1_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2
#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL0 0x2178
#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2
#define mmDIG1_AFMT_INTERRUPT_STATUS 0x2179
#define mmDIG1_AFMT_INTERRUPT_STATUS_BASE_IDX 2
#define mmDIG1_HDMI_GC 0x217b
#define mmDIG1_HDMI_GC_BASE_IDX 2
#define mmDIG1_AFMT_AUDIO_PACKET_CONTROL2 0x217c
#define mmDIG1_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2
#define mmDIG1_AFMT_ISRC1_0 0x217d
#define mmDIG1_AFMT_ISRC1_0_BASE_IDX 2
#define mmDIG1_AFMT_ISRC1_1 0x217e
#define mmDIG1_AFMT_ISRC1_1_BASE_IDX 2
#define mmDIG1_AFMT_ISRC1_2 0x217f
#define mmDIG1_AFMT_ISRC1_2_BASE_IDX 2
#define mmDIG1_AFMT_ISRC1_3 0x2180
#define mmDIG1_AFMT_ISRC1_3_BASE_IDX 2
#define mmDIG1_AFMT_ISRC1_4 0x2181
#define mmDIG1_AFMT_ISRC1_4_BASE_IDX 2
#define mmDIG1_AFMT_ISRC2_0 0x2182
#define mmDIG1_AFMT_ISRC2_0_BASE_IDX 2
#define mmDIG1_AFMT_ISRC2_1 0x2183
#define mmDIG1_AFMT_ISRC2_1_BASE_IDX 2
#define mmDIG1_AFMT_ISRC2_2 0x2184
#define mmDIG1_AFMT_ISRC2_2_BASE_IDX 2
#define mmDIG1_AFMT_ISRC2_3 0x2185
#define mmDIG1_AFMT_ISRC2_3_BASE_IDX 2
#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL2 0x2186
#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2
#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL3 0x2187
#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2
#define mmDIG1_HDMI_DB_CONTROL 0x2188
#define mmDIG1_HDMI_DB_CONTROL_BASE_IDX 2
#define mmDIG1_DME_CONTROL 0x2189
#define mmDIG1_DME_CONTROL_BASE_IDX 2
#define mmDIG1_AFMT_MPEG_INFO0 0x218a
#define mmDIG1_AFMT_MPEG_INFO0_BASE_IDX 2
#define mmDIG1_AFMT_MPEG_INFO1 0x218b
#define mmDIG1_AFMT_MPEG_INFO1_BASE_IDX 2
#define mmDIG1_AFMT_GENERIC_HDR 0x218c
#define mmDIG1_AFMT_GENERIC_HDR_BASE_IDX 2
#define mmDIG1_AFMT_GENERIC_0 0x218d
#define mmDIG1_AFMT_GENERIC_0_BASE_IDX 2
#define mmDIG1_AFMT_GENERIC_1 0x218e
#define mmDIG1_AFMT_GENERIC_1_BASE_IDX 2
#define mmDIG1_AFMT_GENERIC_2 0x218f
#define mmDIG1_AFMT_GENERIC_2_BASE_IDX 2
#define mmDIG1_AFMT_GENERIC_3 0x2190
#define mmDIG1_AFMT_GENERIC_3_BASE_IDX 2
#define mmDIG1_AFMT_GENERIC_4 0x2191
#define mmDIG1_AFMT_GENERIC_4_BASE_IDX 2
#define mmDIG1_AFMT_GENERIC_5 0x2192
#define mmDIG1_AFMT_GENERIC_5_BASE_IDX 2
#define mmDIG1_AFMT_GENERIC_6 0x2193
#define mmDIG1_AFMT_GENERIC_6_BASE_IDX 2
#define mmDIG1_AFMT_GENERIC_7 0x2194
#define mmDIG1_AFMT_GENERIC_7_BASE_IDX 2
#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL1 0x2195
#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2
#define mmDIG1_HDMI_ACR_32_0 0x2196
#define mmDIG1_HDMI_ACR_32_0_BASE_IDX 2
#define mmDIG1_HDMI_ACR_32_1 0x2197
#define mmDIG1_HDMI_ACR_32_1_BASE_IDX 2
#define mmDIG1_HDMI_ACR_44_0 0x2198
#define mmDIG1_HDMI_ACR_44_0_BASE_IDX 2
#define mmDIG1_HDMI_ACR_44_1 0x2199
#define mmDIG1_HDMI_ACR_44_1_BASE_IDX 2
#define mmDIG1_HDMI_ACR_48_0 0x219a
#define mmDIG1_HDMI_ACR_48_0_BASE_IDX 2
#define mmDIG1_HDMI_ACR_48_1 0x219b
#define mmDIG1_HDMI_ACR_48_1_BASE_IDX 2
#define mmDIG1_HDMI_ACR_STATUS_0 0x219c
#define mmDIG1_HDMI_ACR_STATUS_0_BASE_IDX 2
#define mmDIG1_HDMI_ACR_STATUS_1 0x219d
#define mmDIG1_HDMI_ACR_STATUS_1_BASE_IDX 2
#define mmDIG1_AFMT_AUDIO_INFO0 0x219e
#define mmDIG1_AFMT_AUDIO_INFO0_BASE_IDX 2
#define mmDIG1_AFMT_AUDIO_INFO1 0x219f
#define mmDIG1_AFMT_AUDIO_INFO1_BASE_IDX 2
#define mmDIG1_AFMT_60958_0 0x21a0
#define mmDIG1_AFMT_60958_0_BASE_IDX 2
#define mmDIG1_AFMT_60958_1 0x21a1
#define mmDIG1_AFMT_60958_1_BASE_IDX 2
#define mmDIG1_AFMT_AUDIO_CRC_CONTROL 0x21a2
#define mmDIG1_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2
#define mmDIG1_AFMT_RAMP_CONTROL0 0x21a3
#define mmDIG1_AFMT_RAMP_CONTROL0_BASE_IDX 2
#define mmDIG1_AFMT_RAMP_CONTROL1 0x21a4
#define mmDIG1_AFMT_RAMP_CONTROL1_BASE_IDX 2
#define mmDIG1_AFMT_RAMP_CONTROL2 0x21a5
#define mmDIG1_AFMT_RAMP_CONTROL2_BASE_IDX 2
#define mmDIG1_AFMT_RAMP_CONTROL3 0x21a6
#define mmDIG1_AFMT_RAMP_CONTROL3_BASE_IDX 2
#define mmDIG1_AFMT_60958_2 0x21a7
#define mmDIG1_AFMT_60958_2_BASE_IDX 2
#define mmDIG1_AFMT_AUDIO_CRC_RESULT 0x21a8
#define mmDIG1_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2
#define mmDIG1_AFMT_STATUS 0x21a9
#define mmDIG1_AFMT_STATUS_BASE_IDX 2
#define mmDIG1_AFMT_AUDIO_PACKET_CONTROL 0x21aa
#define mmDIG1_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2
#define mmDIG1_AFMT_VBI_PACKET_CONTROL 0x21ab
#define mmDIG1_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2
#define mmDIG1_AFMT_INFOFRAME_CONTROL0 0x21ac
#define mmDIG1_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2
#define mmDIG1_AFMT_AUDIO_SRC_CONTROL 0x21ad
#define mmDIG1_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2
#define mmDIG1_DIG_BE_CNTL 0x21af
#define mmDIG1_DIG_BE_CNTL_BASE_IDX 2
#define mmDIG1_DIG_BE_EN_CNTL 0x21b0
#define mmDIG1_DIG_BE_EN_CNTL_BASE_IDX 2
#define mmDIG1_TMDS_CNTL 0x21d3
#define mmDIG1_TMDS_CNTL_BASE_IDX 2
#define mmDIG1_TMDS_CONTROL_CHAR 0x21d4
#define mmDIG1_TMDS_CONTROL_CHAR_BASE_IDX 2
#define mmDIG1_TMDS_CONTROL0_FEEDBACK 0x21d5
#define mmDIG1_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2
#define mmDIG1_TMDS_STEREOSYNC_CTL_SEL 0x21d6
#define mmDIG1_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2
#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_0_1 0x21d7
#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2
#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_2_3 0x21d8
#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2
#define mmDIG1_TMDS_CTL_BITS 0x21da
#define mmDIG1_TMDS_CTL_BITS_BASE_IDX 2
#define mmDIG1_TMDS_DCBALANCER_CONTROL 0x21db
#define mmDIG1_TMDS_DCBALANCER_CONTROL_BASE_IDX 2
#define mmDIG1_TMDS_SYNC_DCBALANCE_CHAR 0x21dc
#define mmDIG1_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX 2
#define mmDIG1_TMDS_CTL0_1_GEN_CNTL 0x21dd
#define mmDIG1_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2
#define mmDIG1_TMDS_CTL2_3_GEN_CNTL 0x21de
#define mmDIG1_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2
#define mmDIG1_DIG_VERSION 0x21e0
#define mmDIG1_DIG_VERSION_BASE_IDX 2
#define mmDIG1_DIG_LANE_ENABLE 0x21e1
#define mmDIG1_DIG_LANE_ENABLE_BASE_IDX 2
#define mmDIG1_AFMT_CNTL 0x21e6
#define mmDIG1_AFMT_CNTL_BASE_IDX 2
#define mmDIG1_AFMT_VBI_PACKET_CONTROL1 0x21e7
#define mmDIG1_AFMT_VBI_PACKET_CONTROL1_BASE_IDX 2
#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL5 0x21f6
#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX 2
// addressBlock: dce_dc_dio_dp1_dispdec
// base address: 0x400
#define mmDP1_DP_LINK_CNTL 0x2208
#define mmDP1_DP_LINK_CNTL_BASE_IDX 2
#define mmDP1_DP_PIXEL_FORMAT 0x2209
#define mmDP1_DP_PIXEL_FORMAT_BASE_IDX 2
#define mmDP1_DP_MSA_COLORIMETRY 0x220a
#define mmDP1_DP_MSA_COLORIMETRY_BASE_IDX 2
#define mmDP1_DP_CONFIG 0x220b
#define mmDP1_DP_CONFIG_BASE_IDX 2
#define mmDP1_DP_VID_STREAM_CNTL 0x220c
#define mmDP1_DP_VID_STREAM_CNTL_BASE_IDX 2
#define mmDP1_DP_STEER_FIFO 0x220d
#define mmDP1_DP_STEER_FIFO_BASE_IDX 2
#define mmDP1_DP_MSA_MISC 0x220e
#define mmDP1_DP_MSA_MISC_BASE_IDX 2
#define mmDP1_DP_VID_TIMING 0x2210
#define mmDP1_DP_VID_TIMING_BASE_IDX 2
#define mmDP1_DP_VID_N 0x2211
#define mmDP1_DP_VID_N_BASE_IDX 2
#define mmDP1_DP_VID_M 0x2212
#define mmDP1_DP_VID_M_BASE_IDX 2
#define mmDP1_DP_LINK_FRAMING_CNTL 0x2213
#define mmDP1_DP_LINK_FRAMING_CNTL_BASE_IDX 2
#define mmDP1_DP_HBR2_EYE_PATTERN 0x2214
#define mmDP1_DP_HBR2_EYE_PATTERN_BASE_IDX 2
#define mmDP1_DP_VID_MSA_VBID 0x2215
#define mmDP1_DP_VID_MSA_VBID_BASE_IDX 2
#define mmDP1_DP_VID_INTERRUPT_CNTL 0x2216
#define mmDP1_DP_VID_INTERRUPT_CNTL_BASE_IDX 2
#define mmDP1_DP_DPHY_CNTL 0x2217
#define mmDP1_DP_DPHY_CNTL_BASE_IDX 2
#define mmDP1_DP_DPHY_TRAINING_PATTERN_SEL 0x2218
#define mmDP1_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2
#define mmDP1_DP_DPHY_SYM0 0x2219
#define mmDP1_DP_DPHY_SYM0_BASE_IDX 2
#define mmDP1_DP_DPHY_SYM1 0x221a
#define mmDP1_DP_DPHY_SYM1_BASE_IDX 2
#define mmDP1_DP_DPHY_SYM2 0x221b
#define mmDP1_DP_DPHY_SYM2_BASE_IDX 2
#define mmDP1_DP_DPHY_8B10B_CNTL 0x221c
#define mmDP1_DP_DPHY_8B10B_CNTL_BASE_IDX 2
#define mmDP1_DP_DPHY_PRBS_CNTL 0x221d
#define mmDP1_DP_DPHY_PRBS_CNTL_BASE_IDX 2
#define mmDP1_DP_DPHY_SCRAM_CNTL 0x221e
#define mmDP1_DP_DPHY_SCRAM_CNTL_BASE_IDX 2
#define mmDP1_DP_DPHY_CRC_EN 0x221f
#define mmDP1_DP_DPHY_CRC_EN_BASE_IDX 2
#define mmDP1_DP_DPHY_CRC_CNTL 0x2220
#define mmDP1_DP_DPHY_CRC_CNTL_BASE_IDX 2
#define mmDP1_DP_DPHY_CRC_RESULT 0x2221
#define mmDP1_DP_DPHY_CRC_RESULT_BASE_IDX 2
#define mmDP1_DP_DPHY_CRC_MST_CNTL 0x2222
#define mmDP1_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2
#define mmDP1_DP_DPHY_CRC_MST_STATUS 0x2223
#define mmDP1_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2
#define mmDP1_DP_DPHY_FAST_TRAINING 0x2224
#define mmDP1_DP_DPHY_FAST_TRAINING_BASE_IDX 2
#define mmDP1_DP_DPHY_FAST_TRAINING_STATUS 0x2225
#define mmDP1_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2
#define mmDP1_DP_SEC_CNTL 0x222b
#define mmDP1_DP_SEC_CNTL_BASE_IDX 2
#define mmDP1_DP_SEC_CNTL1 0x222c
#define mmDP1_DP_SEC_CNTL1_BASE_IDX 2
#define mmDP1_DP_SEC_FRAMING1 0x222d
#define mmDP1_DP_SEC_FRAMING1_BASE_IDX 2
#define mmDP1_DP_SEC_FRAMING2 0x222e
#define mmDP1_DP_SEC_FRAMING2_BASE_IDX 2
#define mmDP1_DP_SEC_FRAMING3 0x222f
#define mmDP1_DP_SEC_FRAMING3_BASE_IDX 2
#define mmDP1_DP_SEC_FRAMING4 0x2230
#define mmDP1_DP_SEC_FRAMING4_BASE_IDX 2
#define mmDP1_DP_SEC_AUD_N 0x2231
#define mmDP1_DP_SEC_AUD_N_BASE_IDX 2
#define mmDP1_DP_SEC_AUD_N_READBACK 0x2232
#define mmDP1_DP_SEC_AUD_N_READBACK_BASE_IDX 2
#define mmDP1_DP_SEC_AUD_M 0x2233
#define mmDP1_DP_SEC_AUD_M_BASE_IDX 2
#define mmDP1_DP_SEC_AUD_M_READBACK 0x2234
#define mmDP1_DP_SEC_AUD_M_READBACK_BASE_IDX 2
#define mmDP1_DP_SEC_TIMESTAMP 0x2235
#define mmDP1_DP_SEC_TIMESTAMP_BASE_IDX 2
#define mmDP1_DP_SEC_PACKET_CNTL 0x2236
#define mmDP1_DP_SEC_PACKET_CNTL_BASE_IDX 2
#define mmDP1_DP_MSE_RATE_CNTL 0x2237
#define mmDP1_DP_MSE_RATE_CNTL_BASE_IDX 2
#define mmDP1_DP_MSE_RATE_UPDATE 0x2239
#define mmDP1_DP_MSE_RATE_UPDATE_BASE_IDX 2
#define mmDP1_DP_MSE_SAT0 0x223a
#define mmDP1_DP_MSE_SAT0_BASE_IDX 2
#define mmDP1_DP_MSE_SAT1 0x223b
#define mmDP1_DP_MSE_SAT1_BASE_IDX 2
#define mmDP1_DP_MSE_SAT2 0x223c
#define mmDP1_DP_MSE_SAT2_BASE_IDX 2
#define mmDP1_DP_MSE_SAT_UPDATE 0x223d
#define mmDP1_DP_MSE_SAT_UPDATE_BASE_IDX 2
#define mmDP1_DP_MSE_LINK_TIMING 0x223e
#define mmDP1_DP_MSE_LINK_TIMING_BASE_IDX 2
#define mmDP1_DP_MSE_MISC_CNTL 0x223f
#define mmDP1_DP_MSE_MISC_CNTL_BASE_IDX 2
#define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL 0x2244
#define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2
#define mmDP1_DP_DPHY_HBR2_PATTERN_CONTROL 0x2245
#define mmDP1_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2
#define mmDP1_DP_MSE_SAT0_STATUS 0x2247
#define mmDP1_DP_MSE_SAT0_STATUS_BASE_IDX 2
#define mmDP1_DP_MSE_SAT1_STATUS 0x2248
#define mmDP1_DP_MSE_SAT1_STATUS_BASE_IDX 2
#define mmDP1_DP_MSE_SAT2_STATUS 0x2249
#define mmDP1_DP_MSE_SAT2_STATUS_BASE_IDX 2
#define mmDP1_DP_MSA_TIMING_PARAM1 0x224c
#define mmDP1_DP_MSA_TIMING_PARAM1_BASE_IDX 2
#define mmDP1_DP_MSA_TIMING_PARAM2 0x224d
#define mmDP1_DP_MSA_TIMING_PARAM2_BASE_IDX 2
#define mmDP1_DP_MSA_TIMING_PARAM3 0x224e
#define mmDP1_DP_MSA_TIMING_PARAM3_BASE_IDX 2
#define mmDP1_DP_MSA_TIMING_PARAM4 0x224f
#define mmDP1_DP_MSA_TIMING_PARAM4_BASE_IDX 2
#define mmDP1_DP_DSC_CNTL 0x2252
#define mmDP1_DP_DSC_CNTL_BASE_IDX 2
#define mmDP1_DP_SEC_CNTL2 0x2253
#define mmDP1_DP_SEC_CNTL2_BASE_IDX 2
#define mmDP1_DP_SEC_CNTL3 0x2254
#define mmDP1_DP_SEC_CNTL3_BASE_IDX 2
#define mmDP1_DP_SEC_CNTL4 0x2255
#define mmDP1_DP_SEC_CNTL4_BASE_IDX 2
#define mmDP1_DP_SEC_CNTL5 0x2256
#define mmDP1_DP_SEC_CNTL5_BASE_IDX 2
#define mmDP1_DP_SEC_CNTL6 0x2257
#define mmDP1_DP_SEC_CNTL6_BASE_IDX 2
#define mmDP1_DP_SEC_CNTL7 0x2258
#define mmDP1_DP_SEC_CNTL7_BASE_IDX 2
#define mmDP1_DP_DB_CNTL 0x2259
#define mmDP1_DP_DB_CNTL_BASE_IDX 2
#define mmDP1_DP_MSA_VBID_MISC 0x225a
#define mmDP1_DP_MSA_VBID_MISC_BASE_IDX 2
#define mmDP1_DP_SEC_METADATA_TRANSMISSION 0x225b
#define mmDP1_DP_SEC_METADATA_TRANSMISSION_BASE_IDX 2
#define mmDP1_DP_DSC_BYTES_PER_PIXEL 0x225c
#define mmDP1_DP_DSC_BYTES_PER_PIXEL_BASE_IDX 2
// addressBlock: dce_dc_dcio_dcio_dispdec
// base address: 0x0
#define mmDC_GENERICA 0x2868
#define mmDC_GENERICA_BASE_IDX 2
#define mmUNIPHYA_LINK_CNTL 0x286d
#define mmUNIPHYA_LINK_CNTL_BASE_IDX 2
#define mmUNIPHYA_CHANNEL_XBAR_CNTL 0x286e
#define mmUNIPHYA_CHANNEL_XBAR_CNTL_BASE_IDX 2
#define mmUNIPHYB_LINK_CNTL 0x286f
#define mmUNIPHYB_LINK_CNTL_BASE_IDX 2
#define mmUNIPHYB_CHANNEL_XBAR_CNTL 0x2870
#define mmUNIPHYB_CHANNEL_XBAR_CNTL_BASE_IDX 2
#define mmDCIO_WRCMD_DELAY 0x287e
#define mmDCIO_WRCMD_DELAY_BASE_IDX 2
#define mmDC_PINSTRAPS 0x2880
#define mmDC_PINSTRAPS_BASE_IDX 2
#define mmDCIO_CLOCK_CNTL 0x2895
#define mmDCIO_CLOCK_CNTL_BASE_IDX 2
#define mmDCIO_SOFT_RESET 0x289e
#define mmDCIO_SOFT_RESET_BASE_IDX 2
// addressBlock: dce_dc_dcio_dcio_chip_dispdec
// base address: 0x0
#define mmDC_GPIO_DDC1_MASK 0x28d0
#define mmDC_GPIO_DDC1_MASK_BASE_IDX 2
#define mmDC_GPIO_DDC1_A 0x28d1
#define mmDC_GPIO_DDC1_A_BASE_IDX 2
#define mmDC_GPIO_DDC1_EN 0x28d2
#define mmDC_GPIO_DDC1_EN_BASE_IDX 2
#define mmDC_GPIO_DDC1_Y 0x28d3
#define mmDC_GPIO_DDC1_Y_BASE_IDX 2
#define mmDC_GPIO_DDC2_MASK 0x28d4
#define mmDC_GPIO_DDC2_MASK_BASE_IDX 2
#define mmDC_GPIO_DDC2_A 0x28d5
#define mmDC_GPIO_DDC2_A_BASE_IDX 2
#define mmDC_GPIO_DDC2_EN 0x28d6
#define mmDC_GPIO_DDC2_EN_BASE_IDX 2
#define mmDC_GPIO_DDC2_Y 0x28d7
#define mmDC_GPIO_DDC2_Y_BASE_IDX 2
#define mmDC_GPIO_HPD_MASK 0x28f4
#define mmDC_GPIO_HPD_MASK_BASE_IDX 2
#define mmDC_GPIO_HPD_A 0x28f5
#define mmDC_GPIO_HPD_A_BASE_IDX 2
#define mmDC_GPIO_HPD_EN 0x28f6
#define mmDC_GPIO_HPD_EN_BASE_IDX 2
#define mmDC_GPIO_HPD_Y 0x28f7
#define mmDC_GPIO_HPD_Y_BASE_IDX 2
#define mmDC_GPIO_PAD_STRENGTH_1 0x28fc
#define mmDC_GPIO_PAD_STRENGTH_1_BASE_IDX 2
#define mmPHY_AUX_CNTL 0x28ff
#define mmPHY_AUX_CNTL_BASE_IDX 2
#define mmDC_GPIO_AUX_CTRL_1 0x2917
#define mmDC_GPIO_AUX_CTRL_1_BASE_IDX 2
#define mmDC_GPIO_AUX_CTRL_2 0x2918
#define mmDC_GPIO_AUX_CTRL_2_BASE_IDX 2
#define mmDC_GPIO_AUX_CTRL_3 0x291b
#define mmDC_GPIO_AUX_CTRL_3_BASE_IDX 2
#define mmDC_GPIO_AUX_CTRL_4 0x291c
#define mmDC_GPIO_AUX_CTRL_4_BASE_IDX 2
#define mmDC_GPIO_AUX_CTRL_5 0x291d
#define mmDC_GPIO_AUX_CTRL_5_BASE_IDX 2
#define mmAUXI2C_PAD_ALL_PWR_OK 0x291e
#define mmAUXI2C_PAD_ALL_PWR_OK_BASE_IDX 2
// addressBlock: azf0endpoint0_endpointind
// base address: 0x0
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058
#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059
#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a
#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b
#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c
#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d
#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e
#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f
#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060
#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a
#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b
#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c
#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d
#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e
// addressBlock: azf0endpoint1_endpointind
// base address: 0x0
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058
#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059
#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a
#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b
#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c
#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d
#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e
#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f
#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060
#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a
#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b
#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c
#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d
#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e
// addressBlock: azf0inputendpoint0_inputendpointind
// base address: 0x0
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068
// addressBlock: azf0inputendpoint1_inputendpointind
// base address: 0x0
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068
#endif
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