chromium/components/zucchini/arm_utils.cc

// Copyright 2019 The Chromium Authors
// Use of this source code is governed by a BSD-style license that can be
// found in the LICENSE file.

#include "components/zucchini/arm_utils.h"

#include "components/zucchini/algorithm.h"

namespace zucchini {

namespace {

inline bool IsMisaligned(rva_t rva, ArmAlign align) { … }

}  // namespace

/******** AArch32Rel32Translator ********/

AArch32Rel32Translator::AArch32Rel32Translator() = default;

// The mapping between ARM instruction "Code" to "Displacement" involves complex
// bit manipulation. The comments below annotate bits mappings using a string.
// * Bits are listed from highest-order to lowerst-order (like in the manual).
// * '0' and '1' denote literals.
// * Uppercase letters denote a single bit in "Code". For example, 'S' denotes
//   a sign bit that gets extended in "Displacement". To follow naming in the
//   manual, these may enumerated, and written as "(I1)", "(I2)", etc.
// * Lowercase letters denote bit fields with orders preserved.

// static
ArmAlign AArch32Rel32Translator::DecodeA24(uint32_t code32, arm_disp_t* disp) { … }

// static
bool AArch32Rel32Translator::EncodeA24(arm_disp_t disp, uint32_t* code32) { … }

// static
bool AArch32Rel32Translator::ReadA24(rva_t instr_rva,
                                     uint32_t code32,
                                     rva_t* target_rva) { … }

// static
bool AArch32Rel32Translator::WriteA24(rva_t instr_rva,
                                      rva_t target_rva,
                                      uint32_t* code32) { … }

// static
ArmAlign AArch32Rel32Translator::DecodeT8(uint16_t code16, arm_disp_t* disp) { … }

// static
bool AArch32Rel32Translator::EncodeT8(arm_disp_t disp, uint16_t* code16) { … }

// static
bool AArch32Rel32Translator::ReadT8(rva_t instr_rva,
                                    uint16_t code16,
                                    rva_t* target_rva) { … }

// static
bool AArch32Rel32Translator::WriteT8(rva_t instr_rva,
                                     rva_t target_rva,
                                     uint16_t* code16) { … }

// static
ArmAlign AArch32Rel32Translator::DecodeT11(uint16_t code16, arm_disp_t* disp) { … }

// static
bool AArch32Rel32Translator::EncodeT11(arm_disp_t disp, uint16_t* code16) { … }

// static
bool AArch32Rel32Translator::ReadT11(rva_t instr_rva,
                                     uint16_t code16,
                                     rva_t* target_rva) { … }

// static
bool AArch32Rel32Translator::WriteT11(rva_t instr_rva,
                                      rva_t target_rva,
                                      uint16_t* code16) { … }

// static
ArmAlign AArch32Rel32Translator::DecodeT20(uint32_t code32, arm_disp_t* disp) { … }

// static
bool AArch32Rel32Translator::EncodeT20(arm_disp_t disp, uint32_t* code32) { … }

// static
bool AArch32Rel32Translator::ReadT20(rva_t instr_rva,
                                     uint32_t code32,
                                     rva_t* target_rva) { … }

// static
bool AArch32Rel32Translator::WriteT20(rva_t instr_rva,
                                      rva_t target_rva,
                                      uint32_t* code32) { … }

// static
ArmAlign AArch32Rel32Translator::DecodeT24(uint32_t code32, arm_disp_t* disp) { … }

// static
bool AArch32Rel32Translator::EncodeT24(arm_disp_t disp, uint32_t* code32) { … }

// static
bool AArch32Rel32Translator::ReadT24(rva_t instr_rva,
                                     uint32_t code32,
                                     rva_t* target_rva) { … }

// static
bool AArch32Rel32Translator::WriteT24(rva_t instr_rva,
                                      rva_t target_rva,
                                      uint32_t* code32) { … }

/******** AArch64Rel32Translator ********/

AArch64Rel32Translator::AArch64Rel32Translator() = default;

// static
ArmAlign AArch64Rel32Translator::DecodeImmd14(uint32_t code32,
                                              arm_disp_t* disp) { … }

// static
bool AArch64Rel32Translator::EncodeImmd14(arm_disp_t disp, uint32_t* code32) { … }

// static
bool AArch64Rel32Translator::ReadImmd14(rva_t instr_rva,
                                        uint32_t code32,
                                        rva_t* target_rva) { … }

// static
bool AArch64Rel32Translator::WriteImmd14(rva_t instr_rva,
                                         rva_t target_rva,
                                         uint32_t* code32) { … }

// static
ArmAlign AArch64Rel32Translator::DecodeImmd19(uint32_t code32,
                                              arm_disp_t* disp) { … }

// static
bool AArch64Rel32Translator::EncodeImmd19(arm_disp_t disp, uint32_t* code32) { … }

// static
bool AArch64Rel32Translator::ReadImmd19(rva_t instr_rva,
                                        uint32_t code32,
                                        rva_t* target_rva) { … }

// static
bool AArch64Rel32Translator::WriteImmd19(rva_t instr_rva,
                                         rva_t target_rva,
                                         uint32_t* code32) { … }

// static
ArmAlign AArch64Rel32Translator::DecodeImmd26(uint32_t code32,
                                              arm_disp_t* disp) { … }

// static
bool AArch64Rel32Translator::EncodeImmd26(arm_disp_t disp, uint32_t* code32) { … }

// static
bool AArch64Rel32Translator::ReadImmd26(rva_t instr_rva,
                                        uint32_t code32,
                                        rva_t* target_rva) { … }

// static
bool AArch64Rel32Translator::WriteImmd26(rva_t instr_rva,
                                         rva_t target_rva,
                                         uint32_t* code32) { … }

}  // namespace zucchini