/* * Copyright (c) 2016, Alliance for Open Media. All rights reserved. * * This source code is subject to the terms of the BSD 2 Clause License and * the Alliance for Open Media Patent License 1.0. If the BSD 2 Clause License * was not distributed with this source code in the LICENSE file, you can * obtain it at www.aomedia.org/license/software. If the Alliance for Open * Media Patent License 1.0 was not distributed with this source code in the * PATENTS file, you can obtain it at www.aomedia.org/license/patent. */ #ifndef AOM_AOM_DSP_SIMD_V256_INTRINSICS_X86_H_ #define AOM_AOM_DSP_SIMD_V256_INTRINSICS_X86_H_ #if !defined(__AVX2__) #include "aom_dsp/simd/v256_intrinsics_v128.h" #else // The _m256i type seems to cause problems for g++'s mangling prior to // version 5, but adding -fabi-version=0 fixes this. #if !defined(__clang__) && defined(__GNUC__) && __GNUC__ < 5 && \ defined(__AVX2__) && defined(__cplusplus) #pragma GCC optimize "-fabi-version=0" #endif #include <immintrin.h> #include "aom_dsp/simd/v128_intrinsics_x86.h" v256; SIMD_INLINE uint32_t v256_low_u32(v256 a) { … } SIMD_INLINE v64 v256_low_v64(v256 a) { … } SIMD_INLINE uint64_t v256_low_u64(v256 a) { … } SIMD_INLINE v128 v256_low_v128(v256 a) { … } SIMD_INLINE v128 v256_high_v128(v256 a) { … } SIMD_INLINE v256 v256_from_v128(v128 a, v128 b) { … } SIMD_INLINE v256 v256_from_v64(v64 a, v64 b, v64 c, v64 d) { … } SIMD_INLINE v256 v256_from_64(uint64_t a, uint64_t b, uint64_t c, uint64_t d) { … } SIMD_INLINE v256 v256_load_aligned(const void *p) { … } SIMD_INLINE v256 v256_load_unaligned(const void *p) { … } SIMD_INLINE void v256_store_aligned(void *p, v256 a) { … } SIMD_INLINE void v256_store_unaligned(void *p, v256 a) { … } SIMD_INLINE v256 v256_zero(void) { … } SIMD_INLINE v256 v256_dup_8(uint8_t x) { … } SIMD_INLINE v256 v256_dup_16(uint16_t x) { … } SIMD_INLINE v256 v256_dup_32(uint32_t x) { … } SIMD_INLINE v256 v256_dup_64(uint64_t x) { … } SIMD_INLINE v256 v256_add_8(v256 a, v256 b) { … } SIMD_INLINE v256 v256_add_16(v256 a, v256 b) { … } SIMD_INLINE v256 v256_sadd_u8(v256 a, v256 b) { … } SIMD_INLINE v256 v256_sadd_s8(v256 a, v256 b) { … } SIMD_INLINE v256 v256_sadd_s16(v256 a, v256 b) { … } SIMD_INLINE v256 v256_add_32(v256 a, v256 b) { … } SIMD_INLINE v256 v256_add_64(v256 a, v256 b) { … } SIMD_INLINE v256 v256_padd_u8(v256 a) { … } SIMD_INLINE v256 v256_padd_s16(v256 a) { … } SIMD_INLINE v256 v256_sub_8(v256 a, v256 b) { … } SIMD_INLINE v256 v256_ssub_u8(v256 a, v256 b) { … } SIMD_INLINE v256 v256_ssub_s8(v256 a, v256 b) { … } SIMD_INLINE v256 v256_sub_16(v256 a, v256 b) { … } SIMD_INLINE v256 v256_ssub_s16(v256 a, v256 b) { … } SIMD_INLINE v256 v256_ssub_u16(v256 a, v256 b) { … } SIMD_INLINE v256 v256_sub_32(v256 a, v256 b) { … } SIMD_INLINE v256 v256_sub_64(v256 a, v256 b) { … } SIMD_INLINE v256 v256_abs_s16(v256 a) { … } SIMD_INLINE v256 v256_abs_s8(v256 a) { … } // AVX doesn't have the direct intrinsics to zip/unzip 8, 16, 32 bit // lanes of lower or upper halves of a 256bit vector because the // unpack/pack intrinsics operate on the 256 bit input vector as 2 // independent 128 bit vectors. SIMD_INLINE v256 v256_ziplo_8(v256 a, v256 b) { … } SIMD_INLINE v256 v256_ziphi_8(v256 a, v256 b) { … } SIMD_INLINE v256 v256_ziplo_16(v256 a, v256 b) { … } SIMD_INLINE v256 v256_ziphi_16(v256 a, v256 b) { … } SIMD_INLINE v256 v256_ziplo_32(v256 a, v256 b) { … } SIMD_INLINE v256 v256_ziphi_32(v256 a, v256 b) { … } SIMD_INLINE v256 v256_ziplo_64(v256 a, v256 b) { … } SIMD_INLINE v256 v256_ziphi_64(v256 a, v256 b) { … } SIMD_INLINE v256 v256_ziplo_128(v256 a, v256 b) { … } SIMD_INLINE v256 v256_ziphi_128(v256 a, v256 b) { … } SIMD_INLINE v256 v256_zip_8(v128 a, v128 b) { … } SIMD_INLINE v256 v256_zip_16(v128 a, v128 b) { … } SIMD_INLINE v256 v256_zip_32(v128 a, v128 b) { … } SIMD_INLINE v256 v256_unziphi_8(v256 a, v256 b) { … } SIMD_INLINE v256 v256_unziplo_8(v256 a, v256 b) { … } SIMD_INLINE v256 v256_unziphi_16(v256 a, v256 b) { … } SIMD_INLINE v256 v256_unziplo_16(v256 a, v256 b) { … } SIMD_INLINE v256 v256_unziphi_32(v256 a, v256 b) { … } SIMD_INLINE v256 v256_unziplo_32(v256 a, v256 b) { … } SIMD_INLINE v256 v256_unziphi_64(v256 a, v256 b) { … } SIMD_INLINE v256 v256_unziplo_64(v256 a, v256 b) { … } SIMD_INLINE v256 v256_unpack_u8_s16(v128 a) { … } SIMD_INLINE v256 v256_unpacklo_u8_s16(v256 a) { … } SIMD_INLINE v256 v256_unpackhi_u8_s16(v256 a) { … } SIMD_INLINE v256 v256_unpack_s8_s16(v128 a) { … } SIMD_INLINE v256 v256_unpacklo_s8_s16(v256 a) { … } SIMD_INLINE v256 v256_unpackhi_s8_s16(v256 a) { … } SIMD_INLINE v256 v256_pack_s32_s16(v256 a, v256 b) { … } SIMD_INLINE v256 v256_pack_s32_u16(v256 a, v256 b) { … } SIMD_INLINE v256 v256_pack_s16_u8(v256 a, v256 b) { … } SIMD_INLINE v256 v256_pack_s16_s8(v256 a, v256 b) { … } SIMD_INLINE v256 v256_unpack_u16_s32(v128 a) { … } SIMD_INLINE v256 v256_unpack_s16_s32(v128 a) { … } SIMD_INLINE v256 v256_unpacklo_u16_s32(v256 a) { … } SIMD_INLINE v256 v256_unpacklo_s16_s32(v256 a) { … } SIMD_INLINE v256 v256_unpackhi_u16_s32(v256 a) { … } SIMD_INLINE v256 v256_unpackhi_s16_s32(v256 a) { … } SIMD_INLINE v256 v256_shuffle_8(v256 a, v256 pattern) { … } SIMD_INLINE v256 v256_wideshuffle_8(v256 a, v256 b, v256 pattern) { … } SIMD_INLINE v256 v256_pshuffle_8(v256 a, v256 pattern) { … } SIMD_INLINE int64_t v256_dotp_su8(v256 a, v256 b) { … } SIMD_INLINE int64_t v256_dotp_s16(v256 a, v256 b) { … } SIMD_INLINE int64_t v256_dotp_s32(v256 a, v256 b) { … } SIMD_INLINE uint64_t v256_hadd_u8(v256 a) { … } sad256_internal; SIMD_INLINE sad256_internal v256_sad_u8_init(void) { … } /* Implementation dependent return value. Result must be finalised with v256_sad_u8_sum(). The result for more than 32 v256_sad_u8() calls is undefined. */ SIMD_INLINE sad256_internal v256_sad_u8(sad256_internal s, v256 a, v256 b) { … } SIMD_INLINE uint32_t v256_sad_u8_sum(sad256_internal s) { … } ssd256_internal; SIMD_INLINE ssd256_internal v256_ssd_u8_init(void) { … } /* Implementation dependent return value. Result must be finalised with * v256_ssd_u8_sum(). */ SIMD_INLINE ssd256_internal v256_ssd_u8(ssd256_internal s, v256 a, v256 b) { … } SIMD_INLINE uint32_t v256_ssd_u8_sum(ssd256_internal s) { … } SIMD_INLINE v256 v256_or(v256 a, v256 b) { … } SIMD_INLINE v256 v256_xor(v256 a, v256 b) { … } SIMD_INLINE v256 v256_and(v256 a, v256 b) { … } SIMD_INLINE v256 v256_andn(v256 a, v256 b) { … } SIMD_INLINE v256 v256_mul_s16(v64 a, v64 b) { … } SIMD_INLINE v256 v256_mullo_s16(v256 a, v256 b) { … } SIMD_INLINE v256 v256_mulhi_s16(v256 a, v256 b) { … } SIMD_INLINE v256 v256_mullo_s32(v256 a, v256 b) { … } SIMD_INLINE v256 v256_madd_s16(v256 a, v256 b) { … } SIMD_INLINE v256 v256_madd_us8(v256 a, v256 b) { … } SIMD_INLINE v256 v256_avg_u8(v256 a, v256 b) { … } SIMD_INLINE v256 v256_rdavg_u8(v256 a, v256 b) { … } SIMD_INLINE v256 v256_rdavg_u16(v256 a, v256 b) { … } SIMD_INLINE v256 v256_avg_u16(v256 a, v256 b) { … } SIMD_INLINE v256 v256_min_u8(v256 a, v256 b) { … } SIMD_INLINE v256 v256_max_u8(v256 a, v256 b) { … } SIMD_INLINE v256 v256_min_s8(v256 a, v256 b) { … } SIMD_INLINE uint32_t v256_movemask_8(v256 a) { … } SIMD_INLINE v256 v256_blend_8(v256 a, v256 b, v256 c) { … } SIMD_INLINE v256 v256_max_s8(v256 a, v256 b) { … } SIMD_INLINE v256 v256_min_s16(v256 a, v256 b) { … } SIMD_INLINE v256 v256_max_s16(v256 a, v256 b) { … } SIMD_INLINE v256 v256_min_s32(v256 a, v256 b) { … } SIMD_INLINE v256 v256_max_s32(v256 a, v256 b) { … } SIMD_INLINE v256 v256_cmpgt_s8(v256 a, v256 b) { … } SIMD_INLINE v256 v256_cmplt_s8(v256 a, v256 b) { … } SIMD_INLINE v256 v256_cmpeq_8(v256 a, v256 b) { … } SIMD_INLINE v256 v256_cmpgt_s16(v256 a, v256 b) { … } SIMD_INLINE v256 v256_cmplt_s16(v256 a, v256 b) { … } SIMD_INLINE v256 v256_cmpeq_16(v256 a, v256 b) { … } SIMD_INLINE v256 v256_cmpgt_s32(v256 a, v256 b) { … } SIMD_INLINE v256 v256_cmplt_s32(v256 a, v256 b) { … } SIMD_INLINE v256 v256_cmpeq_32(v256 a, v256 b) { … } SIMD_INLINE v256 v256_shl_8(v256 a, unsigned int c) { … } SIMD_INLINE v256 v256_shr_u8(v256 a, unsigned int c) { … } SIMD_INLINE v256 v256_shr_s8(v256 a, unsigned int c) { … } SIMD_INLINE v256 v256_shl_16(v256 a, unsigned int c) { … } SIMD_INLINE v256 v256_shr_u16(v256 a, unsigned int c) { … } SIMD_INLINE v256 v256_shr_s16(v256 a, unsigned int c) { … } SIMD_INLINE v256 v256_shl_32(v256 a, unsigned int c) { … } SIMD_INLINE v256 v256_shr_u32(v256 a, unsigned int c) { … } SIMD_INLINE v256 v256_shr_s32(v256 a, unsigned int c) { … } SIMD_INLINE v256 v256_shl_64(v256 a, unsigned int c) { … } SIMD_INLINE v256 v256_shr_u64(v256 a, unsigned int c) { … } SIMD_INLINE v256 v256_shr_s64(v256 a, unsigned int c) { … } /* These intrinsics require immediate values, so we must use #defines to enforce that. */ // _mm256_slli_si256 works on 128 bit lanes and can't be used #define v256_shl_n_byte(a, n) … // _mm256_srli_si256 works on 128 bit lanes and can't be used #define v256_shr_n_byte(a, n) … // _mm256_alignr_epi8 works on two 128 bit lanes and can't be used #define v256_align(a, b, c) … #define v256_shl_n_8(a, c) … #define v256_shr_n_u8(a, c) … #define v256_shr_n_s8(a, c) … #define v256_shl_n_16(a, c) … #define v256_shr_n_u16(a, c) … #define v256_shr_n_s16(a, c) … #define v256_shl_n_32(a, c) … #define v256_shr_n_u32(a, c) … #define v256_shr_n_s32(a, c) … #define v256_shl_n_64(a, c) … #define v256_shr_n_u64(a, c) … #define v256_shr_n_s64(a, c) … #define v256_shr_n_word(a, n) … #define v256_shl_n_word(a, n) … sad256_internal_u16; SIMD_INLINE sad256_internal_u16 v256_sad_u16_init(void) { … } /* Implementation dependent return value. Result must be finalised with * v256_sad_u16_sum(). */ SIMD_INLINE sad256_internal_u16 v256_sad_u16(sad256_internal_u16 s, v256 a, v256 b) { … } SIMD_INLINE uint32_t v256_sad_u16_sum(sad256_internal_u16 s) { … } ssd256_internal_s16; SIMD_INLINE ssd256_internal_s16 v256_ssd_s16_init(void) { … } /* Implementation dependent return value. Result must be finalised with * v256_ssd_s16_sum(). */ SIMD_INLINE ssd256_internal_s16 v256_ssd_s16(ssd256_internal_s16 s, v256 a, v256 b) { … } SIMD_INLINE uint64_t v256_ssd_s16_sum(ssd256_internal_s16 s) { … } #endif #endif // AOM_AOM_DSP_SIMD_V256_INTRINSICS_X86_H_
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