/* CpuArch.h -- CPU specific code 2022-07-15 : Igor Pavlov : Public domain */ #ifndef __CPU_ARCH_H #define __CPU_ARCH_H #include "7zTypes.h" EXTERN_C_BEGIN /* MY_CPU_LE means that CPU is LITTLE ENDIAN. MY_CPU_BE means that CPU is BIG ENDIAN. If MY_CPU_LE and MY_CPU_BE are not defined, we don't know about ENDIANNESS of platform. MY_CPU_LE_UNALIGN means that CPU is LITTLE ENDIAN and CPU supports unaligned memory accesses. MY_CPU_64BIT means that processor can work with 64-bit registers. MY_CPU_64BIT can be used to select fast code branch MY_CPU_64BIT doesn't mean that (sizeof(void *) == 8) */ #if defined(_M_X64) \ || defined(_M_AMD64) \ || defined(__x86_64__) \ || defined(__AMD64__) \ || defined(__amd64__) #define MY_CPU_AMD64 #ifdef __ILP32__ #define MY_CPU_NAME … #define MY_CPU_SIZEOF_POINTER … #else #define MY_CPU_NAME … #define MY_CPU_SIZEOF_POINTER … #endif #define MY_CPU_64BIT #endif #if defined(_M_IX86) \ || defined(__i386__) #define MY_CPU_X86 #define MY_CPU_NAME … /* #define MY_CPU_32BIT */ #define MY_CPU_SIZEOF_POINTER … #endif #if defined(_M_ARM64) \ || defined(__AARCH64EL__) \ || defined(__AARCH64EB__) \ || defined(__aarch64__) #define MY_CPU_ARM64 #define MY_CPU_NAME … #define MY_CPU_64BIT #endif #if defined(_M_ARM) \ || defined(_M_ARM_NT) \ || defined(_M_ARMT) \ || defined(__arm__) \ || defined(__thumb__) \ || defined(__ARMEL__) \ || defined(__ARMEB__) \ || defined(__THUMBEL__) \ || defined(__THUMBEB__) #define MY_CPU_ARM #if defined(__thumb__) || defined(__THUMBEL__) || defined(_M_ARMT) #define MY_CPU_NAME … #else #define MY_CPU_NAME … #endif /* #define MY_CPU_32BIT */ #define MY_CPU_SIZEOF_POINTER … #endif #if defined(_M_IA64) \ || defined(__ia64__) #define MY_CPU_IA64 #define MY_CPU_NAME … #define MY_CPU_64BIT #endif #if defined(__mips64) \ || defined(__mips64__) \ || (defined(__mips) && (__mips == 64 || __mips == 4 || __mips == 3)) #define MY_CPU_NAME … #define MY_CPU_64BIT #elif defined(__mips__) #define MY_CPU_NAME … /* #define MY_CPU_32BIT */ #endif #if defined(__ppc64__) \ || defined(__powerpc64__) \ || defined(__ppc__) \ || defined(__powerpc__) \ || defined(__PPC__) \ || defined(_POWER) #if defined(__ppc64__) \ || defined(__powerpc64__) \ || defined(_LP64) \ || defined(__64BIT__) #ifdef __ILP32__ #define MY_CPU_NAME … #define MY_CPU_SIZEOF_POINTER … #else #define MY_CPU_NAME … #define MY_CPU_SIZEOF_POINTER … #endif #define MY_CPU_64BIT #else #define MY_CPU_NAME … #define MY_CPU_SIZEOF_POINTER … /* #define MY_CPU_32BIT */ #endif #endif #if defined(__riscv) \ || defined(__riscv__) #if __riscv_xlen == 32 #define MY_CPU_NAME … #elif __riscv_xlen == 64 #define MY_CPU_NAME … #else #define MY_CPU_NAME … #endif #endif #if defined(MY_CPU_X86) || defined(MY_CPU_AMD64) #define MY_CPU_X86_OR_AMD64 #endif #if defined(MY_CPU_ARM) || defined(MY_CPU_ARM64) #define MY_CPU_ARM_OR_ARM64 #endif #ifdef _WIN32 #ifdef MY_CPU_ARM #define MY_CPU_ARM_LE #endif #ifdef MY_CPU_ARM64 #define MY_CPU_ARM64_LE #endif #ifdef _M_IA64 #define MY_CPU_IA64_LE #endif #endif #if defined(MY_CPU_X86_OR_AMD64) \ || defined(MY_CPU_ARM_LE) \ || defined(MY_CPU_ARM64_LE) \ || defined(MY_CPU_IA64_LE) \ || defined(__LITTLE_ENDIAN__) \ || defined(__ARMEL__) \ || defined(__THUMBEL__) \ || defined(__AARCH64EL__) \ || defined(__MIPSEL__) \ || defined(__MIPSEL) \ || defined(_MIPSEL) \ || defined(__BFIN__) \ || (defined(__BYTE_ORDER__) && (__BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__)) #define MY_CPU_LE #endif #if defined(__BIG_ENDIAN__) \ || defined(__ARMEB__) \ || defined(__THUMBEB__) \ || defined(__AARCH64EB__) \ || defined(__MIPSEB__) \ || defined(__MIPSEB) \ || defined(_MIPSEB) \ || defined(__m68k__) \ || defined(__s390__) \ || defined(__s390x__) \ || defined(__zarch__) \ || (defined(__BYTE_ORDER__) && (__BYTE_ORDER__ == __ORDER_BIG_ENDIAN__)) #define MY_CPU_BE #endif #if defined(MY_CPU_LE) && defined(MY_CPU_BE) #error Stop_Compiling_Bad_Endian #endif #if defined(MY_CPU_32BIT) && defined(MY_CPU_64BIT) #error Stop_Compiling_Bad_32_64_BIT #endif #ifdef __SIZEOF_POINTER__ #ifdef MY_CPU_SIZEOF_POINTER #if MY_CPU_SIZEOF_POINTER != __SIZEOF_POINTER__ #error Stop_Compiling_Bad_MY_CPU_PTR_SIZE #endif #else #define MY_CPU_SIZEOF_POINTER … #endif #endif #if defined(MY_CPU_SIZEOF_POINTER) && (MY_CPU_SIZEOF_POINTER == 4) #if defined (_LP64) #error Stop_Compiling_Bad_MY_CPU_PTR_SIZE #endif #endif #ifdef _MSC_VER #if _MSC_VER >= 1300 #define MY_CPU_pragma_pack_push_1 … #define MY_CPU_pragma_pop … #else #define MY_CPU_pragma_pack_push_1 #define MY_CPU_pragma_pop #endif #else #ifdef __xlC__ #define MY_CPU_pragma_pack_push_1 … #define MY_CPU_pragma_pop … #else #define MY_CPU_pragma_pack_push_1 … #define MY_CPU_pragma_pop … #endif #endif #ifndef MY_CPU_NAME #ifdef MY_CPU_LE #define MY_CPU_NAME … #elif defined(MY_CPU_BE) #define MY_CPU_NAME … #else /* #define MY_CPU_NAME "" */ #endif #endif // Disable MY_CPU_LE_UNALIGN. Although the underlying ISA may be able to load // unaligned words, doing so via pointer casts is undefined behavior in C and // C++, under both strict aliasing and because it is invalid to construct // unaligned pointers. Instead, load the bytes generically and leave optimizing // this to the compiler. #if 0 #ifdef MY_CPU_LE #if defined(MY_CPU_X86_OR_AMD64) \ || defined(MY_CPU_ARM64) #define MY_CPU_LE_UNALIGN #define MY_CPU_LE_UNALIGN_64 #elif defined(__ARM_FEATURE_UNALIGNED) /* gcc9 for 32-bit arm can use LDRD instruction that requires 32-bit alignment. So we can't use unaligned 64-bit operations. */ #define MY_CPU_LE_UNALIGN #endif #endif #endif #ifdef MY_CPU_LE_UNALIGN #define GetUi16 … #define GetUi32 … #ifdef MY_CPU_LE_UNALIGN_64 #define GetUi64 … #endif #define SetUi16 … #define SetUi32 … #ifdef MY_CPU_LE_UNALIGN_64 #define SetUi64 … #endif #else #define GetUi16(p) … #define GetUi32(p) … #define SetUi16(p, v) … #define SetUi32(p, v) … #endif #ifndef MY_CPU_LE_UNALIGN_64 #define GetUi64(p) … #define SetUi64(p, v) … #endif #ifdef __has_builtin #define MY__has_builtin(x) … #else #define MY__has_builtin … #endif #if defined(MY_CPU_LE_UNALIGN) && /* defined(_WIN64) && */ defined(_MSC_VER) && (_MSC_VER >= 1300) /* Note: we use bswap instruction, that is unsupported in 386 cpu */ #include <stdlib.h> #pragma intrinsic(_byteswap_ushort) #pragma intrinsic(_byteswap_ulong) #pragma intrinsic(_byteswap_uint64) /* #define GetBe16(p) _byteswap_ushort(*(const UInt16 *)(const Byte *)(p)) */ #define GetBe32 … #define GetBe64 … #define SetBe32 … #elif defined(MY_CPU_LE_UNALIGN) && ( \ (defined(__GNUC__) && (__GNUC__ > 4 || (__GNUC__ == 4 && __GNUC_MINOR__ >= 3))) \ || (defined(__clang__) && MY__has_builtin(__builtin_bswap16)) ) /* #define GetBe16(p) __builtin_bswap16(*(const UInt16 *)(const void *)(p)) */ #define GetBe32 … #define GetBe64 … #define SetBe32 … #else #define GetBe32(p) … #define GetBe64(p) … #define SetBe32(p, v) … #endif #ifndef GetBe16 #define GetBe16(p) … #endif #ifdef MY_CPU_X86_OR_AMD64 Cx86cpuid; enum { … }; void MyCPUID(UInt32 function, UInt32 *a, UInt32 *b, UInt32 *c, UInt32 *d); BoolInt x86cpuid_CheckAndRead(Cx86cpuid *p); int x86cpuid_GetFirm(const Cx86cpuid *p); #define x86cpuid_GetFamily(ver) … #define x86cpuid_GetModel(ver) … #define x86cpuid_GetStepping(ver) … BoolInt CPU_Is_InOrder(void); BoolInt CPU_IsSupported_AES(void); BoolInt CPU_IsSupported_AVX2(void); BoolInt CPU_IsSupported_VAES_AVX2(void); BoolInt CPU_IsSupported_SSSE3(void); BoolInt CPU_IsSupported_SSE41(void); BoolInt CPU_IsSupported_SHA(void); BoolInt CPU_IsSupported_PageGB(void); #elif defined(MY_CPU_ARM_OR_ARM64) BoolInt CPU_IsSupported_CRC32(void); BoolInt CPU_IsSupported_NEON(void); #if defined(_WIN32) BoolInt CPU_IsSupported_CRYPTO(void); #define CPU_IsSupported_SHA1 … #define CPU_IsSupported_SHA2 … #define CPU_IsSupported_AES … #else BoolInt CPU_IsSupported_SHA1(void); BoolInt CPU_IsSupported_SHA2(void); BoolInt CPU_IsSupported_AES(void); #endif #endif #if defined(__APPLE__) int My_sysctlbyname_Get(const char *name, void *buf, size_t *bufSize); int My_sysctlbyname_Get_UInt32(const char *name, UInt32 *val); #endif EXTERN_C_END #endif
Codebase Browser
chromium