/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |* *| |* Machine Code Emitter *| |* *| |* Automatically generated file, do not edit! *| |* *| \*===----------------------------------------------------------------------===*/ uint64_t AArch64MCCodeEmitter::getBinaryCodeForInstr(const MCInst &MI, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const { … } #ifdef GET_OPERAND_BIT_OFFSET #undef GET_OPERAND_BIT_OFFSET uint32_t AArch64MCCodeEmitter::getOperandBitOffset(const MCInst &MI, unsigned OpNum, const MCSubtargetInfo &STI) const { switch (MI.getOpcode()) { case AArch64::AUTIA1716: case AArch64::AUTIA171615: case AArch64::AUTIASP: case AArch64::AUTIAZ: case AArch64::AUTIB1716: case AArch64::AUTIB171615: case AArch64::AUTIBSP: case AArch64::AUTIBZ: case AArch64::AXFLAG: case AArch64::BRB_IALL: case AArch64::BRB_INJ: case AArch64::CFINV: case AArch64::CHKFEAT: case AArch64::DRPS: case AArch64::ERET: case AArch64::ERETAA: case AArch64::ERETAB: case AArch64::GCSPOPCX: case AArch64::GCSPOPX: case AArch64::GCSPUSHX: case AArch64::PACIA1716: case AArch64::PACIA171615: case AArch64::PACIASP: case AArch64::PACIASPPC: case AArch64::PACIAZ: case AArch64::PACIB1716: case AArch64::PACIB171615: case AArch64::PACIBSP: case AArch64::PACIBSPPC: case AArch64::PACIBZ: case AArch64::PACM: case AArch64::PACNBIASPPC: case AArch64::PACNBIBSPPC: case AArch64::RETAA: case AArch64::RETAB: case AArch64::SB: case AArch64::SETFFR: case AArch64::TCOMMIT: case AArch64::TSB: case AArch64::XAFLAG: case AArch64::XPACLRI: case AArch64::ZERO_T: { break; } case AArch64::DSBnXS: { switch (OpNum) { case 0: // op: CRm return 10; } break; } case AArch64::CLREX: case AArch64::DMB: case AArch64::DSB: case AArch64::ISB: { switch (OpNum) { case 0: // op: CRm return 8; } break; } case AArch64::WHILEGE_CXX_B: case AArch64::WHILEGE_CXX_D: case AArch64::WHILEGE_CXX_H: case AArch64::WHILEGE_CXX_S: case AArch64::WHILEGT_CXX_B: case AArch64::WHILEGT_CXX_D: case AArch64::WHILEGT_CXX_H: case AArch64::WHILEGT_CXX_S: case AArch64::WHILEHI_CXX_B: case AArch64::WHILEHI_CXX_D: case AArch64::WHILEHI_CXX_H: case AArch64::WHILEHI_CXX_S: case AArch64::WHILEHS_CXX_B: case AArch64::WHILEHS_CXX_D: case AArch64::WHILEHS_CXX_H: case AArch64::WHILEHS_CXX_S: case AArch64::WHILELE_CXX_B: case AArch64::WHILELE_CXX_D: case AArch64::WHILELE_CXX_H: case AArch64::WHILELE_CXX_S: case AArch64::WHILELO_CXX_B: case AArch64::WHILELO_CXX_D: case AArch64::WHILELO_CXX_H: case AArch64::WHILELO_CXX_S: case AArch64::WHILELS_CXX_B: case AArch64::WHILELS_CXX_D: case AArch64::WHILELS_CXX_H: case AArch64::WHILELS_CXX_S: case AArch64::WHILELT_CXX_B: case AArch64::WHILELT_CXX_D: case AArch64::WHILELT_CXX_H: case AArch64::WHILELT_CXX_S: { switch (OpNum) { case 0: // op: PNd return 0; case 1: // op: Rn return 5; case 3: // op: vl return 13; case 2: // op: Rm return 16; } break; } case AArch64::PTRUE_C_B: case AArch64::PTRUE_C_D: case AArch64::PTRUE_C_H: case AArch64::PTRUE_C_S: { switch (OpNum) { case 0: // op: PNd return 0; } break; } case AArch64::PEXT_2PCI_B: case AArch64::PEXT_2PCI_D: case AArch64::PEXT_2PCI_H: case AArch64::PEXT_2PCI_S: case AArch64::PEXT_PCI_B: case AArch64::PEXT_PCI_D: case AArch64::PEXT_PCI_H: case AArch64::PEXT_PCI_S: { switch (OpNum) { case 0: // op: Pd return 0; case 1: // op: PNn return 5; case 2: // op: index return 8; } break; } case AArch64::BRKAS_PPzP: case AArch64::BRKA_PPzP: case AArch64::BRKBS_PPzP: case AArch64::BRKB_PPzP: { switch (OpNum) { case 0: // op: Pd return 0; case 1: // op: Pg return 10; case 2: // op: Pn return 5; } break; } case AArch64::CMPEQ_PPzZI_B: case AArch64::CMPEQ_PPzZI_D: case AArch64::CMPEQ_PPzZI_H: case AArch64::CMPEQ_PPzZI_S: case AArch64::CMPGE_PPzZI_B: case AArch64::CMPGE_PPzZI_D: case AArch64::CMPGE_PPzZI_H: case AArch64::CMPGE_PPzZI_S: case AArch64::CMPGT_PPzZI_B: case AArch64::CMPGT_PPzZI_D: case AArch64::CMPGT_PPzZI_H: case AArch64::CMPGT_PPzZI_S: case AArch64::CMPLE_PPzZI_B: case AArch64::CMPLE_PPzZI_D: case AArch64::CMPLE_PPzZI_H: case AArch64::CMPLE_PPzZI_S: case AArch64::CMPLT_PPzZI_B: case AArch64::CMPLT_PPzZI_D: case AArch64::CMPLT_PPzZI_H: case AArch64::CMPLT_PPzZI_S: case AArch64::CMPNE_PPzZI_B: case AArch64::CMPNE_PPzZI_D: case AArch64::CMPNE_PPzZI_H: case AArch64::CMPNE_PPzZI_S: { switch (OpNum) { case 0: // op: Pd return 0; case 1: // op: Pg return 10; case 2: // op: Zn return 5; case 3: // op: imm5 return 16; } break; } case AArch64::CMPHI_PPzZI_B: case AArch64::CMPHI_PPzZI_D: case AArch64::CMPHI_PPzZI_H: case AArch64::CMPHI_PPzZI_S: case AArch64::CMPHS_PPzZI_B: case AArch64::CMPHS_PPzZI_D: case AArch64::CMPHS_PPzZI_H: case AArch64::CMPHS_PPzZI_S: case AArch64::CMPLO_PPzZI_B: case AArch64::CMPLO_PPzZI_D: case AArch64::CMPLO_PPzZI_H: case AArch64::CMPLO_PPzZI_S: case AArch64::CMPLS_PPzZI_B: case AArch64::CMPLS_PPzZI_D: case AArch64::CMPLS_PPzZI_H: case AArch64::CMPLS_PPzZI_S: { switch (OpNum) { case 0: // op: Pd return 0; case 1: // op: Pg return 10; case 2: // op: Zn return 5; case 3: // op: imm7 return 14; } break; } case AArch64::FCMEQ_PPzZ0_D: case AArch64::FCMEQ_PPzZ0_H: case AArch64::FCMEQ_PPzZ0_S: case AArch64::FCMGE_PPzZ0_D: case AArch64::FCMGE_PPzZ0_H: case AArch64::FCMGE_PPzZ0_S: case AArch64::FCMGT_PPzZ0_D: case AArch64::FCMGT_PPzZ0_H: case AArch64::FCMGT_PPzZ0_S: case AArch64::FCMLE_PPzZ0_D: case AArch64::FCMLE_PPzZ0_H: case AArch64::FCMLE_PPzZ0_S: case AArch64::FCMLT_PPzZ0_D: case AArch64::FCMLT_PPzZ0_H: case AArch64::FCMLT_PPzZ0_S: case AArch64::FCMNE_PPzZ0_D: case AArch64::FCMNE_PPzZ0_H: case AArch64::FCMNE_PPzZ0_S: { switch (OpNum) { case 0: // op: Pd return 0; case 1: // op: Pg return 10; case 2: // op: Zn return 5; } break; } case AArch64::ANDS_PPzPP: case AArch64::AND_PPzPP: case AArch64::BICS_PPzPP: case AArch64::BIC_PPzPP: case AArch64::BRKPAS_PPzPP: case AArch64::BRKPA_PPzPP: case AArch64::BRKPBS_PPzPP: case AArch64::BRKPB_PPzPP: case AArch64::EORS_PPzPP: case AArch64::EOR_PPzPP: case AArch64::NANDS_PPzPP: case AArch64::NAND_PPzPP: case AArch64::NORS_PPzPP: case AArch64::NOR_PPzPP: case AArch64::ORNS_PPzPP: case AArch64::ORN_PPzPP: case AArch64::ORRS_PPzPP: case AArch64::ORR_PPzPP: case AArch64::SEL_PPPP: { switch (OpNum) { case 0: // op: Pd return 0; case 1: // op: Pg return 10; case 3: // op: Pm return 16; case 2: // op: Pn return 5; } break; } case AArch64::CMPEQ_PPzZZ_B: case AArch64::CMPEQ_PPzZZ_D: case AArch64::CMPEQ_PPzZZ_H: case AArch64::CMPEQ_PPzZZ_S: case AArch64::CMPEQ_WIDE_PPzZZ_B: case AArch64::CMPEQ_WIDE_PPzZZ_H: case AArch64::CMPEQ_WIDE_PPzZZ_S: case AArch64::CMPGE_PPzZZ_B: case AArch64::CMPGE_PPzZZ_D: case AArch64::CMPGE_PPzZZ_H: case AArch64::CMPGE_PPzZZ_S: case AArch64::CMPGE_WIDE_PPzZZ_B: case AArch64::CMPGE_WIDE_PPzZZ_H: case AArch64::CMPGE_WIDE_PPzZZ_S: case AArch64::CMPGT_PPzZZ_B: case AArch64::CMPGT_PPzZZ_D: case AArch64::CMPGT_PPzZZ_H: case AArch64::CMPGT_PPzZZ_S: case AArch64::CMPGT_WIDE_PPzZZ_B: case AArch64::CMPGT_WIDE_PPzZZ_H: case AArch64::CMPGT_WIDE_PPzZZ_S: case AArch64::CMPHI_PPzZZ_B: case AArch64::CMPHI_PPzZZ_D: case AArch64::CMPHI_PPzZZ_H: case AArch64::CMPHI_PPzZZ_S: case AArch64::CMPHI_WIDE_PPzZZ_B: case AArch64::CMPHI_WIDE_PPzZZ_H: case AArch64::CMPHI_WIDE_PPzZZ_S: case AArch64::CMPHS_PPzZZ_B: case AArch64::CMPHS_PPzZZ_D: case AArch64::CMPHS_PPzZZ_H: case AArch64::CMPHS_PPzZZ_S: case AArch64::CMPHS_WIDE_PPzZZ_B: case AArch64::CMPHS_WIDE_PPzZZ_H: case AArch64::CMPHS_WIDE_PPzZZ_S: case AArch64::CMPLE_WIDE_PPzZZ_B: case AArch64::CMPLE_WIDE_PPzZZ_H: case AArch64::CMPLE_WIDE_PPzZZ_S: case AArch64::CMPLO_WIDE_PPzZZ_B: case AArch64::CMPLO_WIDE_PPzZZ_H: case AArch64::CMPLO_WIDE_PPzZZ_S: case AArch64::CMPLS_WIDE_PPzZZ_B: case AArch64::CMPLS_WIDE_PPzZZ_H: case AArch64::CMPLS_WIDE_PPzZZ_S: case AArch64::CMPLT_WIDE_PPzZZ_B: case AArch64::CMPLT_WIDE_PPzZZ_H: case AArch64::CMPLT_WIDE_PPzZZ_S: case AArch64::CMPNE_PPzZZ_B: case AArch64::CMPNE_PPzZZ_D: case AArch64::CMPNE_PPzZZ_H: case AArch64::CMPNE_PPzZZ_S: case AArch64::CMPNE_WIDE_PPzZZ_B: case AArch64::CMPNE_WIDE_PPzZZ_H: case AArch64::CMPNE_WIDE_PPzZZ_S: case AArch64::FACGE_PPzZZ_D: case AArch64::FACGE_PPzZZ_H: case AArch64::FACGE_PPzZZ_S: case AArch64::FACGT_PPzZZ_D: case AArch64::FACGT_PPzZZ_H: case AArch64::FACGT_PPzZZ_S: case AArch64::FCMEQ_PPzZZ_D: case AArch64::FCMEQ_PPzZZ_H: case AArch64::FCMEQ_PPzZZ_S: case AArch64::FCMGE_PPzZZ_D: case AArch64::FCMGE_PPzZZ_H: case AArch64::FCMGE_PPzZZ_S: case AArch64::FCMGT_PPzZZ_D: case AArch64::FCMGT_PPzZZ_H: case AArch64::FCMGT_PPzZZ_S: case AArch64::FCMNE_PPzZZ_D: case AArch64::FCMNE_PPzZZ_H: case AArch64::FCMNE_PPzZZ_S: case AArch64::FCMUO_PPzZZ_D: case AArch64::FCMUO_PPzZZ_H: case AArch64::FCMUO_PPzZZ_S: case AArch64::MATCH_PPzZZ_B: case AArch64::MATCH_PPzZZ_H: case AArch64::NMATCH_PPzZZ_B: case AArch64::NMATCH_PPzZZ_H: { switch (OpNum) { case 0: // op: Pd return 0; case 1: // op: Pg return 10; case 3: // op: Zm return 16; case 2: // op: Zn return 5; } break; } case AArch64::RDFFRS_PPz: case AArch64::RDFFR_PPz: { switch (OpNum) { case 0: // op: Pd return 0; case 1: // op: Pg return 5; } break; } case AArch64::PUNPKHI_PP: case AArch64::PUNPKLO_PP: case AArch64::REV_PP_B: case AArch64::REV_PP_D: case AArch64::REV_PP_H: case AArch64::REV_PP_S: { switch (OpNum) { case 0: // op: Pd return 0; case 1: // op: Pn return 5; } break; } case AArch64::PMOV_PZI_D: case AArch64::PMOV_PZI_H: case AArch64::PMOV_PZI_S: { switch (OpNum) { case 0: // op: Pd return 0; case 1: // op: Zn return 5; case 2: // op: index return 17; } break; } case AArch64::PMOV_PZI_B: { switch (OpNum) { case 0: // op: Pd return 0; case 1: // op: Zn return 5; } break; } case AArch64::PTRUES_B: case AArch64::PTRUES_D: case AArch64::PTRUES_H: case AArch64::PTRUES_S: case AArch64::PTRUE_B: case AArch64::PTRUE_D: case AArch64::PTRUE_H: case AArch64::PTRUE_S: { switch (OpNum) { case 0: // op: Pd return 0; case 1: // op: pattern return 5; } break; } case AArch64::BRKA_PPmP: case AArch64::BRKB_PPmP: { switch (OpNum) { case 0: // op: Pd return 0; case 2: // op: Pg return 10; case 3: // op: Pn return 5; } break; } case AArch64::TRN1_PPP_B: case AArch64::TRN1_PPP_D: case AArch64::TRN1_PPP_H: case AArch64::TRN1_PPP_S: case AArch64::TRN2_PPP_B: case AArch64::TRN2_PPP_D: case AArch64::TRN2_PPP_H: case AArch64::TRN2_PPP_S: case AArch64::UZP1_PPP_B: case AArch64::UZP1_PPP_D: case AArch64::UZP1_PPP_H: case AArch64::UZP1_PPP_S: case AArch64::UZP2_PPP_B: case AArch64::UZP2_PPP_D: case AArch64::UZP2_PPP_H: case AArch64::UZP2_PPP_S: case AArch64::ZIP1_PPP_B: case AArch64::ZIP1_PPP_D: case AArch64::ZIP1_PPP_H: case AArch64::ZIP1_PPP_S: case AArch64::ZIP2_PPP_B: case AArch64::ZIP2_PPP_D: case AArch64::ZIP2_PPP_H: case AArch64::ZIP2_PPP_S: { switch (OpNum) { case 0: // op: Pd return 0; case 2: // op: Pm return 16; case 1: // op: Pn return 5; } break; } case AArch64::WHILEGE_PWW_B: case AArch64::WHILEGE_PWW_D: case AArch64::WHILEGE_PWW_H: case AArch64::WHILEGE_PWW_S: case AArch64::WHILEGE_PXX_B: case AArch64::WHILEGE_PXX_D: case AArch64::WHILEGE_PXX_H: case AArch64::WHILEGE_PXX_S: case AArch64::WHILEGT_PWW_B: case AArch64::WHILEGT_PWW_D: case AArch64::WHILEGT_PWW_H: case AArch64::WHILEGT_PWW_S: case AArch64::WHILEGT_PXX_B: case AArch64::WHILEGT_PXX_D: case AArch64::WHILEGT_PXX_H: case AArch64::WHILEGT_PXX_S: case AArch64::WHILEHI_PWW_B: case AArch64::WHILEHI_PWW_D: case AArch64::WHILEHI_PWW_H: case AArch64::WHILEHI_PWW_S: case AArch64::WHILEHI_PXX_B: case AArch64::WHILEHI_PXX_D: case AArch64::WHILEHI_PXX_H: case AArch64::WHILEHI_PXX_S: case AArch64::WHILEHS_PWW_B: case AArch64::WHILEHS_PWW_D: case AArch64::WHILEHS_PWW_H: case AArch64::WHILEHS_PWW_S: case AArch64::WHILEHS_PXX_B: case AArch64::WHILEHS_PXX_D: case AArch64::WHILEHS_PXX_H: case AArch64::WHILEHS_PXX_S: case AArch64::WHILELE_PWW_B: case AArch64::WHILELE_PWW_D: case AArch64::WHILELE_PWW_H: case AArch64::WHILELE_PWW_S: case AArch64::WHILELE_PXX_B: case AArch64::WHILELE_PXX_D: case AArch64::WHILELE_PXX_H: case AArch64::WHILELE_PXX_S: case AArch64::WHILELO_PWW_B: case AArch64::WHILELO_PWW_D: case AArch64::WHILELO_PWW_H: case AArch64::WHILELO_PWW_S: case AArch64::WHILELO_PXX_B: case AArch64::WHILELO_PXX_D: case AArch64::WHILELO_PXX_H: case AArch64::WHILELO_PXX_S: case AArch64::WHILELS_PWW_B: case AArch64::WHILELS_PWW_D: case AArch64::WHILELS_PWW_H: case AArch64::WHILELS_PWW_S: case AArch64::WHILELS_PXX_B: case AArch64::WHILELS_PXX_D: case AArch64::WHILELS_PXX_H: case AArch64::WHILELS_PXX_S: case AArch64::WHILELT_PWW_B: case AArch64::WHILELT_PWW_D: case AArch64::WHILELT_PWW_H: case AArch64::WHILELT_PWW_S: case AArch64::WHILELT_PXX_B: case AArch64::WHILELT_PXX_D: case AArch64::WHILELT_PXX_H: case AArch64::WHILELT_PXX_S: case AArch64::WHILERW_PXX_B: case AArch64::WHILERW_PXX_D: case AArch64::WHILERW_PXX_H: case AArch64::WHILERW_PXX_S: case AArch64::WHILEWR_PXX_B: case AArch64::WHILEWR_PXX_D: case AArch64::WHILEWR_PXX_H: case AArch64::WHILEWR_PXX_S: { switch (OpNum) { case 0: // op: Pd return 0; case 2: // op: Rm return 16; case 1: // op: Rn return 5; } break; } case AArch64::PFALSE: case AArch64::RDFFR_P: { switch (OpNum) { case 0: // op: Pd return 0; } break; } case AArch64::WHILEGE_2PXX_B: case AArch64::WHILEGE_2PXX_D: case AArch64::WHILEGE_2PXX_H: case AArch64::WHILEGE_2PXX_S: case AArch64::WHILEGT_2PXX_B: case AArch64::WHILEGT_2PXX_D: case AArch64::WHILEGT_2PXX_H: case AArch64::WHILEGT_2PXX_S: case AArch64::WHILEHI_2PXX_B: case AArch64::WHILEHI_2PXX_D: case AArch64::WHILEHI_2PXX_H: case AArch64::WHILEHI_2PXX_S: case AArch64::WHILEHS_2PXX_B: case AArch64::WHILEHS_2PXX_D: case AArch64::WHILEHS_2PXX_H: case AArch64::WHILEHS_2PXX_S: case AArch64::WHILELE_2PXX_B: case AArch64::WHILELE_2PXX_D: case AArch64::WHILELE_2PXX_H: case AArch64::WHILELE_2PXX_S: case AArch64::WHILELO_2PXX_B: case AArch64::WHILELO_2PXX_D: case AArch64::WHILELO_2PXX_H: case AArch64::WHILELO_2PXX_S: case AArch64::WHILELS_2PXX_B: case AArch64::WHILELS_2PXX_D: case AArch64::WHILELS_2PXX_H: case AArch64::WHILELS_2PXX_S: case AArch64::WHILELT_2PXX_B: case AArch64::WHILELT_2PXX_D: case AArch64::WHILELT_2PXX_H: case AArch64::WHILELT_2PXX_S: { switch (OpNum) { case 0: // op: Pd return 1; case 1: // op: Rn return 5; case 2: // op: Rm return 16; } break; } case AArch64::BRKNS_PPzP: case AArch64::BRKN_PPzP: { switch (OpNum) { case 0: // op: Pdm return 0; case 1: // op: Pg return 10; case 2: // op: Pn return 5; } break; } case AArch64::PFIRST_B: case AArch64::PNEXT_B: case AArch64::PNEXT_D: case AArch64::PNEXT_H: case AArch64::PNEXT_S: { switch (OpNum) { case 0: // op: Pdn return 0; case 1: // op: Pg return 5; } break; } case AArch64::PTEST_PP: { switch (OpNum) { case 0: // op: Pg return 10; case 1: // op: Pn return 5; } break; } case AArch64::WRFFR: { switch (OpNum) { case 0: // op: Pn return 5; } break; } case AArch64::LDR_PXI: case AArch64::STR_PXI: { switch (OpNum) { case 0: // op: Pt return 0; case 1: // op: Rn return 5; case 2: // op: imm9 return 10; } break; } case AArch64::CNTP_XCI_B: case AArch64::CNTP_XCI_D: case AArch64::CNTP_XCI_H: case AArch64::CNTP_XCI_S: { switch (OpNum) { case 0: // op: Rd return 0; case 1: // op: PNn return 5; case 2: // op: vl return 10; } break; } case AArch64::ADDPL_XXI: case AArch64::ADDSPL_XXI: case AArch64::ADDSVL_XXI: case AArch64::ADDVL_XXI: { switch (OpNum) { case 0: // op: Rd return 0; case 1: // op: Rn return 16; case 2: // op: imm6 return 5; } break; } case AArch64::FMADDDrrr: case AArch64::FMADDHrrr: case AArch64::FMADDSrrr: case AArch64::FMSUBDrrr: case AArch64::FMSUBHrrr: case AArch64::FMSUBSrrr: case AArch64::FNMADDDrrr: case AArch64::FNMADDHrrr: case AArch64::FNMADDSrrr: case AArch64::FNMSUBDrrr: case AArch64::FNMSUBHrrr: case AArch64::FNMSUBSrrr: case AArch64::MADDPT: case AArch64::MADDWrrr: case AArch64::MADDXrrr: case AArch64::MSUBPT: case AArch64::MSUBWrrr: case AArch64::MSUBXrrr: case AArch64::SMADDLrrr: case AArch64::SMSUBLrrr: case AArch64::UMADDLrrr: case AArch64::UMSUBLrrr: { switch (OpNum) { case 0: // op: Rd return 0; case 1: // op: Rn return 5; case 2: // op: Rm return 16; case 3: // op: Ra return 10; } break; } case AArch64::CSELWr: case AArch64::CSELXr: case AArch64::CSINCWr: case AArch64::CSINCXr: case AArch64::CSINVWr: case AArch64::CSINVXr: case AArch64::CSNEGWr: case AArch64::CSNEGXr: case AArch64::FCSELDrrr: case AArch64::FCSELHrrr: case AArch64::FCSELSrrr: { switch (OpNum) { case 0: // op: Rd return 0; case 1: // op: Rn return 5; case 2: // op: Rm return 16; case 3: // op: cond return 12; } break; } case AArch64::ADDSXrx64: case AArch64::ADDXrx64: case AArch64::SUBSXrx64: case AArch64::SUBXrx64: { switch (OpNum) { case 0: // op: Rd return 0; case 1: // op: Rn return 5; case 2: // op: Rm return 16; case 3: // op: ext return 10; } break; } case AArch64::ADDSWrx: case AArch64::ADDSXrx: case AArch64::ADDWrx: case AArch64::ADDXrx: case AArch64::SUBSWrx: case AArch64::SUBSXrx: case AArch64::SUBWrx: case AArch64::SUBXrx: { switch (OpNum) { case 0: // op: Rd return 0; case 1: // op: Rn return 5; case 2: // op: Rm return 16; case 3: // op: extend return 10; } break; } case AArch64::FMULXv1i16_indexed: case AArch64::FMULXv1i32_indexed: case AArch64::FMULXv1i64_indexed: case AArch64::FMULXv2i32_indexed: case AArch64::FMULXv2i64_indexed: case AArch64::FMULXv4i16_indexed: case AArch64::FMULXv4i32_indexed: case AArch64::FMULXv8i16_indexed: case AArch64::FMULv1i16_indexed: case AArch64::FMULv1i32_indexed: case AArch64::FMULv1i64_indexed: case AArch64::FMULv2i32_indexed: case AArch64::FMULv2i64_indexed: case AArch64::FMULv4i16_indexed: case AArch64::FMULv4i32_indexed: case AArch64::FMULv8i16_indexed: case AArch64::MULv2i32_indexed: case AArch64::MULv4i16_indexed: case AArch64::MULv4i32_indexed: case AArch64::MULv8i16_indexed: case AArch64::SMULLv2i32_indexed: case AArch64::SMULLv4i16_indexed: case AArch64::SMULLv4i32_indexed: case AArch64::SMULLv8i16_indexed: case AArch64::SQDMULHv1i16_indexed: case AArch64::SQDMULHv1i32_indexed: case AArch64::SQDMULHv2i32_indexed: case AArch64::SQDMULHv4i16_indexed: case AArch64::SQDMULHv4i32_indexed: case AArch64::SQDMULHv8i16_indexed: case AArch64::SQDMULLv1i32_indexed: case AArch64::SQDMULLv1i64_indexed: case AArch64::SQDMULLv2i32_indexed: case AArch64::SQDMULLv4i16_indexed: case AArch64::SQDMULLv4i32_indexed: case AArch64::SQDMULLv8i16_indexed: case AArch64::SQRDMULHv1i16_indexed: case AArch64::SQRDMULHv1i32_indexed: case AArch64::SQRDMULHv2i32_indexed: case AArch64::SQRDMULHv4i16_indexed: case AArch64::SQRDMULHv4i32_indexed: case AArch64::SQRDMULHv8i16_indexed: case AArch64::UMULLv2i32_indexed: case AArch64::UMULLv4i16_indexed: case AArch64::UMULLv4i32_indexed: case AArch64::UMULLv8i16_indexed: { switch (OpNum) { case 0: // op: Rd return 0; case 1: // op: Rn return 5; case 2: // op: Rm return 16; case 3: // op: idx return 11; } break; } case AArch64::LUT2v8f16: { switch (OpNum) { case 0: // op: Rd return 0; case 1: // op: Rn return 5; case 2: // op: Rm return 16; case 3: // op: idx return 12; } break; } case AArch64::LUT2v16f8: case AArch64::LUT4v8f16: { switch (OpNum) { case 0: // op: Rd return 0; case 1: // op: Rn return 5; case 2: // op: Rm return 16; case 3: // op: idx return 13; } break; } case AArch64::LUT4v16f8: { switch (OpNum) { case 0: // op: Rd return 0; case 1: // op: Rn return 5; case 2: // op: Rm return 16; case 3: // op: idx return 14; } break; } case AArch64::EXTRWrri: case AArch64::EXTRXrri: { switch (OpNum) { case 0: // op: Rd return 0; case 1: // op: Rn return 5; case 2: // op: Rm return 16; case 3: // op: imm return 10; } break; } case AArch64::EXTv8i8: case AArch64::EXTv16i8: { switch (OpNum) { case 0: // op: Rd return 0; case 1: // op: Rn return 5; case 2: // op: Rm return 16; case 3: // op: imm return 11; } break; } case AArch64::FCADDv2f32: case AArch64::FCADDv2f64: case AArch64::FCADDv4f16: case AArch64::FCADDv4f32: case AArch64::FCADDv8f16: { switch (OpNum) { case 0: // op: Rd return 0; case 1: // op: Rn return 5; case 2: // op: Rm return 16; case 3: // op: rot return 12; } break; } case AArch64::ADDSWrs: case AArch64::ADDSXrs: case AArch64::ADDWrs: case AArch64::ADDXrs: case AArch64::ANDSWrs: case AArch64::ANDSXrs: case AArch64::ANDWrs: case AArch64::ANDXrs: case AArch64::BICSWrs: case AArch64::BICSXrs: case AArch64::BICWrs: case AArch64::BICXrs: case AArch64::EONWrs: case AArch64::EONXrs: case AArch64::EORWrs: case AArch64::EORXrs: case AArch64::ORNWrs: case AArch64::ORNXrs: case AArch64::ORRWrs: case AArch64::ORRXrs: case AArch64::SUBSWrs: case AArch64::SUBSXrs: case AArch64::SUBWrs: case AArch64::SUBXrs: { switch (OpNum) { case 0: // op: Rd return 0; case 1: // op: Rn return 5; case 2: // op: Rm return 16; case 3: // op: shift return 10; } break; } case AArch64::ADDPT_shift: case AArch64::SUBPT_shift: { switch (OpNum) { case 0: // op: Rd return 0; case 1: // op: Rn return 5; case 2: // op: Rm return 16; case 3: // op: shift_imm return 10; } break; } case AArch64::ADCSWr: case AArch64::ADCSXr: case AArch64::ADCWr: case AArch64::ADCXr: case AArch64::ADDHNv2i64_v2i32: case AArch64::ADDHNv4i32_v4i16: case AArch64::ADDHNv8i16_v8i8: case AArch64::ADDPv2i32: case AArch64::ADDPv2i64: case AArch64::ADDPv4i16: case AArch64::ADDPv4i32: case AArch64::ADDPv8i8: case AArch64::ADDPv8i16: case AArch64::ADDPv16i8: case AArch64::ADDv1i64: case AArch64::ADDv2i32: case AArch64::ADDv2i64: case AArch64::ADDv4i16: case AArch64::ADDv4i32: case AArch64::ADDv8i8: case AArch64::ADDv8i16: case AArch64::ADDv16i8: case AArch64::ANDv8i8: case AArch64::ANDv16i8: case AArch64::ASRVWr: case AArch64::ASRVXr: case AArch64::BICv8i8: case AArch64::BICv16i8: case AArch64::CMEQv1i64: case AArch64::CMEQv2i32: case AArch64::CMEQv2i64: case AArch64::CMEQv4i16: case AArch64::CMEQv4i32: case AArch64::CMEQv8i8: case AArch64::CMEQv8i16: case AArch64::CMEQv16i8: case AArch64::CMGEv1i64: case AArch64::CMGEv2i32: case AArch64::CMGEv2i64: case AArch64::CMGEv4i16: case AArch64::CMGEv4i32: case AArch64::CMGEv8i8: case AArch64::CMGEv8i16: case AArch64::CMGEv16i8: case AArch64::CMGTv1i64: case AArch64::CMGTv2i32: case AArch64::CMGTv2i64: case AArch64::CMGTv4i16: case AArch64::CMGTv4i32: case AArch64::CMGTv8i8: case AArch64::CMGTv8i16: case AArch64::CMGTv16i8: case AArch64::CMHIv1i64: case AArch64::CMHIv2i32: case AArch64::CMHIv2i64: case AArch64::CMHIv4i16: case AArch64::CMHIv4i32: case AArch64::CMHIv8i8: case AArch64::CMHIv8i16: case AArch64::CMHIv16i8: case AArch64::CMHSv1i64: case AArch64::CMHSv2i32: case AArch64::CMHSv2i64: case AArch64::CMHSv4i16: case AArch64::CMHSv4i32: case AArch64::CMHSv8i8: case AArch64::CMHSv8i16: case AArch64::CMHSv16i8: case AArch64::CMTSTv1i64: case AArch64::CMTSTv2i32: case AArch64::CMTSTv2i64: case AArch64::CMTSTv4i16: case AArch64::CMTSTv4i32: case AArch64::CMTSTv8i8: case AArch64::CMTSTv8i16: case AArch64::CMTSTv16i8: case AArch64::CRC32Brr: case AArch64::CRC32CBrr: case AArch64::CRC32CHrr: case AArch64::CRC32CWrr: case AArch64::CRC32CXrr: case AArch64::CRC32Hrr: case AArch64::CRC32Wrr: case AArch64::CRC32Xrr: case AArch64::EORv8i8: case AArch64::EORv16i8: case AArch64::FABD16: case AArch64::FABD32: case AArch64::FABD64: case AArch64::FABDv2f32: case AArch64::FABDv2f64: case AArch64::FABDv4f16: case AArch64::FABDv4f32: case AArch64::FABDv8f16: case AArch64::FACGE16: case AArch64::FACGE32: case AArch64::FACGE64: case AArch64::FACGEv2f32: case AArch64::FACGEv2f64: case AArch64::FACGEv4f16: case AArch64::FACGEv4f32: case AArch64::FACGEv8f16: case AArch64::FACGT16: case AArch64::FACGT32: case AArch64::FACGT64: case AArch64::FACGTv2f32: case AArch64::FACGTv2f64: case AArch64::FACGTv4f16: case AArch64::FACGTv4f32: case AArch64::FACGTv8f16: case AArch64::FADDDrr: case AArch64::FADDHrr: case AArch64::FADDPv2f32: case AArch64::FADDPv2f64: case AArch64::FADDPv4f16: case AArch64::FADDPv4f32: case AArch64::FADDPv8f16: case AArch64::FADDSrr: case AArch64::FADDv2f32: case AArch64::FADDv2f64: case AArch64::FADDv4f16: case AArch64::FADDv4f32: case AArch64::FADDv8f16: case AArch64::FAMAXv2f32: case AArch64::FAMAXv2f64: case AArch64::FAMAXv4f16: case AArch64::FAMAXv4f32: case AArch64::FAMAXv8f16: case AArch64::FAMINv2f32: case AArch64::FAMINv2f64: case AArch64::FAMINv4f16: case AArch64::FAMINv4f32: case AArch64::FAMINv8f16: case AArch64::FCMEQ16: case AArch64::FCMEQ32: case AArch64::FCMEQ64: case AArch64::FCMEQv2f32: case AArch64::FCMEQv2f64: case AArch64::FCMEQv4f16: case AArch64::FCMEQv4f32: case AArch64::FCMEQv8f16: case AArch64::FCMGE16: case AArch64::FCMGE32: case AArch64::FCMGE64: case AArch64::FCMGEv2f32: case AArch64::FCMGEv2f64: case AArch64::FCMGEv4f16: case AArch64::FCMGEv4f32: case AArch64::FCMGEv8f16: case AArch64::FCMGT16: case AArch64::FCMGT32: case AArch64::FCMGT64: case AArch64::FCMGTv2f32: case AArch64::FCMGTv2f64: case AArch64::FCMGTv4f16: case AArch64::FCMGTv4f32: case AArch64::FCMGTv8f16: case AArch64::FCVTN_F16_F8v8f8: case AArch64::FCVTN_F16_F8v16f8: case AArch64::FCVTN_F32_F8v8f8: case AArch64::FDIVDrr: case AArch64::FDIVHrr: case AArch64::FDIVSrr: case AArch64::FDIVv2f32: case AArch64::FDIVv2f64: case AArch64::FDIVv4f16: case AArch64::FDIVv4f32: case AArch64::FDIVv8f16: case AArch64::FMAXDrr: case AArch64::FMAXHrr: case AArch64::FMAXNMDrr: case AArch64::FMAXNMHrr: case AArch64::FMAXNMPv2f32: case AArch64::FMAXNMPv2f64: case AArch64::FMAXNMPv4f16: case AArch64::FMAXNMPv4f32: case AArch64::FMAXNMPv8f16: case AArch64::FMAXNMSrr: case AArch64::FMAXNMv2f32: case AArch64::FMAXNMv2f64: case AArch64::FMAXNMv4f16: case AArch64::FMAXNMv4f32: case AArch64::FMAXNMv8f16: case AArch64::FMAXPv2f32: case AArch64::FMAXPv2f64: case AArch64::FMAXPv4f16: case AArch64::FMAXPv4f32: case AArch64::FMAXPv8f16: case AArch64::FMAXSrr: case AArch64::FMAXv2f32: case AArch64::FMAXv2f64: case AArch64::FMAXv4f16: case AArch64::FMAXv4f32: case AArch64::FMAXv8f16: case AArch64::FMINDrr: case AArch64::FMINHrr: case AArch64::FMINNMDrr: case AArch64::FMINNMHrr: case AArch64::FMINNMPv2f32: case AArch64::FMINNMPv2f64: case AArch64::FMINNMPv4f16: case AArch64::FMINNMPv4f32: case AArch64::FMINNMPv8f16: case AArch64::FMINNMSrr: case AArch64::FMINNMv2f32: case AArch64::FMINNMv2f64: case AArch64::FMINNMv4f16: case AArch64::FMINNMv4f32: case AArch64::FMINNMv8f16: case AArch64::FMINPv2f32: case AArch64::FMINPv2f64: case AArch64::FMINPv4f16: case AArch64::FMINPv4f32: case AArch64::FMINPv8f16: case AArch64::FMINSrr: case AArch64::FMINv2f32: case AArch64::FMINv2f64: case AArch64::FMINv4f16: case AArch64::FMINv4f32: case AArch64::FMINv8f16: case AArch64::FMULDrr: case AArch64::FMULHrr: case AArch64::FMULSrr: case AArch64::FMULX16: case AArch64::FMULX32: case AArch64::FMULX64: case AArch64::FMULXv2f32: case AArch64::FMULXv2f64: case AArch64::FMULXv4f16: case AArch64::FMULXv4f32: case AArch64::FMULXv8f16: case AArch64::FMULv2f32: case AArch64::FMULv2f64: case AArch64::FMULv4f16: case AArch64::FMULv4f32: case AArch64::FMULv8f16: case AArch64::FNMULDrr: case AArch64::FNMULHrr: case AArch64::FNMULSrr: case AArch64::FRECPS16: case AArch64::FRECPS32: case AArch64::FRECPS64: case AArch64::FRECPSv2f32: case AArch64::FRECPSv2f64: case AArch64::FRECPSv4f16: case AArch64::FRECPSv4f32: case AArch64::FRECPSv8f16: case AArch64::FRSQRTS16: case AArch64::FRSQRTS32: case AArch64::FRSQRTS64: case AArch64::FRSQRTSv2f32: case AArch64::FRSQRTSv2f64: case AArch64::FRSQRTSv4f16: case AArch64::FRSQRTSv4f32: case AArch64::FRSQRTSv8f16: case AArch64::FSCALEv2f32: case AArch64::FSCALEv2f64: case AArch64::FSCALEv4f16: case AArch64::FSCALEv4f32: case AArch64::FSCALEv8f16: case AArch64::FSUBDrr: case AArch64::FSUBHrr: case AArch64::FSUBSrr: case AArch64::FSUBv2f32: case AArch64::FSUBv2f64: case AArch64::FSUBv4f16: case AArch64::FSUBv4f32: case AArch64::FSUBv8f16: case AArch64::GMI: case AArch64::IRG: case AArch64::LSLVWr: case AArch64::LSLVXr: case AArch64::LSRVWr: case AArch64::LSRVXr: case AArch64::MULv2i32: case AArch64::MULv4i16: case AArch64::MULv4i32: case AArch64::MULv8i8: case AArch64::MULv8i16: case AArch64::MULv16i8: case AArch64::ORNv8i8: case AArch64::ORNv16i8: case AArch64::ORRv8i8: case AArch64::ORRv16i8: case AArch64::PACGA: case AArch64::PMULLv1i64: case AArch64::PMULLv2i64: case AArch64::PMULLv8i8: case AArch64::PMULLv16i8: case AArch64::PMULv8i8: case AArch64::PMULv16i8: case AArch64::RADDHNv2i64_v2i32: case AArch64::RADDHNv4i32_v4i16: case AArch64::RADDHNv8i16_v8i8: case AArch64::RORVWr: case AArch64::RORVXr: case AArch64::RSUBHNv2i64_v2i32: case AArch64::RSUBHNv4i32_v4i16: case AArch64::RSUBHNv8i16_v8i8: case AArch64::SABDLv2i32_v2i64: case AArch64::SABDLv4i16_v4i32: case AArch64::SABDLv4i32_v2i64: case AArch64::SABDLv8i8_v8i16: case AArch64::SABDLv8i16_v4i32: case AArch64::SABDLv16i8_v8i16: case AArch64::SABDv2i32: case AArch64::SABDv4i16: case AArch64::SABDv4i32: case AArch64::SABDv8i8: case AArch64::SABDv8i16: case AArch64::SABDv16i8: case AArch64::SADDLv2i32_v2i64: case AArch64::SADDLv4i16_v4i32: case AArch64::SADDLv4i32_v2i64: case AArch64::SADDLv8i8_v8i16: case AArch64::SADDLv8i16_v4i32: case AArch64::SADDLv16i8_v8i16: case AArch64::SADDWv2i32_v2i64: case AArch64::SADDWv4i16_v4i32: case AArch64::SADDWv4i32_v2i64: case AArch64::SADDWv8i8_v8i16: case AArch64::SADDWv8i16_v4i32: case AArch64::SADDWv16i8_v8i16: case AArch64::SBCSWr: case AArch64::SBCSXr: case AArch64::SBCWr: case AArch64::SBCXr: case AArch64::SDIVWr: case AArch64::SDIVXr: case AArch64::SHADDv2i32: case AArch64::SHADDv4i16: case AArch64::SHADDv4i32: case AArch64::SHADDv8i8: case AArch64::SHADDv8i16: case AArch64::SHADDv16i8: case AArch64::SHSUBv2i32: case AArch64::SHSUBv4i16: case AArch64::SHSUBv4i32: case AArch64::SHSUBv8i8: case AArch64::SHSUBv8i16: case AArch64::SHSUBv16i8: case AArch64::SMAXPv2i32: case AArch64::SMAXPv4i16: case AArch64::SMAXPv4i32: case AArch64::SMAXPv8i8: case AArch64::SMAXPv8i16: case AArch64::SMAXPv16i8: case AArch64::SMAXWrr: case AArch64::SMAXXrr: case AArch64::SMAXv2i32: case AArch64::SMAXv4i16: case AArch64::SMAXv4i32: case AArch64::SMAXv8i8: case AArch64::SMAXv8i16: case AArch64::SMAXv16i8: case AArch64::SMINPv2i32: case AArch64::SMINPv4i16: case AArch64::SMINPv4i32: case AArch64::SMINPv8i8: case AArch64::SMINPv8i16: case AArch64::SMINPv16i8: case AArch64::SMINWrr: case AArch64::SMINXrr: case AArch64::SMINv2i32: case AArch64::SMINv4i16: case AArch64::SMINv4i32: case AArch64::SMINv8i8: case AArch64::SMINv8i16: case AArch64::SMINv16i8: case AArch64::SMULHrr: case AArch64::SMULLv2i32_v2i64: case AArch64::SMULLv4i16_v4i32: case AArch64::SMULLv4i32_v2i64: case AArch64::SMULLv8i8_v8i16: case AArch64::SMULLv8i16_v4i32: case AArch64::SMULLv16i8_v8i16: case AArch64::SQADDv1i8: case AArch64::SQADDv1i16: case AArch64::SQADDv1i32: case AArch64::SQADDv1i64: case AArch64::SQADDv2i32: case AArch64::SQADDv2i64: case AArch64::SQADDv4i16: case AArch64::SQADDv4i32: case AArch64::SQADDv8i8: case AArch64::SQADDv8i16: case AArch64::SQADDv16i8: case AArch64::SQDMULHv1i16: case AArch64::SQDMULHv1i32: case AArch64::SQDMULHv2i32: case AArch64::SQDMULHv4i16: case AArch64::SQDMULHv4i32: case AArch64::SQDMULHv8i16: case AArch64::SQDMULLi16: case AArch64::SQDMULLi32: case AArch64::SQDMULLv2i32_v2i64: case AArch64::SQDMULLv4i16_v4i32: case AArch64::SQDMULLv4i32_v2i64: case AArch64::SQDMULLv8i16_v4i32: case AArch64::SQRDMULHv1i16: case AArch64::SQRDMULHv1i32: case AArch64::SQRDMULHv2i32: case AArch64::SQRDMULHv4i16: case AArch64::SQRDMULHv4i32: case AArch64::SQRDMULHv8i16: case AArch64::SQRSHLv1i8: case AArch64::SQRSHLv1i16: case AArch64::SQRSHLv1i32: case AArch64::SQRSHLv1i64: case AArch64::SQRSHLv2i32: case AArch64::SQRSHLv2i64: case AArch64::SQRSHLv4i16: case AArch64::SQRSHLv4i32: case AArch64::SQRSHLv8i8: case AArch64::SQRSHLv8i16: case AArch64::SQRSHLv16i8: case AArch64::SQSHLv1i8: case AArch64::SQSHLv1i16: case AArch64::SQSHLv1i32: case AArch64::SQSHLv1i64: case AArch64::SQSHLv2i32: case AArch64::SQSHLv2i64: case AArch64::SQSHLv4i16: case AArch64::SQSHLv4i32: case AArch64::SQSHLv8i8: case AArch64::SQSHLv8i16: case AArch64::SQSHLv16i8: case AArch64::SQSUBv1i8: case AArch64::SQSUBv1i16: case AArch64::SQSUBv1i32: case AArch64::SQSUBv1i64: case AArch64::SQSUBv2i32: case AArch64::SQSUBv2i64: case AArch64::SQSUBv4i16: case AArch64::SQSUBv4i32: case AArch64::SQSUBv8i8: case AArch64::SQSUBv8i16: case AArch64::SQSUBv16i8: case AArch64::SRHADDv2i32: case AArch64::SRHADDv4i16: case AArch64::SRHADDv4i32: case AArch64::SRHADDv8i8: case AArch64::SRHADDv8i16: case AArch64::SRHADDv16i8: case AArch64::SRSHLv1i64: case AArch64::SRSHLv2i32: case AArch64::SRSHLv2i64: case AArch64::SRSHLv4i16: case AArch64::SRSHLv4i32: case AArch64::SRSHLv8i8: case AArch64::SRSHLv8i16: case AArch64::SRSHLv16i8: case AArch64::SSHLv1i64: case AArch64::SSHLv2i32: case AArch64::SSHLv2i64: case AArch64::SSHLv4i16: case AArch64::SSHLv4i32: case AArch64::SSHLv8i8: case AArch64::SSHLv8i16: case AArch64::SSHLv16i8: case AArch64::SSUBLv2i32_v2i64: case AArch64::SSUBLv4i16_v4i32: case AArch64::SSUBLv4i32_v2i64: case AArch64::SSUBLv8i8_v8i16: case AArch64::SSUBLv8i16_v4i32: case AArch64::SSUBLv16i8_v8i16: case AArch64::SSUBWv2i32_v2i64: case AArch64::SSUBWv4i16_v4i32: case AArch64::SSUBWv4i32_v2i64: case AArch64::SSUBWv8i8_v8i16: case AArch64::SSUBWv8i16_v4i32: case AArch64::SSUBWv16i8_v8i16: case AArch64::SUBHNv2i64_v2i32: case AArch64::SUBHNv4i32_v4i16: case AArch64::SUBHNv8i16_v8i8: case AArch64::SUBP: case AArch64::SUBPS: case AArch64::SUBv1i64: case AArch64::SUBv2i32: case AArch64::SUBv2i64: case AArch64::SUBv4i16: case AArch64::SUBv4i32: case AArch64::SUBv8i8: case AArch64::SUBv8i16: case AArch64::SUBv16i8: case AArch64::TRN1v2i32: case AArch64::TRN1v2i64: case AArch64::TRN1v4i16: case AArch64::TRN1v4i32: case AArch64::TRN1v8i8: case AArch64::TRN1v8i16: case AArch64::TRN1v16i8: case AArch64::TRN2v2i32: case AArch64::TRN2v2i64: case AArch64::TRN2v4i16: case AArch64::TRN2v4i32: case AArch64::TRN2v8i8: case AArch64::TRN2v8i16: case AArch64::TRN2v16i8: case AArch64::UABDLv2i32_v2i64: case AArch64::UABDLv4i16_v4i32: case AArch64::UABDLv4i32_v2i64: case AArch64::UABDLv8i8_v8i16: case AArch64::UABDLv8i16_v4i32: case AArch64::UABDLv16i8_v8i16: case AArch64::UABDv2i32: case AArch64::UABDv4i16: case AArch64::UABDv4i32: case AArch64::UABDv8i8: case AArch64::UABDv8i16: case AArch64::UABDv16i8: case AArch64::UADDLv2i32_v2i64: case AArch64::UADDLv4i16_v4i32: case AArch64::UADDLv4i32_v2i64: case AArch64::UADDLv8i8_v8i16: case AArch64::UADDLv8i16_v4i32: case AArch64::UADDLv16i8_v8i16: case AArch64::UADDWv2i32_v2i64: case AArch64::UADDWv4i16_v4i32: case AArch64::UADDWv4i32_v2i64: case AArch64::UADDWv8i8_v8i16: case AArch64::UADDWv8i16_v4i32: case AArch64::UADDWv16i8_v8i16: case AArch64::UDIVWr: case AArch64::UDIVXr: case AArch64::UHADDv2i32: case AArch64::UHADDv4i16: case AArch64::UHADDv4i32: case AArch64::UHADDv8i8: case AArch64::UHADDv8i16: case AArch64::UHADDv16i8: case AArch64::UHSUBv2i32: case AArch64::UHSUBv4i16: case AArch64::UHSUBv4i32: case AArch64::UHSUBv8i8: case AArch64::UHSUBv8i16: case AArch64::UHSUBv16i8: case AArch64::UMAXPv2i32: case AArch64::UMAXPv4i16: case AArch64::UMAXPv4i32: case AArch64::UMAXPv8i8: case AArch64::UMAXPv8i16: case AArch64::UMAXPv16i8: case AArch64::UMAXWrr: case AArch64::UMAXXrr: case AArch64::UMAXv2i32: case AArch64::UMAXv4i16: case AArch64::UMAXv4i32: case AArch64::UMAXv8i8: case AArch64::UMAXv8i16: case AArch64::UMAXv16i8: case AArch64::UMINPv2i32: case AArch64::UMINPv4i16: case AArch64::UMINPv4i32: case AArch64::UMINPv8i8: case AArch64::UMINPv8i16: case AArch64::UMINPv16i8: case AArch64::UMINWrr: case AArch64::UMINXrr: case AArch64::UMINv2i32: case AArch64::UMINv4i16: case AArch64::UMINv4i32: case AArch64::UMINv8i8: case AArch64::UMINv8i16: case AArch64::UMINv16i8: case AArch64::UMULHrr: case AArch64::UMULLv2i32_v2i64: case AArch64::UMULLv4i16_v4i32: case AArch64::UMULLv4i32_v2i64: case AArch64::UMULLv8i8_v8i16: case AArch64::UMULLv8i16_v4i32: case AArch64::UMULLv16i8_v8i16: case AArch64::UQADDv1i8: case AArch64::UQADDv1i16: case AArch64::UQADDv1i32: case AArch64::UQADDv1i64: case AArch64::UQADDv2i32: case AArch64::UQADDv2i64: case AArch64::UQADDv4i16: case AArch64::UQADDv4i32: case AArch64::UQADDv8i8: case AArch64::UQADDv8i16: case AArch64::UQADDv16i8: case AArch64::UQRSHLv1i8: case AArch64::UQRSHLv1i16: case AArch64::UQRSHLv1i32: case AArch64::UQRSHLv1i64: case AArch64::UQRSHLv2i32: case AArch64::UQRSHLv2i64: case AArch64::UQRSHLv4i16: case AArch64::UQRSHLv4i32: case AArch64::UQRSHLv8i8: case AArch64::UQRSHLv8i16: case AArch64::UQRSHLv16i8: case AArch64::UQSHLv1i8: case AArch64::UQSHLv1i16: case AArch64::UQSHLv1i32: case AArch64::UQSHLv1i64: case AArch64::UQSHLv2i32: case AArch64::UQSHLv2i64: case AArch64::UQSHLv4i16: case AArch64::UQSHLv4i32: case AArch64::UQSHLv8i8: case AArch64::UQSHLv8i16: case AArch64::UQSHLv16i8: case AArch64::UQSUBv1i8: case AArch64::UQSUBv1i16: case AArch64::UQSUBv1i32: case AArch64::UQSUBv1i64: case AArch64::UQSUBv2i32: case AArch64::UQSUBv2i64: case AArch64::UQSUBv4i16: case AArch64::UQSUBv4i32: case AArch64::UQSUBv8i8: case AArch64::UQSUBv8i16: case AArch64::UQSUBv16i8: case AArch64::URHADDv2i32: case AArch64::URHADDv4i16: case AArch64::URHADDv4i32: case AArch64::URHADDv8i8: case AArch64::URHADDv8i16: case AArch64::URHADDv16i8: case AArch64::URSHLv1i64: case AArch64::URSHLv2i32: case AArch64::URSHLv2i64: case AArch64::URSHLv4i16: case AArch64::URSHLv4i32: case AArch64::URSHLv8i8: case AArch64::URSHLv8i16: case AArch64::URSHLv16i8: case AArch64::USHLv1i64: case AArch64::USHLv2i32: case AArch64::USHLv2i64: case AArch64::USHLv4i16: case AArch64::USHLv4i32: case AArch64::USHLv8i8: case AArch64::USHLv8i16: case AArch64::USHLv16i8: case AArch64::USUBLv2i32_v2i64: case AArch64::USUBLv4i16_v4i32: case AArch64::USUBLv4i32_v2i64: case AArch64::USUBLv8i8_v8i16: case AArch64::USUBLv8i16_v4i32: case AArch64::USUBLv16i8_v8i16: case AArch64::USUBWv2i32_v2i64: case AArch64::USUBWv4i16_v4i32: case AArch64::USUBWv4i32_v2i64: case AArch64::USUBWv8i8_v8i16: case AArch64::USUBWv8i16_v4i32: case AArch64::USUBWv16i8_v8i16: case AArch64::UZP1v2i32: case AArch64::UZP1v2i64: case AArch64::UZP1v4i16: case AArch64::UZP1v4i32: case AArch64::UZP1v8i8: case AArch64::UZP1v8i16: case AArch64::UZP1v16i8: case AArch64::UZP2v2i32: case AArch64::UZP2v2i64: case AArch64::UZP2v4i16: case AArch64::UZP2v4i32: case AArch64::UZP2v8i8: case AArch64::UZP2v8i16: case AArch64::UZP2v16i8: case AArch64::ZIP1v2i32: case AArch64::ZIP1v2i64: case AArch64::ZIP1v4i16: case AArch64::ZIP1v4i32: case AArch64::ZIP1v8i8: case AArch64::ZIP1v8i16: case AArch64::ZIP1v16i8: case AArch64::ZIP2v2i32: case AArch64::ZIP2v2i64: case AArch64::ZIP2v4i16: case AArch64::ZIP2v4i32: case AArch64::ZIP2v8i8: case AArch64::ZIP2v8i16: case AArch64::ZIP2v16i8: { switch (OpNum) { case 0: // op: Rd return 0; case 1: // op: Rn return 5; case 2: // op: Rm return 16; } break; } case AArch64::DUPv8i8lane: case AArch64::DUPv16i8lane: case AArch64::SMOVvi8to32: case AArch64::SMOVvi8to64: case AArch64::UMOVvi8: { switch (OpNum) { case 0: // op: Rd return 0; case 1: // op: Rn return 5; case 2: // op: idx return 17; } break; } case AArch64::DUPv4i16lane: case AArch64::DUPv8i16lane: case AArch64::SMOVvi16to32: case AArch64::SMOVvi16to64: case AArch64::UMOVvi16: { switch (OpNum) { case 0: // op: Rd return 0; case 1: // op: Rn return 5; case 2: // op: idx return 18; } break; } case AArch64::DUPv2i32lane: case AArch64::DUPv4i32lane: case AArch64::SMOVvi32to64: case AArch64::UMOVvi32: { switch (OpNum) { case 0: // op: Rd return 0; case 1: // op: Rn return 5; case 2: // op: idx return 19; } break; } case AArch64::DUPv2i64lane: case AArch64::UMOVvi64: { switch (OpNum) { case 0: // op: Rd return 0; case 1: // op: Rn return 5; case 2: // op: idx return 20; } break; } case AArch64::ADDSWri: case AArch64::ADDSXri: case AArch64::ADDWri: case AArch64::ADDXri: case AArch64::ANDSWri: case AArch64::ANDSXri: case AArch64::ANDWri: case AArch64::ANDXri: case AArch64::EORWri: case AArch64::EORXri: case AArch64::ORRWri: case AArch64::ORRXri: case AArch64::SMAXWri: case AArch64::SMAXXri: case AArch64::SMINWri: case AArch64::SMINXri: case AArch64::SUBSWri: case AArch64::SUBSXri: case AArch64::SUBWri: case AArch64::SUBXri: case AArch64::UMAXWri: case AArch64::UMAXXri: case AArch64::UMINWri: case AArch64::UMINXri: { switch (OpNum) { case 0: // op: Rd return 0; case 1: // op: Rn return 5; case 2: // op: imm return 10; } break; } case AArch64::FCVTZSd: case AArch64::FCVTZSh: case AArch64::FCVTZSs: case AArch64::FCVTZSv2i32_shift: case AArch64::FCVTZSv2i64_shift: case AArch64::FCVTZSv4i16_shift: case AArch64::FCVTZSv4i32_shift: case AArch64::FCVTZSv8i16_shift: case AArch64::FCVTZUd: case AArch64::FCVTZUh: case AArch64::FCVTZUs: case AArch64::FCVTZUv2i32_shift: case AArch64::FCVTZUv2i64_shift: case AArch64::FCVTZUv4i16_shift: case AArch64::FCVTZUv4i32_shift: case AArch64::FCVTZUv8i16_shift: case AArch64::RSHRNv2i32_shift: case AArch64::RSHRNv4i16_shift: case AArch64::RSHRNv8i8_shift: case AArch64::SCVTFd: case AArch64::SCVTFh: case AArch64::SCVTFs: case AArch64::SCVTFv2i32_shift: case AArch64::SCVTFv2i64_shift: case AArch64::SCVTFv4i16_shift: case AArch64::SCVTFv4i32_shift: case AArch64::SCVTFv8i16_shift: case AArch64::SHLd: case AArch64::SHLv2i32_shift: case AArch64::SHLv2i64_shift: case AArch64::SHLv4i16_shift: case AArch64::SHLv4i32_shift: case AArch64::SHLv8i8_shift: case AArch64::SHLv8i16_shift: case AArch64::SHLv16i8_shift: case AArch64::SHRNv2i32_shift: case AArch64::SHRNv4i16_shift: case AArch64::SHRNv8i8_shift: case AArch64::SQRSHRNb: case AArch64::SQRSHRNh: case AArch64::SQRSHRNs: case AArch64::SQRSHRNv2i32_shift: case AArch64::SQRSHRNv4i16_shift: case AArch64::SQRSHRNv8i8_shift: case AArch64::SQRSHRUNb: case AArch64::SQRSHRUNh: case AArch64::SQRSHRUNs: case AArch64::SQRSHRUNv2i32_shift: case AArch64::SQRSHRUNv4i16_shift: case AArch64::SQRSHRUNv8i8_shift: case AArch64::SQSHLUb: case AArch64::SQSHLUd: case AArch64::SQSHLUh: case AArch64::SQSHLUs: case AArch64::SQSHLUv2i32_shift: case AArch64::SQSHLUv2i64_shift: case AArch64::SQSHLUv4i16_shift: case AArch64::SQSHLUv4i32_shift: case AArch64::SQSHLUv8i8_shift: case AArch64::SQSHLUv8i16_shift: case AArch64::SQSHLUv16i8_shift: case AArch64::SQSHLb: case AArch64::SQSHLd: case AArch64::SQSHLh: case AArch64::SQSHLs: case AArch64::SQSHLv2i32_shift: case AArch64::SQSHLv2i64_shift: case AArch64::SQSHLv4i16_shift: case AArch64::SQSHLv4i32_shift: case AArch64::SQSHLv8i8_shift: case AArch64::SQSHLv8i16_shift: case AArch64::SQSHLv16i8_shift: case AArch64::SQSHRNb: case AArch64::SQSHRNh: case AArch64::SQSHRNs: case AArch64::SQSHRNv2i32_shift: case AArch64::SQSHRNv4i16_shift: case AArch64::SQSHRNv8i8_shift: case AArch64::SQSHRUNb: case AArch64::SQSHRUNh: case AArch64::SQSHRUNs: case AArch64::SQSHRUNv2i32_shift: case AArch64::SQSHRUNv4i16_shift: case AArch64::SQSHRUNv8i8_shift: case AArch64::SRSHRd: case AArch64::SRSHRv2i32_shift: case AArch64::SRSHRv2i64_shift: case AArch64::SRSHRv4i16_shift: case AArch64::SRSHRv4i32_shift: case AArch64::SRSHRv8i8_shift: case AArch64::SRSHRv8i16_shift: case AArch64::SRSHRv16i8_shift: case AArch64::SSHLLv2i32_shift: case AArch64::SSHLLv4i16_shift: case AArch64::SSHLLv4i32_shift: case AArch64::SSHLLv8i8_shift: case AArch64::SSHLLv8i16_shift: case AArch64::SSHLLv16i8_shift: case AArch64::SSHRd: case AArch64::SSHRv2i32_shift: case AArch64::SSHRv2i64_shift: case AArch64::SSHRv4i16_shift: case AArch64::SSHRv4i32_shift: case AArch64::SSHRv8i8_shift: case AArch64::SSHRv8i16_shift: case AArch64::SSHRv16i8_shift: case AArch64::UCVTFd: case AArch64::UCVTFh: case AArch64::UCVTFs: case AArch64::UCVTFv2i32_shift: case AArch64::UCVTFv2i64_shift: case AArch64::UCVTFv4i16_shift: case AArch64::UCVTFv4i32_shift: case AArch64::UCVTFv8i16_shift: case AArch64::UQRSHRNb: case AArch64::UQRSHRNh: case AArch64::UQRSHRNs: case AArch64::UQRSHRNv2i32_shift: case AArch64::UQRSHRNv4i16_shift: case AArch64::UQRSHRNv8i8_shift: case AArch64::UQSHLb: case AArch64::UQSHLd: case AArch64::UQSHLh: case AArch64::UQSHLs: case AArch64::UQSHLv2i32_shift: case AArch64::UQSHLv2i64_shift: case AArch64::UQSHLv4i16_shift: case AArch64::UQSHLv4i32_shift: case AArch64::UQSHLv8i8_shift: case AArch64::UQSHLv8i16_shift: case AArch64::UQSHLv16i8_shift: case AArch64::UQSHRNb: case AArch64::UQSHRNh: case AArch64::UQSHRNs: case AArch64::UQSHRNv2i32_shift: case AArch64::UQSHRNv4i16_shift: case AArch64::UQSHRNv8i8_shift: case AArch64::URSHRd: case AArch64::URSHRv2i32_shift: case AArch64::URSHRv2i64_shift: case AArch64::URSHRv4i16_shift: case AArch64::URSHRv4i32_shift: case AArch64::URSHRv8i8_shift: case AArch64::URSHRv8i16_shift: case AArch64::URSHRv16i8_shift: case AArch64::USHLLv2i32_shift: case AArch64::USHLLv4i16_shift: case AArch64::USHLLv4i32_shift: case AArch64::USHLLv8i8_shift: case AArch64::USHLLv8i16_shift: case AArch64::USHLLv16i8_shift: case AArch64::USHRd: case AArch64::USHRv2i32_shift: case AArch64::USHRv2i64_shift: case AArch64::USHRv4i16_shift: case AArch64::USHRv4i32_shift: case AArch64::USHRv8i8_shift: case AArch64::USHRv8i16_shift: case AArch64::USHRv16i8_shift: { switch (OpNum) { case 0: // op: Rd return 0; case 1: // op: Rn return 5; case 2: // op: imm return 16; } break; } case AArch64::ADDG: case AArch64::SUBG: { switch (OpNum) { case 0: // op: Rd return 0; case 1: // op: Rn return 5; case 2: // op: imm6 return 16; case 3: // op: imm4 return 10; } break; } case AArch64::SBFMWri: case AArch64::SBFMXri: case AArch64::UBFMWri: case AArch64::UBFMXri: { switch (OpNum) { case 0: // op: Rd return 0; case 1: // op: Rn return 5; case 2: // op: immr return 16; case 3: // op: imms return 10; } break; } case AArch64::FCVTZSSWDri: case AArch64::FCVTZSSWHri: case AArch64::FCVTZSSWSri: case AArch64::FCVTZSSXDri: case AArch64::FCVTZSSXHri: case AArch64::FCVTZSSXSri: case AArch64::FCVTZUSWDri: case AArch64::FCVTZUSWHri: case AArch64::FCVTZUSWSri: case AArch64::FCVTZUSXDri: case AArch64::FCVTZUSXHri: case AArch64::FCVTZUSXSri: case AArch64::SCVTFSWDri: case AArch64::SCVTFSWHri: case AArch64::SCVTFSWSri: case AArch64::SCVTFSXDri: case AArch64::SCVTFSXHri: case AArch64::SCVTFSXSri: case AArch64::UCVTFSWDri: case AArch64::UCVTFSWHri: case AArch64::UCVTFSWSri: case AArch64::UCVTFSXDri: case AArch64::UCVTFSXHri: case AArch64::UCVTFSXSri: { switch (OpNum) { case 0: // op: Rd return 0; case 1: // op: Rn return 5; case 2: // op: scale return 10; } break; } case AArch64::ABSWr: case AArch64::ABSXr: case AArch64::ABSv1i64: case AArch64::ABSv2i32: case AArch64::ABSv2i64: case AArch64::ABSv4i16: case AArch64::ABSv4i32: case AArch64::ABSv8i8: case AArch64::ABSv8i16: case AArch64::ABSv16i8: case AArch64::ADDPv2i64p: case AArch64::ADDVv4i16v: case AArch64::ADDVv4i32v: case AArch64::ADDVv8i8v: case AArch64::ADDVv8i16v: case AArch64::ADDVv16i8v: case AArch64::AESIMCrr: case AArch64::AESMCrr: case AArch64::BF1CVTL2v8f16: case AArch64::BF1CVTLv8f16: case AArch64::BF2CVTL2v8f16: case AArch64::BF2CVTLv8f16: case AArch64::BFCVT: case AArch64::BFCVTN: case AArch64::CLSWr: case AArch64::CLSXr: case AArch64::CLSv2i32: case AArch64::CLSv4i16: case AArch64::CLSv4i32: case AArch64::CLSv8i8: case AArch64::CLSv8i16: case AArch64::CLSv16i8: case AArch64::CLZWr: case AArch64::CLZXr: case AArch64::CLZv2i32: case AArch64::CLZv4i16: case AArch64::CLZv4i32: case AArch64::CLZv8i8: case AArch64::CLZv8i16: case AArch64::CLZv16i8: case AArch64::CMEQv1i64rz: case AArch64::CMEQv2i32rz: case AArch64::CMEQv2i64rz: case AArch64::CMEQv4i16rz: case AArch64::CMEQv4i32rz: case AArch64::CMEQv8i8rz: case AArch64::CMEQv8i16rz: case AArch64::CMEQv16i8rz: case AArch64::CMGEv1i64rz: case AArch64::CMGEv2i32rz: case AArch64::CMGEv2i64rz: case AArch64::CMGEv4i16rz: case AArch64::CMGEv4i32rz: case AArch64::CMGEv8i8rz: case AArch64::CMGEv8i16rz: case AArch64::CMGEv16i8rz: case AArch64::CMGTv1i64rz: case AArch64::CMGTv2i32rz: case AArch64::CMGTv2i64rz: case AArch64::CMGTv4i16rz: case AArch64::CMGTv4i32rz: case AArch64::CMGTv8i8rz: case AArch64::CMGTv8i16rz: case AArch64::CMGTv16i8rz: case AArch64::CMLEv1i64rz: case AArch64::CMLEv2i32rz: case AArch64::CMLEv2i64rz: case AArch64::CMLEv4i16rz: case AArch64::CMLEv4i32rz: case AArch64::CMLEv8i8rz: case AArch64::CMLEv8i16rz: case AArch64::CMLEv16i8rz: case AArch64::CMLTv1i64rz: case AArch64::CMLTv2i32rz: case AArch64::CMLTv2i64rz: case AArch64::CMLTv4i16rz: case AArch64::CMLTv4i32rz: case AArch64::CMLTv8i8rz: case AArch64::CMLTv8i16rz: case AArch64::CMLTv16i8rz: case AArch64::CNTWr: case AArch64::CNTXr: case AArch64::CNTv8i8: case AArch64::CNTv16i8: case AArch64::CTZWr: case AArch64::CTZXr: case AArch64::DUPv2i32gpr: case AArch64::DUPv2i64gpr: case AArch64::DUPv4i16gpr: case AArch64::DUPv4i32gpr: case AArch64::DUPv8i8gpr: case AArch64::DUPv8i16gpr: case AArch64::DUPv16i8gpr: case AArch64::F1CVTL2v8f16: case AArch64::F1CVTLv8f16: case AArch64::F2CVTL2v8f16: case AArch64::F2CVTLv8f16: case AArch64::FABSDr: case AArch64::FABSHr: case AArch64::FABSSr: case AArch64::FABSv2f32: case AArch64::FABSv2f64: case AArch64::FABSv4f16: case AArch64::FABSv4f32: case AArch64::FABSv8f16: case AArch64::FADDPv2i16p: case AArch64::FADDPv2i32p: case AArch64::FADDPv2i64p: case AArch64::FCMEQv1i16rz: case AArch64::FCMEQv1i32rz: case AArch64::FCMEQv1i64rz: case AArch64::FCMEQv2i32rz: case AArch64::FCMEQv2i64rz: case AArch64::FCMEQv4i16rz: case AArch64::FCMEQv4i32rz: case AArch64::FCMEQv8i16rz: case AArch64::FCMGEv1i16rz: case AArch64::FCMGEv1i32rz: case AArch64::FCMGEv1i64rz: case AArch64::FCMGEv2i32rz: case AArch64::FCMGEv2i64rz: case AArch64::FCMGEv4i16rz: case AArch64::FCMGEv4i32rz: case AArch64::FCMGEv8i16rz: case AArch64::FCMGTv1i16rz: case AArch64::FCMGTv1i32rz: case AArch64::FCMGTv1i64rz: case AArch64::FCMGTv2i32rz: case AArch64::FCMGTv2i64rz: case AArch64::FCMGTv4i16rz: case AArch64::FCMGTv4i32rz: case AArch64::FCMGTv8i16rz: case AArch64::FCMLEv1i16rz: case AArch64::FCMLEv1i32rz: case AArch64::FCMLEv1i64rz: case AArch64::FCMLEv2i32rz: case AArch64::FCMLEv2i64rz: case AArch64::FCMLEv4i16rz: case AArch64::FCMLEv4i32rz: case AArch64::FCMLEv8i16rz: case AArch64::FCMLTv1i16rz: case AArch64::FCMLTv1i32rz: case AArch64::FCMLTv1i64rz: case AArch64::FCMLTv2i32rz: case AArch64::FCMLTv2i64rz: case AArch64::FCMLTv4i16rz: case AArch64::FCMLTv4i32rz: case AArch64::FCMLTv8i16rz: case AArch64::FCVTASUWDr: case AArch64::FCVTASUWHr: case AArch64::FCVTASUWSr: case AArch64::FCVTASUXDr: case AArch64::FCVTASUXHr: case AArch64::FCVTASUXSr: case AArch64::FCVTASv1f16: case AArch64::FCVTASv1i32: case AArch64::FCVTASv1i64: case AArch64::FCVTASv2f32: case AArch64::FCVTASv2f64: case AArch64::FCVTASv4f16: case AArch64::FCVTASv4f32: case AArch64::FCVTASv8f16: case AArch64::FCVTAUUWDr: case AArch64::FCVTAUUWHr: case AArch64::FCVTAUUWSr: case AArch64::FCVTAUUXDr: case AArch64::FCVTAUUXHr: case AArch64::FCVTAUUXSr: case AArch64::FCVTAUv1f16: case AArch64::FCVTAUv1i32: case AArch64::FCVTAUv1i64: case AArch64::FCVTAUv2f32: case AArch64::FCVTAUv2f64: case AArch64::FCVTAUv4f16: case AArch64::FCVTAUv4f32: case AArch64::FCVTAUv8f16: case AArch64::FCVTDHr: case AArch64::FCVTDSr: case AArch64::FCVTHDr: case AArch64::FCVTHSr: case AArch64::FCVTLv2i32: case AArch64::FCVTLv4i16: case AArch64::FCVTLv4i32: case AArch64::FCVTLv8i16: case AArch64::FCVTMSUWDr: case AArch64::FCVTMSUWHr: case AArch64::FCVTMSUWSr: case AArch64::FCVTMSUXDr: case AArch64::FCVTMSUXHr: case AArch64::FCVTMSUXSr: case AArch64::FCVTMSv1f16: case AArch64::FCVTMSv1i32: case AArch64::FCVTMSv1i64: case AArch64::FCVTMSv2f32: case AArch64::FCVTMSv2f64: case AArch64::FCVTMSv4f16: case AArch64::FCVTMSv4f32: case AArch64::FCVTMSv8f16: case AArch64::FCVTMUUWDr: case AArch64::FCVTMUUWHr: case AArch64::FCVTMUUWSr: case AArch64::FCVTMUUXDr: case AArch64::FCVTMUUXHr: case AArch64::FCVTMUUXSr: case AArch64::FCVTMUv1f16: case AArch64::FCVTMUv1i32: case AArch64::FCVTMUv1i64: case AArch64::FCVTMUv2f32: case AArch64::FCVTMUv2f64: case AArch64::FCVTMUv4f16: case AArch64::FCVTMUv4f32: case AArch64::FCVTMUv8f16: case AArch64::FCVTNSUWDr: case AArch64::FCVTNSUWHr: case AArch64::FCVTNSUWSr: case AArch64::FCVTNSUXDr: case AArch64::FCVTNSUXHr: case AArch64::FCVTNSUXSr: case AArch64::FCVTNSv1f16: case AArch64::FCVTNSv1i32: case AArch64::FCVTNSv1i64: case AArch64::FCVTNSv2f32: case AArch64::FCVTNSv2f64: case AArch64::FCVTNSv4f16: case AArch64::FCVTNSv4f32: case AArch64::FCVTNSv8f16: case AArch64::FCVTNUUWDr: case AArch64::FCVTNUUWHr: case AArch64::FCVTNUUWSr: case AArch64::FCVTNUUXDr: case AArch64::FCVTNUUXHr: case AArch64::FCVTNUUXSr: case AArch64::FCVTNUv1f16: case AArch64::FCVTNUv1i32: case AArch64::FCVTNUv1i64: case AArch64::FCVTNUv2f32: case AArch64::FCVTNUv2f64: case AArch64::FCVTNUv4f16: case AArch64::FCVTNUv4f32: case AArch64::FCVTNUv8f16: case AArch64::FCVTNv2i32: case AArch64::FCVTNv4i16: case AArch64::FCVTPSUWDr: case AArch64::FCVTPSUWHr: case AArch64::FCVTPSUWSr: case AArch64::FCVTPSUXDr: case AArch64::FCVTPSUXHr: case AArch64::FCVTPSUXSr: case AArch64::FCVTPSv1f16: case AArch64::FCVTPSv1i32: case AArch64::FCVTPSv1i64: case AArch64::FCVTPSv2f32: case AArch64::FCVTPSv2f64: case AArch64::FCVTPSv4f16: case AArch64::FCVTPSv4f32: case AArch64::FCVTPSv8f16: case AArch64::FCVTPUUWDr: case AArch64::FCVTPUUWHr: case AArch64::FCVTPUUWSr: case AArch64::FCVTPUUXDr: case AArch64::FCVTPUUXHr: case AArch64::FCVTPUUXSr: case AArch64::FCVTPUv1f16: case AArch64::FCVTPUv1i32: case AArch64::FCVTPUv1i64: case AArch64::FCVTPUv2f32: case AArch64::FCVTPUv2f64: case AArch64::FCVTPUv4f16: case AArch64::FCVTPUv4f32: case AArch64::FCVTPUv8f16: case AArch64::FCVTSDr: case AArch64::FCVTSHr: case AArch64::FCVTXNv1i64: case AArch64::FCVTXNv2f32: case AArch64::FCVTZSUWDr: case AArch64::FCVTZSUWHr: case AArch64::FCVTZSUWSr: case AArch64::FCVTZSUXDr: case AArch64::FCVTZSUXHr: case AArch64::FCVTZSUXSr: case AArch64::FCVTZSv1f16: case AArch64::FCVTZSv1i32: case AArch64::FCVTZSv1i64: case AArch64::FCVTZSv2f32: case AArch64::FCVTZSv2f64: case AArch64::FCVTZSv4f16: case AArch64::FCVTZSv4f32: case AArch64::FCVTZSv8f16: case AArch64::FCVTZUUWDr: case AArch64::FCVTZUUWHr: case AArch64::FCVTZUUWSr: case AArch64::FCVTZUUXDr: case AArch64::FCVTZUUXHr: case AArch64::FCVTZUUXSr: case AArch64::FCVTZUv1f16: case AArch64::FCVTZUv1i32: case AArch64::FCVTZUv1i64: case AArch64::FCVTZUv2f32: case AArch64::FCVTZUv2f64: case AArch64::FCVTZUv4f16: case AArch64::FCVTZUv4f32: case AArch64::FCVTZUv8f16: case AArch64::FJCVTZS: case AArch64::FMAXNMPv2i16p: case AArch64::FMAXNMPv2i32p: case AArch64::FMAXNMPv2i64p: case AArch64::FMAXNMVv4i16v: case AArch64::FMAXNMVv4i32v: case AArch64::FMAXNMVv8i16v: case AArch64::FMAXPv2i16p: case AArch64::FMAXPv2i32p: case AArch64::FMAXPv2i64p: case AArch64::FMAXVv4i16v: case AArch64::FMAXVv4i32v: case AArch64::FMAXVv8i16v: case AArch64::FMINNMPv2i16p: case AArch64::FMINNMPv2i32p: case AArch64::FMINNMPv2i64p: case AArch64::FMINNMVv4i16v: case AArch64::FMINNMVv4i32v: case AArch64::FMINNMVv8i16v: case AArch64::FMINPv2i16p: case AArch64::FMINPv2i32p: case AArch64::FMINPv2i64p: case AArch64::FMINVv4i16v: case AArch64::FMINVv4i32v: case AArch64::FMINVv8i16v: case AArch64::FMOVDXHighr: case AArch64::FMOVDXr: case AArch64::FMOVDr: case AArch64::FMOVHWr: case AArch64::FMOVHXr: case AArch64::FMOVHr: case AArch64::FMOVSWr: case AArch64::FMOVSr: case AArch64::FMOVWHr: case AArch64::FMOVWSr: case AArch64::FMOVXDHighr: case AArch64::FMOVXDr: case AArch64::FMOVXHr: case AArch64::FNEGDr: case AArch64::FNEGHr: case AArch64::FNEGSr: case AArch64::FNEGv2f32: case AArch64::FNEGv2f64: case AArch64::FNEGv4f16: case AArch64::FNEGv4f32: case AArch64::FNEGv8f16: case AArch64::FRECPEv1f16: case AArch64::FRECPEv1i32: case AArch64::FRECPEv1i64: case AArch64::FRECPEv2f32: case AArch64::FRECPEv2f64: case AArch64::FRECPEv4f16: case AArch64::FRECPEv4f32: case AArch64::FRECPEv8f16: case AArch64::FRECPXv1f16: case AArch64::FRECPXv1i32: case AArch64::FRECPXv1i64: case AArch64::FRINT32XDr: case AArch64::FRINT32XSr: case AArch64::FRINT32Xv2f32: case AArch64::FRINT32Xv2f64: case AArch64::FRINT32Xv4f32: case AArch64::FRINT32ZDr: case AArch64::FRINT32ZSr: case AArch64::FRINT32Zv2f32: case AArch64::FRINT32Zv2f64: case AArch64::FRINT32Zv4f32: case AArch64::FRINT64XDr: case AArch64::FRINT64XSr: case AArch64::FRINT64Xv2f32: case AArch64::FRINT64Xv2f64: case AArch64::FRINT64Xv4f32: case AArch64::FRINT64ZDr: case AArch64::FRINT64ZSr: case AArch64::FRINT64Zv2f32: case AArch64::FRINT64Zv2f64: case AArch64::FRINT64Zv4f32: case AArch64::FRINTADr: case AArch64::FRINTAHr: case AArch64::FRINTASr: case AArch64::FRINTAv2f32: case AArch64::FRINTAv2f64: case AArch64::FRINTAv4f16: case AArch64::FRINTAv4f32: case AArch64::FRINTAv8f16: case AArch64::FRINTIDr: case AArch64::FRINTIHr: case AArch64::FRINTISr: case AArch64::FRINTIv2f32: case AArch64::FRINTIv2f64: case AArch64::FRINTIv4f16: case AArch64::FRINTIv4f32: case AArch64::FRINTIv8f16: case AArch64::FRINTMDr: case AArch64::FRINTMHr: case AArch64::FRINTMSr: case AArch64::FRINTMv2f32: case AArch64::FRINTMv2f64: case AArch64::FRINTMv4f16: case AArch64::FRINTMv4f32: case AArch64::FRINTMv8f16: case AArch64::FRINTNDr: case AArch64::FRINTNHr: case AArch64::FRINTNSr: case AArch64::FRINTNv2f32: case AArch64::FRINTNv2f64: case AArch64::FRINTNv4f16: case AArch64::FRINTNv4f32: case AArch64::FRINTNv8f16: case AArch64::FRINTPDr: case AArch64::FRINTPHr: case AArch64::FRINTPSr: case AArch64::FRINTPv2f32: case AArch64::FRINTPv2f64: case AArch64::FRINTPv4f16: case AArch64::FRINTPv4f32: case AArch64::FRINTPv8f16: case AArch64::FRINTXDr: case AArch64::FRINTXHr: case AArch64::FRINTXSr: case AArch64::FRINTXv2f32: case AArch64::FRINTXv2f64: case AArch64::FRINTXv4f16: case AArch64::FRINTXv4f32: case AArch64::FRINTXv8f16: case AArch64::FRINTZDr: case AArch64::FRINTZHr: case AArch64::FRINTZSr: case AArch64::FRINTZv2f32: case AArch64::FRINTZv2f64: case AArch64::FRINTZv4f16: case AArch64::FRINTZv4f32: case AArch64::FRINTZv8f16: case AArch64::FRSQRTEv1f16: case AArch64::FRSQRTEv1i32: case AArch64::FRSQRTEv1i64: case AArch64::FRSQRTEv2f32: case AArch64::FRSQRTEv2f64: case AArch64::FRSQRTEv4f16: case AArch64::FRSQRTEv4f32: case AArch64::FRSQRTEv8f16: case AArch64::FSQRTDr: case AArch64::FSQRTHr: case AArch64::FSQRTSr: case AArch64::FSQRTv2f32: case AArch64::FSQRTv2f64: case AArch64::FSQRTv4f16: case AArch64::FSQRTv4f32: case AArch64::FSQRTv8f16: case AArch64::NEGv1i64: case AArch64::NEGv2i32: case AArch64::NEGv2i64: case AArch64::NEGv4i16: case AArch64::NEGv4i32: case AArch64::NEGv8i8: case AArch64::NEGv8i16: case AArch64::NEGv16i8: case AArch64::NOTv8i8: case AArch64::NOTv16i8: case AArch64::RBITWr: case AArch64::RBITXr: case AArch64::RBITv8i8: case AArch64::RBITv16i8: case AArch64::REV16Wr: case AArch64::REV16Xr: case AArch64::REV16v8i8: case AArch64::REV16v16i8: case AArch64::REV32Xr: case AArch64::REV32v4i16: case AArch64::REV32v8i8: case AArch64::REV32v8i16: case AArch64::REV32v16i8: case AArch64::REV64v2i32: case AArch64::REV64v4i16: case AArch64::REV64v4i32: case AArch64::REV64v8i8: case AArch64::REV64v8i16: case AArch64::REV64v16i8: case AArch64::REVWr: case AArch64::REVXr: case AArch64::SADDLPv2i32_v1i64: case AArch64::SADDLPv4i16_v2i32: case AArch64::SADDLPv4i32_v2i64: case AArch64::SADDLPv8i8_v4i16: case AArch64::SADDLPv8i16_v4i32: case AArch64::SADDLPv16i8_v8i16: case AArch64::SADDLVv4i16v: case AArch64::SADDLVv4i32v: case AArch64::SADDLVv8i8v: case AArch64::SADDLVv8i16v: case AArch64::SADDLVv16i8v: case AArch64::SCVTFUWDri: case AArch64::SCVTFUWHri: case AArch64::SCVTFUWSri: case AArch64::SCVTFUXDri: case AArch64::SCVTFUXHri: case AArch64::SCVTFUXSri: case AArch64::SCVTFv1i16: case AArch64::SCVTFv1i32: case AArch64::SCVTFv1i64: case AArch64::SCVTFv2f32: case AArch64::SCVTFv2f64: case AArch64::SCVTFv4f16: case AArch64::SCVTFv4f32: case AArch64::SCVTFv8f16: case AArch64::SHA1Hrr: case AArch64::SHLLv2i32: case AArch64::SHLLv4i16: case AArch64::SHLLv4i32: case AArch64::SHLLv8i8: case AArch64::SHLLv8i16: case AArch64::SHLLv16i8: case AArch64::SMAXVv4i16v: case AArch64::SMAXVv4i32v: case AArch64::SMAXVv8i8v: case AArch64::SMAXVv8i16v: case AArch64::SMAXVv16i8v: case AArch64::SMINVv4i16v: case AArch64::SMINVv4i32v: case AArch64::SMINVv8i8v: case AArch64::SMINVv8i16v: case AArch64::SMINVv16i8v: case AArch64::SMOVvi8to32_idx0: case AArch64::SMOVvi8to64_idx0: case AArch64::SMOVvi16to32_idx0: case AArch64::SMOVvi16to64_idx0: case AArch64::SMOVvi32to64_idx0: case AArch64::SQABSv1i8: case AArch64::SQABSv1i16: case AArch64::SQABSv1i32: case AArch64::SQABSv1i64: case AArch64::SQABSv2i32: case AArch64::SQABSv2i64: case AArch64::SQABSv4i16: case AArch64::SQABSv4i32: case AArch64::SQABSv8i8: case AArch64::SQABSv8i16: case AArch64::SQABSv16i8: case AArch64::SQNEGv1i8: case AArch64::SQNEGv1i16: case AArch64::SQNEGv1i32: case AArch64::SQNEGv1i64: case AArch64::SQNEGv2i32: case AArch64::SQNEGv2i64: case AArch64::SQNEGv4i16: case AArch64::SQNEGv4i32: case AArch64::SQNEGv8i8: case AArch64::SQNEGv8i16: case AArch64::SQNEGv16i8: case AArch64::SQXTNv1i8: case AArch64::SQXTNv1i16: case AArch64::SQXTNv1i32: case AArch64::SQXTNv2i32: case AArch64::SQXTNv4i16: case AArch64::SQXTNv8i8: case AArch64::SQXTUNv1i8: case AArch64::SQXTUNv1i16: case AArch64::SQXTUNv1i32: case AArch64::SQXTUNv2i32: case AArch64::SQXTUNv4i16: case AArch64::SQXTUNv8i8: case AArch64::UADDLPv2i32_v1i64: case AArch64::UADDLPv4i16_v2i32: case AArch64::UADDLPv4i32_v2i64: case AArch64::UADDLPv8i8_v4i16: case AArch64::UADDLPv8i16_v4i32: case AArch64::UADDLPv16i8_v8i16: case AArch64::UADDLVv4i16v: case AArch64::UADDLVv4i32v: case AArch64::UADDLVv8i8v: case AArch64::UADDLVv8i16v: case AArch64::UADDLVv16i8v: case AArch64::UCVTFUWDri: case AArch64::UCVTFUWHri: case AArch64::UCVTFUWSri: case AArch64::UCVTFUXDri: case AArch64::UCVTFUXHri: case AArch64::UCVTFUXSri: case AArch64::UCVTFv1i16: case AArch64::UCVTFv1i32: case AArch64::UCVTFv1i64: case AArch64::UCVTFv2f32: case AArch64::UCVTFv2f64: case AArch64::UCVTFv4f16: case AArch64::UCVTFv4f32: case AArch64::UCVTFv8f16: case AArch64::UMAXVv4i16v: case AArch64::UMAXVv4i32v: case AArch64::UMAXVv8i8v: case AArch64::UMAXVv8i16v: case AArch64::UMAXVv16i8v: case AArch64::UMINVv4i16v: case AArch64::UMINVv4i32v: case AArch64::UMINVv8i8v: case AArch64::UMINVv8i16v: case AArch64::UMINVv16i8v: case AArch64::UMOVvi8_idx0: case AArch64::UMOVvi16_idx0: case AArch64::UMOVvi32_idx0: case AArch64::UMOVvi64_idx0: case AArch64::UQXTNv1i8: case AArch64::UQXTNv1i16: case AArch64::UQXTNv1i32: case AArch64::UQXTNv2i32: case AArch64::UQXTNv4i16: case AArch64::UQXTNv8i8: case AArch64::URECPEv2i32: case AArch64::URECPEv4i32: case AArch64::URSQRTEv2i32: case AArch64::URSQRTEv4i32: case AArch64::XTNv2i32: case AArch64::XTNv4i16: case AArch64::XTNv8i8: { switch (OpNum) { case 0: // op: Rd return 0; case 1: // op: Rn return 5; } break; } case AArch64::FMOVDi: case AArch64::FMOVHi: case AArch64::FMOVSi: { switch (OpNum) { case 0: // op: Rd return 0; case 1: // op: imm return 13; } break; } case AArch64::MOVNWi: case AArch64::MOVNXi: case AArch64::MOVZWi: case AArch64::MOVZXi: { switch (OpNum) { case 0: // op: Rd return 0; case 1: // op: imm return 5; case 2: // op: shift return 21; } break; } case AArch64::RDSVLI_XI: case AArch64::RDVLI_XI: { switch (OpNum) { case 0: // op: Rd return 0; case 1: // op: imm6 return 5; } break; } case AArch64::MOVIv2s_msl: case AArch64::MOVIv4s_msl: case AArch64::MVNIv2s_msl: case AArch64::MVNIv4s_msl: { switch (OpNum) { case 0: // op: Rd return 0; case 1: // op: imm8 return 5; case 2: // op: shift return 12; } break; } case AArch64::MOVIv2i32: case AArch64::MOVIv4i16: case AArch64::MOVIv4i32: case AArch64::MOVIv8i16: case AArch64::MVNIv2i32: case AArch64::MVNIv4i16: case AArch64::MVNIv4i32: case AArch64::MVNIv8i16: { switch (OpNum) { case 0: // op: Rd return 0; case 1: // op: imm8 return 5; case 2: // op: shift return 13; } break; } case AArch64::FMOVv2f32_ns: case AArch64::FMOVv2f64_ns: case AArch64::FMOVv4f16_ns: case AArch64::FMOVv4f32_ns: case AArch64::FMOVv8f16_ns: case AArch64::MOVID: case AArch64::MOVIv2d_ns: case AArch64::MOVIv8b_ns: case AArch64::MOVIv16b_ns: { switch (OpNum) { case 0: // op: Rd return 0; case 1: // op: imm8 return 5; } break; } case AArch64::BFMWri: case AArch64::BFMXri: { switch (OpNum) { case 0: // op: Rd return 0; case 2: // op: Rn return 5; case 3: // op: immr return 16; case 4: // op: imms return 10; } break; } case AArch64::MOVKWi: case AArch64::MOVKXi: { switch (OpNum) { case 0: // op: Rd return 0; case 2: // op: imm return 5; case 3: // op: shift return 21; } break; } case AArch64::CNTB_XPiI: case AArch64::CNTD_XPiI: case AArch64::CNTH_XPiI: case AArch64::CNTW_XPiI: { switch (OpNum) { case 0: // op: Rd return 0; case 2: // op: imm4 return 16; case 1: // op: pattern return 5; } break; } case AArch64::XPACD: case AArch64::XPACI: { switch (OpNum) { case 0: // op: Rd return 0; } break; } case AArch64::DECP_XP_B: case AArch64::DECP_XP_D: case AArch64::DECP_XP_H: case AArch64::DECP_XP_S: case AArch64::INCP_XP_B: case AArch64::INCP_XP_D: case AArch64::INCP_XP_H: case AArch64::INCP_XP_S: case AArch64::SQDECP_XPWd_B: case AArch64::SQDECP_XPWd_D: case AArch64::SQDECP_XPWd_H: case AArch64::SQDECP_XPWd_S: case AArch64::SQDECP_XP_B: case AArch64::SQDECP_XP_D: case AArch64::SQDECP_XP_H: case AArch64::SQDECP_XP_S: case AArch64::SQINCP_XPWd_B: case AArch64::SQINCP_XPWd_D: case AArch64::SQINCP_XPWd_H: case AArch64::SQINCP_XPWd_S: case AArch64::SQINCP_XP_B: case AArch64::SQINCP_XP_D: case AArch64::SQINCP_XP_H: case AArch64::SQINCP_XP_S: case AArch64::UQDECP_WP_B: case AArch64::UQDECP_WP_D: case AArch64::UQDECP_WP_H: case AArch64::UQDECP_WP_S: case AArch64::UQDECP_XP_B: case AArch64::UQDECP_XP_D: case AArch64::UQDECP_XP_H: case AArch64::UQDECP_XP_S: case AArch64::UQINCP_WP_B: case AArch64::UQINCP_WP_D: case AArch64::UQINCP_WP_H: case AArch64::UQINCP_WP_S: case AArch64::UQINCP_XP_B: case AArch64::UQINCP_XP_D: case AArch64::UQINCP_XP_H: case AArch64::UQINCP_XP_S: { switch (OpNum) { case 0: // op: Rdn return 0; case 1: // op: Pg return 5; } break; } case AArch64::DECB_XPiI: case AArch64::DECD_XPiI: case AArch64::DECH_XPiI: case AArch64::DECW_XPiI: case AArch64::INCB_XPiI: case AArch64::INCD_XPiI: case AArch64::INCH_XPiI: case AArch64::INCW_XPiI: case AArch64::SQDECB_XPiI: case AArch64::SQDECB_XPiWdI: case AArch64::SQDECD_XPiI: case AArch64::SQDECD_XPiWdI: case AArch64::SQDECH_XPiI: case AArch64::SQDECH_XPiWdI: case AArch64::SQDECW_XPiI: case AArch64::SQDECW_XPiWdI: case AArch64::SQINCB_XPiI: case AArch64::SQINCB_XPiWdI: case AArch64::SQINCD_XPiI: case AArch64::SQINCD_XPiWdI: case AArch64::SQINCH_XPiI: case AArch64::SQINCH_XPiWdI: case AArch64::SQINCW_XPiI: case AArch64::SQINCW_XPiWdI: case AArch64::UQDECB_WPiI: case AArch64::UQDECB_XPiI: case AArch64::UQDECD_WPiI: case AArch64::UQDECD_XPiI: case AArch64::UQDECH_WPiI: case AArch64::UQDECH_XPiI: case AArch64::UQDECW_WPiI: case AArch64::UQDECW_XPiI: case AArch64::UQINCB_WPiI: case AArch64::UQINCB_XPiI: case AArch64::UQINCD_WPiI: case AArch64::UQINCD_XPiI: case AArch64::UQINCH_WPiI: case AArch64::UQINCH_XPiI: case AArch64::UQINCW_WPiI: case AArch64::UQINCW_XPiI: { switch (OpNum) { case 0: // op: Rdn return 0; case 2: // op: pattern return 5; case 3: // op: imm4 return 16; } break; } case AArch64::RETAASPPCr: case AArch64::RETABSPPCr: { switch (OpNum) { case 0: // op: Rm return 0; } break; } case AArch64::BLRAA: case AArch64::BLRAB: case AArch64::BRAA: case AArch64::BRAB: { switch (OpNum) { case 0: // op: Rn return 5; case 1: // op: Rm return 0; } break; } case AArch64::CCMNWr: case AArch64::CCMNXr: case AArch64::CCMPWr: case AArch64::CCMPXr: case AArch64::FCCMPDrr: case AArch64::FCCMPEDrr: case AArch64::FCCMPEHrr: case AArch64::FCCMPESrr: case AArch64::FCCMPHrr: case AArch64::FCCMPSrr: { switch (OpNum) { case 0: // op: Rn return 5; case 1: // op: Rm return 16; case 2: // op: nzcv return 0; case 3: // op: cond return 12; } break; } case AArch64::RMIF: { switch (OpNum) { case 0: // op: Rn return 5; case 1: // op: imm return 15; case 2: // op: mask return 0; } break; } case AArch64::CCMNWi: case AArch64::CCMNXi: case AArch64::CCMPWi: case AArch64::CCMPXi: { switch (OpNum) { case 0: // op: Rn return 5; case 1: // op: imm return 16; case 2: // op: nzcv return 0; case 3: // op: cond return 12; } break; } case AArch64::AUTIASPPCr: case AArch64::AUTIBSPPCr: case AArch64::BLR: case AArch64::BLRAAZ: case AArch64::BLRABZ: case AArch64::BR: case AArch64::BRAAZ: case AArch64::BRABZ: case AArch64::FCMPDri: case AArch64::FCMPEDri: case AArch64::FCMPEHri: case AArch64::FCMPESri: case AArch64::FCMPHri: case AArch64::FCMPSri: case AArch64::RET: case AArch64::SETF8: case AArch64::SETF16: { switch (OpNum) { case 0: // op: Rn return 5; } break; } case AArch64::LDRBBroW: case AArch64::LDRBBroX: case AArch64::LDRBroW: case AArch64::LDRBroX: case AArch64::LDRDroW: case AArch64::LDRDroX: case AArch64::LDRHHroW: case AArch64::LDRHHroX: case AArch64::LDRHroW: case AArch64::LDRHroX: case AArch64::LDRQroW: case AArch64::LDRQroX: case AArch64::LDRSBWroW: case AArch64::LDRSBWroX: case AArch64::LDRSBXroW: case AArch64::LDRSBXroX: case AArch64::LDRSHWroW: case AArch64::LDRSHWroX: case AArch64::LDRSHXroW: case AArch64::LDRSHXroX: case AArch64::LDRSWroW: case AArch64::LDRSWroX: case AArch64::LDRSroW: case AArch64::LDRSroX: case AArch64::LDRWroW: case AArch64::LDRWroX: case AArch64::LDRXroW: case AArch64::LDRXroX: case AArch64::PRFMroW: case AArch64::PRFMroX: case AArch64::STRBBroW: case AArch64::STRBBroX: case AArch64::STRBroW: case AArch64::STRBroX: case AArch64::STRDroW: case AArch64::STRDroX: case AArch64::STRHHroW: case AArch64::STRHHroX: case AArch64::STRHroW: case AArch64::STRHroX: case AArch64::STRQroW: case AArch64::STRQroX: case AArch64::STRSroW: case AArch64::STRSroX: case AArch64::STRWroW: case AArch64::STRWroX: case AArch64::STRXroW: case AArch64::STRXroX: { switch (OpNum) { case 0: // op: Rt return 0; case 1: // op: Rn return 5; case 2: // op: Rm return 16; case 3: // op: extend return 12; } break; } case AArch64::LDRBBui: case AArch64::LDRBui: case AArch64::LDRDui: case AArch64::LDRHHui: case AArch64::LDRHui: case AArch64::LDRQui: case AArch64::LDRSBWui: case AArch64::LDRSBXui: case AArch64::LDRSHWui: case AArch64::LDRSHXui: case AArch64::LDRSWui: case AArch64::LDRSui: case AArch64::LDRWui: case AArch64::LDRXui: case AArch64::PRFMui: case AArch64::STRBBui: case AArch64::STRBui: case AArch64::STRDui: case AArch64::STRHHui: case AArch64::STRHui: case AArch64::STRQui: case AArch64::STRSui: case AArch64::STRWui: case AArch64::STRXui: { switch (OpNum) { case 0: // op: Rt return 0; case 1: // op: Rn return 5; case 2: // op: offset return 10; } break; } case AArch64::LDAPURBi: case AArch64::LDAPURHi: case AArch64::LDAPURSBWi: case AArch64::LDAPURSBXi: case AArch64::LDAPURSHWi: case AArch64::LDAPURSHXi: case AArch64::LDAPURSWi: case AArch64::LDAPURXi: case AArch64::LDAPURi: case AArch64::LDTRBi: case AArch64::LDTRHi: case AArch64::LDTRSBWi: case AArch64::LDTRSBXi: case AArch64::LDTRSHWi: case AArch64::LDTRSHXi: case AArch64::LDTRSWi: case AArch64::LDTRWi: case AArch64::LDTRXi: case AArch64::LDURBBi: case AArch64::LDURBi: case AArch64::LDURDi: case AArch64::LDURHHi: case AArch64::LDURHi: case AArch64::LDURQi: case AArch64::LDURSBWi: case AArch64::LDURSBXi: case AArch64::LDURSHWi: case AArch64::LDURSHXi: case AArch64::LDURSWi: case AArch64::LDURSi: case AArch64::LDURWi: case AArch64::LDURXi: case AArch64::PRFUMi: case AArch64::STLURBi: case AArch64::STLURHi: case AArch64::STLURWi: case AArch64::STLURXi: case AArch64::STTRBi: case AArch64::STTRHi: case AArch64::STTRWi: case AArch64::STTRXi: case AArch64::STURBBi: case AArch64::STURBi: case AArch64::STURDi: case AArch64::STURHHi: case AArch64::STURHi: case AArch64::STURQi: case AArch64::STURSi: case AArch64::STURWi: case AArch64::STURXi: { switch (OpNum) { case 0: // op: Rt return 0; case 1: // op: Rn return 5; case 2: // op: offset return 12; } break; } case AArch64::LDAPURbi: case AArch64::LDAPURdi: case AArch64::LDAPURhi: case AArch64::LDAPURqi: case AArch64::LDAPURsi: case AArch64::STLURbi: case AArch64::STLURdi: case AArch64::STLURhi: case AArch64::STLURqi: case AArch64::STLURsi: { switch (OpNum) { case 0: // op: Rt return 0; case 1: // op: Rn return 5; case 2: // op: simm return 12; } break; } case AArch64::GCSSTR: case AArch64::GCSSTTR: case AArch64::LD64B: case AArch64::LDARB: case AArch64::LDARH: case AArch64::LDARW: case AArch64::LDARX: case AArch64::LDAXRB: case AArch64::LDAXRH: case AArch64::LDAXRW: case AArch64::LDAXRX: case AArch64::LDLARB: case AArch64::LDLARH: case AArch64::LDLARW: case AArch64::LDLARX: case AArch64::LDXRB: case AArch64::LDXRH: case AArch64::LDXRW: case AArch64::LDXRX: case AArch64::ST64B: case AArch64::STLLRB: case AArch64::STLLRH: case AArch64::STLLRW: case AArch64::STLLRX: case AArch64::STLRB: case AArch64::STLRH: case AArch64::STLRW: case AArch64::STLRX: { switch (OpNum) { case 0: // op: Rt return 0; case 1: // op: Rn return 5; } break; } case AArch64::LDNPDi: case AArch64::LDNPQi: case AArch64::LDNPSi: case AArch64::LDNPWi: case AArch64::LDNPXi: case AArch64::LDPDi: case AArch64::LDPQi: case AArch64::LDPSWi: case AArch64::LDPSi: case AArch64::LDPWi: case AArch64::LDPXi: case AArch64::STGPi: case AArch64::STNPDi: case AArch64::STNPQi: case AArch64::STNPSi: case AArch64::STNPWi: case AArch64::STNPXi: case AArch64::STPDi: case AArch64::STPQi: case AArch64::STPSi: case AArch64::STPWi: case AArch64::STPXi: { switch (OpNum) { case 0: // op: Rt return 0; case 1: // op: Rt2 return 10; case 2: // op: Rn return 5; case 3: // op: offset return 15; } break; } case AArch64::LDAXPW: case AArch64::LDAXPX: case AArch64::LDXPW: case AArch64::LDXPX: { switch (OpNum) { case 0: // op: Rt return 0; case 1: // op: Rt2 return 10; case 2: // op: Rn return 5; } break; } case AArch64::TBNZW: case AArch64::TBNZX: case AArch64::TBZW: case AArch64::TBZX: { switch (OpNum) { case 0: // op: Rt return 0; case 1: // op: bit_off return 19; case 2: // op: target return 5; } break; } case AArch64::LDRDl: case AArch64::LDRQl: case AArch64::LDRSWl: case AArch64::LDRSl: case AArch64::LDRWl: case AArch64::LDRXl: case AArch64::PRFMl: { switch (OpNum) { case 0: // op: Rt return 0; case 1: // op: label return 5; } break; } case AArch64::SYSLxt: { switch (OpNum) { case 0: // op: Rt return 0; case 1: // op: op1 return 16; case 2: // op: Cn return 12; case 3: // op: Cm return 8; case 4: // op: op2 return 5; } break; } case AArch64::MRRS: case AArch64::MRS: { switch (OpNum) { case 0: // op: Rt return 0; case 1: // op: systemreg return 5; } break; } case AArch64::CBNZW: case AArch64::CBNZX: case AArch64::CBZW: case AArch64::CBZX: { switch (OpNum) { case 0: // op: Rt return 0; case 1: // op: target return 5; } break; } case AArch64::RPRFM: { switch (OpNum) { case 0: // op: Rt return 0; case 2: // op: Rn return 5; case 1: // op: Rm return 16; } break; } case AArch64::LDIAPPW: case AArch64::LDIAPPX: case AArch64::STILPW: case AArch64::STILPX: { switch (OpNum) { case 0: // op: Rt return 0; case 2: // op: Rn return 5; case 1: // op: Rt2 return 16; } break; } case AArch64::GCSPOPM: case AArch64::GCSPUSHM: case AArch64::GCSSS1: case AArch64::GCSSS2: case AArch64::TRCIT: case AArch64::TSTART: case AArch64::TTEST: case AArch64::WFET: case AArch64::WFIT: { switch (OpNum) { case 0: // op: Rt return 0; } break; } case AArch64::BCAX: case AArch64::EOR3: case AArch64::SM3SS1: { switch (OpNum) { case 0: // op: Vd return 0; case 1: // op: Vn return 5; case 2: // op: Vm return 16; case 3: // op: Va return 10; } break; } case AArch64::RAX1: case AArch64::SM4ENCKEY: case AArch64::TBLv8i8Four: case AArch64::TBLv8i8One: case AArch64::TBLv8i8Three: case AArch64::TBLv8i8Two: case AArch64::TBLv16i8Four: case AArch64::TBLv16i8One: case AArch64::TBLv16i8Three: case AArch64::TBLv16i8Two: { switch (OpNum) { case 0: // op: Vd return 0; case 1: // op: Vn return 5; case 2: // op: Vm return 16; } break; } case AArch64::XAR: { switch (OpNum) { case 0: // op: Vd return 0; case 1: // op: Vn return 5; case 3: // op: imm return 10; case 2: // op: Vm return 16; } break; } case AArch64::ADDQV_VPZ_B: case AArch64::ADDQV_VPZ_D: case AArch64::ADDQV_VPZ_H: case AArch64::ADDQV_VPZ_S: case AArch64::ANDQV_VPZ_B: case AArch64::ANDQV_VPZ_D: case AArch64::ANDQV_VPZ_H: case AArch64::ANDQV_VPZ_S: case AArch64::EORQV_VPZ_B: case AArch64::EORQV_VPZ_D: case AArch64::EORQV_VPZ_H: case AArch64::EORQV_VPZ_S: case AArch64::FADDQV_D: case AArch64::FADDQV_H: case AArch64::FADDQV_S: case AArch64::FMAXNMQV_D: case AArch64::FMAXNMQV_H: case AArch64::FMAXNMQV_S: case AArch64::FMAXQV_D: case AArch64::FMAXQV_H: case AArch64::FMAXQV_S: case AArch64::FMINNMQV_D: case AArch64::FMINNMQV_H: case AArch64::FMINNMQV_S: case AArch64::FMINQV_D: case AArch64::FMINQV_H: case AArch64::FMINQV_S: case AArch64::ORQV_VPZ_B: case AArch64::ORQV_VPZ_D: case AArch64::ORQV_VPZ_H: case AArch64::ORQV_VPZ_S: case AArch64::SMAXQV_VPZ_B: case AArch64::SMAXQV_VPZ_D: case AArch64::SMAXQV_VPZ_H: case AArch64::SMAXQV_VPZ_S: case AArch64::SMINQV_VPZ_B: case AArch64::SMINQV_VPZ_D: case AArch64::SMINQV_VPZ_H: case AArch64::SMINQV_VPZ_S: case AArch64::UMAXQV_VPZ_B: case AArch64::UMAXQV_VPZ_D: case AArch64::UMAXQV_VPZ_H: case AArch64::UMAXQV_VPZ_S: case AArch64::UMINQV_VPZ_B: case AArch64::UMINQV_VPZ_D: case AArch64::UMINQV_VPZ_H: case AArch64::UMINQV_VPZ_S: { switch (OpNum) { case 0: // op: Vd return 0; case 2: // op: Zn return 5; case 1: // op: Pg return 10; } break; } case AArch64::LD1Fourv1d: case AArch64::LD1Fourv2d: case AArch64::LD1Fourv2s: case AArch64::LD1Fourv4h: case AArch64::LD1Fourv4s: case AArch64::LD1Fourv8b: case AArch64::LD1Fourv8h: case AArch64::LD1Fourv16b: case AArch64::LD1Onev1d: case AArch64::LD1Onev2d: case AArch64::LD1Onev2s: case AArch64::LD1Onev4h: case AArch64::LD1Onev4s: case AArch64::LD1Onev8b: case AArch64::LD1Onev8h: case AArch64::LD1Onev16b: case AArch64::LD1Rv1d: case AArch64::LD1Rv2d: case AArch64::LD1Rv2s: case AArch64::LD1Rv4h: case AArch64::LD1Rv4s: case AArch64::LD1Rv8b: case AArch64::LD1Rv8h: case AArch64::LD1Rv16b: case AArch64::LD1Threev1d: case AArch64::LD1Threev2d: case AArch64::LD1Threev2s: case AArch64::LD1Threev4h: case AArch64::LD1Threev4s: case AArch64::LD1Threev8b: case AArch64::LD1Threev8h: case AArch64::LD1Threev16b: case AArch64::LD1Twov1d: case AArch64::LD1Twov2d: case AArch64::LD1Twov2s: case AArch64::LD1Twov4h: case AArch64::LD1Twov4s: case AArch64::LD1Twov8b: case AArch64::LD1Twov8h: case AArch64::LD1Twov16b: case AArch64::LD2Rv1d: case AArch64::LD2Rv2d: case AArch64::LD2Rv2s: case AArch64::LD2Rv4h: case AArch64::LD2Rv4s: case AArch64::LD2Rv8b: case AArch64::LD2Rv8h: case AArch64::LD2Rv16b: case AArch64::LD2Twov2d: case AArch64::LD2Twov2s: case AArch64::LD2Twov4h: case AArch64::LD2Twov4s: case AArch64::LD2Twov8b: case AArch64::LD2Twov8h: case AArch64::LD2Twov16b: case AArch64::LD3Rv1d: case AArch64::LD3Rv2d: case AArch64::LD3Rv2s: case AArch64::LD3Rv4h: case AArch64::LD3Rv4s: case AArch64::LD3Rv8b: case AArch64::LD3Rv8h: case AArch64::LD3Rv16b: case AArch64::LD3Threev2d: case AArch64::LD3Threev2s: case AArch64::LD3Threev4h: case AArch64::LD3Threev4s: case AArch64::LD3Threev8b: case AArch64::LD3Threev8h: case AArch64::LD3Threev16b: case AArch64::LD4Fourv2d: case AArch64::LD4Fourv2s: case AArch64::LD4Fourv4h: case AArch64::LD4Fourv4s: case AArch64::LD4Fourv8b: case AArch64::LD4Fourv8h: case AArch64::LD4Fourv16b: case AArch64::LD4Rv1d: case AArch64::LD4Rv2d: case AArch64::LD4Rv2s: case AArch64::LD4Rv4h: case AArch64::LD4Rv4s: case AArch64::LD4Rv8b: case AArch64::LD4Rv8h: case AArch64::LD4Rv16b: case AArch64::ST1Fourv1d: case AArch64::ST1Fourv2d: case AArch64::ST1Fourv2s: case AArch64::ST1Fourv4h: case AArch64::ST1Fourv4s: case AArch64::ST1Fourv8b: case AArch64::ST1Fourv8h: case AArch64::ST1Fourv16b: case AArch64::ST1Onev1d: case AArch64::ST1Onev2d: case AArch64::ST1Onev2s: case AArch64::ST1Onev4h: case AArch64::ST1Onev4s: case AArch64::ST1Onev8b: case AArch64::ST1Onev8h: case AArch64::ST1Onev16b: case AArch64::ST1Threev1d: case AArch64::ST1Threev2d: case AArch64::ST1Threev2s: case AArch64::ST1Threev4h: case AArch64::ST1Threev4s: case AArch64::ST1Threev8b: case AArch64::ST1Threev8h: case AArch64::ST1Threev16b: case AArch64::ST1Twov1d: case AArch64::ST1Twov2d: case AArch64::ST1Twov2s: case AArch64::ST1Twov4h: case AArch64::ST1Twov4s: case AArch64::ST1Twov8b: case AArch64::ST1Twov8h: case AArch64::ST1Twov16b: case AArch64::ST2Twov2d: case AArch64::ST2Twov2s: case AArch64::ST2Twov4h: case AArch64::ST2Twov4s: case AArch64::ST2Twov8b: case AArch64::ST2Twov8h: case AArch64::ST2Twov16b: case AArch64::ST3Threev2d: case AArch64::ST3Threev2s: case AArch64::ST3Threev4h: case AArch64::ST3Threev4s: case AArch64::ST3Threev8b: case AArch64::ST3Threev8h: case AArch64::ST3Threev16b: case AArch64::ST4Fourv2d: case AArch64::ST4Fourv2s: case AArch64::ST4Fourv4h: case AArch64::ST4Fourv4s: case AArch64::ST4Fourv8b: case AArch64::ST4Fourv8h: case AArch64::ST4Fourv16b: { switch (OpNum) { case 0: // op: Vt return 0; case 1: // op: Rn return 5; } break; } case AArch64::STL1: { switch (OpNum) { case 0: // op: Vt return 0; case 2: // op: Rn return 5; case 1: // op: Q return 30; } break; } case AArch64::ST1i8: case AArch64::ST2i8: case AArch64::ST3i8: case AArch64::ST4i8: { switch (OpNum) { case 0: // op: Vt return 0; case 2: // op: Rn return 5; case 1: // op: idx return 10; } break; } case AArch64::ST1i16: case AArch64::ST2i16: case AArch64::ST3i16: case AArch64::ST4i16: { switch (OpNum) { case 0: // op: Vt return 0; case 2: // op: Rn return 5; case 1: // op: idx return 11; } break; } case AArch64::ST1i32: case AArch64::ST2i32: case AArch64::ST3i32: case AArch64::ST4i32: { switch (OpNum) { case 0: // op: Vt return 0; case 2: // op: Rn return 5; case 1: // op: idx return 12; } break; } case AArch64::ST1i64: case AArch64::ST2i64: case AArch64::ST3i64: case AArch64::ST4i64: { switch (OpNum) { case 0: // op: Vt return 0; case 2: // op: Rn return 5; case 1: // op: idx return 30; } break; } case AArch64::STLXRB: case AArch64::STLXRH: case AArch64::STLXRW: case AArch64::STLXRX: case AArch64::STXRB: case AArch64::STXRH: case AArch64::STXRW: case AArch64::STXRX: { switch (OpNum) { case 0: // op: Ws return 16; case 1: // op: Rt return 0; case 2: // op: Rn return 5; } break; } case AArch64::STLXPW: case AArch64::STLXPX: case AArch64::STXPW: case AArch64::STXPX: { switch (OpNum) { case 0: // op: Ws return 16; case 1: // op: Rt return 0; case 2: // op: Rt2 return 10; case 3: // op: Rn return 5; } break; } case AArch64::ADR: case AArch64::ADRP: { switch (OpNum) { case 0: // op: Xd return 0; case 1: // op: label return 5; } break; } case AArch64::CPY_ZPzI_B: case AArch64::CPY_ZPzI_D: case AArch64::CPY_ZPzI_H: case AArch64::CPY_ZPzI_S: { switch (OpNum) { case 0: // op: Zd return 0; case 1: // op: Pg return 16; case 2: // op: imm return 5; } break; } case AArch64::LUTI2_ZZZI_H: { switch (OpNum) { case 0: // op: Zd return 0; case 1: // op: Zn return 5; case 2: // op: Zm return 16; case 3: // op: idx return 12; } break; } case AArch64::LUTI2_ZZZI_B: case AArch64::LUTI4_Z2ZZI_H: case AArch64::LUTI4_ZZZI_H: { switch (OpNum) { case 0: // op: Zd return 0; case 1: // op: Zn return 5; case 2: // op: Zm return 16; case 3: // op: idx return 22; } break; } case AArch64::LUTI4_ZZZI_B: { switch (OpNum) { case 0: // op: Zd return 0; case 1: // op: Zn return 5; case 2: // op: Zm return 16; case 3: // op: idx return 23; } break; } case AArch64::SMULLB_ZZZI_D: case AArch64::SMULLB_ZZZI_S: case AArch64::SMULLT_ZZZI_D: case AArch64::SMULLT_ZZZI_S: case AArch64::SQDMULLB_ZZZI_D: case AArch64::SQDMULLB_ZZZI_S: case AArch64::SQDMULLT_ZZZI_D: case AArch64::SQDMULLT_ZZZI_S: case AArch64::UMULLB_ZZZI_D: case AArch64::UMULLB_ZZZI_S: case AArch64::UMULLT_ZZZI_D: case AArch64::UMULLT_ZZZI_S: { switch (OpNum) { case 0: // op: Zd return 0; case 1: // op: Zn return 5; case 2: // op: Zm return 16; case 3: // op: iop return 11; } break; } case AArch64::BFMUL_ZZZI: case AArch64::FMUL_ZZZI_H: case AArch64::FMUL_ZZZI_S: case AArch64::MUL_ZZZI_H: case AArch64::MUL_ZZZI_S: case AArch64::SQDMULH_ZZZI_H: case AArch64::SQDMULH_ZZZI_S: case AArch64::SQRDMULH_ZZZI_H: case AArch64::SQRDMULH_ZZZI_S: { switch (OpNum) { case 0: // op: Zd return 0; case 1: // op: Zn return 5; case 2: // op: Zm return 16; case 3: // op: iop return 19; } break; } case AArch64::FMUL_ZZZI_D: case AArch64::MUL_ZZZI_D: case AArch64::SQDMULH_ZZZI_D: case AArch64::SQRDMULH_ZZZI_D: { switch (OpNum) { case 0: // op: Zd return 0; case 1: // op: Zn return 5; case 2: // op: Zm return 16; case 3: // op: iop return 20; } break; } case AArch64::ADDHNB_ZZZ_B: case AArch64::ADDHNB_ZZZ_H: case AArch64::ADDHNB_ZZZ_S: case AArch64::ADR_LSL_ZZZ_D_0: case AArch64::ADR_LSL_ZZZ_D_1: case AArch64::ADR_LSL_ZZZ_D_2: case AArch64::ADR_LSL_ZZZ_D_3: case AArch64::ADR_LSL_ZZZ_S_0: case AArch64::ADR_LSL_ZZZ_S_1: case AArch64::ADR_LSL_ZZZ_S_2: case AArch64::ADR_LSL_ZZZ_S_3: case AArch64::ADR_SXTW_ZZZ_D_0: case AArch64::ADR_SXTW_ZZZ_D_1: case AArch64::ADR_SXTW_ZZZ_D_2: case AArch64::ADR_SXTW_ZZZ_D_3: case AArch64::ADR_UXTW_ZZZ_D_0: case AArch64::ADR_UXTW_ZZZ_D_1: case AArch64::ADR_UXTW_ZZZ_D_2: case AArch64::ADR_UXTW_ZZZ_D_3: case AArch64::BDEP_ZZZ_B: case AArch64::BDEP_ZZZ_D: case AArch64::BDEP_ZZZ_H: case AArch64::BDEP_ZZZ_S: case AArch64::BEXT_ZZZ_B: case AArch64::BEXT_ZZZ_D: case AArch64::BEXT_ZZZ_H: case AArch64::BEXT_ZZZ_S: case AArch64::BGRP_ZZZ_B: case AArch64::BGRP_ZZZ_D: case AArch64::BGRP_ZZZ_H: case AArch64::BGRP_ZZZ_S: case AArch64::HISTSEG_ZZZ: case AArch64::PMULLB_ZZZ_D: case AArch64::PMULLB_ZZZ_H: case AArch64::PMULLB_ZZZ_Q: case AArch64::PMULLT_ZZZ_D: case AArch64::PMULLT_ZZZ_H: case AArch64::PMULLT_ZZZ_Q: case AArch64::RADDHNB_ZZZ_B: case AArch64::RADDHNB_ZZZ_H: case AArch64::RADDHNB_ZZZ_S: case AArch64::RAX1_ZZZ_D: case AArch64::RSUBHNB_ZZZ_B: case AArch64::RSUBHNB_ZZZ_H: case AArch64::RSUBHNB_ZZZ_S: case AArch64::SABDLB_ZZZ_D: case AArch64::SABDLB_ZZZ_H: case AArch64::SABDLB_ZZZ_S: case AArch64::SABDLT_ZZZ_D: case AArch64::SABDLT_ZZZ_H: case AArch64::SABDLT_ZZZ_S: case AArch64::SADDLBT_ZZZ_D: case AArch64::SADDLBT_ZZZ_H: case AArch64::SADDLBT_ZZZ_S: case AArch64::SADDLB_ZZZ_D: case AArch64::SADDLB_ZZZ_H: case AArch64::SADDLB_ZZZ_S: case AArch64::SADDLT_ZZZ_D: case AArch64::SADDLT_ZZZ_H: case AArch64::SADDLT_ZZZ_S: case AArch64::SADDWB_ZZZ_D: case AArch64::SADDWB_ZZZ_H: case AArch64::SADDWB_ZZZ_S: case AArch64::SADDWT_ZZZ_D: case AArch64::SADDWT_ZZZ_H: case AArch64::SADDWT_ZZZ_S: case AArch64::SM4EKEY_ZZZ_S: case AArch64::SMULLB_ZZZ_D: case AArch64::SMULLB_ZZZ_H: case AArch64::SMULLB_ZZZ_S: case AArch64::SMULLT_ZZZ_D: case AArch64::SMULLT_ZZZ_H: case AArch64::SMULLT_ZZZ_S: case AArch64::SQDMULLB_ZZZ_D: case AArch64::SQDMULLB_ZZZ_H: case AArch64::SQDMULLB_ZZZ_S: case AArch64::SQDMULLT_ZZZ_D: case AArch64::SQDMULLT_ZZZ_H: case AArch64::SQDMULLT_ZZZ_S: case AArch64::SSUBLBT_ZZZ_D: case AArch64::SSUBLBT_ZZZ_H: case AArch64::SSUBLBT_ZZZ_S: case AArch64::SSUBLB_ZZZ_D: case AArch64::SSUBLB_ZZZ_H: case AArch64::SSUBLB_ZZZ_S: case AArch64::SSUBLTB_ZZZ_D: case AArch64::SSUBLTB_ZZZ_H: case AArch64::SSUBLTB_ZZZ_S: case AArch64::SSUBLT_ZZZ_D: case AArch64::SSUBLT_ZZZ_H: case AArch64::SSUBLT_ZZZ_S: case AArch64::SSUBWB_ZZZ_D: case AArch64::SSUBWB_ZZZ_H: case AArch64::SSUBWB_ZZZ_S: case AArch64::SSUBWT_ZZZ_D: case AArch64::SSUBWT_ZZZ_H: case AArch64::SSUBWT_ZZZ_S: case AArch64::SUBHNB_ZZZ_B: case AArch64::SUBHNB_ZZZ_H: case AArch64::SUBHNB_ZZZ_S: case AArch64::TBLQ_ZZZ_B: case AArch64::TBLQ_ZZZ_D: case AArch64::TBLQ_ZZZ_H: case AArch64::TBLQ_ZZZ_S: case AArch64::UABDLB_ZZZ_D: case AArch64::UABDLB_ZZZ_H: case AArch64::UABDLB_ZZZ_S: case AArch64::UABDLT_ZZZ_D: case AArch64::UABDLT_ZZZ_H: case AArch64::UABDLT_ZZZ_S: case AArch64::UADDLB_ZZZ_D: case AArch64::UADDLB_ZZZ_H: case AArch64::UADDLB_ZZZ_S: case AArch64::UADDLT_ZZZ_D: case AArch64::UADDLT_ZZZ_H: case AArch64::UADDLT_ZZZ_S: case AArch64::UADDWB_ZZZ_D: case AArch64::UADDWB_ZZZ_H: case AArch64::UADDWB_ZZZ_S: case AArch64::UADDWT_ZZZ_D: case AArch64::UADDWT_ZZZ_H: case AArch64::UADDWT_ZZZ_S: case AArch64::UMULLB_ZZZ_D: case AArch64::UMULLB_ZZZ_H: case AArch64::UMULLB_ZZZ_S: case AArch64::UMULLT_ZZZ_D: case AArch64::UMULLT_ZZZ_H: case AArch64::UMULLT_ZZZ_S: case AArch64::USUBLB_ZZZ_D: case AArch64::USUBLB_ZZZ_H: case AArch64::USUBLB_ZZZ_S: case AArch64::USUBLT_ZZZ_D: case AArch64::USUBLT_ZZZ_H: case AArch64::USUBLT_ZZZ_S: case AArch64::USUBWB_ZZZ_D: case AArch64::USUBWB_ZZZ_H: case AArch64::USUBWB_ZZZ_S: case AArch64::USUBWT_ZZZ_D: case AArch64::USUBWT_ZZZ_H: case AArch64::USUBWT_ZZZ_S: case AArch64::UZPQ1_ZZZ_B: case AArch64::UZPQ1_ZZZ_D: case AArch64::UZPQ1_ZZZ_H: case AArch64::UZPQ1_ZZZ_S: case AArch64::UZPQ2_ZZZ_B: case AArch64::UZPQ2_ZZZ_D: case AArch64::UZPQ2_ZZZ_H: case AArch64::UZPQ2_ZZZ_S: case AArch64::ZIPQ1_ZZZ_B: case AArch64::ZIPQ1_ZZZ_D: case AArch64::ZIPQ1_ZZZ_H: case AArch64::ZIPQ1_ZZZ_S: case AArch64::ZIPQ2_ZZZ_B: case AArch64::ZIPQ2_ZZZ_D: case AArch64::ZIPQ2_ZZZ_H: case AArch64::ZIPQ2_ZZZ_S: { switch (OpNum) { case 0: // op: Zd return 0; case 1: // op: Zn return 5; case 2: // op: Zm return 16; } break; } case AArch64::DUP_ZZI_B: { switch (OpNum) { case 0: // op: Zd return 0; case 1: // op: Zn return 5; case 2: // op: idx return 17; } break; } case AArch64::DUP_ZZI_H: { switch (OpNum) { case 0: // op: Zd return 0; case 1: // op: Zn return 5; case 2: // op: idx return 18; } break; } case AArch64::DUP_ZZI_S: { switch (OpNum) { case 0: // op: Zd return 0; case 1: // op: Zn return 5; case 2: // op: idx return 19; } break; } case AArch64::DUP_ZZI_D: { switch (OpNum) { case 0: // op: Zd return 0; case 1: // op: Zn return 5; case 2: // op: idx return 20; } break; } case AArch64::DUP_ZZI_Q: { switch (OpNum) { case 0: // op: Zd return 0; case 1: // op: Zn return 5; case 2: // op: idx return 22; } break; } case AArch64::ASR_ZZI_B: case AArch64::ASR_ZZI_D: case AArch64::ASR_ZZI_H: case AArch64::ASR_ZZI_S: case AArch64::LSL_ZZI_B: case AArch64::LSL_ZZI_D: case AArch64::LSL_ZZI_H: case AArch64::LSL_ZZI_S: case AArch64::LSR_ZZI_B: case AArch64::LSR_ZZI_D: case AArch64::LSR_ZZI_H: case AArch64::LSR_ZZI_S: case AArch64::RSHRNB_ZZI_B: case AArch64::RSHRNB_ZZI_H: case AArch64::RSHRNB_ZZI_S: case AArch64::SHRNB_ZZI_B: case AArch64::SHRNB_ZZI_H: case AArch64::SHRNB_ZZI_S: case AArch64::SQRSHRNB_ZZI_B: case AArch64::SQRSHRNB_ZZI_H: case AArch64::SQRSHRNB_ZZI_S: case AArch64::SQRSHRUNB_ZZI_B: case AArch64::SQRSHRUNB_ZZI_H: case AArch64::SQRSHRUNB_ZZI_S: case AArch64::SQSHRNB_ZZI_B: case AArch64::SQSHRNB_ZZI_H: case AArch64::SQSHRNB_ZZI_S: case AArch64::SQSHRUNB_ZZI_B: case AArch64::SQSHRUNB_ZZI_H: case AArch64::SQSHRUNB_ZZI_S: case AArch64::SSHLLB_ZZI_D: case AArch64::SSHLLB_ZZI_H: case AArch64::SSHLLB_ZZI_S: case AArch64::SSHLLT_ZZI_D: case AArch64::SSHLLT_ZZI_H: case AArch64::SSHLLT_ZZI_S: case AArch64::UQRSHRNB_ZZI_B: case AArch64::UQRSHRNB_ZZI_H: case AArch64::UQRSHRNB_ZZI_S: case AArch64::UQSHRNB_ZZI_B: case AArch64::UQSHRNB_ZZI_H: case AArch64::UQSHRNB_ZZI_S: case AArch64::USHLLB_ZZI_D: case AArch64::USHLLB_ZZI_H: case AArch64::USHLLB_ZZI_S: case AArch64::USHLLT_ZZI_D: case AArch64::USHLLT_ZZI_H: case AArch64::USHLLT_ZZI_S: { switch (OpNum) { case 0: // op: Zd return 0; case 1: // op: Zn return 5; case 2: // op: imm return 16; } break; } case AArch64::EXT_ZZI_B: { switch (OpNum) { case 0: // op: Zd return 0; case 1: // op: Zn return 5; case 2: // op: imm8 return 10; } break; } case AArch64::DUPQ_ZZI_B: { switch (OpNum) { case 0: // op: Zd return 0; case 1: // op: Zn return 5; case 2: // op: index return 17; } break; } case AArch64::DUPQ_ZZI_H: { switch (OpNum) { case 0: // op: Zd return 0; case 1: // op: Zn return 5; case 2: // op: index return 18; } break; } case AArch64::DUPQ_ZZI_S: { switch (OpNum) { case 0: // op: Zd return 0; case 1: // op: Zn return 5; case 2: // op: index return 19; } break; } case AArch64::DUPQ_ZZI_D: { switch (OpNum) { case 0: // op: Zd return 0; case 1: // op: Zn return 5; case 2: // op: index return 20; } break; } case AArch64::BF1CVTLT_ZZ_BtoH: case AArch64::BF1CVT_ZZ_BtoH: case AArch64::BF2CVTLT_ZZ_BtoH: case AArch64::BF2CVT_ZZ_BtoH: case AArch64::F1CVTLT_ZZ_BtoH: case AArch64::F1CVT_ZZ_BtoH: case AArch64::F2CVTLT_ZZ_BtoH: case AArch64::F2CVT_ZZ_BtoH: case AArch64::FEXPA_ZZ_D: case AArch64::FEXPA_ZZ_H: case AArch64::FEXPA_ZZ_S: case AArch64::FRECPE_ZZ_D: case AArch64::FRECPE_ZZ_H: case AArch64::FRECPE_ZZ_S: case AArch64::FRSQRTE_ZZ_D: case AArch64::FRSQRTE_ZZ_H: case AArch64::FRSQRTE_ZZ_S: case AArch64::MOVPRFX_ZZ: case AArch64::REV_ZZ_B: case AArch64::REV_ZZ_D: case AArch64::REV_ZZ_H: case AArch64::REV_ZZ_S: case AArch64::SQXTNB_ZZ_B: case AArch64::SQXTNB_ZZ_H: case AArch64::SQXTNB_ZZ_S: case AArch64::SQXTUNB_ZZ_B: case AArch64::SQXTUNB_ZZ_H: case AArch64::SQXTUNB_ZZ_S: case AArch64::SUNPKHI_ZZ_D: case AArch64::SUNPKHI_ZZ_H: case AArch64::SUNPKHI_ZZ_S: case AArch64::SUNPKLO_ZZ_D: case AArch64::SUNPKLO_ZZ_H: case AArch64::SUNPKLO_ZZ_S: case AArch64::UQXTNB_ZZ_B: case AArch64::UQXTNB_ZZ_H: case AArch64::UQXTNB_ZZ_S: case AArch64::UUNPKHI_ZZ_D: case AArch64::UUNPKHI_ZZ_H: case AArch64::UUNPKHI_ZZ_S: case AArch64::UUNPKLO_ZZ_D: case AArch64::UUNPKLO_ZZ_H: case AArch64::UUNPKLO_ZZ_S: { switch (OpNum) { case 0: // op: Zd return 0; case 1: // op: Zn return 5; } break; } case AArch64::SQRSHRN_Z2ZI_StoH: case AArch64::SQRSHRUN_Z2ZI_StoH: case AArch64::UQRSHRN_Z2ZI_StoH: { switch (OpNum) { case 0: // op: Zd return 0; case 1: // op: Zn return 6; case 2: // op: imm4 return 16; } break; } case AArch64::BFCVTN_Z2Z_HtoB: case AArch64::FCVTNB_Z2Z_StoB: case AArch64::FCVTNT_Z2Z_StoB: case AArch64::FCVTN_Z2Z_HtoB: case AArch64::SQCVTN_Z2Z_StoH: case AArch64::SQCVTUN_Z2Z_StoH: case AArch64::UQCVTN_Z2Z_StoH: { switch (OpNum) { case 0: // op: Zd return 0; case 1: // op: Zn return 6; } break; } case AArch64::DUP_ZI_B: case AArch64::DUP_ZI_D: case AArch64::DUP_ZI_H: case AArch64::DUP_ZI_S: { switch (OpNum) { case 0: // op: Zd return 0; case 1: // op: imm return 5; } break; } case AArch64::INDEX_II_B: case AArch64::INDEX_II_D: case AArch64::INDEX_II_H: case AArch64::INDEX_II_S: { switch (OpNum) { case 0: // op: Zd return 0; case 1: // op: imm5 return 5; case 2: // op: imm5b return 16; } break; } case AArch64::FDUP_ZI_D: case AArch64::FDUP_ZI_H: case AArch64::FDUP_ZI_S: { switch (OpNum) { case 0: // op: Zd return 0; case 1: // op: imm8 return 5; } break; } case AArch64::DUPM_ZI: { switch (OpNum) { case 0: // op: Zd return 0; case 1: // op: imms return 5; } break; } case AArch64::BFCVTNT_ZPmZ: case AArch64::BFCVT_ZPmZ: case AArch64::RBIT_ZPmZ_B: case AArch64::RBIT_ZPmZ_D: case AArch64::RBIT_ZPmZ_H: case AArch64::RBIT_ZPmZ_S: case AArch64::REVB_ZPmZ_D: case AArch64::REVB_ZPmZ_H: case AArch64::REVB_ZPmZ_S: case AArch64::REVD_ZPmZ: case AArch64::REVH_ZPmZ_D: case AArch64::REVH_ZPmZ_S: case AArch64::REVW_ZPmZ_D: { switch (OpNum) { case 0: // op: Zd return 0; case 2: // op: Pg return 10; case 3: // op: Zn return 5; } break; } case AArch64::CPY_ZPmI_B: case AArch64::CPY_ZPmI_D: case AArch64::CPY_ZPmI_H: case AArch64::CPY_ZPmI_S: { switch (OpNum) { case 0: // op: Zd return 0; case 2: // op: Pg return 16; case 3: // op: imm return 5; } break; } case AArch64::INDEX_RR_B: case AArch64::INDEX_RR_D: case AArch64::INDEX_RR_H: case AArch64::INDEX_RR_S: { switch (OpNum) { case 0: // op: Zd return 0; case 2: // op: Rm return 16; case 1: // op: Rn return 5; } break; } case AArch64::ADD_ZZZ_B: case AArch64::ADD_ZZZ_CPA: case AArch64::ADD_ZZZ_D: case AArch64::ADD_ZZZ_H: case AArch64::ADD_ZZZ_S: case AArch64::AND_ZZZ: case AArch64::ASR_WIDE_ZZZ_B: case AArch64::ASR_WIDE_ZZZ_H: case AArch64::ASR_WIDE_ZZZ_S: case AArch64::BFADD_ZZZ: case AArch64::BFMUL_ZZZ: case AArch64::BFSUB_ZZZ: case AArch64::BIC_ZZZ: case AArch64::EOR_ZZZ: case AArch64::FADD_ZZZ_D: case AArch64::FADD_ZZZ_H: case AArch64::FADD_ZZZ_S: case AArch64::FMUL_ZZZ_D: case AArch64::FMUL_ZZZ_H: case AArch64::FMUL_ZZZ_S: case AArch64::FRECPS_ZZZ_D: case AArch64::FRECPS_ZZZ_H: case AArch64::FRECPS_ZZZ_S: case AArch64::FRSQRTS_ZZZ_D: case AArch64::FRSQRTS_ZZZ_H: case AArch64::FRSQRTS_ZZZ_S: case AArch64::FSUB_ZZZ_D: case AArch64::FSUB_ZZZ_H: case AArch64::FSUB_ZZZ_S: case AArch64::FTSMUL_ZZZ_D: case AArch64::FTSMUL_ZZZ_H: case AArch64::FTSMUL_ZZZ_S: case AArch64::FTSSEL_ZZZ_D: case AArch64::FTSSEL_ZZZ_H: case AArch64::FTSSEL_ZZZ_S: case AArch64::LSL_WIDE_ZZZ_B: case AArch64::LSL_WIDE_ZZZ_H: case AArch64::LSL_WIDE_ZZZ_S: case AArch64::LSR_WIDE_ZZZ_B: case AArch64::LSR_WIDE_ZZZ_H: case AArch64::LSR_WIDE_ZZZ_S: case AArch64::MUL_ZZZ_B: case AArch64::MUL_ZZZ_D: case AArch64::MUL_ZZZ_H: case AArch64::MUL_ZZZ_S: case AArch64::ORR_ZZZ: case AArch64::PMUL_ZZZ_B: case AArch64::SMULH_ZZZ_B: case AArch64::SMULH_ZZZ_D: case AArch64::SMULH_ZZZ_H: case AArch64::SMULH_ZZZ_S: case AArch64::SQADD_ZZZ_B: case AArch64::SQADD_ZZZ_D: case AArch64::SQADD_ZZZ_H: case AArch64::SQADD_ZZZ_S: case AArch64::SQDMULH_ZZZ_B: case AArch64::SQDMULH_ZZZ_D: case AArch64::SQDMULH_ZZZ_H: case AArch64::SQDMULH_ZZZ_S: case AArch64::SQRDMULH_ZZZ_B: case AArch64::SQRDMULH_ZZZ_D: case AArch64::SQRDMULH_ZZZ_H: case AArch64::SQRDMULH_ZZZ_S: case AArch64::SQSUB_ZZZ_B: case AArch64::SQSUB_ZZZ_D: case AArch64::SQSUB_ZZZ_H: case AArch64::SQSUB_ZZZ_S: case AArch64::SUB_ZZZ_B: case AArch64::SUB_ZZZ_CPA: case AArch64::SUB_ZZZ_D: case AArch64::SUB_ZZZ_H: case AArch64::SUB_ZZZ_S: case AArch64::TBL_ZZZZ_B: case AArch64::TBL_ZZZZ_D: case AArch64::TBL_ZZZZ_H: case AArch64::TBL_ZZZZ_S: case AArch64::TBL_ZZZ_B: case AArch64::TBL_ZZZ_D: case AArch64::TBL_ZZZ_H: case AArch64::TBL_ZZZ_S: case AArch64::TRN1_ZZZ_B: case AArch64::TRN1_ZZZ_D: case AArch64::TRN1_ZZZ_H: case AArch64::TRN1_ZZZ_Q: case AArch64::TRN1_ZZZ_S: case AArch64::TRN2_ZZZ_B: case AArch64::TRN2_ZZZ_D: case AArch64::TRN2_ZZZ_H: case AArch64::TRN2_ZZZ_Q: case AArch64::TRN2_ZZZ_S: case AArch64::UMULH_ZZZ_B: case AArch64::UMULH_ZZZ_D: case AArch64::UMULH_ZZZ_H: case AArch64::UMULH_ZZZ_S: case AArch64::UQADD_ZZZ_B: case AArch64::UQADD_ZZZ_D: case AArch64::UQADD_ZZZ_H: case AArch64::UQADD_ZZZ_S: case AArch64::UQSUB_ZZZ_B: case AArch64::UQSUB_ZZZ_D: case AArch64::UQSUB_ZZZ_H: case AArch64::UQSUB_ZZZ_S: case AArch64::UZP1_ZZZ_B: case AArch64::UZP1_ZZZ_D: case AArch64::UZP1_ZZZ_H: case AArch64::UZP1_ZZZ_Q: case AArch64::UZP1_ZZZ_S: case AArch64::UZP2_ZZZ_B: case AArch64::UZP2_ZZZ_D: case AArch64::UZP2_ZZZ_H: case AArch64::UZP2_ZZZ_Q: case AArch64::UZP2_ZZZ_S: case AArch64::ZIP1_ZZZ_B: case AArch64::ZIP1_ZZZ_D: case AArch64::ZIP1_ZZZ_H: case AArch64::ZIP1_ZZZ_Q: case AArch64::ZIP1_ZZZ_S: case AArch64::ZIP2_ZZZ_B: case AArch64::ZIP2_ZZZ_D: case AArch64::ZIP2_ZZZ_H: case AArch64::ZIP2_ZZZ_Q: case AArch64::ZIP2_ZZZ_S: { switch (OpNum) { case 0: // op: Zd return 0; case 2: // op: Zm return 16; case 1: // op: Zn return 5; } break; } case AArch64::HISTCNT_ZPzZZ_D: case AArch64::HISTCNT_ZPzZZ_S: { switch (OpNum) { case 0: // op: Zd return 0; case 2: // op: Zn return 5; case 1: // op: Pg return 10; case 3: // op: Zm return 16; } break; } case AArch64::ADDHNT_ZZZ_B: case AArch64::ADDHNT_ZZZ_H: case AArch64::ADDHNT_ZZZ_S: case AArch64::EORBT_ZZZ_B: case AArch64::EORBT_ZZZ_D: case AArch64::EORBT_ZZZ_H: case AArch64::EORBT_ZZZ_S: case AArch64::EORTB_ZZZ_B: case AArch64::EORTB_ZZZ_D: case AArch64::EORTB_ZZZ_H: case AArch64::EORTB_ZZZ_S: case AArch64::RADDHNT_ZZZ_B: case AArch64::RADDHNT_ZZZ_H: case AArch64::RADDHNT_ZZZ_S: case AArch64::RSUBHNT_ZZZ_B: case AArch64::RSUBHNT_ZZZ_H: case AArch64::RSUBHNT_ZZZ_S: case AArch64::SUBHNT_ZZZ_B: case AArch64::SUBHNT_ZZZ_H: case AArch64::SUBHNT_ZZZ_S: { switch (OpNum) { case 0: // op: Zd return 0; case 2: // op: Zn return 5; case 3: // op: Zm return 16; } break; } case AArch64::RSHRNT_ZZI_B: case AArch64::RSHRNT_ZZI_H: case AArch64::RSHRNT_ZZI_S: case AArch64::SHRNT_ZZI_B: case AArch64::SHRNT_ZZI_H: case AArch64::SHRNT_ZZI_S: case AArch64::SLI_ZZI_B: case AArch64::SLI_ZZI_D: case AArch64::SLI_ZZI_H: case AArch64::SLI_ZZI_S: case AArch64::SQRSHRNT_ZZI_B: case AArch64::SQRSHRNT_ZZI_H: case AArch64::SQRSHRNT_ZZI_S: case AArch64::SQRSHRUNT_ZZI_B: case AArch64::SQRSHRUNT_ZZI_H: case AArch64::SQRSHRUNT_ZZI_S: case AArch64::SQSHRNT_ZZI_B: case AArch64::SQSHRNT_ZZI_H: case AArch64::SQSHRNT_ZZI_S: case AArch64::SQSHRUNT_ZZI_B: case AArch64::SQSHRUNT_ZZI_H: case AArch64::SQSHRUNT_ZZI_S: case AArch64::SRI_ZZI_B: case AArch64::SRI_ZZI_D: case AArch64::SRI_ZZI_H: case AArch64::SRI_ZZI_S: case AArch64::UQRSHRNT_ZZI_B: case AArch64::UQRSHRNT_ZZI_H: case AArch64::UQRSHRNT_ZZI_S: case AArch64::UQSHRNT_ZZI_B: case AArch64::UQSHRNT_ZZI_H: case AArch64::UQSHRNT_ZZI_S: { switch (OpNum) { case 0: // op: Zd return 0; case 2: // op: Zn return 5; case 3: // op: imm return 16; } break; } case AArch64::SQXTNT_ZZ_B: case AArch64::SQXTNT_ZZ_H: case AArch64::SQXTNT_ZZ_S: case AArch64::SQXTUNT_ZZ_B: case AArch64::SQXTUNT_ZZ_H: case AArch64::SQXTUNT_ZZ_S: case AArch64::UQXTNT_ZZ_B: case AArch64::UQXTNT_ZZ_H: case AArch64::UQXTNT_ZZ_S: { switch (OpNum) { case 0: // op: Zd return 0; case 2: // op: Zn return 5; } break; } case AArch64::PMOV_ZIP_D: case AArch64::PMOV_ZIP_H: case AArch64::PMOV_ZIP_S: { switch (OpNum) { case 0: // op: Zd return 0; case 3: // op: Pn return 5; case 2: // op: index return 17; } break; } case AArch64::PMOV_ZIP_B: { switch (OpNum) { case 0: // op: Zd return 0; case 3: // op: Pn return 5; } break; } case AArch64::TBXQ_ZZZ_B: case AArch64::TBXQ_ZZZ_D: case AArch64::TBXQ_ZZZ_H: case AArch64::TBXQ_ZZZ_S: case AArch64::TBX_ZZZ_B: case AArch64::TBX_ZZZ_D: case AArch64::TBX_ZZZ_H: case AArch64::TBX_ZZZ_S: { switch (OpNum) { case 0: // op: Zd return 0; case 3: // op: Zm return 16; case 2: // op: Zn return 5; } break; } case AArch64::FCVTLT_ZPmZ_HtoS: case AArch64::FCVTLT_ZPmZ_StoD: case AArch64::FCVTNT_ZPmZ_DtoS: case AArch64::FCVTNT_ZPmZ_StoH: case AArch64::FCVTXNT_ZPmZ_DtoS: { switch (OpNum) { case 0: // op: Zd return 0; case 3: // op: Zn return 5; case 2: // op: Pg return 10; } break; } case AArch64::MOVA_2ZMXI_H_D: case AArch64::MOVA_2ZMXI_V_D: { switch (OpNum) { case 0: // op: Zd return 1; case 2: // op: Rs return 13; case 1: // op: ZAn return 5; } break; } case AArch64::MOVA_2ZMXI_H_S: case AArch64::MOVA_2ZMXI_V_S: { switch (OpNum) { case 0: // op: Zd return 1; case 2: // op: Rs return 13; case 1: // op: ZAn return 6; case 3: // op: imm return 5; } break; } case AArch64::MOVA_2ZMXI_H_H: case AArch64::MOVA_2ZMXI_V_H: { switch (OpNum) { case 0: // op: Zd return 1; case 2: // op: Rs return 13; case 1: // op: ZAn return 7; case 3: // op: imm return 5; } break; } case AArch64::MOVA_2ZMXI_H_B: case AArch64::MOVA_2ZMXI_V_B: { switch (OpNum) { case 0: // op: Zd return 1; case 2: // op: Rs return 13; case 3: // op: imm return 5; } break; } case AArch64::UZP_VG2_2ZZZ_B: case AArch64::UZP_VG2_2ZZZ_D: case AArch64::UZP_VG2_2ZZZ_H: case AArch64::UZP_VG2_2ZZZ_Q: case AArch64::UZP_VG2_2ZZZ_S: case AArch64::ZIP_VG2_2ZZZ_B: case AArch64::ZIP_VG2_2ZZZ_D: case AArch64::ZIP_VG2_2ZZZ_H: case AArch64::ZIP_VG2_2ZZZ_Q: case AArch64::ZIP_VG2_2ZZZ_S: { switch (OpNum) { case 0: // op: Zd return 1; case 2: // op: Zm return 16; case 1: // op: Zn return 5; } break; } case AArch64::MOVAZ_2ZMI_H_D: case AArch64::MOVAZ_2ZMI_V_D: { switch (OpNum) { case 0: // op: Zd return 1; case 3: // op: Rs return 13; case 2: // op: ZAn return 5; } break; } case AArch64::MOVAZ_2ZMI_H_S: case AArch64::MOVAZ_2ZMI_V_S: { switch (OpNum) { case 0: // op: Zd return 1; case 3: // op: Rs return 13; case 2: // op: ZAn return 6; case 4: // op: imm return 5; } break; } case AArch64::MOVAZ_2ZMI_H_H: case AArch64::MOVAZ_2ZMI_V_H: { switch (OpNum) { case 0: // op: Zd return 1; case 3: // op: Rs return 13; case 2: // op: ZAn return 7; case 4: // op: imm return 5; } break; } case AArch64::MOVAZ_2ZMI_H_B: case AArch64::MOVAZ_2ZMI_V_B: { switch (OpNum) { case 0: // op: Zd return 1; case 3: // op: Rs return 13; case 4: // op: imm return 5; } break; } case AArch64::MOVA_4ZMXI_H_D: case AArch64::MOVA_4ZMXI_H_S: case AArch64::MOVA_4ZMXI_V_D: case AArch64::MOVA_4ZMXI_V_S: { switch (OpNum) { case 0: // op: Zd return 2; case 2: // op: Rs return 13; case 1: // op: ZAn return 5; } break; } case AArch64::MOVA_4ZMXI_H_H: case AArch64::MOVA_4ZMXI_V_H: { switch (OpNum) { case 0: // op: Zd return 2; case 2: // op: Rs return 13; case 1: // op: ZAn return 6; case 3: // op: imm return 5; } break; } case AArch64::MOVA_4ZMXI_H_B: case AArch64::MOVA_4ZMXI_V_B: { switch (OpNum) { case 0: // op: Zd return 2; case 2: // op: Rs return 13; case 3: // op: imm return 5; } break; } case AArch64::MOVAZ_4ZMI_H_D: case AArch64::MOVAZ_4ZMI_H_S: case AArch64::MOVAZ_4ZMI_V_D: case AArch64::MOVAZ_4ZMI_V_S: { switch (OpNum) { case 0: // op: Zd return 2; case 3: // op: Rs return 13; case 2: // op: ZAn return 5; } break; } case AArch64::MOVAZ_4ZMI_H_H: case AArch64::MOVAZ_4ZMI_V_H: { switch (OpNum) { case 0: // op: Zd return 2; case 3: // op: Rs return 13; case 2: // op: ZAn return 6; case 4: // op: imm return 5; } break; } case AArch64::MOVAZ_4ZMI_H_B: case AArch64::MOVAZ_4ZMI_V_B: { switch (OpNum) { case 0: // op: Zd return 2; case 3: // op: Rs return 13; case 4: // op: imm return 5; } break; } case AArch64::FCMLA_ZPmZZ_D: case AArch64::FCMLA_ZPmZZ_H: case AArch64::FCMLA_ZPmZZ_S: { switch (OpNum) { case 0: // op: Zda return 0; case 1: // op: Pg return 10; case 3: // op: Zn return 5; case 4: // op: Zm return 16; case 5: // op: imm return 13; } break; } case AArch64::SDOT_ZZZI_HtoS: case AArch64::UDOT_ZZZI_HtoS: { switch (OpNum) { case 0: // op: Zda return 0; case 2: // op: Zn return 5; case 3: // op: Zm return 16; case 4: // op: i2 return 19; } break; } case AArch64::SUDOT_ZZZI: case AArch64::USDOT_ZZZI: { switch (OpNum) { case 0: // op: Zda return 0; case 2: // op: Zn return 5; case 3: // op: Zm return 16; case 4: // op: idx return 19; } break; } case AArch64::FMLALB_ZZZI: case AArch64::FMLALLBB_ZZZI: case AArch64::FMLALLBT_ZZZI: case AArch64::FMLALLTB_ZZZI: case AArch64::FMLALLTT_ZZZI: case AArch64::FMLALT_ZZZI: { switch (OpNum) { case 0: // op: Zda return 0; case 2: // op: Zn return 5; case 3: // op: Zm return 16; case 4: // op: imm4 return 10; } break; } case AArch64::BFMLALB_ZZZI: case AArch64::BFMLALT_ZZZI: case AArch64::BFMLSLB_ZZZI_S: case AArch64::BFMLSLT_ZZZI_S: case AArch64::FDOT_ZZZI_BtoH: case AArch64::FMLALB_ZZZI_SHH: case AArch64::FMLALT_ZZZI_SHH: case AArch64::FMLSLB_ZZZI_SHH: case AArch64::FMLSLT_ZZZI_SHH: case AArch64::SMLALB_ZZZI_D: case AArch64::SMLALB_ZZZI_S: case AArch64::SMLALT_ZZZI_D: case AArch64::SMLALT_ZZZI_S: case AArch64::SMLSLB_ZZZI_D: case AArch64::SMLSLB_ZZZI_S: case AArch64::SMLSLT_ZZZI_D: case AArch64::SMLSLT_ZZZI_S: case AArch64::SQDMLALB_ZZZI_D: case AArch64::SQDMLALB_ZZZI_S: case AArch64::SQDMLALT_ZZZI_D: case AArch64::SQDMLALT_ZZZI_S: case AArch64::SQDMLSLB_ZZZI_D: case AArch64::SQDMLSLB_ZZZI_S: case AArch64::SQDMLSLT_ZZZI_D: case AArch64::SQDMLSLT_ZZZI_S: case AArch64::UMLALB_ZZZI_D: case AArch64::UMLALB_ZZZI_S: case AArch64::UMLALT_ZZZI_D: case AArch64::UMLALT_ZZZI_S: case AArch64::UMLSLB_ZZZI_D: case AArch64::UMLSLB_ZZZI_S: case AArch64::UMLSLT_ZZZI_D: case AArch64::UMLSLT_ZZZI_S: { switch (OpNum) { case 0: // op: Zda return 0; case 2: // op: Zn return 5; case 3: // op: Zm return 16; case 4: // op: iop return 11; } break; } case AArch64::BFDOT_ZZI: case AArch64::BFMLA_ZZZI: case AArch64::BFMLS_ZZZI: case AArch64::FDOT_ZZZI_BtoS: case AArch64::FDOT_ZZZI_S: case AArch64::FMLA_ZZZI_H: case AArch64::FMLA_ZZZI_S: case AArch64::FMLS_ZZZI_H: case AArch64::FMLS_ZZZI_S: case AArch64::MLA_ZZZI_H: case AArch64::MLA_ZZZI_S: case AArch64::MLS_ZZZI_H: case AArch64::MLS_ZZZI_S: case AArch64::SQRDMLAH_ZZZI_H: case AArch64::SQRDMLAH_ZZZI_S: case AArch64::SQRDMLSH_ZZZI_H: case AArch64::SQRDMLSH_ZZZI_S: { switch (OpNum) { case 0: // op: Zda return 0; case 2: // op: Zn return 5; case 3: // op: Zm return 16; case 4: // op: iop return 19; } break; } case AArch64::FMLA_ZZZI_D: case AArch64::FMLS_ZZZI_D: case AArch64::MLA_ZZZI_D: case AArch64::MLS_ZZZI_D: case AArch64::SQRDMLAH_ZZZI_D: case AArch64::SQRDMLSH_ZZZI_D: { switch (OpNum) { case 0: // op: Zda return 0; case 2: // op: Zn return 5; case 3: // op: Zm return 16; case 4: // op: iop return 20; } break; } case AArch64::CDOT_ZZZ_D: case AArch64::CDOT_ZZZ_S: case AArch64::CMLA_ZZZ_B: case AArch64::CMLA_ZZZ_D: case AArch64::CMLA_ZZZ_H: case AArch64::CMLA_ZZZ_S: case AArch64::SQRDCMLAH_ZZZ_B: case AArch64::SQRDCMLAH_ZZZ_D: case AArch64::SQRDCMLAH_ZZZ_H: case AArch64::SQRDCMLAH_ZZZ_S: { switch (OpNum) { case 0: // op: Zda return 0; case 2: // op: Zn return 5; case 3: // op: Zm return 16; case 4: // op: rot return 10; } break; } case AArch64::ADCLB_ZZZ_D: case AArch64::ADCLB_ZZZ_S: case AArch64::ADCLT_ZZZ_D: case AArch64::ADCLT_ZZZ_S: case AArch64::BFDOT_ZZZ: case AArch64::BFMLALB_ZZZ: case AArch64::BFMLALT_ZZZ: case AArch64::BFMLSLB_ZZZ_S: case AArch64::BFMLSLT_ZZZ_S: case AArch64::FDOT_ZZZ_BtoH: case AArch64::FDOT_ZZZ_BtoS: case AArch64::FDOT_ZZZ_S: case AArch64::FMLALB_ZZZ: case AArch64::FMLALB_ZZZ_SHH: case AArch64::FMLALLBB_ZZZ: case AArch64::FMLALLBT_ZZZ: case AArch64::FMLALLTB_ZZZ: case AArch64::FMLALLTT_ZZZ: case AArch64::FMLALT_ZZZ: case AArch64::FMLALT_ZZZ_SHH: case AArch64::FMLSLB_ZZZ_SHH: case AArch64::FMLSLT_ZZZ_SHH: case AArch64::FMMLA_ZZZ_D: case AArch64::FMMLA_ZZZ_S: case AArch64::MLA_CPA: case AArch64::SABALB_ZZZ_D: case AArch64::SABALB_ZZZ_H: case AArch64::SABALB_ZZZ_S: case AArch64::SABALT_ZZZ_D: case AArch64::SABALT_ZZZ_H: case AArch64::SABALT_ZZZ_S: case AArch64::SABA_ZZZ_B: case AArch64::SABA_ZZZ_D: case AArch64::SABA_ZZZ_H: case AArch64::SABA_ZZZ_S: case AArch64::SBCLB_ZZZ_D: case AArch64::SBCLB_ZZZ_S: case AArch64::SBCLT_ZZZ_D: case AArch64::SBCLT_ZZZ_S: case AArch64::SDOT_ZZZ_D: case AArch64::SDOT_ZZZ_HtoS: case AArch64::SDOT_ZZZ_S: case AArch64::SMLALB_ZZZ_D: case AArch64::SMLALB_ZZZ_H: case AArch64::SMLALB_ZZZ_S: case AArch64::SMLALT_ZZZ_D: case AArch64::SMLALT_ZZZ_H: case AArch64::SMLALT_ZZZ_S: case AArch64::SMLSLB_ZZZ_D: case AArch64::SMLSLB_ZZZ_H: case AArch64::SMLSLB_ZZZ_S: case AArch64::SMLSLT_ZZZ_D: case AArch64::SMLSLT_ZZZ_H: case AArch64::SMLSLT_ZZZ_S: case AArch64::SMMLA_ZZZ: case AArch64::SQDMLALBT_ZZZ_D: case AArch64::SQDMLALBT_ZZZ_H: case AArch64::SQDMLALBT_ZZZ_S: case AArch64::SQDMLALB_ZZZ_D: case AArch64::SQDMLALB_ZZZ_H: case AArch64::SQDMLALB_ZZZ_S: case AArch64::SQDMLALT_ZZZ_D: case AArch64::SQDMLALT_ZZZ_H: case AArch64::SQDMLALT_ZZZ_S: case AArch64::SQDMLSLBT_ZZZ_D: case AArch64::SQDMLSLBT_ZZZ_H: case AArch64::SQDMLSLBT_ZZZ_S: case AArch64::SQDMLSLB_ZZZ_D: case AArch64::SQDMLSLB_ZZZ_H: case AArch64::SQDMLSLB_ZZZ_S: case AArch64::SQDMLSLT_ZZZ_D: case AArch64::SQDMLSLT_ZZZ_H: case AArch64::SQDMLSLT_ZZZ_S: case AArch64::SQRDMLAH_ZZZ_B: case AArch64::SQRDMLAH_ZZZ_D: case AArch64::SQRDMLAH_ZZZ_H: case AArch64::SQRDMLAH_ZZZ_S: case AArch64::SQRDMLSH_ZZZ_B: case AArch64::SQRDMLSH_ZZZ_D: case AArch64::SQRDMLSH_ZZZ_H: case AArch64::SQRDMLSH_ZZZ_S: case AArch64::UABALB_ZZZ_D: case AArch64::UABALB_ZZZ_H: case AArch64::UABALB_ZZZ_S: case AArch64::UABALT_ZZZ_D: case AArch64::UABALT_ZZZ_H: case AArch64::UABALT_ZZZ_S: case AArch64::UABA_ZZZ_B: case AArch64::UABA_ZZZ_D: case AArch64::UABA_ZZZ_H: case AArch64::UABA_ZZZ_S: case AArch64::UDOT_ZZZ_D: case AArch64::UDOT_ZZZ_HtoS: case AArch64::UDOT_ZZZ_S: case AArch64::UMLALB_ZZZ_D: case AArch64::UMLALB_ZZZ_H: case AArch64::UMLALB_ZZZ_S: case AArch64::UMLALT_ZZZ_D: case AArch64::UMLALT_ZZZ_H: case AArch64::UMLALT_ZZZ_S: case AArch64::UMLSLB_ZZZ_D: case AArch64::UMLSLB_ZZZ_H: case AArch64::UMLSLB_ZZZ_S: case AArch64::UMLSLT_ZZZ_D: case AArch64::UMLSLT_ZZZ_H: case AArch64::UMLSLT_ZZZ_S: case AArch64::UMMLA_ZZZ: case AArch64::USDOT_ZZZ: case AArch64::USMMLA_ZZZ: { switch (OpNum) { case 0: // op: Zda return 0; case 2: // op: Zn return 5; case 3: // op: Zm return 16; } break; } case AArch64::SRSRA_ZZI_B: case AArch64::SRSRA_ZZI_D: case AArch64::SRSRA_ZZI_H: case AArch64::SRSRA_ZZI_S: case AArch64::SSRA_ZZI_B: case AArch64::SSRA_ZZI_D: case AArch64::SSRA_ZZI_H: case AArch64::SSRA_ZZI_S: case AArch64::URSRA_ZZI_B: case AArch64::URSRA_ZZI_D: case AArch64::URSRA_ZZI_H: case AArch64::URSRA_ZZI_S: case AArch64::USRA_ZZI_B: case AArch64::USRA_ZZI_D: case AArch64::USRA_ZZI_H: case AArch64::USRA_ZZI_S: { switch (OpNum) { case 0: // op: Zda return 0; case 2: // op: Zn return 5; case 3: // op: imm return 16; } break; } case AArch64::SDOT_ZZZI_S: case AArch64::UDOT_ZZZI_S: { switch (OpNum) { case 0: // op: Zda return 0; case 2: // op: Zn return 5; case 4: // op: iop return 19; case 3: // op: Zm return 16; } break; } case AArch64::SDOT_ZZZI_D: case AArch64::UDOT_ZZZI_D: { switch (OpNum) { case 0: // op: Zda return 0; case 2: // op: Zn return 5; case 4: // op: iop return 20; case 3: // op: Zm return 16; } break; } case AArch64::FCMLA_ZZZI_H: { switch (OpNum) { case 0: // op: Zda return 0; case 2: // op: Zn return 5; case 5: // op: imm return 10; case 3: // op: Zm return 16; case 4: // op: iop return 19; } break; } case AArch64::FCMLA_ZZZI_S: { switch (OpNum) { case 0: // op: Zda return 0; case 2: // op: Zn return 5; case 5: // op: imm return 10; case 3: // op: Zm return 16; case 4: // op: iop return 20; } break; } case AArch64::CDOT_ZZZI_S: case AArch64::CMLA_ZZZI_H: case AArch64::SQRDCMLAH_ZZZI_H: { switch (OpNum) { case 0: // op: Zda return 0; case 2: // op: Zn return 5; case 5: // op: rot return 10; case 4: // op: iop return 19; case 3: // op: Zm return 16; } break; } case AArch64::CDOT_ZZZI_D: case AArch64::CMLA_ZZZI_S: case AArch64::SQRDCMLAH_ZZZI_S: { switch (OpNum) { case 0: // op: Zda return 0; case 2: // op: Zn return 5; case 5: // op: rot return 10; case 4: // op: iop return 20; case 3: // op: Zm return 16; } break; } case AArch64::MAD_CPA: { switch (OpNum) { case 0: // op: Zdn return 0; case 2: // op: Zm return 16; case 3: // op: Za return 5; } break; } case AArch64::XAR_ZZZI_B: case AArch64::XAR_ZZZI_D: case AArch64::XAR_ZZZI_H: case AArch64::XAR_ZZZI_S: { switch (OpNum) { case 0: // op: Zdn return 0; case 2: // op: Zm return 5; case 3: // op: imm return 16; } break; } case AArch64::FTMAD_ZZI_D: case AArch64::FTMAD_ZZI_H: case AArch64::FTMAD_ZZI_S: { switch (OpNum) { case 0: // op: Zdn return 0; case 2: // op: Zm return 5; case 3: // op: imm3 return 16; } break; } case AArch64::EXTQ_ZZI: { switch (OpNum) { case 0: // op: Zdn return 0; case 2: // op: Zm return 5; case 3: // op: imm4 return 16; } break; } case AArch64::EXT_ZZI: { switch (OpNum) { case 0: // op: Zdn return 0; case 2: // op: Zm return 5; case 3: // op: imm8 return 10; } break; } case AArch64::CADD_ZZI_B: case AArch64::CADD_ZZI_D: case AArch64::CADD_ZZI_H: case AArch64::CADD_ZZI_S: case AArch64::SQCADD_ZZI_B: case AArch64::SQCADD_ZZI_D: case AArch64::SQCADD_ZZI_H: case AArch64::SQCADD_ZZI_S: { switch (OpNum) { case 0: // op: Zdn return 0; case 2: // op: Zm return 5; case 3: // op: rot return 10; } break; } case AArch64::AESD_ZZZ_B: case AArch64::AESE_ZZZ_B: case AArch64::SM4E_ZZZ_S: { switch (OpNum) { case 0: // op: Zdn return 0; case 2: // op: Zm return 5; } break; } case AArch64::ADD_ZI_B: case AArch64::ADD_ZI_D: case AArch64::ADD_ZI_H: case AArch64::ADD_ZI_S: case AArch64::MUL_ZI_B: case AArch64::MUL_ZI_D: case AArch64::MUL_ZI_H: case AArch64::MUL_ZI_S: case AArch64::SMAX_ZI_B: case AArch64::SMAX_ZI_D: case AArch64::SMAX_ZI_H: case AArch64::SMAX_ZI_S: case AArch64::SMIN_ZI_B: case AArch64::SMIN_ZI_D: case AArch64::SMIN_ZI_H: case AArch64::SMIN_ZI_S: case AArch64::SQADD_ZI_B: case AArch64::SQADD_ZI_D: case AArch64::SQADD_ZI_H: case AArch64::SQADD_ZI_S: case AArch64::SQSUB_ZI_B: case AArch64::SQSUB_ZI_D: case AArch64::SQSUB_ZI_H: case AArch64::SQSUB_ZI_S: case AArch64::SUBR_ZI_B: case AArch64::SUBR_ZI_D: case AArch64::SUBR_ZI_H: case AArch64::SUBR_ZI_S: case AArch64::SUB_ZI_B: case AArch64::SUB_ZI_D: case AArch64::SUB_ZI_H: case AArch64::SUB_ZI_S: case AArch64::UMAX_ZI_B: case AArch64::UMAX_ZI_D: case AArch64::UMAX_ZI_H: case AArch64::UMAX_ZI_S: case AArch64::UMIN_ZI_B: case AArch64::UMIN_ZI_D: case AArch64::UMIN_ZI_H: case AArch64::UMIN_ZI_S: case AArch64::UQADD_ZI_B: case AArch64::UQADD_ZI_D: case AArch64::UQADD_ZI_H: case AArch64::UQADD_ZI_S: case AArch64::UQSUB_ZI_B: case AArch64::UQSUB_ZI_D: case AArch64::UQSUB_ZI_H: case AArch64::UQSUB_ZI_S: { switch (OpNum) { case 0: // op: Zdn return 0; case 2: // op: imm return 5; } break; } case AArch64::AND_ZI: case AArch64::EOR_ZI: case AArch64::ORR_ZI: { switch (OpNum) { case 0: // op: Zdn return 0; case 2: // op: imms13 return 5; } break; } case AArch64::DECD_ZPiI: case AArch64::DECH_ZPiI: case AArch64::DECW_ZPiI: case AArch64::INCD_ZPiI: case AArch64::INCH_ZPiI: case AArch64::INCW_ZPiI: case AArch64::SQDECD_ZPiI: case AArch64::SQDECH_ZPiI: case AArch64::SQDECW_ZPiI: case AArch64::SQINCD_ZPiI: case AArch64::SQINCH_ZPiI: case AArch64::SQINCW_ZPiI: case AArch64::UQDECD_ZPiI: case AArch64::UQDECH_ZPiI: case AArch64::UQDECW_ZPiI: case AArch64::UQINCD_ZPiI: case AArch64::UQINCH_ZPiI: case AArch64::UQINCW_ZPiI: { switch (OpNum) { case 0: // op: Zdn return 0; case 2: // op: pattern return 5; case 3: // op: imm4 return 16; } break; } case AArch64::BCAX_ZZZZ: case AArch64::BSL1N_ZZZZ: case AArch64::BSL2N_ZZZZ: case AArch64::BSL_ZZZZ: case AArch64::EOR3_ZZZZ: case AArch64::NBSL_ZZZZ: { switch (OpNum) { case 0: // op: Zdn return 0; case 3: // op: Zk return 5; case 2: // op: Zm return 16; } break; } case AArch64::FCADD_ZPmZ_D: case AArch64::FCADD_ZPmZ_H: case AArch64::FCADD_ZPmZ_S: { switch (OpNum) { case 0: // op: Zdn return 0; case 3: // op: Zm return 5; case 1: // op: Pg return 10; case 4: // op: imm return 16; } break; } case AArch64::AESIMC_ZZ_B: case AArch64::AESMC_ZZ_B: { switch (OpNum) { case 0: // op: Zdn return 0; } break; } case AArch64::LD1RO_B: case AArch64::LD1RO_D: case AArch64::LD1RO_H: case AArch64::LD1RO_W: case AArch64::LD1RQ_B: case AArch64::LD1RQ_D: case AArch64::LD1RQ_H: case AArch64::LD1RQ_W: { switch (OpNum) { case 0: // op: Zt return 0; case 1: // op: Pg return 10; case 2: // op: Rn return 5; case 3: // op: Rm return 16; } break; } case AArch64::LD2B_IMM: case AArch64::LD2D_IMM: case AArch64::LD2H_IMM: case AArch64::LD2Q_IMM: case AArch64::LD2W_IMM: case AArch64::LD3B_IMM: case AArch64::LD3D_IMM: case AArch64::LD3H_IMM: case AArch64::LD3Q_IMM: case AArch64::LD3W_IMM: case AArch64::LD4B_IMM: case AArch64::LD4D_IMM: case AArch64::LD4H_IMM: case AArch64::LD4Q_IMM: case AArch64::LD4W_IMM: case AArch64::LDNT1B_ZRI: case AArch64::LDNT1D_ZRI: case AArch64::LDNT1H_ZRI: case AArch64::LDNT1W_ZRI: { switch (OpNum) { case 0: // op: Zt return 0; case 1: // op: Pg return 10; case 2: // op: Rn return 5; case 3: // op: imm4 return 16; } break; } case AArch64::LD1B: case AArch64::LD1B_D: case AArch64::LD1B_H: case AArch64::LD1B_S: case AArch64::LD1D: case AArch64::LD1H: case AArch64::LD1H_D: case AArch64::LD1H_S: case AArch64::LD1SB_D: case AArch64::LD1SB_H: case AArch64::LD1SB_S: case AArch64::LD1SH_D: case AArch64::LD1SH_S: case AArch64::LD1SW_D: case AArch64::LD1W: case AArch64::LD1W_D: case AArch64::LDFF1B: case AArch64::LDFF1B_D: case AArch64::LDFF1B_H: case AArch64::LDFF1B_S: case AArch64::LDFF1D: case AArch64::LDFF1H: case AArch64::LDFF1H_D: case AArch64::LDFF1H_S: case AArch64::LDFF1SB_D: case AArch64::LDFF1SB_H: case AArch64::LDFF1SB_S: case AArch64::LDFF1SH_D: case AArch64::LDFF1SH_S: case AArch64::LDFF1SW_D: case AArch64::LDFF1W: case AArch64::LDFF1W_D: { switch (OpNum) { case 0: // op: Zt return 0; case 1: // op: Pg return 10; case 3: // op: Rm return 16; case 2: // op: Rn return 5; } break; } case AArch64::LD1D_Q: case AArch64::LD1W_Q: case AArch64::ST2Q: case AArch64::ST3Q: case AArch64::ST4Q: { switch (OpNum) { case 0: // op: Zt return 0; case 2: // op: Rn return 5; case 1: // op: Pg return 10; case 3: // op: Rm return 16; } break; } case AArch64::LD1D_Q_IMM: case AArch64::LD1RO_B_IMM: case AArch64::LD1RO_D_IMM: case AArch64::LD1RO_H_IMM: case AArch64::LD1RO_W_IMM: case AArch64::LD1RQ_B_IMM: case AArch64::LD1RQ_D_IMM: case AArch64::LD1RQ_H_IMM: case AArch64::LD1RQ_W_IMM: case AArch64::LD1W_Q_IMM: case AArch64::ST2Q_IMM: case AArch64::ST3Q_IMM: case AArch64::ST4Q_IMM: { switch (OpNum) { case 0: // op: Zt return 0; case 2: // op: Rn return 5; case 1: // op: Pg return 10; case 3: // op: imm4 return 16; } break; } case AArch64::GLD1Q: case AArch64::SST1Q: { switch (OpNum) { case 0: // op: Zt return 0; case 2: // op: Zn return 5; case 1: // op: Pg return 10; case 3: // op: Rm return 16; } break; } case AArch64::LD1B_2Z_IMM: case AArch64::LD1D_2Z_IMM: case AArch64::LD1H_2Z_IMM: case AArch64::LD1W_2Z_IMM: case AArch64::LDNT1B_2Z_IMM: case AArch64::LDNT1D_2Z_IMM: case AArch64::LDNT1H_2Z_IMM: case AArch64::LDNT1W_2Z_IMM: case AArch64::ST1B_2Z_IMM: case AArch64::ST1D_2Z_IMM: case AArch64::ST1H_2Z_IMM: case AArch64::ST1W_2Z_IMM: case AArch64::STNT1B_2Z_IMM: case AArch64::STNT1D_2Z_IMM: case AArch64::STNT1H_2Z_IMM: case AArch64::STNT1W_2Z_IMM: { switch (OpNum) { case 0: // op: Zt return 1; case 2: // op: Rn return 5; case 1: // op: PNg return 10; case 3: // op: imm4 return 16; } break; } case AArch64::LD1B_2Z: case AArch64::LD1D_2Z: case AArch64::LD1H_2Z: case AArch64::LD1W_2Z: case AArch64::LDNT1B_2Z: case AArch64::LDNT1D_2Z: case AArch64::LDNT1H_2Z: case AArch64::LDNT1W_2Z: case AArch64::ST1B_2Z: case AArch64::ST1D_2Z: case AArch64::ST1H_2Z: case AArch64::ST1W_2Z: case AArch64::STNT1B_2Z: case AArch64::STNT1D_2Z: case AArch64::STNT1H_2Z: case AArch64::STNT1W_2Z: { switch (OpNum) { case 0: // op: Zt return 1; case 3: // op: Rm return 16; case 2: // op: Rn return 5; case 1: // op: PNg return 10; } break; } case AArch64::LD1B_4Z_IMM: case AArch64::LD1D_4Z_IMM: case AArch64::LD1H_4Z_IMM: case AArch64::LD1W_4Z_IMM: case AArch64::LDNT1B_4Z_IMM: case AArch64::LDNT1D_4Z_IMM: case AArch64::LDNT1H_4Z_IMM: case AArch64::LDNT1W_4Z_IMM: case AArch64::ST1B_4Z_IMM: case AArch64::ST1D_4Z_IMM: case AArch64::ST1H_4Z_IMM: case AArch64::ST1W_4Z_IMM: case AArch64::STNT1B_4Z_IMM: case AArch64::STNT1D_4Z_IMM: case AArch64::STNT1H_4Z_IMM: case AArch64::STNT1W_4Z_IMM: { switch (OpNum) { case 0: // op: Zt return 2; case 2: // op: Rn return 5; case 1: // op: PNg return 10; case 3: // op: imm4 return 16; } break; } case AArch64::LD1B_4Z: case AArch64::LD1D_4Z: case AArch64::LD1H_4Z: case AArch64::LD1W_4Z: case AArch64::LDNT1B_4Z: case AArch64::LDNT1D_4Z: case AArch64::LDNT1H_4Z: case AArch64::LDNT1W_4Z: case AArch64::ST1B_4Z: case AArch64::ST1D_4Z: case AArch64::ST1H_4Z: case AArch64::ST1W_4Z: case AArch64::STNT1B_4Z: case AArch64::STNT1D_4Z: case AArch64::STNT1H_4Z: case AArch64::STNT1W_4Z: { switch (OpNum) { case 0: // op: Zt return 2; case 3: // op: Rm return 16; case 2: // op: Rn return 5; case 1: // op: PNg return 10; } break; } case AArch64::B: case AArch64::BL: { switch (OpNum) { case 0: // op: addr return 0; } break; } case AArch64::BCcc: case AArch64::Bcc: { switch (OpNum) { case 0: // op: cond return 0; case 1: // op: target return 5; } break; } case AArch64::DUPi8: { switch (OpNum) { case 0: // op: dst return 0; case 1: // op: src return 5; case 2: // op: idx return 17; } break; } case AArch64::DUPi16: { switch (OpNum) { case 0: // op: dst return 0; case 1: // op: src return 5; case 2: // op: idx return 18; } break; } case AArch64::DUPi32: { switch (OpNum) { case 0: // op: dst return 0; case 1: // op: src return 5; case 2: // op: idx return 19; } break; } case AArch64::DUPi64: { switch (OpNum) { case 0: // op: dst return 0; case 1: // op: src return 5; case 2: // op: idx return 20; } break; } case AArch64::UDF: case AArch64::ZERO_M: { switch (OpNum) { case 0: // op: imm return 0; } break; } case AArch64::BRK: case AArch64::DCPS1: case AArch64::DCPS2: case AArch64::DCPS3: case AArch64::HINT: case AArch64::HLT: case AArch64::HVC: case AArch64::SMC: case AArch64::SVC: case AArch64::TCANCEL: { switch (OpNum) { case 0: // op: imm return 5; } break; } case AArch64::AUTIASPPCi: case AArch64::AUTIBSPPCi: case AArch64::RETAASPPCi: case AArch64::RETABSPPCi: { switch (OpNum) { case 0: // op: label return 5; } break; } case AArch64::SYSPxt_XZR: { switch (OpNum) { case 0: // op: op1 return 16; case 1: // op: Cn return 12; case 2: // op: Cm return 8; case 3: // op: op2 return 5; } break; } case AArch64::MSRpstateImm1: case AArch64::MSRpstateImm4: { switch (OpNum) { case 0: // op: pstatefield return 5; case 1: // op: imm return 8; } break; } case AArch64::MSRpstatesvcrImm1: { switch (OpNum) { case 0: // op: pstatefield return 9; case 1: // op: imm return 8; } break; } case AArch64::SEL_VG2_2ZC2Z2Z_B: case AArch64::SEL_VG2_2ZC2Z2Z_D: case AArch64::SEL_VG2_2ZC2Z2Z_H: case AArch64::SEL_VG2_2ZC2Z2Z_S: { switch (OpNum) { case 1: // op: PNg return 10; case 3: // op: Zm return 17; case 2: // op: Zn return 6; case 0: // op: Zd return 1; } break; } case AArch64::SEL_VG4_4ZC4Z4Z_B: case AArch64::SEL_VG4_4ZC4Z4Z_D: case AArch64::SEL_VG4_4ZC4Z4Z_H: case AArch64::SEL_VG4_4ZC4Z4Z_S: { switch (OpNum) { case 1: // op: PNg return 10; case 3: // op: Zm return 18; case 2: // op: Zn return 7; case 0: // op: Zd return 2; } break; } case AArch64::LASTA_RPZ_B: case AArch64::LASTA_RPZ_D: case AArch64::LASTA_RPZ_H: case AArch64::LASTA_RPZ_S: case AArch64::LASTB_RPZ_B: case AArch64::LASTB_RPZ_D: case AArch64::LASTB_RPZ_H: case AArch64::LASTB_RPZ_S: { switch (OpNum) { case 1: // op: Pg return 10; case 0: // op: Rd return 0; case 2: // op: Zn return 5; } break; } case AArch64::CLASTA_RPZ_B: case AArch64::CLASTA_RPZ_D: case AArch64::CLASTA_RPZ_H: case AArch64::CLASTA_RPZ_S: case AArch64::CLASTB_RPZ_B: case AArch64::CLASTB_RPZ_D: case AArch64::CLASTB_RPZ_H: case AArch64::CLASTB_RPZ_S: { switch (OpNum) { case 1: // op: Pg return 10; case 0: // op: Rdn return 0; case 3: // op: Zm return 5; } break; } case AArch64::ANDV_VPZ_B: case AArch64::ANDV_VPZ_D: case AArch64::ANDV_VPZ_H: case AArch64::ANDV_VPZ_S: case AArch64::EORV_VPZ_B: case AArch64::EORV_VPZ_D: case AArch64::EORV_VPZ_H: case AArch64::EORV_VPZ_S: case AArch64::LASTA_VPZ_B: case AArch64::LASTA_VPZ_D: case AArch64::LASTA_VPZ_H: case AArch64::LASTA_VPZ_S: case AArch64::LASTB_VPZ_B: case AArch64::LASTB_VPZ_D: case AArch64::LASTB_VPZ_H: case AArch64::LASTB_VPZ_S: case AArch64::ORV_VPZ_B: case AArch64::ORV_VPZ_D: case AArch64::ORV_VPZ_H: case AArch64::ORV_VPZ_S: case AArch64::SADDV_VPZ_B: case AArch64::SADDV_VPZ_H: case AArch64::SADDV_VPZ_S: case AArch64::SMAXV_VPZ_B: case AArch64::SMAXV_VPZ_D: case AArch64::SMAXV_VPZ_H: case AArch64::SMAXV_VPZ_S: case AArch64::SMINV_VPZ_B: case AArch64::SMINV_VPZ_D: case AArch64::SMINV_VPZ_H: case AArch64::SMINV_VPZ_S: case AArch64::UADDV_VPZ_B: case AArch64::UADDV_VPZ_D: case AArch64::UADDV_VPZ_H: case AArch64::UADDV_VPZ_S: case AArch64::UMAXV_VPZ_B: case AArch64::UMAXV_VPZ_D: case AArch64::UMAXV_VPZ_H: case AArch64::UMAXV_VPZ_S: case AArch64::UMINV_VPZ_B: case AArch64::UMINV_VPZ_D: case AArch64::UMINV_VPZ_H: case AArch64::UMINV_VPZ_S: { switch (OpNum) { case 1: // op: Pg return 10; case 0: // op: Vd return 0; case 2: // op: Zn return 5; } break; } case AArch64::CLASTA_VPZ_B: case AArch64::CLASTA_VPZ_D: case AArch64::CLASTA_VPZ_H: case AArch64::CLASTA_VPZ_S: case AArch64::CLASTB_VPZ_B: case AArch64::CLASTB_VPZ_D: case AArch64::CLASTB_VPZ_H: case AArch64::CLASTB_VPZ_S: case AArch64::FADDA_VPZ_D: case AArch64::FADDA_VPZ_H: case AArch64::FADDA_VPZ_S: { switch (OpNum) { case 1: // op: Pg return 10; case 0: // op: Vdn return 0; case 3: // op: Zm return 5; } break; } case AArch64::COMPACT_ZPZ_D: case AArch64::COMPACT_ZPZ_S: case AArch64::MOVPRFX_ZPzZ_B: case AArch64::MOVPRFX_ZPzZ_D: case AArch64::MOVPRFX_ZPzZ_H: case AArch64::MOVPRFX_ZPzZ_S: { switch (OpNum) { case 1: // op: Pg return 10; case 0: // op: Zd return 0; case 2: // op: Zn return 5; } break; } case AArch64::SEL_ZPZZ_B: case AArch64::SEL_ZPZZ_D: case AArch64::SEL_ZPZZ_H: case AArch64::SEL_ZPZZ_S: { switch (OpNum) { case 1: // op: Pg return 10; case 0: // op: Zd return 0; case 3: // op: Zm return 16; case 2: // op: Zn return 5; } break; } case AArch64::BFMLA_ZPmZZ: case AArch64::BFMLS_ZPmZZ: case AArch64::FMLA_ZPmZZ_D: case AArch64::FMLA_ZPmZZ_H: case AArch64::FMLA_ZPmZZ_S: case AArch64::FMLS_ZPmZZ_D: case AArch64::FMLS_ZPmZZ_H: case AArch64::FMLS_ZPmZZ_S: case AArch64::FNMLA_ZPmZZ_D: case AArch64::FNMLA_ZPmZZ_H: case AArch64::FNMLA_ZPmZZ_S: case AArch64::FNMLS_ZPmZZ_D: case AArch64::FNMLS_ZPmZZ_H: case AArch64::FNMLS_ZPmZZ_S: case AArch64::MLA_ZPmZZ_B: case AArch64::MLA_ZPmZZ_D: case AArch64::MLA_ZPmZZ_H: case AArch64::MLA_ZPmZZ_S: case AArch64::MLS_ZPmZZ_B: case AArch64::MLS_ZPmZZ_D: case AArch64::MLS_ZPmZZ_H: case AArch64::MLS_ZPmZZ_S: { switch (OpNum) { case 1: // op: Pg return 10; case 0: // op: Zda return 0; case 4: // op: Zm return 16; case 3: // op: Zn return 5; } break; } case AArch64::ADD_ZPmZ_B: case AArch64::ADD_ZPmZ_CPA: case AArch64::ADD_ZPmZ_D: case AArch64::ADD_ZPmZ_H: case AArch64::ADD_ZPmZ_S: case AArch64::AND_ZPmZ_B: case AArch64::AND_ZPmZ_D: case AArch64::AND_ZPmZ_H: case AArch64::AND_ZPmZ_S: case AArch64::ASRR_ZPmZ_B: case AArch64::ASRR_ZPmZ_D: case AArch64::ASRR_ZPmZ_H: case AArch64::ASRR_ZPmZ_S: case AArch64::ASR_WIDE_ZPmZ_B: case AArch64::ASR_WIDE_ZPmZ_H: case AArch64::ASR_WIDE_ZPmZ_S: case AArch64::ASR_ZPmZ_B: case AArch64::ASR_ZPmZ_D: case AArch64::ASR_ZPmZ_H: case AArch64::ASR_ZPmZ_S: case AArch64::BFADD_ZPmZZ: case AArch64::BFMAXNM_ZPmZZ: case AArch64::BFMAX_ZPmZZ: case AArch64::BFMINNM_ZPmZZ: case AArch64::BFMIN_ZPmZZ: case AArch64::BFMUL_ZPmZZ: case AArch64::BFSUB_ZPmZZ: case AArch64::BIC_ZPmZ_B: case AArch64::BIC_ZPmZ_D: case AArch64::BIC_ZPmZ_H: case AArch64::BIC_ZPmZ_S: case AArch64::CLASTA_ZPZ_B: case AArch64::CLASTA_ZPZ_D: case AArch64::CLASTA_ZPZ_H: case AArch64::CLASTA_ZPZ_S: case AArch64::CLASTB_ZPZ_B: case AArch64::CLASTB_ZPZ_D: case AArch64::CLASTB_ZPZ_H: case AArch64::CLASTB_ZPZ_S: case AArch64::EOR_ZPmZ_B: case AArch64::EOR_ZPmZ_D: case AArch64::EOR_ZPmZ_H: case AArch64::EOR_ZPmZ_S: case AArch64::FABD_ZPmZ_D: case AArch64::FABD_ZPmZ_H: case AArch64::FABD_ZPmZ_S: case AArch64::FADD_ZPmZ_D: case AArch64::FADD_ZPmZ_H: case AArch64::FADD_ZPmZ_S: case AArch64::FAMAX_ZPmZ_D: case AArch64::FAMAX_ZPmZ_H: case AArch64::FAMAX_ZPmZ_S: case AArch64::FAMIN_ZPmZ_D: case AArch64::FAMIN_ZPmZ_H: case AArch64::FAMIN_ZPmZ_S: case AArch64::FDIVR_ZPmZ_D: case AArch64::FDIVR_ZPmZ_H: case AArch64::FDIVR_ZPmZ_S: case AArch64::FDIV_ZPmZ_D: case AArch64::FDIV_ZPmZ_H: case AArch64::FDIV_ZPmZ_S: case AArch64::FMAXNM_ZPmZ_D: case AArch64::FMAXNM_ZPmZ_H: case AArch64::FMAXNM_ZPmZ_S: case AArch64::FMAX_ZPmZ_D: case AArch64::FMAX_ZPmZ_H: case AArch64::FMAX_ZPmZ_S: case AArch64::FMINNM_ZPmZ_D: case AArch64::FMINNM_ZPmZ_H: case AArch64::FMINNM_ZPmZ_S: case AArch64::FMIN_ZPmZ_D: case AArch64::FMIN_ZPmZ_H: case AArch64::FMIN_ZPmZ_S: case AArch64::FMULX_ZPmZ_D: case AArch64::FMULX_ZPmZ_H: case AArch64::FMULX_ZPmZ_S: case AArch64::FMUL_ZPmZ_D: case AArch64::FMUL_ZPmZ_H: case AArch64::FMUL_ZPmZ_S: case AArch64::FSCALE_ZPmZ_D: case AArch64::FSCALE_ZPmZ_H: case AArch64::FSCALE_ZPmZ_S: case AArch64::FSUBR_ZPmZ_D: case AArch64::FSUBR_ZPmZ_H: case AArch64::FSUBR_ZPmZ_S: case AArch64::FSUB_ZPmZ_D: case AArch64::FSUB_ZPmZ_H: case AArch64::FSUB_ZPmZ_S: case AArch64::LSLR_ZPmZ_B: case AArch64::LSLR_ZPmZ_D: case AArch64::LSLR_ZPmZ_H: case AArch64::LSLR_ZPmZ_S: case AArch64::LSL_WIDE_ZPmZ_B: case AArch64::LSL_WIDE_ZPmZ_H: case AArch64::LSL_WIDE_ZPmZ_S: case AArch64::LSL_ZPmZ_B: case AArch64::LSL_ZPmZ_D: case AArch64::LSL_ZPmZ_H: case AArch64::LSL_ZPmZ_S: case AArch64::LSRR_ZPmZ_B: case AArch64::LSRR_ZPmZ_D: case AArch64::LSRR_ZPmZ_H: case AArch64::LSRR_ZPmZ_S: case AArch64::LSR_WIDE_ZPmZ_B: case AArch64::LSR_WIDE_ZPmZ_H: case AArch64::LSR_WIDE_ZPmZ_S: case AArch64::LSR_ZPmZ_B: case AArch64::LSR_ZPmZ_D: case AArch64::LSR_ZPmZ_H: case AArch64::LSR_ZPmZ_S: case AArch64::MUL_ZPmZ_B: case AArch64::MUL_ZPmZ_D: case AArch64::MUL_ZPmZ_H: case AArch64::MUL_ZPmZ_S: case AArch64::ORR_ZPmZ_B: case AArch64::ORR_ZPmZ_D: case AArch64::ORR_ZPmZ_H: case AArch64::ORR_ZPmZ_S: case AArch64::SABD_ZPmZ_B: case AArch64::SABD_ZPmZ_D: case AArch64::SABD_ZPmZ_H: case AArch64::SABD_ZPmZ_S: case AArch64::SDIVR_ZPmZ_D: case AArch64::SDIVR_ZPmZ_S: case AArch64::SDIV_ZPmZ_D: case AArch64::SDIV_ZPmZ_S: case AArch64::SMAX_ZPmZ_B: case AArch64::SMAX_ZPmZ_D: case AArch64::SMAX_ZPmZ_H: case AArch64::SMAX_ZPmZ_S: case AArch64::SMIN_ZPmZ_B: case AArch64::SMIN_ZPmZ_D: case AArch64::SMIN_ZPmZ_H: case AArch64::SMIN_ZPmZ_S: case AArch64::SMULH_ZPmZ_B: case AArch64::SMULH_ZPmZ_D: case AArch64::SMULH_ZPmZ_H: case AArch64::SMULH_ZPmZ_S: case AArch64::SPLICE_ZPZ_B: case AArch64::SPLICE_ZPZ_D: case AArch64::SPLICE_ZPZ_H: case AArch64::SPLICE_ZPZ_S: case AArch64::SUBR_ZPmZ_B: case AArch64::SUBR_ZPmZ_D: case AArch64::SUBR_ZPmZ_H: case AArch64::SUBR_ZPmZ_S: case AArch64::SUB_ZPmZ_B: case AArch64::SUB_ZPmZ_CPA: case AArch64::SUB_ZPmZ_D: case AArch64::SUB_ZPmZ_H: case AArch64::SUB_ZPmZ_S: case AArch64::UABD_ZPmZ_B: case AArch64::UABD_ZPmZ_D: case AArch64::UABD_ZPmZ_H: case AArch64::UABD_ZPmZ_S: case AArch64::UDIVR_ZPmZ_D: case AArch64::UDIVR_ZPmZ_S: case AArch64::UDIV_ZPmZ_D: case AArch64::UDIV_ZPmZ_S: case AArch64::UMAX_ZPmZ_B: case AArch64::UMAX_ZPmZ_D: case AArch64::UMAX_ZPmZ_H: case AArch64::UMAX_ZPmZ_S: case AArch64::UMIN_ZPmZ_B: case AArch64::UMIN_ZPmZ_D: case AArch64::UMIN_ZPmZ_H: case AArch64::UMIN_ZPmZ_S: case AArch64::UMULH_ZPmZ_B: case AArch64::UMULH_ZPmZ_D: case AArch64::UMULH_ZPmZ_H: case AArch64::UMULH_ZPmZ_S: { switch (OpNum) { case 1: // op: Pg return 10; case 0: // op: Zdn return 0; case 3: // op: Zm return 5; } break; } case AArch64::FADD_ZPmI_D: case AArch64::FADD_ZPmI_H: case AArch64::FADD_ZPmI_S: case AArch64::FMAXNM_ZPmI_D: case AArch64::FMAXNM_ZPmI_H: case AArch64::FMAXNM_ZPmI_S: case AArch64::FMAX_ZPmI_D: case AArch64::FMAX_ZPmI_H: case AArch64::FMAX_ZPmI_S: case AArch64::FMINNM_ZPmI_D: case AArch64::FMINNM_ZPmI_H: case AArch64::FMINNM_ZPmI_S: case AArch64::FMIN_ZPmI_D: case AArch64::FMIN_ZPmI_H: case AArch64::FMIN_ZPmI_S: case AArch64::FMUL_ZPmI_D: case AArch64::FMUL_ZPmI_H: case AArch64::FMUL_ZPmI_S: case AArch64::FSUBR_ZPmI_D: case AArch64::FSUBR_ZPmI_H: case AArch64::FSUBR_ZPmI_S: case AArch64::FSUB_ZPmI_D: case AArch64::FSUB_ZPmI_H: case AArch64::FSUB_ZPmI_S: { switch (OpNum) { case 1: // op: Pg return 10; case 0: // op: Zdn return 0; case 3: // op: i1 return 5; } break; } case AArch64::ASRD_ZPmI_B: case AArch64::ASRD_ZPmI_D: case AArch64::ASRD_ZPmI_H: case AArch64::ASRD_ZPmI_S: case AArch64::ASR_ZPmI_B: case AArch64::ASR_ZPmI_D: case AArch64::ASR_ZPmI_H: case AArch64::ASR_ZPmI_S: case AArch64::LSL_ZPmI_B: case AArch64::LSL_ZPmI_D: case AArch64::LSL_ZPmI_H: case AArch64::LSL_ZPmI_S: case AArch64::LSR_ZPmI_B: case AArch64::LSR_ZPmI_D: case AArch64::LSR_ZPmI_H: case AArch64::LSR_ZPmI_S: case AArch64::SQSHLU_ZPmI_B: case AArch64::SQSHLU_ZPmI_D: case AArch64::SQSHLU_ZPmI_H: case AArch64::SQSHLU_ZPmI_S: case AArch64::SQSHL_ZPmI_B: case AArch64::SQSHL_ZPmI_D: case AArch64::SQSHL_ZPmI_H: case AArch64::SQSHL_ZPmI_S: case AArch64::SRSHR_ZPmI_B: case AArch64::SRSHR_ZPmI_D: case AArch64::SRSHR_ZPmI_H: case AArch64::SRSHR_ZPmI_S: case AArch64::UQSHL_ZPmI_B: case AArch64::UQSHL_ZPmI_D: case AArch64::UQSHL_ZPmI_H: case AArch64::UQSHL_ZPmI_S: case AArch64::URSHR_ZPmI_B: case AArch64::URSHR_ZPmI_D: case AArch64::URSHR_ZPmI_H: case AArch64::URSHR_ZPmI_S: { switch (OpNum) { case 1: // op: Pg return 10; case 0: // op: Zdn return 0; case 3: // op: imm return 5; } break; } case AArch64::MAD_ZPmZZ_B: case AArch64::MAD_ZPmZZ_D: case AArch64::MAD_ZPmZZ_H: case AArch64::MAD_ZPmZZ_S: case AArch64::MSB_ZPmZZ_B: case AArch64::MSB_ZPmZZ_D: case AArch64::MSB_ZPmZZ_H: case AArch64::MSB_ZPmZZ_S: { switch (OpNum) { case 1: // op: Pg return 10; case 0: // op: Zdn return 0; case 4: // op: Za return 5; case 3: // op: Zm return 16; } break; } case AArch64::CNTP_XPP_B: case AArch64::CNTP_XPP_D: case AArch64::CNTP_XPP_H: case AArch64::CNTP_XPP_S: { switch (OpNum) { case 1: // op: Pg return 10; case 2: // op: Pn return 5; case 0: // op: Rd return 0; } break; } case AArch64::LD1B_D_IMM: case AArch64::LD1B_H_IMM: case AArch64::LD1B_IMM: case AArch64::LD1B_S_IMM: case AArch64::LD1D_IMM: case AArch64::LD1H_D_IMM: case AArch64::LD1H_IMM: case AArch64::LD1H_S_IMM: case AArch64::LD1SB_D_IMM: case AArch64::LD1SB_H_IMM: case AArch64::LD1SB_S_IMM: case AArch64::LD1SH_D_IMM: case AArch64::LD1SH_S_IMM: case AArch64::LD1SW_D_IMM: case AArch64::LD1W_D_IMM: case AArch64::LD1W_IMM: case AArch64::LDNF1B_D_IMM: case AArch64::LDNF1B_H_IMM: case AArch64::LDNF1B_IMM: case AArch64::LDNF1B_S_IMM: case AArch64::LDNF1D_IMM: case AArch64::LDNF1H_D_IMM: case AArch64::LDNF1H_IMM: case AArch64::LDNF1H_S_IMM: case AArch64::LDNF1SB_D_IMM: case AArch64::LDNF1SB_H_IMM: case AArch64::LDNF1SB_S_IMM: case AArch64::LDNF1SH_D_IMM: case AArch64::LDNF1SH_S_IMM: case AArch64::LDNF1SW_D_IMM: case AArch64::LDNF1W_D_IMM: case AArch64::LDNF1W_IMM: case AArch64::ST1B_D_IMM: case AArch64::ST1B_H_IMM: case AArch64::ST1B_IMM: case AArch64::ST1B_S_IMM: case AArch64::ST1D_IMM: case AArch64::ST1D_Q_IMM: case AArch64::ST1H_D_IMM: case AArch64::ST1H_IMM: case AArch64::ST1H_S_IMM: case AArch64::ST1W_D_IMM: case AArch64::ST1W_IMM: case AArch64::ST1W_Q_IMM: case AArch64::ST2B_IMM: case AArch64::ST2D_IMM: case AArch64::ST2H_IMM: case AArch64::ST2W_IMM: case AArch64::ST3B_IMM: case AArch64::ST3D_IMM: case AArch64::ST3H_IMM: case AArch64::ST3W_IMM: case AArch64::ST4B_IMM: case AArch64::ST4D_IMM: case AArch64::ST4H_IMM: case AArch64::ST4W_IMM: case AArch64::STNT1B_ZRI: case AArch64::STNT1D_ZRI: case AArch64::STNT1H_ZRI: case AArch64::STNT1W_ZRI: { switch (OpNum) { case 1: // op: Pg return 10; case 2: // op: Rn return 5; case 0: // op: Zt return 0; case 3: // op: imm4 return 16; } break; } case AArch64::LD1RB_D_IMM: case AArch64::LD1RB_H_IMM: case AArch64::LD1RB_IMM: case AArch64::LD1RB_S_IMM: case AArch64::LD1RD_IMM: case AArch64::LD1RH_D_IMM: case AArch64::LD1RH_IMM: case AArch64::LD1RH_S_IMM: case AArch64::LD1RSB_D_IMM: case AArch64::LD1RSB_H_IMM: case AArch64::LD1RSB_S_IMM: case AArch64::LD1RSH_D_IMM: case AArch64::LD1RSH_S_IMM: case AArch64::LD1RSW_IMM: case AArch64::LD1RW_D_IMM: case AArch64::LD1RW_IMM: { switch (OpNum) { case 1: // op: Pg return 10; case 2: // op: Rn return 5; case 0: // op: Zt return 0; case 3: // op: imm6 return 16; } break; } case AArch64::GLD1B_D: case AArch64::GLD1B_D_SXTW: case AArch64::GLD1B_D_UXTW: case AArch64::GLD1B_S_SXTW: case AArch64::GLD1B_S_UXTW: case AArch64::GLD1D: case AArch64::GLD1D_SCALED: case AArch64::GLD1D_SXTW: case AArch64::GLD1D_SXTW_SCALED: case AArch64::GLD1D_UXTW: case AArch64::GLD1D_UXTW_SCALED: case AArch64::GLD1H_D: case AArch64::GLD1H_D_SCALED: case AArch64::GLD1H_D_SXTW: case AArch64::GLD1H_D_SXTW_SCALED: case AArch64::GLD1H_D_UXTW: case AArch64::GLD1H_D_UXTW_SCALED: case AArch64::GLD1H_S_SXTW: case AArch64::GLD1H_S_SXTW_SCALED: case AArch64::GLD1H_S_UXTW: case AArch64::GLD1H_S_UXTW_SCALED: case AArch64::GLD1SB_D: case AArch64::GLD1SB_D_SXTW: case AArch64::GLD1SB_D_UXTW: case AArch64::GLD1SB_S_SXTW: case AArch64::GLD1SB_S_UXTW: case AArch64::GLD1SH_D: case AArch64::GLD1SH_D_SCALED: case AArch64::GLD1SH_D_SXTW: case AArch64::GLD1SH_D_SXTW_SCALED: case AArch64::GLD1SH_D_UXTW: case AArch64::GLD1SH_D_UXTW_SCALED: case AArch64::GLD1SH_S_SXTW: case AArch64::GLD1SH_S_SXTW_SCALED: case AArch64::GLD1SH_S_UXTW: case AArch64::GLD1SH_S_UXTW_SCALED: case AArch64::GLD1SW_D: case AArch64::GLD1SW_D_SCALED: case AArch64::GLD1SW_D_SXTW: case AArch64::GLD1SW_D_SXTW_SCALED: case AArch64::GLD1SW_D_UXTW: case AArch64::GLD1SW_D_UXTW_SCALED: case AArch64::GLD1W_D: case AArch64::GLD1W_D_SCALED: case AArch64::GLD1W_D_SXTW: case AArch64::GLD1W_D_SXTW_SCALED: case AArch64::GLD1W_D_UXTW: case AArch64::GLD1W_D_UXTW_SCALED: case AArch64::GLD1W_SXTW: case AArch64::GLD1W_SXTW_SCALED: case AArch64::GLD1W_UXTW: case AArch64::GLD1W_UXTW_SCALED: case AArch64::GLDFF1B_D: case AArch64::GLDFF1B_D_SXTW: case AArch64::GLDFF1B_D_UXTW: case AArch64::GLDFF1B_S_SXTW: case AArch64::GLDFF1B_S_UXTW: case AArch64::GLDFF1D: case AArch64::GLDFF1D_SCALED: case AArch64::GLDFF1D_SXTW: case AArch64::GLDFF1D_SXTW_SCALED: case AArch64::GLDFF1D_UXTW: case AArch64::GLDFF1D_UXTW_SCALED: case AArch64::GLDFF1H_D: case AArch64::GLDFF1H_D_SCALED: case AArch64::GLDFF1H_D_SXTW: case AArch64::GLDFF1H_D_SXTW_SCALED: case AArch64::GLDFF1H_D_UXTW: case AArch64::GLDFF1H_D_UXTW_SCALED: case AArch64::GLDFF1H_S_SXTW: case AArch64::GLDFF1H_S_SXTW_SCALED: case AArch64::GLDFF1H_S_UXTW: case AArch64::GLDFF1H_S_UXTW_SCALED: case AArch64::GLDFF1SB_D: case AArch64::GLDFF1SB_D_SXTW: case AArch64::GLDFF1SB_D_UXTW: case AArch64::GLDFF1SB_S_SXTW: case AArch64::GLDFF1SB_S_UXTW: case AArch64::GLDFF1SH_D: case AArch64::GLDFF1SH_D_SCALED: case AArch64::GLDFF1SH_D_SXTW: case AArch64::GLDFF1SH_D_SXTW_SCALED: case AArch64::GLDFF1SH_D_UXTW: case AArch64::GLDFF1SH_D_UXTW_SCALED: case AArch64::GLDFF1SH_S_SXTW: case AArch64::GLDFF1SH_S_SXTW_SCALED: case AArch64::GLDFF1SH_S_UXTW: case AArch64::GLDFF1SH_S_UXTW_SCALED: case AArch64::GLDFF1SW_D: case AArch64::GLDFF1SW_D_SCALED: case AArch64::GLDFF1SW_D_SXTW: case AArch64::GLDFF1SW_D_SXTW_SCALED: case AArch64::GLDFF1SW_D_UXTW: case AArch64::GLDFF1SW_D_UXTW_SCALED: case AArch64::GLDFF1W_D: case AArch64::GLDFF1W_D_SCALED: case AArch64::GLDFF1W_D_SXTW: case AArch64::GLDFF1W_D_SXTW_SCALED: case AArch64::GLDFF1W_D_UXTW: case AArch64::GLDFF1W_D_UXTW_SCALED: case AArch64::GLDFF1W_SXTW: case AArch64::GLDFF1W_SXTW_SCALED: case AArch64::GLDFF1W_UXTW: case AArch64::GLDFF1W_UXTW_SCALED: case AArch64::SST1B_D: case AArch64::SST1B_D_SXTW: case AArch64::SST1B_D_UXTW: case AArch64::SST1B_S_SXTW: case AArch64::SST1B_S_UXTW: case AArch64::SST1D: case AArch64::SST1D_SCALED: case AArch64::SST1D_SXTW: case AArch64::SST1D_SXTW_SCALED: case AArch64::SST1D_UXTW: case AArch64::SST1D_UXTW_SCALED: case AArch64::SST1H_D: case AArch64::SST1H_D_SCALED: case AArch64::SST1H_D_SXTW: case AArch64::SST1H_D_SXTW_SCALED: case AArch64::SST1H_D_UXTW: case AArch64::SST1H_D_UXTW_SCALED: case AArch64::SST1H_S_SXTW: case AArch64::SST1H_S_SXTW_SCALED: case AArch64::SST1H_S_UXTW: case AArch64::SST1H_S_UXTW_SCALED: case AArch64::SST1W_D: case AArch64::SST1W_D_SCALED: case AArch64::SST1W_D_SXTW: case AArch64::SST1W_D_SXTW_SCALED: case AArch64::SST1W_D_UXTW: case AArch64::SST1W_D_UXTW_SCALED: case AArch64::SST1W_SXTW: case AArch64::SST1W_SXTW_SCALED: case AArch64::SST1W_UXTW: case AArch64::SST1W_UXTW_SCALED: { switch (OpNum) { case 1: // op: Pg return 10; case 2: // op: Rn return 5; case 3: // op: Zm return 16; case 0: // op: Zt return 0; } break; } case AArch64::PRFB_D_SCALED: case AArch64::PRFB_D_SXTW_SCALED: case AArch64::PRFB_D_UXTW_SCALED: case AArch64::PRFB_S_SXTW_SCALED: case AArch64::PRFB_S_UXTW_SCALED: case AArch64::PRFD_D_SCALED: case AArch64::PRFD_D_SXTW_SCALED: case AArch64::PRFD_D_UXTW_SCALED: case AArch64::PRFD_S_SXTW_SCALED: case AArch64::PRFD_S_UXTW_SCALED: case AArch64::PRFH_D_SCALED: case AArch64::PRFH_D_SXTW_SCALED: case AArch64::PRFH_D_UXTW_SCALED: case AArch64::PRFH_S_SXTW_SCALED: case AArch64::PRFH_S_UXTW_SCALED: case AArch64::PRFW_D_SCALED: case AArch64::PRFW_D_SXTW_SCALED: case AArch64::PRFW_D_UXTW_SCALED: case AArch64::PRFW_S_SXTW_SCALED: case AArch64::PRFW_S_UXTW_SCALED: { switch (OpNum) { case 1: // op: Pg return 10; case 2: // op: Rn return 5; case 3: // op: Zm return 16; case 0: // op: prfop return 0; } break; } case AArch64::SPLICE_ZPZZ_B: case AArch64::SPLICE_ZPZZ_D: case AArch64::SPLICE_ZPZZ_H: case AArch64::SPLICE_ZPZZ_S: { switch (OpNum) { case 1: // op: Pg return 10; case 2: // op: Zn return 5; case 0: // op: Zd return 0; } break; } case AArch64::GLD1B_D_IMM: case AArch64::GLD1B_S_IMM: case AArch64::GLD1D_IMM: case AArch64::GLD1H_D_IMM: case AArch64::GLD1H_S_IMM: case AArch64::GLD1SB_D_IMM: case AArch64::GLD1SB_S_IMM: case AArch64::GLD1SH_D_IMM: case AArch64::GLD1SH_S_IMM: case AArch64::GLD1SW_D_IMM: case AArch64::GLD1W_D_IMM: case AArch64::GLD1W_IMM: case AArch64::GLDFF1B_D_IMM: case AArch64::GLDFF1B_S_IMM: case AArch64::GLDFF1D_IMM: case AArch64::GLDFF1H_D_IMM: case AArch64::GLDFF1H_S_IMM: case AArch64::GLDFF1SB_D_IMM: case AArch64::GLDFF1SB_S_IMM: case AArch64::GLDFF1SH_D_IMM: case AArch64::GLDFF1SH_S_IMM: case AArch64::GLDFF1SW_D_IMM: case AArch64::GLDFF1W_D_IMM: case AArch64::GLDFF1W_IMM: { switch (OpNum) { case 1: // op: Pg return 10; case 2: // op: Zn return 5; case 0: // op: Zt return 0; case 3: // op: imm5 return 16; } break; } case AArch64::PRFB_D_PZI: case AArch64::PRFB_S_PZI: case AArch64::PRFD_D_PZI: case AArch64::PRFD_S_PZI: case AArch64::PRFH_D_PZI: case AArch64::PRFH_S_PZI: case AArch64::PRFW_D_PZI: case AArch64::PRFW_S_PZI: { switch (OpNum) { case 1: // op: Pg return 10; case 2: // op: Zn return 5; case 3: // op: imm5 return 16; case 0: // op: prfop return 0; } break; } case AArch64::LD2B: case AArch64::LD2D: case AArch64::LD2H: case AArch64::LD2Q: case AArch64::LD2W: case AArch64::LD3B: case AArch64::LD3D: case AArch64::LD3H: case AArch64::LD3Q: case AArch64::LD3W: case AArch64::LD4B: case AArch64::LD4D: case AArch64::LD4H: case AArch64::LD4Q: case AArch64::LD4W: case AArch64::LDNT1B_ZRR: case AArch64::LDNT1D_ZRR: case AArch64::LDNT1H_ZRR: case AArch64::LDNT1W_ZRR: case AArch64::ST1B: case AArch64::ST1B_D: case AArch64::ST1B_H: case AArch64::ST1B_S: case AArch64::ST1D: case AArch64::ST1D_Q: case AArch64::ST1H: case AArch64::ST1H_D: case AArch64::ST1H_S: case AArch64::ST1W: case AArch64::ST1W_D: case AArch64::ST1W_Q: case AArch64::ST2B: case AArch64::ST2D: case AArch64::ST2H: case AArch64::ST2W: case AArch64::ST3B: case AArch64::ST3D: case AArch64::ST3H: case AArch64::ST3W: case AArch64::ST4B: case AArch64::ST4D: case AArch64::ST4H: case AArch64::ST4W: case AArch64::STNT1B_ZRR: case AArch64::STNT1D_ZRR: case AArch64::STNT1H_ZRR: case AArch64::STNT1W_ZRR: { switch (OpNum) { case 1: // op: Pg return 10; case 3: // op: Rm return 16; case 2: // op: Rn return 5; case 0: // op: Zt return 0; } break; } case AArch64::LDNT1B_ZZR_D: case AArch64::LDNT1B_ZZR_S: case AArch64::LDNT1D_ZZR_D: case AArch64::LDNT1H_ZZR_D: case AArch64::LDNT1H_ZZR_S: case AArch64::LDNT1SB_ZZR_D: case AArch64::LDNT1SB_ZZR_S: case AArch64::LDNT1SH_ZZR_D: case AArch64::LDNT1SH_ZZR_S: case AArch64::LDNT1SW_ZZR_D: case AArch64::LDNT1W_ZZR_D: case AArch64::LDNT1W_ZZR_S: case AArch64::STNT1B_ZZR_D: case AArch64::STNT1B_ZZR_S: case AArch64::STNT1D_ZZR_D: case AArch64::STNT1H_ZZR_D: case AArch64::STNT1H_ZZR_S: case AArch64::STNT1W_ZZR_D: case AArch64::STNT1W_ZZR_S: { switch (OpNum) { case 1: // op: Pg return 10; case 3: // op: Rm return 16; case 2: // op: Zn return 5; case 0: // op: Zt return 0; } break; } case AArch64::ADDP_ZPmZ_B: case AArch64::ADDP_ZPmZ_D: case AArch64::ADDP_ZPmZ_H: case AArch64::ADDP_ZPmZ_S: case AArch64::FADDP_ZPmZZ_D: case AArch64::FADDP_ZPmZZ_H: case AArch64::FADDP_ZPmZZ_S: case AArch64::FMAXNMP_ZPmZZ_D: case AArch64::FMAXNMP_ZPmZZ_H: case AArch64::FMAXNMP_ZPmZZ_S: case AArch64::FMAXP_ZPmZZ_D: case AArch64::FMAXP_ZPmZZ_H: case AArch64::FMAXP_ZPmZZ_S: case AArch64::FMINNMP_ZPmZZ_D: case AArch64::FMINNMP_ZPmZZ_H: case AArch64::FMINNMP_ZPmZZ_S: case AArch64::FMINP_ZPmZZ_D: case AArch64::FMINP_ZPmZZ_H: case AArch64::FMINP_ZPmZZ_S: case AArch64::SHADD_ZPmZ_B: case AArch64::SHADD_ZPmZ_D: case AArch64::SHADD_ZPmZ_H: case AArch64::SHADD_ZPmZ_S: case AArch64::SHSUBR_ZPmZ_B: case AArch64::SHSUBR_ZPmZ_D: case AArch64::SHSUBR_ZPmZ_H: case AArch64::SHSUBR_ZPmZ_S: case AArch64::SHSUB_ZPmZ_B: case AArch64::SHSUB_ZPmZ_D: case AArch64::SHSUB_ZPmZ_H: case AArch64::SHSUB_ZPmZ_S: case AArch64::SMAXP_ZPmZ_B: case AArch64::SMAXP_ZPmZ_D: case AArch64::SMAXP_ZPmZ_H: case AArch64::SMAXP_ZPmZ_S: case AArch64::SMINP_ZPmZ_B: case AArch64::SMINP_ZPmZ_D: case AArch64::SMINP_ZPmZ_H: case AArch64::SMINP_ZPmZ_S: case AArch64::SQADD_ZPmZ_B: case AArch64::SQADD_ZPmZ_D: case AArch64::SQADD_ZPmZ_H: case AArch64::SQADD_ZPmZ_S: case AArch64::SQRSHLR_ZPmZ_B: case AArch64::SQRSHLR_ZPmZ_D: case AArch64::SQRSHLR_ZPmZ_H: case AArch64::SQRSHLR_ZPmZ_S: case AArch64::SQRSHL_ZPmZ_B: case AArch64::SQRSHL_ZPmZ_D: case AArch64::SQRSHL_ZPmZ_H: case AArch64::SQRSHL_ZPmZ_S: case AArch64::SQSHLR_ZPmZ_B: case AArch64::SQSHLR_ZPmZ_D: case AArch64::SQSHLR_ZPmZ_H: case AArch64::SQSHLR_ZPmZ_S: case AArch64::SQSHL_ZPmZ_B: case AArch64::SQSHL_ZPmZ_D: case AArch64::SQSHL_ZPmZ_H: case AArch64::SQSHL_ZPmZ_S: case AArch64::SQSUBR_ZPmZ_B: case AArch64::SQSUBR_ZPmZ_D: case AArch64::SQSUBR_ZPmZ_H: case AArch64::SQSUBR_ZPmZ_S: case AArch64::SQSUB_ZPmZ_B: case AArch64::SQSUB_ZPmZ_D: case AArch64::SQSUB_ZPmZ_H: case AArch64::SQSUB_ZPmZ_S: case AArch64::SRHADD_ZPmZ_B: case AArch64::SRHADD_ZPmZ_D: case AArch64::SRHADD_ZPmZ_H: case AArch64::SRHADD_ZPmZ_S: case AArch64::SRSHLR_ZPmZ_B: case AArch64::SRSHLR_ZPmZ_D: case AArch64::SRSHLR_ZPmZ_H: case AArch64::SRSHLR_ZPmZ_S: case AArch64::SRSHL_ZPmZ_B: case AArch64::SRSHL_ZPmZ_D: case AArch64::SRSHL_ZPmZ_H: case AArch64::SRSHL_ZPmZ_S: case AArch64::SUQADD_ZPmZ_B: case AArch64::SUQADD_ZPmZ_D: case AArch64::SUQADD_ZPmZ_H: case AArch64::SUQADD_ZPmZ_S: case AArch64::UHADD_ZPmZ_B: case AArch64::UHADD_ZPmZ_D: case AArch64::UHADD_ZPmZ_H: case AArch64::UHADD_ZPmZ_S: case AArch64::UHSUBR_ZPmZ_B: case AArch64::UHSUBR_ZPmZ_D: case AArch64::UHSUBR_ZPmZ_H: case AArch64::UHSUBR_ZPmZ_S: case AArch64::UHSUB_ZPmZ_B: case AArch64::UHSUB_ZPmZ_D: case AArch64::UHSUB_ZPmZ_H: case AArch64::UHSUB_ZPmZ_S: case AArch64::UMAXP_ZPmZ_B: case AArch64::UMAXP_ZPmZ_D: case AArch64::UMAXP_ZPmZ_H: case AArch64::UMAXP_ZPmZ_S: case AArch64::UMINP_ZPmZ_B: case AArch64::UMINP_ZPmZ_D: case AArch64::UMINP_ZPmZ_H: case AArch64::UMINP_ZPmZ_S: case AArch64::UQADD_ZPmZ_B: case AArch64::UQADD_ZPmZ_D: case AArch64::UQADD_ZPmZ_H: case AArch64::UQADD_ZPmZ_S: case AArch64::UQRSHLR_ZPmZ_B: case AArch64::UQRSHLR_ZPmZ_D: case AArch64::UQRSHLR_ZPmZ_H: case AArch64::UQRSHLR_ZPmZ_S: case AArch64::UQRSHL_ZPmZ_B: case AArch64::UQRSHL_ZPmZ_D: case AArch64::UQRSHL_ZPmZ_H: case AArch64::UQRSHL_ZPmZ_S: case AArch64::UQSHLR_ZPmZ_B: case AArch64::UQSHLR_ZPmZ_D: case AArch64::UQSHLR_ZPmZ_H: case AArch64::UQSHLR_ZPmZ_S: case AArch64::UQSHL_ZPmZ_B: case AArch64::UQSHL_ZPmZ_D: case AArch64::UQSHL_ZPmZ_H: case AArch64::UQSHL_ZPmZ_S: case AArch64::UQSUBR_ZPmZ_B: case AArch64::UQSUBR_ZPmZ_D: case AArch64::UQSUBR_ZPmZ_H: case AArch64::UQSUBR_ZPmZ_S: case AArch64::UQSUB_ZPmZ_B: case AArch64::UQSUB_ZPmZ_D: case AArch64::UQSUB_ZPmZ_H: case AArch64::UQSUB_ZPmZ_S: case AArch64::URHADD_ZPmZ_B: case AArch64::URHADD_ZPmZ_D: case AArch64::URHADD_ZPmZ_H: case AArch64::URHADD_ZPmZ_S: case AArch64::URSHLR_ZPmZ_B: case AArch64::URSHLR_ZPmZ_D: case AArch64::URSHLR_ZPmZ_H: case AArch64::URSHLR_ZPmZ_S: case AArch64::URSHL_ZPmZ_B: case AArch64::URSHL_ZPmZ_D: case AArch64::URSHL_ZPmZ_H: case AArch64::URSHL_ZPmZ_S: case AArch64::USQADD_ZPmZ_B: case AArch64::USQADD_ZPmZ_D: case AArch64::USQADD_ZPmZ_H: case AArch64::USQADD_ZPmZ_S: { switch (OpNum) { case 1: // op: Pg return 10; case 3: // op: Zm return 5; case 0: // op: Zdn return 0; } break; } case AArch64::SADALP_ZPmZ_D: case AArch64::SADALP_ZPmZ_H: case AArch64::SADALP_ZPmZ_S: case AArch64::UADALP_ZPmZ_D: case AArch64::UADALP_ZPmZ_H: case AArch64::UADALP_ZPmZ_S: { switch (OpNum) { case 1: // op: Pg return 10; case 3: // op: Zn return 5; case 0: // op: Zda return 0; } break; } case AArch64::SST1B_D_IMM: case AArch64::SST1B_S_IMM: case AArch64::SST1D_IMM: case AArch64::SST1H_D_IMM: case AArch64::SST1H_S_IMM: case AArch64::SST1W_D_IMM: case AArch64::SST1W_IMM: { switch (OpNum) { case 1: // op: Pg return 10; case 3: // op: imm5 return 16; case 2: // op: Zn return 5; case 0: // op: Zt return 0; } break; } case AArch64::FMAD_ZPmZZ_D: case AArch64::FMAD_ZPmZZ_H: case AArch64::FMAD_ZPmZZ_S: case AArch64::FMSB_ZPmZZ_D: case AArch64::FMSB_ZPmZZ_H: case AArch64::FMSB_ZPmZZ_S: case AArch64::FNMAD_ZPmZZ_D: case AArch64::FNMAD_ZPmZZ_H: case AArch64::FNMAD_ZPmZZ_S: case AArch64::FNMSB_ZPmZZ_D: case AArch64::FNMSB_ZPmZZ_H: case AArch64::FNMSB_ZPmZZ_S: { switch (OpNum) { case 1: // op: Pg return 10; case 4: // op: Za return 16; case 0: // op: Zdn return 0; case 3: // op: Zm return 5; } break; } case AArch64::BF16DOTlanev4bf16: case AArch64::BF16DOTlanev8bf16: case AArch64::BFMLALBIdx: case AArch64::BFMLALTIdx: case AArch64::FDOTlanev4f16: case AArch64::FDOTlanev8f8: case AArch64::FDOTlanev8f16: case AArch64::FDOTlanev16f8: case AArch64::FMLAL2lanev4f16: case AArch64::FMLAL2lanev8f16: case AArch64::FMLALBlanev8f16: case AArch64::FMLALLBBlanev4f32: case AArch64::FMLALLBTlanev4f32: case AArch64::FMLALLTBlanev4f32: case AArch64::FMLALLTTlanev4f32: case AArch64::FMLALTlanev8f16: case AArch64::FMLALlanev4f16: case AArch64::FMLALlanev8f16: case AArch64::FMLAv1i16_indexed: case AArch64::FMLAv1i32_indexed: case AArch64::FMLAv1i64_indexed: case AArch64::FMLAv2i32_indexed: case AArch64::FMLAv2i64_indexed: case AArch64::FMLAv4i16_indexed: case AArch64::FMLAv4i32_indexed: case AArch64::FMLAv8i16_indexed: case AArch64::FMLSL2lanev4f16: case AArch64::FMLSL2lanev8f16: case AArch64::FMLSLlanev4f16: case AArch64::FMLSLlanev8f16: case AArch64::FMLSv1i16_indexed: case AArch64::FMLSv1i32_indexed: case AArch64::FMLSv1i64_indexed: case AArch64::FMLSv2i32_indexed: case AArch64::FMLSv2i64_indexed: case AArch64::FMLSv4i16_indexed: case AArch64::FMLSv4i32_indexed: case AArch64::FMLSv8i16_indexed: case AArch64::MLAv2i32_indexed: case AArch64::MLAv4i16_indexed: case AArch64::MLAv4i32_indexed: case AArch64::MLAv8i16_indexed: case AArch64::MLSv2i32_indexed: case AArch64::MLSv4i16_indexed: case AArch64::MLSv4i32_indexed: case AArch64::MLSv8i16_indexed: case AArch64::SDOTlanev8i8: case AArch64::SDOTlanev16i8: case AArch64::SMLALv2i32_indexed: case AArch64::SMLALv4i16_indexed: case AArch64::SMLALv4i32_indexed: case AArch64::SMLALv8i16_indexed: case AArch64::SMLSLv2i32_indexed: case AArch64::SMLSLv4i16_indexed: case AArch64::SMLSLv4i32_indexed: case AArch64::SMLSLv8i16_indexed: case AArch64::SQDMLALv1i32_indexed: case AArch64::SQDMLALv1i64_indexed: case AArch64::SQDMLALv2i32_indexed: case AArch64::SQDMLALv4i16_indexed: case AArch64::SQDMLALv4i32_indexed: case AArch64::SQDMLALv8i16_indexed: case AArch64::SQDMLSLv1i32_indexed: case AArch64::SQDMLSLv1i64_indexed: case AArch64::SQDMLSLv2i32_indexed: case AArch64::SQDMLSLv4i16_indexed: case AArch64::SQDMLSLv4i32_indexed: case AArch64::SQDMLSLv8i16_indexed: case AArch64::SQRDMLAHv1i16_indexed: case AArch64::SQRDMLAHv1i32_indexed: case AArch64::SQRDMLAHv2i32_indexed: case AArch64::SQRDMLAHv4i16_indexed: case AArch64::SQRDMLAHv4i32_indexed: case AArch64::SQRDMLAHv8i16_indexed: case AArch64::SQRDMLSHv1i16_indexed: case AArch64::SQRDMLSHv1i32_indexed: case AArch64::SQRDMLSHv2i32_indexed: case AArch64::SQRDMLSHv4i16_indexed: case AArch64::SQRDMLSHv4i32_indexed: case AArch64::SQRDMLSHv8i16_indexed: case AArch64::SUDOTlanev8i8: case AArch64::SUDOTlanev16i8: case AArch64::UDOTlanev8i8: case AArch64::UDOTlanev16i8: case AArch64::UMLALv2i32_indexed: case AArch64::UMLALv4i16_indexed: case AArch64::UMLALv4i32_indexed: case AArch64::UMLALv8i16_indexed: case AArch64::UMLSLv2i32_indexed: case AArch64::UMLSLv4i16_indexed: case AArch64::UMLSLv4i32_indexed: case AArch64::UMLSLv8i16_indexed: case AArch64::USDOTlanev8i8: case AArch64::USDOTlanev16i8: { switch (OpNum) { case 1: // op: Rd return 0; case 2: // op: Rn return 5; case 3: // op: Rm return 16; case 4: // op: idx return 11; } break; } case AArch64::FCMLAv2f32: case AArch64::FCMLAv2f64: case AArch64::FCMLAv4f16: case AArch64::FCMLAv4f32: case AArch64::FCMLAv8f16: { switch (OpNum) { case 1: // op: Rd return 0; case 2: // op: Rn return 5; case 3: // op: Rm return 16; case 4: // op: rot return 11; } break; } case AArch64::FCMLAv4f32_indexed: case AArch64::FCMLAv8f16_indexed: { switch (OpNum) { case 1: // op: Rd return 0; case 2: // op: Rn return 5; case 3: // op: Rm return 16; case 5: // op: rot return 13; case 4: // op: idx return 11; } break; } case AArch64::FCMLAv4f16_indexed: { switch (OpNum) { case 1: // op: Rd return 0; case 2: // op: Rn return 5; case 3: // op: Rm return 16; case 5: // op: rot return 13; case 4: // op: idx return 21; } break; } case AArch64::ADDHNv2i64_v4i32: case AArch64::ADDHNv4i32_v8i16: case AArch64::ADDHNv8i16_v16i8: case AArch64::BFDOTv4bf16: case AArch64::BFDOTv8bf16: case AArch64::BFMLALB: case AArch64::BFMLALT: case AArch64::BFMMLA: case AArch64::BIFv8i8: case AArch64::BIFv16i8: case AArch64::BITv8i8: case AArch64::BITv16i8: case AArch64::BSLv8i8: case AArch64::BSLv16i8: case AArch64::FCVTN_F32_F82v16f8: case AArch64::FDOTv2f32: case AArch64::FDOTv4f16: case AArch64::FDOTv4f32: case AArch64::FDOTv8f16: case AArch64::FMLAL2v4f16: case AArch64::FMLAL2v8f16: case AArch64::FMLALBv8f16: case AArch64::FMLALLBBv4f32: case AArch64::FMLALLBTv4f32: case AArch64::FMLALLTBv4f32: case AArch64::FMLALLTTv4f32: case AArch64::FMLALTv8f16: case AArch64::FMLALv4f16: case AArch64::FMLALv8f16: case AArch64::FMLAv2f32: case AArch64::FMLAv2f64: case AArch64::FMLAv4f16: case AArch64::FMLAv4f32: case AArch64::FMLAv8f16: case AArch64::FMLSL2v4f16: case AArch64::FMLSL2v8f16: case AArch64::FMLSLv4f16: case AArch64::FMLSLv8f16: case AArch64::FMLSv2f32: case AArch64::FMLSv2f64: case AArch64::FMLSv4f16: case AArch64::FMLSv4f32: case AArch64::FMLSv8f16: case AArch64::MLAv2i32: case AArch64::MLAv4i16: case AArch64::MLAv4i32: case AArch64::MLAv8i8: case AArch64::MLAv8i16: case AArch64::MLAv16i8: case AArch64::MLSv2i32: case AArch64::MLSv4i16: case AArch64::MLSv4i32: case AArch64::MLSv8i8: case AArch64::MLSv8i16: case AArch64::MLSv16i8: case AArch64::RADDHNv2i64_v4i32: case AArch64::RADDHNv4i32_v8i16: case AArch64::RADDHNv8i16_v16i8: case AArch64::RSUBHNv2i64_v4i32: case AArch64::RSUBHNv4i32_v8i16: case AArch64::RSUBHNv8i16_v16i8: case AArch64::SABALv2i32_v2i64: case AArch64::SABALv4i16_v4i32: case AArch64::SABALv4i32_v2i64: case AArch64::SABALv8i8_v8i16: case AArch64::SABALv8i16_v4i32: case AArch64::SABALv16i8_v8i16: case AArch64::SABAv2i32: case AArch64::SABAv4i16: case AArch64::SABAv4i32: case AArch64::SABAv8i8: case AArch64::SABAv8i16: case AArch64::SABAv16i8: case AArch64::SDOTv8i8: case AArch64::SDOTv16i8: case AArch64::SHA1Crrr: case AArch64::SHA1Mrrr: case AArch64::SHA1Prrr: case AArch64::SHA1SU0rrr: case AArch64::SHA256H2rrr: case AArch64::SHA256Hrrr: case AArch64::SHA256SU1rrr: case AArch64::SMLALv2i32_v2i64: case AArch64::SMLALv4i16_v4i32: case AArch64::SMLALv4i32_v2i64: case AArch64::SMLALv8i8_v8i16: case AArch64::SMLALv8i16_v4i32: case AArch64::SMLALv16i8_v8i16: case AArch64::SMLSLv2i32_v2i64: case AArch64::SMLSLv4i16_v4i32: case AArch64::SMLSLv4i32_v2i64: case AArch64::SMLSLv8i8_v8i16: case AArch64::SMLSLv8i16_v4i32: case AArch64::SMLSLv16i8_v8i16: case AArch64::SMMLA: case AArch64::SQDMLALi16: case AArch64::SQDMLALi32: case AArch64::SQDMLALv2i32_v2i64: case AArch64::SQDMLALv4i16_v4i32: case AArch64::SQDMLALv4i32_v2i64: case AArch64::SQDMLALv8i16_v4i32: case AArch64::SQDMLSLi16: case AArch64::SQDMLSLi32: case AArch64::SQDMLSLv2i32_v2i64: case AArch64::SQDMLSLv4i16_v4i32: case AArch64::SQDMLSLv4i32_v2i64: case AArch64::SQDMLSLv8i16_v4i32: case AArch64::SQRDMLAHv1i16: case AArch64::SQRDMLAHv1i32: case AArch64::SQRDMLAHv2i32: case AArch64::SQRDMLAHv4i16: case AArch64::SQRDMLAHv4i32: case AArch64::SQRDMLAHv8i16: case AArch64::SQRDMLSHv1i16: case AArch64::SQRDMLSHv1i32: case AArch64::SQRDMLSHv2i32: case AArch64::SQRDMLSHv4i16: case AArch64::SQRDMLSHv4i32: case AArch64::SQRDMLSHv8i16: case AArch64::SUBHNv2i64_v4i32: case AArch64::SUBHNv4i32_v8i16: case AArch64::SUBHNv8i16_v16i8: case AArch64::UABALv2i32_v2i64: case AArch64::UABALv4i16_v4i32: case AArch64::UABALv4i32_v2i64: case AArch64::UABALv8i8_v8i16: case AArch64::UABALv8i16_v4i32: case AArch64::UABALv16i8_v8i16: case AArch64::UABAv2i32: case AArch64::UABAv4i16: case AArch64::UABAv4i32: case AArch64::UABAv8i8: case AArch64::UABAv8i16: case AArch64::UABAv16i8: case AArch64::UDOTv8i8: case AArch64::UDOTv16i8: case AArch64::UMLALv2i32_v2i64: case AArch64::UMLALv4i16_v4i32: case AArch64::UMLALv4i32_v2i64: case AArch64::UMLALv8i8_v8i16: case AArch64::UMLALv8i16_v4i32: case AArch64::UMLALv16i8_v8i16: case AArch64::UMLSLv2i32_v2i64: case AArch64::UMLSLv4i16_v4i32: case AArch64::UMLSLv4i32_v2i64: case AArch64::UMLSLv8i8_v8i16: case AArch64::UMLSLv8i16_v4i32: case AArch64::UMLSLv16i8_v8i16: case AArch64::UMMLA: case AArch64::USDOTv8i8: case AArch64::USDOTv16i8: case AArch64::USMMLA: { switch (OpNum) { case 1: // op: Rd return 0; case 2: // op: Rn return 5; case 3: // op: Rm return 16; } break; } case AArch64::RSHRNv4i32_shift: case AArch64::RSHRNv8i16_shift: case AArch64::RSHRNv16i8_shift: case AArch64::SHRNv4i32_shift: case AArch64::SHRNv8i16_shift: case AArch64::SHRNv16i8_shift: case AArch64::SLId: case AArch64::SLIv2i32_shift: case AArch64::SLIv2i64_shift: case AArch64::SLIv4i16_shift: case AArch64::SLIv4i32_shift: case AArch64::SLIv8i8_shift: case AArch64::SLIv8i16_shift: case AArch64::SLIv16i8_shift: case AArch64::SQRSHRNv4i32_shift: case AArch64::SQRSHRNv8i16_shift: case AArch64::SQRSHRNv16i8_shift: case AArch64::SQRSHRUNv4i32_shift: case AArch64::SQRSHRUNv8i16_shift: case AArch64::SQRSHRUNv16i8_shift: case AArch64::SQSHRNv4i32_shift: case AArch64::SQSHRNv8i16_shift: case AArch64::SQSHRNv16i8_shift: case AArch64::SQSHRUNv4i32_shift: case AArch64::SQSHRUNv8i16_shift: case AArch64::SQSHRUNv16i8_shift: case AArch64::SRId: case AArch64::SRIv2i32_shift: case AArch64::SRIv2i64_shift: case AArch64::SRIv4i16_shift: case AArch64::SRIv4i32_shift: case AArch64::SRIv8i8_shift: case AArch64::SRIv8i16_shift: case AArch64::SRIv16i8_shift: case AArch64::SRSRAd: case AArch64::SRSRAv2i32_shift: case AArch64::SRSRAv2i64_shift: case AArch64::SRSRAv4i16_shift: case AArch64::SRSRAv4i32_shift: case AArch64::SRSRAv8i8_shift: case AArch64::SRSRAv8i16_shift: case AArch64::SRSRAv16i8_shift: case AArch64::SSRAd: case AArch64::SSRAv2i32_shift: case AArch64::SSRAv2i64_shift: case AArch64::SSRAv4i16_shift: case AArch64::SSRAv4i32_shift: case AArch64::SSRAv8i8_shift: case AArch64::SSRAv8i16_shift: case AArch64::SSRAv16i8_shift: case AArch64::UQRSHRNv4i32_shift: case AArch64::UQRSHRNv8i16_shift: case AArch64::UQRSHRNv16i8_shift: case AArch64::UQSHRNv4i32_shift: case AArch64::UQSHRNv8i16_shift: case AArch64::UQSHRNv16i8_shift: case AArch64::URSRAd: case AArch64::URSRAv2i32_shift: case AArch64::URSRAv2i64_shift: case AArch64::URSRAv4i16_shift: case AArch64::URSRAv4i32_shift: case AArch64::URSRAv8i8_shift: case AArch64::URSRAv8i16_shift: case AArch64::URSRAv16i8_shift: case AArch64::USRAd: case AArch64::USRAv2i32_shift: case AArch64::USRAv2i64_shift: case AArch64::USRAv4i16_shift: case AArch64::USRAv4i32_shift: case AArch64::USRAv8i8_shift: case AArch64::USRAv8i16_shift: case AArch64::USRAv16i8_shift: { switch (OpNum) { case 1: // op: Rd return 0; case 2: // op: Rn return 5; case 3: // op: imm return 16; } break; } case AArch64::AESDrr: case AArch64::AESErr: case AArch64::AUTDA: case AArch64::AUTDB: case AArch64::AUTIA: case AArch64::AUTIB: case AArch64::BFCVTN2: case AArch64::FCVTNv4i32: case AArch64::FCVTNv8i16: case AArch64::FCVTXNv4f32: case AArch64::PACDA: case AArch64::PACDB: case AArch64::PACIA: case AArch64::PACIB: case AArch64::SADALPv2i32_v1i64: case AArch64::SADALPv4i16_v2i32: case AArch64::SADALPv4i32_v2i64: case AArch64::SADALPv8i8_v4i16: case AArch64::SADALPv8i16_v4i32: case AArch64::SADALPv16i8_v8i16: case AArch64::SHA1SU1rr: case AArch64::SHA256SU0rr: case AArch64::SQXTNv4i32: case AArch64::SQXTNv8i16: case AArch64::SQXTNv16i8: case AArch64::SQXTUNv4i32: case AArch64::SQXTUNv8i16: case AArch64::SQXTUNv16i8: case AArch64::SUQADDv1i8: case AArch64::SUQADDv1i16: case AArch64::SUQADDv1i32: case AArch64::SUQADDv1i64: case AArch64::SUQADDv2i32: case AArch64::SUQADDv2i64: case AArch64::SUQADDv4i16: case AArch64::SUQADDv4i32: case AArch64::SUQADDv8i8: case AArch64::SUQADDv8i16: case AArch64::SUQADDv16i8: case AArch64::UADALPv2i32_v1i64: case AArch64::UADALPv4i16_v2i32: case AArch64::UADALPv4i32_v2i64: case AArch64::UADALPv8i8_v4i16: case AArch64::UADALPv8i16_v4i32: case AArch64::UADALPv16i8_v8i16: case AArch64::UQXTNv4i32: case AArch64::UQXTNv8i16: case AArch64::UQXTNv16i8: case AArch64::USQADDv1i8: case AArch64::USQADDv1i16: case AArch64::USQADDv1i32: case AArch64::USQADDv1i64: case AArch64::USQADDv2i32: case AArch64::USQADDv2i64: case AArch64::USQADDv4i16: case AArch64::USQADDv4i32: case AArch64::USQADDv8i8: case AArch64::USQADDv8i16: case AArch64::USQADDv16i8: case AArch64::XTNv4i32: case AArch64::XTNv8i16: case AArch64::XTNv16i8: { switch (OpNum) { case 1: // op: Rd return 0; case 2: // op: Rn return 5; } break; } case AArch64::BICv2i32: case AArch64::BICv4i16: case AArch64::BICv4i32: case AArch64::BICv8i16: case AArch64::ORRv2i32: case AArch64::ORRv4i16: case AArch64::ORRv4i32: case AArch64::ORRv8i16: { switch (OpNum) { case 1: // op: Rd return 0; case 2: // op: imm8 return 5; case 3: // op: shift return 13; } break; } case AArch64::INSvi8lane: { switch (OpNum) { case 1: // op: Rd return 0; case 3: // op: Rn return 5; case 2: // op: idx return 17; case 4: // op: idx2 return 11; } break; } case AArch64::INSvi8gpr: { switch (OpNum) { case 1: // op: Rd return 0; case 3: // op: Rn return 5; case 2: // op: idx return 17; } break; } case AArch64::INSvi16lane: { switch (OpNum) { case 1: // op: Rd return 0; case 3: // op: Rn return 5; case 2: // op: idx return 18; case 4: // op: idx2 return 12; } break; } case AArch64::INSvi16gpr: { switch (OpNum) { case 1: // op: Rd return 0; case 3: // op: Rn return 5; case 2: // op: idx return 18; } break; } case AArch64::INSvi32lane: { switch (OpNum) { case 1: // op: Rd return 0; case 3: // op: Rn return 5; case 2: // op: idx return 19; case 4: // op: idx2 return 13; } break; } case AArch64::INSvi32gpr: { switch (OpNum) { case 1: // op: Rd return 0; case 3: // op: Rn return 5; case 2: // op: idx return 19; } break; } case AArch64::INSvi64lane: { switch (OpNum) { case 1: // op: Rd return 0; case 3: // op: Rn return 5; case 2: // op: idx return 20; case 4: // op: idx2 return 14; } break; } case AArch64::INSvi64gpr: { switch (OpNum) { case 1: // op: Rd return 0; case 3: // op: Rn return 5; case 2: // op: idx return 20; } break; } case AArch64::AUTDZA: case AArch64::AUTDZB: case AArch64::AUTIZA: case AArch64::AUTIZB: case AArch64::PACDZA: case AArch64::PACDZB: case AArch64::PACIZA: case AArch64::PACIZB: { switch (OpNum) { case 1: // op: Rd return 0; } break; } case AArch64::CTERMEQ_WW: case AArch64::CTERMEQ_XX: case AArch64::CTERMNE_WW: case AArch64::CTERMNE_XX: case AArch64::FCMPDrr: case AArch64::FCMPEDrr: case AArch64::FCMPEHrr: case AArch64::FCMPESrr: case AArch64::FCMPHrr: case AArch64::FCMPSrr: { switch (OpNum) { case 1: // op: Rm return 16; case 0: // op: Rn return 5; } break; } case AArch64::ST2Gi: case AArch64::STGi: case AArch64::STZ2Gi: case AArch64::STZGi: { switch (OpNum) { case 1: // op: Rn return 5; case 0: // op: Rt return 0; case 2: // op: offset return 12; } break; } case AArch64::LDAPRB: case AArch64::LDAPRH: case AArch64::LDAPRW: case AArch64::LDAPRX: case AArch64::LDGM: case AArch64::STGM: case AArch64::STZGM: { switch (OpNum) { case 1: // op: Rn return 5; case 0: // op: Rt return 0; } break; } case AArch64::INDEX_RI_B: case AArch64::INDEX_RI_D: case AArch64::INDEX_RI_H: case AArch64::INDEX_RI_S: { switch (OpNum) { case 1: // op: Rn return 5; case 0: // op: Zd return 0; case 2: // op: imm5 return 16; } break; } case AArch64::DUP_ZR_B: case AArch64::DUP_ZR_D: case AArch64::DUP_ZR_H: case AArch64::DUP_ZR_S: { switch (OpNum) { case 1: // op: Rn return 5; case 0: // op: Zd return 0; } break; } case AArch64::LDR_ZXI: case AArch64::STR_ZXI: { switch (OpNum) { case 1: // op: Rn return 5; case 0: // op: Zt return 0; case 2: // op: imm9 return 10; } break; } case AArch64::LDR_TX: case AArch64::STR_TX: { switch (OpNum) { case 1: // op: Rn return 5; } break; } case AArch64::LDADDAB: case AArch64::LDADDAH: case AArch64::LDADDALB: case AArch64::LDADDALH: case AArch64::LDADDALW: case AArch64::LDADDALX: case AArch64::LDADDAW: case AArch64::LDADDAX: case AArch64::LDADDB: case AArch64::LDADDH: case AArch64::LDADDLB: case AArch64::LDADDLH: case AArch64::LDADDLW: case AArch64::LDADDLX: case AArch64::LDADDW: case AArch64::LDADDX: case AArch64::LDCLRAB: case AArch64::LDCLRAH: case AArch64::LDCLRALB: case AArch64::LDCLRALH: case AArch64::LDCLRALW: case AArch64::LDCLRALX: case AArch64::LDCLRAW: case AArch64::LDCLRAX: case AArch64::LDCLRB: case AArch64::LDCLRH: case AArch64::LDCLRLB: case AArch64::LDCLRLH: case AArch64::LDCLRLW: case AArch64::LDCLRLX: case AArch64::LDCLRW: case AArch64::LDCLRX: case AArch64::LDEORAB: case AArch64::LDEORAH: case AArch64::LDEORALB: case AArch64::LDEORALH: case AArch64::LDEORALW: case AArch64::LDEORALX: case AArch64::LDEORAW: case AArch64::LDEORAX: case AArch64::LDEORB: case AArch64::LDEORH: case AArch64::LDEORLB: case AArch64::LDEORLH: case AArch64::LDEORLW: case AArch64::LDEORLX: case AArch64::LDEORW: case AArch64::LDEORX: case AArch64::LDSETAB: case AArch64::LDSETAH: case AArch64::LDSETALB: case AArch64::LDSETALH: case AArch64::LDSETALW: case AArch64::LDSETALX: case AArch64::LDSETAW: case AArch64::LDSETAX: case AArch64::LDSETB: case AArch64::LDSETH: case AArch64::LDSETLB: case AArch64::LDSETLH: case AArch64::LDSETLW: case AArch64::LDSETLX: case AArch64::LDSETW: case AArch64::LDSETX: case AArch64::LDSMAXAB: case AArch64::LDSMAXAH: case AArch64::LDSMAXALB: case AArch64::LDSMAXALH: case AArch64::LDSMAXALW: case AArch64::LDSMAXALX: case AArch64::LDSMAXAW: case AArch64::LDSMAXAX: case AArch64::LDSMAXB: case AArch64::LDSMAXH: case AArch64::LDSMAXLB: case AArch64::LDSMAXLH: case AArch64::LDSMAXLW: case AArch64::LDSMAXLX: case AArch64::LDSMAXW: case AArch64::LDSMAXX: case AArch64::LDSMINAB: case AArch64::LDSMINAH: case AArch64::LDSMINALB: case AArch64::LDSMINALH: case AArch64::LDSMINALW: case AArch64::LDSMINALX: case AArch64::LDSMINAW: case AArch64::LDSMINAX: case AArch64::LDSMINB: case AArch64::LDSMINH: case AArch64::LDSMINLB: case AArch64::LDSMINLH: case AArch64::LDSMINLW: case AArch64::LDSMINLX: case AArch64::LDSMINW: case AArch64::LDSMINX: case AArch64::LDUMAXAB: case AArch64::LDUMAXAH: case AArch64::LDUMAXALB: case AArch64::LDUMAXALH: case AArch64::LDUMAXALW: case AArch64::LDUMAXALX: case AArch64::LDUMAXAW: case AArch64::LDUMAXAX: case AArch64::LDUMAXB: case AArch64::LDUMAXH: case AArch64::LDUMAXLB: case AArch64::LDUMAXLH: case AArch64::LDUMAXLW: case AArch64::LDUMAXLX: case AArch64::LDUMAXW: case AArch64::LDUMAXX: case AArch64::LDUMINAB: case AArch64::LDUMINAH: case AArch64::LDUMINALB: case AArch64::LDUMINALH: case AArch64::LDUMINALW: case AArch64::LDUMINALX: case AArch64::LDUMINAW: case AArch64::LDUMINAX: case AArch64::LDUMINB: case AArch64::LDUMINH: case AArch64::LDUMINLB: case AArch64::LDUMINLH: case AArch64::LDUMINLW: case AArch64::LDUMINLX: case AArch64::LDUMINW: case AArch64::LDUMINX: case AArch64::RCWCLR: case AArch64::RCWCLRA: case AArch64::RCWCLRAL: case AArch64::RCWCLRL: case AArch64::RCWCLRS: case AArch64::RCWCLRSA: case AArch64::RCWCLRSAL: case AArch64::RCWCLRSL: case AArch64::RCWSET: case AArch64::RCWSETA: case AArch64::RCWSETAL: case AArch64::RCWSETL: case AArch64::RCWSETS: case AArch64::RCWSETSA: case AArch64::RCWSETSAL: case AArch64::RCWSETSL: case AArch64::RCWSWP: case AArch64::RCWSWPA: case AArch64::RCWSWPAL: case AArch64::RCWSWPL: case AArch64::RCWSWPS: case AArch64::RCWSWPSA: case AArch64::RCWSWPSAL: case AArch64::RCWSWPSL: case AArch64::SWPAB: case AArch64::SWPAH: case AArch64::SWPALB: case AArch64::SWPALH: case AArch64::SWPALW: case AArch64::SWPALX: case AArch64::SWPAW: case AArch64::SWPAX: case AArch64::SWPB: case AArch64::SWPH: case AArch64::SWPLB: case AArch64::SWPLH: case AArch64::SWPLW: case AArch64::SWPLX: case AArch64::SWPW: case AArch64::SWPX: { switch (OpNum) { case 1: // op: Rs return 16; case 2: // op: Rn return 5; case 0: // op: Rt return 0; } break; } case AArch64::CASAB: case AArch64::CASAH: case AArch64::CASALB: case AArch64::CASALH: case AArch64::CASALW: case AArch64::CASALX: case AArch64::CASAW: case AArch64::CASAX: case AArch64::CASB: case AArch64::CASH: case AArch64::CASLB: case AArch64::CASLH: case AArch64::CASLW: case AArch64::CASLX: case AArch64::CASPALW: case AArch64::CASPALX: case AArch64::CASPAW: case AArch64::CASPAX: case AArch64::CASPLW: case AArch64::CASPLX: case AArch64::CASPW: case AArch64::CASPX: case AArch64::CASW: case AArch64::CASX: case AArch64::RCWCAS: case AArch64::RCWCASA: case AArch64::RCWCASAL: case AArch64::RCWCASL: case AArch64::RCWCASP: case AArch64::RCWCASPA: case AArch64::RCWCASPAL: case AArch64::RCWCASPL: case AArch64::RCWSCAS: case AArch64::RCWSCASA: case AArch64::RCWSCASAL: case AArch64::RCWSCASL: case AArch64::RCWSCASP: case AArch64::RCWSCASPA: case AArch64::RCWSCASPAL: case AArch64::RCWSCASPL: { switch (OpNum) { case 1: // op: Rs return 16; case 3: // op: Rn return 5; case 2: // op: Rt return 0; } break; } case AArch64::MSR: case AArch64::MSRR: { switch (OpNum) { case 1: // op: Rt return 0; case 0: // op: systemreg return 5; } break; } case AArch64::ST64BV: case AArch64::ST64BV0: { switch (OpNum) { case 1: // op: Rt return 0; case 2: // op: Rn return 5; case 0: // op: Rs return 16; } break; } case AArch64::LDRBBpost: case AArch64::LDRBBpre: case AArch64::LDRBpost: case AArch64::LDRBpre: case AArch64::LDRDpost: case AArch64::LDRDpre: case AArch64::LDRHHpost: case AArch64::LDRHHpre: case AArch64::LDRHpost: case AArch64::LDRHpre: case AArch64::LDRQpost: case AArch64::LDRQpre: case AArch64::LDRSBWpost: case AArch64::LDRSBWpre: case AArch64::LDRSBXpost: case AArch64::LDRSBXpre: case AArch64::LDRSHWpost: case AArch64::LDRSHWpre: case AArch64::LDRSHXpost: case AArch64::LDRSHXpre: case AArch64::LDRSWpost: case AArch64::LDRSWpre: case AArch64::LDRSpost: case AArch64::LDRSpre: case AArch64::LDRWpost: case AArch64::LDRWpre: case AArch64::LDRXpost: case AArch64::LDRXpre: case AArch64::STRBBpost: case AArch64::STRBBpre: case AArch64::STRBpost: case AArch64::STRBpre: case AArch64::STRDpost: case AArch64::STRDpre: case AArch64::STRHHpost: case AArch64::STRHHpre: case AArch64::STRHpost: case AArch64::STRHpre: case AArch64::STRQpost: case AArch64::STRQpre: case AArch64::STRSpost: case AArch64::STRSpre: case AArch64::STRWpost: case AArch64::STRWpre: case AArch64::STRXpost: case AArch64::STRXpre: { switch (OpNum) { case 1: // op: Rt return 0; case 2: // op: Rn return 5; case 3: // op: offset return 12; } break; } case AArch64::LDAPRWpost: case AArch64::LDAPRXpost: case AArch64::STLRWpre: case AArch64::STLRXpre: { switch (OpNum) { case 1: // op: Rt return 0; case 2: // op: Rn return 5; } break; } case AArch64::LDPDpost: case AArch64::LDPDpre: case AArch64::LDPQpost: case AArch64::LDPQpre: case AArch64::LDPSWpost: case AArch64::LDPSWpre: case AArch64::LDPSpost: case AArch64::LDPSpre: case AArch64::LDPWpost: case AArch64::LDPWpre: case AArch64::LDPXpost: case AArch64::LDPXpre: case AArch64::STGPpost: case AArch64::STGPpre: case AArch64::STPDpost: case AArch64::STPDpre: case AArch64::STPQpost: case AArch64::STPQpre: case AArch64::STPSpost: case AArch64::STPSpre: case AArch64::STPWpost: case AArch64::STPWpre: case AArch64::STPXpost: case AArch64::STPXpre: { switch (OpNum) { case 1: // op: Rt return 0; case 2: // op: Rt2 return 10; case 3: // op: Rn return 5; case 4: // op: offset return 15; } break; } case AArch64::LDIAPPWpost: case AArch64::LDIAPPXpost: case AArch64::STILPWpre: case AArch64::STILPXpre: { switch (OpNum) { case 1: // op: Rt return 0; case 3: // op: Rn return 5; case 2: // op: Rt2 return 16; } break; } case AArch64::LDR_ZA: case AArch64::STR_ZA: { switch (OpNum) { case 1: // op: Rv return 13; case 3: // op: Rn return 5; case 2: // op: imm4 return 0; } break; } case AArch64::SHA512H: case AArch64::SHA512H2: case AArch64::SHA512SU1: case AArch64::SM3PARTW1: case AArch64::SM3PARTW2: case AArch64::TBXv8i8Four: case AArch64::TBXv8i8One: case AArch64::TBXv8i8Three: case AArch64::TBXv8i8Two: case AArch64::TBXv16i8Four: case AArch64::TBXv16i8One: case AArch64::TBXv16i8Three: case AArch64::TBXv16i8Two: { switch (OpNum) { case 1: // op: Vd return 0; case 2: // op: Vn return 5; case 3: // op: Vm return 16; } break; } case AArch64::SM3TT1A: case AArch64::SM3TT1B: case AArch64::SM3TT2A: case AArch64::SM3TT2B: { switch (OpNum) { case 1: // op: Vd return 0; case 2: // op: Vn return 5; case 4: // op: imm return 12; case 3: // op: Vm return 16; } break; } case AArch64::SHA512SU0: case AArch64::SM4E: { switch (OpNum) { case 1: // op: Vd return 0; case 2: // op: Vn return 5; } break; } case AArch64::LD1Fourv1d_POST: case AArch64::LD1Fourv2d_POST: case AArch64::LD1Fourv2s_POST: case AArch64::LD1Fourv4h_POST: case AArch64::LD1Fourv4s_POST: case AArch64::LD1Fourv8b_POST: case AArch64::LD1Fourv8h_POST: case AArch64::LD1Fourv16b_POST: case AArch64::LD1Onev1d_POST: case AArch64::LD1Onev2d_POST: case AArch64::LD1Onev2s_POST: case AArch64::LD1Onev4h_POST: case AArch64::LD1Onev4s_POST: case AArch64::LD1Onev8b_POST: case AArch64::LD1Onev8h_POST: case AArch64::LD1Onev16b_POST: case AArch64::LD1Rv1d_POST: case AArch64::LD1Rv2d_POST: case AArch64::LD1Rv2s_POST: case AArch64::LD1Rv4h_POST: case AArch64::LD1Rv4s_POST: case AArch64::LD1Rv8b_POST: case AArch64::LD1Rv8h_POST: case AArch64::LD1Rv16b_POST: case AArch64::LD1Threev1d_POST: case AArch64::LD1Threev2d_POST: case AArch64::LD1Threev2s_POST: case AArch64::LD1Threev4h_POST: case AArch64::LD1Threev4s_POST: case AArch64::LD1Threev8b_POST: case AArch64::LD1Threev8h_POST: case AArch64::LD1Threev16b_POST: case AArch64::LD1Twov1d_POST: case AArch64::LD1Twov2d_POST: case AArch64::LD1Twov2s_POST: case AArch64::LD1Twov4h_POST: case AArch64::LD1Twov4s_POST: case AArch64::LD1Twov8b_POST: case AArch64::LD1Twov8h_POST: case AArch64::LD1Twov16b_POST: case AArch64::LD2Rv1d_POST: case AArch64::LD2Rv2d_POST: case AArch64::LD2Rv2s_POST: case AArch64::LD2Rv4h_POST: case AArch64::LD2Rv4s_POST: case AArch64::LD2Rv8b_POST: case AArch64::LD2Rv8h_POST: case AArch64::LD2Rv16b_POST: case AArch64::LD2Twov2d_POST: case AArch64::LD2Twov2s_POST: case AArch64::LD2Twov4h_POST: case AArch64::LD2Twov4s_POST: case AArch64::LD2Twov8b_POST: case AArch64::LD2Twov8h_POST: case AArch64::LD2Twov16b_POST: case AArch64::LD3Rv1d_POST: case AArch64::LD3Rv2d_POST: case AArch64::LD3Rv2s_POST: case AArch64::LD3Rv4h_POST: case AArch64::LD3Rv4s_POST: case AArch64::LD3Rv8b_POST: case AArch64::LD3Rv8h_POST: case AArch64::LD3Rv16b_POST: case AArch64::LD3Threev2d_POST: case AArch64::LD3Threev2s_POST: case AArch64::LD3Threev4h_POST: case AArch64::LD3Threev4s_POST: case AArch64::LD3Threev8b_POST: case AArch64::LD3Threev8h_POST: case AArch64::LD3Threev16b_POST: case AArch64::LD4Fourv2d_POST: case AArch64::LD4Fourv2s_POST: case AArch64::LD4Fourv4h_POST: case AArch64::LD4Fourv4s_POST: case AArch64::LD4Fourv8b_POST: case AArch64::LD4Fourv8h_POST: case AArch64::LD4Fourv16b_POST: case AArch64::LD4Rv1d_POST: case AArch64::LD4Rv2d_POST: case AArch64::LD4Rv2s_POST: case AArch64::LD4Rv4h_POST: case AArch64::LD4Rv4s_POST: case AArch64::LD4Rv8b_POST: case AArch64::LD4Rv8h_POST: case AArch64::LD4Rv16b_POST: case AArch64::ST1Fourv1d_POST: case AArch64::ST1Fourv2d_POST: case AArch64::ST1Fourv2s_POST: case AArch64::ST1Fourv4h_POST: case AArch64::ST1Fourv4s_POST: case AArch64::ST1Fourv8b_POST: case AArch64::ST1Fourv8h_POST: case AArch64::ST1Fourv16b_POST: case AArch64::ST1Onev1d_POST: case AArch64::ST1Onev2d_POST: case AArch64::ST1Onev2s_POST: case AArch64::ST1Onev4h_POST: case AArch64::ST1Onev4s_POST: case AArch64::ST1Onev8b_POST: case AArch64::ST1Onev8h_POST: case AArch64::ST1Onev16b_POST: case AArch64::ST1Threev1d_POST: case AArch64::ST1Threev2d_POST: case AArch64::ST1Threev2s_POST: case AArch64::ST1Threev4h_POST: case AArch64::ST1Threev4s_POST: case AArch64::ST1Threev8b_POST: case AArch64::ST1Threev8h_POST: case AArch64::ST1Threev16b_POST: case AArch64::ST1Twov1d_POST: case AArch64::ST1Twov2d_POST: case AArch64::ST1Twov2s_POST: case AArch64::ST1Twov4h_POST: case AArch64::ST1Twov4s_POST: case AArch64::ST1Twov8b_POST: case AArch64::ST1Twov8h_POST: case AArch64::ST1Twov16b_POST: case AArch64::ST2Twov2d_POST: case AArch64::ST2Twov2s_POST: case AArch64::ST2Twov4h_POST: case AArch64::ST2Twov4s_POST: case AArch64::ST2Twov8b_POST: case AArch64::ST2Twov8h_POST: case AArch64::ST2Twov16b_POST: case AArch64::ST3Threev2d_POST: case AArch64::ST3Threev2s_POST: case AArch64::ST3Threev4h_POST: case AArch64::ST3Threev4s_POST: case AArch64::ST3Threev8b_POST: case AArch64::ST3Threev8h_POST: case AArch64::ST3Threev16b_POST: case AArch64::ST4Fourv2d_POST: case AArch64::ST4Fourv2s_POST: case AArch64::ST4Fourv4h_POST: case AArch64::ST4Fourv4s_POST: case AArch64::ST4Fourv8b_POST: case AArch64::ST4Fourv8h_POST: case AArch64::ST4Fourv16b_POST: { switch (OpNum) { case 1: // op: Vt return 0; case 2: // op: Rn return 5; case 3: // op: Xm return 16; } break; } case AArch64::LDAP1: { switch (OpNum) { case 1: // op: Vt return 0; case 3: // op: Rn return 5; case 2: // op: Q return 30; } break; } case AArch64::ST1i8_POST: case AArch64::ST2i8_POST: case AArch64::ST3i8_POST: case AArch64::ST4i8_POST: { switch (OpNum) { case 1: // op: Vt return 0; case 3: // op: Rn return 5; case 2: // op: idx return 10; case 4: // op: Xm return 16; } break; } case AArch64::LD1i8: case AArch64::LD2i8: case AArch64::LD3i8: case AArch64::LD4i8: { switch (OpNum) { case 1: // op: Vt return 0; case 3: // op: Rn return 5; case 2: // op: idx return 10; } break; } case AArch64::ST1i16_POST: case AArch64::ST2i16_POST: case AArch64::ST3i16_POST: case AArch64::ST4i16_POST: { switch (OpNum) { case 1: // op: Vt return 0; case 3: // op: Rn return 5; case 2: // op: idx return 11; case 4: // op: Xm return 16; } break; } case AArch64::LD1i16: case AArch64::LD2i16: case AArch64::LD3i16: case AArch64::LD4i16: { switch (OpNum) { case 1: // op: Vt return 0; case 3: // op: Rn return 5; case 2: // op: idx return 11; } break; } case AArch64::ST1i32_POST: case AArch64::ST2i32_POST: case AArch64::ST3i32_POST: case AArch64::ST4i32_POST: { switch (OpNum) { case 1: // op: Vt return 0; case 3: // op: Rn return 5; case 2: // op: idx return 12; case 4: // op: Xm return 16; } break; } case AArch64::LD1i32: case AArch64::LD2i32: case AArch64::LD3i32: case AArch64::LD4i32: { switch (OpNum) { case 1: // op: Vt return 0; case 3: // op: Rn return 5; case 2: // op: idx return 12; } break; } case AArch64::ST1i64_POST: case AArch64::ST2i64_POST: case AArch64::ST3i64_POST: case AArch64::ST4i64_POST: { switch (OpNum) { case 1: // op: Vt return 0; case 3: // op: Rn return 5; case 2: // op: idx return 30; case 4: // op: Xm return 16; } break; } case AArch64::LD1i64: case AArch64::LD2i64: case AArch64::LD3i64: case AArch64::LD4i64: { switch (OpNum) { case 1: // op: Vt return 0; case 3: // op: Rn return 5; case 2: // op: idx return 30; } break; } case AArch64::BF1CVTL_2ZZ_BtoH_NAME: case AArch64::BF1CVT_2ZZ_BtoH_NAME: case AArch64::BF2CVTL_2ZZ_BtoH_NAME: case AArch64::BF2CVT_2ZZ_BtoH_NAME: case AArch64::F1CVTL_2ZZ_BtoH_NAME: case AArch64::F1CVT_2ZZ_BtoH_NAME: case AArch64::F2CVTL_2ZZ_BtoH_NAME: case AArch64::F2CVT_2ZZ_BtoH_NAME: case AArch64::FCVTL_2ZZ_H_S: case AArch64::FCVT_2ZZ_H_S: case AArch64::SUNPK_VG2_2ZZ_D: case AArch64::SUNPK_VG2_2ZZ_H: case AArch64::SUNPK_VG2_2ZZ_S: case AArch64::UUNPK_VG2_2ZZ_D: case AArch64::UUNPK_VG2_2ZZ_H: case AArch64::UUNPK_VG2_2ZZ_S: { switch (OpNum) { case 1: // op: Zn return 5; case 0: // op: Zd return 1; } break; } case AArch64::BFCVTN_Z2Z_StoH: case AArch64::BFCVT_Z2Z_HtoB: case AArch64::BFCVT_Z2Z_StoH: case AArch64::FCVTN_Z2Z_StoH: case AArch64::FCVT_Z2Z_HtoB: case AArch64::FCVT_Z2Z_StoH: case AArch64::SQCVTU_Z2Z_StoH: case AArch64::SQCVT_Z2Z_StoH: case AArch64::UQCVT_Z2Z_StoH: { switch (OpNum) { case 1: // op: Zn return 6; case 0: // op: Zd return 0; } break; } case AArch64::FCVTZS_2Z2Z_StoS: case AArch64::FCVTZU_2Z2Z_StoS: case AArch64::FRINTA_2Z2Z_S: case AArch64::FRINTM_2Z2Z_S: case AArch64::FRINTN_2Z2Z_S: case AArch64::FRINTP_2Z2Z_S: case AArch64::SCVTF_2Z2Z_StoS: case AArch64::UCVTF_2Z2Z_StoS: { switch (OpNum) { case 1: // op: Zn return 6; case 0: // op: Zd return 1; } break; } case AArch64::SUNPK_VG4_4Z2Z_D: case AArch64::SUNPK_VG4_4Z2Z_H: case AArch64::SUNPK_VG4_4Z2Z_S: case AArch64::UUNPK_VG4_4Z2Z_D: case AArch64::UUNPK_VG4_4Z2Z_H: case AArch64::UUNPK_VG4_4Z2Z_S: { switch (OpNum) { case 1: // op: Zn return 6; case 0: // op: Zd return 2; } break; } case AArch64::SQRSHRN_VG4_Z4ZI_B: case AArch64::SQRSHRN_VG4_Z4ZI_H: case AArch64::SQRSHRUN_VG4_Z4ZI_B: case AArch64::SQRSHRUN_VG4_Z4ZI_H: case AArch64::SQRSHRU_VG4_Z4ZI_B: case AArch64::SQRSHRU_VG4_Z4ZI_H: case AArch64::SQRSHR_VG4_Z4ZI_B: case AArch64::SQRSHR_VG4_Z4ZI_H: case AArch64::UQRSHRN_VG4_Z4ZI_B: case AArch64::UQRSHRN_VG4_Z4ZI_H: case AArch64::UQRSHR_VG4_Z4ZI_B: case AArch64::UQRSHR_VG4_Z4ZI_H: { switch (OpNum) { case 1: // op: Zn return 7; case 0: // op: Zd return 0; case 2: // op: imm return 16; } break; } case AArch64::FCVTN_Z4Z_StoB_NAME: case AArch64::FCVT_Z4Z_StoB_NAME: case AArch64::SQCVTN_Z4Z_DtoH: case AArch64::SQCVTN_Z4Z_StoB: case AArch64::SQCVTUN_Z4Z_DtoH: case AArch64::SQCVTUN_Z4Z_StoB: case AArch64::SQCVTU_Z4Z_DtoH: case AArch64::SQCVTU_Z4Z_StoB: case AArch64::SQCVT_Z4Z_DtoH: case AArch64::SQCVT_Z4Z_StoB: case AArch64::UQCVTN_Z4Z_DtoH: case AArch64::UQCVTN_Z4Z_StoB: case AArch64::UQCVT_Z4Z_DtoH: case AArch64::UQCVT_Z4Z_StoB: { switch (OpNum) { case 1: // op: Zn return 7; case 0: // op: Zd return 0; } break; } case AArch64::FCVTZS_4Z4Z_StoS: case AArch64::FCVTZU_4Z4Z_StoS: case AArch64::FRINTA_4Z4Z_S: case AArch64::FRINTM_4Z4Z_S: case AArch64::FRINTN_4Z4Z_S: case AArch64::FRINTP_4Z4Z_S: case AArch64::SCVTF_4Z4Z_StoS: case AArch64::UCVTF_4Z4Z_StoS: case AArch64::UZP_VG4_4Z4Z_B: case AArch64::UZP_VG4_4Z4Z_D: case AArch64::UZP_VG4_4Z4Z_H: case AArch64::UZP_VG4_4Z4Z_Q: case AArch64::UZP_VG4_4Z4Z_S: case AArch64::ZIP_VG4_4Z4Z_B: case AArch64::ZIP_VG4_4Z4Z_D: case AArch64::ZIP_VG4_4Z4Z_H: case AArch64::ZIP_VG4_4Z4Z_Q: case AArch64::ZIP_VG4_4Z4Z_S: { switch (OpNum) { case 1: // op: Zn return 7; case 0: // op: Zd return 2; } break; } case AArch64::MOVT_TIX: { switch (OpNum) { case 1: // op: imm3 return 12; case 2: // op: Rt return 0; } break; } case AArch64::ABS_ZPmZ_B: case AArch64::ABS_ZPmZ_D: case AArch64::ABS_ZPmZ_H: case AArch64::ABS_ZPmZ_S: case AArch64::CLS_ZPmZ_B: case AArch64::CLS_ZPmZ_D: case AArch64::CLS_ZPmZ_H: case AArch64::CLS_ZPmZ_S: case AArch64::CLZ_ZPmZ_B: case AArch64::CLZ_ZPmZ_D: case AArch64::CLZ_ZPmZ_H: case AArch64::CLZ_ZPmZ_S: case AArch64::CNOT_ZPmZ_B: case AArch64::CNOT_ZPmZ_D: case AArch64::CNOT_ZPmZ_H: case AArch64::CNOT_ZPmZ_S: case AArch64::CNT_ZPmZ_B: case AArch64::CNT_ZPmZ_D: case AArch64::CNT_ZPmZ_H: case AArch64::CNT_ZPmZ_S: case AArch64::FABS_ZPmZ_D: case AArch64::FABS_ZPmZ_H: case AArch64::FABS_ZPmZ_S: case AArch64::FCVTX_ZPmZ_DtoS: case AArch64::FCVTZS_ZPmZ_DtoD: case AArch64::FCVTZS_ZPmZ_DtoS: case AArch64::FCVTZS_ZPmZ_HtoD: case AArch64::FCVTZS_ZPmZ_HtoH: case AArch64::FCVTZS_ZPmZ_HtoS: case AArch64::FCVTZS_ZPmZ_StoD: case AArch64::FCVTZS_ZPmZ_StoS: case AArch64::FCVTZU_ZPmZ_DtoD: case AArch64::FCVTZU_ZPmZ_DtoS: case AArch64::FCVTZU_ZPmZ_HtoD: case AArch64::FCVTZU_ZPmZ_HtoH: case AArch64::FCVTZU_ZPmZ_HtoS: case AArch64::FCVTZU_ZPmZ_StoD: case AArch64::FCVTZU_ZPmZ_StoS: case AArch64::FCVT_ZPmZ_DtoH: case AArch64::FCVT_ZPmZ_DtoS: case AArch64::FCVT_ZPmZ_HtoD: case AArch64::FCVT_ZPmZ_HtoS: case AArch64::FCVT_ZPmZ_StoD: case AArch64::FCVT_ZPmZ_StoH: case AArch64::FLOGB_ZPmZ_D: case AArch64::FLOGB_ZPmZ_H: case AArch64::FLOGB_ZPmZ_S: case AArch64::FNEG_ZPmZ_D: case AArch64::FNEG_ZPmZ_H: case AArch64::FNEG_ZPmZ_S: case AArch64::FRECPX_ZPmZ_D: case AArch64::FRECPX_ZPmZ_H: case AArch64::FRECPX_ZPmZ_S: case AArch64::FRINTA_ZPmZ_D: case AArch64::FRINTA_ZPmZ_H: case AArch64::FRINTA_ZPmZ_S: case AArch64::FRINTI_ZPmZ_D: case AArch64::FRINTI_ZPmZ_H: case AArch64::FRINTI_ZPmZ_S: case AArch64::FRINTM_ZPmZ_D: case AArch64::FRINTM_ZPmZ_H: case AArch64::FRINTM_ZPmZ_S: case AArch64::FRINTN_ZPmZ_D: case AArch64::FRINTN_ZPmZ_H: case AArch64::FRINTN_ZPmZ_S: case AArch64::FRINTP_ZPmZ_D: case AArch64::FRINTP_ZPmZ_H: case AArch64::FRINTP_ZPmZ_S: case AArch64::FRINTX_ZPmZ_D: case AArch64::FRINTX_ZPmZ_H: case AArch64::FRINTX_ZPmZ_S: case AArch64::FRINTZ_ZPmZ_D: case AArch64::FRINTZ_ZPmZ_H: case AArch64::FRINTZ_ZPmZ_S: case AArch64::FSQRT_ZPmZ_D: case AArch64::FSQRT_ZPmZ_H: case AArch64::FSQRT_ZPmZ_S: case AArch64::MOVPRFX_ZPmZ_B: case AArch64::MOVPRFX_ZPmZ_D: case AArch64::MOVPRFX_ZPmZ_H: case AArch64::MOVPRFX_ZPmZ_S: case AArch64::NEG_ZPmZ_B: case AArch64::NEG_ZPmZ_D: case AArch64::NEG_ZPmZ_H: case AArch64::NEG_ZPmZ_S: case AArch64::NOT_ZPmZ_B: case AArch64::NOT_ZPmZ_D: case AArch64::NOT_ZPmZ_H: case AArch64::NOT_ZPmZ_S: case AArch64::SCVTF_ZPmZ_DtoD: case AArch64::SCVTF_ZPmZ_DtoH: case AArch64::SCVTF_ZPmZ_DtoS: case AArch64::SCVTF_ZPmZ_HtoH: case AArch64::SCVTF_ZPmZ_StoD: case AArch64::SCVTF_ZPmZ_StoH: case AArch64::SCVTF_ZPmZ_StoS: case AArch64::SQABS_ZPmZ_B: case AArch64::SQABS_ZPmZ_D: case AArch64::SQABS_ZPmZ_H: case AArch64::SQABS_ZPmZ_S: case AArch64::SQNEG_ZPmZ_B: case AArch64::SQNEG_ZPmZ_D: case AArch64::SQNEG_ZPmZ_H: case AArch64::SQNEG_ZPmZ_S: case AArch64::SXTB_ZPmZ_D: case AArch64::SXTB_ZPmZ_H: case AArch64::SXTB_ZPmZ_S: case AArch64::SXTH_ZPmZ_D: case AArch64::SXTH_ZPmZ_S: case AArch64::SXTW_ZPmZ_D: case AArch64::UCVTF_ZPmZ_DtoD: case AArch64::UCVTF_ZPmZ_DtoH: case AArch64::UCVTF_ZPmZ_DtoS: case AArch64::UCVTF_ZPmZ_HtoH: case AArch64::UCVTF_ZPmZ_StoD: case AArch64::UCVTF_ZPmZ_StoH: case AArch64::UCVTF_ZPmZ_StoS: case AArch64::URECPE_ZPmZ_S: case AArch64::URSQRTE_ZPmZ_S: case AArch64::UXTB_ZPmZ_D: case AArch64::UXTB_ZPmZ_H: case AArch64::UXTB_ZPmZ_S: case AArch64::UXTH_ZPmZ_D: case AArch64::UXTH_ZPmZ_S: case AArch64::UXTW_ZPmZ_D: { switch (OpNum) { case 2: // op: Pg return 10; case 0: // op: Zd return 0; case 3: // op: Zn return 5; } break; } case AArch64::CPY_ZPmR_B: case AArch64::CPY_ZPmR_D: case AArch64::CPY_ZPmR_H: case AArch64::CPY_ZPmR_S: { switch (OpNum) { case 2: // op: Pg return 10; case 3: // op: Rn return 5; case 0: // op: Zd return 0; } break; } case AArch64::CPY_ZPmV_B: case AArch64::CPY_ZPmV_D: case AArch64::CPY_ZPmV_H: case AArch64::CPY_ZPmV_S: { switch (OpNum) { case 2: // op: Pg return 10; case 3: // op: Vn return 5; case 0: // op: Zd return 0; } break; } case AArch64::FCPY_ZPmI_D: case AArch64::FCPY_ZPmI_H: case AArch64::FCPY_ZPmI_S: { switch (OpNum) { case 2: // op: Pg return 16; case 0: // op: Zd return 0; case 3: // op: imm8 return 5; } break; } case AArch64::DECP_ZP_D: case AArch64::DECP_ZP_H: case AArch64::DECP_ZP_S: case AArch64::INCP_ZP_D: case AArch64::INCP_ZP_H: case AArch64::INCP_ZP_S: case AArch64::SQDECP_ZP_D: case AArch64::SQDECP_ZP_H: case AArch64::SQDECP_ZP_S: case AArch64::SQINCP_ZP_D: case AArch64::SQINCP_ZP_H: case AArch64::SQINCP_ZP_S: case AArch64::UQDECP_ZP_D: case AArch64::UQDECP_ZP_H: case AArch64::UQDECP_ZP_S: case AArch64::UQINCP_ZP_D: case AArch64::UQINCP_ZP_H: case AArch64::UQINCP_ZP_S: { switch (OpNum) { case 2: // op: Pm return 5; case 0: // op: Zdn return 0; } break; } case AArch64::MOPSSETGE: case AArch64::MOPSSETGEN: case AArch64::MOPSSETGET: case AArch64::MOPSSETGETN: case AArch64::SETE: case AArch64::SETEN: case AArch64::SETET: case AArch64::SETETN: case AArch64::SETGM: case AArch64::SETGMN: case AArch64::SETGMT: case AArch64::SETGMTN: case AArch64::SETGP: case AArch64::SETGPN: case AArch64::SETGPT: case AArch64::SETGPTN: case AArch64::SETM: case AArch64::SETMN: case AArch64::SETMT: case AArch64::SETMTN: case AArch64::SETP: case AArch64::SETPN: case AArch64::SETPT: case AArch64::SETPTN: { switch (OpNum) { case 2: // op: Rd return 0; case 3: // op: Rn return 5; case 4: // op: Rm return 16; } break; } case AArch64::INDEX_IR_B: case AArch64::INDEX_IR_D: case AArch64::INDEX_IR_H: case AArch64::INDEX_IR_S: { switch (OpNum) { case 2: // op: Rm return 16; case 0: // op: Zd return 0; case 1: // op: imm5 return 5; } break; } case AArch64::INSR_ZR_B: case AArch64::INSR_ZR_D: case AArch64::INSR_ZR_H: case AArch64::INSR_ZR_S: { switch (OpNum) { case 2: // op: Rm return 5; case 0: // op: Zdn return 0; } break; } case AArch64::PRFB_PRI: case AArch64::PRFD_PRI: case AArch64::PRFH_PRI: case AArch64::PRFW_PRI: { switch (OpNum) { case 2: // op: Rn return 5; case 1: // op: Pg return 10; case 3: // op: imm6 return 16; case 0: // op: prfop return 0; } break; } case AArch64::LDG: case AArch64::ST2GPostIndex: case AArch64::ST2GPreIndex: case AArch64::STGPostIndex: case AArch64::STGPreIndex: case AArch64::STZ2GPostIndex: case AArch64::STZ2GPreIndex: case AArch64::STZGPostIndex: case AArch64::STZGPreIndex: { switch (OpNum) { case 2: // op: Rn return 5; case 1: // op: Rt return 0; case 3: // op: offset return 12; } break; } case AArch64::MOVA_VG2_MXI2Z: { switch (OpNum) { case 2: // op: Rs return 13; case 3: // op: imm return 0; case 4: // op: Zn return 6; } break; } case AArch64::MOVA_VG4_MXI4Z: { switch (OpNum) { case 2: // op: Rs return 13; case 3: // op: imm return 0; case 4: // op: Zn return 7; } break; } case AArch64::MOVA_VG2_2ZMXI: { switch (OpNum) { case 2: // op: Rs return 13; case 3: // op: imm return 5; case 0: // op: Zd return 1; } break; } case AArch64::MOVA_VG4_4ZMXI: { switch (OpNum) { case 2: // op: Rs return 13; case 3: // op: imm return 5; case 0: // op: Zd return 2; } break; } case AArch64::MOVA_MXI2Z_H_D: case AArch64::MOVA_MXI2Z_V_D: { switch (OpNum) { case 2: // op: Rs return 13; case 4: // op: Zn return 6; case 0: // op: ZAd return 0; } break; } case AArch64::MOVA_MXI2Z_H_S: case AArch64::MOVA_MXI2Z_V_S: { switch (OpNum) { case 2: // op: Rs return 13; case 4: // op: Zn return 6; case 0: // op: ZAd return 1; case 3: // op: imm return 0; } break; } case AArch64::MOVA_MXI2Z_H_H: case AArch64::MOVA_MXI2Z_V_H: { switch (OpNum) { case 2: // op: Rs return 13; case 4: // op: Zn return 6; case 0: // op: ZAd return 2; case 3: // op: imm return 0; } break; } case AArch64::MOVA_MXI2Z_H_B: case AArch64::MOVA_MXI2Z_V_B: { switch (OpNum) { case 2: // op: Rs return 13; case 4: // op: Zn return 6; case 3: // op: imm return 0; } break; } case AArch64::MOVA_MXI4Z_H_D: case AArch64::MOVA_MXI4Z_H_S: case AArch64::MOVA_MXI4Z_V_D: case AArch64::MOVA_MXI4Z_V_S: { switch (OpNum) { case 2: // op: Rs return 13; case 4: // op: Zn return 7; case 0: // op: ZAd return 0; } break; } case AArch64::MOVA_MXI4Z_H_H: case AArch64::MOVA_MXI4Z_V_H: { switch (OpNum) { case 2: // op: Rs return 13; case 4: // op: Zn return 7; case 0: // op: ZAd return 1; case 3: // op: imm return 0; } break; } case AArch64::MOVA_MXI4Z_H_B: case AArch64::MOVA_MXI4Z_V_B: { switch (OpNum) { case 2: // op: Rs return 13; case 4: // op: Zn return 7; case 3: // op: imm return 0; } break; } case AArch64::LDCLRP: case AArch64::LDCLRPA: case AArch64::LDCLRPAL: case AArch64::LDCLRPL: case AArch64::LDSETP: case AArch64::LDSETPA: case AArch64::LDSETPAL: case AArch64::LDSETPL: case AArch64::SWPP: case AArch64::SWPPA: case AArch64::SWPPAL: case AArch64::SWPPL: { switch (OpNum) { case 2: // op: Rt return 0; case 3: // op: Rt2 return 16; case 4: // op: Rn return 5; } break; } case AArch64::ZERO_MXI_2Z: case AArch64::ZERO_MXI_4Z: case AArch64::ZERO_MXI_VG2_2Z: case AArch64::ZERO_MXI_VG2_4Z: case AArch64::ZERO_MXI_VG2_Z: case AArch64::ZERO_MXI_VG4_2Z: case AArch64::ZERO_MXI_VG4_4Z: case AArch64::ZERO_MXI_VG4_Z: { switch (OpNum) { case 2: // op: Rv return 13; case 3: // op: imm return 0; } break; } case AArch64::ADD_VG2_M2Z_D: case AArch64::ADD_VG2_M2Z_S: case AArch64::BFADD_VG2_M2Z_H: case AArch64::BFSUB_VG2_M2Z_H: case AArch64::FADD_VG2_M2Z_D: case AArch64::FADD_VG2_M2Z_H: case AArch64::FADD_VG2_M2Z_S: case AArch64::FSUB_VG2_M2Z_D: case AArch64::FSUB_VG2_M2Z_H: case AArch64::FSUB_VG2_M2Z_S: case AArch64::SUB_VG2_M2Z_D: case AArch64::SUB_VG2_M2Z_S: { switch (OpNum) { case 2: // op: Rv return 13; case 3: // op: imm3 return 0; case 4: // op: Zm return 6; } break; } case AArch64::ADD_VG4_M4Z_D: case AArch64::ADD_VG4_M4Z_S: case AArch64::BFADD_VG4_M4Z_H: case AArch64::BFSUB_VG4_M4Z_H: case AArch64::FADD_VG4_M4Z_D: case AArch64::FADD_VG4_M4Z_H: case AArch64::FADD_VG4_M4Z_S: case AArch64::FSUB_VG4_M4Z_D: case AArch64::FSUB_VG4_M4Z_H: case AArch64::FSUB_VG4_M4Z_S: case AArch64::SUB_VG4_M4Z_D: case AArch64::SUB_VG4_M4Z_S: { switch (OpNum) { case 2: // op: Rv return 13; case 3: // op: imm3 return 0; case 4: // op: Zm return 7; } break; } case AArch64::INSERT_MXIPZ_H_Q: case AArch64::INSERT_MXIPZ_V_Q: { switch (OpNum) { case 2: // op: Rv return 13; case 4: // op: Pg return 10; case 5: // op: Zn return 5; case 0: // op: ZAd return 0; } break; } case AArch64::INSERT_MXIPZ_H_D: case AArch64::INSERT_MXIPZ_V_D: { switch (OpNum) { case 2: // op: Rv return 13; case 4: // op: Pg return 10; case 5: // op: Zn return 5; case 0: // op: ZAd return 1; case 3: // op: imm return 0; } break; } case AArch64::INSERT_MXIPZ_H_S: case AArch64::INSERT_MXIPZ_V_S: { switch (OpNum) { case 2: // op: Rv return 13; case 4: // op: Pg return 10; case 5: // op: Zn return 5; case 0: // op: ZAd return 2; case 3: // op: imm return 0; } break; } case AArch64::INSERT_MXIPZ_H_H: case AArch64::INSERT_MXIPZ_V_H: { switch (OpNum) { case 2: // op: Rv return 13; case 4: // op: Pg return 10; case 5: // op: Zn return 5; case 0: // op: ZAd return 3; case 3: // op: imm return 0; } break; } case AArch64::INSERT_MXIPZ_H_B: case AArch64::INSERT_MXIPZ_V_B: { switch (OpNum) { case 2: // op: Rv return 13; case 4: // op: Pg return 10; case 5: // op: Zn return 5; case 3: // op: imm return 0; } break; } case AArch64::BFMLAL_MZZ_HtoS: case AArch64::BFMLAL_VG2_M2ZZ_HtoS: case AArch64::BFMLAL_VG4_M4ZZ_HtoS: case AArch64::BFMLSL_MZZ_HtoS: case AArch64::BFMLSL_VG2_M2ZZ_HtoS: case AArch64::BFMLSL_VG4_M4ZZ_HtoS: case AArch64::FMLAL_MZZ_HtoS: case AArch64::FMLAL_VG2_M2ZZ_BtoH: case AArch64::FMLAL_VG2_M2ZZ_HtoS: case AArch64::FMLAL_VG2_MZZ_BtoH: case AArch64::FMLAL_VG4_M4ZZ_BtoH: case AArch64::FMLAL_VG4_M4ZZ_HtoS: case AArch64::FMLSL_MZZ_HtoS: case AArch64::FMLSL_VG2_M2ZZ_HtoS: case AArch64::FMLSL_VG4_M4ZZ_HtoS: case AArch64::SMLAL_MZZ_HtoS: case AArch64::SMLAL_VG2_M2ZZ_HtoS: case AArch64::SMLAL_VG4_M4ZZ_HtoS: case AArch64::SMLSL_MZZ_HtoS: case AArch64::SMLSL_VG2_M2ZZ_HtoS: case AArch64::SMLSL_VG4_M4ZZ_HtoS: case AArch64::UMLAL_MZZ_HtoS: case AArch64::UMLAL_VG2_M2ZZ_HtoS: case AArch64::UMLAL_VG4_M4ZZ_HtoS: case AArch64::UMLSL_MZZ_HtoS: case AArch64::UMLSL_VG2_M2ZZ_HtoS: case AArch64::UMLSL_VG4_M4ZZ_HtoS: { switch (OpNum) { case 2: // op: Rv return 13; case 5: // op: Zm return 16; case 4: // op: Zn return 5; case 3: // op: imm return 0; } break; } case AArch64::BFMLAL_VG2_M2Z2Z_HtoS: case AArch64::BFMLSL_VG2_M2Z2Z_HtoS: case AArch64::FMLAL_VG2_M2Z2Z_BtoH: case AArch64::FMLAL_VG2_M2Z2Z_HtoS: case AArch64::FMLSL_VG2_M2Z2Z_HtoS: case AArch64::SMLAL_VG2_M2Z2Z_HtoS: case AArch64::SMLSL_VG2_M2Z2Z_HtoS: case AArch64::UMLAL_VG2_M2Z2Z_HtoS: case AArch64::UMLSL_VG2_M2Z2Z_HtoS: { switch (OpNum) { case 2: // op: Rv return 13; case 5: // op: Zm return 17; case 4: // op: Zn return 6; case 3: // op: imm return 0; } break; } case AArch64::BFMLAL_VG4_M4Z4Z_HtoS: case AArch64::BFMLSL_VG4_M4Z4Z_HtoS: case AArch64::FMLAL_VG4_M4Z4Z_BtoH: case AArch64::FMLAL_VG4_M4Z4Z_HtoS: case AArch64::FMLSL_VG4_M4Z4Z_HtoS: case AArch64::SMLAL_VG4_M4Z4Z_HtoS: case AArch64::SMLSL_VG4_M4Z4Z_HtoS: case AArch64::UMLAL_VG4_M4Z4Z_HtoS: case AArch64::UMLSL_VG4_M4Z4Z_HtoS: { switch (OpNum) { case 2: // op: Rv return 13; case 5: // op: Zm return 18; case 4: // op: Zn return 7; case 3: // op: imm return 0; } break; } case AArch64::INSR_ZV_B: case AArch64::INSR_ZV_D: case AArch64::INSR_ZV_H: case AArch64::INSR_ZV_S: { switch (OpNum) { case 2: // op: Vm return 5; case 0: // op: Zdn return 0; } break; } case AArch64::LD1i8_POST: case AArch64::LD2i8_POST: case AArch64::LD3i8_POST: case AArch64::LD4i8_POST: { switch (OpNum) { case 2: // op: Vt return 0; case 4: // op: Rn return 5; case 3: // op: idx return 10; case 5: // op: Xm return 16; } break; } case AArch64::LD1i16_POST: case AArch64::LD2i16_POST: case AArch64::LD3i16_POST: case AArch64::LD4i16_POST: { switch (OpNum) { case 2: // op: Vt return 0; case 4: // op: Rn return 5; case 3: // op: idx return 11; case 5: // op: Xm return 16; } break; } case AArch64::LD1i32_POST: case AArch64::LD2i32_POST: case AArch64::LD3i32_POST: case AArch64::LD4i32_POST: { switch (OpNum) { case 2: // op: Vt return 0; case 4: // op: Rn return 5; case 3: // op: idx return 12; case 5: // op: Xm return 16; } break; } case AArch64::LD1i64_POST: case AArch64::LD2i64_POST: case AArch64::LD3i64_POST: case AArch64::LD4i64_POST: { switch (OpNum) { case 2: // op: Vt return 0; case 4: // op: Rn return 5; case 3: // op: idx return 30; case 5: // op: Xm return 16; } break; } case AArch64::ADD_VG2_2ZZ_B: case AArch64::ADD_VG2_2ZZ_D: case AArch64::ADD_VG2_2ZZ_H: case AArch64::ADD_VG2_2ZZ_S: case AArch64::BFMAXNM_VG2_2ZZ_H: case AArch64::BFMAX_VG2_2ZZ_H: case AArch64::BFMINNM_VG2_2ZZ_H: case AArch64::BFMIN_VG2_2ZZ_H: case AArch64::FMAXNM_VG2_2ZZ_D: case AArch64::FMAXNM_VG2_2ZZ_H: case AArch64::FMAXNM_VG2_2ZZ_S: case AArch64::FMAX_VG2_2ZZ_D: case AArch64::FMAX_VG2_2ZZ_H: case AArch64::FMAX_VG2_2ZZ_S: case AArch64::FMINNM_VG2_2ZZ_D: case AArch64::FMINNM_VG2_2ZZ_H: case AArch64::FMINNM_VG2_2ZZ_S: case AArch64::FMIN_VG2_2ZZ_D: case AArch64::FMIN_VG2_2ZZ_H: case AArch64::FMIN_VG2_2ZZ_S: case AArch64::FSCALE_2ZZ_D: case AArch64::FSCALE_2ZZ_H: case AArch64::FSCALE_2ZZ_S: case AArch64::SMAX_VG2_2ZZ_B: case AArch64::SMAX_VG2_2ZZ_D: case AArch64::SMAX_VG2_2ZZ_H: case AArch64::SMAX_VG2_2ZZ_S: case AArch64::SMIN_VG2_2ZZ_B: case AArch64::SMIN_VG2_2ZZ_D: case AArch64::SMIN_VG2_2ZZ_H: case AArch64::SMIN_VG2_2ZZ_S: case AArch64::SQDMULH_VG2_2ZZ_B: case AArch64::SQDMULH_VG2_2ZZ_D: case AArch64::SQDMULH_VG2_2ZZ_H: case AArch64::SQDMULH_VG2_2ZZ_S: case AArch64::SRSHL_VG2_2ZZ_B: case AArch64::SRSHL_VG2_2ZZ_D: case AArch64::SRSHL_VG2_2ZZ_H: case AArch64::SRSHL_VG2_2ZZ_S: case AArch64::UMAX_VG2_2ZZ_B: case AArch64::UMAX_VG2_2ZZ_D: case AArch64::UMAX_VG2_2ZZ_H: case AArch64::UMAX_VG2_2ZZ_S: case AArch64::UMIN_VG2_2ZZ_B: case AArch64::UMIN_VG2_2ZZ_D: case AArch64::UMIN_VG2_2ZZ_H: case AArch64::UMIN_VG2_2ZZ_S: case AArch64::URSHL_VG2_2ZZ_B: case AArch64::URSHL_VG2_2ZZ_D: case AArch64::URSHL_VG2_2ZZ_H: case AArch64::URSHL_VG2_2ZZ_S: { switch (OpNum) { case 2: // op: Zm return 16; case 0: // op: Zdn return 1; } break; } case AArch64::ADD_VG4_4ZZ_B: case AArch64::ADD_VG4_4ZZ_D: case AArch64::ADD_VG4_4ZZ_H: case AArch64::ADD_VG4_4ZZ_S: case AArch64::BFMAXNM_VG4_4ZZ_H: case AArch64::BFMAX_VG4_4ZZ_H: case AArch64::BFMINNM_VG4_4ZZ_H: case AArch64::BFMIN_VG4_4ZZ_H: case AArch64::FMAXNM_VG4_4ZZ_D: case AArch64::FMAXNM_VG4_4ZZ_H: case AArch64::FMAXNM_VG4_4ZZ_S: case AArch64::FMAX_VG4_4ZZ_D: case AArch64::FMAX_VG4_4ZZ_H: case AArch64::FMAX_VG4_4ZZ_S: case AArch64::FMINNM_VG4_4ZZ_D: case AArch64::FMINNM_VG4_4ZZ_H: case AArch64::FMINNM_VG4_4ZZ_S: case AArch64::FMIN_VG4_4ZZ_D: case AArch64::FMIN_VG4_4ZZ_H: case AArch64::FMIN_VG4_4ZZ_S: case AArch64::FSCALE_4ZZ_D: case AArch64::FSCALE_4ZZ_H: case AArch64::FSCALE_4ZZ_S: case AArch64::SMAX_VG4_4ZZ_B: case AArch64::SMAX_VG4_4ZZ_D: case AArch64::SMAX_VG4_4ZZ_H: case AArch64::SMAX_VG4_4ZZ_S: case AArch64::SMIN_VG4_4ZZ_B: case AArch64::SMIN_VG4_4ZZ_D: case AArch64::SMIN_VG4_4ZZ_H: case AArch64::SMIN_VG4_4ZZ_S: case AArch64::SQDMULH_VG4_4ZZ_B: case AArch64::SQDMULH_VG4_4ZZ_D: case AArch64::SQDMULH_VG4_4ZZ_H: case AArch64::SQDMULH_VG4_4ZZ_S: case AArch64::SRSHL_VG4_4ZZ_B: case AArch64::SRSHL_VG4_4ZZ_D: case AArch64::SRSHL_VG4_4ZZ_H: case AArch64::SRSHL_VG4_4ZZ_S: case AArch64::UMAX_VG4_4ZZ_B: case AArch64::UMAX_VG4_4ZZ_D: case AArch64::UMAX_VG4_4ZZ_H: case AArch64::UMAX_VG4_4ZZ_S: case AArch64::UMIN_VG4_4ZZ_B: case AArch64::UMIN_VG4_4ZZ_D: case AArch64::UMIN_VG4_4ZZ_H: case AArch64::UMIN_VG4_4ZZ_S: case AArch64::URSHL_VG4_4ZZ_B: case AArch64::URSHL_VG4_4ZZ_D: case AArch64::URSHL_VG4_4ZZ_H: case AArch64::URSHL_VG4_4ZZ_S: { switch (OpNum) { case 2: // op: Zm return 16; case 0: // op: Zdn return 2; } break; } case AArch64::BFMAXNM_VG2_2Z2Z_H: case AArch64::BFMAX_VG2_2Z2Z_H: case AArch64::BFMINNM_VG2_2Z2Z_H: case AArch64::BFMIN_VG2_2Z2Z_H: case AArch64::FAMAX_2Z2Z_D: case AArch64::FAMAX_2Z2Z_H: case AArch64::FAMAX_2Z2Z_S: case AArch64::FAMIN_2Z2Z_D: case AArch64::FAMIN_2Z2Z_H: case AArch64::FAMIN_2Z2Z_S: case AArch64::FMAXNM_VG2_2Z2Z_D: case AArch64::FMAXNM_VG2_2Z2Z_H: case AArch64::FMAXNM_VG2_2Z2Z_S: case AArch64::FMAX_VG2_2Z2Z_D: case AArch64::FMAX_VG2_2Z2Z_H: case AArch64::FMAX_VG2_2Z2Z_S: case AArch64::FMINNM_VG2_2Z2Z_D: case AArch64::FMINNM_VG2_2Z2Z_H: case AArch64::FMINNM_VG2_2Z2Z_S: case AArch64::FMIN_VG2_2Z2Z_D: case AArch64::FMIN_VG2_2Z2Z_H: case AArch64::FMIN_VG2_2Z2Z_S: case AArch64::FSCALE_2Z2Z_D: case AArch64::FSCALE_2Z2Z_H: case AArch64::FSCALE_2Z2Z_S: case AArch64::SMAX_VG2_2Z2Z_B: case AArch64::SMAX_VG2_2Z2Z_D: case AArch64::SMAX_VG2_2Z2Z_H: case AArch64::SMAX_VG2_2Z2Z_S: case AArch64::SMIN_VG2_2Z2Z_B: case AArch64::SMIN_VG2_2Z2Z_D: case AArch64::SMIN_VG2_2Z2Z_H: case AArch64::SMIN_VG2_2Z2Z_S: case AArch64::SQDMULH_VG2_2Z2Z_B: case AArch64::SQDMULH_VG2_2Z2Z_D: case AArch64::SQDMULH_VG2_2Z2Z_H: case AArch64::SQDMULH_VG2_2Z2Z_S: case AArch64::SRSHL_VG2_2Z2Z_B: case AArch64::SRSHL_VG2_2Z2Z_D: case AArch64::SRSHL_VG2_2Z2Z_H: case AArch64::SRSHL_VG2_2Z2Z_S: case AArch64::UMAX_VG2_2Z2Z_B: case AArch64::UMAX_VG2_2Z2Z_D: case AArch64::UMAX_VG2_2Z2Z_H: case AArch64::UMAX_VG2_2Z2Z_S: case AArch64::UMIN_VG2_2Z2Z_B: case AArch64::UMIN_VG2_2Z2Z_D: case AArch64::UMIN_VG2_2Z2Z_H: case AArch64::UMIN_VG2_2Z2Z_S: case AArch64::URSHL_VG2_2Z2Z_B: case AArch64::URSHL_VG2_2Z2Z_D: case AArch64::URSHL_VG2_2Z2Z_H: case AArch64::URSHL_VG2_2Z2Z_S: { switch (OpNum) { case 2: // op: Zm return 17; case 0: // op: Zdn return 1; } break; } case AArch64::BFMAXNM_VG4_4Z2Z_H: case AArch64::BFMAX_VG4_4Z2Z_H: case AArch64::BFMINNM_VG4_4Z2Z_H: case AArch64::BFMIN_VG4_4Z2Z_H: case AArch64::FAMAX_4Z4Z_D: case AArch64::FAMAX_4Z4Z_H: case AArch64::FAMAX_4Z4Z_S: case AArch64::FAMIN_4Z4Z_D: case AArch64::FAMIN_4Z4Z_H: case AArch64::FAMIN_4Z4Z_S: case AArch64::FMAXNM_VG4_4Z4Z_D: case AArch64::FMAXNM_VG4_4Z4Z_H: case AArch64::FMAXNM_VG4_4Z4Z_S: case AArch64::FMAX_VG4_4Z4Z_D: case AArch64::FMAX_VG4_4Z4Z_H: case AArch64::FMAX_VG4_4Z4Z_S: case AArch64::FMINNM_VG4_4Z4Z_D: case AArch64::FMINNM_VG4_4Z4Z_H: case AArch64::FMINNM_VG4_4Z4Z_S: case AArch64::FMIN_VG4_4Z4Z_D: case AArch64::FMIN_VG4_4Z4Z_H: case AArch64::FMIN_VG4_4Z4Z_S: case AArch64::FSCALE_4Z4Z_D: case AArch64::FSCALE_4Z4Z_H: case AArch64::FSCALE_4Z4Z_S: case AArch64::SMAX_VG4_4Z4Z_B: case AArch64::SMAX_VG4_4Z4Z_D: case AArch64::SMAX_VG4_4Z4Z_H: case AArch64::SMAX_VG4_4Z4Z_S: case AArch64::SMIN_VG4_4Z4Z_B: case AArch64::SMIN_VG4_4Z4Z_D: case AArch64::SMIN_VG4_4Z4Z_H: case AArch64::SMIN_VG4_4Z4Z_S: case AArch64::SQDMULH_VG4_4Z4Z_B: case AArch64::SQDMULH_VG4_4Z4Z_D: case AArch64::SQDMULH_VG4_4Z4Z_H: case AArch64::SQDMULH_VG4_4Z4Z_S: case AArch64::SRSHL_VG4_4Z4Z_B: case AArch64::SRSHL_VG4_4Z4Z_D: case AArch64::SRSHL_VG4_4Z4Z_H: case AArch64::SRSHL_VG4_4Z4Z_S: case AArch64::UMAX_VG4_4Z4Z_B: case AArch64::UMAX_VG4_4Z4Z_D: case AArch64::UMAX_VG4_4Z4Z_H: case AArch64::UMAX_VG4_4Z4Z_S: case AArch64::UMIN_VG4_4Z4Z_B: case AArch64::UMIN_VG4_4Z4Z_D: case AArch64::UMIN_VG4_4Z4Z_H: case AArch64::UMIN_VG4_4Z4Z_S: case AArch64::URSHL_VG4_4Z4Z_B: case AArch64::URSHL_VG4_4Z4Z_D: case AArch64::URSHL_VG4_4Z4Z_H: case AArch64::URSHL_VG4_4Z4Z_S: { switch (OpNum) { case 2: // op: Zm return 18; case 0: // op: Zdn return 2; } break; } case AArch64::FADDV_VPZ_D: case AArch64::FADDV_VPZ_H: case AArch64::FADDV_VPZ_S: case AArch64::FMAXNMV_VPZ_D: case AArch64::FMAXNMV_VPZ_H: case AArch64::FMAXNMV_VPZ_S: case AArch64::FMAXV_VPZ_D: case AArch64::FMAXV_VPZ_H: case AArch64::FMAXV_VPZ_S: case AArch64::FMINNMV_VPZ_D: case AArch64::FMINNMV_VPZ_H: case AArch64::FMINNMV_VPZ_S: case AArch64::FMINV_VPZ_D: case AArch64::FMINV_VPZ_H: case AArch64::FMINV_VPZ_S: { switch (OpNum) { case 2: // op: Zn return 5; case 0: // op: Vd return 0; case 1: // op: Pg return 10; } break; } case AArch64::LUTI2_ZTZI_B: case AArch64::LUTI2_ZTZI_H: case AArch64::LUTI2_ZTZI_S: case AArch64::LUTI4_ZTZI_B: case AArch64::LUTI4_ZTZI_H: case AArch64::LUTI4_ZTZI_S: { switch (OpNum) { case 2: // op: Zn return 5; case 0: // op: Zd return 0; case 3: // op: i return 14; } break; } case AArch64::LUTI2_S_2ZTZI_B: case AArch64::LUTI2_S_2ZTZI_H: case AArch64::LUTI4_S_2ZTZI_B: case AArch64::LUTI4_S_2ZTZI_H: { switch (OpNum) { case 2: // op: Zn return 5; case 0: // op: Zd return 0; case 3: // op: i return 15; } break; } case AArch64::LUTI2_S_4ZTZI_B: case AArch64::LUTI2_S_4ZTZI_H: case AArch64::LUTI4_S_4ZTZI_H: { switch (OpNum) { case 2: // op: Zn return 5; case 0: // op: Zd return 0; case 3: // op: i return 16; } break; } case AArch64::LUTI2_2ZTZI_B: case AArch64::LUTI2_2ZTZI_H: case AArch64::LUTI2_2ZTZI_S: case AArch64::LUTI4_2ZTZI_B: case AArch64::LUTI4_2ZTZI_H: case AArch64::LUTI4_2ZTZI_S: { switch (OpNum) { case 2: // op: Zn return 5; case 0: // op: Zd return 1; case 3: // op: i return 15; } break; } case AArch64::LUTI2_4ZTZI_B: case AArch64::LUTI2_4ZTZI_H: case AArch64::LUTI2_4ZTZI_S: case AArch64::LUTI4_4ZTZI_H: case AArch64::LUTI4_4ZTZI_S: { switch (OpNum) { case 2: // op: Zn return 5; case 0: // op: Zd return 2; case 3: // op: i return 16; } break; } case AArch64::LUTI4_S_4ZZT2Z: { switch (OpNum) { case 2: // op: Zn return 6; case 0: // op: Zd return 0; } break; } case AArch64::LUTI4_4ZZT2Z: { switch (OpNum) { case 2: // op: Zn return 6; case 0: // op: Zd return 2; } break; } case AArch64::MOVT: { switch (OpNum) { case 2: // op: Zt return 0; case 1: // op: off2 return 12; } break; } case AArch64::MOVT_XTI: { switch (OpNum) { case 2: // op: imm3 return 12; case 0: // op: Rt return 0; } break; } case AArch64::SQRSHRU_VG2_Z2ZI_H: case AArch64::SQRSHR_VG2_Z2ZI_H: case AArch64::UQRSHR_VG2_Z2ZI_H: { switch (OpNum) { case 2: // op: imm4 return 16; case 1: // op: Zn return 6; case 0: // op: Zd return 0; } break; } case AArch64::LDRAAindexed: case AArch64::LDRABindexed: { switch (OpNum) { case 2: // op: offset return 12; case 1: // op: Rn return 5; case 0: // op: Rt return 0; } break; } case AArch64::ADDHA_MPPZ_D: case AArch64::ADDHA_MPPZ_S: case AArch64::ADDVA_MPPZ_D: case AArch64::ADDVA_MPPZ_S: { switch (OpNum) { case 3: // op: Pm return 13; case 2: // op: Pn return 10; case 4: // op: Zn return 5; case 0: // op: ZAda return 0; } break; } case AArch64::CPYE: case AArch64::CPYEN: case AArch64::CPYERN: case AArch64::CPYERT: case AArch64::CPYERTN: case AArch64::CPYERTRN: case AArch64::CPYERTWN: case AArch64::CPYET: case AArch64::CPYETN: case AArch64::CPYETRN: case AArch64::CPYETWN: case AArch64::CPYEWN: case AArch64::CPYEWT: case AArch64::CPYEWTN: case AArch64::CPYEWTRN: case AArch64::CPYEWTWN: case AArch64::CPYFE: case AArch64::CPYFEN: case AArch64::CPYFERN: case AArch64::CPYFERT: case AArch64::CPYFERTN: case AArch64::CPYFERTRN: case AArch64::CPYFERTWN: case AArch64::CPYFET: case AArch64::CPYFETN: case AArch64::CPYFETRN: case AArch64::CPYFETWN: case AArch64::CPYFEWN: case AArch64::CPYFEWT: case AArch64::CPYFEWTN: case AArch64::CPYFEWTRN: case AArch64::CPYFEWTWN: case AArch64::CPYFM: case AArch64::CPYFMN: case AArch64::CPYFMRN: case AArch64::CPYFMRT: case AArch64::CPYFMRTN: case AArch64::CPYFMRTRN: case AArch64::CPYFMRTWN: case AArch64::CPYFMT: case AArch64::CPYFMTN: case AArch64::CPYFMTRN: case AArch64::CPYFMTWN: case AArch64::CPYFMWN: case AArch64::CPYFMWT: case AArch64::CPYFMWTN: case AArch64::CPYFMWTRN: case AArch64::CPYFMWTWN: case AArch64::CPYFP: case AArch64::CPYFPN: case AArch64::CPYFPRN: case AArch64::CPYFPRT: case AArch64::CPYFPRTN: case AArch64::CPYFPRTRN: case AArch64::CPYFPRTWN: case AArch64::CPYFPT: case AArch64::CPYFPTN: case AArch64::CPYFPTRN: case AArch64::CPYFPTWN: case AArch64::CPYFPWN: case AArch64::CPYFPWT: case AArch64::CPYFPWTN: case AArch64::CPYFPWTRN: case AArch64::CPYFPWTWN: case AArch64::CPYM: case AArch64::CPYMN: case AArch64::CPYMRN: case AArch64::CPYMRT: case AArch64::CPYMRTN: case AArch64::CPYMRTRN: case AArch64::CPYMRTWN: case AArch64::CPYMT: case AArch64::CPYMTN: case AArch64::CPYMTRN: case AArch64::CPYMTWN: case AArch64::CPYMWN: case AArch64::CPYMWT: case AArch64::CPYMWTN: case AArch64::CPYMWTRN: case AArch64::CPYMWTWN: case AArch64::CPYP: case AArch64::CPYPN: case AArch64::CPYPRN: case AArch64::CPYPRT: case AArch64::CPYPRTN: case AArch64::CPYPRTRN: case AArch64::CPYPRTWN: case AArch64::CPYPT: case AArch64::CPYPTN: case AArch64::CPYPTRN: case AArch64::CPYPTWN: case AArch64::CPYPWN: case AArch64::CPYPWT: case AArch64::CPYPWTN: case AArch64::CPYPWTRN: case AArch64::CPYPWTWN: { switch (OpNum) { case 3: // op: Rd return 0; case 4: // op: Rs return 16; case 5: // op: Rn return 5; } break; } case AArch64::LD1B_2Z_STRIDED: case AArch64::LD1B_4Z_STRIDED: case AArch64::LD1D_2Z_STRIDED: case AArch64::LD1D_4Z_STRIDED: case AArch64::LD1H_2Z_STRIDED: case AArch64::LD1H_4Z_STRIDED: case AArch64::LD1W_2Z_STRIDED: case AArch64::LD1W_4Z_STRIDED: case AArch64::LDNT1B_2Z_STRIDED: case AArch64::LDNT1B_4Z_STRIDED: case AArch64::LDNT1D_2Z_STRIDED: case AArch64::LDNT1D_4Z_STRIDED: case AArch64::LDNT1H_2Z_STRIDED: case AArch64::LDNT1H_4Z_STRIDED: case AArch64::LDNT1W_2Z_STRIDED: case AArch64::LDNT1W_4Z_STRIDED: case AArch64::ST1B_2Z_STRIDED: case AArch64::ST1B_4Z_STRIDED: case AArch64::ST1D_2Z_STRIDED: case AArch64::ST1D_4Z_STRIDED: case AArch64::ST1H_2Z_STRIDED: case AArch64::ST1H_4Z_STRIDED: case AArch64::ST1W_2Z_STRIDED: case AArch64::ST1W_4Z_STRIDED: case AArch64::STNT1B_2Z_STRIDED: case AArch64::STNT1B_4Z_STRIDED: case AArch64::STNT1D_2Z_STRIDED: case AArch64::STNT1D_4Z_STRIDED: case AArch64::STNT1H_2Z_STRIDED: case AArch64::STNT1H_4Z_STRIDED: case AArch64::STNT1W_2Z_STRIDED: case AArch64::STNT1W_4Z_STRIDED: { switch (OpNum) { case 3: // op: Rm return 16; case 1: // op: PNg return 10; case 2: // op: Rn return 5; case 0: // op: Zt return 0; } break; } case AArch64::PRFB_PRR: case AArch64::PRFD_PRR: case AArch64::PRFH_PRR: case AArch64::PRFW_PRR: { switch (OpNum) { case 3: // op: Rm return 16; case 2: // op: Rn return 5; case 1: // op: Pg return 10; case 0: // op: prfop return 0; } break; } case AArch64::MOVAZ_ZMI_H_Q: case AArch64::MOVAZ_ZMI_V_Q: { switch (OpNum) { case 3: // op: Rs return 13; case 0: // op: Zd return 0; case 1: // op: ZAn return 5; } break; } case AArch64::MOVAZ_ZMI_H_D: case AArch64::MOVAZ_ZMI_V_D: { switch (OpNum) { case 3: // op: Rs return 13; case 0: // op: Zd return 0; case 1: // op: ZAn return 6; case 4: // op: imm return 5; } break; } case AArch64::MOVAZ_ZMI_H_S: case AArch64::MOVAZ_ZMI_V_S: { switch (OpNum) { case 3: // op: Rs return 13; case 0: // op: Zd return 0; case 1: // op: ZAn return 7; case 4: // op: imm return 5; } break; } case AArch64::MOVAZ_ZMI_H_H: case AArch64::MOVAZ_ZMI_V_H: { switch (OpNum) { case 3: // op: Rs return 13; case 0: // op: Zd return 0; case 1: // op: ZAn return 8; case 4: // op: imm return 5; } break; } case AArch64::MOVAZ_ZMI_H_B: case AArch64::MOVAZ_ZMI_V_B: { switch (OpNum) { case 3: // op: Rs return 13; case 0: // op: Zd return 0; case 4: // op: imm return 5; } break; } case AArch64::MOVAZ_VG2_2ZMXI: { switch (OpNum) { case 3: // op: Rs return 13; case 4: // op: imm return 5; case 0: // op: Zd return 1; } break; } case AArch64::MOVAZ_VG4_4ZMXI: { switch (OpNum) { case 3: // op: Rs return 13; case 4: // op: imm return 5; case 0: // op: Zd return 2; } break; } case AArch64::RCWCLRP: case AArch64::RCWCLRPA: case AArch64::RCWCLRPAL: case AArch64::RCWCLRPL: case AArch64::RCWCLRSP: case AArch64::RCWCLRSPA: case AArch64::RCWCLRSPAL: case AArch64::RCWCLRSPL: case AArch64::RCWSETP: case AArch64::RCWSETPA: case AArch64::RCWSETPAL: case AArch64::RCWSETPL: case AArch64::RCWSETSP: case AArch64::RCWSETSPA: case AArch64::RCWSETSPAL: case AArch64::RCWSETSPL: case AArch64::RCWSWPP: case AArch64::RCWSWPPA: case AArch64::RCWSWPPAL: case AArch64::RCWSWPPL: case AArch64::RCWSWPSP: case AArch64::RCWSWPSPA: case AArch64::RCWSWPSPAL: case AArch64::RCWSWPSPL: { switch (OpNum) { case 3: // op: Rt2 return 16; case 4: // op: Rn return 5; case 2: // op: Rt return 0; } break; } case AArch64::PSEL_PPPRI_B: { switch (OpNum) { case 3: // op: Rv return 16; case 1: // op: Pn return 10; case 2: // op: Pm return 5; case 0: // op: Pd return 0; case 4: // op: imm return 19; } break; } case AArch64::PSEL_PPPRI_H: { switch (OpNum) { case 3: // op: Rv return 16; case 1: // op: Pn return 10; case 2: // op: Pm return 5; case 0: // op: Pd return 0; case 4: // op: imm return 20; } break; } case AArch64::PSEL_PPPRI_S: { switch (OpNum) { case 3: // op: Rv return 16; case 1: // op: Pn return 10; case 2: // op: Pm return 5; case 0: // op: Pd return 0; case 4: // op: imm return 22; } break; } case AArch64::PSEL_PPPRI_D: { switch (OpNum) { case 3: // op: Rv return 16; case 1: // op: Pn return 10; case 2: // op: Pm return 5; case 0: // op: Pd return 0; case 4: // op: imm return 23; } break; } case AArch64::BFMMLA_ZZZ: { switch (OpNum) { case 3: // op: Zm return 16; case 0: // op: Zda return 0; case 2: // op: Zn return 5; } break; } case AArch64::BFCLAMP_ZZZ: case AArch64::FCLAMP_ZZZ_D: case AArch64::FCLAMP_ZZZ_H: case AArch64::FCLAMP_ZZZ_S: case AArch64::SCLAMP_ZZZ_B: case AArch64::SCLAMP_ZZZ_D: case AArch64::SCLAMP_ZZZ_H: case AArch64::SCLAMP_ZZZ_S: case AArch64::UCLAMP_ZZZ_B: case AArch64::UCLAMP_ZZZ_D: case AArch64::UCLAMP_ZZZ_H: case AArch64::UCLAMP_ZZZ_S: { switch (OpNum) { case 3: // op: Zm return 16; case 2: // op: Zn return 5; case 0: // op: Zd return 0; } break; } case AArch64::BFCLAMP_VG2_2ZZZ_H: case AArch64::FCLAMP_VG2_2Z2Z_D: case AArch64::FCLAMP_VG2_2Z2Z_H: case AArch64::FCLAMP_VG2_2Z2Z_S: case AArch64::SCLAMP_VG2_2Z2Z_B: case AArch64::SCLAMP_VG2_2Z2Z_D: case AArch64::SCLAMP_VG2_2Z2Z_H: case AArch64::SCLAMP_VG2_2Z2Z_S: case AArch64::UCLAMP_VG2_2Z2Z_B: case AArch64::UCLAMP_VG2_2Z2Z_D: case AArch64::UCLAMP_VG2_2Z2Z_H: case AArch64::UCLAMP_VG2_2Z2Z_S: { switch (OpNum) { case 3: // op: Zm return 16; case 2: // op: Zn return 5; case 0: // op: Zd return 1; } break; } case AArch64::BFCLAMP_VG4_4ZZZ_H: case AArch64::FCLAMP_VG4_4Z4Z_D: case AArch64::FCLAMP_VG4_4Z4Z_H: case AArch64::FCLAMP_VG4_4Z4Z_S: case AArch64::SCLAMP_VG4_4Z4Z_B: case AArch64::SCLAMP_VG4_4Z4Z_D: case AArch64::SCLAMP_VG4_4Z4Z_H: case AArch64::SCLAMP_VG4_4Z4Z_S: case AArch64::UCLAMP_VG4_4Z4Z_B: case AArch64::UCLAMP_VG4_4Z4Z_D: case AArch64::UCLAMP_VG4_4Z4Z_H: case AArch64::UCLAMP_VG4_4Z4Z_S: { switch (OpNum) { case 3: // op: Zm return 16; case 2: // op: Zn return 5; case 0: // op: Zd return 2; } break; } case AArch64::LD1B_2Z_STRIDED_IMM: case AArch64::LD1B_4Z_STRIDED_IMM: case AArch64::LD1D_2Z_STRIDED_IMM: case AArch64::LD1D_4Z_STRIDED_IMM: case AArch64::LD1H_2Z_STRIDED_IMM: case AArch64::LD1H_4Z_STRIDED_IMM: case AArch64::LD1W_2Z_STRIDED_IMM: case AArch64::LD1W_4Z_STRIDED_IMM: case AArch64::LDNT1B_2Z_STRIDED_IMM: case AArch64::LDNT1B_4Z_STRIDED_IMM: case AArch64::LDNT1D_2Z_STRIDED_IMM: case AArch64::LDNT1D_4Z_STRIDED_IMM: case AArch64::LDNT1H_2Z_STRIDED_IMM: case AArch64::LDNT1H_4Z_STRIDED_IMM: case AArch64::LDNT1W_2Z_STRIDED_IMM: case AArch64::LDNT1W_4Z_STRIDED_IMM: case AArch64::ST1B_2Z_STRIDED_IMM: case AArch64::ST1B_4Z_STRIDED_IMM: case AArch64::ST1D_2Z_STRIDED_IMM: case AArch64::ST1D_4Z_STRIDED_IMM: case AArch64::ST1H_2Z_STRIDED_IMM: case AArch64::ST1H_4Z_STRIDED_IMM: case AArch64::ST1W_2Z_STRIDED_IMM: case AArch64::ST1W_4Z_STRIDED_IMM: case AArch64::STNT1B_2Z_STRIDED_IMM: case AArch64::STNT1B_4Z_STRIDED_IMM: case AArch64::STNT1D_2Z_STRIDED_IMM: case AArch64::STNT1D_4Z_STRIDED_IMM: case AArch64::STNT1H_2Z_STRIDED_IMM: case AArch64::STNT1H_4Z_STRIDED_IMM: case AArch64::STNT1W_2Z_STRIDED_IMM: case AArch64::STNT1W_4Z_STRIDED_IMM: { switch (OpNum) { case 3: // op: imm4 return 16; case 1: // op: PNg return 10; case 2: // op: Rn return 5; case 0: // op: Zt return 0; } break; } case AArch64::LDRAAwriteback: case AArch64::LDRABwriteback: { switch (OpNum) { case 3: // op: offset return 12; case 2: // op: Rn return 5; case 1: // op: Rt return 0; } break; } case AArch64::SYSPxt: case AArch64::SYSxt: { switch (OpNum) { case 4: // op: Rt return 0; case 0: // op: op1 return 16; case 1: // op: Cn return 12; case 2: // op: Cm return 8; case 3: // op: op2 return 5; } break; } case AArch64::EXTRACT_ZPMXI_H_Q: case AArch64::EXTRACT_ZPMXI_V_Q: { switch (OpNum) { case 4: // op: Rv return 13; case 2: // op: Pg return 10; case 0: // op: Zd return 0; case 3: // op: ZAn return 5; } break; } case AArch64::EXTRACT_ZPMXI_H_D: case AArch64::EXTRACT_ZPMXI_V_D: { switch (OpNum) { case 4: // op: Rv return 13; case 2: // op: Pg return 10; case 0: // op: Zd return 0; case 3: // op: ZAn return 6; case 5: // op: imm return 5; } break; } case AArch64::EXTRACT_ZPMXI_H_S: case AArch64::EXTRACT_ZPMXI_V_S: { switch (OpNum) { case 4: // op: Rv return 13; case 2: // op: Pg return 10; case 0: // op: Zd return 0; case 3: // op: ZAn return 7; case 5: // op: imm return 5; } break; } case AArch64::EXTRACT_ZPMXI_H_H: case AArch64::EXTRACT_ZPMXI_V_H: { switch (OpNum) { case 4: // op: Rv return 13; case 2: // op: Pg return 10; case 0: // op: Zd return 0; case 3: // op: ZAn return 8; case 5: // op: imm return 5; } break; } case AArch64::EXTRACT_ZPMXI_H_B: case AArch64::EXTRACT_ZPMXI_V_B: { switch (OpNum) { case 4: // op: Rv return 13; case 2: // op: Pg return 10; case 0: // op: Zd return 0; case 5: // op: imm return 5; } break; } case AArch64::LD1_MXIPXX_H_Q: case AArch64::LD1_MXIPXX_V_Q: case AArch64::ST1_MXIPXX_H_Q: case AArch64::ST1_MXIPXX_V_Q: { switch (OpNum) { case 5: // op: Rm return 16; case 1: // op: Rv return 13; case 3: // op: Pg return 10; case 4: // op: Rn return 5; case 0: // op: ZAt return 0; } break; } case AArch64::LD1_MXIPXX_H_D: case AArch64::LD1_MXIPXX_V_D: case AArch64::ST1_MXIPXX_H_D: case AArch64::ST1_MXIPXX_V_D: { switch (OpNum) { case 5: // op: Rm return 16; case 1: // op: Rv return 13; case 3: // op: Pg return 10; case 4: // op: Rn return 5; case 0: // op: ZAt return 1; case 2: // op: imm return 0; } break; } case AArch64::LD1_MXIPXX_H_S: case AArch64::LD1_MXIPXX_V_S: case AArch64::ST1_MXIPXX_H_S: case AArch64::ST1_MXIPXX_V_S: { switch (OpNum) { case 5: // op: Rm return 16; case 1: // op: Rv return 13; case 3: // op: Pg return 10; case 4: // op: Rn return 5; case 0: // op: ZAt return 2; case 2: // op: imm return 0; } break; } case AArch64::LD1_MXIPXX_H_H: case AArch64::LD1_MXIPXX_V_H: case AArch64::ST1_MXIPXX_H_H: case AArch64::ST1_MXIPXX_V_H: { switch (OpNum) { case 5: // op: Rm return 16; case 1: // op: Rv return 13; case 3: // op: Pg return 10; case 4: // op: Rn return 5; case 0: // op: ZAt return 3; case 2: // op: imm return 0; } break; } case AArch64::LD1_MXIPXX_H_B: case AArch64::LD1_MXIPXX_V_B: case AArch64::ST1_MXIPXX_H_B: case AArch64::ST1_MXIPXX_V_B: { switch (OpNum) { case 5: // op: Rm return 16; case 1: // op: Rv return 13; case 3: // op: Pg return 10; case 4: // op: Rn return 5; case 2: // op: imm return 0; } break; } case AArch64::FMLALL_MZZ_BtoS: case AArch64::FMLALL_VG2_M2ZZ_BtoS: case AArch64::FMLALL_VG4_M4ZZ_BtoS: case AArch64::SMLALL_MZZ_BtoS: case AArch64::SMLALL_MZZ_HtoD: case AArch64::SMLALL_VG2_M2ZZ_BtoS: case AArch64::SMLALL_VG2_M2ZZ_HtoD: case AArch64::SMLALL_VG4_M4ZZ_BtoS: case AArch64::SMLALL_VG4_M4ZZ_HtoD: case AArch64::SMLSLL_MZZ_BtoS: case AArch64::SMLSLL_MZZ_HtoD: case AArch64::SMLSLL_VG2_M2ZZ_BtoS: case AArch64::SMLSLL_VG2_M2ZZ_HtoD: case AArch64::SMLSLL_VG4_M4ZZ_BtoS: case AArch64::SMLSLL_VG4_M4ZZ_HtoD: case AArch64::SUMLALL_VG2_M2ZZ_BtoS: case AArch64::SUMLALL_VG4_M4ZZ_BtoS: case AArch64::UMLALL_MZZ_BtoS: case AArch64::UMLALL_MZZ_HtoD: case AArch64::UMLALL_VG2_M2ZZ_BtoS: case AArch64::UMLALL_VG2_M2ZZ_HtoD: case AArch64::UMLALL_VG4_M4ZZ_BtoS: case AArch64::UMLALL_VG4_M4ZZ_HtoD: case AArch64::UMLSLL_MZZ_BtoS: case AArch64::UMLSLL_MZZ_HtoD: case AArch64::UMLSLL_VG2_M2ZZ_BtoS: case AArch64::UMLSLL_VG2_M2ZZ_HtoD: case AArch64::UMLSLL_VG4_M4ZZ_BtoS: case AArch64::UMLSLL_VG4_M4ZZ_HtoD: case AArch64::USMLALL_MZZ_BtoS: case AArch64::USMLALL_VG2_M2ZZ_BtoS: case AArch64::USMLALL_VG4_M4ZZ_BtoS: { switch (OpNum) { case 5: // op: Zm return 16; case 2: // op: Rv return 13; case 4: // op: Zn return 5; case 3: // op: imm return 0; } break; } case AArch64::BFDOT_VG2_M2ZZI_HtoS: case AArch64::BFVDOT_VG2_M2ZZI_HtoS: case AArch64::FDOT_VG2_M2ZZI_BtoS: case AArch64::FDOT_VG2_M2ZZI_HtoS: case AArch64::FMLA_VG2_M2ZZI_S: case AArch64::FMLS_VG2_M2ZZI_S: case AArch64::FVDOT_VG2_M2ZZI_HtoS: case AArch64::SDOT_VG2_M2ZZI_BToS: case AArch64::SDOT_VG2_M2ZZI_HToS: case AArch64::SUDOT_VG2_M2ZZI_BToS: case AArch64::SVDOT_VG2_M2ZZI_HtoS: case AArch64::UDOT_VG2_M2ZZI_BToS: case AArch64::UDOT_VG2_M2ZZI_HToS: case AArch64::USDOT_VG2_M2ZZI_BToS: case AArch64::UVDOT_VG2_M2ZZI_HtoS: { switch (OpNum) { case 5: // op: Zm return 16; case 2: // op: Rv return 13; case 4: // op: Zn return 6; case 3: // op: imm3 return 0; case 6: // op: i return 10; } break; } case AArch64::BFMLA_VG2_M2ZZI: case AArch64::BFMLS_VG2_M2ZZI: case AArch64::FDOT_VG2_M2ZZI_BtoH: case AArch64::FMLA_VG2_M2ZZI_H: case AArch64::FMLS_VG2_M2ZZI_H: case AArch64::FVDOTB_VG4_M2ZZI_BtoS: case AArch64::FVDOTT_VG4_M2ZZI_BtoS: case AArch64::FVDOT_VG2_M2ZZI_BtoH: { switch (OpNum) { case 5: // op: Zm return 16; case 2: // op: Rv return 13; case 4: // op: Zn return 6; case 3: // op: imm3 return 0; case 6: // op: i return 3; } break; } case AArch64::BFDOT_VG4_M4ZZI_HtoS: case AArch64::FDOT_VG4_M4ZZI_BtoS: case AArch64::FDOT_VG4_M4ZZI_HtoS: case AArch64::FMLA_VG4_M4ZZI_S: case AArch64::FMLS_VG4_M4ZZI_S: case AArch64::SDOT_VG4_M4ZZI_BToS: case AArch64::SDOT_VG4_M4ZZI_HToS: case AArch64::SUDOT_VG4_M4ZZI_BToS: case AArch64::SUVDOT_VG4_M4ZZI_BToS: case AArch64::SVDOT_VG4_M4ZZI_BtoS: case AArch64::UDOT_VG4_M4ZZI_BtoS: case AArch64::UDOT_VG4_M4ZZI_HToS: case AArch64::USDOT_VG4_M4ZZI_BToS: case AArch64::USVDOT_VG4_M4ZZI_BToS: case AArch64::UVDOT_VG4_M4ZZI_BtoS: { switch (OpNum) { case 5: // op: Zm return 16; case 2: // op: Rv return 13; case 4: // op: Zn return 7; case 3: // op: imm3 return 0; case 6: // op: i return 10; } break; } case AArch64::BFMLA_VG4_M4ZZI: case AArch64::BFMLS_VG4_M4ZZI: case AArch64::FDOT_VG4_M4ZZI_BtoH: case AArch64::FMLA_VG4_M4ZZI_H: case AArch64::FMLS_VG4_M4ZZI_H: { switch (OpNum) { case 5: // op: Zm return 16; case 2: // op: Rv return 13; case 4: // op: Zn return 7; case 3: // op: imm3 return 0; case 6: // op: i return 3; } break; } case AArch64::FMLALL_MZZI_BtoS: case AArch64::SMLALL_MZZI_BtoS: case AArch64::SMLALL_MZZI_HtoD: case AArch64::SMLSLL_MZZI_BtoS: case AArch64::SMLSLL_MZZI_HtoD: case AArch64::SUMLALL_MZZI_BtoS: case AArch64::UMLALL_MZZI_BtoS: case AArch64::UMLALL_MZZI_HtoD: case AArch64::UMLSLL_MZZI_BtoS: case AArch64::UMLSLL_MZZI_HtoD: case AArch64::USMLALL_MZZI_BtoS: { switch (OpNum) { case 5: // op: Zm return 16; case 2: // op: Rv return 13; case 6: // op: i return 10; case 4: // op: Zn return 5; case 3: // op: imm2 return 0; } break; } case AArch64::FMLALL_VG2_M2ZZI_BtoS: case AArch64::SMLALL_VG2_M2ZZI_BtoS: case AArch64::SMLALL_VG2_M2ZZI_HtoD: case AArch64::SMLSLL_VG2_M2ZZI_BtoS: case AArch64::SMLSLL_VG2_M2ZZI_HtoD: case AArch64::SUMLALL_VG2_M2ZZI_BtoS: case AArch64::UMLALL_VG2_M2ZZI_BtoS: case AArch64::UMLALL_VG2_M2ZZI_HtoD: case AArch64::UMLSLL_VG2_M2ZZI_BtoS: case AArch64::UMLSLL_VG2_M2ZZI_HtoD: case AArch64::USMLALL_VG2_M2ZZI_BtoS: { switch (OpNum) { case 5: // op: Zm return 16; case 2: // op: Rv return 13; case 6: // op: i return 1; case 3: // op: imm return 0; case 4: // op: Zn return 6; } break; } case AArch64::FMLALL_VG4_M4ZZI_BtoS: case AArch64::SMLALL_VG4_M4ZZI_BtoS: case AArch64::SMLALL_VG4_M4ZZI_HtoD: case AArch64::SMLSLL_VG4_M4ZZI_BtoS: case AArch64::SMLSLL_VG4_M4ZZI_HtoD: case AArch64::SUMLALL_VG4_M4ZZI_BtoS: case AArch64::UMLALL_VG4_M4ZZI_BtoS: case AArch64::UMLALL_VG4_M4ZZI_HtoD: case AArch64::UMLSLL_VG4_M4ZZI_BtoS: case AArch64::UMLSLL_VG4_M4ZZI_HtoD: case AArch64::USMLALL_VG4_M4ZZI_BtoS: { switch (OpNum) { case 5: // op: Zm return 16; case 2: // op: Rv return 13; case 6: // op: i return 1; case 3: // op: imm return 0; case 4: // op: Zn return 7; } break; } case AArch64::FMLAL_VG2_M2ZZI_BtoH: { switch (OpNum) { case 5: // op: Zm return 16; case 2: // op: Rv return 13; case 6: // op: i return 2; case 3: // op: imm2 return 0; case 4: // op: Zn return 6; } break; } case AArch64::FMLAL_VG4_M4ZZI_BtoH: { switch (OpNum) { case 5: // op: Zm return 16; case 2: // op: Rv return 13; case 6: // op: i return 2; case 3: // op: imm2 return 0; case 4: // op: Zn return 7; } break; } case AArch64::FMLAL_MZZI_BtoH: { switch (OpNum) { case 5: // op: Zm return 16; case 2: // op: Rv return 13; case 6: // op: i return 3; case 4: // op: Zn return 5; case 3: // op: imm3 return 0; } break; } case AArch64::FMLA_VG2_M2ZZI_D: case AArch64::FMLS_VG2_M2ZZI_D: case AArch64::SDOT_VG2_M2ZZI_HtoD: case AArch64::UDOT_VG2_M2ZZI_HtoD: { switch (OpNum) { case 5: // op: Zm return 16; case 2: // op: Rv return 13; case 6: // op: i1 return 10; case 4: // op: Zn return 6; case 3: // op: imm3 return 0; } break; } case AArch64::FMLA_VG4_M4ZZI_D: case AArch64::FMLS_VG4_M4ZZI_D: case AArch64::SDOT_VG4_M4ZZI_HtoD: case AArch64::SVDOT_VG4_M4ZZI_HtoD: case AArch64::UDOT_VG4_M4ZZI_HtoD: case AArch64::UVDOT_VG4_M4ZZI_HtoD: { switch (OpNum) { case 5: // op: Zm return 16; case 2: // op: Rv return 13; case 6: // op: i1 return 10; case 4: // op: Zn return 7; case 3: // op: imm3 return 0; } break; } case AArch64::BFMLAL_MZZI_HtoS: case AArch64::BFMLSL_MZZI_HtoS: case AArch64::FMLAL_MZZI_HtoS: case AArch64::FMLSL_MZZI_HtoS: case AArch64::SMLAL_MZZI_HtoS: case AArch64::SMLSL_MZZI_HtoS: case AArch64::UMLAL_MZZI_HtoS: case AArch64::UMLSL_MZZI_HtoS: { switch (OpNum) { case 5: // op: Zm return 16; case 2: // op: Rv return 13; case 6: // op: i3 return 10; case 4: // op: Zn return 5; case 3: // op: imm return 0; } break; } case AArch64::BFMLAL_VG2_M2ZZI_HtoS: case AArch64::BFMLSL_VG2_M2ZZI_HtoS: case AArch64::FMLAL_VG2_M2ZZI_HtoS: case AArch64::FMLSL_VG2_M2ZZI_HtoS: case AArch64::SMLAL_VG2_M2ZZI_S: case AArch64::SMLSL_VG2_M2ZZI_S: case AArch64::UMLAL_VG2_M2ZZI_S: case AArch64::UMLSL_VG2_M2ZZI_S: { switch (OpNum) { case 5: // op: Zm return 16; case 2: // op: Rv return 13; case 6: // op: i3 return 2; case 4: // op: Zn return 6; case 3: // op: imm return 0; } break; } case AArch64::BFMLAL_VG4_M4ZZI_HtoS: case AArch64::BFMLSL_VG4_M4ZZI_HtoS: case AArch64::FMLAL_VG4_M4ZZI_HtoS: case AArch64::FMLSL_VG4_M4ZZI_HtoS: case AArch64::SMLAL_VG4_M4ZZI_HtoS: case AArch64::SMLSL_VG4_M4ZZI_HtoS: case AArch64::UMLAL_VG4_M4ZZI_HtoS: case AArch64::UMLSL_VG4_M4ZZI_HtoS: { switch (OpNum) { case 5: // op: Zm return 16; case 2: // op: Rv return 13; case 6: // op: i3 return 2; case 4: // op: Zn return 7; case 3: // op: imm return 0; } break; } case AArch64::BFMOPA_MPPZZ: case AArch64::BFMOPA_MPPZZ_H: case AArch64::BFMOPS_MPPZZ: case AArch64::BFMOPS_MPPZZ_H: case AArch64::BMOPA_MPPZZ_S: case AArch64::BMOPS_MPPZZ_S: case AArch64::FMOPAL_MPPZZ: case AArch64::FMOPA_MPPZZ_BtoH: case AArch64::FMOPA_MPPZZ_BtoS: case AArch64::FMOPA_MPPZZ_D: case AArch64::FMOPA_MPPZZ_H: case AArch64::FMOPA_MPPZZ_S: case AArch64::FMOPSL_MPPZZ: case AArch64::FMOPS_MPPZZ_D: case AArch64::FMOPS_MPPZZ_H: case AArch64::FMOPS_MPPZZ_S: case AArch64::SMOPA_MPPZZ_D: case AArch64::SMOPA_MPPZZ_HtoS: case AArch64::SMOPA_MPPZZ_S: case AArch64::SMOPS_MPPZZ_D: case AArch64::SMOPS_MPPZZ_HtoS: case AArch64::SMOPS_MPPZZ_S: case AArch64::SUMOPA_MPPZZ_D: case AArch64::SUMOPA_MPPZZ_S: case AArch64::SUMOPS_MPPZZ_D: case AArch64::SUMOPS_MPPZZ_S: case AArch64::UMOPA_MPPZZ_D: case AArch64::UMOPA_MPPZZ_HtoS: case AArch64::UMOPA_MPPZZ_S: case AArch64::UMOPS_MPPZZ_D: case AArch64::UMOPS_MPPZZ_HtoS: case AArch64::UMOPS_MPPZZ_S: case AArch64::USMOPA_MPPZZ_D: case AArch64::USMOPA_MPPZZ_S: case AArch64::USMOPS_MPPZZ_D: case AArch64::USMOPS_MPPZZ_S: { switch (OpNum) { case 5: // op: Zm return 16; case 3: // op: Pm return 13; case 2: // op: Pn return 10; case 4: // op: Zn return 5; case 0: // op: ZAda return 0; } break; } case AArch64::ADD_VG2_M2ZZ_D: case AArch64::ADD_VG2_M2ZZ_S: case AArch64::ADD_VG4_M4ZZ_D: case AArch64::ADD_VG4_M4ZZ_S: case AArch64::BFDOT_VG2_M2ZZ_HtoS: case AArch64::BFDOT_VG4_M4ZZ_HtoS: case AArch64::BFMLA_VG2_M2ZZ: case AArch64::BFMLA_VG4_M4ZZ: case AArch64::BFMLS_VG2_M2ZZ: case AArch64::BFMLS_VG4_M4ZZ: case AArch64::FDOT_VG2_M2ZZ_BtoH: case AArch64::FDOT_VG2_M2ZZ_BtoS: case AArch64::FDOT_VG2_M2ZZ_HtoS: case AArch64::FDOT_VG4_M4ZZ_BtoH: case AArch64::FDOT_VG4_M4ZZ_BtoS: case AArch64::FDOT_VG4_M4ZZ_HtoS: case AArch64::FMLA_VG2_M2ZZ_D: case AArch64::FMLA_VG2_M2ZZ_H: case AArch64::FMLA_VG2_M2ZZ_S: case AArch64::FMLA_VG4_M4ZZ_D: case AArch64::FMLA_VG4_M4ZZ_H: case AArch64::FMLA_VG4_M4ZZ_S: case AArch64::FMLS_VG2_M2ZZ_D: case AArch64::FMLS_VG2_M2ZZ_H: case AArch64::FMLS_VG2_M2ZZ_S: case AArch64::FMLS_VG4_M4ZZ_D: case AArch64::FMLS_VG4_M4ZZ_H: case AArch64::FMLS_VG4_M4ZZ_S: case AArch64::SDOT_VG2_M2ZZ_BtoS: case AArch64::SDOT_VG2_M2ZZ_HtoD: case AArch64::SDOT_VG2_M2ZZ_HtoS: case AArch64::SDOT_VG4_M4ZZ_BtoS: case AArch64::SDOT_VG4_M4ZZ_HtoD: case AArch64::SDOT_VG4_M4ZZ_HtoS: case AArch64::SUB_VG2_M2ZZ_D: case AArch64::SUB_VG2_M2ZZ_S: case AArch64::SUB_VG4_M4ZZ_D: case AArch64::SUB_VG4_M4ZZ_S: case AArch64::SUDOT_VG2_M2ZZ_BToS: case AArch64::SUDOT_VG4_M4ZZ_BToS: case AArch64::UDOT_VG2_M2ZZ_BtoS: case AArch64::UDOT_VG2_M2ZZ_HtoD: case AArch64::UDOT_VG2_M2ZZ_HtoS: case AArch64::UDOT_VG4_M4ZZ_BtoS: case AArch64::UDOT_VG4_M4ZZ_HtoD: case AArch64::UDOT_VG4_M4ZZ_HtoS: case AArch64::USDOT_VG2_M2ZZ_BToS: case AArch64::USDOT_VG4_M4ZZ_BToS: { switch (OpNum) { case 5: // op: Zm return 16; case 4: // op: Zn return 5; case 2: // op: Rv return 13; case 3: // op: imm3 return 0; } break; } case AArch64::FMLALL_VG2_M2Z2Z_BtoS: case AArch64::SMLALL_VG2_M2Z2Z_BtoS: case AArch64::SMLALL_VG2_M2Z2Z_HtoD: case AArch64::SMLSLL_VG2_M2Z2Z_BtoS: case AArch64::SMLSLL_VG2_M2Z2Z_HtoD: case AArch64::UMLALL_VG2_M2Z2Z_BtoS: case AArch64::UMLALL_VG2_M2Z2Z_HtoD: case AArch64::UMLSLL_VG2_M2Z2Z_BtoS: case AArch64::UMLSLL_VG2_M2Z2Z_HtoD: case AArch64::USMLALL_VG2_M2Z2Z_BtoS: { switch (OpNum) { case 5: // op: Zm return 17; case 2: // op: Rv return 13; case 4: // op: Zn return 6; case 3: // op: imm return 0; } break; } case AArch64::ADD_VG2_M2Z2Z_D: case AArch64::ADD_VG2_M2Z2Z_S: case AArch64::BFDOT_VG2_M2Z2Z_HtoS: case AArch64::BFMLA_VG2_M2Z2Z: case AArch64::BFMLS_VG2_M2Z2Z: case AArch64::FDOT_VG2_M2Z2Z_BtoH: case AArch64::FDOT_VG2_M2Z2Z_BtoS: case AArch64::FDOT_VG2_M2Z2Z_HtoS: case AArch64::FMLA_VG2_M2Z2Z_D: case AArch64::FMLA_VG2_M2Z2Z_S: case AArch64::FMLA_VG2_M2Z4Z_H: case AArch64::FMLS_VG2_M2Z2Z_D: case AArch64::FMLS_VG2_M2Z2Z_H: case AArch64::FMLS_VG2_M2Z2Z_S: case AArch64::SDOT_VG2_M2Z2Z_BtoS: case AArch64::SDOT_VG2_M2Z2Z_HtoD: case AArch64::SDOT_VG2_M2Z2Z_HtoS: case AArch64::SUB_VG2_M2Z2Z_D: case AArch64::SUB_VG2_M2Z2Z_S: case AArch64::UDOT_VG2_M2Z2Z_BtoS: case AArch64::UDOT_VG2_M2Z2Z_HtoD: case AArch64::UDOT_VG2_M2Z2Z_HtoS: case AArch64::USDOT_VG2_M2Z2Z_BToS: { switch (OpNum) { case 5: // op: Zm return 17; case 4: // op: Zn return 6; case 2: // op: Rv return 13; case 3: // op: imm3 return 0; } break; } case AArch64::FMLALL_VG4_M4Z4Z_BtoS: case AArch64::SMLALL_VG4_M4Z4Z_BtoS: case AArch64::SMLALL_VG4_M4Z4Z_HtoD: case AArch64::SMLSLL_VG4_M4Z4Z_BtoS: case AArch64::SMLSLL_VG4_M4Z4Z_HtoD: case AArch64::UMLALL_VG4_M4Z4Z_BtoS: case AArch64::UMLALL_VG4_M4Z4Z_HtoD: case AArch64::UMLSLL_VG4_M4Z4Z_BtoS: case AArch64::UMLSLL_VG4_M4Z4Z_HtoD: case AArch64::USMLALL_VG4_M4Z4Z_BtoS: { switch (OpNum) { case 5: // op: Zm return 18; case 2: // op: Rv return 13; case 4: // op: Zn return 7; case 3: // op: imm return 0; } break; } case AArch64::ADD_VG4_M4Z4Z_D: case AArch64::ADD_VG4_M4Z4Z_S: case AArch64::BFDOT_VG4_M4Z4Z_HtoS: case AArch64::BFMLA_VG4_M4Z4Z: case AArch64::BFMLS_VG4_M4Z4Z: case AArch64::FDOT_VG4_M4Z4Z_BtoH: case AArch64::FDOT_VG4_M4Z4Z_BtoS: case AArch64::FDOT_VG4_M4Z4Z_HtoS: case AArch64::FMLA_VG4_M4Z4Z_D: case AArch64::FMLA_VG4_M4Z4Z_H: case AArch64::FMLA_VG4_M4Z4Z_S: case AArch64::FMLS_VG4_M4Z2Z_H: case AArch64::FMLS_VG4_M4Z4Z_D: case AArch64::FMLS_VG4_M4Z4Z_S: case AArch64::SDOT_VG4_M4Z4Z_BtoS: case AArch64::SDOT_VG4_M4Z4Z_HtoD: case AArch64::SDOT_VG4_M4Z4Z_HtoS: case AArch64::SUB_VG4_M4Z4Z_D: case AArch64::SUB_VG4_M4Z4Z_S: case AArch64::UDOT_VG4_M4Z4Z_BtoS: case AArch64::UDOT_VG4_M4Z4Z_HtoD: case AArch64::UDOT_VG4_M4Z4Z_HtoS: case AArch64::USDOT_VG4_M4Z4Z_BToS: { switch (OpNum) { case 5: // op: Zm return 18; case 4: // op: Zn return 7; case 2: // op: Rv return 13; case 3: // op: imm3 return 0; } break; } } std::string msg; raw_string_ostream Msg(msg); Msg << "Not supported instr[opcode]: " << MI << "[" << OpNum << "]"; report_fatal_error(Msg.str().c_str()); } #endif // GET_OPERAND_BIT_OFFSET
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