/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |* *| |* Target Instruction Enum Values and Descriptors *| |* *| |* Automatically generated file, do not edit! *| |* *| \*===----------------------------------------------------------------------===*/ #ifdef GET_INSTRINFO_ENUM #undef GET_INSTRINFO_ENUM namespace llvm { namespace R600 { enum { … }; } // end namespace R600 } // end namespace llvm #endif // GET_INSTRINFO_ENUM #ifdef GET_INSTRINFO_SCHED_ENUM #undef GET_INSTRINFO_SCHED_ENUM namespace llvm { namespace R600 { namespace Sched { enum { … }; } // end namespace Sched } // end namespace R600 } // end namespace llvm #endif // GET_INSTRINFO_SCHED_ENUM #if defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR) namespace llvm { struct R600InstrTable { MCInstrDesc Insts[636]; static_assert(alignof(MCInstrDesc) >= alignof(MCOperandInfo), "Unwanted padding between Insts and OperandInfo"); MCOperandInfo OperandInfo[462]; static_assert(alignof(MCOperandInfo) >= alignof(MCPhysReg), "Unwanted padding between OperandInfo and ImplicitOps"); MCPhysReg ImplicitOps[1]; }; } // end namespace llvm #endif // defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR) #ifdef GET_INSTRINFO_MC_DESC #undef GET_INSTRINFO_MC_DESC namespace llvm { static_assert(sizeof(MCOperandInfo) % sizeof(MCPhysReg) == 0); static constexpr unsigned R600ImpOpBase = sizeof R600InstrTable::OperandInfo / (sizeof(MCPhysReg)); extern const R600InstrTable R600Descs = { { { 635, 21, 1, 0, 3, 0, 0, R600ImpOpBase + 0, 263, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #635 = XOR_INT { 634, 1, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #634 = WHILE_LOOP_R600 { 633, 1, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #633 = WHILE_LOOP_EG { 632, 4, 1, 0, 1, 0, 0, R600ImpOpBase + 0, 450, 0|(1ULL<<MCID::MayLoad), 0x1000ULL }, // Inst #632 = VTX_READ_8_eg { 631, 4, 1, 0, 1, 0, 0, R600ImpOpBase + 0, 450, 0|(1ULL<<MCID::MayLoad), 0x1000ULL }, // Inst #631 = VTX_READ_8_cm { 630, 4, 1, 0, 1, 0, 0, R600ImpOpBase + 0, 458, 0|(1ULL<<MCID::MayLoad), 0x1000ULL }, // Inst #630 = VTX_READ_64_eg { 629, 4, 1, 0, 1, 0, 0, R600ImpOpBase + 0, 458, 0|(1ULL<<MCID::MayLoad), 0x1000ULL }, // Inst #629 = VTX_READ_64_cm { 628, 4, 1, 0, 1, 0, 0, R600ImpOpBase + 0, 454, 0|(1ULL<<MCID::MayLoad), 0x1000ULL }, // Inst #628 = VTX_READ_32_eg { 627, 4, 1, 0, 1, 0, 0, R600ImpOpBase + 0, 454, 0|(1ULL<<MCID::MayLoad), 0x1000ULL }, // Inst #627 = VTX_READ_32_cm { 626, 4, 1, 0, 1, 0, 0, R600ImpOpBase + 0, 450, 0|(1ULL<<MCID::MayLoad), 0x1000ULL }, // Inst #626 = VTX_READ_16_eg { 625, 4, 1, 0, 1, 0, 0, R600ImpOpBase + 0, 450, 0|(1ULL<<MCID::MayLoad), 0x1000ULL }, // Inst #625 = VTX_READ_16_cm { 624, 4, 1, 0, 1, 0, 0, R600ImpOpBase + 0, 446, 0|(1ULL<<MCID::MayLoad), 0x1000ULL }, // Inst #624 = VTX_READ_128_eg { 623, 4, 1, 0, 1, 0, 0, R600ImpOpBase + 0, 446, 0|(1ULL<<MCID::MayLoad), 0x1000ULL }, // Inst #623 = VTX_READ_128_cm { 622, 14, 1, 0, 4, 0, 0, R600ImpOpBase + 0, 284, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // Inst #622 = UINT_TO_FLT_r600 { 621, 14, 1, 0, 4, 0, 0, R600ImpOpBase + 0, 284, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // Inst #621 = UINT_TO_FLT_eg { 620, 14, 1, 0, 3, 0, 0, R600ImpOpBase + 0, 284, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // Inst #620 = TRUNC { 619, 4, 1, 0, 1, 0, 0, R600ImpOpBase + 0, 446, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1000ULL }, // Inst #619 = TEX_VTX_TEXBUF { 618, 4, 1, 0, 1, 0, 0, R600ImpOpBase + 0, 446, 0, 0x1000ULL }, // Inst #618 = TEX_VTX_CONSTBUF { 617, 19, 1, 0, 1, 0, 0, R600ImpOpBase + 0, 427, 0, 0x2000ULL }, // Inst #617 = TEX_SET_GRADIENTS_V { 616, 19, 1, 0, 1, 0, 0, R600ImpOpBase + 0, 427, 0, 0x2000ULL }, // Inst #616 = TEX_SET_GRADIENTS_H { 615, 19, 1, 0, 1, 0, 0, R600ImpOpBase + 0, 427, 0, 0x2000ULL }, // Inst #615 = TEX_SAMPLE_LB { 614, 19, 1, 0, 1, 0, 0, R600ImpOpBase + 0, 427, 0, 0x2000ULL }, // Inst #614 = TEX_SAMPLE_L { 613, 19, 1, 0, 1, 0, 0, R600ImpOpBase + 0, 427, 0, 0x2000ULL }, // Inst #613 = TEX_SAMPLE_G { 612, 19, 1, 0, 1, 0, 0, R600ImpOpBase + 0, 427, 0, 0x2000ULL }, // Inst #612 = TEX_SAMPLE_C_LB { 611, 19, 1, 0, 1, 0, 0, R600ImpOpBase + 0, 427, 0, 0x2000ULL }, // Inst #611 = TEX_SAMPLE_C_L { 610, 19, 1, 0, 1, 0, 0, R600ImpOpBase + 0, 427, 0, 0x2000ULL }, // Inst #610 = TEX_SAMPLE_C_G { 609, 19, 1, 0, 1, 0, 0, R600ImpOpBase + 0, 427, 0, 0x2000ULL }, // Inst #609 = TEX_SAMPLE_C { 608, 19, 1, 0, 1, 0, 0, R600ImpOpBase + 0, 427, 0, 0x2000ULL }, // Inst #608 = TEX_SAMPLE { 607, 19, 1, 0, 1, 0, 0, R600ImpOpBase + 0, 427, 0, 0x2000ULL }, // Inst #607 = TEX_LDPTR { 606, 19, 1, 0, 1, 0, 0, R600ImpOpBase + 0, 427, 0, 0x2000ULL }, // Inst #606 = TEX_LD { 605, 19, 1, 0, 1, 0, 0, R600ImpOpBase + 0, 427, 0, 0x2000ULL }, // Inst #605 = TEX_GET_TEXTURE_RESINFO { 604, 19, 1, 0, 1, 0, 0, R600ImpOpBase + 0, 427, 0, 0x2000ULL }, // Inst #604 = TEX_GET_GRADIENTS_V { 603, 19, 1, 0, 1, 0, 0, R600ImpOpBase + 0, 427, 0, 0x2000ULL }, // Inst #603 = TEX_GET_GRADIENTS_H { 602, 21, 1, 0, 3, 0, 0, R600ImpOpBase + 0, 263, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #602 = SUB_INT { 601, 21, 1, 0, 3, 0, 0, R600ImpOpBase + 0, 263, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #601 = SUBB_UINT { 600, 21, 1, 0, 3, 0, 0, R600ImpOpBase + 0, 263, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #600 = SNE { 599, 14, 1, 0, 4, 0, 0, R600ImpOpBase + 0, 284, 0|(1ULL<<MCID::Predicable), 0x4610ULL }, // Inst #599 = SIN_r700 { 598, 14, 1, 0, 4, 0, 0, R600ImpOpBase + 0, 284, 0|(1ULL<<MCID::Predicable), 0x4610ULL }, // Inst #598 = SIN_r600 { 597, 14, 1, 0, 4, 0, 0, R600ImpOpBase + 0, 284, 0|(1ULL<<MCID::Predicable), 0x4610ULL }, // Inst #597 = SIN_eg { 596, 14, 1, 0, 4, 0, 0, R600ImpOpBase + 0, 284, 0|(1ULL<<MCID::Predicable), 0x4650ULL }, // Inst #596 = SIN_cm { 595, 21, 1, 0, 3, 0, 0, R600ImpOpBase + 0, 263, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #595 = SGT { 594, 21, 1, 0, 3, 0, 0, R600ImpOpBase + 0, 263, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #594 = SGE { 593, 21, 1, 0, 3, 0, 0, R600ImpOpBase + 0, 263, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #593 = SETNE_INT { 592, 21, 1, 0, 3, 0, 0, R600ImpOpBase + 0, 263, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #592 = SETNE_DX10 { 591, 21, 1, 0, 3, 0, 0, R600ImpOpBase + 0, 263, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #591 = SETGT_UINT { 590, 21, 1, 0, 3, 0, 0, R600ImpOpBase + 0, 263, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #590 = SETGT_INT { 589, 21, 1, 0, 3, 0, 0, R600ImpOpBase + 0, 263, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #589 = SETGT_DX10 { 588, 21, 1, 0, 3, 0, 0, R600ImpOpBase + 0, 263, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #588 = SETGE_UINT { 587, 21, 1, 0, 3, 0, 0, R600ImpOpBase + 0, 263, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #587 = SETGE_INT { 586, 21, 1, 0, 3, 0, 0, R600ImpOpBase + 0, 263, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #586 = SETGE_DX10 { 585, 21, 1, 0, 3, 0, 0, R600ImpOpBase + 0, 263, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #585 = SETE_INT { 584, 21, 1, 0, 3, 0, 0, R600ImpOpBase + 0, 263, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #584 = SETE_DX10 { 583, 21, 1, 0, 3, 0, 0, R600ImpOpBase + 0, 263, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #583 = SETE { 582, 14, 1, 0, 3, 0, 0, R600ImpOpBase + 0, 284, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // Inst #582 = RNDNE { 581, 14, 1, 0, 4, 0, 0, R600ImpOpBase + 0, 284, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // Inst #581 = RECIP_UINT_r600 { 580, 14, 1, 0, 4, 0, 0, R600ImpOpBase + 0, 284, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // Inst #580 = RECIP_UINT_eg { 579, 14, 1, 0, 4, 0, 0, R600ImpOpBase + 0, 284, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // Inst #579 = RECIP_IEEE_r600 { 578, 14, 1, 0, 4, 0, 0, R600ImpOpBase + 0, 284, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // Inst #578 = RECIP_IEEE_eg { 577, 14, 1, 0, 4, 0, 0, R600ImpOpBase + 0, 284, 0|(1ULL<<MCID::Predicable), 0x4640ULL }, // Inst #577 = RECIP_IEEE_cm { 576, 14, 1, 0, 4, 0, 0, R600ImpOpBase + 0, 284, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // Inst #576 = RECIP_CLAMPED_r600 { 575, 14, 1, 0, 4, 0, 0, R600ImpOpBase + 0, 284, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // Inst #575 = RECIP_CLAMPED_eg { 574, 14, 1, 0, 4, 0, 0, R600ImpOpBase + 0, 284, 0|(1ULL<<MCID::Predicable), 0x4640ULL }, // Inst #574 = RECIP_CLAMPED_cm { 573, 14, 1, 0, 4, 0, 0, R600ImpOpBase + 0, 284, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // Inst #573 = RECIPSQRT_IEEE_r600 { 572, 14, 1, 0, 4, 0, 0, R600ImpOpBase + 0, 284, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // Inst #572 = RECIPSQRT_IEEE_eg { 571, 14, 1, 0, 4, 0, 0, R600ImpOpBase + 0, 284, 0|(1ULL<<MCID::Predicable), 0x4640ULL }, // Inst #571 = RECIPSQRT_IEEE_cm { 570, 14, 1, 0, 4, 0, 0, R600ImpOpBase + 0, 284, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // Inst #570 = RECIPSQRT_CLAMPED_r600 { 569, 14, 1, 0, 4, 0, 0, R600ImpOpBase + 0, 284, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // Inst #569 = RECIPSQRT_CLAMPED_eg { 568, 14, 1, 0, 4, 0, 0, R600ImpOpBase + 0, 284, 0|(1ULL<<MCID::Predicable), 0x4640ULL }, // Inst #568 = RECIPSQRT_CLAMPED_cm { 567, 3, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 424, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x20000ULL }, // Inst #567 = RAT_WRITE_CACHELESS_64_eg { 566, 3, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 421, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x20000ULL }, // Inst #566 = RAT_WRITE_CACHELESS_32_eg { 565, 3, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 418, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x20000ULL }, // Inst #565 = RAT_WRITE_CACHELESS_128_eg { 564, 4, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 414, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // Inst #564 = RAT_STORE_TYPED_eg { 563, 4, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 414, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // Inst #563 = RAT_STORE_TYPED_cm { 562, 2, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 412, 0|(1ULL<<MCID::MayStore), 0x20000ULL }, // Inst #562 = RAT_STORE_DWORD64 { 561, 2, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 410, 0|(1ULL<<MCID::MayStore), 0x20000ULL }, // Inst #561 = RAT_STORE_DWORD32 { 560, 2, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 408, 0|(1ULL<<MCID::MayStore), 0x20000ULL }, // Inst #560 = RAT_STORE_DWORD128 { 559, 2, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 408, 0|(1ULL<<MCID::MayStore), 0x20000ULL }, // Inst #559 = RAT_MSKOR { 558, 3, 1, 0, 1, 0, 0, R600ImpOpBase + 0, 405, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // Inst #558 = RAT_ATOMIC_XOR_RTN { 557, 3, 1, 0, 1, 0, 0, R600ImpOpBase + 0, 405, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // Inst #557 = RAT_ATOMIC_XOR_NORET { 556, 3, 1, 0, 1, 0, 0, R600ImpOpBase + 0, 405, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // Inst #556 = RAT_ATOMIC_XCHG_INT_RTN { 555, 3, 1, 0, 1, 0, 0, R600ImpOpBase + 0, 405, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // Inst #555 = RAT_ATOMIC_XCHG_INT_NORET { 554, 3, 1, 0, 1, 0, 0, R600ImpOpBase + 0, 405, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // Inst #554 = RAT_ATOMIC_SUB_RTN { 553, 3, 1, 0, 1, 0, 0, R600ImpOpBase + 0, 405, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // Inst #553 = RAT_ATOMIC_SUB_NORET { 552, 3, 1, 0, 1, 0, 0, R600ImpOpBase + 0, 405, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // Inst #552 = RAT_ATOMIC_RSUB_RTN { 551, 3, 1, 0, 1, 0, 0, R600ImpOpBase + 0, 405, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // Inst #551 = RAT_ATOMIC_RSUB_NORET { 550, 3, 1, 0, 1, 0, 0, R600ImpOpBase + 0, 405, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // Inst #550 = RAT_ATOMIC_OR_RTN { 549, 3, 1, 0, 1, 0, 0, R600ImpOpBase + 0, 405, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // Inst #549 = RAT_ATOMIC_OR_NORET { 548, 3, 1, 0, 1, 0, 0, R600ImpOpBase + 0, 405, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // Inst #548 = RAT_ATOMIC_MIN_UINT_RTN { 547, 3, 1, 0, 1, 0, 0, R600ImpOpBase + 0, 405, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // Inst #547 = RAT_ATOMIC_MIN_UINT_NORET { 546, 3, 1, 0, 1, 0, 0, R600ImpOpBase + 0, 405, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // Inst #546 = RAT_ATOMIC_MIN_INT_RTN { 545, 3, 1, 0, 1, 0, 0, R600ImpOpBase + 0, 405, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // Inst #545 = RAT_ATOMIC_MIN_INT_NORET { 544, 3, 1, 0, 1, 0, 0, R600ImpOpBase + 0, 405, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // Inst #544 = RAT_ATOMIC_MAX_UINT_RTN { 543, 3, 1, 0, 1, 0, 0, R600ImpOpBase + 0, 405, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // Inst #543 = RAT_ATOMIC_MAX_UINT_NORET { 542, 3, 1, 0, 1, 0, 0, R600ImpOpBase + 0, 405, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // Inst #542 = RAT_ATOMIC_MAX_INT_RTN { 541, 3, 1, 0, 1, 0, 0, R600ImpOpBase + 0, 405, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // Inst #541 = RAT_ATOMIC_MAX_INT_NORET { 540, 3, 1, 0, 1, 0, 0, R600ImpOpBase + 0, 405, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // Inst #540 = RAT_ATOMIC_INC_UINT_RTN { 539, 3, 1, 0, 1, 0, 0, R600ImpOpBase + 0, 405, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // Inst #539 = RAT_ATOMIC_INC_UINT_NORET { 538, 3, 1, 0, 1, 0, 0, R600ImpOpBase + 0, 405, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // Inst #538 = RAT_ATOMIC_DEC_UINT_RTN { 537, 3, 1, 0, 1, 0, 0, R600ImpOpBase + 0, 405, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // Inst #537 = RAT_ATOMIC_DEC_UINT_NORET { 536, 3, 1, 0, 1, 0, 0, R600ImpOpBase + 0, 405, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // Inst #536 = RAT_ATOMIC_CMPXCHG_INT_RTN { 535, 3, 1, 0, 1, 0, 0, R600ImpOpBase + 0, 405, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // Inst #535 = RAT_ATOMIC_CMPXCHG_INT_NORET { 534, 3, 1, 0, 1, 0, 0, R600ImpOpBase + 0, 405, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // Inst #534 = RAT_ATOMIC_AND_RTN { 533, 3, 1, 0, 1, 0, 0, R600ImpOpBase + 0, 405, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // Inst #533 = RAT_ATOMIC_AND_NORET { 532, 3, 1, 0, 1, 0, 0, R600ImpOpBase + 0, 405, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // Inst #532 = RAT_ATOMIC_ADD_RTN { 531, 3, 1, 0, 1, 0, 0, R600ImpOpBase + 0, 405, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // Inst #531 = RAT_ATOMIC_ADD_NORET { 530, 9, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 333, 0|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // Inst #530 = R600_ExportSwz { 529, 7, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 326, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // Inst #529 = R600_ExportBuf { 528, 21, 1, 0, 3, 0, 0, R600ImpOpBase + 0, 263, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #528 = PRED_SETNE_INT { 527, 21, 1, 0, 3, 0, 0, R600ImpOpBase + 0, 263, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #527 = PRED_SETNE { 526, 21, 1, 0, 3, 0, 0, R600ImpOpBase + 0, 263, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #526 = PRED_SETGT_INT { 525, 21, 1, 0, 3, 0, 0, R600ImpOpBase + 0, 263, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #525 = PRED_SETGT { 524, 21, 1, 0, 3, 0, 0, R600ImpOpBase + 0, 263, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #524 = PRED_SETGE_INT { 523, 21, 1, 0, 3, 0, 0, R600ImpOpBase + 0, 263, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #523 = PRED_SETGE { 522, 21, 1, 0, 3, 0, 0, R600ImpOpBase + 0, 263, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #522 = PRED_SETE_INT { 521, 21, 1, 0, 3, 0, 0, R600ImpOpBase + 0, 263, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #521 = PRED_SETE { 520, 2, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 21, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #520 = POP_R600 { 519, 2, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 21, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #519 = POP_EG { 518, 0, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #518 = PAD { 517, 21, 1, 0, 3, 0, 0, R600ImpOpBase + 0, 263, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #517 = OR_INT { 516, 14, 1, 0, 3, 0, 0, R600ImpOpBase + 0, 284, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // Inst #516 = NOT_INT { 515, 21, 1, 0, 2, 0, 0, R600ImpOpBase + 0, 263, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #515 = MUL_UINT24_eg { 514, 19, 1, 0, 3, 0, 0, R600ImpOpBase + 0, 298, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // Inst #514 = MUL_LIT_r600 { 513, 19, 1, 0, 3, 0, 0, R600ImpOpBase + 0, 298, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // Inst #513 = MUL_LIT_eg { 512, 21, 1, 0, 2, 0, 0, R600ImpOpBase + 0, 263, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #512 = MUL_INT24_cm { 511, 21, 1, 0, 3, 0, 0, R600ImpOpBase + 0, 263, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #511 = MUL_IEEE { 510, 21, 1, 0, 4, 0, 0, R600ImpOpBase + 0, 263, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #510 = MULLO_UINT_r600 { 509, 21, 1, 0, 4, 0, 0, R600ImpOpBase + 0, 263, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #509 = MULLO_UINT_eg { 508, 21, 1, 0, 4, 0, 0, R600ImpOpBase + 0, 263, 0|(1ULL<<MCID::Predicable), 0x4a40ULL }, // Inst #508 = MULLO_UINT_cm { 507, 21, 1, 0, 4, 0, 0, R600ImpOpBase + 0, 263, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #507 = MULLO_INT_r600 { 506, 21, 1, 0, 4, 0, 0, R600ImpOpBase + 0, 263, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #506 = MULLO_INT_eg { 505, 21, 1, 0, 4, 0, 0, R600ImpOpBase + 0, 263, 0|(1ULL<<MCID::Predicable), 0x4a40ULL }, // Inst #505 = MULLO_INT_cm { 504, 21, 1, 0, 4, 0, 0, R600ImpOpBase + 0, 263, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #504 = MULHI_UINT_r600 { 503, 21, 1, 0, 4, 0, 0, R600ImpOpBase + 0, 263, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #503 = MULHI_UINT_eg { 502, 21, 1, 0, 2, 0, 0, R600ImpOpBase + 0, 263, 0|(1ULL<<MCID::Predicable), 0x4a40ULL }, // Inst #502 = MULHI_UINT_cm24 { 501, 21, 1, 0, 4, 0, 0, R600ImpOpBase + 0, 263, 0|(1ULL<<MCID::Predicable), 0x4a40ULL }, // Inst #501 = MULHI_UINT_cm { 500, 21, 1, 0, 2, 0, 0, R600ImpOpBase + 0, 263, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #500 = MULHI_UINT24_eg { 499, 21, 1, 0, 4, 0, 0, R600ImpOpBase + 0, 263, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #499 = MULHI_INT_r600 { 498, 21, 1, 0, 4, 0, 0, R600ImpOpBase + 0, 263, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #498 = MULHI_INT_eg { 497, 21, 1, 0, 2, 0, 0, R600ImpOpBase + 0, 263, 0|(1ULL<<MCID::Predicable), 0x4a40ULL }, // Inst #497 = MULHI_INT_cm24 { 496, 21, 1, 0, 4, 0, 0, R600ImpOpBase + 0, 263, 0|(1ULL<<MCID::Predicable), 0x4a40ULL }, // Inst #496 = MULHI_INT_cm { 495, 19, 1, 0, 3, 0, 0, R600ImpOpBase + 0, 298, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // Inst #495 = MULADD_r600 { 494, 19, 1, 0, 3, 0, 0, R600ImpOpBase + 0, 298, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // Inst #494 = MULADD_eg { 493, 19, 1, 0, 2, 0, 0, R600ImpOpBase + 0, 298, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // Inst #493 = MULADD_UINT24_eg { 492, 19, 1, 0, 2, 0, 0, R600ImpOpBase + 0, 298, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // Inst #492 = MULADD_INT24_cm { 491, 19, 1, 0, 3, 0, 0, R600ImpOpBase + 0, 298, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // Inst #491 = MULADD_IEEE_r600 { 490, 19, 1, 0, 3, 0, 0, R600ImpOpBase + 0, 298, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // Inst #490 = MULADD_IEEE_eg { 489, 21, 1, 0, 3, 0, 0, R600ImpOpBase + 0, 263, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #489 = MUL { 488, 14, 1, 0, 2, 0, 0, R600ImpOpBase + 0, 284, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x4600ULL }, // Inst #488 = MOVA_INT_eg { 487, 14, 1, 0, 3, 0, 0, R600ImpOpBase + 0, 284, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // Inst #487 = MOV { 486, 21, 1, 0, 3, 0, 0, R600ImpOpBase + 0, 263, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #486 = MIN_UINT { 485, 21, 1, 0, 3, 0, 0, R600ImpOpBase + 0, 263, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #485 = MIN_INT { 484, 21, 1, 0, 3, 0, 0, R600ImpOpBase + 0, 263, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #484 = MIN_DX10 { 483, 21, 1, 0, 3, 0, 0, R600ImpOpBase + 0, 263, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #483 = MIN { 482, 21, 1, 0, 3, 0, 0, R600ImpOpBase + 0, 263, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #482 = MAX_UINT { 481, 21, 1, 0, 3, 0, 0, R600ImpOpBase + 0, 263, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #481 = MAX_INT { 480, 21, 1, 0, 3, 0, 0, R600ImpOpBase + 0, 263, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #480 = MAX_DX10 { 479, 21, 1, 0, 3, 0, 0, R600ImpOpBase + 0, 263, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #479 = MAX { 478, 21, 1, 0, 3, 0, 0, R600ImpOpBase + 0, 263, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #478 = LSHR_r600 { 477, 21, 1, 0, 3, 0, 0, R600ImpOpBase + 0, 263, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #477 = LSHR_eg { 476, 21, 1, 0, 3, 0, 0, R600ImpOpBase + 0, 263, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #476 = LSHL_r600 { 475, 21, 1, 0, 3, 0, 0, R600ImpOpBase + 0, 263, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #475 = LSHL_eg { 474, 1, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #474 = LOOP_BREAK_R600 { 473, 1, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #473 = LOOP_BREAK_EG { 472, 14, 1, 0, 4, 0, 0, R600ImpOpBase + 0, 284, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // Inst #472 = LOG_IEEE_r600 { 471, 14, 1, 0, 4, 0, 0, R600ImpOpBase + 0, 284, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // Inst #471 = LOG_IEEE_eg { 470, 14, 1, 0, 4, 0, 0, R600ImpOpBase + 0, 284, 0|(1ULL<<MCID::Predicable), 0x4640ULL }, // Inst #470 = LOG_IEEE_cm { 469, 14, 1, 0, 3, 0, 0, R600ImpOpBase + 0, 284, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // Inst #469 = LOG_CLAMPED_r600 { 468, 14, 1, 0, 3, 0, 0, R600ImpOpBase + 0, 284, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // Inst #468 = LOG_CLAMPED_eg { 467, 2, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 13, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #467 = LITERALS { 466, 10, 1, 0, 5, 0, 0, R600ImpOpBase + 0, 363, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x14200ULL }, // Inst #466 = LDS_XOR_RET { 465, 9, 0, 0, 5, 0, 0, R600ImpOpBase + 0, 354, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x14200ULL }, // Inst #465 = LDS_XOR { 464, 10, 1, 0, 5, 0, 0, R600ImpOpBase + 0, 363, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x14200ULL }, // Inst #464 = LDS_WRXCHG_RET { 463, 9, 0, 0, 5, 0, 0, R600ImpOpBase + 0, 354, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x14200ULL }, // Inst #463 = LDS_WRXCHG { 462, 9, 0, 0, 5, 0, 0, R600ImpOpBase + 0, 354, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x14200ULL }, // Inst #462 = LDS_WRITE { 461, 7, 1, 0, 5, 0, 0, R600ImpOpBase + 0, 373, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0xc200ULL }, // Inst #461 = LDS_USHORT_READ_RET { 460, 7, 1, 0, 5, 0, 0, R600ImpOpBase + 0, 373, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0xc200ULL }, // Inst #460 = LDS_UBYTE_READ_RET { 459, 10, 1, 0, 5, 0, 0, R600ImpOpBase + 0, 363, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x14200ULL }, // Inst #459 = LDS_SUB_RET { 458, 9, 0, 0, 5, 0, 0, R600ImpOpBase + 0, 354, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x14200ULL }, // Inst #458 = LDS_SUB { 457, 9, 0, 0, 5, 0, 0, R600ImpOpBase + 0, 354, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x14200ULL }, // Inst #457 = LDS_SHORT_WRITE { 456, 7, 1, 0, 5, 0, 0, R600ImpOpBase + 0, 373, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0xc200ULL }, // Inst #456 = LDS_SHORT_READ_RET { 455, 7, 1, 0, 5, 0, 0, R600ImpOpBase + 0, 373, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0xc200ULL }, // Inst #455 = LDS_READ_RET { 454, 10, 1, 0, 5, 0, 0, R600ImpOpBase + 0, 363, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x14200ULL }, // Inst #454 = LDS_OR_RET { 453, 9, 0, 0, 5, 0, 0, R600ImpOpBase + 0, 354, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x14200ULL }, // Inst #453 = LDS_OR { 452, 10, 1, 0, 5, 0, 0, R600ImpOpBase + 0, 363, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x14200ULL }, // Inst #452 = LDS_MIN_UINT_RET { 451, 9, 0, 0, 5, 0, 0, R600ImpOpBase + 0, 354, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x14200ULL }, // Inst #451 = LDS_MIN_UINT { 450, 10, 1, 0, 5, 0, 0, R600ImpOpBase + 0, 363, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x14200ULL }, // Inst #450 = LDS_MIN_INT_RET { 449, 9, 0, 0, 5, 0, 0, R600ImpOpBase + 0, 354, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x14200ULL }, // Inst #449 = LDS_MIN_INT { 448, 10, 1, 0, 5, 0, 0, R600ImpOpBase + 0, 363, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x14200ULL }, // Inst #448 = LDS_MAX_UINT_RET { 447, 9, 0, 0, 5, 0, 0, R600ImpOpBase + 0, 354, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x14200ULL }, // Inst #447 = LDS_MAX_UINT { 446, 10, 1, 0, 5, 0, 0, R600ImpOpBase + 0, 363, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x14200ULL }, // Inst #446 = LDS_MAX_INT_RET { 445, 9, 0, 0, 5, 0, 0, R600ImpOpBase + 0, 354, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x14200ULL }, // Inst #445 = LDS_MAX_INT { 444, 13, 1, 0, 5, 0, 0, R600ImpOpBase + 0, 392, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x44200ULL }, // Inst #444 = LDS_CMPST_RET { 443, 12, 0, 0, 5, 0, 0, R600ImpOpBase + 0, 380, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44200ULL }, // Inst #443 = LDS_CMPST { 442, 9, 0, 0, 5, 0, 0, R600ImpOpBase + 0, 354, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x14200ULL }, // Inst #442 = LDS_BYTE_WRITE { 441, 7, 1, 0, 5, 0, 0, R600ImpOpBase + 0, 373, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0xc200ULL }, // Inst #441 = LDS_BYTE_READ_RET { 440, 10, 1, 0, 5, 0, 0, R600ImpOpBase + 0, 363, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x14200ULL }, // Inst #440 = LDS_AND_RET { 439, 9, 0, 0, 5, 0, 0, R600ImpOpBase + 0, 354, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x14200ULL }, // Inst #439 = LDS_AND { 438, 10, 1, 0, 5, 0, 0, R600ImpOpBase + 0, 363, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x14200ULL }, // Inst #438 = LDS_ADD_RET { 437, 9, 0, 0, 5, 0, 0, R600ImpOpBase + 0, 354, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x14200ULL }, // Inst #437 = LDS_ADD { 436, 21, 1, 0, 3, 0, 0, R600ImpOpBase + 0, 263, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x4a00ULL }, // Inst #436 = KILLGT { 435, 14, 1, 0, 4, 0, 0, R600ImpOpBase + 0, 284, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // Inst #435 = INT_TO_FLT_r600 { 434, 14, 1, 0, 4, 0, 0, R600ImpOpBase + 0, 284, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // Inst #434 = INT_TO_FLT_eg { 433, 21, 1, 0, 3, 0, 0, R600ImpOpBase + 0, 263, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #433 = INTERP_ZW { 432, 21, 1, 0, 3, 0, 0, R600ImpOpBase + 0, 263, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #432 = INTERP_XY { 431, 2, 1, 0, 1, 0, 0, R600ImpOpBase + 0, 352, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #431 = INTERP_VEC_LOAD { 430, 5, 2, 0, 1, 0, 0, R600ImpOpBase + 0, 347, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #430 = INTERP_PAIR_ZW { 429, 5, 2, 0, 1, 0, 0, R600ImpOpBase + 0, 342, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #429 = INTERP_PAIR_XY { 428, 14, 1, 0, 3, 0, 0, R600ImpOpBase + 0, 284, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // Inst #428 = INTERP_LOAD_P0 { 427, 0, 0, 0, 3, 0, 0, R600ImpOpBase + 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x4000ULL }, // Inst #427 = GROUP_BARRIER { 426, 14, 1, 0, 3, 0, 0, R600ImpOpBase + 0, 284, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // Inst #426 = FRACT { 425, 19, 1, 0, 2, 0, 0, R600ImpOpBase + 0, 298, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // Inst #425 = FMA_eg { 424, 14, 1, 0, 4, 0, 0, R600ImpOpBase + 0, 284, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // Inst #424 = FLT_TO_UINT_r600 { 423, 14, 1, 0, 4, 0, 0, R600ImpOpBase + 0, 284, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // Inst #423 = FLT_TO_UINT_eg { 422, 14, 1, 0, 4, 0, 0, R600ImpOpBase + 0, 284, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // Inst #422 = FLT_TO_INT_r600 { 421, 14, 1, 0, 3, 0, 0, R600ImpOpBase + 0, 284, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // Inst #421 = FLT_TO_INT_eg { 420, 14, 1, 0, 2, 0, 0, R600ImpOpBase + 0, 284, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // Inst #420 = FLT32_TO_FLT16 { 419, 14, 1, 0, 2, 0, 0, R600ImpOpBase + 0, 284, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // Inst #419 = FLT16_TO_FLT32 { 418, 14, 1, 0, 3, 0, 0, R600ImpOpBase + 0, 284, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // Inst #418 = FLOOR { 417, 14, 1, 0, 2, 0, 0, R600ImpOpBase + 0, 284, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // Inst #417 = FFBL_INT { 416, 14, 1, 0, 2, 0, 0, R600ImpOpBase + 0, 284, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // Inst #416 = FFBH_UINT { 415, 1, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #415 = FETCH_CLAUSE { 414, 14, 1, 0, 4, 0, 0, R600ImpOpBase + 0, 284, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // Inst #414 = EXP_IEEE_r600 { 413, 14, 1, 0, 4, 0, 0, R600ImpOpBase + 0, 284, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // Inst #413 = EXP_IEEE_eg { 412, 14, 1, 0, 4, 0, 0, R600ImpOpBase + 0, 284, 0|(1ULL<<MCID::Predicable), 0x4640ULL }, // Inst #412 = EXP_IEEE_cm { 411, 1, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #411 = END_LOOP_R600 { 410, 1, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #410 = END_LOOP_EG { 409, 9, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 333, 0|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // Inst #409 = EG_ExportSwz { 408, 7, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 326, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // Inst #408 = EG_ExportBuf { 407, 21, 1, 0, 3, 0, 0, R600ImpOpBase + 0, 263, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #407 = DOT4_r600 { 406, 21, 1, 0, 3, 0, 0, R600ImpOpBase + 0, 263, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #406 = DOT4_eg { 405, 21, 1, 0, 3, 0, 0, R600ImpOpBase + 0, 263, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #405 = CUBE_r600_real { 404, 21, 1, 0, 3, 0, 0, R600ImpOpBase + 0, 263, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #404 = CUBE_eg_real { 403, 14, 1, 0, 4, 0, 0, R600ImpOpBase + 0, 284, 0|(1ULL<<MCID::Predicable), 0x4610ULL }, // Inst #403 = COS_r700 { 402, 14, 1, 0, 4, 0, 0, R600ImpOpBase + 0, 284, 0|(1ULL<<MCID::Predicable), 0x4610ULL }, // Inst #402 = COS_r600 { 401, 14, 1, 0, 4, 0, 0, R600ImpOpBase + 0, 284, 0|(1ULL<<MCID::Predicable), 0x4610ULL }, // Inst #401 = COS_eg { 400, 14, 1, 0, 4, 0, 0, R600ImpOpBase + 0, 284, 0|(1ULL<<MCID::Predicable), 0x4650ULL }, // Inst #400 = COS_cm { 399, 19, 1, 0, 2, 0, 0, R600ImpOpBase + 0, 298, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // Inst #399 = CNDGT_r600 { 398, 19, 1, 0, 2, 0, 0, R600ImpOpBase + 0, 298, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // Inst #398 = CNDGT_eg { 397, 19, 1, 0, 3, 0, 0, R600ImpOpBase + 0, 298, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // Inst #397 = CNDGT_INT { 396, 19, 1, 0, 2, 0, 0, R600ImpOpBase + 0, 298, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // Inst #396 = CNDGE_r600 { 395, 19, 1, 0, 2, 0, 0, R600ImpOpBase + 0, 298, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // Inst #395 = CNDGE_eg { 394, 19, 1, 0, 3, 0, 0, R600ImpOpBase + 0, 298, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // Inst #394 = CNDGE_INT { 393, 19, 1, 0, 3, 0, 0, R600ImpOpBase + 0, 298, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // Inst #393 = CNDE_r600 { 392, 19, 1, 0, 3, 0, 0, R600ImpOpBase + 0, 298, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // Inst #392 = CNDE_eg { 391, 19, 1, 0, 3, 0, 0, R600ImpOpBase + 0, 298, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // Inst #391 = CNDE_INT { 390, 2, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 21, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #390 = CF_VC_R600 { 389, 2, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 21, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #389 = CF_VC_EG { 388, 2, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 21, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #388 = CF_TC_R600 { 387, 2, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 21, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #387 = CF_TC_EG { 386, 1, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #386 = CF_PUSH_ELSE_R600 { 385, 2, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 21, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #385 = CF_PUSH_EG { 384, 2, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 21, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #384 = CF_JUMP_R600 { 383, 2, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 21, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #383 = CF_JUMP_EG { 382, 0, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #382 = CF_END_R600 { 381, 0, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #381 = CF_END_EG { 380, 0, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #380 = CF_END_CM { 379, 2, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 21, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #379 = CF_ELSE_R600 { 378, 2, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 21, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #378 = CF_ELSE_EG { 377, 1, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #377 = CF_CONTINUE_R600 { 376, 1, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #376 = CF_CONTINUE_EG { 375, 0, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #375 = CF_CALL_FS_R600 { 374, 0, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #374 = CF_CALL_FS_EG { 373, 9, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 317, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #373 = CF_ALU_PUSH_BEFORE { 372, 9, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 317, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #372 = CF_ALU_POP_AFTER { 371, 9, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 317, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #371 = CF_ALU_ELSE_AFTER { 370, 9, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 317, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #370 = CF_ALU_CONTINUE { 369, 9, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 317, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #369 = CF_ALU_BREAK { 368, 9, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 317, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #368 = CF_ALU { 367, 14, 1, 0, 3, 0, 0, R600ImpOpBase + 0, 284, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // Inst #367 = CEIL { 366, 19, 1, 0, 2, 0, 0, R600ImpOpBase + 0, 298, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // Inst #366 = BIT_ALIGN_INT_eg { 365, 21, 1, 0, 2, 0, 0, R600ImpOpBase + 0, 263, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #365 = BFM_INT_eg { 364, 19, 1, 0, 2, 0, 0, R600ImpOpBase + 0, 298, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // Inst #364 = BFI_INT_eg { 363, 19, 1, 0, 2, 0, 0, R600ImpOpBase + 0, 298, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // Inst #363 = BFE_UINT_eg { 362, 19, 1, 0, 2, 0, 0, R600ImpOpBase + 0, 298, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // Inst #362 = BFE_INT_eg { 361, 14, 1, 0, 2, 0, 0, R600ImpOpBase + 0, 284, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // Inst #361 = BCNT_INT { 360, 21, 1, 0, 3, 0, 0, R600ImpOpBase + 0, 263, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #360 = ASHR_r600 { 359, 21, 1, 0, 3, 0, 0, R600ImpOpBase + 0, 263, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #359 = ASHR_eg { 358, 21, 1, 0, 3, 0, 0, R600ImpOpBase + 0, 263, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #358 = AND_INT { 357, 1, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #357 = ALU_CLAUSE { 356, 21, 1, 0, 3, 0, 0, R600ImpOpBase + 0, 263, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #356 = ADD_INT { 355, 21, 1, 0, 3, 0, 0, R600ImpOpBase + 0, 263, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #355 = ADDC_UINT { 354, 21, 1, 0, 3, 0, 0, R600ImpOpBase + 0, 263, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // Inst #354 = ADD { 353, 0, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #353 = WHILELOOP { 352, 7, 1, 0, 1, 0, 0, R600ImpOpBase + 0, 256, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x2000ULL }, // Inst #352 = TXD_SHADOW { 351, 7, 1, 0, 1, 0, 0, R600ImpOpBase + 0, 256, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x2000ULL }, // Inst #351 = TXD { 350, 0, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #350 = RETURN { 349, 0, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #349 = RETDYN { 348, 4, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 252, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4000000000000000ULL }, // Inst #348 = R600_RegisterStore { 347, 4, 1, 0, 1, 0, 0, R600ImpOpBase + 0, 252, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x8000000000000000ULL }, // Inst #347 = R600_RegisterLoad { 346, 4, 1, 0, 3, 0, 0, R600ImpOpBase + 0, 248, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #346 = R600_INSERT_ELT_V4 { 345, 4, 1, 0, 3, 0, 0, R600ImpOpBase + 0, 244, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #345 = R600_INSERT_ELT_V2 { 344, 3, 1, 0, 3, 0, 0, R600ImpOpBase + 0, 241, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #344 = R600_EXTRACT_ELT_V4 { 343, 3, 1, 0, 3, 0, 0, R600ImpOpBase + 0, 238, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #343 = R600_EXTRACT_ELT_V2 { 342, 4, 1, 0, 1, 0, 0, R600ImpOpBase + 0, 234, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x180ULL }, // Inst #342 = PRED_X { 341, 2, 1, 0, 1, 0, 0, R600ImpOpBase + 0, 157, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #341 = MOV_IMM_I32 { 340, 2, 1, 0, 1, 0, 0, R600ImpOpBase + 0, 157, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #340 = MOV_IMM_GLOBAL_ADDR { 339, 2, 1, 0, 1, 0, 0, R600ImpOpBase + 0, 157, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #339 = MOV_IMM_F32 { 338, 1, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 156, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #338 = MASK_WRITE { 337, 2, 0, 0, 3, 0, 0, R600ImpOpBase + 0, 232, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #337 = JUMP_COND { 336, 1, 0, 0, 3, 0, 0, R600ImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #336 = JUMP { 335, 1, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 156, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #335 = IF_PREDICATE_SET { 334, 1, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 156, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #334 = IF_LOGICALZ_i32 { 333, 1, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 156, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #333 = IF_LOGICALZ_f32 { 332, 1, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 156, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #332 = IF_LOGICALNZ_i32 { 331, 1, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 156, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #331 = IF_LOGICALNZ_f32 { 330, 2, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 154, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #330 = IFC_i32 { 329, 2, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 154, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #329 = IFC_f32 { 328, 0, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #328 = FUNC { 327, 2, 1, 0, 1, 0, 0, R600ImpOpBase + 0, 154, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #327 = FNEG_R600 { 326, 2, 1, 0, 1, 0, 0, R600ImpOpBase + 0, 154, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #326 = FABS_R600 { 325, 0, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #325 = ENDSWITCH { 324, 0, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #324 = ENDMAIN { 323, 0, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #323 = ENDLOOP { 322, 0, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #322 = ENDIF { 321, 0, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #321 = ENDFUNC { 320, 0, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #320 = END { 319, 0, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #319 = ELSE { 318, 0, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #318 = DUMMY_CHAIN { 317, 71, 1, 0, 3, 0, 0, R600ImpOpBase + 0, 161, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable), 0x0ULL }, // Inst #317 = DOT_4 { 316, 0, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #316 = DEFAULT { 315, 2, 1, 0, 2, 0, 0, R600ImpOpBase + 0, 159, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #315 = CUBE_r600_pseudo { 314, 2, 1, 0, 2, 0, 0, R600ImpOpBase + 0, 159, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #314 = CUBE_eg_pseudo { 313, 1, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 156, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #313 = CONTINUE_LOGICALZ_i32 { 312, 1, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 156, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #312 = CONTINUE_LOGICALZ_f32 { 311, 1, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 156, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #311 = CONTINUE_LOGICALNZ_i32 { 310, 1, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 156, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #310 = CONTINUE_LOGICALNZ_f32 { 309, 2, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 154, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #309 = CONTINUEC_i32 { 308, 2, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 154, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #308 = CONTINUEC_f32 { 307, 0, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #307 = CONTINUE { 306, 2, 1, 0, 1, 0, 0, R600ImpOpBase + 0, 157, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // Inst #306 = CONST_COPY { 305, 1, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 156, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #305 = BREAK_LOGICALZ_i32 { 304, 1, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 156, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #304 = BREAK_LOGICALZ_f32 { 303, 1, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 156, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #303 = BREAK_LOGICALNZ_i32 { 302, 1, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 156, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #302 = BREAK_LOGICALNZ_f32 { 301, 2, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 154, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #301 = BREAKC_i32 { 300, 2, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 154, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #300 = BREAKC_f32 { 299, 0, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #299 = BREAK { 298, 2, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 152, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #298 = BRANCH_COND_i32 { 297, 2, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 152, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #297 = BRANCH_COND_f32 { 296, 1, 0, 0, 1, 0, 0, R600ImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #296 = BRANCH { 295, 4, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 148, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #295 = G_UBFX { 294, 4, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 148, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #294 = G_SBFX { 293, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #293 = G_VECREDUCE_UMIN { 292, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #292 = G_VECREDUCE_UMAX { 291, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #291 = G_VECREDUCE_SMIN { 290, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #290 = G_VECREDUCE_SMAX { 289, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #289 = G_VECREDUCE_XOR { 288, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #288 = G_VECREDUCE_OR { 287, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #287 = G_VECREDUCE_AND { 286, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #286 = G_VECREDUCE_MUL { 285, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #285 = G_VECREDUCE_ADD { 284, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #284 = G_VECREDUCE_FMINIMUM { 283, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #283 = G_VECREDUCE_FMAXIMUM { 282, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #282 = G_VECREDUCE_FMIN { 281, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #281 = G_VECREDUCE_FMAX { 280, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #280 = G_VECREDUCE_FMUL { 279, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #279 = G_VECREDUCE_FADD { 278, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 131, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #278 = G_VECREDUCE_SEQ_FMUL { 277, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 131, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #277 = G_VECREDUCE_SEQ_FADD { 276, 1, 0, 0, 0, 0, 0, R600ImpOpBase + 0, 1, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #276 = G_UBSANTRAP { 275, 0, 0, 0, 0, 0, 0, R600ImpOpBase + 0, 1, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #275 = G_DEBUGTRAP { 274, 0, 0, 0, 0, 0, 0, R600ImpOpBase + 0, 1, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #274 = G_TRAP { 273, 3, 0, 0, 0, 0, 0, R600ImpOpBase + 0, 58, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #273 = G_BZERO { 272, 4, 0, 0, 0, 0, 0, R600ImpOpBase + 0, 144, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #272 = G_MEMSET { 271, 4, 0, 0, 0, 0, 0, R600ImpOpBase + 0, 144, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #271 = G_MEMMOVE { 270, 3, 0, 0, 0, 0, 0, R600ImpOpBase + 0, 131, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #270 = G_MEMCPY_INLINE { 269, 4, 0, 0, 0, 0, 0, R600ImpOpBase + 0, 144, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #269 = G_MEMCPY { 268, 2, 0, 0, 0, 0, 0, R600ImpOpBase + 0, 142, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #268 = G_WRITE_REGISTER { 267, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #267 = G_READ_REGISTER { 266, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #266 = G_STRICT_FLDEXP { 265, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #265 = G_STRICT_FSQRT { 264, 4, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 46, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #264 = G_STRICT_FMA { 263, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #263 = G_STRICT_FREM { 262, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #262 = G_STRICT_FDIV { 261, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #261 = G_STRICT_FMUL { 260, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #260 = G_STRICT_FSUB { 259, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #259 = G_STRICT_FADD { 258, 1, 0, 0, 0, 0, 0, R600ImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #258 = G_STACKRESTORE { 257, 1, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #257 = G_STACKSAVE { 256, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 69, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #256 = G_DYN_STACKALLOC { 255, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #255 = G_JUMP_TABLE { 254, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #254 = G_BLOCK_ADDR { 253, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #253 = G_ADDRSPACE_CAST { 252, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #252 = G_FNEARBYINT { 251, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #251 = G_FRINT { 250, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #250 = G_FFLOOR { 249, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #249 = G_FSQRT { 248, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #248 = G_FTANH { 247, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #247 = G_FSINH { 246, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #246 = G_FCOSH { 245, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #245 = G_FATAN { 244, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #244 = G_FASIN { 243, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #243 = G_FACOS { 242, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #242 = G_FTAN { 241, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #241 = G_FSIN { 240, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #240 = G_FCOS { 239, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #239 = G_FCEIL { 238, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #238 = G_BITREVERSE { 237, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #237 = G_BSWAP { 236, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #236 = G_CTPOP { 235, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #235 = G_CTLZ_ZERO_UNDEF { 234, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #234 = G_CTLZ { 233, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #233 = G_CTTZ_ZERO_UNDEF { 232, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #232 = G_CTTZ { 231, 4, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 138, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #231 = G_VECTOR_COMPRESS { 230, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #230 = G_SPLAT_VECTOR { 229, 4, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 134, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #229 = G_SHUFFLE_VECTOR { 228, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 131, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #228 = G_EXTRACT_VECTOR_ELT { 227, 4, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 127, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #227 = G_INSERT_VECTOR_ELT { 226, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 40, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #226 = G_EXTRACT_SUBVECTOR { 225, 4, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 63, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #225 = G_INSERT_SUBVECTOR { 224, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #224 = G_VSCALE { 223, 3, 0, 0, 0, 0, 0, R600ImpOpBase + 0, 124, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #223 = G_BRJT { 222, 1, 0, 0, 0, 0, 0, R600ImpOpBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #222 = G_BR { 221, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #221 = G_LLROUND { 220, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #220 = G_LROUND { 219, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #219 = G_ABS { 218, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #218 = G_UMAX { 217, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #217 = G_UMIN { 216, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #216 = G_SMAX { 215, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #215 = G_SMIN { 214, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #214 = G_PTRMASK { 213, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #213 = G_PTR_ADD { 212, 0, 0, 0, 0, 0, 0, R600ImpOpBase + 0, 1, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #212 = G_RESET_FPMODE { 211, 1, 0, 0, 0, 0, 0, R600ImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #211 = G_SET_FPMODE { 210, 1, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #210 = G_GET_FPMODE { 209, 0, 0, 0, 0, 0, 0, R600ImpOpBase + 0, 1, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #209 = G_RESET_FPENV { 208, 1, 0, 0, 0, 0, 0, R600ImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #208 = G_SET_FPENV { 207, 1, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #207 = G_GET_FPENV { 206, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #206 = G_FMAXIMUM { 205, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #205 = G_FMINIMUM { 204, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #204 = G_FMAXNUM_IEEE { 203, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #203 = G_FMINNUM_IEEE { 202, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #202 = G_FMAXNUM { 201, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #201 = G_FMINNUM { 200, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #200 = G_FCANONICALIZE { 199, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 98, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #199 = G_IS_FPCLASS { 198, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #198 = G_FCOPYSIGN { 197, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #197 = G_FABS { 196, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #196 = G_UITOFP { 195, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #195 = G_SITOFP { 194, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #194 = G_FPTOUI { 193, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #193 = G_FPTOSI { 192, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #192 = G_FPTRUNC { 191, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #191 = G_FPEXT { 190, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #190 = G_FNEG { 189, 3, 2, 0, 0, 0, 0, R600ImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #189 = G_FFREXP { 188, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #188 = G_FLDEXP { 187, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #187 = G_FLOG10 { 186, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #186 = G_FLOG2 { 185, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #185 = G_FLOG { 184, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #184 = G_FEXP10 { 183, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #183 = G_FEXP2 { 182, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #182 = G_FEXP { 181, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #181 = G_FPOWI { 180, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #180 = G_FPOW { 179, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #179 = G_FREM { 178, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #178 = G_FDIV { 177, 4, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 46, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #177 = G_FMAD { 176, 4, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 46, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #176 = G_FMA { 175, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #175 = G_FMUL { 174, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #174 = G_FSUB { 173, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #173 = G_FADD { 172, 4, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #172 = G_UDIVFIXSAT { 171, 4, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #171 = G_SDIVFIXSAT { 170, 4, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #170 = G_UDIVFIX { 169, 4, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #169 = G_SDIVFIX { 168, 4, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #168 = G_UMULFIXSAT { 167, 4, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #167 = G_SMULFIXSAT { 166, 4, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #166 = G_UMULFIX { 165, 4, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #165 = G_SMULFIX { 164, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #164 = G_SSHLSAT { 163, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #163 = G_USHLSAT { 162, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #162 = G_SSUBSAT { 161, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #161 = G_USUBSAT { 160, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #160 = G_SADDSAT { 159, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #159 = G_UADDSAT { 158, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #158 = G_SMULH { 157, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #157 = G_UMULH { 156, 4, 2, 0, 0, 0, 0, R600ImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #156 = G_SMULO { 155, 4, 2, 0, 0, 0, 0, R600ImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #155 = G_UMULO { 154, 5, 2, 0, 0, 0, 0, R600ImpOpBase + 0, 115, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #154 = G_SSUBE { 153, 4, 2, 0, 0, 0, 0, R600ImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #153 = G_SSUBO { 152, 5, 2, 0, 0, 0, 0, R600ImpOpBase + 0, 115, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #152 = G_SADDE { 151, 4, 2, 0, 0, 0, 0, R600ImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #151 = G_SADDO { 150, 5, 2, 0, 0, 0, 0, R600ImpOpBase + 0, 115, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #150 = G_USUBE { 149, 4, 2, 0, 0, 0, 0, R600ImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #149 = G_USUBO { 148, 5, 2, 0, 0, 0, 0, R600ImpOpBase + 0, 115, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #148 = G_UADDE { 147, 4, 2, 0, 0, 0, 0, R600ImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #147 = G_UADDO { 146, 4, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #146 = G_SELECT { 145, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 112, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #145 = G_UCMP { 144, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 112, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #144 = G_SCMP { 143, 4, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 108, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #143 = G_FCMP { 142, 4, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 108, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #142 = G_ICMP { 141, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #141 = G_ROTL { 140, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #140 = G_ROTR { 139, 4, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 104, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #139 = G_FSHR { 138, 4, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 104, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #138 = G_FSHL { 137, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #137 = G_ASHR { 136, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #136 = G_LSHR { 135, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #135 = G_SHL { 134, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #134 = G_ZEXT { 133, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 40, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #133 = G_SEXT_INREG { 132, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #132 = G_SEXT { 131, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 98, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #131 = G_VAARG { 130, 1, 0, 0, 0, 0, 0, R600ImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #130 = G_VASTART { 129, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #129 = G_FCONSTANT { 128, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #128 = G_CONSTANT { 127, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #127 = G_TRUNC { 126, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #126 = G_ANYEXT { 125, 1, 0, 0, 0, 0, 0, R600ImpOpBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #125 = G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS { 124, 1, 0, 0, 0, 0, 0, R600ImpOpBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #124 = G_INTRINSIC_CONVERGENT { 123, 1, 0, 0, 0, 0, 0, R600ImpOpBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #123 = G_INTRINSIC_W_SIDE_EFFECTS { 122, 1, 0, 0, 0, 0, 0, R600ImpOpBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #122 = G_INTRINSIC { 121, 0, 0, 0, 0, 0, 0, R600ImpOpBase + 0, 1, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #121 = G_INVOKE_REGION_START { 120, 1, 0, 0, 0, 0, 0, R600ImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #120 = G_BRINDIRECT { 119, 2, 0, 0, 0, 0, 0, R600ImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #119 = G_BRCOND { 118, 4, 0, 0, 0, 0, 0, R600ImpOpBase + 0, 94, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #118 = G_PREFETCH { 117, 2, 0, 0, 0, 0, 0, R600ImpOpBase + 0, 21, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #117 = G_FENCE { 116, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #116 = G_ATOMICRMW_UDEC_WRAP { 115, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #115 = G_ATOMICRMW_UINC_WRAP { 114, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #114 = G_ATOMICRMW_FMIN { 113, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #113 = G_ATOMICRMW_FMAX { 112, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #112 = G_ATOMICRMW_FSUB { 111, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #111 = G_ATOMICRMW_FADD { 110, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #110 = G_ATOMICRMW_UMIN { 109, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #109 = G_ATOMICRMW_UMAX { 108, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #108 = G_ATOMICRMW_MIN { 107, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #107 = G_ATOMICRMW_MAX { 106, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #106 = G_ATOMICRMW_XOR { 105, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #105 = G_ATOMICRMW_OR { 104, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #104 = G_ATOMICRMW_NAND { 103, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #103 = G_ATOMICRMW_AND { 102, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #102 = G_ATOMICRMW_SUB { 101, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #101 = G_ATOMICRMW_ADD { 100, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #100 = G_ATOMICRMW_XCHG { 99, 4, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #99 = G_ATOMIC_CMPXCHG { 98, 5, 2, 0, 0, 0, 0, R600ImpOpBase + 0, 82, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #98 = G_ATOMIC_CMPXCHG_WITH_SUCCESS { 97, 5, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 77, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #97 = G_INDEXED_STORE { 96, 2, 0, 0, 0, 0, 0, R600ImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #96 = G_STORE { 95, 5, 2, 0, 0, 0, 0, R600ImpOpBase + 0, 72, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #95 = G_INDEXED_ZEXTLOAD { 94, 5, 2, 0, 0, 0, 0, R600ImpOpBase + 0, 72, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #94 = G_INDEXED_SEXTLOAD { 93, 5, 2, 0, 0, 0, 0, R600ImpOpBase + 0, 72, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #93 = G_INDEXED_LOAD { 92, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #92 = G_ZEXTLOAD { 91, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #91 = G_SEXTLOAD { 90, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #90 = G_LOAD { 89, 1, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #89 = G_READSTEADYCOUNTER { 88, 1, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #88 = G_READCYCLECOUNTER { 87, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #87 = G_INTRINSIC_ROUNDEVEN { 86, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #86 = G_INTRINSIC_LLRINT { 85, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #85 = G_INTRINSIC_LRINT { 84, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #84 = G_INTRINSIC_ROUND { 83, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #83 = G_INTRINSIC_TRUNC { 82, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 69, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #82 = G_INTRINSIC_FPTRUNC_ROUND { 81, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #81 = G_CONSTANT_FOLD_BARRIER { 80, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #80 = G_FREEZE { 79, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #79 = G_BITCAST { 78, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #78 = G_INTTOPTR { 77, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #77 = G_PTRTOINT { 76, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #76 = G_CONCAT_VECTORS { 75, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #75 = G_BUILD_VECTOR_TRUNC { 74, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #74 = G_BUILD_VECTOR { 73, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #73 = G_MERGE_VALUES { 72, 4, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 63, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #72 = G_INSERT { 71, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #71 = G_UNMERGE_VALUES { 70, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 58, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #70 = G_EXTRACT { 69, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #69 = G_CONSTANT_POOL { 68, 5, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 53, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #68 = G_PTRAUTH_GLOBAL_VALUE { 67, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #67 = G_GLOBAL_VALUE { 66, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #66 = G_FRAME_INDEX { 65, 1, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #65 = G_PHI { 64, 1, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #64 = G_IMPLICIT_DEF { 63, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #63 = G_XOR { 62, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #62 = G_OR { 61, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #61 = G_AND { 60, 4, 2, 0, 0, 0, 0, R600ImpOpBase + 0, 46, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #60 = G_UDIVREM { 59, 4, 2, 0, 0, 0, 0, R600ImpOpBase + 0, 46, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #59 = G_SDIVREM { 58, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #58 = G_UREM { 57, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #57 = G_SREM { 56, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #56 = G_UDIV { 55, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #55 = G_SDIV { 54, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #54 = G_MUL { 53, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #53 = G_SUB { 52, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #52 = G_ADD { 51, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 40, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #51 = G_ASSERT_ALIGN { 50, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 40, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #50 = G_ASSERT_ZEXT { 49, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 40, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #49 = G_ASSERT_SEXT { 48, 1, 0, 0, 0, 0, 0, R600ImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #48 = CONVERGENCECTRL_GLUE { 47, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 13, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #47 = CONVERGENCECTRL_LOOP { 46, 1, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #46 = CONVERGENCECTRL_ANCHOR { 45, 1, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #45 = CONVERGENCECTRL_ENTRY { 44, 1, 0, 0, 0, 0, 0, R600ImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL }, // Inst #44 = JUMP_TABLE_DEBUG_INFO { 43, 0, 0, 0, 0, 0, 0, R600ImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #43 = MEMBARRIER { 42, 0, 0, 0, 0, 0, 0, R600ImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #42 = FAKE_USE { 41, 0, 0, 0, 0, 0, 0, R600ImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #41 = ICALL_BRANCH_FUNNEL { 40, 3, 0, 0, 0, 0, 0, R600ImpOpBase + 0, 37, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #40 = PATCHABLE_TYPED_EVENT_CALL { 39, 2, 0, 0, 0, 0, 0, R600ImpOpBase + 0, 35, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #39 = PATCHABLE_EVENT_CALL { 38, 0, 0, 0, 0, 0, 0, R600ImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #38 = PATCHABLE_TAIL_CALL { 37, 0, 0, 0, 0, 0, 0, R600ImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #37 = PATCHABLE_FUNCTION_EXIT { 36, 0, 0, 0, 0, 0, 0, R600ImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #36 = PATCHABLE_RET { 35, 0, 0, 0, 0, 0, 0, R600ImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #35 = PATCHABLE_FUNCTION_ENTER { 34, 0, 0, 0, 0, 0, 0, R600ImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #34 = PATCHABLE_OP { 33, 1, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #33 = FAULTING_OP { 32, 2, 0, 0, 0, 0, 0, R600ImpOpBase + 0, 33, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #32 = LOCAL_ESCAPE { 31, 0, 0, 0, 0, 0, 0, R600ImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #31 = STATEPOINT { 30, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 30, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #30 = PREALLOCATED_ARG { 29, 1, 0, 0, 0, 0, 0, R600ImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #29 = PREALLOCATED_SETUP { 28, 1, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 29, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x0ULL }, // Inst #28 = LOAD_STACK_GUARD { 27, 6, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 23, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #27 = PATCHPOINT { 26, 0, 0, 0, 0, 0, 0, R600ImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #26 = FENTRY_CALL { 25, 2, 0, 0, 0, 0, 0, R600ImpOpBase + 0, 21, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #25 = STACKMAP { 24, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 19, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL }, // Inst #24 = ARITH_FENCE { 23, 4, 0, 0, 0, 0, 0, R600ImpOpBase + 0, 15, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #23 = PSEUDO_PROBE { 22, 1, 0, 0, 0, 0, 0, R600ImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL }, // Inst #22 = LIFETIME_END { 21, 1, 0, 0, 0, 0, 0, R600ImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL }, // Inst #21 = LIFETIME_START { 20, 0, 0, 0, 0, 0, 0, R600ImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #20 = BUNDLE { 19, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 13, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // Inst #19 = COPY { 18, 2, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 13, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // Inst #18 = REG_SEQUENCE { 17, 1, 0, 0, 0, 0, 0, R600ImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL }, // Inst #17 = DBG_LABEL { 16, 0, 0, 0, 0, 0, 0, R600ImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #16 = DBG_PHI { 15, 0, 0, 0, 0, 0, 0, R600ImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #15 = DBG_INSTR_REF { 14, 0, 0, 0, 0, 0, 0, R600ImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #14 = DBG_VALUE_LIST { 13, 0, 0, 0, 0, 0, 0, R600ImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #13 = DBG_VALUE { 12, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // Inst #12 = COPY_TO_REGCLASS { 11, 4, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 9, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #11 = SUBREG_TO_REG { 10, 1, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // Inst #10 = IMPLICIT_DEF { 9, 4, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 5, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #9 = INSERT_SUBREG { 8, 3, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 2, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #8 = EXTRACT_SUBREG { 7, 0, 0, 0, 0, 0, 0, R600ImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #7 = KILL { 6, 1, 0, 0, 0, 0, 0, R600ImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // Inst #6 = ANNOTATION_LABEL { 5, 1, 0, 0, 0, 0, 0, R600ImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // Inst #5 = GC_LABEL { 4, 1, 0, 0, 0, 0, 0, R600ImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // Inst #4 = EH_LABEL { 3, 1, 0, 0, 0, 0, 0, R600ImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // Inst #3 = CFI_INSTRUCTION { 2, 0, 0, 0, 0, 0, 0, R600ImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2 = INLINEASM_BR { 1, 0, 0, 0, 0, 0, 0, R600ImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #1 = INLINEASM { 0, 1, 1, 0, 0, 0, 0, R600ImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #0 = PHI }, { /* 0 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 1 */ /* 1 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, /* 2 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, /* 5 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, /* 9 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, /* 13 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 15 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, /* 19 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) }, /* 21 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, /* 23 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, /* 29 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, /* 30 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, /* 33 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, /* 35 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 37 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 40 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 }, /* 43 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, /* 46 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, /* 50 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, /* 51 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 53 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, /* 58 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 }, /* 61 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, /* 63 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 }, /* 67 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, /* 69 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, /* 72 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 77 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 82 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, /* 87 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, /* 91 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, /* 94 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, /* 98 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 101 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, /* 104 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, /* 108 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, /* 112 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, /* 115 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, /* 120 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 }, /* 124 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, /* 127 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, /* 131 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, /* 134 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 138 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, /* 142 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, /* 144 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 }, /* 148 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, /* 152 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 154 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 156 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 157 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, /* 159 */ { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 161 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_TReg32_YRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_TReg32_YRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_TReg32_ZRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_TReg32_ZRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_TReg32_WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_TReg32_WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 232 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Predicate_BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 234 */ { R600::R600_Predicate_BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, /* 238 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg64VerticalRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 241 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg128VerticalRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 244 */ { R600::R600_Reg64VerticalRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg64VerticalRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 248 */ { R600::R600_Reg128VerticalRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg128VerticalRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 252 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, /* 256 */ { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, /* 263 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 284 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 298 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 317 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, /* 326 */ { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, /* 333 */ { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, /* 342 */ { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_YRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { R600::R600_TReg32_YRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 347 */ { R600::R600_TReg32_ZRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { R600::R600_TReg32_YRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 352 */ { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, /* 354 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 363 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 373 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 380 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 392 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 405 */ { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 408 */ { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 410 */ { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 412 */ { R600::R600_Reg64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 414 */ { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 418 */ { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 421 */ { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 424 */ { R600::R600_Reg64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 427 */ { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 446 */ { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, /* 450 */ { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, /* 454 */ { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, /* 458 */ { R600::R600_Reg64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }, { /* 0 */ } }; #ifdef __GNUC__ #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Woverlength-strings" #endif extern const char R600InstrNameData[] = { /* 0 */ "CF_TC_R600\0" /* 11 */ "CF_VC_R600\0" /* 22 */ "CF_END_R600\0" /* 34 */ "CF_ELSE_R600\0" /* 47 */ "CF_PUSH_ELSE_R600\0" /* 65 */ "CF_CONTINUE_R600\0" /* 82 */ "FNEG_R600\0" /* 92 */ "LOOP_BREAK_R600\0" /* 108 */ "CF_JUMP_R600\0" /* 121 */ "END_LOOP_R600\0" /* 135 */ "WHILE_LOOP_R600\0" /* 151 */ "POP_R600\0" /* 160 */ "FABS_R600\0" /* 170 */ "CF_CALL_FS_R600\0" /* 186 */ "DOT4_r600\0" /* 196 */ "MULADD_r600\0" /* 208 */ "LOG_CLAMPED_r600\0" /* 225 */ "RECIP_CLAMPED_r600\0" /* 244 */ "RECIPSQRT_CLAMPED_r600\0" /* 267 */ "CNDE_r600\0" /* 277 */ "MULADD_IEEE_r600\0" /* 294 */ "LOG_IEEE_r600\0" /* 308 */ "RECIP_IEEE_r600\0" /* 324 */ "EXP_IEEE_r600\0" /* 338 */ "RECIPSQRT_IEEE_r600\0" /* 358 */ "CNDGE_r600\0" /* 369 */ "LSHL_r600\0" /* 379 */ "SIN_r600\0" /* 388 */ "ASHR_r600\0" /* 398 */ "LSHR_r600\0" /* 408 */ "COS_r600\0" /* 417 */ "CNDGT_r600\0" /* 428 */ "MUL_LIT_r600\0" /* 441 */ "UINT_TO_FLT_r600\0" /* 458 */ "MULHI_UINT_r600\0" /* 474 */ "MULLO_UINT_r600\0" /* 490 */ "FLT_TO_UINT_r600\0" /* 507 */ "RECIP_UINT_r600\0" /* 523 */ "MULHI_INT_r600\0" /* 538 */ "MULLO_INT_r600\0" /* 553 */ "FLT_TO_INT_r600\0" /* 569 */ "SIN_r700\0" /* 578 */ "COS_r700\0" /* 587 */ "G_FLOG10\0" /* 596 */ "G_FEXP10\0" /* 605 */ "SETGE_DX10\0" /* 616 */ "SETNE_DX10\0" /* 627 */ "SETE_DX10\0" /* 637 */ "MIN_DX10\0" /* 646 */ "SETGT_DX10\0" /* 657 */ "MAX_DX10\0" /* 666 */ "INTERP_LOAD_P0\0" /* 681 */ "RAT_STORE_DWORD32\0" /* 699 */ "MOV_IMM_F32\0" /* 711 */ "MOV_IMM_I32\0" /* 723 */ "FLT16_TO_FLT32\0" /* 738 */ "CONTINUEC_f32\0" /* 752 */ "IFC_f32\0" /* 760 */ "BREAKC_f32\0" /* 771 */ "BRANCH_COND_f32\0" /* 787 */ "CONTINUE_LOGICALZ_f32\0" /* 809 */ "IF_LOGICALZ_f32\0" /* 825 */ "BREAK_LOGICALZ_f32\0" /* 844 */ "CONTINUE_LOGICALNZ_f32\0" /* 867 */ "IF_LOGICALNZ_f32\0" /* 884 */ "BREAK_LOGICALNZ_f32\0" /* 904 */ "CONTINUEC_i32\0" /* 918 */ "IFC_i32\0" /* 926 */ "BREAKC_i32\0" /* 937 */ "BRANCH_COND_i32\0" /* 953 */ "CONTINUE_LOGICALZ_i32\0" /* 975 */ "IF_LOGICALZ_i32\0" /* 991 */ "BREAK_LOGICALZ_i32\0" /* 1010 */ "CONTINUE_LOGICALNZ_i32\0" /* 1033 */ "IF_LOGICALNZ_i32\0" /* 1050 */ "BREAK_LOGICALNZ_i32\0" /* 1070 */ "G_FLOG2\0" /* 1078 */ "G_FEXP2\0" /* 1086 */ "R600_EXTRACT_ELT_V2\0" /* 1106 */ "R600_INSERT_ELT_V2\0" /* 1125 */ "MULHI_UINT_cm24\0" /* 1141 */ "MULHI_INT_cm24\0" /* 1156 */ "RAT_STORE_DWORD64\0" /* 1174 */ "R600_EXTRACT_ELT_V4\0" /* 1194 */ "R600_INSERT_ELT_V4\0" /* 1213 */ "DOT_4\0" /* 1219 */ "FLT32_TO_FLT16\0" /* 1234 */ "RAT_STORE_DWORD128\0" /* 1253 */ "G_FMA\0" /* 1259 */ "G_STRICT_FMA\0" /* 1272 */ "TEX_SAMPLE_C_LB\0" /* 1288 */ "TEX_SAMPLE_LB\0" /* 1302 */ "G_FSUB\0" /* 1309 */ "G_STRICT_FSUB\0" /* 1323 */ "G_ATOMICRMW_FSUB\0" /* 1340 */ "G_SUB\0" /* 1346 */ "LDS_SUB\0" /* 1354 */ "G_ATOMICRMW_SUB\0" /* 1370 */ "G_INTRINSIC\0" /* 1382 */ "ENDFUNC\0" /* 1390 */ "G_FPTRUNC\0" /* 1400 */ "G_INTRINSIC_TRUNC\0" /* 1418 */ "G_TRUNC\0" /* 1426 */ "G_BUILD_VECTOR_TRUNC\0" /* 1447 */ "G_DYN_STACKALLOC\0" /* 1464 */ "TEX_SAMPLE_C\0" /* 1477 */ "G_FMAD\0" /* 1484 */ "G_INDEXED_SEXTLOAD\0" /* 1503 */ "G_SEXTLOAD\0" /* 1514 */ "G_INDEXED_ZEXTLOAD\0" /* 1533 */ "G_ZEXTLOAD\0" /* 1544 */ "INTERP_VEC_LOAD\0" /* 1560 */ "G_INDEXED_LOAD\0" /* 1575 */ "G_LOAD\0" /* 1582 */ "PAD\0" /* 1586 */ "G_VECREDUCE_FADD\0" /* 1603 */ "G_FADD\0" /* 1610 */ "G_VECREDUCE_SEQ_FADD\0" /* 1631 */ "G_STRICT_FADD\0" /* 1645 */ "G_ATOMICRMW_FADD\0" /* 1662 */ "G_VECREDUCE_ADD\0" /* 1678 */ "G_ADD\0" /* 1684 */ "G_PTR_ADD\0" /* 1694 */ "LDS_ADD\0" /* 1702 */ "G_ATOMICRMW_ADD\0" /* 1718 */ "TEX_LD\0" /* 1725 */ "G_ATOMICRMW_NAND\0" /* 1742 */ "G_VECREDUCE_AND\0" /* 1758 */ "G_AND\0" /* 1764 */ "LDS_AND\0" /* 1772 */ "G_ATOMICRMW_AND\0" /* 1788 */ "LIFETIME_END\0" /* 1801 */ "G_BRCOND\0" /* 1810 */ "JUMP_COND\0" /* 1820 */ "G_LLROUND\0" /* 1830 */ "G_LROUND\0" /* 1839 */ "G_INTRINSIC_ROUND\0" /* 1857 */ "G_INTRINSIC_FPTRUNC_ROUND\0" /* 1883 */ "LOAD_STACK_GUARD\0" /* 1900 */ "TXD\0" /* 1904 */ "PSEUDO_PROBE\0" /* 1917 */ "G_SSUBE\0" /* 1925 */ "G_USUBE\0" /* 1933 */ "G_FENCE\0" /* 1941 */ "ARITH_FENCE\0" /* 1953 */ "REG_SEQUENCE\0" /* 1966 */ "G_SADDE\0" /* 1974 */ "G_UADDE\0" /* 1982 */ "G_GET_FPMODE\0" /* 1995 */ "G_RESET_FPMODE\0" /* 2010 */ "G_SET_FPMODE\0" /* 2023 */ "MUL_IEEE\0" /* 2032 */ "G_FMINNUM_IEEE\0" /* 2047 */ "G_FMAXNUM_IEEE\0" /* 2062 */ "SGE\0" /* 2066 */ "PRED_SETGE\0" /* 2077 */ "G_VSCALE\0" /* 2086 */ "G_JUMP_TABLE\0" /* 2099 */ "BUNDLE\0" /* 2106 */ "TEX_SAMPLE\0" /* 2117 */ "RNDNE\0" /* 2123 */ "G_MEMCPY_INLINE\0" /* 2139 */ "SNE\0" /* 2143 */ "PRED_SETNE\0" /* 2154 */ "LOCAL_ESCAPE\0" /* 2167 */ "CF_ALU_PUSH_BEFORE\0" /* 2186 */ "G_STACKRESTORE\0" /* 2201 */ "G_INDEXED_STORE\0" /* 2217 */ "G_STORE\0" /* 2225 */ "ELSE\0" /* 2230 */ "G_BITREVERSE\0" /* 2243 */ "FETCH_CLAUSE\0" /* 2256 */ "ALU_CLAUSE\0" /* 2267 */ "FAKE_USE\0" /* 2276 */ "PRED_SETE\0" /* 2286 */ "LDS_BYTE_WRITE\0" /* 2301 */ "MASK_WRITE\0" /* 2312 */ "LDS_WRITE\0" /* 2322 */ "LDS_SHORT_WRITE\0" /* 2338 */ "DBG_VALUE\0" /* 2348 */ "G_GLOBAL_VALUE\0" /* 2363 */ "G_PTRAUTH_GLOBAL_VALUE\0" /* 2386 */ "CONVERGENCECTRL_GLUE\0" /* 2407 */ "CF_ALU_CONTINUE\0" /* 2423 */ "G_STACKSAVE\0" /* 2435 */ "G_MEMMOVE\0" /* 2445 */ "G_FREEZE\0" /* 2454 */ "G_FCANONICALIZE\0" /* 2470 */ "G_CTLZ_ZERO_UNDEF\0" /* 2488 */ "G_CTTZ_ZERO_UNDEF\0" /* 2506 */ "G_IMPLICIT_DEF\0" /* 2521 */ "DBG_INSTR_REF\0" /* 2535 */ "ENDIF\0" /* 2541 */ "TEX_VTX_CONSTBUF\0" /* 2558 */ "TEX_VTX_TEXBUF\0" /* 2573 */ "G_FNEG\0" /* 2580 */ "EXTRACT_SUBREG\0" /* 2595 */ "INSERT_SUBREG\0" /* 2609 */ "G_SEXT_INREG\0" /* 2622 */ "SUBREG_TO_REG\0" /* 2636 */ "CF_TC_EG\0" /* 2645 */ "CF_VC_EG\0" /* 2654 */ "CF_END_EG\0" /* 2664 */ "CF_ELSE_EG\0" /* 2675 */ "CF_CONTINUE_EG\0" /* 2690 */ "CF_PUSH_EG\0" /* 2701 */ "LOOP_BREAK_EG\0" /* 2715 */ "CF_JUMP_EG\0" /* 2726 */ "END_LOOP_EG\0" /* 2738 */ "WHILE_LOOP_EG\0" /* 2752 */ "POP_EG\0" /* 2759 */ "CF_CALL_FS_EG\0" /* 2773 */ "G_ATOMIC_CMPXCHG\0" /* 2790 */ "LDS_WRXCHG\0" /* 2801 */ "G_ATOMICRMW_XCHG\0" /* 2818 */ "G_FLOG\0" /* 2825 */ "G_VAARG\0" /* 2833 */ "PREALLOCATED_ARG\0" /* 2850 */ "TEX_SAMPLE_C_G\0" /* 2865 */ "TEX_SAMPLE_G\0" /* 2878 */ "BRANCH\0" /* 2885 */ "G_PREFETCH\0" /* 2896 */ "ENDSWITCH\0" /* 2906 */ "G_SMULH\0" /* 2914 */ "G_UMULH\0" /* 2922 */ "G_FTANH\0" /* 2930 */ "G_FSINH\0" /* 2938 */ "G_FCOSH\0" /* 2946 */ "TEX_GET_GRADIENTS_H\0" /* 2966 */ "TEX_SET_GRADIENTS_H\0" /* 2986 */ "DBG_PHI\0" /* 2994 */ "G_FPTOSI\0" /* 3003 */ "G_FPTOUI\0" /* 3012 */ "G_FPOWI\0" /* 3020 */ "CF_ALU_BREAK\0" /* 3033 */ "G_PTRMASK\0" /* 3043 */ "GC_LABEL\0" /* 3052 */ "DBG_LABEL\0" /* 3062 */ "EH_LABEL\0" /* 3071 */ "ANNOTATION_LABEL\0" /* 3088 */ "ICALL_BRANCH_FUNNEL\0" /* 3108 */ "G_FSHL\0" /* 3115 */ "G_SHL\0" /* 3121 */ "G_FCEIL\0" /* 3129 */ "PATCHABLE_TAIL_CALL\0" /* 3149 */ "PATCHABLE_TYPED_EVENT_CALL\0" /* 3176 */ "PATCHABLE_EVENT_CALL\0" /* 3197 */ "FENTRY_CALL\0" /* 3209 */ "KILL\0" /* 3214 */ "G_CONSTANT_POOL\0" /* 3230 */ "G_ROTL\0" /* 3237 */ "G_VECREDUCE_FMUL\0" /* 3254 */ "G_FMUL\0" /* 3261 */ "G_VECREDUCE_SEQ_FMUL\0" /* 3282 */ "G_STRICT_FMUL\0" /* 3296 */ "G_VECREDUCE_MUL\0" /* 3312 */ "G_MUL\0" /* 3318 */ "TEX_SAMPLE_C_L\0" /* 3333 */ "TEX_SAMPLE_L\0" /* 3346 */ "CF_END_CM\0" /* 3356 */ "G_FREM\0" /* 3363 */ "G_STRICT_FREM\0" /* 3377 */ "G_SREM\0" /* 3384 */ "G_UREM\0" /* 3391 */ "G_SDIVREM\0" /* 3401 */ "G_UDIVREM\0" /* 3411 */ "INLINEASM\0" /* 3421 */ "G_VECREDUCE_FMINIMUM\0" /* 3442 */ "G_FMINIMUM\0" /* 3453 */ "G_VECREDUCE_FMAXIMUM\0" /* 3474 */ "G_FMAXIMUM\0" /* 3485 */ "G_FMINNUM\0" /* 3495 */ "G_FMAXNUM\0" /* 3505 */ "G_FATAN\0" /* 3513 */ "G_FTAN\0" /* 3520 */ "G_INTRINSIC_ROUNDEVEN\0" /* 3542 */ "G_ASSERT_ALIGN\0" /* 3557 */ "G_FCOPYSIGN\0" /* 3569 */ "DUMMY_CHAIN\0" /* 3581 */ "ENDMAIN\0" /* 3589 */ "G_VECREDUCE_FMIN\0" /* 3606 */ "G_ATOMICRMW_FMIN\0" /* 3623 */ "G_VECREDUCE_SMIN\0" /* 3640 */ "G_SMIN\0" /* 3647 */ "G_VECREDUCE_UMIN\0" /* 3664 */ "G_UMIN\0" /* 3671 */ "G_ATOMICRMW_UMIN\0" /* 3688 */ "G_ATOMICRMW_MIN\0" /* 3704 */ "G_FASIN\0" /* 3712 */ "G_FSIN\0" /* 3719 */ "CFI_INSTRUCTION\0" /* 3735 */ "RETURN\0" /* 3742 */ "RAT_ATOMIC_RSUB_RTN\0" /* 3762 */ "RAT_ATOMIC_SUB_RTN\0" /* 3781 */ "RAT_ATOMIC_ADD_RTN\0" /* 3800 */ "RAT_ATOMIC_AND_RTN\0" /* 3819 */ "RAT_ATOMIC_XOR_RTN\0" /* 3838 */ "RAT_ATOMIC_OR_RTN\0" /* 3856 */ "RAT_ATOMIC_DEC_UINT_RTN\0" /* 3880 */ "RAT_ATOMIC_INC_UINT_RTN\0" /* 3904 */ "RAT_ATOMIC_MIN_UINT_RTN\0" /* 3928 */ "RAT_ATOMIC_MAX_UINT_RTN\0" /* 3952 */ "RAT_ATOMIC_CMPXCHG_INT_RTN\0" /* 3979 */ "RAT_ATOMIC_XCHG_INT_RTN\0" /* 4003 */ "RAT_ATOMIC_MIN_INT_RTN\0" /* 4026 */ "RAT_ATOMIC_MAX_INT_RTN\0" /* 4049 */ "RETDYN\0" /* 4056 */ "G_SSUBO\0" /* 4064 */ "G_USUBO\0" /* 4072 */ "G_SADDO\0" /* 4080 */ "G_UADDO\0" /* 4088 */ "TEX_GET_TEXTURE_RESINFO\0" /* 4112 */ "JUMP_TABLE_DEBUG_INFO\0" /* 4134 */ "G_SMULO\0" /* 4142 */ "G_UMULO\0" /* 4150 */ "G_BZERO\0" /* 4158 */ "STACKMAP\0" /* 4167 */ "G_DEBUGTRAP\0" /* 4179 */ "G_UBSANTRAP\0" /* 4191 */ "G_TRAP\0" /* 4198 */ "G_ATOMICRMW_UDEC_WRAP\0" /* 4220 */ "G_ATOMICRMW_UINC_WRAP\0" /* 4242 */ "G_BSWAP\0" /* 4250 */ "G_SITOFP\0" /* 4259 */ "G_UITOFP\0" /* 4268 */ "G_FCMP\0" /* 4275 */ "G_ICMP\0" /* 4282 */ "G_SCMP\0" /* 4289 */ "G_UCMP\0" /* 4296 */ "JUMP\0" /* 4301 */ "ENDLOOP\0" /* 4309 */ "WHILELOOP\0" /* 4319 */ "CONVERGENCECTRL_LOOP\0" /* 4340 */ "G_CTPOP\0" /* 4348 */ "PATCHABLE_OP\0" /* 4361 */ "FAULTING_OP\0" /* 4373 */ "PREALLOCATED_SETUP\0" /* 4392 */ "G_FLDEXP\0" /* 4401 */ "G_STRICT_FLDEXP\0" /* 4417 */ "G_FEXP\0" /* 4424 */ "G_FFREXP\0" /* 4433 */ "G_BR\0" /* 4438 */ "INLINEASM_BR\0" /* 4451 */ "G_BLOCK_ADDR\0" /* 4464 */ "MOV_IMM_GLOBAL_ADDR\0" /* 4484 */ "MEMBARRIER\0" /* 4495 */ "G_CONSTANT_FOLD_BARRIER\0" /* 4519 */ "GROUP_BARRIER\0" /* 4533 */ "CF_ALU_ELSE_AFTER\0" /* 4551 */ "CF_ALU_POP_AFTER\0" /* 4568 */ "PATCHABLE_FUNCTION_ENTER\0" /* 4593 */ "G_READCYCLECOUNTER\0" /* 4612 */ "G_READSTEADYCOUNTER\0" /* 4632 */ "G_READ_REGISTER\0" /* 4648 */ "G_WRITE_REGISTER\0" /* 4665 */ "G_ASHR\0" /* 4672 */ "G_FSHR\0" /* 4679 */ "G_LSHR\0" /* 4686 */ "CONVERGENCECTRL_ANCHOR\0" /* 4709 */ "RAT_MSKOR\0" /* 4719 */ "G_FFLOOR\0" /* 4728 */ "G_EXTRACT_SUBVECTOR\0" /* 4748 */ "G_INSERT_SUBVECTOR\0" /* 4767 */ "G_BUILD_VECTOR\0" /* 4782 */ "G_SHUFFLE_VECTOR\0" /* 4799 */ "G_SPLAT_VECTOR\0" /* 4814 */ "G_VECREDUCE_XOR\0" /* 4830 */ "G_XOR\0" /* 4836 */ "LDS_XOR\0" /* 4844 */ "G_ATOMICRMW_XOR\0" /* 4860 */ "G_VECREDUCE_OR\0" /* 4875 */ "G_OR\0" /* 4880 */ "LDS_OR\0" /* 4887 */ "G_ATOMICRMW_OR\0" /* 4902 */ "G_ROTR\0" /* 4909 */ "TEX_LDPTR\0" /* 4919 */ "G_INTTOPTR\0" /* 4930 */ "G_FABS\0" /* 4937 */ "G_ABS\0" /* 4943 */ "G_UNMERGE_VALUES\0" /* 4960 */ "G_MERGE_VALUES\0" /* 4975 */ "LITERALS\0" /* 4984 */ "G_FACOS\0" /* 4992 */ "G_FCOS\0" /* 4999 */ "G_CONCAT_VECTORS\0" /* 5016 */ "COPY_TO_REGCLASS\0" /* 5033 */ "G_IS_FPCLASS\0" /* 5046 */ "G_ATOMIC_CMPXCHG_WITH_SUCCESS\0" /* 5076 */ "G_VECTOR_COMPRESS\0" /* 5094 */ "G_INTRINSIC_W_SIDE_EFFECTS\0" /* 5121 */ "G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS\0" /* 5159 */ "G_SSUBSAT\0" /* 5169 */ "G_USUBSAT\0" /* 5179 */ "G_SADDSAT\0" /* 5189 */ "G_UADDSAT\0" /* 5199 */ "G_SSHLSAT\0" /* 5209 */ "G_USHLSAT\0" /* 5219 */ "G_SMULFIXSAT\0" /* 5232 */ "G_UMULFIXSAT\0" /* 5245 */ "G_SDIVFIXSAT\0" /* 5258 */ "G_UDIVFIXSAT\0" /* 5271 */ "FRACT\0" /* 5277 */ "G_EXTRACT\0" /* 5287 */ "G_SELECT\0" /* 5296 */ "G_BRINDIRECT\0" /* 5309 */ "RAT_ATOMIC_RSUB_NORET\0" /* 5331 */ "RAT_ATOMIC_SUB_NORET\0" /* 5352 */ "RAT_ATOMIC_ADD_NORET\0" /* 5373 */ "RAT_ATOMIC_AND_NORET\0" /* 5394 */ "RAT_ATOMIC_XOR_NORET\0" /* 5415 */ "RAT_ATOMIC_OR_NORET\0" /* 5435 */ "RAT_ATOMIC_DEC_UINT_NORET\0" /* 5461 */ "RAT_ATOMIC_INC_UINT_NORET\0" /* 5487 */ "RAT_ATOMIC_MIN_UINT_NORET\0" /* 5513 */ "RAT_ATOMIC_MAX_UINT_NORET\0" /* 5539 */ "RAT_ATOMIC_CMPXCHG_INT_NORET\0" /* 5568 */ "RAT_ATOMIC_XCHG_INT_NORET\0" /* 5594 */ "RAT_ATOMIC_MIN_INT_NORET\0" /* 5619 */ "RAT_ATOMIC_MAX_INT_NORET\0" /* 5644 */ "LDS_SUB_RET\0" /* 5656 */ "LDS_UBYTE_READ_RET\0" /* 5675 */ "LDS_BYTE_READ_RET\0" /* 5693 */ "LDS_READ_RET\0" /* 5706 */ "LDS_USHORT_READ_RET\0" /* 5726 */ "LDS_SHORT_READ_RET\0" /* 5745 */ "LDS_ADD_RET\0" /* 5757 */ "LDS_AND_RET\0" /* 5769 */ "PATCHABLE_RET\0" /* 5783 */ "LDS_WRXCHG_RET\0" /* 5798 */ "LDS_XOR_RET\0" /* 5810 */ "LDS_OR_RET\0" /* 5821 */ "LDS_MIN_UINT_RET\0" /* 5838 */ "LDS_MAX_UINT_RET\0" /* 5855 */ "LDS_MIN_INT_RET\0" /* 5871 */ "LDS_MAX_INT_RET\0" /* 5887 */ "LDS_CMPST_RET\0" /* 5901 */ "G_MEMSET\0" /* 5910 */ "IF_PREDICATE_SET\0" /* 5927 */ "KILLGT\0" /* 5934 */ "SGT\0" /* 5938 */ "PRED_SETGT\0" /* 5949 */ "PATCHABLE_FUNCTION_EXIT\0" /* 5973 */ "G_BRJT\0" /* 5980 */ "G_EXTRACT_VECTOR_ELT\0" /* 6001 */ "G_INSERT_VECTOR_ELT\0" /* 6021 */ "DEFAULT\0" /* 6029 */ "G_FCONSTANT\0" /* 6041 */ "G_CONSTANT\0" /* 6052 */ "G_INTRINSIC_CONVERGENT\0" /* 6075 */ "STATEPOINT\0" /* 6086 */ "PATCHPOINT\0" /* 6097 */ "G_PTRTOINT\0" /* 6108 */ "G_FRINT\0" /* 6116 */ "G_INTRINSIC_LLRINT\0" /* 6135 */ "G_INTRINSIC_LRINT\0" /* 6153 */ "SUBB_UINT\0" /* 6163 */ "ADDC_UINT\0" /* 6173 */ "SETGE_UINT\0" /* 6184 */ "FFBH_UINT\0" /* 6194 */ "LDS_MIN_UINT\0" /* 6207 */ "SETGT_UINT\0" /* 6218 */ "LDS_MAX_UINT\0" /* 6231 */ "G_FNEARBYINT\0" /* 6244 */ "SUB_INT\0" /* 6252 */ "ADD_INT\0" /* 6260 */ "AND_INT\0" /* 6268 */ "CNDE_INT\0" /* 6277 */ "CNDGE_INT\0" /* 6287 */ "PRED_SETGE_INT\0" /* 6302 */ "PRED_SETNE_INT\0" /* 6317 */ "PRED_SETE_INT\0" /* 6331 */ "FFBL_INT\0" /* 6340 */ "LDS_MIN_INT\0" /* 6352 */ "XOR_INT\0" /* 6360 */ "CNDGT_INT\0" /* 6370 */ "PRED_SETGT_INT\0" /* 6385 */ "BCNT_INT\0" /* 6394 */ "NOT_INT\0" /* 6402 */ "LDS_MAX_INT\0" /* 6414 */ "G_VASTART\0" /* 6424 */ "LIFETIME_START\0" /* 6439 */ "G_INVOKE_REGION_START\0" /* 6461 */ "G_INSERT\0" /* 6470 */ "G_FSQRT\0" /* 6478 */ "G_STRICT_FSQRT\0" /* 6493 */ "G_BITCAST\0" /* 6503 */ "G_ADDRSPACE_CAST\0" /* 6520 */ "DBG_VALUE_LIST\0" /* 6535 */ "LDS_CMPST\0" /* 6545 */ "G_FPEXT\0" /* 6553 */ "G_SEXT\0" /* 6560 */ "G_ASSERT_SEXT\0" /* 6574 */ "G_ANYEXT\0" /* 6583 */ "G_ZEXT\0" /* 6590 */ "G_ASSERT_ZEXT\0" /* 6604 */ "CF_ALU\0" /* 6611 */ "G_FDIV\0" /* 6618 */ "G_STRICT_FDIV\0" /* 6632 */ "G_SDIV\0" /* 6639 */ "G_UDIV\0" /* 6646 */ "G_GET_FPENV\0" /* 6658 */ "G_RESET_FPENV\0" /* 6672 */ "G_SET_FPENV\0" /* 6684 */ "MOV\0" /* 6688 */ "TEX_GET_GRADIENTS_V\0" /* 6708 */ "TEX_SET_GRADIENTS_V\0" /* 6728 */ "TXD_SHADOW\0" /* 6739 */ "G_FPOW\0" /* 6746 */ "INTERP_ZW\0" /* 6756 */ "INTERP_PAIR_ZW\0" /* 6771 */ "G_VECREDUCE_FMAX\0" /* 6788 */ "G_ATOMICRMW_FMAX\0" /* 6805 */ "G_VECREDUCE_SMAX\0" /* 6822 */ "G_SMAX\0" /* 6829 */ "G_VECREDUCE_UMAX\0" /* 6846 */ "G_UMAX\0" /* 6853 */ "G_ATOMICRMW_UMAX\0" /* 6870 */ "G_ATOMICRMW_MAX\0" /* 6886 */ "G_FRAME_INDEX\0" /* 6900 */ "G_SBFX\0" /* 6907 */ "G_UBFX\0" /* 6914 */ "G_SMULFIX\0" /* 6924 */ "G_UMULFIX\0" /* 6934 */ "G_SDIVFIX\0" /* 6944 */ "G_UDIVFIX\0" /* 6954 */ "PRED_X\0" /* 6961 */ "G_MEMCPY\0" /* 6970 */ "CONST_COPY\0" /* 6981 */ "CONVERGENCECTRL_ENTRY\0" /* 7003 */ "INTERP_XY\0" /* 7013 */ "INTERP_PAIR_XY\0" /* 7028 */ "G_CTLZ\0" /* 7035 */ "G_CTTZ\0" /* 7042 */ "R600_RegisterLoad\0" /* 7060 */ "R600_RegisterStore\0" /* 7079 */ "R600_ExportBuf\0" /* 7094 */ "EG_ExportBuf\0" /* 7107 */ "VTX_READ_32_eg\0" /* 7122 */ "RAT_WRITE_CACHELESS_32_eg\0" /* 7148 */ "MULADD_UINT24_eg\0" /* 7165 */ "MULHI_UINT24_eg\0" /* 7181 */ "MUL_UINT24_eg\0" /* 7195 */ "VTX_READ_64_eg\0" /* 7210 */ "RAT_WRITE_CACHELESS_64_eg\0" /* 7236 */ "DOT4_eg\0" /* 7244 */ "VTX_READ_16_eg\0" /* 7259 */ "VTX_READ_128_eg\0" /* 7275 */ "RAT_WRITE_CACHELESS_128_eg\0" /* 7302 */ "VTX_READ_8_eg\0" /* 7316 */ "FMA_eg\0" /* 7323 */ "MULADD_eg\0" /* 7333 */ "LOG_CLAMPED_eg\0" /* 7348 */ "RECIP_CLAMPED_eg\0" /* 7365 */ "RECIPSQRT_CLAMPED_eg\0" /* 7386 */ "RAT_STORE_TYPED_eg\0" /* 7405 */ "CNDE_eg\0" /* 7413 */ "MULADD_IEEE_eg\0" /* 7428 */ "LOG_IEEE_eg\0" /* 7440 */ "RECIP_IEEE_eg\0" /* 7454 */ "EXP_IEEE_eg\0" /* 7466 */ "RECIPSQRT_IEEE_eg\0" /* 7484 */ "CNDGE_eg\0" /* 7493 */ "LSHL_eg\0" /* 7501 */ "SIN_eg\0" /* 7508 */ "ASHR_eg\0" /* 7516 */ "LSHR_eg\0" /* 7524 */ "COS_eg\0" /* 7531 */ "CNDGT_eg\0" /* 7540 */ "MUL_LIT_eg\0" /* 7551 */ "UINT_TO_FLT_eg\0" /* 7566 */ "BFE_UINT_eg\0" /* 7578 */ "MULHI_UINT_eg\0" /* 7592 */ "MULLO_UINT_eg\0" /* 7606 */ "FLT_TO_UINT_eg\0" /* 7621 */ "RECIP_UINT_eg\0" /* 7635 */ "MOVA_INT_eg\0" /* 7647 */ "BFE_INT_eg\0" /* 7658 */ "BFI_INT_eg\0" /* 7669 */ "MULHI_INT_eg\0" /* 7682 */ "BFM_INT_eg\0" /* 7693 */ "BIT_ALIGN_INT_eg\0" /* 7710 */ "MULLO_INT_eg\0" /* 7723 */ "FLT_TO_INT_eg\0" /* 7737 */ "CUBE_r600_real\0" /* 7752 */ "CUBE_eg_real\0" /* 7765 */ "VTX_READ_32_cm\0" /* 7780 */ "MULADD_INT24_cm\0" /* 7796 */ "MUL_INT24_cm\0" /* 7809 */ "VTX_READ_64_cm\0" /* 7824 */ "VTX_READ_16_cm\0" /* 7839 */ "VTX_READ_128_cm\0" /* 7855 */ "VTX_READ_8_cm\0" /* 7869 */ "RECIP_CLAMPED_cm\0" /* 7886 */ "RECIPSQRT_CLAMPED_cm\0" /* 7907 */ "RAT_STORE_TYPED_cm\0" /* 7926 */ "LOG_IEEE_cm\0" /* 7938 */ "RECIP_IEEE_cm\0" /* 7952 */ "EXP_IEEE_cm\0" /* 7964 */ "RECIPSQRT_IEEE_cm\0" /* 7982 */ "SIN_cm\0" /* 7989 */ "COS_cm\0" /* 7996 */ "MULHI_UINT_cm\0" /* 8010 */ "MULLO_UINT_cm\0" /* 8024 */ "MULHI_INT_cm\0" /* 8037 */ "MULLO_INT_cm\0" /* 8050 */ "CUBE_r600_pseudo\0" /* 8067 */ "CUBE_eg_pseudo\0" /* 8082 */ "R600_ExportSwz\0" /* 8097 */ "EG_ExportSwz\0" }; #ifdef __GNUC__ #pragma GCC diagnostic pop #endif extern const unsigned R600InstrNameIndices[] = { 2990U, 3411U, 4438U, 3719U, 3062U, 3043U, 3071U, 3209U, 2580U, 2595U, 2508U, 2622U, 5016U, 2338U, 6520U, 2521U, 2986U, 3052U, 1953U, 6976U, 2099U, 6424U, 1788U, 1904U, 1941U, 4158U, 3197U, 6086U, 1883U, 4373U, 2833U, 6075U, 2154U, 4361U, 4348U, 4568U, 5769U, 5949U, 3129U, 3176U, 3149U, 3088U, 2267U, 4484U, 4112U, 6981U, 4686U, 4319U, 2386U, 6560U, 6590U, 3542U, 1678U, 1340U, 3312U, 6632U, 6639U, 3377U, 3384U, 3391U, 3401U, 1758U, 4875U, 4830U, 2506U, 2988U, 6886U, 2348U, 2363U, 3214U, 5277U, 4943U, 6461U, 4960U, 4767U, 1426U, 4999U, 6097U, 4919U, 6493U, 2445U, 4495U, 1857U, 1400U, 1839U, 6135U, 6116U, 3520U, 4593U, 4612U, 1575U, 1503U, 1533U, 1560U, 1484U, 1514U, 2217U, 2201U, 5046U, 2773U, 2801U, 1702U, 1354U, 1772U, 1725U, 4887U, 4844U, 6870U, 3688U, 6853U, 3671U, 1645U, 1323U, 6788U, 3606U, 4220U, 4198U, 1933U, 2885U, 1801U, 5296U, 6439U, 1370U, 5094U, 6052U, 5121U, 6574U, 1418U, 6041U, 6029U, 6414U, 2825U, 6553U, 2609U, 6583U, 3115U, 4679U, 4665U, 3108U, 4672U, 4902U, 3230U, 4275U, 4268U, 4282U, 4289U, 5287U, 4080U, 1974U, 4064U, 1925U, 4072U, 1966U, 4056U, 1917U, 4142U, 4134U, 2914U, 2906U, 5189U, 5179U, 5169U, 5159U, 5209U, 5199U, 6914U, 6924U, 5219U, 5232U, 6934U, 6944U, 5245U, 5258U, 1603U, 1302U, 3254U, 1253U, 1477U, 6611U, 3356U, 6739U, 3012U, 4417U, 1078U, 596U, 2818U, 1070U, 587U, 4392U, 4424U, 2573U, 6545U, 1390U, 2994U, 3003U, 4250U, 4259U, 4930U, 3557U, 5033U, 2454U, 3485U, 3495U, 2032U, 2047U, 3442U, 3474U, 6646U, 6672U, 6658U, 1982U, 2010U, 1995U, 1684U, 3033U, 3640U, 6822U, 3664U, 6846U, 4937U, 1830U, 1820U, 4433U, 5973U, 2077U, 4748U, 4728U, 6001U, 5980U, 4782U, 4799U, 5076U, 7035U, 2488U, 7028U, 2470U, 4340U, 4242U, 2230U, 3121U, 4992U, 3712U, 3513U, 4984U, 3704U, 3505U, 2938U, 2930U, 2922U, 6470U, 4719U, 6108U, 6231U, 6503U, 4451U, 2086U, 1447U, 2423U, 2186U, 1631U, 1309U, 3282U, 6618U, 3363U, 1259U, 6478U, 4401U, 4632U, 4648U, 6961U, 2123U, 2435U, 5901U, 4150U, 4191U, 4167U, 4179U, 1610U, 3261U, 1586U, 3237U, 6771U, 3589U, 3453U, 3421U, 1662U, 3296U, 1742U, 4860U, 4814U, 6805U, 3623U, 6829U, 3647U, 6900U, 6907U, 2878U, 771U, 937U, 3027U, 760U, 926U, 884U, 1050U, 825U, 991U, 6970U, 2414U, 738U, 904U, 844U, 1010U, 787U, 953U, 8067U, 8050U, 6021U, 1213U, 3569U, 2225U, 1797U, 1382U, 2535U, 4301U, 3581U, 2896U, 160U, 82U, 1385U, 752U, 918U, 867U, 1033U, 809U, 975U, 5910U, 4296U, 1810U, 2301U, 699U, 4464U, 711U, 6954U, 1086U, 1174U, 1106U, 1194U, 7042U, 7060U, 4049U, 3735U, 1900U, 6728U, 4309U, 1599U, 6163U, 6252U, 2256U, 6260U, 7508U, 388U, 6385U, 7647U, 7566U, 7658U, 7682U, 7693U, 3124U, 6604U, 3020U, 2407U, 4533U, 4551U, 2167U, 2759U, 170U, 2675U, 65U, 2664U, 34U, 3346U, 2654U, 22U, 2715U, 108U, 2690U, 47U, 2636U, 0U, 2645U, 11U, 6268U, 7405U, 267U, 6277U, 7484U, 358U, 6360U, 7531U, 417U, 7989U, 7524U, 408U, 578U, 7752U, 7737U, 7236U, 186U, 7094U, 8097U, 2726U, 121U, 7952U, 7454U, 324U, 2243U, 6184U, 6331U, 4722U, 723U, 1219U, 7723U, 553U, 7606U, 490U, 7316U, 5271U, 4519U, 666U, 7013U, 6756U, 1544U, 7003U, 6746U, 7552U, 442U, 5927U, 1694U, 5745U, 1764U, 5757U, 5675U, 2286U, 6535U, 5887U, 6402U, 5871U, 6218U, 5838U, 6340U, 5855U, 6194U, 5821U, 4880U, 5810U, 5693U, 5726U, 2322U, 1346U, 5644U, 5656U, 5706U, 2312U, 2790U, 5783U, 4836U, 5798U, 4975U, 7333U, 208U, 7926U, 7428U, 294U, 2701U, 92U, 7493U, 369U, 7516U, 398U, 6784U, 657U, 6406U, 6222U, 3602U, 637U, 6344U, 6198U, 6684U, 7635U, 3250U, 7413U, 277U, 7780U, 7148U, 7323U, 196U, 8024U, 1141U, 7669U, 523U, 7165U, 7996U, 1125U, 7578U, 458U, 8037U, 7710U, 538U, 8010U, 7592U, 474U, 2023U, 7796U, 7540U, 428U, 7181U, 6394U, 6353U, 1582U, 2752U, 151U, 2276U, 6317U, 2066U, 6287U, 5938U, 6370U, 2143U, 6302U, 7079U, 8082U, 5352U, 3781U, 5373U, 3800U, 5539U, 3952U, 5435U, 3856U, 5461U, 3880U, 5619U, 4026U, 5513U, 3928U, 5594U, 4003U, 5487U, 3904U, 5415U, 3838U, 5309U, 3742U, 5331U, 3762U, 5568U, 3979U, 5394U, 3819U, 4709U, 1234U, 681U, 1156U, 7907U, 7386U, 7275U, 7122U, 7210U, 7886U, 7365U, 244U, 7964U, 7466U, 338U, 7869U, 7348U, 225U, 7938U, 7440U, 308U, 7621U, 507U, 2117U, 2281U, 627U, 6322U, 605U, 6292U, 6173U, 646U, 6375U, 6207U, 616U, 6307U, 2062U, 5934U, 7982U, 7501U, 379U, 569U, 2139U, 6153U, 6244U, 2946U, 6688U, 4088U, 1718U, 4909U, 2106U, 1464U, 2850U, 3318U, 1272U, 2865U, 3333U, 1288U, 2966U, 6708U, 2541U, 2558U, 1394U, 7551U, 441U, 7839U, 7259U, 7824U, 7244U, 7765U, 7107U, 7809U, 7195U, 7855U, 7302U, 2738U, 135U, 6352U, }; static inline void InitR600MCInstrInfo(MCInstrInfo *II) { II->InitMCInstrInfo(R600Descs.Insts, R600InstrNameIndices, R600InstrNameData, nullptr, nullptr, 636); } } // end namespace llvm #endif // GET_INSTRINFO_MC_DESC #ifdef GET_INSTRINFO_HEADER #undef GET_INSTRINFO_HEADER namespace llvm { struct R600GenInstrInfo : public TargetInstrInfo { explicit R600GenInstrInfo(unsigned CFSetupOpcode = ~0u, unsigned CFDestroyOpcode = ~0u, unsigned CatchRetOpcode = ~0u, unsigned ReturnOpcode = ~0u); ~R600GenInstrInfo() override = default; }; } // end namespace llvm #endif // GET_INSTRINFO_HEADER #ifdef GET_INSTRINFO_HELPER_DECLS #undef GET_INSTRINFO_HELPER_DECLS #endif // GET_INSTRINFO_HELPER_DECLS #ifdef GET_INSTRINFO_HELPERS #undef GET_INSTRINFO_HELPERS #endif // GET_INSTRINFO_HELPERS #ifdef GET_INSTRINFO_CTOR_DTOR #undef GET_INSTRINFO_CTOR_DTOR namespace llvm { extern const R600InstrTable R600Descs; extern const unsigned R600InstrNameIndices[]; extern const char R600InstrNameData[]; R600GenInstrInfo::R600GenInstrInfo(unsigned CFSetupOpcode, unsigned CFDestroyOpcode, unsigned CatchRetOpcode, unsigned ReturnOpcode) : TargetInstrInfo(CFSetupOpcode, CFDestroyOpcode, CatchRetOpcode, ReturnOpcode) { InitMCInstrInfo(R600Descs.Insts, R600InstrNameIndices, R600InstrNameData, nullptr, nullptr, 636); } } // end namespace llvm #endif // GET_INSTRINFO_CTOR_DTOR #ifdef GET_INSTRINFO_OPERAND_ENUM #undef GET_INSTRINFO_OPERAND_ENUM namespace llvm { namespace R600 { namespace OpName { enum { … }; } // end namespace OpName } // end namespace R600 } // end namespace llvm #endif //GET_INSTRINFO_OPERAND_ENUM #ifdef GET_INSTRINFO_NAMED_OPS #undef GET_INSTRINFO_NAMED_OPS namespace llvm { namespace R600 { LLVM_READONLY int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx) { static const int16_t OperandMap [][107] = { {0, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, }, {0, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 2, -1, 3, 4, -1, 5, -1, 6, 7, 8, -1, 9, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, }, {0, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 2, -1, 3, 4, -1, 5, -1, 6, 10, 11, -1, 12, 7, -1, 8, 9, -1, -1, -1, -1, -1, -1, -1, -1, -1, }, {0, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 2, -1, 3, -1, -1, -1, -1, -1, 4, 5, -1, 6, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, }, {0, 3, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1, 2, 4, 5, -1, 6, 7, 8, 9, -1, 10, 15, 16, 17, 18, 11, 12, 13, 14, -1, -1, -1, -1, -1, -1, -1, -1, -1, }, {0, 5, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1, 2, 3, 4, 6, 7, 8, 9, -1, -1, -1, -1, -1, 10, 11, 12, 13, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, }, {0, 7, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1, 2, 3, 4, 5, 6, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, }, {0, -1, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, }, {0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1, 3, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, }, {-1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1, -1, 2, 3, -1, 4, -1, 5, 6, 7, -1, 8, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, }, {-1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1, -1, 2, 3, -1, 4, -1, 5, 9, 10, -1, 11, 6, -1, 7, 8, -1, -1, -1, -1, -1, -1, -1, -1, -1, }, {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1, 3, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, }, {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, 1, 2, 3, 4, 5, 6, 7, 8, }, }; switch(Opcode) { case R600::CUBE_eg_pseudo: case R600::CUBE_r600_pseudo: return OperandMap[0][NamedIdx]; case R600::LDS_ADD_RET: case R600::LDS_AND_RET: case R600::LDS_MAX_INT_RET: case R600::LDS_MAX_UINT_RET: case R600::LDS_MIN_INT_RET: case R600::LDS_MIN_UINT_RET: case R600::LDS_OR_RET: case R600::LDS_SUB_RET: case R600::LDS_WRXCHG_RET: case R600::LDS_XOR_RET: return OperandMap[1][NamedIdx]; case R600::LDS_CMPST_RET: return OperandMap[2][NamedIdx]; case R600::LDS_BYTE_READ_RET: case R600::LDS_READ_RET: case R600::LDS_SHORT_READ_RET: case R600::LDS_UBYTE_READ_RET: case R600::LDS_USHORT_READ_RET: return OperandMap[3][NamedIdx]; case R600::BFE_INT_eg: case R600::BFE_UINT_eg: case R600::BFI_INT_eg: case R600::BIT_ALIGN_INT_eg: case R600::CNDE_INT: case R600::CNDE_eg: case R600::CNDE_r600: case R600::CNDGE_INT: case R600::CNDGE_eg: case R600::CNDGE_r600: case R600::CNDGT_INT: case R600::CNDGT_eg: case R600::CNDGT_r600: case R600::FMA_eg: case R600::MULADD_IEEE_eg: case R600::MULADD_IEEE_r600: case R600::MULADD_INT24_cm: case R600::MULADD_UINT24_eg: case R600::MULADD_eg: case R600::MULADD_r600: case R600::MUL_LIT_eg: case R600::MUL_LIT_r600: return OperandMap[4][NamedIdx]; case R600::BCNT_INT: case R600::CEIL: case R600::COS_cm: case R600::COS_eg: case R600::COS_r600: case R600::COS_r700: case R600::EXP_IEEE_cm: case R600::EXP_IEEE_eg: case R600::EXP_IEEE_r600: case R600::FFBH_UINT: case R600::FFBL_INT: case R600::FLOOR: case R600::FLT16_TO_FLT32: case R600::FLT32_TO_FLT16: case R600::FLT_TO_INT_eg: case R600::FLT_TO_INT_r600: case R600::FLT_TO_UINT_eg: case R600::FLT_TO_UINT_r600: case R600::FRACT: case R600::INTERP_LOAD_P0: case R600::INT_TO_FLT_eg: case R600::INT_TO_FLT_r600: case R600::LOG_CLAMPED_eg: case R600::LOG_CLAMPED_r600: case R600::LOG_IEEE_cm: case R600::LOG_IEEE_eg: case R600::LOG_IEEE_r600: case R600::MOV: case R600::MOVA_INT_eg: case R600::NOT_INT: case R600::RECIPSQRT_CLAMPED_cm: case R600::RECIPSQRT_CLAMPED_eg: case R600::RECIPSQRT_CLAMPED_r600: case R600::RECIPSQRT_IEEE_cm: case R600::RECIPSQRT_IEEE_eg: case R600::RECIPSQRT_IEEE_r600: case R600::RECIP_CLAMPED_cm: case R600::RECIP_CLAMPED_eg: case R600::RECIP_CLAMPED_r600: case R600::RECIP_IEEE_cm: case R600::RECIP_IEEE_eg: case R600::RECIP_IEEE_r600: case R600::RECIP_UINT_eg: case R600::RECIP_UINT_r600: case R600::RNDNE: case R600::SIN_cm: case R600::SIN_eg: case R600::SIN_r600: case R600::SIN_r700: case R600::TRUNC: case R600::UINT_TO_FLT_eg: case R600::UINT_TO_FLT_r600: return OperandMap[5][NamedIdx]; case R600::ADD: case R600::ADDC_UINT: case R600::ADD_INT: case R600::AND_INT: case R600::ASHR_eg: case R600::ASHR_r600: case R600::BFM_INT_eg: case R600::CUBE_eg_real: case R600::CUBE_r600_real: case R600::DOT4_eg: case R600::DOT4_r600: case R600::INTERP_XY: case R600::INTERP_ZW: case R600::KILLGT: case R600::LSHL_eg: case R600::LSHL_r600: case R600::LSHR_eg: case R600::LSHR_r600: case R600::MAX: case R600::MAX_DX10: case R600::MAX_INT: case R600::MAX_UINT: case R600::MIN: case R600::MIN_DX10: case R600::MIN_INT: case R600::MIN_UINT: case R600::MUL: case R600::MULHI_INT_cm: case R600::MULHI_INT_cm24: case R600::MULHI_INT_eg: case R600::MULHI_INT_r600: case R600::MULHI_UINT24_eg: case R600::MULHI_UINT_cm: case R600::MULHI_UINT_cm24: case R600::MULHI_UINT_eg: case R600::MULHI_UINT_r600: case R600::MULLO_INT_cm: case R600::MULLO_INT_eg: case R600::MULLO_INT_r600: case R600::MULLO_UINT_cm: case R600::MULLO_UINT_eg: case R600::MULLO_UINT_r600: case R600::MUL_IEEE: case R600::MUL_INT24_cm: case R600::MUL_UINT24_eg: case R600::OR_INT: case R600::PRED_SETE: case R600::PRED_SETE_INT: case R600::PRED_SETGE: case R600::PRED_SETGE_INT: case R600::PRED_SETGT: case R600::PRED_SETGT_INT: case R600::PRED_SETNE: case R600::PRED_SETNE_INT: case R600::SETE: case R600::SETE_DX10: case R600::SETE_INT: case R600::SETGE_DX10: case R600::SETGE_INT: case R600::SETGE_UINT: case R600::SETGT_DX10: case R600::SETGT_INT: case R600::SETGT_UINT: case R600::SETNE_DX10: case R600::SETNE_INT: case R600::SGE: case R600::SGT: case R600::SNE: case R600::SUBB_UINT: case R600::SUB_INT: case R600::XOR_INT: return OperandMap[6][NamedIdx]; case R600::DOT_4: return OperandMap[7][NamedIdx]; case R600::R600_RegisterLoad: return OperandMap[8][NamedIdx]; case R600::LDS_ADD: case R600::LDS_AND: case R600::LDS_BYTE_WRITE: case R600::LDS_MAX_INT: case R600::LDS_MAX_UINT: case R600::LDS_MIN_INT: case R600::LDS_MIN_UINT: case R600::LDS_OR: case R600::LDS_SHORT_WRITE: case R600::LDS_SUB: case R600::LDS_WRITE: case R600::LDS_WRXCHG: case R600::LDS_XOR: return OperandMap[9][NamedIdx]; case R600::LDS_CMPST: return OperandMap[10][NamedIdx]; case R600::R600_RegisterStore: return OperandMap[11][NamedIdx]; case R600::CF_ALU: case R600::CF_ALU_BREAK: case R600::CF_ALU_CONTINUE: case R600::CF_ALU_ELSE_AFTER: case R600::CF_ALU_POP_AFTER: case R600::CF_ALU_PUSH_BEFORE: return OperandMap[12][NamedIdx]; default: return -1; } } } // end namespace R600 } // end namespace llvm #endif //GET_INSTRINFO_NAMED_OPS #ifdef GET_INSTRINFO_OPERAND_TYPES_ENUM #undef GET_INSTRINFO_OPERAND_TYPES_ENUM namespace llvm { namespace R600 { namespace OpTypes { enum OperandType { ABS = 0, BANK_SWIZZLE = 1, CLAMP = 2, CT = 3, FRAMEri = 4, InstFlag = 5, KCACHE = 6, LAST = 7, LITERAL = 8, MEMrr = 9, MEMxi = 10, NEG = 11, OMOD = 12, R600_Pred = 13, REL = 14, RSel = 15, SEL = 16, UEM = 17, UP = 18, WRITE = 19, brtarget = 20, f32imm = 21, f64imm = 22, i1imm = 23, i1imm_0 = 24, i8imm = 25, i16imm = 26, i32imm = 27, i64imm = 28, ptype0 = 29, ptype1 = 30, ptype2 = 31, ptype3 = 32, ptype4 = 33, ptype5 = 34, s16imm = 35, type0 = 36, type1 = 37, type2 = 38, type3 = 39, type4 = 40, type5 = 41, u16imm = 42, untyped_imm_0 = 43, R600_Addr = 44, R600_Addr_W = 45, R600_Addr_Y = 46, R600_Addr_Z = 47, R600_ArrayBase = 48, R600_KC0 = 49, R600_KC0_W = 50, R600_KC0_X = 51, R600_KC0_Y = 52, R600_KC0_Z = 53, R600_KC1 = 54, R600_KC1_W = 55, R600_KC1_X = 56, R600_KC1_Y = 57, R600_KC1_Z = 58, R600_LDS_SRC_REG = 59, R600_Predicate = 60, R600_Predicate_Bit = 61, R600_Reg32 = 62, R600_Reg64 = 63, R600_Reg64Vertical = 64, R600_Reg128 = 65, R600_Reg128Vertical = 66, R600_TReg32 = 67, R600_TReg32_W = 68, R600_TReg32_X = 69, R600_TReg32_Y = 70, R600_TReg32_Z = 71, OPERAND_TYPE_LIST_END }; } // end namespace OpTypes } // end namespace R600 } // end namespace llvm #endif // GET_INSTRINFO_OPERAND_TYPES_ENUM #ifdef GET_INSTRINFO_OPERAND_TYPE #undef GET_INSTRINFO_OPERAND_TYPE namespace llvm { namespace R600 { LLVM_READONLY static int getOperandType(uint16_t Opcode, uint16_t OpIdx) { static const uint16_t Offsets[] = { /* PHI */ 0, /* INLINEASM */ 1, /* INLINEASM_BR */ 1, /* CFI_INSTRUCTION */ 1, /* EH_LABEL */ 2, /* GC_LABEL */ 3, /* ANNOTATION_LABEL */ 4, /* KILL */ 5, /* EXTRACT_SUBREG */ 5, /* INSERT_SUBREG */ 8, /* IMPLICIT_DEF */ 12, /* SUBREG_TO_REG */ 13, /* COPY_TO_REGCLASS */ 17, /* DBG_VALUE */ 20, /* DBG_VALUE_LIST */ 20, /* DBG_INSTR_REF */ 20, /* DBG_PHI */ 20, /* DBG_LABEL */ 20, /* REG_SEQUENCE */ 21, /* COPY */ 23, /* BUNDLE */ 25, /* LIFETIME_START */ 25, /* LIFETIME_END */ 26, /* PSEUDO_PROBE */ 27, /* ARITH_FENCE */ 31, /* STACKMAP */ 33, /* FENTRY_CALL */ 35, /* PATCHPOINT */ 35, /* LOAD_STACK_GUARD */ 41, /* PREALLOCATED_SETUP */ 42, /* PREALLOCATED_ARG */ 43, /* STATEPOINT */ 46, /* LOCAL_ESCAPE */ 46, /* FAULTING_OP */ 48, /* PATCHABLE_OP */ 49, /* PATCHABLE_FUNCTION_ENTER */ 49, /* PATCHABLE_RET */ 49, /* PATCHABLE_FUNCTION_EXIT */ 49, /* PATCHABLE_TAIL_CALL */ 49, /* PATCHABLE_EVENT_CALL */ 49, /* PATCHABLE_TYPED_EVENT_CALL */ 51, /* ICALL_BRANCH_FUNNEL */ 54, /* FAKE_USE */ 54, /* MEMBARRIER */ 54, /* JUMP_TABLE_DEBUG_INFO */ 54, /* CONVERGENCECTRL_ENTRY */ 55, /* CONVERGENCECTRL_ANCHOR */ 56, /* CONVERGENCECTRL_LOOP */ 57, /* CONVERGENCECTRL_GLUE */ 59, /* G_ASSERT_SEXT */ 60, /* G_ASSERT_ZEXT */ 63, /* G_ASSERT_ALIGN */ 66, /* G_ADD */ 69, /* G_SUB */ 72, /* G_MUL */ 75, /* G_SDIV */ 78, /* G_UDIV */ 81, /* G_SREM */ 84, /* G_UREM */ 87, /* G_SDIVREM */ 90, /* G_UDIVREM */ 94, /* G_AND */ 98, /* G_OR */ 101, /* G_XOR */ 104, /* G_IMPLICIT_DEF */ 107, /* G_PHI */ 108, /* G_FRAME_INDEX */ 109, /* G_GLOBAL_VALUE */ 111, /* G_PTRAUTH_GLOBAL_VALUE */ 113, /* G_CONSTANT_POOL */ 118, /* G_EXTRACT */ 120, /* G_UNMERGE_VALUES */ 123, /* G_INSERT */ 125, /* G_MERGE_VALUES */ 129, /* G_BUILD_VECTOR */ 131, /* G_BUILD_VECTOR_TRUNC */ 133, /* G_CONCAT_VECTORS */ 135, /* G_PTRTOINT */ 137, /* G_INTTOPTR */ 139, /* G_BITCAST */ 141, /* G_FREEZE */ 143, /* G_CONSTANT_FOLD_BARRIER */ 145, /* G_INTRINSIC_FPTRUNC_ROUND */ 147, /* G_INTRINSIC_TRUNC */ 150, /* G_INTRINSIC_ROUND */ 152, /* G_INTRINSIC_LRINT */ 154, /* G_INTRINSIC_LLRINT */ 156, /* G_INTRINSIC_ROUNDEVEN */ 158, /* G_READCYCLECOUNTER */ 160, /* G_READSTEADYCOUNTER */ 161, /* G_LOAD */ 162, /* G_SEXTLOAD */ 164, /* G_ZEXTLOAD */ 166, /* G_INDEXED_LOAD */ 168, /* G_INDEXED_SEXTLOAD */ 173, /* G_INDEXED_ZEXTLOAD */ 178, /* G_STORE */ 183, /* G_INDEXED_STORE */ 185, /* G_ATOMIC_CMPXCHG_WITH_SUCCESS */ 190, /* G_ATOMIC_CMPXCHG */ 195, /* G_ATOMICRMW_XCHG */ 199, /* G_ATOMICRMW_ADD */ 202, /* G_ATOMICRMW_SUB */ 205, /* G_ATOMICRMW_AND */ 208, /* G_ATOMICRMW_NAND */ 211, /* G_ATOMICRMW_OR */ 214, /* G_ATOMICRMW_XOR */ 217, /* G_ATOMICRMW_MAX */ 220, /* G_ATOMICRMW_MIN */ 223, /* G_ATOMICRMW_UMAX */ 226, /* G_ATOMICRMW_UMIN */ 229, /* G_ATOMICRMW_FADD */ 232, /* G_ATOMICRMW_FSUB */ 235, /* G_ATOMICRMW_FMAX */ 238, /* G_ATOMICRMW_FMIN */ 241, /* G_ATOMICRMW_UINC_WRAP */ 244, /* G_ATOMICRMW_UDEC_WRAP */ 247, /* G_FENCE */ 250, /* G_PREFETCH */ 252, /* G_BRCOND */ 256, /* G_BRINDIRECT */ 258, /* G_INVOKE_REGION_START */ 259, /* G_INTRINSIC */ 259, /* G_INTRINSIC_W_SIDE_EFFECTS */ 260, /* G_INTRINSIC_CONVERGENT */ 261, /* G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS */ 262, /* G_ANYEXT */ 263, /* G_TRUNC */ 265, /* G_CONSTANT */ 267, /* G_FCONSTANT */ 269, /* G_VASTART */ 271, /* G_VAARG */ 272, /* G_SEXT */ 275, /* G_SEXT_INREG */ 277, /* G_ZEXT */ 280, /* G_SHL */ 282, /* G_LSHR */ 285, /* G_ASHR */ 288, /* G_FSHL */ 291, /* G_FSHR */ 295, /* G_ROTR */ 299, /* G_ROTL */ 302, /* G_ICMP */ 305, /* G_FCMP */ 309, /* G_SCMP */ 313, /* G_UCMP */ 316, /* G_SELECT */ 319, /* G_UADDO */ 323, /* G_UADDE */ 327, /* G_USUBO */ 332, /* G_USUBE */ 336, /* G_SADDO */ 341, /* G_SADDE */ 345, /* G_SSUBO */ 350, /* G_SSUBE */ 354, /* G_UMULO */ 359, /* G_SMULO */ 363, /* G_UMULH */ 367, /* G_SMULH */ 370, /* G_UADDSAT */ 373, /* G_SADDSAT */ 376, /* G_USUBSAT */ 379, /* G_SSUBSAT */ 382, /* G_USHLSAT */ 385, /* G_SSHLSAT */ 388, /* G_SMULFIX */ 391, /* G_UMULFIX */ 395, /* G_SMULFIXSAT */ 399, /* G_UMULFIXSAT */ 403, /* G_SDIVFIX */ 407, /* G_UDIVFIX */ 411, /* G_SDIVFIXSAT */ 415, /* G_UDIVFIXSAT */ 419, /* G_FADD */ 423, /* G_FSUB */ 426, /* G_FMUL */ 429, /* G_FMA */ 432, /* G_FMAD */ 436, /* G_FDIV */ 440, /* G_FREM */ 443, /* G_FPOW */ 446, /* G_FPOWI */ 449, /* G_FEXP */ 452, /* G_FEXP2 */ 454, /* G_FEXP10 */ 456, /* G_FLOG */ 458, /* G_FLOG2 */ 460, /* G_FLOG10 */ 462, /* G_FLDEXP */ 464, /* G_FFREXP */ 467, /* G_FNEG */ 470, /* G_FPEXT */ 472, /* G_FPTRUNC */ 474, /* G_FPTOSI */ 476, /* G_FPTOUI */ 478, /* G_SITOFP */ 480, /* G_UITOFP */ 482, /* G_FABS */ 484, /* G_FCOPYSIGN */ 486, /* G_IS_FPCLASS */ 489, /* G_FCANONICALIZE */ 492, /* G_FMINNUM */ 494, /* G_FMAXNUM */ 497, /* G_FMINNUM_IEEE */ 500, /* G_FMAXNUM_IEEE */ 503, /* G_FMINIMUM */ 506, /* G_FMAXIMUM */ 509, /* G_GET_FPENV */ 512, /* G_SET_FPENV */ 513, /* G_RESET_FPENV */ 514, /* G_GET_FPMODE */ 514, /* G_SET_FPMODE */ 515, /* G_RESET_FPMODE */ 516, /* G_PTR_ADD */ 516, /* G_PTRMASK */ 519, /* G_SMIN */ 522, /* G_SMAX */ 525, /* G_UMIN */ 528, /* G_UMAX */ 531, /* G_ABS */ 534, /* G_LROUND */ 536, /* G_LLROUND */ 538, /* G_BR */ 540, /* G_BRJT */ 541, /* G_VSCALE */ 544, /* G_INSERT_SUBVECTOR */ 546, /* G_EXTRACT_SUBVECTOR */ 550, /* G_INSERT_VECTOR_ELT */ 553, /* G_EXTRACT_VECTOR_ELT */ 557, /* G_SHUFFLE_VECTOR */ 560, /* G_SPLAT_VECTOR */ 564, /* G_VECTOR_COMPRESS */ 566, /* G_CTTZ */ 570, /* G_CTTZ_ZERO_UNDEF */ 572, /* G_CTLZ */ 574, /* G_CTLZ_ZERO_UNDEF */ 576, /* G_CTPOP */ 578, /* G_BSWAP */ 580, /* G_BITREVERSE */ 582, /* G_FCEIL */ 584, /* G_FCOS */ 586, /* G_FSIN */ 588, /* G_FTAN */ 590, /* G_FACOS */ 592, /* G_FASIN */ 594, /* G_FATAN */ 596, /* G_FCOSH */ 598, /* G_FSINH */ 600, /* G_FTANH */ 602, /* G_FSQRT */ 604, /* G_FFLOOR */ 606, /* G_FRINT */ 608, /* G_FNEARBYINT */ 610, /* G_ADDRSPACE_CAST */ 612, /* G_BLOCK_ADDR */ 614, /* G_JUMP_TABLE */ 616, /* G_DYN_STACKALLOC */ 618, /* G_STACKSAVE */ 621, /* G_STACKRESTORE */ 622, /* G_STRICT_FADD */ 623, /* G_STRICT_FSUB */ 626, /* G_STRICT_FMUL */ 629, /* G_STRICT_FDIV */ 632, /* G_STRICT_FREM */ 635, /* G_STRICT_FMA */ 638, /* G_STRICT_FSQRT */ 642, /* G_STRICT_FLDEXP */ 644, /* G_READ_REGISTER */ 647, /* G_WRITE_REGISTER */ 649, /* G_MEMCPY */ 651, /* G_MEMCPY_INLINE */ 655, /* G_MEMMOVE */ 658, /* G_MEMSET */ 662, /* G_BZERO */ 666, /* G_TRAP */ 669, /* G_DEBUGTRAP */ 669, /* G_UBSANTRAP */ 669, /* G_VECREDUCE_SEQ_FADD */ 670, /* G_VECREDUCE_SEQ_FMUL */ 673, /* G_VECREDUCE_FADD */ 676, /* G_VECREDUCE_FMUL */ 678, /* G_VECREDUCE_FMAX */ 680, /* G_VECREDUCE_FMIN */ 682, /* G_VECREDUCE_FMAXIMUM */ 684, /* G_VECREDUCE_FMINIMUM */ 686, /* G_VECREDUCE_ADD */ 688, /* G_VECREDUCE_MUL */ 690, /* G_VECREDUCE_AND */ 692, /* G_VECREDUCE_OR */ 694, /* G_VECREDUCE_XOR */ 696, /* G_VECREDUCE_SMAX */ 698, /* G_VECREDUCE_SMIN */ 700, /* G_VECREDUCE_UMAX */ 702, /* G_VECREDUCE_UMIN */ 704, /* G_SBFX */ 706, /* G_UBFX */ 710, /* BRANCH */ 714, /* BRANCH_COND_f32 */ 715, /* BRANCH_COND_i32 */ 717, /* BREAK */ 719, /* BREAKC_f32 */ 719, /* BREAKC_i32 */ 721, /* BREAK_LOGICALNZ_f32 */ 723, /* BREAK_LOGICALNZ_i32 */ 724, /* BREAK_LOGICALZ_f32 */ 725, /* BREAK_LOGICALZ_i32 */ 726, /* CONST_COPY */ 727, /* CONTINUE */ 729, /* CONTINUEC_f32 */ 729, /* CONTINUEC_i32 */ 731, /* CONTINUE_LOGICALNZ_f32 */ 733, /* CONTINUE_LOGICALNZ_i32 */ 734, /* CONTINUE_LOGICALZ_f32 */ 735, /* CONTINUE_LOGICALZ_i32 */ 736, /* CUBE_eg_pseudo */ 737, /* CUBE_r600_pseudo */ 739, /* DEFAULT */ 741, /* DOT_4 */ 741, /* DUMMY_CHAIN */ 812, /* ELSE */ 812, /* END */ 812, /* ENDFUNC */ 812, /* ENDIF */ 812, /* ENDLOOP */ 812, /* ENDMAIN */ 812, /* ENDSWITCH */ 812, /* FABS_R600 */ 812, /* FNEG_R600 */ 814, /* FUNC */ 816, /* IFC_f32 */ 816, /* IFC_i32 */ 818, /* IF_LOGICALNZ_f32 */ 820, /* IF_LOGICALNZ_i32 */ 821, /* IF_LOGICALZ_f32 */ 822, /* IF_LOGICALZ_i32 */ 823, /* IF_PREDICATE_SET */ 824, /* JUMP */ 825, /* JUMP_COND */ 826, /* MASK_WRITE */ 828, /* MOV_IMM_F32 */ 829, /* MOV_IMM_GLOBAL_ADDR */ 831, /* MOV_IMM_I32 */ 833, /* PRED_X */ 835, /* R600_EXTRACT_ELT_V2 */ 839, /* R600_EXTRACT_ELT_V4 */ 842, /* R600_INSERT_ELT_V2 */ 845, /* R600_INSERT_ELT_V4 */ 849, /* R600_RegisterLoad */ 853, /* R600_RegisterStore */ 857, /* RETDYN */ 861, /* RETURN */ 861, /* TXD */ 861, /* TXD_SHADOW */ 868, /* WHILELOOP */ 875, /* ADD */ 875, /* ADDC_UINT */ 896, /* ADD_INT */ 917, /* ALU_CLAUSE */ 938, /* AND_INT */ 939, /* ASHR_eg */ 960, /* ASHR_r600 */ 981, /* BCNT_INT */ 1002, /* BFE_INT_eg */ 1016, /* BFE_UINT_eg */ 1035, /* BFI_INT_eg */ 1054, /* BFM_INT_eg */ 1073, /* BIT_ALIGN_INT_eg */ 1094, /* CEIL */ 1113, /* CF_ALU */ 1127, /* CF_ALU_BREAK */ 1136, /* CF_ALU_CONTINUE */ 1145, /* CF_ALU_ELSE_AFTER */ 1154, /* CF_ALU_POP_AFTER */ 1163, /* CF_ALU_PUSH_BEFORE */ 1172, /* CF_CALL_FS_EG */ 1181, /* CF_CALL_FS_R600 */ 1181, /* CF_CONTINUE_EG */ 1181, /* CF_CONTINUE_R600 */ 1182, /* CF_ELSE_EG */ 1183, /* CF_ELSE_R600 */ 1185, /* CF_END_CM */ 1187, /* CF_END_EG */ 1187, /* CF_END_R600 */ 1187, /* CF_JUMP_EG */ 1187, /* CF_JUMP_R600 */ 1189, /* CF_PUSH_EG */ 1191, /* CF_PUSH_ELSE_R600 */ 1193, /* CF_TC_EG */ 1194, /* CF_TC_R600 */ 1196, /* CF_VC_EG */ 1198, /* CF_VC_R600 */ 1200, /* CNDE_INT */ 1202, /* CNDE_eg */ 1221, /* CNDE_r600 */ 1240, /* CNDGE_INT */ 1259, /* CNDGE_eg */ 1278, /* CNDGE_r600 */ 1297, /* CNDGT_INT */ 1316, /* CNDGT_eg */ 1335, /* CNDGT_r600 */ 1354, /* COS_cm */ 1373, /* COS_eg */ 1387, /* COS_r600 */ 1401, /* COS_r700 */ 1415, /* CUBE_eg_real */ 1429, /* CUBE_r600_real */ 1450, /* DOT4_eg */ 1471, /* DOT4_r600 */ 1492, /* EG_ExportBuf */ 1513, /* EG_ExportSwz */ 1520, /* END_LOOP_EG */ 1529, /* END_LOOP_R600 */ 1530, /* EXP_IEEE_cm */ 1531, /* EXP_IEEE_eg */ 1545, /* EXP_IEEE_r600 */ 1559, /* FETCH_CLAUSE */ 1573, /* FFBH_UINT */ 1574, /* FFBL_INT */ 1588, /* FLOOR */ 1602, /* FLT16_TO_FLT32 */ 1616, /* FLT32_TO_FLT16 */ 1630, /* FLT_TO_INT_eg */ 1644, /* FLT_TO_INT_r600 */ 1658, /* FLT_TO_UINT_eg */ 1672, /* FLT_TO_UINT_r600 */ 1686, /* FMA_eg */ 1700, /* FRACT */ 1719, /* GROUP_BARRIER */ 1733, /* INTERP_LOAD_P0 */ 1733, /* INTERP_PAIR_XY */ 1747, /* INTERP_PAIR_ZW */ 1752, /* INTERP_VEC_LOAD */ 1757, /* INTERP_XY */ 1759, /* INTERP_ZW */ 1780, /* INT_TO_FLT_eg */ 1801, /* INT_TO_FLT_r600 */ 1815, /* KILLGT */ 1829, /* LDS_ADD */ 1850, /* LDS_ADD_RET */ 1859, /* LDS_AND */ 1869, /* LDS_AND_RET */ 1878, /* LDS_BYTE_READ_RET */ 1888, /* LDS_BYTE_WRITE */ 1895, /* LDS_CMPST */ 1904, /* LDS_CMPST_RET */ 1916, /* LDS_MAX_INT */ 1929, /* LDS_MAX_INT_RET */ 1938, /* LDS_MAX_UINT */ 1948, /* LDS_MAX_UINT_RET */ 1957, /* LDS_MIN_INT */ 1967, /* LDS_MIN_INT_RET */ 1976, /* LDS_MIN_UINT */ 1986, /* LDS_MIN_UINT_RET */ 1995, /* LDS_OR */ 2005, /* LDS_OR_RET */ 2014, /* LDS_READ_RET */ 2024, /* LDS_SHORT_READ_RET */ 2031, /* LDS_SHORT_WRITE */ 2038, /* LDS_SUB */ 2047, /* LDS_SUB_RET */ 2056, /* LDS_UBYTE_READ_RET */ 2066, /* LDS_USHORT_READ_RET */ 2073, /* LDS_WRITE */ 2080, /* LDS_WRXCHG */ 2089, /* LDS_WRXCHG_RET */ 2098, /* LDS_XOR */ 2108, /* LDS_XOR_RET */ 2117, /* LITERALS */ 2127, /* LOG_CLAMPED_eg */ 2129, /* LOG_CLAMPED_r600 */ 2143, /* LOG_IEEE_cm */ 2157, /* LOG_IEEE_eg */ 2171, /* LOG_IEEE_r600 */ 2185, /* LOOP_BREAK_EG */ 2199, /* LOOP_BREAK_R600 */ 2200, /* LSHL_eg */ 2201, /* LSHL_r600 */ 2222, /* LSHR_eg */ 2243, /* LSHR_r600 */ 2264, /* MAX */ 2285, /* MAX_DX10 */ 2306, /* MAX_INT */ 2327, /* MAX_UINT */ 2348, /* MIN */ 2369, /* MIN_DX10 */ 2390, /* MIN_INT */ 2411, /* MIN_UINT */ 2432, /* MOV */ 2453, /* MOVA_INT_eg */ 2467, /* MUL */ 2481, /* MULADD_IEEE_eg */ 2502, /* MULADD_IEEE_r600 */ 2521, /* MULADD_INT24_cm */ 2540, /* MULADD_UINT24_eg */ 2559, /* MULADD_eg */ 2578, /* MULADD_r600 */ 2597, /* MULHI_INT_cm */ 2616, /* MULHI_INT_cm24 */ 2637, /* MULHI_INT_eg */ 2658, /* MULHI_INT_r600 */ 2679, /* MULHI_UINT24_eg */ 2700, /* MULHI_UINT_cm */ 2721, /* MULHI_UINT_cm24 */ 2742, /* MULHI_UINT_eg */ 2763, /* MULHI_UINT_r600 */ 2784, /* MULLO_INT_cm */ 2805, /* MULLO_INT_eg */ 2826, /* MULLO_INT_r600 */ 2847, /* MULLO_UINT_cm */ 2868, /* MULLO_UINT_eg */ 2889, /* MULLO_UINT_r600 */ 2910, /* MUL_IEEE */ 2931, /* MUL_INT24_cm */ 2952, /* MUL_LIT_eg */ 2973, /* MUL_LIT_r600 */ 2992, /* MUL_UINT24_eg */ 3011, /* NOT_INT */ 3032, /* OR_INT */ 3046, /* PAD */ 3067, /* POP_EG */ 3067, /* POP_R600 */ 3069, /* PRED_SETE */ 3071, /* PRED_SETE_INT */ 3092, /* PRED_SETGE */ 3113, /* PRED_SETGE_INT */ 3134, /* PRED_SETGT */ 3155, /* PRED_SETGT_INT */ 3176, /* PRED_SETNE */ 3197, /* PRED_SETNE_INT */ 3218, /* R600_ExportBuf */ 3239, /* R600_ExportSwz */ 3246, /* RAT_ATOMIC_ADD_NORET */ 3255, /* RAT_ATOMIC_ADD_RTN */ 3258, /* RAT_ATOMIC_AND_NORET */ 3261, /* RAT_ATOMIC_AND_RTN */ 3264, /* RAT_ATOMIC_CMPXCHG_INT_NORET */ 3267, /* RAT_ATOMIC_CMPXCHG_INT_RTN */ 3270, /* RAT_ATOMIC_DEC_UINT_NORET */ 3273, /* RAT_ATOMIC_DEC_UINT_RTN */ 3276, /* RAT_ATOMIC_INC_UINT_NORET */ 3279, /* RAT_ATOMIC_INC_UINT_RTN */ 3282, /* RAT_ATOMIC_MAX_INT_NORET */ 3285, /* RAT_ATOMIC_MAX_INT_RTN */ 3288, /* RAT_ATOMIC_MAX_UINT_NORET */ 3291, /* RAT_ATOMIC_MAX_UINT_RTN */ 3294, /* RAT_ATOMIC_MIN_INT_NORET */ 3297, /* RAT_ATOMIC_MIN_INT_RTN */ 3300, /* RAT_ATOMIC_MIN_UINT_NORET */ 3303, /* RAT_ATOMIC_MIN_UINT_RTN */ 3306, /* RAT_ATOMIC_OR_NORET */ 3309, /* RAT_ATOMIC_OR_RTN */ 3312, /* RAT_ATOMIC_RSUB_NORET */ 3315, /* RAT_ATOMIC_RSUB_RTN */ 3318, /* RAT_ATOMIC_SUB_NORET */ 3321, /* RAT_ATOMIC_SUB_RTN */ 3324, /* RAT_ATOMIC_XCHG_INT_NORET */ 3327, /* RAT_ATOMIC_XCHG_INT_RTN */ 3330, /* RAT_ATOMIC_XOR_NORET */ 3333, /* RAT_ATOMIC_XOR_RTN */ 3336, /* RAT_MSKOR */ 3339, /* RAT_STORE_DWORD128 */ 3341, /* RAT_STORE_DWORD32 */ 3343, /* RAT_STORE_DWORD64 */ 3345, /* RAT_STORE_TYPED_cm */ 3347, /* RAT_STORE_TYPED_eg */ 3351, /* RAT_WRITE_CACHELESS_128_eg */ 3355, /* RAT_WRITE_CACHELESS_32_eg */ 3358, /* RAT_WRITE_CACHELESS_64_eg */ 3361, /* RECIPSQRT_CLAMPED_cm */ 3364, /* RECIPSQRT_CLAMPED_eg */ 3378, /* RECIPSQRT_CLAMPED_r600 */ 3392, /* RECIPSQRT_IEEE_cm */ 3406, /* RECIPSQRT_IEEE_eg */ 3420, /* RECIPSQRT_IEEE_r600 */ 3434, /* RECIP_CLAMPED_cm */ 3448, /* RECIP_CLAMPED_eg */ 3462, /* RECIP_CLAMPED_r600 */ 3476, /* RECIP_IEEE_cm */ 3490, /* RECIP_IEEE_eg */ 3504, /* RECIP_IEEE_r600 */ 3518, /* RECIP_UINT_eg */ 3532, /* RECIP_UINT_r600 */ 3546, /* RNDNE */ 3560, /* SETE */ 3574, /* SETE_DX10 */ 3595, /* SETE_INT */ 3616, /* SETGE_DX10 */ 3637, /* SETGE_INT */ 3658, /* SETGE_UINT */ 3679, /* SETGT_DX10 */ 3700, /* SETGT_INT */ 3721, /* SETGT_UINT */ 3742, /* SETNE_DX10 */ 3763, /* SETNE_INT */ 3784, /* SGE */ 3805, /* SGT */ 3826, /* SIN_cm */ 3847, /* SIN_eg */ 3861, /* SIN_r600 */ 3875, /* SIN_r700 */ 3889, /* SNE */ 3903, /* SUBB_UINT */ 3924, /* SUB_INT */ 3945, /* TEX_GET_GRADIENTS_H */ 3966, /* TEX_GET_GRADIENTS_V */ 3985, /* TEX_GET_TEXTURE_RESINFO */ 4004, /* TEX_LD */ 4023, /* TEX_LDPTR */ 4042, /* TEX_SAMPLE */ 4061, /* TEX_SAMPLE_C */ 4080, /* TEX_SAMPLE_C_G */ 4099, /* TEX_SAMPLE_C_L */ 4118, /* TEX_SAMPLE_C_LB */ 4137, /* TEX_SAMPLE_G */ 4156, /* TEX_SAMPLE_L */ 4175, /* TEX_SAMPLE_LB */ 4194, /* TEX_SET_GRADIENTS_H */ 4213, /* TEX_SET_GRADIENTS_V */ 4232, /* TEX_VTX_CONSTBUF */ 4251, /* TEX_VTX_TEXBUF */ 4255, /* TRUNC */ 4259, /* UINT_TO_FLT_eg */ 4273, /* UINT_TO_FLT_r600 */ 4287, /* VTX_READ_128_cm */ 4301, /* VTX_READ_128_eg */ 4305, /* VTX_READ_16_cm */ 4309, /* VTX_READ_16_eg */ 4313, /* VTX_READ_32_cm */ 4317, /* VTX_READ_32_eg */ 4321, /* VTX_READ_64_cm */ 4325, /* VTX_READ_64_eg */ 4329, /* VTX_READ_8_cm */ 4333, /* VTX_READ_8_eg */ 4337, /* WHILE_LOOP_EG */ 4341, /* WHILE_LOOP_R600 */ 4342, /* XOR_INT */ 4343, }; using namespace OpTypes; static const int8_t OpcodeOperandTypes[] = { /* PHI */ -1, /* INLINEASM */ /* INLINEASM_BR */ /* CFI_INSTRUCTION */ i32imm, /* EH_LABEL */ i32imm, /* GC_LABEL */ i32imm, /* ANNOTATION_LABEL */ i32imm, /* KILL */ /* EXTRACT_SUBREG */ -1, -1, i32imm, /* INSERT_SUBREG */ -1, -1, -1, i32imm, /* IMPLICIT_DEF */ -1, /* SUBREG_TO_REG */ -1, -1, -1, i32imm, /* COPY_TO_REGCLASS */ -1, -1, i32imm, /* DBG_VALUE */ /* DBG_VALUE_LIST */ /* DBG_INSTR_REF */ /* DBG_PHI */ /* DBG_LABEL */ -1, /* REG_SEQUENCE */ -1, -1, /* COPY */ -1, -1, /* BUNDLE */ /* LIFETIME_START */ i32imm, /* LIFETIME_END */ i32imm, /* PSEUDO_PROBE */ i64imm, i64imm, i8imm, i32imm, /* ARITH_FENCE */ -1, -1, /* STACKMAP */ i64imm, i32imm, /* FENTRY_CALL */ /* PATCHPOINT */ -1, i64imm, i32imm, -1, i32imm, i32imm, /* LOAD_STACK_GUARD */ -1, /* PREALLOCATED_SETUP */ i32imm, /* PREALLOCATED_ARG */ -1, i32imm, i32imm, /* STATEPOINT */ /* LOCAL_ESCAPE */ -1, i32imm, /* FAULTING_OP */ -1, /* PATCHABLE_OP */ /* PATCHABLE_FUNCTION_ENTER */ /* PATCHABLE_RET */ /* PATCHABLE_FUNCTION_EXIT */ /* PATCHABLE_TAIL_CALL */ /* PATCHABLE_EVENT_CALL */ -1, -1, /* PATCHABLE_TYPED_EVENT_CALL */ -1, -1, -1, /* ICALL_BRANCH_FUNNEL */ /* FAKE_USE */ /* MEMBARRIER */ /* JUMP_TABLE_DEBUG_INFO */ i64imm, /* CONVERGENCECTRL_ENTRY */ -1, /* CONVERGENCECTRL_ANCHOR */ -1, /* CONVERGENCECTRL_LOOP */ -1, -1, /* CONVERGENCECTRL_GLUE */ -1, /* G_ASSERT_SEXT */ type0, type0, untyped_imm_0, /* G_ASSERT_ZEXT */ type0, type0, untyped_imm_0, /* G_ASSERT_ALIGN */ type0, type0, untyped_imm_0, /* G_ADD */ type0, type0, type0, /* G_SUB */ type0, type0, type0, /* G_MUL */ type0, type0, type0, /* G_SDIV */ type0, type0, type0, /* G_UDIV */ type0, type0, type0, /* G_SREM */ type0, type0, type0, /* G_UREM */ type0, type0, type0, /* G_SDIVREM */ type0, type0, type0, type0, /* G_UDIVREM */ type0, type0, type0, type0, /* G_AND */ type0, type0, type0, /* G_OR */ type0, type0, type0, /* G_XOR */ type0, type0, type0, /* G_IMPLICIT_DEF */ type0, /* G_PHI */ type0, /* G_FRAME_INDEX */ type0, -1, /* G_GLOBAL_VALUE */ type0, -1, /* G_PTRAUTH_GLOBAL_VALUE */ type0, -1, i32imm, type1, i64imm, /* G_CONSTANT_POOL */ type0, -1, /* G_EXTRACT */ type0, type1, untyped_imm_0, /* G_UNMERGE_VALUES */ type0, type1, /* G_INSERT */ type0, type0, type1, untyped_imm_0, /* G_MERGE_VALUES */ type0, type1, /* G_BUILD_VECTOR */ type0, type1, /* G_BUILD_VECTOR_TRUNC */ type0, type1, /* G_CONCAT_VECTORS */ type0, type1, /* G_PTRTOINT */ type0, type1, /* G_INTTOPTR */ type0, type1, /* G_BITCAST */ type0, type1, /* G_FREEZE */ type0, type0, /* G_CONSTANT_FOLD_BARRIER */ type0, type0, /* G_INTRINSIC_FPTRUNC_ROUND */ type0, type1, i32imm, /* G_INTRINSIC_TRUNC */ type0, type0, /* G_INTRINSIC_ROUND */ type0, type0, /* G_INTRINSIC_LRINT */ type0, type1, /* G_INTRINSIC_LLRINT */ type0, type1, /* G_INTRINSIC_ROUNDEVEN */ type0, type0, /* G_READCYCLECOUNTER */ type0, /* G_READSTEADYCOUNTER */ type0, /* G_LOAD */ type0, ptype1, /* G_SEXTLOAD */ type0, ptype1, /* G_ZEXTLOAD */ type0, ptype1, /* G_INDEXED_LOAD */ type0, ptype1, ptype1, type2, -1, /* G_INDEXED_SEXTLOAD */ type0, ptype1, ptype1, type2, -1, /* G_INDEXED_ZEXTLOAD */ type0, ptype1, ptype1, type2, -1, /* G_STORE */ type0, ptype1, /* G_INDEXED_STORE */ ptype0, type1, ptype0, ptype2, -1, /* G_ATOMIC_CMPXCHG_WITH_SUCCESS */ type0, type1, type2, type0, type0, /* G_ATOMIC_CMPXCHG */ type0, ptype1, type0, type0, /* G_ATOMICRMW_XCHG */ type0, ptype1, type0, /* G_ATOMICRMW_ADD */ type0, ptype1, type0, /* G_ATOMICRMW_SUB */ type0, ptype1, type0, /* G_ATOMICRMW_AND */ type0, ptype1, type0, /* G_ATOMICRMW_NAND */ type0, ptype1, type0, /* G_ATOMICRMW_OR */ type0, ptype1, type0, /* G_ATOMICRMW_XOR */ type0, ptype1, type0, /* G_ATOMICRMW_MAX */ type0, ptype1, type0, /* G_ATOMICRMW_MIN */ type0, ptype1, type0, /* G_ATOMICRMW_UMAX */ type0, ptype1, type0, /* G_ATOMICRMW_UMIN */ type0, ptype1, type0, /* G_ATOMICRMW_FADD */ type0, ptype1, type0, /* G_ATOMICRMW_FSUB */ type0, ptype1, type0, /* G_ATOMICRMW_FMAX */ type0, ptype1, type0, /* G_ATOMICRMW_FMIN */ type0, ptype1, type0, /* G_ATOMICRMW_UINC_WRAP */ type0, ptype1, type0, /* G_ATOMICRMW_UDEC_WRAP */ type0, ptype1, type0, /* G_FENCE */ i32imm, i32imm, /* G_PREFETCH */ ptype0, i32imm, i32imm, i32imm, /* G_BRCOND */ type0, -1, /* G_BRINDIRECT */ type0, /* G_INVOKE_REGION_START */ /* G_INTRINSIC */ -1, /* G_INTRINSIC_W_SIDE_EFFECTS */ -1, /* G_INTRINSIC_CONVERGENT */ -1, /* G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS */ -1, /* G_ANYEXT */ type0, type1, /* G_TRUNC */ type0, type1, /* G_CONSTANT */ type0, -1, /* G_FCONSTANT */ type0, -1, /* G_VASTART */ type0, /* G_VAARG */ type0, type1, -1, /* G_SEXT */ type0, type1, /* G_SEXT_INREG */ type0, type0, untyped_imm_0, /* G_ZEXT */ type0, type1, /* G_SHL */ type0, type0, type1, /* G_LSHR */ type0, type0, type1, /* G_ASHR */ type0, type0, type1, /* G_FSHL */ type0, type0, type0, type1, /* G_FSHR */ type0, type0, type0, type1, /* G_ROTR */ type0, type0, type1, /* G_ROTL */ type0, type0, type1, /* G_ICMP */ type0, -1, type1, type1, /* G_FCMP */ type0, -1, type1, type1, /* G_SCMP */ type0, type1, type1, /* G_UCMP */ type0, type1, type1, /* G_SELECT */ type0, type1, type0, type0, /* G_UADDO */ type0, type1, type0, type0, /* G_UADDE */ type0, type1, type0, type0, type1, /* G_USUBO */ type0, type1, type0, type0, /* G_USUBE */ type0, type1, type0, type0, type1, /* G_SADDO */ type0, type1, type0, type0, /* G_SADDE */ type0, type1, type0, type0, type1, /* G_SSUBO */ type0, type1, type0, type0, /* G_SSUBE */ type0, type1, type0, type0, type1, /* G_UMULO */ type0, type1, type0, type0, /* G_SMULO */ type0, type1, type0, type0, /* G_UMULH */ type0, type0, type0, /* G_SMULH */ type0, type0, type0, /* G_UADDSAT */ type0, type0, type0, /* G_SADDSAT */ type0, type0, type0, /* G_USUBSAT */ type0, type0, type0, /* G_SSUBSAT */ type0, type0, type0, /* G_USHLSAT */ type0, type0, type1, /* G_SSHLSAT */ type0, type0, type1, /* G_SMULFIX */ type0, type0, type0, untyped_imm_0, /* G_UMULFIX */ type0, type0, type0, untyped_imm_0, /* G_SMULFIXSAT */ type0, type0, type0, untyped_imm_0, /* G_UMULFIXSAT */ type0, type0, type0, untyped_imm_0, /* G_SDIVFIX */ type0, type0, type0, untyped_imm_0, /* G_UDIVFIX */ type0, type0, type0, untyped_imm_0, /* G_SDIVFIXSAT */ type0, type0, type0, untyped_imm_0, /* G_UDIVFIXSAT */ type0, type0, type0, untyped_imm_0, /* G_FADD */ type0, type0, type0, /* G_FSUB */ type0, type0, type0, /* G_FMUL */ type0, type0, type0, /* G_FMA */ type0, type0, type0, type0, /* G_FMAD */ type0, type0, type0, type0, /* G_FDIV */ type0, type0, type0, /* G_FREM */ type0, type0, type0, /* G_FPOW */ type0, type0, type0, /* G_FPOWI */ type0, type0, type1, /* G_FEXP */ type0, type0, /* G_FEXP2 */ type0, type0, /* G_FEXP10 */ type0, type0, /* G_FLOG */ type0, type0, /* G_FLOG2 */ type0, type0, /* G_FLOG10 */ type0, type0, /* G_FLDEXP */ type0, type0, type1, /* G_FFREXP */ type0, type1, type0, /* G_FNEG */ type0, type0, /* G_FPEXT */ type0, type1, /* G_FPTRUNC */ type0, type1, /* G_FPTOSI */ type0, type1, /* G_FPTOUI */ type0, type1, /* G_SITOFP */ type0, type1, /* G_UITOFP */ type0, type1, /* G_FABS */ type0, type0, /* G_FCOPYSIGN */ type0, type0, type1, /* G_IS_FPCLASS */ type0, type1, -1, /* G_FCANONICALIZE */ type0, type0, /* G_FMINNUM */ type0, type0, type0, /* G_FMAXNUM */ type0, type0, type0, /* G_FMINNUM_IEEE */ type0, type0, type0, /* G_FMAXNUM_IEEE */ type0, type0, type0, /* G_FMINIMUM */ type0, type0, type0, /* G_FMAXIMUM */ type0, type0, type0, /* G_GET_FPENV */ type0, /* G_SET_FPENV */ type0, /* G_RESET_FPENV */ /* G_GET_FPMODE */ type0, /* G_SET_FPMODE */ type0, /* G_RESET_FPMODE */ /* G_PTR_ADD */ ptype0, ptype0, type1, /* G_PTRMASK */ ptype0, ptype0, type1, /* G_SMIN */ type0, type0, type0, /* G_SMAX */ type0, type0, type0, /* G_UMIN */ type0, type0, type0, /* G_UMAX */ type0, type0, type0, /* G_ABS */ type0, type0, /* G_LROUND */ type0, type1, /* G_LLROUND */ type0, type1, /* G_BR */ -1, /* G_BRJT */ ptype0, -1, type1, /* G_VSCALE */ type0, -1, /* G_INSERT_SUBVECTOR */ type0, type0, type1, untyped_imm_0, /* G_EXTRACT_SUBVECTOR */ type0, type0, untyped_imm_0, /* G_INSERT_VECTOR_ELT */ type0, type0, type1, type2, /* G_EXTRACT_VECTOR_ELT */ type0, type1, type2, /* G_SHUFFLE_VECTOR */ type0, type1, type1, -1, /* G_SPLAT_VECTOR */ type0, type1, /* G_VECTOR_COMPRESS */ type0, type0, type1, type0, /* G_CTTZ */ type0, type1, /* G_CTTZ_ZERO_UNDEF */ type0, type1, /* G_CTLZ */ type0, type1, /* G_CTLZ_ZERO_UNDEF */ type0, type1, /* G_CTPOP */ type0, type1, /* G_BSWAP */ type0, type0, /* G_BITREVERSE */ type0, type0, /* G_FCEIL */ type0, type0, /* G_FCOS */ type0, type0, /* G_FSIN */ type0, type0, /* G_FTAN */ type0, type0, /* G_FACOS */ type0, type0, /* G_FASIN */ type0, type0, /* G_FATAN */ type0, type0, /* G_FCOSH */ type0, type0, /* G_FSINH */ type0, type0, /* G_FTANH */ type0, type0, /* G_FSQRT */ type0, type0, /* G_FFLOOR */ type0, type0, /* G_FRINT */ type0, type0, /* G_FNEARBYINT */ type0, type0, /* G_ADDRSPACE_CAST */ type0, type1, /* G_BLOCK_ADDR */ type0, -1, /* G_JUMP_TABLE */ type0, -1, /* G_DYN_STACKALLOC */ ptype0, type1, i32imm, /* G_STACKSAVE */ ptype0, /* G_STACKRESTORE */ ptype0, /* G_STRICT_FADD */ type0, type0, type0, /* G_STRICT_FSUB */ type0, type0, type0, /* G_STRICT_FMUL */ type0, type0, type0, /* G_STRICT_FDIV */ type0, type0, type0, /* G_STRICT_FREM */ type0, type0, type0, /* G_STRICT_FMA */ type0, type0, type0, type0, /* G_STRICT_FSQRT */ type0, type0, /* G_STRICT_FLDEXP */ type0, type0, type1, /* G_READ_REGISTER */ type0, -1, /* G_WRITE_REGISTER */ -1, type0, /* G_MEMCPY */ ptype0, ptype1, type2, untyped_imm_0, /* G_MEMCPY_INLINE */ ptype0, ptype1, type2, /* G_MEMMOVE */ ptype0, ptype1, type2, untyped_imm_0, /* G_MEMSET */ ptype0, type1, type2, untyped_imm_0, /* G_BZERO */ ptype0, type1, untyped_imm_0, /* G_TRAP */ /* G_DEBUGTRAP */ /* G_UBSANTRAP */ i8imm, /* G_VECREDUCE_SEQ_FADD */ type0, type1, type2, /* G_VECREDUCE_SEQ_FMUL */ type0, type1, type2, /* G_VECREDUCE_FADD */ type0, type1, /* G_VECREDUCE_FMUL */ type0, type1, /* G_VECREDUCE_FMAX */ type0, type1, /* G_VECREDUCE_FMIN */ type0, type1, /* G_VECREDUCE_FMAXIMUM */ type0, type1, /* G_VECREDUCE_FMINIMUM */ type0, type1, /* G_VECREDUCE_ADD */ type0, type1, /* G_VECREDUCE_MUL */ type0, type1, /* G_VECREDUCE_AND */ type0, type1, /* G_VECREDUCE_OR */ type0, type1, /* G_VECREDUCE_XOR */ type0, type1, /* G_VECREDUCE_SMAX */ type0, type1, /* G_VECREDUCE_SMIN */ type0, type1, /* G_VECREDUCE_UMAX */ type0, type1, /* G_VECREDUCE_UMIN */ type0, type1, /* G_SBFX */ type0, type0, type1, type1, /* G_UBFX */ type0, type0, type1, type1, /* BRANCH */ brtarget, /* BRANCH_COND_f32 */ brtarget, R600_Reg32, /* BRANCH_COND_i32 */ brtarget, R600_Reg32, /* BREAK */ /* BREAKC_f32 */ R600_Reg32, R600_Reg32, /* BREAKC_i32 */ R600_Reg32, R600_Reg32, /* BREAK_LOGICALNZ_f32 */ R600_Reg32, /* BREAK_LOGICALNZ_i32 */ R600_Reg32, /* BREAK_LOGICALZ_f32 */ R600_Reg32, /* BREAK_LOGICALZ_i32 */ R600_Reg32, /* CONST_COPY */ R600_Reg32, i32imm, /* CONTINUE */ /* CONTINUEC_f32 */ R600_Reg32, R600_Reg32, /* CONTINUEC_i32 */ R600_Reg32, R600_Reg32, /* CONTINUE_LOGICALNZ_f32 */ R600_Reg32, /* CONTINUE_LOGICALNZ_i32 */ R600_Reg32, /* CONTINUE_LOGICALZ_f32 */ R600_Reg32, /* CONTINUE_LOGICALZ_i32 */ R600_Reg32, /* CUBE_eg_pseudo */ R600_Reg128, R600_Reg128, /* CUBE_r600_pseudo */ R600_Reg128, R600_Reg128, /* DEFAULT */ /* DOT_4 */ R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_TReg32_X, NEG, REL, ABS, SEL, R600_TReg32_X, NEG, REL, ABS, SEL, R600_Predicate, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_TReg32_Y, NEG, REL, ABS, SEL, R600_TReg32_Y, NEG, REL, ABS, SEL, R600_Predicate, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_TReg32_Z, NEG, REL, ABS, SEL, R600_TReg32_Z, NEG, REL, ABS, SEL, R600_Predicate, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_TReg32_W, NEG, REL, ABS, SEL, R600_TReg32_W, NEG, REL, ABS, SEL, R600_Predicate, LITERAL, LITERAL, /* DUMMY_CHAIN */ /* ELSE */ /* END */ /* ENDFUNC */ /* ENDIF */ /* ENDLOOP */ /* ENDMAIN */ /* ENDSWITCH */ /* FABS_R600 */ R600_Reg32, R600_Reg32, /* FNEG_R600 */ R600_Reg32, R600_Reg32, /* FUNC */ /* IFC_f32 */ R600_Reg32, R600_Reg32, /* IFC_i32 */ R600_Reg32, R600_Reg32, /* IF_LOGICALNZ_f32 */ R600_Reg32, /* IF_LOGICALNZ_i32 */ R600_Reg32, /* IF_LOGICALZ_f32 */ R600_Reg32, /* IF_LOGICALZ_i32 */ R600_Reg32, /* IF_PREDICATE_SET */ R600_Reg32, /* JUMP */ brtarget, /* JUMP_COND */ brtarget, R600_Predicate_Bit, /* MASK_WRITE */ R600_Reg32, /* MOV_IMM_F32 */ R600_Reg32, f32imm, /* MOV_IMM_GLOBAL_ADDR */ R600_Reg32, i32imm, /* MOV_IMM_I32 */ R600_Reg32, i32imm, /* PRED_X */ R600_Predicate_Bit, R600_Reg32, i32imm, i32imm, /* R600_EXTRACT_ELT_V2 */ R600_Reg32, R600_Reg64Vertical, R600_Reg32, /* R600_EXTRACT_ELT_V4 */ R600_Reg32, R600_Reg128Vertical, R600_Reg32, /* R600_INSERT_ELT_V2 */ R600_Reg64Vertical, R600_Reg64Vertical, R600_Reg32, R600_Reg32, /* R600_INSERT_ELT_V4 */ R600_Reg128Vertical, R600_Reg128Vertical, R600_Reg32, R600_Reg32, /* R600_RegisterLoad */ R600_Reg32, R600_Reg32, i32imm, i32imm, /* R600_RegisterStore */ R600_Reg32, R600_Reg32, i32imm, i32imm, /* RETDYN */ /* RETURN */ /* TXD */ R600_Reg128, R600_Reg128, R600_Reg128, R600_Reg128, i32imm, i32imm, i32imm, /* TXD_SHADOW */ R600_Reg128, R600_Reg128, R600_Reg128, R600_Reg128, i32imm, i32imm, i32imm, /* WHILELOOP */ /* ADD */ R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, /* ADDC_UINT */ R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, /* ADD_INT */ R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, /* ALU_CLAUSE */ i32imm, /* AND_INT */ R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, /* ASHR_eg */ R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, /* ASHR_r600 */ R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, /* BCNT_INT */ R600_Reg32, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, /* BFE_INT_eg */ R600_Reg32, REL, CLAMP, R600_Reg32, NEG, REL, SEL, R600_Reg32, NEG, REL, SEL, R600_Reg32, NEG, REL, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, /* BFE_UINT_eg */ R600_Reg32, REL, CLAMP, R600_Reg32, NEG, REL, SEL, R600_Reg32, NEG, REL, SEL, R600_Reg32, NEG, REL, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, /* BFI_INT_eg */ R600_Reg32, REL, CLAMP, R600_Reg32, NEG, REL, SEL, R600_Reg32, NEG, REL, SEL, R600_Reg32, NEG, REL, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, /* BFM_INT_eg */ R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, /* BIT_ALIGN_INT_eg */ R600_Reg32, REL, CLAMP, R600_Reg32, NEG, REL, SEL, R600_Reg32, NEG, REL, SEL, R600_Reg32, NEG, REL, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, /* CEIL */ R600_Reg32, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, /* CF_ALU */ i32imm, i32imm, i32imm, KCACHE, KCACHE, i32imm, i32imm, i32imm, i32imm, /* CF_ALU_BREAK */ i32imm, i32imm, i32imm, KCACHE, KCACHE, i32imm, i32imm, i32imm, i32imm, /* CF_ALU_CONTINUE */ i32imm, i32imm, i32imm, KCACHE, KCACHE, i32imm, i32imm, i32imm, i32imm, /* CF_ALU_ELSE_AFTER */ i32imm, i32imm, i32imm, KCACHE, KCACHE, i32imm, i32imm, i32imm, i32imm, /* CF_ALU_POP_AFTER */ i32imm, i32imm, i32imm, KCACHE, KCACHE, i32imm, i32imm, i32imm, i32imm, /* CF_ALU_PUSH_BEFORE */ i32imm, i32imm, i32imm, KCACHE, KCACHE, i32imm, i32imm, i32imm, i32imm, /* CF_CALL_FS_EG */ /* CF_CALL_FS_R600 */ /* CF_CONTINUE_EG */ i32imm, /* CF_CONTINUE_R600 */ i32imm, /* CF_ELSE_EG */ i32imm, i32imm, /* CF_ELSE_R600 */ i32imm, i32imm, /* CF_END_CM */ /* CF_END_EG */ /* CF_END_R600 */ /* CF_JUMP_EG */ i32imm, i32imm, /* CF_JUMP_R600 */ i32imm, i32imm, /* CF_PUSH_EG */ i32imm, i32imm, /* CF_PUSH_ELSE_R600 */ i32imm, /* CF_TC_EG */ i32imm, i32imm, /* CF_TC_R600 */ i32imm, i32imm, /* CF_VC_EG */ i32imm, i32imm, /* CF_VC_R600 */ i32imm, i32imm, /* CNDE_INT */ R600_Reg32, REL, CLAMP, R600_Reg32, NEG, REL, SEL, R600_Reg32, NEG, REL, SEL, R600_Reg32, NEG, REL, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, /* CNDE_eg */ R600_Reg32, REL, CLAMP, R600_Reg32, NEG, REL, SEL, R600_Reg32, NEG, REL, SEL, R600_Reg32, NEG, REL, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, /* CNDE_r600 */ R600_Reg32, REL, CLAMP, R600_Reg32, NEG, REL, SEL, R600_Reg32, NEG, REL, SEL, R600_Reg32, NEG, REL, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, /* CNDGE_INT */ R600_Reg32, REL, CLAMP, R600_Reg32, NEG, REL, SEL, R600_Reg32, NEG, REL, SEL, R600_Reg32, NEG, REL, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, /* CNDGE_eg */ R600_Reg32, REL, CLAMP, R600_Reg32, NEG, REL, SEL, R600_Reg32, NEG, REL, SEL, R600_Reg32, NEG, REL, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, /* CNDGE_r600 */ R600_Reg32, REL, CLAMP, R600_Reg32, NEG, REL, SEL, R600_Reg32, NEG, REL, SEL, R600_Reg32, NEG, REL, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, /* CNDGT_INT */ R600_Reg32, REL, CLAMP, R600_Reg32, NEG, REL, SEL, R600_Reg32, NEG, REL, SEL, R600_Reg32, NEG, REL, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, /* CNDGT_eg */ R600_Reg32, REL, CLAMP, R600_Reg32, NEG, REL, SEL, R600_Reg32, NEG, REL, SEL, R600_Reg32, NEG, REL, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, /* CNDGT_r600 */ R600_Reg32, REL, CLAMP, R600_Reg32, NEG, REL, SEL, R600_Reg32, NEG, REL, SEL, R600_Reg32, NEG, REL, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, /* COS_cm */ R600_Reg32, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, /* COS_eg */ R600_Reg32, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, /* COS_r600 */ R600_Reg32, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, /* COS_r700 */ R600_Reg32, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, /* CUBE_eg_real */ R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, /* CUBE_r600_real */ R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, /* DOT4_eg */ R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, /* DOT4_r600 */ R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, /* EG_ExportBuf */ R600_Reg128, i32imm, i32imm, i32imm, i32imm, i32imm, i32imm, /* EG_ExportSwz */ R600_Reg128, i32imm, i32imm, RSel, RSel, RSel, RSel, i32imm, i32imm, /* END_LOOP_EG */ i32imm, /* END_LOOP_R600 */ i32imm, /* EXP_IEEE_cm */ R600_Reg32, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, /* EXP_IEEE_eg */ R600_Reg32, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, /* EXP_IEEE_r600 */ R600_Reg32, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, /* FETCH_CLAUSE */ i32imm, /* FFBH_UINT */ R600_Reg32, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, /* FFBL_INT */ R600_Reg32, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, /* FLOOR */ R600_Reg32, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, /* FLT16_TO_FLT32 */ R600_Reg32, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, /* FLT32_TO_FLT16 */ R600_Reg32, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, /* FLT_TO_INT_eg */ R600_Reg32, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, /* FLT_TO_INT_r600 */ R600_Reg32, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, /* FLT_TO_UINT_eg */ R600_Reg32, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, /* FLT_TO_UINT_r600 */ R600_Reg32, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, /* FMA_eg */ R600_Reg32, REL, CLAMP, R600_Reg32, NEG, REL, SEL, R600_Reg32, NEG, REL, SEL, R600_Reg32, NEG, REL, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, /* FRACT */ R600_Reg32, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, /* GROUP_BARRIER */ /* INTERP_LOAD_P0 */ R600_Reg32, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, /* INTERP_PAIR_XY */ R600_TReg32_X, R600_TReg32_Y, i32imm, R600_TReg32_Y, R600_TReg32_X, /* INTERP_PAIR_ZW */ R600_TReg32_Z, R600_TReg32_W, i32imm, R600_TReg32_Y, R600_TReg32_X, /* INTERP_VEC_LOAD */ R600_Reg128, i32imm, /* INTERP_XY */ R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, /* INTERP_ZW */ R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, /* INT_TO_FLT_eg */ R600_Reg32, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, /* INT_TO_FLT_r600 */ R600_Reg32, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, /* KILLGT */ R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, /* LDS_ADD */ R600_Reg32, REL, SEL, R600_Reg32, REL, SEL, LAST, R600_Predicate, BANK_SWIZZLE, /* LDS_ADD_RET */ R600_Reg32, R600_Reg32, REL, SEL, R600_Reg32, REL, SEL, LAST, R600_Predicate, BANK_SWIZZLE, /* LDS_AND */ R600_Reg32, REL, SEL, R600_Reg32, REL, SEL, LAST, R600_Predicate, BANK_SWIZZLE, /* LDS_AND_RET */ R600_Reg32, R600_Reg32, REL, SEL, R600_Reg32, REL, SEL, LAST, R600_Predicate, BANK_SWIZZLE, /* LDS_BYTE_READ_RET */ R600_Reg32, R600_Reg32, REL, SEL, LAST, R600_Predicate, BANK_SWIZZLE, /* LDS_BYTE_WRITE */ R600_Reg32, REL, SEL, R600_Reg32, REL, SEL, LAST, R600_Predicate, BANK_SWIZZLE, /* LDS_CMPST */ R600_Reg32, REL, SEL, R600_Reg32, REL, SEL, R600_Reg32, REL, SEL, LAST, R600_Predicate, BANK_SWIZZLE, /* LDS_CMPST_RET */ R600_Reg32, R600_Reg32, REL, SEL, R600_Reg32, REL, SEL, R600_Reg32, REL, SEL, LAST, R600_Predicate, BANK_SWIZZLE, /* LDS_MAX_INT */ R600_Reg32, REL, SEL, R600_Reg32, REL, SEL, LAST, R600_Predicate, BANK_SWIZZLE, /* LDS_MAX_INT_RET */ R600_Reg32, R600_Reg32, REL, SEL, R600_Reg32, REL, SEL, LAST, R600_Predicate, BANK_SWIZZLE, /* LDS_MAX_UINT */ R600_Reg32, REL, SEL, R600_Reg32, REL, SEL, LAST, R600_Predicate, BANK_SWIZZLE, /* LDS_MAX_UINT_RET */ R600_Reg32, R600_Reg32, REL, SEL, R600_Reg32, REL, SEL, LAST, R600_Predicate, BANK_SWIZZLE, /* LDS_MIN_INT */ R600_Reg32, REL, SEL, R600_Reg32, REL, SEL, LAST, R600_Predicate, BANK_SWIZZLE, /* LDS_MIN_INT_RET */ R600_Reg32, R600_Reg32, REL, SEL, R600_Reg32, REL, SEL, LAST, R600_Predicate, BANK_SWIZZLE, /* LDS_MIN_UINT */ R600_Reg32, REL, SEL, R600_Reg32, REL, SEL, LAST, R600_Predicate, BANK_SWIZZLE, /* LDS_MIN_UINT_RET */ R600_Reg32, R600_Reg32, REL, SEL, R600_Reg32, REL, SEL, LAST, R600_Predicate, BANK_SWIZZLE, /* LDS_OR */ R600_Reg32, REL, SEL, R600_Reg32, REL, SEL, LAST, R600_Predicate, BANK_SWIZZLE, /* LDS_OR_RET */ R600_Reg32, R600_Reg32, REL, SEL, R600_Reg32, REL, SEL, LAST, R600_Predicate, BANK_SWIZZLE, /* LDS_READ_RET */ R600_Reg32, R600_Reg32, REL, SEL, LAST, R600_Predicate, BANK_SWIZZLE, /* LDS_SHORT_READ_RET */ R600_Reg32, R600_Reg32, REL, SEL, LAST, R600_Predicate, BANK_SWIZZLE, /* LDS_SHORT_WRITE */ R600_Reg32, REL, SEL, R600_Reg32, REL, SEL, LAST, R600_Predicate, BANK_SWIZZLE, /* LDS_SUB */ R600_Reg32, REL, SEL, R600_Reg32, REL, SEL, LAST, R600_Predicate, BANK_SWIZZLE, /* LDS_SUB_RET */ R600_Reg32, R600_Reg32, REL, SEL, R600_Reg32, REL, SEL, LAST, R600_Predicate, BANK_SWIZZLE, /* LDS_UBYTE_READ_RET */ R600_Reg32, R600_Reg32, REL, SEL, LAST, R600_Predicate, BANK_SWIZZLE, /* LDS_USHORT_READ_RET */ R600_Reg32, R600_Reg32, REL, SEL, LAST, R600_Predicate, BANK_SWIZZLE, /* LDS_WRITE */ R600_Reg32, REL, SEL, R600_Reg32, REL, SEL, LAST, R600_Predicate, BANK_SWIZZLE, /* LDS_WRXCHG */ R600_Reg32, REL, SEL, R600_Reg32, REL, SEL, LAST, R600_Predicate, BANK_SWIZZLE, /* LDS_WRXCHG_RET */ R600_Reg32, R600_Reg32, REL, SEL, R600_Reg32, REL, SEL, LAST, R600_Predicate, BANK_SWIZZLE, /* LDS_XOR */ R600_Reg32, REL, SEL, R600_Reg32, REL, SEL, LAST, R600_Predicate, BANK_SWIZZLE, /* LDS_XOR_RET */ R600_Reg32, R600_Reg32, REL, SEL, R600_Reg32, REL, SEL, LAST, R600_Predicate, BANK_SWIZZLE, /* LITERALS */ LITERAL, LITERAL, /* LOG_CLAMPED_eg */ R600_Reg32, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, /* LOG_CLAMPED_r600 */ R600_Reg32, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, /* LOG_IEEE_cm */ R600_Reg32, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, /* LOG_IEEE_eg */ R600_Reg32, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, /* LOG_IEEE_r600 */ R600_Reg32, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, /* LOOP_BREAK_EG */ i32imm, /* LOOP_BREAK_R600 */ i32imm, /* LSHL_eg */ R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, /* LSHL_r600 */ R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, /* LSHR_eg */ R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, /* LSHR_r600 */ R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, /* MAX */ R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, /* MAX_DX10 */ R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, /* MAX_INT */ R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, /* MAX_UINT */ R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, /* MIN */ R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, /* MIN_DX10 */ R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, /* MIN_INT */ R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, /* MIN_UINT */ R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, /* MOV */ R600_Reg32, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, /* MOVA_INT_eg */ R600_Reg32, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, /* MUL */ R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, /* MULADD_IEEE_eg */ R600_Reg32, REL, CLAMP, R600_Reg32, NEG, REL, SEL, R600_Reg32, NEG, REL, SEL, R600_Reg32, NEG, REL, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, /* MULADD_IEEE_r600 */ R600_Reg32, REL, CLAMP, R600_Reg32, NEG, REL, SEL, R600_Reg32, NEG, REL, SEL, R600_Reg32, NEG, REL, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, /* MULADD_INT24_cm */ R600_Reg32, REL, CLAMP, R600_Reg32, NEG, REL, SEL, R600_Reg32, NEG, REL, SEL, R600_Reg32, NEG, REL, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, /* MULADD_UINT24_eg */ R600_Reg32, REL, CLAMP, R600_Reg32, NEG, REL, SEL, R600_Reg32, NEG, REL, SEL, R600_Reg32, NEG, REL, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, /* MULADD_eg */ R600_Reg32, REL, CLAMP, R600_Reg32, NEG, REL, SEL, R600_Reg32, NEG, REL, SEL, R600_Reg32, NEG, REL, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, /* MULADD_r600 */ R600_Reg32, REL, CLAMP, R600_Reg32, NEG, REL, SEL, R600_Reg32, NEG, REL, SEL, R600_Reg32, NEG, REL, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, /* MULHI_INT_cm */ R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, /* MULHI_INT_cm24 */ R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, /* MULHI_INT_eg */ R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, /* MULHI_INT_r600 */ R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, /* MULHI_UINT24_eg */ R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, /* MULHI_UINT_cm */ R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, /* MULHI_UINT_cm24 */ R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, /* MULHI_UINT_eg */ R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, /* MULHI_UINT_r600 */ R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, /* MULLO_INT_cm */ R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, /* MULLO_INT_eg */ R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, /* MULLO_INT_r600 */ R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, /* MULLO_UINT_cm */ R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, /* MULLO_UINT_eg */ R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, /* MULLO_UINT_r600 */ R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, /* MUL_IEEE */ R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, /* MUL_INT24_cm */ R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, /* MUL_LIT_eg */ R600_Reg32, REL, CLAMP, R600_Reg32, NEG, REL, SEL, R600_Reg32, NEG, REL, SEL, R600_Reg32, NEG, REL, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, /* MUL_LIT_r600 */ R600_Reg32, REL, CLAMP, R600_Reg32, NEG, REL, SEL, R600_Reg32, NEG, REL, SEL, R600_Reg32, NEG, REL, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, /* MUL_UINT24_eg */ R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, /* NOT_INT */ R600_Reg32, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, /* OR_INT */ R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, /* PAD */ /* POP_EG */ i32imm, i32imm, /* POP_R600 */ i32imm, i32imm, /* PRED_SETE */ R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, /* PRED_SETE_INT */ R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, /* PRED_SETGE */ R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, /* PRED_SETGE_INT */ R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, /* PRED_SETGT */ R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, /* PRED_SETGT_INT */ R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, /* PRED_SETNE */ R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, /* PRED_SETNE_INT */ R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, /* R600_ExportBuf */ R600_Reg128, i32imm, i32imm, i32imm, i32imm, i32imm, i32imm, /* R600_ExportSwz */ R600_Reg128, i32imm, i32imm, RSel, RSel, RSel, RSel, i32imm, i32imm, /* RAT_ATOMIC_ADD_NORET */ R600_Reg128, R600_Reg128, R600_TReg32_X, /* RAT_ATOMIC_ADD_RTN */ R600_Reg128, R600_Reg128, R600_TReg32_X, /* RAT_ATOMIC_AND_NORET */ R600_Reg128, R600_Reg128, R600_TReg32_X, /* RAT_ATOMIC_AND_RTN */ R600_Reg128, R600_Reg128, R600_TReg32_X, /* RAT_ATOMIC_CMPXCHG_INT_NORET */ R600_Reg128, R600_Reg128, R600_TReg32_X, /* RAT_ATOMIC_CMPXCHG_INT_RTN */ R600_Reg128, R600_Reg128, R600_TReg32_X, /* RAT_ATOMIC_DEC_UINT_NORET */ R600_Reg128, R600_Reg128, R600_TReg32_X, /* RAT_ATOMIC_DEC_UINT_RTN */ R600_Reg128, R600_Reg128, R600_TReg32_X, /* RAT_ATOMIC_INC_UINT_NORET */ R600_Reg128, R600_Reg128, R600_TReg32_X, /* RAT_ATOMIC_INC_UINT_RTN */ R600_Reg128, R600_Reg128, R600_TReg32_X, /* RAT_ATOMIC_MAX_INT_NORET */ R600_Reg128, R600_Reg128, R600_TReg32_X, /* RAT_ATOMIC_MAX_INT_RTN */ R600_Reg128, R600_Reg128, R600_TReg32_X, /* RAT_ATOMIC_MAX_UINT_NORET */ R600_Reg128, R600_Reg128, R600_TReg32_X, /* RAT_ATOMIC_MAX_UINT_RTN */ R600_Reg128, R600_Reg128, R600_TReg32_X, /* RAT_ATOMIC_MIN_INT_NORET */ R600_Reg128, R600_Reg128, R600_TReg32_X, /* RAT_ATOMIC_MIN_INT_RTN */ R600_Reg128, R600_Reg128, R600_TReg32_X, /* RAT_ATOMIC_MIN_UINT_NORET */ R600_Reg128, R600_Reg128, R600_TReg32_X, /* RAT_ATOMIC_MIN_UINT_RTN */ R600_Reg128, R600_Reg128, R600_TReg32_X, /* RAT_ATOMIC_OR_NORET */ R600_Reg128, R600_Reg128, R600_TReg32_X, /* RAT_ATOMIC_OR_RTN */ R600_Reg128, R600_Reg128, R600_TReg32_X, /* RAT_ATOMIC_RSUB_NORET */ R600_Reg128, R600_Reg128, R600_TReg32_X, /* RAT_ATOMIC_RSUB_RTN */ R600_Reg128, R600_Reg128, R600_TReg32_X, /* RAT_ATOMIC_SUB_NORET */ R600_Reg128, R600_Reg128, R600_TReg32_X, /* RAT_ATOMIC_SUB_RTN */ R600_Reg128, R600_Reg128, R600_TReg32_X, /* RAT_ATOMIC_XCHG_INT_NORET */ R600_Reg128, R600_Reg128, R600_TReg32_X, /* RAT_ATOMIC_XCHG_INT_RTN */ R600_Reg128, R600_Reg128, R600_TReg32_X, /* RAT_ATOMIC_XOR_NORET */ R600_Reg128, R600_Reg128, R600_TReg32_X, /* RAT_ATOMIC_XOR_RTN */ R600_Reg128, R600_Reg128, R600_TReg32_X, /* RAT_MSKOR */ R600_Reg128, R600_TReg32_X, /* RAT_STORE_DWORD128 */ R600_Reg128, R600_TReg32_X, /* RAT_STORE_DWORD32 */ R600_TReg32_X, R600_TReg32_X, /* RAT_STORE_DWORD64 */ R600_Reg64, R600_TReg32_X, /* RAT_STORE_TYPED_cm */ R600_Reg128, R600_Reg128, i32imm, InstFlag, /* RAT_STORE_TYPED_eg */ R600_Reg128, R600_Reg128, i32imm, InstFlag, /* RAT_WRITE_CACHELESS_128_eg */ R600_Reg128, R600_TReg32_X, InstFlag, /* RAT_WRITE_CACHELESS_32_eg */ R600_TReg32_X, R600_TReg32_X, InstFlag, /* RAT_WRITE_CACHELESS_64_eg */ R600_Reg64, R600_TReg32_X, InstFlag, /* RECIPSQRT_CLAMPED_cm */ R600_Reg32, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, /* RECIPSQRT_CLAMPED_eg */ R600_Reg32, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, /* RECIPSQRT_CLAMPED_r600 */ R600_Reg32, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, /* RECIPSQRT_IEEE_cm */ R600_Reg32, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, /* RECIPSQRT_IEEE_eg */ R600_Reg32, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, /* RECIPSQRT_IEEE_r600 */ R600_Reg32, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, /* RECIP_CLAMPED_cm */ R600_Reg32, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, /* RECIP_CLAMPED_eg */ R600_Reg32, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, /* RECIP_CLAMPED_r600 */ R600_Reg32, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, /* RECIP_IEEE_cm */ R600_Reg32, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, /* RECIP_IEEE_eg */ R600_Reg32, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, /* RECIP_IEEE_r600 */ R600_Reg32, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, /* RECIP_UINT_eg */ R600_Reg32, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, /* RECIP_UINT_r600 */ R600_Reg32, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, /* RNDNE */ R600_Reg32, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, /* SETE */ R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, /* SETE_DX10 */ R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, /* SETE_INT */ R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, /* SETGE_DX10 */ R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, /* SETGE_INT */ R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, /* SETGE_UINT */ R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, /* SETGT_DX10 */ R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, /* SETGT_INT */ R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, /* SETGT_UINT */ R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, /* SETNE_DX10 */ R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, /* SETNE_INT */ R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, /* SGE */ R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, /* SGT */ R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, /* SIN_cm */ R600_Reg32, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, /* SIN_eg */ R600_Reg32, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, /* SIN_r600 */ R600_Reg32, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, /* SIN_r700 */ R600_Reg32, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, /* SNE */ R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, /* SUBB_UINT */ R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, /* SUB_INT */ R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, /* TEX_GET_GRADIENTS_H */ R600_Reg128, R600_Reg128, RSel, RSel, RSel, RSel, i32imm, i32imm, i32imm, RSel, RSel, RSel, RSel, i32imm, i32imm, CT, CT, CT, CT, /* TEX_GET_GRADIENTS_V */ R600_Reg128, R600_Reg128, RSel, RSel, RSel, RSel, i32imm, i32imm, i32imm, RSel, RSel, RSel, RSel, i32imm, i32imm, CT, CT, CT, CT, /* TEX_GET_TEXTURE_RESINFO */ R600_Reg128, R600_Reg128, RSel, RSel, RSel, RSel, i32imm, i32imm, i32imm, RSel, RSel, RSel, RSel, i32imm, i32imm, CT, CT, CT, CT, /* TEX_LD */ R600_Reg128, R600_Reg128, RSel, RSel, RSel, RSel, i32imm, i32imm, i32imm, RSel, RSel, RSel, RSel, i32imm, i32imm, CT, CT, CT, CT, /* TEX_LDPTR */ R600_Reg128, R600_Reg128, RSel, RSel, RSel, RSel, i32imm, i32imm, i32imm, RSel, RSel, RSel, RSel, i32imm, i32imm, CT, CT, CT, CT, /* TEX_SAMPLE */ R600_Reg128, R600_Reg128, RSel, RSel, RSel, RSel, i32imm, i32imm, i32imm, RSel, RSel, RSel, RSel, i32imm, i32imm, CT, CT, CT, CT, /* TEX_SAMPLE_C */ R600_Reg128, R600_Reg128, RSel, RSel, RSel, RSel, i32imm, i32imm, i32imm, RSel, RSel, RSel, RSel, i32imm, i32imm, CT, CT, CT, CT, /* TEX_SAMPLE_C_G */ R600_Reg128, R600_Reg128, RSel, RSel, RSel, RSel, i32imm, i32imm, i32imm, RSel, RSel, RSel, RSel, i32imm, i32imm, CT, CT, CT, CT, /* TEX_SAMPLE_C_L */ R600_Reg128, R600_Reg128, RSel, RSel, RSel, RSel, i32imm, i32imm, i32imm, RSel, RSel, RSel, RSel, i32imm, i32imm, CT, CT, CT, CT, /* TEX_SAMPLE_C_LB */ R600_Reg128, R600_Reg128, RSel, RSel, RSel, RSel, i32imm, i32imm, i32imm, RSel, RSel, RSel, RSel, i32imm, i32imm, CT, CT, CT, CT, /* TEX_SAMPLE_G */ R600_Reg128, R600_Reg128, RSel, RSel, RSel, RSel, i32imm, i32imm, i32imm, RSel, RSel, RSel, RSel, i32imm, i32imm, CT, CT, CT, CT, /* TEX_SAMPLE_L */ R600_Reg128, R600_Reg128, RSel, RSel, RSel, RSel, i32imm, i32imm, i32imm, RSel, RSel, RSel, RSel, i32imm, i32imm, CT, CT, CT, CT, /* TEX_SAMPLE_LB */ R600_Reg128, R600_Reg128, RSel, RSel, RSel, RSel, i32imm, i32imm, i32imm, RSel, RSel, RSel, RSel, i32imm, i32imm, CT, CT, CT, CT, /* TEX_SET_GRADIENTS_H */ R600_Reg128, R600_Reg128, RSel, RSel, RSel, RSel, i32imm, i32imm, i32imm, RSel, RSel, RSel, RSel, i32imm, i32imm, CT, CT, CT, CT, /* TEX_SET_GRADIENTS_V */ R600_Reg128, R600_Reg128, RSel, RSel, RSel, RSel, i32imm, i32imm, i32imm, RSel, RSel, RSel, RSel, i32imm, i32imm, CT, CT, CT, CT, /* TEX_VTX_CONSTBUF */ R600_Reg128, R600_TReg32_X, i32imm, i32imm, /* TEX_VTX_TEXBUF */ R600_Reg128, R600_TReg32_X, i32imm, i32imm, /* TRUNC */ R600_Reg32, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, /* UINT_TO_FLT_eg */ R600_Reg32, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, /* UINT_TO_FLT_r600 */ R600_Reg32, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, /* VTX_READ_128_cm */ R600_Reg128, R600_TReg32_X, i32imm, i8imm, /* VTX_READ_128_eg */ R600_Reg128, R600_TReg32_X, i32imm, i8imm, /* VTX_READ_16_cm */ R600_TReg32_X, R600_TReg32_X, i32imm, i8imm, /* VTX_READ_16_eg */ R600_TReg32_X, R600_TReg32_X, i32imm, i8imm, /* VTX_READ_32_cm */ R600_TReg32_X, R600_TReg32_X, i32imm, i8imm, /* VTX_READ_32_eg */ R600_TReg32_X, R600_TReg32_X, i32imm, i8imm, /* VTX_READ_64_cm */ R600_Reg64, R600_TReg32_X, i32imm, i8imm, /* VTX_READ_64_eg */ R600_Reg64, R600_TReg32_X, i32imm, i8imm, /* VTX_READ_8_cm */ R600_TReg32_X, R600_TReg32_X, i32imm, i8imm, /* VTX_READ_8_eg */ R600_TReg32_X, R600_TReg32_X, i32imm, i8imm, /* WHILE_LOOP_EG */ i32imm, /* WHILE_LOOP_R600 */ i32imm, /* XOR_INT */ R600_Reg32, UEM, UP, WRITE, OMOD, REL, CLAMP, R600_Reg32, NEG, REL, ABS, SEL, R600_Reg32, NEG, REL, ABS, SEL, LAST, R600_Predicate, LITERAL, BANK_SWIZZLE, }; return OpcodeOperandTypes[Offsets[Opcode] + OpIdx]; } } // end namespace R600 } // end namespace llvm #endif // GET_INSTRINFO_OPERAND_TYPE #ifdef GET_INSTRINFO_MEM_OPERAND_SIZE #undef GET_INSTRINFO_MEM_OPERAND_SIZE namespace llvm { namespace R600 { LLVM_READONLY static int getMemOperandSize(int OpType) { switch (OpType) { default: return 0; } } } // end namespace R600 } // end namespace llvm #endif // GET_INSTRINFO_MEM_OPERAND_SIZE #ifdef GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP #undef GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP namespace llvm { namespace R600 { LLVM_READONLY static unsigned getLogicalOperandSize(uint16_t Opcode, uint16_t LogicalOpIdx) { return LogicalOpIdx; } LLVM_READONLY static inline unsigned getLogicalOperandIdx(uint16_t Opcode, uint16_t LogicalOpIdx) { auto S = 0U; for (auto i = 0U; i < LogicalOpIdx; ++i) S += getLogicalOperandSize(Opcode, i); return S; } } // end namespace R600 } // end namespace llvm #endif // GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP #ifdef GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP #undef GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP namespace llvm { namespace R600 { LLVM_READONLY static int getLogicalOperandType(uint16_t Opcode, uint16_t LogicalOpIdx) { return -1; } } // end namespace R600 } // end namespace llvm #endif // GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP #ifdef GET_INSTRINFO_MC_HELPER_DECLS #undef GET_INSTRINFO_MC_HELPER_DECLS namespace llvm { class MCInst; class FeatureBitset; namespace R600_MC { void verifyInstructionPredicates(unsigned Opcode, const FeatureBitset &Features); } // end namespace R600_MC } // end namespace llvm #endif // GET_INSTRINFO_MC_HELPER_DECLS #ifdef GET_INSTRINFO_MC_HELPERS #undef GET_INSTRINFO_MC_HELPERS namespace llvm { namespace R600_MC { } // end namespace R600_MC } // end namespace llvm #endif // GET_GENISTRINFO_MC_HELPERS #if (defined(ENABLE_INSTR_PREDICATE_VERIFIER) && !defined(NDEBUG)) ||\ defined(GET_AVAILABLE_OPCODE_CHECKER) #define GET_COMPUTE_FEATURES #endif #ifdef GET_COMPUTE_FEATURES #undef GET_COMPUTE_FEATURES namespace llvm { namespace R600_MC { // Bits for subtarget features that participate in instruction matching. enum SubtargetFeatureBits : uint8_t { }; inline FeatureBitset computeAvailableFeatures(const FeatureBitset &FB) { FeatureBitset Features; return Features; } inline FeatureBitset computeRequiredFeatures(unsigned Opcode) { enum : uint8_t { CEFBS_None, }; static constexpr FeatureBitset FeatureBitsets[] = { {}, // CEFBS_None }; static constexpr uint8_t RequiredFeaturesRefs[] = { CEFBS_None, // PHI = 0 CEFBS_None, // INLINEASM = 1 CEFBS_None, // INLINEASM_BR = 2 CEFBS_None, // CFI_INSTRUCTION = 3 CEFBS_None, // EH_LABEL = 4 CEFBS_None, // GC_LABEL = 5 CEFBS_None, // ANNOTATION_LABEL = 6 CEFBS_None, // KILL = 7 CEFBS_None, // EXTRACT_SUBREG = 8 CEFBS_None, // INSERT_SUBREG = 9 CEFBS_None, // IMPLICIT_DEF = 10 CEFBS_None, // SUBREG_TO_REG = 11 CEFBS_None, // COPY_TO_REGCLASS = 12 CEFBS_None, // DBG_VALUE = 13 CEFBS_None, // DBG_VALUE_LIST = 14 CEFBS_None, // DBG_INSTR_REF = 15 CEFBS_None, // DBG_PHI = 16 CEFBS_None, // DBG_LABEL = 17 CEFBS_None, // REG_SEQUENCE = 18 CEFBS_None, // COPY = 19 CEFBS_None, // BUNDLE = 20 CEFBS_None, // LIFETIME_START = 21 CEFBS_None, // LIFETIME_END = 22 CEFBS_None, // PSEUDO_PROBE = 23 CEFBS_None, // ARITH_FENCE = 24 CEFBS_None, // STACKMAP = 25 CEFBS_None, // FENTRY_CALL = 26 CEFBS_None, // PATCHPOINT = 27 CEFBS_None, // LOAD_STACK_GUARD = 28 CEFBS_None, // PREALLOCATED_SETUP = 29 CEFBS_None, // PREALLOCATED_ARG = 30 CEFBS_None, // STATEPOINT = 31 CEFBS_None, // LOCAL_ESCAPE = 32 CEFBS_None, // FAULTING_OP = 33 CEFBS_None, // PATCHABLE_OP = 34 CEFBS_None, // PATCHABLE_FUNCTION_ENTER = 35 CEFBS_None, // PATCHABLE_RET = 36 CEFBS_None, // PATCHABLE_FUNCTION_EXIT = 37 CEFBS_None, // PATCHABLE_TAIL_CALL = 38 CEFBS_None, // PATCHABLE_EVENT_CALL = 39 CEFBS_None, // PATCHABLE_TYPED_EVENT_CALL = 40 CEFBS_None, // ICALL_BRANCH_FUNNEL = 41 CEFBS_None, // FAKE_USE = 42 CEFBS_None, // MEMBARRIER = 43 CEFBS_None, // JUMP_TABLE_DEBUG_INFO = 44 CEFBS_None, // CONVERGENCECTRL_ENTRY = 45 CEFBS_None, // CONVERGENCECTRL_ANCHOR = 46 CEFBS_None, // CONVERGENCECTRL_LOOP = 47 CEFBS_None, // CONVERGENCECTRL_GLUE = 48 CEFBS_None, // G_ASSERT_SEXT = 49 CEFBS_None, // G_ASSERT_ZEXT = 50 CEFBS_None, // G_ASSERT_ALIGN = 51 CEFBS_None, // G_ADD = 52 CEFBS_None, // G_SUB = 53 CEFBS_None, // G_MUL = 54 CEFBS_None, // G_SDIV = 55 CEFBS_None, // G_UDIV = 56 CEFBS_None, // G_SREM = 57 CEFBS_None, // G_UREM = 58 CEFBS_None, // G_SDIVREM = 59 CEFBS_None, // G_UDIVREM = 60 CEFBS_None, // G_AND = 61 CEFBS_None, // G_OR = 62 CEFBS_None, // G_XOR = 63 CEFBS_None, // G_IMPLICIT_DEF = 64 CEFBS_None, // G_PHI = 65 CEFBS_None, // G_FRAME_INDEX = 66 CEFBS_None, // G_GLOBAL_VALUE = 67 CEFBS_None, // G_PTRAUTH_GLOBAL_VALUE = 68 CEFBS_None, // G_CONSTANT_POOL = 69 CEFBS_None, // G_EXTRACT = 70 CEFBS_None, // G_UNMERGE_VALUES = 71 CEFBS_None, // G_INSERT = 72 CEFBS_None, // G_MERGE_VALUES = 73 CEFBS_None, // G_BUILD_VECTOR = 74 CEFBS_None, // G_BUILD_VECTOR_TRUNC = 75 CEFBS_None, // G_CONCAT_VECTORS = 76 CEFBS_None, // G_PTRTOINT = 77 CEFBS_None, // G_INTTOPTR = 78 CEFBS_None, // G_BITCAST = 79 CEFBS_None, // G_FREEZE = 80 CEFBS_None, // G_CONSTANT_FOLD_BARRIER = 81 CEFBS_None, // G_INTRINSIC_FPTRUNC_ROUND = 82 CEFBS_None, // G_INTRINSIC_TRUNC = 83 CEFBS_None, // G_INTRINSIC_ROUND = 84 CEFBS_None, // G_INTRINSIC_LRINT = 85 CEFBS_None, // G_INTRINSIC_LLRINT = 86 CEFBS_None, // G_INTRINSIC_ROUNDEVEN = 87 CEFBS_None, // G_READCYCLECOUNTER = 88 CEFBS_None, // G_READSTEADYCOUNTER = 89 CEFBS_None, // G_LOAD = 90 CEFBS_None, // G_SEXTLOAD = 91 CEFBS_None, // G_ZEXTLOAD = 92 CEFBS_None, // G_INDEXED_LOAD = 93 CEFBS_None, // G_INDEXED_SEXTLOAD = 94 CEFBS_None, // G_INDEXED_ZEXTLOAD = 95 CEFBS_None, // G_STORE = 96 CEFBS_None, // G_INDEXED_STORE = 97 CEFBS_None, // G_ATOMIC_CMPXCHG_WITH_SUCCESS = 98 CEFBS_None, // G_ATOMIC_CMPXCHG = 99 CEFBS_None, // G_ATOMICRMW_XCHG = 100 CEFBS_None, // G_ATOMICRMW_ADD = 101 CEFBS_None, // G_ATOMICRMW_SUB = 102 CEFBS_None, // G_ATOMICRMW_AND = 103 CEFBS_None, // G_ATOMICRMW_NAND = 104 CEFBS_None, // G_ATOMICRMW_OR = 105 CEFBS_None, // G_ATOMICRMW_XOR = 106 CEFBS_None, // G_ATOMICRMW_MAX = 107 CEFBS_None, // G_ATOMICRMW_MIN = 108 CEFBS_None, // G_ATOMICRMW_UMAX = 109 CEFBS_None, // G_ATOMICRMW_UMIN = 110 CEFBS_None, // G_ATOMICRMW_FADD = 111 CEFBS_None, // G_ATOMICRMW_FSUB = 112 CEFBS_None, // G_ATOMICRMW_FMAX = 113 CEFBS_None, // G_ATOMICRMW_FMIN = 114 CEFBS_None, // G_ATOMICRMW_UINC_WRAP = 115 CEFBS_None, // G_ATOMICRMW_UDEC_WRAP = 116 CEFBS_None, // G_FENCE = 117 CEFBS_None, // G_PREFETCH = 118 CEFBS_None, // G_BRCOND = 119 CEFBS_None, // G_BRINDIRECT = 120 CEFBS_None, // G_INVOKE_REGION_START = 121 CEFBS_None, // G_INTRINSIC = 122 CEFBS_None, // G_INTRINSIC_W_SIDE_EFFECTS = 123 CEFBS_None, // G_INTRINSIC_CONVERGENT = 124 CEFBS_None, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS = 125 CEFBS_None, // G_ANYEXT = 126 CEFBS_None, // G_TRUNC = 127 CEFBS_None, // G_CONSTANT = 128 CEFBS_None, // G_FCONSTANT = 129 CEFBS_None, // G_VASTART = 130 CEFBS_None, // G_VAARG = 131 CEFBS_None, // G_SEXT = 132 CEFBS_None, // G_SEXT_INREG = 133 CEFBS_None, // G_ZEXT = 134 CEFBS_None, // G_SHL = 135 CEFBS_None, // G_LSHR = 136 CEFBS_None, // G_ASHR = 137 CEFBS_None, // G_FSHL = 138 CEFBS_None, // G_FSHR = 139 CEFBS_None, // G_ROTR = 140 CEFBS_None, // G_ROTL = 141 CEFBS_None, // G_ICMP = 142 CEFBS_None, // G_FCMP = 143 CEFBS_None, // G_SCMP = 144 CEFBS_None, // G_UCMP = 145 CEFBS_None, // G_SELECT = 146 CEFBS_None, // G_UADDO = 147 CEFBS_None, // G_UADDE = 148 CEFBS_None, // G_USUBO = 149 CEFBS_None, // G_USUBE = 150 CEFBS_None, // G_SADDO = 151 CEFBS_None, // G_SADDE = 152 CEFBS_None, // G_SSUBO = 153 CEFBS_None, // G_SSUBE = 154 CEFBS_None, // G_UMULO = 155 CEFBS_None, // G_SMULO = 156 CEFBS_None, // G_UMULH = 157 CEFBS_None, // G_SMULH = 158 CEFBS_None, // G_UADDSAT = 159 CEFBS_None, // G_SADDSAT = 160 CEFBS_None, // G_USUBSAT = 161 CEFBS_None, // G_SSUBSAT = 162 CEFBS_None, // G_USHLSAT = 163 CEFBS_None, // G_SSHLSAT = 164 CEFBS_None, // G_SMULFIX = 165 CEFBS_None, // G_UMULFIX = 166 CEFBS_None, // G_SMULFIXSAT = 167 CEFBS_None, // G_UMULFIXSAT = 168 CEFBS_None, // G_SDIVFIX = 169 CEFBS_None, // G_UDIVFIX = 170 CEFBS_None, // G_SDIVFIXSAT = 171 CEFBS_None, // G_UDIVFIXSAT = 172 CEFBS_None, // G_FADD = 173 CEFBS_None, // G_FSUB = 174 CEFBS_None, // G_FMUL = 175 CEFBS_None, // G_FMA = 176 CEFBS_None, // G_FMAD = 177 CEFBS_None, // G_FDIV = 178 CEFBS_None, // G_FREM = 179 CEFBS_None, // G_FPOW = 180 CEFBS_None, // G_FPOWI = 181 CEFBS_None, // G_FEXP = 182 CEFBS_None, // G_FEXP2 = 183 CEFBS_None, // G_FEXP10 = 184 CEFBS_None, // G_FLOG = 185 CEFBS_None, // G_FLOG2 = 186 CEFBS_None, // G_FLOG10 = 187 CEFBS_None, // G_FLDEXP = 188 CEFBS_None, // G_FFREXP = 189 CEFBS_None, // G_FNEG = 190 CEFBS_None, // G_FPEXT = 191 CEFBS_None, // G_FPTRUNC = 192 CEFBS_None, // G_FPTOSI = 193 CEFBS_None, // G_FPTOUI = 194 CEFBS_None, // G_SITOFP = 195 CEFBS_None, // G_UITOFP = 196 CEFBS_None, // G_FABS = 197 CEFBS_None, // G_FCOPYSIGN = 198 CEFBS_None, // G_IS_FPCLASS = 199 CEFBS_None, // G_FCANONICALIZE = 200 CEFBS_None, // G_FMINNUM = 201 CEFBS_None, // G_FMAXNUM = 202 CEFBS_None, // G_FMINNUM_IEEE = 203 CEFBS_None, // G_FMAXNUM_IEEE = 204 CEFBS_None, // G_FMINIMUM = 205 CEFBS_None, // G_FMAXIMUM = 206 CEFBS_None, // G_GET_FPENV = 207 CEFBS_None, // G_SET_FPENV = 208 CEFBS_None, // G_RESET_FPENV = 209 CEFBS_None, // G_GET_FPMODE = 210 CEFBS_None, // G_SET_FPMODE = 211 CEFBS_None, // G_RESET_FPMODE = 212 CEFBS_None, // G_PTR_ADD = 213 CEFBS_None, // G_PTRMASK = 214 CEFBS_None, // G_SMIN = 215 CEFBS_None, // G_SMAX = 216 CEFBS_None, // G_UMIN = 217 CEFBS_None, // G_UMAX = 218 CEFBS_None, // G_ABS = 219 CEFBS_None, // G_LROUND = 220 CEFBS_None, // G_LLROUND = 221 CEFBS_None, // G_BR = 222 CEFBS_None, // G_BRJT = 223 CEFBS_None, // G_VSCALE = 224 CEFBS_None, // G_INSERT_SUBVECTOR = 225 CEFBS_None, // G_EXTRACT_SUBVECTOR = 226 CEFBS_None, // G_INSERT_VECTOR_ELT = 227 CEFBS_None, // G_EXTRACT_VECTOR_ELT = 228 CEFBS_None, // G_SHUFFLE_VECTOR = 229 CEFBS_None, // G_SPLAT_VECTOR = 230 CEFBS_None, // G_VECTOR_COMPRESS = 231 CEFBS_None, // G_CTTZ = 232 CEFBS_None, // G_CTTZ_ZERO_UNDEF = 233 CEFBS_None, // G_CTLZ = 234 CEFBS_None, // G_CTLZ_ZERO_UNDEF = 235 CEFBS_None, // G_CTPOP = 236 CEFBS_None, // G_BSWAP = 237 CEFBS_None, // G_BITREVERSE = 238 CEFBS_None, // G_FCEIL = 239 CEFBS_None, // G_FCOS = 240 CEFBS_None, // G_FSIN = 241 CEFBS_None, // G_FTAN = 242 CEFBS_None, // G_FACOS = 243 CEFBS_None, // G_FASIN = 244 CEFBS_None, // G_FATAN = 245 CEFBS_None, // G_FCOSH = 246 CEFBS_None, // G_FSINH = 247 CEFBS_None, // G_FTANH = 248 CEFBS_None, // G_FSQRT = 249 CEFBS_None, // G_FFLOOR = 250 CEFBS_None, // G_FRINT = 251 CEFBS_None, // G_FNEARBYINT = 252 CEFBS_None, // G_ADDRSPACE_CAST = 253 CEFBS_None, // G_BLOCK_ADDR = 254 CEFBS_None, // G_JUMP_TABLE = 255 CEFBS_None, // G_DYN_STACKALLOC = 256 CEFBS_None, // G_STACKSAVE = 257 CEFBS_None, // G_STACKRESTORE = 258 CEFBS_None, // G_STRICT_FADD = 259 CEFBS_None, // G_STRICT_FSUB = 260 CEFBS_None, // G_STRICT_FMUL = 261 CEFBS_None, // G_STRICT_FDIV = 262 CEFBS_None, // G_STRICT_FREM = 263 CEFBS_None, // G_STRICT_FMA = 264 CEFBS_None, // G_STRICT_FSQRT = 265 CEFBS_None, // G_STRICT_FLDEXP = 266 CEFBS_None, // G_READ_REGISTER = 267 CEFBS_None, // G_WRITE_REGISTER = 268 CEFBS_None, // G_MEMCPY = 269 CEFBS_None, // G_MEMCPY_INLINE = 270 CEFBS_None, // G_MEMMOVE = 271 CEFBS_None, // G_MEMSET = 272 CEFBS_None, // G_BZERO = 273 CEFBS_None, // G_TRAP = 274 CEFBS_None, // G_DEBUGTRAP = 275 CEFBS_None, // G_UBSANTRAP = 276 CEFBS_None, // G_VECREDUCE_SEQ_FADD = 277 CEFBS_None, // G_VECREDUCE_SEQ_FMUL = 278 CEFBS_None, // G_VECREDUCE_FADD = 279 CEFBS_None, // G_VECREDUCE_FMUL = 280 CEFBS_None, // G_VECREDUCE_FMAX = 281 CEFBS_None, // G_VECREDUCE_FMIN = 282 CEFBS_None, // G_VECREDUCE_FMAXIMUM = 283 CEFBS_None, // G_VECREDUCE_FMINIMUM = 284 CEFBS_None, // G_VECREDUCE_ADD = 285 CEFBS_None, // G_VECREDUCE_MUL = 286 CEFBS_None, // G_VECREDUCE_AND = 287 CEFBS_None, // G_VECREDUCE_OR = 288 CEFBS_None, // G_VECREDUCE_XOR = 289 CEFBS_None, // G_VECREDUCE_SMAX = 290 CEFBS_None, // G_VECREDUCE_SMIN = 291 CEFBS_None, // G_VECREDUCE_UMAX = 292 CEFBS_None, // G_VECREDUCE_UMIN = 293 CEFBS_None, // G_SBFX = 294 CEFBS_None, // G_UBFX = 295 CEFBS_None, // BRANCH = 296 CEFBS_None, // BRANCH_COND_f32 = 297 CEFBS_None, // BRANCH_COND_i32 = 298 CEFBS_None, // BREAK = 299 CEFBS_None, // BREAKC_f32 = 300 CEFBS_None, // BREAKC_i32 = 301 CEFBS_None, // BREAK_LOGICALNZ_f32 = 302 CEFBS_None, // BREAK_LOGICALNZ_i32 = 303 CEFBS_None, // BREAK_LOGICALZ_f32 = 304 CEFBS_None, // BREAK_LOGICALZ_i32 = 305 CEFBS_None, // CONST_COPY = 306 CEFBS_None, // CONTINUE = 307 CEFBS_None, // CONTINUEC_f32 = 308 CEFBS_None, // CONTINUEC_i32 = 309 CEFBS_None, // CONTINUE_LOGICALNZ_f32 = 310 CEFBS_None, // CONTINUE_LOGICALNZ_i32 = 311 CEFBS_None, // CONTINUE_LOGICALZ_f32 = 312 CEFBS_None, // CONTINUE_LOGICALZ_i32 = 313 CEFBS_None, // CUBE_eg_pseudo = 314 CEFBS_None, // CUBE_r600_pseudo = 315 CEFBS_None, // DEFAULT = 316 CEFBS_None, // DOT_4 = 317 CEFBS_None, // DUMMY_CHAIN = 318 CEFBS_None, // ELSE = 319 CEFBS_None, // END = 320 CEFBS_None, // ENDFUNC = 321 CEFBS_None, // ENDIF = 322 CEFBS_None, // ENDLOOP = 323 CEFBS_None, // ENDMAIN = 324 CEFBS_None, // ENDSWITCH = 325 CEFBS_None, // FABS_R600 = 326 CEFBS_None, // FNEG_R600 = 327 CEFBS_None, // FUNC = 328 CEFBS_None, // IFC_f32 = 329 CEFBS_None, // IFC_i32 = 330 CEFBS_None, // IF_LOGICALNZ_f32 = 331 CEFBS_None, // IF_LOGICALNZ_i32 = 332 CEFBS_None, // IF_LOGICALZ_f32 = 333 CEFBS_None, // IF_LOGICALZ_i32 = 334 CEFBS_None, // IF_PREDICATE_SET = 335 CEFBS_None, // JUMP = 336 CEFBS_None, // JUMP_COND = 337 CEFBS_None, // MASK_WRITE = 338 CEFBS_None, // MOV_IMM_F32 = 339 CEFBS_None, // MOV_IMM_GLOBAL_ADDR = 340 CEFBS_None, // MOV_IMM_I32 = 341 CEFBS_None, // PRED_X = 342 CEFBS_None, // R600_EXTRACT_ELT_V2 = 343 CEFBS_None, // R600_EXTRACT_ELT_V4 = 344 CEFBS_None, // R600_INSERT_ELT_V2 = 345 CEFBS_None, // R600_INSERT_ELT_V4 = 346 CEFBS_None, // R600_RegisterLoad = 347 CEFBS_None, // R600_RegisterStore = 348 CEFBS_None, // RETDYN = 349 CEFBS_None, // RETURN = 350 CEFBS_None, // TXD = 351 CEFBS_None, // TXD_SHADOW = 352 CEFBS_None, // WHILELOOP = 353 CEFBS_None, // ADD = 354 CEFBS_None, // ADDC_UINT = 355 CEFBS_None, // ADD_INT = 356 CEFBS_None, // ALU_CLAUSE = 357 CEFBS_None, // AND_INT = 358 CEFBS_None, // ASHR_eg = 359 CEFBS_None, // ASHR_r600 = 360 CEFBS_None, // BCNT_INT = 361 CEFBS_None, // BFE_INT_eg = 362 CEFBS_None, // BFE_UINT_eg = 363 CEFBS_None, // BFI_INT_eg = 364 CEFBS_None, // BFM_INT_eg = 365 CEFBS_None, // BIT_ALIGN_INT_eg = 366 CEFBS_None, // CEIL = 367 CEFBS_None, // CF_ALU = 368 CEFBS_None, // CF_ALU_BREAK = 369 CEFBS_None, // CF_ALU_CONTINUE = 370 CEFBS_None, // CF_ALU_ELSE_AFTER = 371 CEFBS_None, // CF_ALU_POP_AFTER = 372 CEFBS_None, // CF_ALU_PUSH_BEFORE = 373 CEFBS_None, // CF_CALL_FS_EG = 374 CEFBS_None, // CF_CALL_FS_R600 = 375 CEFBS_None, // CF_CONTINUE_EG = 376 CEFBS_None, // CF_CONTINUE_R600 = 377 CEFBS_None, // CF_ELSE_EG = 378 CEFBS_None, // CF_ELSE_R600 = 379 CEFBS_None, // CF_END_CM = 380 CEFBS_None, // CF_END_EG = 381 CEFBS_None, // CF_END_R600 = 382 CEFBS_None, // CF_JUMP_EG = 383 CEFBS_None, // CF_JUMP_R600 = 384 CEFBS_None, // CF_PUSH_EG = 385 CEFBS_None, // CF_PUSH_ELSE_R600 = 386 CEFBS_None, // CF_TC_EG = 387 CEFBS_None, // CF_TC_R600 = 388 CEFBS_None, // CF_VC_EG = 389 CEFBS_None, // CF_VC_R600 = 390 CEFBS_None, // CNDE_INT = 391 CEFBS_None, // CNDE_eg = 392 CEFBS_None, // CNDE_r600 = 393 CEFBS_None, // CNDGE_INT = 394 CEFBS_None, // CNDGE_eg = 395 CEFBS_None, // CNDGE_r600 = 396 CEFBS_None, // CNDGT_INT = 397 CEFBS_None, // CNDGT_eg = 398 CEFBS_None, // CNDGT_r600 = 399 CEFBS_None, // COS_cm = 400 CEFBS_None, // COS_eg = 401 CEFBS_None, // COS_r600 = 402 CEFBS_None, // COS_r700 = 403 CEFBS_None, // CUBE_eg_real = 404 CEFBS_None, // CUBE_r600_real = 405 CEFBS_None, // DOT4_eg = 406 CEFBS_None, // DOT4_r600 = 407 CEFBS_None, // EG_ExportBuf = 408 CEFBS_None, // EG_ExportSwz = 409 CEFBS_None, // END_LOOP_EG = 410 CEFBS_None, // END_LOOP_R600 = 411 CEFBS_None, // EXP_IEEE_cm = 412 CEFBS_None, // EXP_IEEE_eg = 413 CEFBS_None, // EXP_IEEE_r600 = 414 CEFBS_None, // FETCH_CLAUSE = 415 CEFBS_None, // FFBH_UINT = 416 CEFBS_None, // FFBL_INT = 417 CEFBS_None, // FLOOR = 418 CEFBS_None, // FLT16_TO_FLT32 = 419 CEFBS_None, // FLT32_TO_FLT16 = 420 CEFBS_None, // FLT_TO_INT_eg = 421 CEFBS_None, // FLT_TO_INT_r600 = 422 CEFBS_None, // FLT_TO_UINT_eg = 423 CEFBS_None, // FLT_TO_UINT_r600 = 424 CEFBS_None, // FMA_eg = 425 CEFBS_None, // FRACT = 426 CEFBS_None, // GROUP_BARRIER = 427 CEFBS_None, // INTERP_LOAD_P0 = 428 CEFBS_None, // INTERP_PAIR_XY = 429 CEFBS_None, // INTERP_PAIR_ZW = 430 CEFBS_None, // INTERP_VEC_LOAD = 431 CEFBS_None, // INTERP_XY = 432 CEFBS_None, // INTERP_ZW = 433 CEFBS_None, // INT_TO_FLT_eg = 434 CEFBS_None, // INT_TO_FLT_r600 = 435 CEFBS_None, // KILLGT = 436 CEFBS_None, // LDS_ADD = 437 CEFBS_None, // LDS_ADD_RET = 438 CEFBS_None, // LDS_AND = 439 CEFBS_None, // LDS_AND_RET = 440 CEFBS_None, // LDS_BYTE_READ_RET = 441 CEFBS_None, // LDS_BYTE_WRITE = 442 CEFBS_None, // LDS_CMPST = 443 CEFBS_None, // LDS_CMPST_RET = 444 CEFBS_None, // LDS_MAX_INT = 445 CEFBS_None, // LDS_MAX_INT_RET = 446 CEFBS_None, // LDS_MAX_UINT = 447 CEFBS_None, // LDS_MAX_UINT_RET = 448 CEFBS_None, // LDS_MIN_INT = 449 CEFBS_None, // LDS_MIN_INT_RET = 450 CEFBS_None, // LDS_MIN_UINT = 451 CEFBS_None, // LDS_MIN_UINT_RET = 452 CEFBS_None, // LDS_OR = 453 CEFBS_None, // LDS_OR_RET = 454 CEFBS_None, // LDS_READ_RET = 455 CEFBS_None, // LDS_SHORT_READ_RET = 456 CEFBS_None, // LDS_SHORT_WRITE = 457 CEFBS_None, // LDS_SUB = 458 CEFBS_None, // LDS_SUB_RET = 459 CEFBS_None, // LDS_UBYTE_READ_RET = 460 CEFBS_None, // LDS_USHORT_READ_RET = 461 CEFBS_None, // LDS_WRITE = 462 CEFBS_None, // LDS_WRXCHG = 463 CEFBS_None, // LDS_WRXCHG_RET = 464 CEFBS_None, // LDS_XOR = 465 CEFBS_None, // LDS_XOR_RET = 466 CEFBS_None, // LITERALS = 467 CEFBS_None, // LOG_CLAMPED_eg = 468 CEFBS_None, // LOG_CLAMPED_r600 = 469 CEFBS_None, // LOG_IEEE_cm = 470 CEFBS_None, // LOG_IEEE_eg = 471 CEFBS_None, // LOG_IEEE_r600 = 472 CEFBS_None, // LOOP_BREAK_EG = 473 CEFBS_None, // LOOP_BREAK_R600 = 474 CEFBS_None, // LSHL_eg = 475 CEFBS_None, // LSHL_r600 = 476 CEFBS_None, // LSHR_eg = 477 CEFBS_None, // LSHR_r600 = 478 CEFBS_None, // MAX = 479 CEFBS_None, // MAX_DX10 = 480 CEFBS_None, // MAX_INT = 481 CEFBS_None, // MAX_UINT = 482 CEFBS_None, // MIN = 483 CEFBS_None, // MIN_DX10 = 484 CEFBS_None, // MIN_INT = 485 CEFBS_None, // MIN_UINT = 486 CEFBS_None, // MOV = 487 CEFBS_None, // MOVA_INT_eg = 488 CEFBS_None, // MUL = 489 CEFBS_None, // MULADD_IEEE_eg = 490 CEFBS_None, // MULADD_IEEE_r600 = 491 CEFBS_None, // MULADD_INT24_cm = 492 CEFBS_None, // MULADD_UINT24_eg = 493 CEFBS_None, // MULADD_eg = 494 CEFBS_None, // MULADD_r600 = 495 CEFBS_None, // MULHI_INT_cm = 496 CEFBS_None, // MULHI_INT_cm24 = 497 CEFBS_None, // MULHI_INT_eg = 498 CEFBS_None, // MULHI_INT_r600 = 499 CEFBS_None, // MULHI_UINT24_eg = 500 CEFBS_None, // MULHI_UINT_cm = 501 CEFBS_None, // MULHI_UINT_cm24 = 502 CEFBS_None, // MULHI_UINT_eg = 503 CEFBS_None, // MULHI_UINT_r600 = 504 CEFBS_None, // MULLO_INT_cm = 505 CEFBS_None, // MULLO_INT_eg = 506 CEFBS_None, // MULLO_INT_r600 = 507 CEFBS_None, // MULLO_UINT_cm = 508 CEFBS_None, // MULLO_UINT_eg = 509 CEFBS_None, // MULLO_UINT_r600 = 510 CEFBS_None, // MUL_IEEE = 511 CEFBS_None, // MUL_INT24_cm = 512 CEFBS_None, // MUL_LIT_eg = 513 CEFBS_None, // MUL_LIT_r600 = 514 CEFBS_None, // MUL_UINT24_eg = 515 CEFBS_None, // NOT_INT = 516 CEFBS_None, // OR_INT = 517 CEFBS_None, // PAD = 518 CEFBS_None, // POP_EG = 519 CEFBS_None, // POP_R600 = 520 CEFBS_None, // PRED_SETE = 521 CEFBS_None, // PRED_SETE_INT = 522 CEFBS_None, // PRED_SETGE = 523 CEFBS_None, // PRED_SETGE_INT = 524 CEFBS_None, // PRED_SETGT = 525 CEFBS_None, // PRED_SETGT_INT = 526 CEFBS_None, // PRED_SETNE = 527 CEFBS_None, // PRED_SETNE_INT = 528 CEFBS_None, // R600_ExportBuf = 529 CEFBS_None, // R600_ExportSwz = 530 CEFBS_None, // RAT_ATOMIC_ADD_NORET = 531 CEFBS_None, // RAT_ATOMIC_ADD_RTN = 532 CEFBS_None, // RAT_ATOMIC_AND_NORET = 533 CEFBS_None, // RAT_ATOMIC_AND_RTN = 534 CEFBS_None, // RAT_ATOMIC_CMPXCHG_INT_NORET = 535 CEFBS_None, // RAT_ATOMIC_CMPXCHG_INT_RTN = 536 CEFBS_None, // RAT_ATOMIC_DEC_UINT_NORET = 537 CEFBS_None, // RAT_ATOMIC_DEC_UINT_RTN = 538 CEFBS_None, // RAT_ATOMIC_INC_UINT_NORET = 539 CEFBS_None, // RAT_ATOMIC_INC_UINT_RTN = 540 CEFBS_None, // RAT_ATOMIC_MAX_INT_NORET = 541 CEFBS_None, // RAT_ATOMIC_MAX_INT_RTN = 542 CEFBS_None, // RAT_ATOMIC_MAX_UINT_NORET = 543 CEFBS_None, // RAT_ATOMIC_MAX_UINT_RTN = 544 CEFBS_None, // RAT_ATOMIC_MIN_INT_NORET = 545 CEFBS_None, // RAT_ATOMIC_MIN_INT_RTN = 546 CEFBS_None, // RAT_ATOMIC_MIN_UINT_NORET = 547 CEFBS_None, // RAT_ATOMIC_MIN_UINT_RTN = 548 CEFBS_None, // RAT_ATOMIC_OR_NORET = 549 CEFBS_None, // RAT_ATOMIC_OR_RTN = 550 CEFBS_None, // RAT_ATOMIC_RSUB_NORET = 551 CEFBS_None, // RAT_ATOMIC_RSUB_RTN = 552 CEFBS_None, // RAT_ATOMIC_SUB_NORET = 553 CEFBS_None, // RAT_ATOMIC_SUB_RTN = 554 CEFBS_None, // RAT_ATOMIC_XCHG_INT_NORET = 555 CEFBS_None, // RAT_ATOMIC_XCHG_INT_RTN = 556 CEFBS_None, // RAT_ATOMIC_XOR_NORET = 557 CEFBS_None, // RAT_ATOMIC_XOR_RTN = 558 CEFBS_None, // RAT_MSKOR = 559 CEFBS_None, // RAT_STORE_DWORD128 = 560 CEFBS_None, // RAT_STORE_DWORD32 = 561 CEFBS_None, // RAT_STORE_DWORD64 = 562 CEFBS_None, // RAT_STORE_TYPED_cm = 563 CEFBS_None, // RAT_STORE_TYPED_eg = 564 CEFBS_None, // RAT_WRITE_CACHELESS_128_eg = 565 CEFBS_None, // RAT_WRITE_CACHELESS_32_eg = 566 CEFBS_None, // RAT_WRITE_CACHELESS_64_eg = 567 CEFBS_None, // RECIPSQRT_CLAMPED_cm = 568 CEFBS_None, // RECIPSQRT_CLAMPED_eg = 569 CEFBS_None, // RECIPSQRT_CLAMPED_r600 = 570 CEFBS_None, // RECIPSQRT_IEEE_cm = 571 CEFBS_None, // RECIPSQRT_IEEE_eg = 572 CEFBS_None, // RECIPSQRT_IEEE_r600 = 573 CEFBS_None, // RECIP_CLAMPED_cm = 574 CEFBS_None, // RECIP_CLAMPED_eg = 575 CEFBS_None, // RECIP_CLAMPED_r600 = 576 CEFBS_None, // RECIP_IEEE_cm = 577 CEFBS_None, // RECIP_IEEE_eg = 578 CEFBS_None, // RECIP_IEEE_r600 = 579 CEFBS_None, // RECIP_UINT_eg = 580 CEFBS_None, // RECIP_UINT_r600 = 581 CEFBS_None, // RNDNE = 582 CEFBS_None, // SETE = 583 CEFBS_None, // SETE_DX10 = 584 CEFBS_None, // SETE_INT = 585 CEFBS_None, // SETGE_DX10 = 586 CEFBS_None, // SETGE_INT = 587 CEFBS_None, // SETGE_UINT = 588 CEFBS_None, // SETGT_DX10 = 589 CEFBS_None, // SETGT_INT = 590 CEFBS_None, // SETGT_UINT = 591 CEFBS_None, // SETNE_DX10 = 592 CEFBS_None, // SETNE_INT = 593 CEFBS_None, // SGE = 594 CEFBS_None, // SGT = 595 CEFBS_None, // SIN_cm = 596 CEFBS_None, // SIN_eg = 597 CEFBS_None, // SIN_r600 = 598 CEFBS_None, // SIN_r700 = 599 CEFBS_None, // SNE = 600 CEFBS_None, // SUBB_UINT = 601 CEFBS_None, // SUB_INT = 602 CEFBS_None, // TEX_GET_GRADIENTS_H = 603 CEFBS_None, // TEX_GET_GRADIENTS_V = 604 CEFBS_None, // TEX_GET_TEXTURE_RESINFO = 605 CEFBS_None, // TEX_LD = 606 CEFBS_None, // TEX_LDPTR = 607 CEFBS_None, // TEX_SAMPLE = 608 CEFBS_None, // TEX_SAMPLE_C = 609 CEFBS_None, // TEX_SAMPLE_C_G = 610 CEFBS_None, // TEX_SAMPLE_C_L = 611 CEFBS_None, // TEX_SAMPLE_C_LB = 612 CEFBS_None, // TEX_SAMPLE_G = 613 CEFBS_None, // TEX_SAMPLE_L = 614 CEFBS_None, // TEX_SAMPLE_LB = 615 CEFBS_None, // TEX_SET_GRADIENTS_H = 616 CEFBS_None, // TEX_SET_GRADIENTS_V = 617 CEFBS_None, // TEX_VTX_CONSTBUF = 618 CEFBS_None, // TEX_VTX_TEXBUF = 619 CEFBS_None, // TRUNC = 620 CEFBS_None, // UINT_TO_FLT_eg = 621 CEFBS_None, // UINT_TO_FLT_r600 = 622 CEFBS_None, // VTX_READ_128_cm = 623 CEFBS_None, // VTX_READ_128_eg = 624 CEFBS_None, // VTX_READ_16_cm = 625 CEFBS_None, // VTX_READ_16_eg = 626 CEFBS_None, // VTX_READ_32_cm = 627 CEFBS_None, // VTX_READ_32_eg = 628 CEFBS_None, // VTX_READ_64_cm = 629 CEFBS_None, // VTX_READ_64_eg = 630 CEFBS_None, // VTX_READ_8_cm = 631 CEFBS_None, // VTX_READ_8_eg = 632 CEFBS_None, // WHILE_LOOP_EG = 633 CEFBS_None, // WHILE_LOOP_R600 = 634 CEFBS_None, // XOR_INT = 635 }; assert(Opcode < 636); return FeatureBitsets[RequiredFeaturesRefs[Opcode]]; } } // end namespace R600_MC } // end namespace llvm #endif // GET_COMPUTE_FEATURES #ifdef GET_AVAILABLE_OPCODE_CHECKER #undef GET_AVAILABLE_OPCODE_CHECKER namespace llvm { namespace R600_MC { bool isOpcodeAvailable(unsigned Opcode, const FeatureBitset &Features) { FeatureBitset AvailableFeatures = computeAvailableFeatures(Features); FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode); FeatureBitset MissingFeatures = (AvailableFeatures & RequiredFeatures) ^ RequiredFeatures; return !MissingFeatures.any(); } } // end namespace R600_MC } // end namespace llvm #endif // GET_AVAILABLE_OPCODE_CHECKER #ifdef ENABLE_INSTR_PREDICATE_VERIFIER #undef ENABLE_INSTR_PREDICATE_VERIFIER #include <sstream> namespace llvm { namespace R600_MC { #ifndef NDEBUG static const char *SubtargetFeatureNames[] = { nullptr }; #endif // NDEBUG void verifyInstructionPredicates( unsigned Opcode, const FeatureBitset &Features) { #ifndef NDEBUG FeatureBitset AvailableFeatures = computeAvailableFeatures(Features); FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode); FeatureBitset MissingFeatures = (AvailableFeatures & RequiredFeatures) ^ RequiredFeatures; if (MissingFeatures.any()) { std::ostringstream Msg; Msg << "Attempting to emit " << &R600InstrNameData[R600InstrNameIndices[Opcode]] << " instruction but the "; for (unsigned i = 0, e = MissingFeatures.size(); i != e; ++i) if (MissingFeatures.test(i)) Msg << SubtargetFeatureNames[i] << " "; Msg << "predicate(s) are not met"; report_fatal_error(Msg.str().c_str()); } #endif // NDEBUG } } // end namespace R600_MC } // end namespace llvm #endif // ENABLE_INSTR_PREDICATE_VERIFIER #ifdef GET_INSTRMAP_INFO #undef GET_INSTRMAP_INFO namespace llvm { namespace R600 { enum DisableEncoding { DisableEncoding_ }; // getLDSNoRetOp LLVM_READONLY int getLDSNoRetOp(uint16_t Opcode) { static const uint16_t getLDSNoRetOpTable[][2] = { { R600::LDS_ADD_RET, R600::LDS_ADD }, { R600::LDS_AND_RET, R600::LDS_AND }, { R600::LDS_MAX_INT_RET, R600::LDS_MAX_INT }, { R600::LDS_MAX_UINT_RET, R600::LDS_MAX_UINT }, { R600::LDS_MIN_INT_RET, R600::LDS_MIN_INT }, { R600::LDS_MIN_UINT_RET, R600::LDS_MIN_UINT }, { R600::LDS_OR_RET, R600::LDS_OR }, { R600::LDS_SUB_RET, R600::LDS_SUB }, { R600::LDS_WRXCHG_RET, R600::LDS_WRXCHG }, { R600::LDS_XOR_RET, R600::LDS_XOR }, }; // End of getLDSNoRetOpTable unsigned mid; unsigned start = 0; unsigned end = 10; while (start < end) { mid = start + (end - start) / 2; if (Opcode == getLDSNoRetOpTable[mid][0]) { break; } if (Opcode < getLDSNoRetOpTable[mid][0]) end = mid; else start = mid + 1; } if (start == end) return -1; // Instruction doesn't exist in this table. return getLDSNoRetOpTable[mid][1]; } } // end namespace R600 } // end namespace llvm #endif // GET_INSTRMAP_INFO
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