llvm/lib/Target/AVR/AVRGenInstrInfo.inc

/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
|*                                                                            *|
|* Target Instruction Enum Values and Descriptors                             *|
|*                                                                            *|
|* Automatically generated file, do not edit!                                 *|
|*                                                                            *|
\*===----------------------------------------------------------------------===*/

#ifdef GET_INSTRINFO_ENUM
#undef GET_INSTRINFO_ENUM
namespace llvm {

namespace AVR {
  enum {
    PHI	= 0,
    INLINEASM	= 1,
    INLINEASM_BR	= 2,
    CFI_INSTRUCTION	= 3,
    EH_LABEL	= 4,
    GC_LABEL	= 5,
    ANNOTATION_LABEL	= 6,
    KILL	= 7,
    EXTRACT_SUBREG	= 8,
    INSERT_SUBREG	= 9,
    IMPLICIT_DEF	= 10,
    SUBREG_TO_REG	= 11,
    COPY_TO_REGCLASS	= 12,
    DBG_VALUE	= 13,
    DBG_VALUE_LIST	= 14,
    DBG_INSTR_REF	= 15,
    DBG_PHI	= 16,
    DBG_LABEL	= 17,
    REG_SEQUENCE	= 18,
    COPY	= 19,
    BUNDLE	= 20,
    LIFETIME_START	= 21,
    LIFETIME_END	= 22,
    PSEUDO_PROBE	= 23,
    ARITH_FENCE	= 24,
    STACKMAP	= 25,
    FENTRY_CALL	= 26,
    PATCHPOINT	= 27,
    LOAD_STACK_GUARD	= 28,
    PREALLOCATED_SETUP	= 29,
    PREALLOCATED_ARG	= 30,
    STATEPOINT	= 31,
    LOCAL_ESCAPE	= 32,
    FAULTING_OP	= 33,
    PATCHABLE_OP	= 34,
    PATCHABLE_FUNCTION_ENTER	= 35,
    PATCHABLE_RET	= 36,
    PATCHABLE_FUNCTION_EXIT	= 37,
    PATCHABLE_TAIL_CALL	= 38,
    PATCHABLE_EVENT_CALL	= 39,
    PATCHABLE_TYPED_EVENT_CALL	= 40,
    ICALL_BRANCH_FUNNEL	= 41,
    FAKE_USE	= 42,
    MEMBARRIER	= 43,
    JUMP_TABLE_DEBUG_INFO	= 44,
    CONVERGENCECTRL_ENTRY	= 45,
    CONVERGENCECTRL_ANCHOR	= 46,
    CONVERGENCECTRL_LOOP	= 47,
    CONVERGENCECTRL_GLUE	= 48,
    G_ASSERT_SEXT	= 49,
    G_ASSERT_ZEXT	= 50,
    G_ASSERT_ALIGN	= 51,
    G_ADD	= 52,
    G_SUB	= 53,
    G_MUL	= 54,
    G_SDIV	= 55,
    G_UDIV	= 56,
    G_SREM	= 57,
    G_UREM	= 58,
    G_SDIVREM	= 59,
    G_UDIVREM	= 60,
    G_AND	= 61,
    G_OR	= 62,
    G_XOR	= 63,
    G_IMPLICIT_DEF	= 64,
    G_PHI	= 65,
    G_FRAME_INDEX	= 66,
    G_GLOBAL_VALUE	= 67,
    G_PTRAUTH_GLOBAL_VALUE	= 68,
    G_CONSTANT_POOL	= 69,
    G_EXTRACT	= 70,
    G_UNMERGE_VALUES	= 71,
    G_INSERT	= 72,
    G_MERGE_VALUES	= 73,
    G_BUILD_VECTOR	= 74,
    G_BUILD_VECTOR_TRUNC	= 75,
    G_CONCAT_VECTORS	= 76,
    G_PTRTOINT	= 77,
    G_INTTOPTR	= 78,
    G_BITCAST	= 79,
    G_FREEZE	= 80,
    G_CONSTANT_FOLD_BARRIER	= 81,
    G_INTRINSIC_FPTRUNC_ROUND	= 82,
    G_INTRINSIC_TRUNC	= 83,
    G_INTRINSIC_ROUND	= 84,
    G_INTRINSIC_LRINT	= 85,
    G_INTRINSIC_LLRINT	= 86,
    G_INTRINSIC_ROUNDEVEN	= 87,
    G_READCYCLECOUNTER	= 88,
    G_READSTEADYCOUNTER	= 89,
    G_LOAD	= 90,
    G_SEXTLOAD	= 91,
    G_ZEXTLOAD	= 92,
    G_INDEXED_LOAD	= 93,
    G_INDEXED_SEXTLOAD	= 94,
    G_INDEXED_ZEXTLOAD	= 95,
    G_STORE	= 96,
    G_INDEXED_STORE	= 97,
    G_ATOMIC_CMPXCHG_WITH_SUCCESS	= 98,
    G_ATOMIC_CMPXCHG	= 99,
    G_ATOMICRMW_XCHG	= 100,
    G_ATOMICRMW_ADD	= 101,
    G_ATOMICRMW_SUB	= 102,
    G_ATOMICRMW_AND	= 103,
    G_ATOMICRMW_NAND	= 104,
    G_ATOMICRMW_OR	= 105,
    G_ATOMICRMW_XOR	= 106,
    G_ATOMICRMW_MAX	= 107,
    G_ATOMICRMW_MIN	= 108,
    G_ATOMICRMW_UMAX	= 109,
    G_ATOMICRMW_UMIN	= 110,
    G_ATOMICRMW_FADD	= 111,
    G_ATOMICRMW_FSUB	= 112,
    G_ATOMICRMW_FMAX	= 113,
    G_ATOMICRMW_FMIN	= 114,
    G_ATOMICRMW_UINC_WRAP	= 115,
    G_ATOMICRMW_UDEC_WRAP	= 116,
    G_FENCE	= 117,
    G_PREFETCH	= 118,
    G_BRCOND	= 119,
    G_BRINDIRECT	= 120,
    G_INVOKE_REGION_START	= 121,
    G_INTRINSIC	= 122,
    G_INTRINSIC_W_SIDE_EFFECTS	= 123,
    G_INTRINSIC_CONVERGENT	= 124,
    G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS	= 125,
    G_ANYEXT	= 126,
    G_TRUNC	= 127,
    G_CONSTANT	= 128,
    G_FCONSTANT	= 129,
    G_VASTART	= 130,
    G_VAARG	= 131,
    G_SEXT	= 132,
    G_SEXT_INREG	= 133,
    G_ZEXT	= 134,
    G_SHL	= 135,
    G_LSHR	= 136,
    G_ASHR	= 137,
    G_FSHL	= 138,
    G_FSHR	= 139,
    G_ROTR	= 140,
    G_ROTL	= 141,
    G_ICMP	= 142,
    G_FCMP	= 143,
    G_SCMP	= 144,
    G_UCMP	= 145,
    G_SELECT	= 146,
    G_UADDO	= 147,
    G_UADDE	= 148,
    G_USUBO	= 149,
    G_USUBE	= 150,
    G_SADDO	= 151,
    G_SADDE	= 152,
    G_SSUBO	= 153,
    G_SSUBE	= 154,
    G_UMULO	= 155,
    G_SMULO	= 156,
    G_UMULH	= 157,
    G_SMULH	= 158,
    G_UADDSAT	= 159,
    G_SADDSAT	= 160,
    G_USUBSAT	= 161,
    G_SSUBSAT	= 162,
    G_USHLSAT	= 163,
    G_SSHLSAT	= 164,
    G_SMULFIX	= 165,
    G_UMULFIX	= 166,
    G_SMULFIXSAT	= 167,
    G_UMULFIXSAT	= 168,
    G_SDIVFIX	= 169,
    G_UDIVFIX	= 170,
    G_SDIVFIXSAT	= 171,
    G_UDIVFIXSAT	= 172,
    G_FADD	= 173,
    G_FSUB	= 174,
    G_FMUL	= 175,
    G_FMA	= 176,
    G_FMAD	= 177,
    G_FDIV	= 178,
    G_FREM	= 179,
    G_FPOW	= 180,
    G_FPOWI	= 181,
    G_FEXP	= 182,
    G_FEXP2	= 183,
    G_FEXP10	= 184,
    G_FLOG	= 185,
    G_FLOG2	= 186,
    G_FLOG10	= 187,
    G_FLDEXP	= 188,
    G_FFREXP	= 189,
    G_FNEG	= 190,
    G_FPEXT	= 191,
    G_FPTRUNC	= 192,
    G_FPTOSI	= 193,
    G_FPTOUI	= 194,
    G_SITOFP	= 195,
    G_UITOFP	= 196,
    G_FABS	= 197,
    G_FCOPYSIGN	= 198,
    G_IS_FPCLASS	= 199,
    G_FCANONICALIZE	= 200,
    G_FMINNUM	= 201,
    G_FMAXNUM	= 202,
    G_FMINNUM_IEEE	= 203,
    G_FMAXNUM_IEEE	= 204,
    G_FMINIMUM	= 205,
    G_FMAXIMUM	= 206,
    G_GET_FPENV	= 207,
    G_SET_FPENV	= 208,
    G_RESET_FPENV	= 209,
    G_GET_FPMODE	= 210,
    G_SET_FPMODE	= 211,
    G_RESET_FPMODE	= 212,
    G_PTR_ADD	= 213,
    G_PTRMASK	= 214,
    G_SMIN	= 215,
    G_SMAX	= 216,
    G_UMIN	= 217,
    G_UMAX	= 218,
    G_ABS	= 219,
    G_LROUND	= 220,
    G_LLROUND	= 221,
    G_BR	= 222,
    G_BRJT	= 223,
    G_VSCALE	= 224,
    G_INSERT_SUBVECTOR	= 225,
    G_EXTRACT_SUBVECTOR	= 226,
    G_INSERT_VECTOR_ELT	= 227,
    G_EXTRACT_VECTOR_ELT	= 228,
    G_SHUFFLE_VECTOR	= 229,
    G_SPLAT_VECTOR	= 230,
    G_VECTOR_COMPRESS	= 231,
    G_CTTZ	= 232,
    G_CTTZ_ZERO_UNDEF	= 233,
    G_CTLZ	= 234,
    G_CTLZ_ZERO_UNDEF	= 235,
    G_CTPOP	= 236,
    G_BSWAP	= 237,
    G_BITREVERSE	= 238,
    G_FCEIL	= 239,
    G_FCOS	= 240,
    G_FSIN	= 241,
    G_FTAN	= 242,
    G_FACOS	= 243,
    G_FASIN	= 244,
    G_FATAN	= 245,
    G_FCOSH	= 246,
    G_FSINH	= 247,
    G_FTANH	= 248,
    G_FSQRT	= 249,
    G_FFLOOR	= 250,
    G_FRINT	= 251,
    G_FNEARBYINT	= 252,
    G_ADDRSPACE_CAST	= 253,
    G_BLOCK_ADDR	= 254,
    G_JUMP_TABLE	= 255,
    G_DYN_STACKALLOC	= 256,
    G_STACKSAVE	= 257,
    G_STACKRESTORE	= 258,
    G_STRICT_FADD	= 259,
    G_STRICT_FSUB	= 260,
    G_STRICT_FMUL	= 261,
    G_STRICT_FDIV	= 262,
    G_STRICT_FREM	= 263,
    G_STRICT_FMA	= 264,
    G_STRICT_FSQRT	= 265,
    G_STRICT_FLDEXP	= 266,
    G_READ_REGISTER	= 267,
    G_WRITE_REGISTER	= 268,
    G_MEMCPY	= 269,
    G_MEMCPY_INLINE	= 270,
    G_MEMMOVE	= 271,
    G_MEMSET	= 272,
    G_BZERO	= 273,
    G_TRAP	= 274,
    G_DEBUGTRAP	= 275,
    G_UBSANTRAP	= 276,
    G_VECREDUCE_SEQ_FADD	= 277,
    G_VECREDUCE_SEQ_FMUL	= 278,
    G_VECREDUCE_FADD	= 279,
    G_VECREDUCE_FMUL	= 280,
    G_VECREDUCE_FMAX	= 281,
    G_VECREDUCE_FMIN	= 282,
    G_VECREDUCE_FMAXIMUM	= 283,
    G_VECREDUCE_FMINIMUM	= 284,
    G_VECREDUCE_ADD	= 285,
    G_VECREDUCE_MUL	= 286,
    G_VECREDUCE_AND	= 287,
    G_VECREDUCE_OR	= 288,
    G_VECREDUCE_XOR	= 289,
    G_VECREDUCE_SMAX	= 290,
    G_VECREDUCE_SMIN	= 291,
    G_VECREDUCE_UMAX	= 292,
    G_VECREDUCE_UMIN	= 293,
    G_SBFX	= 294,
    G_UBFX	= 295,
    ADCWRdRr	= 296,
    ADDWRdRr	= 297,
    ADJCALLSTACKDOWN	= 298,
    ADJCALLSTACKUP	= 299,
    ANDIWRdK	= 300,
    ANDWRdRr	= 301,
    ASRBNRd	= 302,
    ASRWLoRd	= 303,
    ASRWNRd	= 304,
    ASRWRd	= 305,
    Asr16	= 306,
    Asr32	= 307,
    Asr8	= 308,
    AtomicFence	= 309,
    AtomicLoad16	= 310,
    AtomicLoad8	= 311,
    AtomicLoadAdd16	= 312,
    AtomicLoadAdd8	= 313,
    AtomicLoadAnd16	= 314,
    AtomicLoadAnd8	= 315,
    AtomicLoadOr16	= 316,
    AtomicLoadOr8	= 317,
    AtomicLoadSub16	= 318,
    AtomicLoadSub8	= 319,
    AtomicLoadXor16	= 320,
    AtomicLoadXor8	= 321,
    AtomicStore16	= 322,
    AtomicStore8	= 323,
    COMWRd	= 324,
    CPCWRdRr	= 325,
    CPWRdRr	= 326,
    CopyZero	= 327,
    ELPMBRdZ	= 328,
    ELPMBRdZPi	= 329,
    ELPMWRdZ	= 330,
    ELPMWRdZPi	= 331,
    EORWRdRr	= 332,
    FRMIDX	= 333,
    INWRdA	= 334,
    LDDWRdPtrQ	= 335,
    LDDWRdYQ	= 336,
    LDIWRdK	= 337,
    LDSWRdK	= 338,
    LDWRdPtr	= 339,
    LDWRdPtrPd	= 340,
    LDWRdPtrPi	= 341,
    LPMBRdZ	= 342,
    LPMWRdZ	= 343,
    LPMWRdZPi	= 344,
    LSLBNRd	= 345,
    LSLWHiRd	= 346,
    LSLWNRd	= 347,
    LSLWRd	= 348,
    LSRBNRd	= 349,
    LSRWLoRd	= 350,
    LSRWNRd	= 351,
    LSRWRd	= 352,
    Lsl16	= 353,
    Lsl32	= 354,
    Lsl8	= 355,
    Lsr16	= 356,
    Lsr32	= 357,
    Lsr8	= 358,
    NEGWRd	= 359,
    ORIWRdK	= 360,
    ORWRdRr	= 361,
    OUTWARr	= 362,
    POPWRd	= 363,
    PUSHWRr	= 364,
    ROLBRdR1	= 365,
    ROLBRdR17	= 366,
    ROLWRd	= 367,
    RORBRd	= 368,
    RORWRd	= 369,
    Rol16	= 370,
    Rol8	= 371,
    Ror16	= 372,
    Ror8	= 373,
    SBCIWRdK	= 374,
    SBCWRdRr	= 375,
    SEXT	= 376,
    SPREAD	= 377,
    SPWRITE	= 378,
    STDSPQRr	= 379,
    STDWPtrQRr	= 380,
    STDWSPQRr	= 381,
    STSWKRr	= 382,
    STWPtrPdRr	= 383,
    STWPtrPiRr	= 384,
    STWPtrRr	= 385,
    SUBIWRdK	= 386,
    SUBWRdRr	= 387,
    Select16	= 388,
    Select8	= 389,
    ZEXT	= 390,
    ADCRdRr	= 391,
    ADDRdRr	= 392,
    ADIWRdK	= 393,
    ANDIRdK	= 394,
    ANDRdRr	= 395,
    ASRRd	= 396,
    BCLRs	= 397,
    BLD	= 398,
    BRBCsk	= 399,
    BRBSsk	= 400,
    BREAK	= 401,
    BREQk	= 402,
    BRGEk	= 403,
    BRLOk	= 404,
    BRLTk	= 405,
    BRMIk	= 406,
    BRNEk	= 407,
    BRPLk	= 408,
    BRSHk	= 409,
    BSETs	= 410,
    BST	= 411,
    CALLk	= 412,
    CBIAb	= 413,
    COMRd	= 414,
    CPCRdRr	= 415,
    CPIRdK	= 416,
    CPRdRr	= 417,
    CPSE	= 418,
    DECRd	= 419,
    DESK	= 420,
    EICALL	= 421,
    EIJMP	= 422,
    ELPM	= 423,
    ELPMRdZ	= 424,
    ELPMRdZPi	= 425,
    EORRdRr	= 426,
    FMUL	= 427,
    FMULS	= 428,
    FMULSU	= 429,
    ICALL	= 430,
    IJMP	= 431,
    INCRd	= 432,
    INRdA	= 433,
    JMPk	= 434,
    LACZRd	= 435,
    LASZRd	= 436,
    LATZRd	= 437,
    LDDRdPtrQ	= 438,
    LDIRdK	= 439,
    LDRdPtr	= 440,
    LDRdPtrPd	= 441,
    LDRdPtrPi	= 442,
    LDSRdK	= 443,
    LDSRdKTiny	= 444,
    LPM	= 445,
    LPMRdZ	= 446,
    LPMRdZPi	= 447,
    LSRRd	= 448,
    MOVRdRr	= 449,
    MOVWRdRr	= 450,
    MULRdRr	= 451,
    MULSRdRr	= 452,
    MULSURdRr	= 453,
    NEGRd	= 454,
    NOP	= 455,
    ORIRdK	= 456,
    ORRdRr	= 457,
    OUTARr	= 458,
    POPRd	= 459,
    PUSHRr	= 460,
    RCALLk	= 461,
    RET	= 462,
    RETI	= 463,
    RJMPk	= 464,
    RORRd	= 465,
    SBCIRdK	= 466,
    SBCRdRr	= 467,
    SBIAb	= 468,
    SBICAb	= 469,
    SBISAb	= 470,
    SBIWRdK	= 471,
    SBRCRrB	= 472,
    SBRSRrB	= 473,
    SLEEP	= 474,
    SPM	= 475,
    SPMZPi	= 476,
    STDPtrQRr	= 477,
    STPtrPdRr	= 478,
    STPtrPiRr	= 479,
    STPtrRr	= 480,
    STSKRr	= 481,
    STSKRrTiny	= 482,
    SUBIRdK	= 483,
    SUBRdRr	= 484,
    SWAPRd	= 485,
    WDR	= 486,
    XCHZRd	= 487,
    INSTRUCTION_LIST_END = 488
  };

} // end namespace AVR
} // end namespace llvm
#endif // GET_INSTRINFO_ENUM

#ifdef GET_INSTRINFO_SCHED_ENUM
#undef GET_INSTRINFO_SCHED_ENUM
namespace llvm {

namespace AVR {
namespace Sched {
  enum {
    NoInstrModel	= 0,
    SCHED_LIST_END = 1
  };
} // end namespace Sched
} // end namespace AVR
} // end namespace llvm
#endif // GET_INSTRINFO_SCHED_ENUM

#if defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
namespace llvm {

struct AVRInstrTable {
  MCInstrDesc Insts[488];
  static_assert(alignof(MCInstrDesc) >= alignof(MCOperandInfo), "Unwanted padding between Insts and OperandInfo");
  MCOperandInfo OperandInfo[319];
  static_assert(alignof(MCOperandInfo) >= alignof(MCPhysReg), "Unwanted padding between OperandInfo and ImplicitOps");
  MCPhysReg ImplicitOps[44];
};

} // end namespace llvm
#endif // defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)

#ifdef GET_INSTRINFO_MC_DESC
#undef GET_INSTRINFO_MC_DESC
namespace llvm {

static_assert(sizeof(MCOperandInfo) % sizeof(MCPhysReg) == 0);
static constexpr unsigned AVRImpOpBase = sizeof AVRInstrTable::OperandInfo / (sizeof(MCPhysReg));

extern const AVRInstrTable AVRDescs = {
  {
    { 487,	2,	1,	2,	0,	0,	0,	AVRImpOpBase + 0,	223,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #487 = XCHZRd
    { 486,	0,	0,	2,	0,	0,	0,	AVRImpOpBase + 0,	1,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #486 = WDR
    { 485,	2,	1,	2,	0,	0,	0,	AVRImpOpBase + 0,	238,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #485 = SWAPRd
    { 484,	3,	1,	2,	0,	0,	1,	AVRImpOpBase + 2,	269,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #484 = SUBRdRr
    { 483,	3,	1,	2,	0,	0,	1,	AVRImpOpBase + 2,	275,	0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #483 = SUBIRdK
    { 482,	2,	0,	2,	0,	0,	0,	AVRImpOpBase + 0,	317,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #482 = STSKRrTiny
    { 481,	2,	0,	4,	0,	0,	0,	AVRImpOpBase + 0,	305,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #481 = STSKRr
    { 480,	2,	0,	2,	0,	0,	0,	AVRImpOpBase + 0,	315,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #480 = STPtrRr
    { 479,	4,	1,	2,	0,	0,	0,	AVRImpOpBase + 0,	311,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #479 = STPtrPiRr
    { 478,	4,	1,	2,	0,	0,	0,	AVRImpOpBase + 0,	311,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #478 = STPtrPdRr
    { 477,	3,	0,	2,	0,	0,	0,	AVRImpOpBase + 0,	308,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #477 = STDPtrQRr
    { 476,	1,	0,	2,	0,	2,	1,	AVRImpOpBase + 41,	307,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #476 = SPMZPi
    { 475,	0,	0,	2,	0,	3,	0,	AVRImpOpBase + 38,	1,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #475 = SPM
    { 474,	0,	0,	2,	0,	0,	0,	AVRImpOpBase + 0,	1,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #474 = SLEEP
    { 473,	2,	0,	2,	0,	0,	0,	AVRImpOpBase + 0,	283,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #473 = SBRSRrB
    { 472,	2,	0,	2,	0,	0,	0,	AVRImpOpBase + 0,	283,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #472 = SBRCRrB
    { 471,	3,	1,	2,	0,	0,	1,	AVRImpOpBase + 2,	272,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #471 = SBIWRdK
    { 470,	2,	0,	2,	0,	0,	0,	AVRImpOpBase + 0,	285,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #470 = SBISAb
    { 469,	2,	0,	2,	0,	0,	0,	AVRImpOpBase + 0,	285,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #469 = SBICAb
    { 468,	2,	0,	2,	0,	0,	0,	AVRImpOpBase + 0,	285,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #468 = SBIAb
    { 467,	3,	1,	2,	0,	1,	1,	AVRImpOpBase + 0,	269,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #467 = SBCRdRr
    { 466,	3,	1,	2,	0,	1,	1,	AVRImpOpBase + 0,	275,	0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #466 = SBCIRdK
    { 465,	2,	1,	2,	0,	1,	1,	AVRImpOpBase + 0,	238,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #465 = RORRd
    { 464,	1,	0,	2,	0,	0,	0,	AVRImpOpBase + 0,	0,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #464 = RJMPk
    { 463,	0,	0,	2,	0,	0,	0,	AVRImpOpBase + 0,	1,	0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #463 = RETI
    { 462,	0,	0,	2,	0,	0,	0,	AVRImpOpBase + 0,	1,	0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #462 = RET
    { 461,	1,	0,	2,	0,	1,	0,	AVRImpOpBase + 16,	0,	0|(1ULL<<MCID::Call)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #461 = RCALLk
    { 460,	1,	0,	2,	0,	1,	1,	AVRImpOpBase + 10,	193,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #460 = PUSHRr
    { 459,	1,	1,	2,	0,	1,	1,	AVRImpOpBase + 10,	193,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #459 = POPRd
    { 458,	2,	0,	2,	0,	0,	0,	AVRImpOpBase + 0,	305,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #458 = OUTARr
    { 457,	3,	1,	2,	0,	0,	1,	AVRImpOpBase + 2,	269,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #457 = ORRdRr
    { 456,	3,	1,	2,	0,	0,	1,	AVRImpOpBase + 2,	275,	0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #456 = ORIRdK
    { 455,	0,	0,	2,	0,	0,	0,	AVRImpOpBase + 0,	1,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #455 = NOP
    { 454,	2,	1,	2,	0,	0,	1,	AVRImpOpBase + 2,	238,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #454 = NEGRd
    { 453,	2,	0,	2,	0,	0,	3,	AVRImpOpBase + 35,	291,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #453 = MULSURdRr
    { 452,	2,	0,	2,	0,	0,	3,	AVRImpOpBase + 35,	303,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #452 = MULSRdRr
    { 451,	2,	0,	2,	0,	0,	3,	AVRImpOpBase + 35,	287,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #451 = MULRdRr
    { 450,	2,	1,	2,	0,	0,	0,	AVRImpOpBase + 0,	191,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #450 = MOVWRdRr
    { 449,	2,	1,	2,	0,	0,	0,	AVRImpOpBase + 0,	287,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #449 = MOVRdRr
    { 448,	2,	1,	2,	0,	0,	1,	AVRImpOpBase + 2,	238,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #448 = LSRRd
    { 447,	2,	1,	2,	0,	0,	1,	AVRImpOpBase + 9,	223,	0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #447 = LPMRdZPi
    { 446,	2,	1,	2,	0,	0,	0,	AVRImpOpBase + 0,	223,	0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #446 = LPMRdZ
    { 445,	0,	0,	2,	0,	1,	1,	AVRImpOpBase + 33,	1,	0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #445 = LPM
    { 444,	2,	1,	2,	0,	0,	0,	AVRImpOpBase + 0,	289,	0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #444 = LDSRdKTiny
    { 443,	2,	1,	4,	0,	0,	0,	AVRImpOpBase + 0,	293,	0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #443 = LDSRdK
    { 442,	3,	2,	2,	0,	0,	0,	AVRImpOpBase + 0,	300,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #442 = LDRdPtrPi
    { 441,	3,	2,	2,	0,	0,	0,	AVRImpOpBase + 0,	300,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #441 = LDRdPtrPd
    { 440,	2,	1,	2,	0,	0,	0,	AVRImpOpBase + 0,	298,	0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #440 = LDRdPtr
    { 439,	2,	1,	2,	0,	0,	0,	AVRImpOpBase + 0,	289,	0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #439 = LDIRdK
    { 438,	3,	1,	2,	0,	0,	0,	AVRImpOpBase + 0,	295,	0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #438 = LDDRdPtrQ
    { 437,	2,	1,	2,	0,	0,	0,	AVRImpOpBase + 0,	223,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #437 = LATZRd
    { 436,	2,	1,	2,	0,	0,	0,	AVRImpOpBase + 0,	223,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #436 = LASZRd
    { 435,	2,	1,	2,	0,	0,	0,	AVRImpOpBase + 0,	223,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #435 = LACZRd
    { 434,	1,	0,	4,	0,	0,	0,	AVRImpOpBase + 0,	0,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #434 = JMPk
    { 433,	2,	1,	2,	0,	0,	0,	AVRImpOpBase + 0,	293,	0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #433 = INRdA
    { 432,	2,	1,	2,	0,	0,	1,	AVRImpOpBase + 2,	238,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #432 = INCRd
    { 431,	0,	0,	2,	0,	1,	0,	AVRImpOpBase + 9,	1,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #431 = IJMP
    { 430,	0,	0,	2,	0,	2,	0,	AVRImpOpBase + 6,	1,	0|(1ULL<<MCID::Call)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #430 = ICALL
    { 429,	2,	0,	2,	0,	0,	3,	AVRImpOpBase + 35,	291,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #429 = FMULSU
    { 428,	2,	0,	2,	0,	0,	3,	AVRImpOpBase + 35,	291,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #428 = FMULS
    { 427,	2,	0,	2,	0,	0,	3,	AVRImpOpBase + 35,	291,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #427 = FMUL
    { 426,	3,	1,	2,	0,	0,	1,	AVRImpOpBase + 2,	269,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #426 = EORRdRr
    { 425,	2,	1,	2,	0,	0,	1,	AVRImpOpBase + 9,	223,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #425 = ELPMRdZPi
    { 424,	2,	1,	2,	0,	0,	0,	AVRImpOpBase + 0,	223,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #424 = ELPMRdZ
    { 423,	0,	0,	2,	0,	1,	1,	AVRImpOpBase + 33,	1,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #423 = ELPM
    { 422,	0,	0,	2,	0,	1,	0,	AVRImpOpBase + 9,	1,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #422 = EIJMP
    { 421,	0,	0,	2,	0,	2,	0,	AVRImpOpBase + 6,	1,	0|(1ULL<<MCID::Call)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #421 = EICALL
    { 420,	1,	0,	2,	0,	0,	16,	AVRImpOpBase + 17,	1,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #420 = DESK
    { 419,	2,	1,	2,	0,	0,	1,	AVRImpOpBase + 2,	238,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #419 = DECRd
    { 418,	2,	0,	2,	0,	0,	1,	AVRImpOpBase + 2,	287,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #418 = CPSE
    { 417,	2,	0,	2,	0,	0,	1,	AVRImpOpBase + 2,	287,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #417 = CPRdRr
    { 416,	2,	0,	2,	0,	0,	1,	AVRImpOpBase + 2,	289,	0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #416 = CPIRdK
    { 415,	2,	0,	2,	0,	1,	1,	AVRImpOpBase + 0,	287,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #415 = CPCRdRr
    { 414,	2,	1,	2,	0,	0,	1,	AVRImpOpBase + 2,	238,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #414 = COMRd
    { 413,	2,	0,	2,	0,	0,	0,	AVRImpOpBase + 0,	285,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #413 = CBIAb
    { 412,	1,	0,	4,	0,	1,	0,	AVRImpOpBase + 16,	0,	0|(1ULL<<MCID::Call)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #412 = CALLk
    { 411,	2,	0,	2,	0,	0,	1,	AVRImpOpBase + 2,	283,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #411 = BST
    { 410,	1,	0,	2,	0,	0,	1,	AVRImpOpBase + 2,	1,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #410 = BSETs
    { 409,	1,	0,	2,	0,	1,	0,	AVRImpOpBase + 2,	0,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #409 = BRSHk
    { 408,	1,	0,	2,	0,	1,	0,	AVRImpOpBase + 2,	0,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #408 = BRPLk
    { 407,	1,	0,	2,	0,	1,	0,	AVRImpOpBase + 2,	0,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #407 = BRNEk
    { 406,	1,	0,	2,	0,	1,	0,	AVRImpOpBase + 2,	0,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #406 = BRMIk
    { 405,	1,	0,	2,	0,	1,	0,	AVRImpOpBase + 2,	0,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #405 = BRLTk
    { 404,	1,	0,	2,	0,	1,	0,	AVRImpOpBase + 2,	0,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #404 = BRLOk
    { 403,	1,	0,	2,	0,	1,	0,	AVRImpOpBase + 2,	0,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #403 = BRGEk
    { 402,	1,	0,	2,	0,	1,	0,	AVRImpOpBase + 2,	0,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #402 = BREQk
    { 401,	0,	0,	2,	0,	0,	0,	AVRImpOpBase + 0,	1,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #401 = BREAK
    { 400,	2,	0,	2,	0,	1,	0,	AVRImpOpBase + 2,	281,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #400 = BRBSsk
    { 399,	2,	0,	2,	0,	1,	0,	AVRImpOpBase + 2,	281,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #399 = BRBCsk
    { 398,	3,	1,	2,	0,	1,	0,	AVRImpOpBase + 2,	278,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #398 = BLD
    { 397,	1,	0,	2,	0,	0,	1,	AVRImpOpBase + 2,	1,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #397 = BCLRs
    { 396,	2,	1,	2,	0,	0,	1,	AVRImpOpBase + 2,	238,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #396 = ASRRd
    { 395,	3,	1,	2,	0,	0,	1,	AVRImpOpBase + 2,	269,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #395 = ANDRdRr
    { 394,	3,	1,	2,	0,	0,	1,	AVRImpOpBase + 2,	275,	0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #394 = ANDIRdK
    { 393,	3,	1,	2,	0,	0,	1,	AVRImpOpBase + 2,	272,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #393 = ADIWRdK
    { 392,	3,	1,	2,	0,	0,	1,	AVRImpOpBase + 2,	269,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #392 = ADDRdRr
    { 391,	3,	1,	2,	0,	1,	1,	AVRImpOpBase + 0,	269,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #391 = ADCRdRr
    { 390,	2,	1,	2,	0,	0,	1,	AVRImpOpBase + 2,	240,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #390 = ZEXT
    { 389,	4,	1,	2,	0,	1,	0,	AVRImpOpBase + 2,	265,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #389 = Select8
    { 388,	4,	1,	2,	0,	1,	0,	AVRImpOpBase + 2,	261,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #388 = Select16
    { 387,	3,	1,	2,	0,	0,	1,	AVRImpOpBase + 2,	152,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #387 = SUBWRdRr
    { 386,	3,	1,	2,	0,	0,	1,	AVRImpOpBase + 2,	155,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #386 = SUBIWRdK
    { 385,	2,	0,	2,	0,	0,	0,	AVRImpOpBase + 0,	187,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #385 = STWPtrRr
    { 384,	4,	1,	2,	0,	0,	0,	AVRImpOpBase + 0,	257,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #384 = STWPtrPiRr
    { 383,	4,	1,	2,	0,	0,	0,	AVRImpOpBase + 0,	257,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #383 = STWPtrPdRr
    { 382,	2,	0,	2,	0,	0,	0,	AVRImpOpBase + 0,	255,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #382 = STSWKRr
    { 381,	3,	0,	2,	0,	0,	1,	AVRImpOpBase + 16,	252,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #381 = STDWSPQRr
    { 380,	3,	0,	2,	0,	0,	0,	AVRImpOpBase + 0,	249,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #380 = STDWPtrQRr
    { 379,	3,	0,	2,	0,	0,	1,	AVRImpOpBase + 16,	246,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #379 = STDSPQRr
    { 378,	2,	1,	2,	0,	0,	1,	AVRImpOpBase + 16,	244,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #378 = SPWRITE
    { 377,	2,	1,	2,	0,	1,	0,	AVRImpOpBase + 16,	242,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #377 = SPREAD
    { 376,	2,	1,	2,	0,	0,	1,	AVRImpOpBase + 2,	240,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #376 = SEXT
    { 375,	3,	1,	2,	0,	1,	1,	AVRImpOpBase + 0,	152,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #375 = SBCWRdRr
    { 374,	3,	1,	2,	0,	1,	1,	AVRImpOpBase + 0,	155,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #374 = SBCIWRdK
    { 373,	3,	1,	2,	0,	0,	1,	AVRImpOpBase + 2,	174,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #373 = Ror8
    { 372,	3,	1,	2,	0,	0,	1,	AVRImpOpBase + 2,	166,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #372 = Ror16
    { 371,	3,	1,	2,	0,	0,	1,	AVRImpOpBase + 2,	174,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #371 = Rol8
    { 370,	3,	1,	2,	0,	0,	1,	AVRImpOpBase + 2,	166,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #370 = Rol16
    { 369,	2,	1,	2,	0,	1,	1,	AVRImpOpBase + 0,	161,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #369 = RORWRd
    { 368,	2,	1,	2,	0,	0,	1,	AVRImpOpBase + 2,	238,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #368 = RORBRd
    { 367,	2,	1,	2,	0,	1,	1,	AVRImpOpBase + 0,	161,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #367 = ROLWRd
    { 366,	2,	1,	2,	0,	1,	1,	AVRImpOpBase + 14,	238,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #366 = ROLBRdR17
    { 365,	2,	1,	2,	0,	1,	1,	AVRImpOpBase + 12,	238,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #365 = ROLBRdR1
    { 364,	1,	0,	2,	0,	1,	1,	AVRImpOpBase + 10,	237,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #364 = PUSHWRr
    { 363,	1,	1,	2,	0,	1,	1,	AVRImpOpBase + 10,	237,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #363 = POPWRd
    { 362,	2,	0,	2,	0,	0,	0,	AVRImpOpBase + 0,	235,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #362 = OUTWARr
    { 361,	3,	1,	2,	0,	0,	1,	AVRImpOpBase + 2,	152,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #361 = ORWRdRr
    { 360,	3,	1,	2,	0,	0,	1,	AVRImpOpBase + 2,	155,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #360 = ORIWRdK
    { 359,	3,	1,	2,	0,	0,	1,	AVRImpOpBase + 2,	232,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #359 = NEGWRd
    { 358,	3,	1,	2,	0,	0,	1,	AVRImpOpBase + 2,	174,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #358 = Lsr8
    { 357,	5,	2,	2,	0,	0,	1,	AVRImpOpBase + 2,	169,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #357 = Lsr32
    { 356,	3,	1,	2,	0,	0,	1,	AVRImpOpBase + 2,	166,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #356 = Lsr16
    { 355,	3,	1,	2,	0,	0,	1,	AVRImpOpBase + 2,	174,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #355 = Lsl8
    { 354,	5,	2,	2,	0,	0,	1,	AVRImpOpBase + 2,	169,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #354 = Lsl32
    { 353,	3,	1,	2,	0,	0,	1,	AVRImpOpBase + 2,	166,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #353 = Lsl16
    { 352,	2,	1,	2,	0,	0,	1,	AVRImpOpBase + 2,	161,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #352 = LSRWRd
    { 351,	3,	1,	2,	0,	0,	1,	AVRImpOpBase + 2,	229,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #351 = LSRWNRd
    { 350,	2,	1,	2,	0,	0,	1,	AVRImpOpBase + 2,	161,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #350 = LSRWLoRd
    { 349,	3,	1,	2,	0,	0,	1,	AVRImpOpBase + 2,	158,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #349 = LSRBNRd
    { 348,	2,	1,	2,	0,	0,	1,	AVRImpOpBase + 2,	161,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #348 = LSLWRd
    { 347,	3,	1,	2,	0,	0,	1,	AVRImpOpBase + 2,	229,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #347 = LSLWNRd
    { 346,	2,	1,	2,	0,	0,	1,	AVRImpOpBase + 2,	161,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #346 = LSLWHiRd
    { 345,	3,	1,	2,	0,	0,	1,	AVRImpOpBase + 2,	158,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #345 = LSLBNRd
    { 344,	2,	1,	2,	0,	0,	1,	AVRImpOpBase + 9,	227,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #344 = LPMWRdZPi
    { 343,	2,	1,	2,	0,	0,	1,	AVRImpOpBase + 8,	225,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #343 = LPMWRdZ
    { 342,	2,	1,	2,	0,	0,	1,	AVRImpOpBase + 8,	223,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #342 = LPMBRdZ
    { 341,	3,	2,	2,	0,	0,	0,	AVRImpOpBase + 0,	220,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #341 = LDWRdPtrPi
    { 340,	3,	2,	2,	0,	0,	0,	AVRImpOpBase + 0,	220,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #340 = LDWRdPtrPd
    { 339,	2,	1,	2,	0,	0,	0,	AVRImpOpBase + 0,	218,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #339 = LDWRdPtr
    { 338,	2,	1,	2,	0,	0,	0,	AVRImpOpBase + 0,	216,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #338 = LDSWRdK
    { 337,	2,	1,	2,	0,	0,	0,	AVRImpOpBase + 0,	214,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #337 = LDIWRdK
    { 336,	3,	1,	2,	0,	0,	0,	AVRImpOpBase + 0,	211,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #336 = LDDWRdYQ
    { 335,	3,	1,	2,	0,	0,	0,	AVRImpOpBase + 0,	208,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #335 = LDDWRdPtrQ
    { 334,	2,	1,	2,	0,	0,	0,	AVRImpOpBase + 0,	206,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #334 = INWRdA
    { 333,	3,	1,	2,	0,	0,	1,	AVRImpOpBase + 2,	203,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #333 = FRMIDX
    { 332,	3,	1,	2,	0,	0,	1,	AVRImpOpBase + 2,	152,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #332 = EORWRdRr
    { 331,	3,	1,	2,	0,	0,	1,	AVRImpOpBase + 9,	200,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #331 = ELPMWRdZPi
    { 330,	3,	1,	2,	0,	0,	1,	AVRImpOpBase + 8,	197,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #330 = ELPMWRdZ
    { 329,	3,	1,	2,	0,	0,	1,	AVRImpOpBase + 9,	194,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #329 = ELPMBRdZPi
    { 328,	3,	1,	2,	0,	0,	1,	AVRImpOpBase + 8,	194,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #328 = ELPMBRdZ
    { 327,	1,	1,	2,	0,	0,	0,	AVRImpOpBase + 0,	193,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #327 = CopyZero
    { 326,	2,	0,	2,	0,	0,	1,	AVRImpOpBase + 2,	191,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #326 = CPWRdRr
    { 325,	2,	0,	2,	0,	1,	1,	AVRImpOpBase + 0,	191,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #325 = CPCWRdRr
    { 324,	2,	1,	2,	0,	0,	1,	AVRImpOpBase + 2,	161,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #324 = COMWRd
    { 323,	2,	0,	2,	0,	0,	0,	AVRImpOpBase + 0,	189,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #323 = AtomicStore8
    { 322,	2,	0,	2,	0,	0,	0,	AVRImpOpBase + 0,	187,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #322 = AtomicStore16
    { 321,	3,	1,	2,	0,	0,	0,	AVRImpOpBase + 0,	184,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #321 = AtomicLoadXor8
    { 320,	3,	1,	2,	0,	0,	0,	AVRImpOpBase + 0,	181,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #320 = AtomicLoadXor16
    { 319,	3,	1,	2,	0,	0,	0,	AVRImpOpBase + 0,	184,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #319 = AtomicLoadSub8
    { 318,	3,	1,	2,	0,	0,	0,	AVRImpOpBase + 0,	181,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #318 = AtomicLoadSub16
    { 317,	3,	1,	2,	0,	0,	0,	AVRImpOpBase + 0,	184,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #317 = AtomicLoadOr8
    { 316,	3,	1,	2,	0,	0,	0,	AVRImpOpBase + 0,	181,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #316 = AtomicLoadOr16
    { 315,	3,	1,	2,	0,	0,	0,	AVRImpOpBase + 0,	184,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #315 = AtomicLoadAnd8
    { 314,	3,	1,	2,	0,	0,	0,	AVRImpOpBase + 0,	181,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #314 = AtomicLoadAnd16
    { 313,	3,	1,	2,	0,	0,	0,	AVRImpOpBase + 0,	184,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #313 = AtomicLoadAdd8
    { 312,	3,	1,	2,	0,	0,	0,	AVRImpOpBase + 0,	181,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #312 = AtomicLoadAdd16
    { 311,	2,	1,	2,	0,	0,	0,	AVRImpOpBase + 0,	179,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #311 = AtomicLoad8
    { 310,	2,	1,	2,	0,	0,	0,	AVRImpOpBase + 0,	177,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #310 = AtomicLoad16
    { 309,	0,	0,	2,	0,	0,	0,	AVRImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #309 = AtomicFence
    { 308,	3,	1,	2,	0,	0,	1,	AVRImpOpBase + 2,	174,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #308 = Asr8
    { 307,	5,	2,	2,	0,	0,	1,	AVRImpOpBase + 2,	169,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #307 = Asr32
    { 306,	3,	1,	2,	0,	0,	1,	AVRImpOpBase + 2,	166,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #306 = Asr16
    { 305,	2,	1,	2,	0,	0,	1,	AVRImpOpBase + 2,	161,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #305 = ASRWRd
    { 304,	3,	1,	2,	0,	0,	1,	AVRImpOpBase + 2,	163,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #304 = ASRWNRd
    { 303,	2,	1,	2,	0,	0,	1,	AVRImpOpBase + 2,	161,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #303 = ASRWLoRd
    { 302,	3,	1,	2,	0,	0,	1,	AVRImpOpBase + 2,	158,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #302 = ASRBNRd
    { 301,	3,	1,	2,	0,	0,	1,	AVRImpOpBase + 2,	152,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #301 = ANDWRdRr
    { 300,	3,	1,	2,	0,	0,	1,	AVRImpOpBase + 2,	155,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #300 = ANDIWRdK
    { 299,	2,	0,	2,	0,	1,	1,	AVRImpOpBase + 6,	21,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #299 = ADJCALLSTACKUP
    { 298,	2,	0,	2,	0,	1,	2,	AVRImpOpBase + 3,	21,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #298 = ADJCALLSTACKDOWN
    { 297,	3,	1,	2,	0,	0,	1,	AVRImpOpBase + 2,	152,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #297 = ADDWRdRr
    { 296,	3,	1,	2,	0,	1,	1,	AVRImpOpBase + 0,	152,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #296 = ADCWRdRr
    { 295,	4,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	148,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #295 = G_UBFX
    { 294,	4,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	148,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #294 = G_SBFX
    { 293,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #293 = G_VECREDUCE_UMIN
    { 292,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #292 = G_VECREDUCE_UMAX
    { 291,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #291 = G_VECREDUCE_SMIN
    { 290,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #290 = G_VECREDUCE_SMAX
    { 289,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #289 = G_VECREDUCE_XOR
    { 288,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #288 = G_VECREDUCE_OR
    { 287,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #287 = G_VECREDUCE_AND
    { 286,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #286 = G_VECREDUCE_MUL
    { 285,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #285 = G_VECREDUCE_ADD
    { 284,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #284 = G_VECREDUCE_FMINIMUM
    { 283,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #283 = G_VECREDUCE_FMAXIMUM
    { 282,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #282 = G_VECREDUCE_FMIN
    { 281,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #281 = G_VECREDUCE_FMAX
    { 280,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #280 = G_VECREDUCE_FMUL
    { 279,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #279 = G_VECREDUCE_FADD
    { 278,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	131,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #278 = G_VECREDUCE_SEQ_FMUL
    { 277,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	131,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #277 = G_VECREDUCE_SEQ_FADD
    { 276,	1,	0,	0,	0,	0,	0,	AVRImpOpBase + 0,	1,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #276 = G_UBSANTRAP
    { 275,	0,	0,	0,	0,	0,	0,	AVRImpOpBase + 0,	1,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #275 = G_DEBUGTRAP
    { 274,	0,	0,	0,	0,	0,	0,	AVRImpOpBase + 0,	1,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #274 = G_TRAP
    { 273,	3,	0,	0,	0,	0,	0,	AVRImpOpBase + 0,	58,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #273 = G_BZERO
    { 272,	4,	0,	0,	0,	0,	0,	AVRImpOpBase + 0,	144,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #272 = G_MEMSET
    { 271,	4,	0,	0,	0,	0,	0,	AVRImpOpBase + 0,	144,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #271 = G_MEMMOVE
    { 270,	3,	0,	0,	0,	0,	0,	AVRImpOpBase + 0,	131,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #270 = G_MEMCPY_INLINE
    { 269,	4,	0,	0,	0,	0,	0,	AVRImpOpBase + 0,	144,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #269 = G_MEMCPY
    { 268,	2,	0,	0,	0,	0,	0,	AVRImpOpBase + 0,	142,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL },  // Inst #268 = G_WRITE_REGISTER
    { 267,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	51,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL },  // Inst #267 = G_READ_REGISTER
    { 266,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	101,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #266 = G_STRICT_FLDEXP
    { 265,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #265 = G_STRICT_FSQRT
    { 264,	4,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	46,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #264 = G_STRICT_FMA
    { 263,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #263 = G_STRICT_FREM
    { 262,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #262 = G_STRICT_FDIV
    { 261,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #261 = G_STRICT_FMUL
    { 260,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #260 = G_STRICT_FSUB
    { 259,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #259 = G_STRICT_FADD
    { 258,	1,	0,	0,	0,	0,	0,	AVRImpOpBase + 0,	50,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #258 = G_STACKRESTORE
    { 257,	1,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	50,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #257 = G_STACKSAVE
    { 256,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	69,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #256 = G_DYN_STACKALLOC
    { 255,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	51,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #255 = G_JUMP_TABLE
    { 254,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	51,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #254 = G_BLOCK_ADDR
    { 253,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #253 = G_ADDRSPACE_CAST
    { 252,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #252 = G_FNEARBYINT
    { 251,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #251 = G_FRINT
    { 250,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #250 = G_FFLOOR
    { 249,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #249 = G_FSQRT
    { 248,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #248 = G_FTANH
    { 247,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #247 = G_FSINH
    { 246,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #246 = G_FCOSH
    { 245,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #245 = G_FATAN
    { 244,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #244 = G_FASIN
    { 243,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #243 = G_FACOS
    { 242,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #242 = G_FTAN
    { 241,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #241 = G_FSIN
    { 240,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #240 = G_FCOS
    { 239,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #239 = G_FCEIL
    { 238,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #238 = G_BITREVERSE
    { 237,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #237 = G_BSWAP
    { 236,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #236 = G_CTPOP
    { 235,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #235 = G_CTLZ_ZERO_UNDEF
    { 234,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #234 = G_CTLZ
    { 233,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #233 = G_CTTZ_ZERO_UNDEF
    { 232,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #232 = G_CTTZ
    { 231,	4,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	138,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #231 = G_VECTOR_COMPRESS
    { 230,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #230 = G_SPLAT_VECTOR
    { 229,	4,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	134,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #229 = G_SHUFFLE_VECTOR
    { 228,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	131,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #228 = G_EXTRACT_VECTOR_ELT
    { 227,	4,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	127,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #227 = G_INSERT_VECTOR_ELT
    { 226,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	40,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #226 = G_EXTRACT_SUBVECTOR
    { 225,	4,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	63,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #225 = G_INSERT_SUBVECTOR
    { 224,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	51,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #224 = G_VSCALE
    { 223,	3,	0,	0,	0,	0,	0,	AVRImpOpBase + 0,	124,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #223 = G_BRJT
    { 222,	1,	0,	0,	0,	0,	0,	AVRImpOpBase + 0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #222 = G_BR
    { 221,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #221 = G_LLROUND
    { 220,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #220 = G_LROUND
    { 219,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #219 = G_ABS
    { 218,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #218 = G_UMAX
    { 217,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #217 = G_UMIN
    { 216,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #216 = G_SMAX
    { 215,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #215 = G_SMIN
    { 214,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	101,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #214 = G_PTRMASK
    { 213,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	101,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #213 = G_PTR_ADD
    { 212,	0,	0,	0,	0,	0,	0,	AVRImpOpBase + 0,	1,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #212 = G_RESET_FPMODE
    { 211,	1,	0,	0,	0,	0,	0,	AVRImpOpBase + 0,	50,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #211 = G_SET_FPMODE
    { 210,	1,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	50,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #210 = G_GET_FPMODE
    { 209,	0,	0,	0,	0,	0,	0,	AVRImpOpBase + 0,	1,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #209 = G_RESET_FPENV
    { 208,	1,	0,	0,	0,	0,	0,	AVRImpOpBase + 0,	50,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #208 = G_SET_FPENV
    { 207,	1,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	50,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #207 = G_GET_FPENV
    { 206,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #206 = G_FMAXIMUM
    { 205,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #205 = G_FMINIMUM
    { 204,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #204 = G_FMAXNUM_IEEE
    { 203,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #203 = G_FMINNUM_IEEE
    { 202,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #202 = G_FMAXNUM
    { 201,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #201 = G_FMINNUM
    { 200,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #200 = G_FCANONICALIZE
    { 199,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	98,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #199 = G_IS_FPCLASS
    { 198,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	101,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #198 = G_FCOPYSIGN
    { 197,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #197 = G_FABS
    { 196,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #196 = G_UITOFP
    { 195,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #195 = G_SITOFP
    { 194,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #194 = G_FPTOUI
    { 193,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #193 = G_FPTOSI
    { 192,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #192 = G_FPTRUNC
    { 191,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #191 = G_FPEXT
    { 190,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #190 = G_FNEG
    { 189,	3,	2,	0,	0,	0,	0,	AVRImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #189 = G_FFREXP
    { 188,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	101,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #188 = G_FLDEXP
    { 187,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #187 = G_FLOG10
    { 186,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #186 = G_FLOG2
    { 185,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #185 = G_FLOG
    { 184,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #184 = G_FEXP10
    { 183,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #183 = G_FEXP2
    { 182,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #182 = G_FEXP
    { 181,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	101,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #181 = G_FPOWI
    { 180,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #180 = G_FPOW
    { 179,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #179 = G_FREM
    { 178,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #178 = G_FDIV
    { 177,	4,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	46,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #177 = G_FMAD
    { 176,	4,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	46,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #176 = G_FMA
    { 175,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #175 = G_FMUL
    { 174,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #174 = G_FSUB
    { 173,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #173 = G_FADD
    { 172,	4,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	120,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #172 = G_UDIVFIXSAT
    { 171,	4,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	120,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #171 = G_SDIVFIXSAT
    { 170,	4,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	120,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #170 = G_UDIVFIX
    { 169,	4,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	120,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #169 = G_SDIVFIX
    { 168,	4,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	120,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #168 = G_UMULFIXSAT
    { 167,	4,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	120,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #167 = G_SMULFIXSAT
    { 166,	4,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	120,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #166 = G_UMULFIX
    { 165,	4,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	120,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #165 = G_SMULFIX
    { 164,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	101,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #164 = G_SSHLSAT
    { 163,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	101,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #163 = G_USHLSAT
    { 162,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #162 = G_SSUBSAT
    { 161,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #161 = G_USUBSAT
    { 160,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #160 = G_SADDSAT
    { 159,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #159 = G_UADDSAT
    { 158,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #158 = G_SMULH
    { 157,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #157 = G_UMULH
    { 156,	4,	2,	0,	0,	0,	0,	AVRImpOpBase + 0,	87,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #156 = G_SMULO
    { 155,	4,	2,	0,	0,	0,	0,	AVRImpOpBase + 0,	87,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #155 = G_UMULO
    { 154,	5,	2,	0,	0,	0,	0,	AVRImpOpBase + 0,	115,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #154 = G_SSUBE
    { 153,	4,	2,	0,	0,	0,	0,	AVRImpOpBase + 0,	87,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #153 = G_SSUBO
    { 152,	5,	2,	0,	0,	0,	0,	AVRImpOpBase + 0,	115,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #152 = G_SADDE
    { 151,	4,	2,	0,	0,	0,	0,	AVRImpOpBase + 0,	87,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #151 = G_SADDO
    { 150,	5,	2,	0,	0,	0,	0,	AVRImpOpBase + 0,	115,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #150 = G_USUBE
    { 149,	4,	2,	0,	0,	0,	0,	AVRImpOpBase + 0,	87,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #149 = G_USUBO
    { 148,	5,	2,	0,	0,	0,	0,	AVRImpOpBase + 0,	115,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #148 = G_UADDE
    { 147,	4,	2,	0,	0,	0,	0,	AVRImpOpBase + 0,	87,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #147 = G_UADDO
    { 146,	4,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	87,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #146 = G_SELECT
    { 145,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	112,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #145 = G_UCMP
    { 144,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	112,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #144 = G_SCMP
    { 143,	4,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	108,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #143 = G_FCMP
    { 142,	4,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	108,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #142 = G_ICMP
    { 141,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	101,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #141 = G_ROTL
    { 140,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	101,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #140 = G_ROTR
    { 139,	4,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	104,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #139 = G_FSHR
    { 138,	4,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	104,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #138 = G_FSHL
    { 137,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	101,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #137 = G_ASHR
    { 136,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	101,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #136 = G_LSHR
    { 135,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	101,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #135 = G_SHL
    { 134,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #134 = G_ZEXT
    { 133,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	40,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #133 = G_SEXT_INREG
    { 132,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #132 = G_SEXT
    { 131,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	98,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #131 = G_VAARG
    { 130,	1,	0,	0,	0,	0,	0,	AVRImpOpBase + 0,	50,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #130 = G_VASTART
    { 129,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	51,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #129 = G_FCONSTANT
    { 128,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	51,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #128 = G_CONSTANT
    { 127,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #127 = G_TRUNC
    { 126,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #126 = G_ANYEXT
    { 125,	1,	0,	0,	0,	0,	0,	AVRImpOpBase + 0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL },  // Inst #125 = G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
    { 124,	1,	0,	0,	0,	0,	0,	AVRImpOpBase + 0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL },  // Inst #124 = G_INTRINSIC_CONVERGENT
    { 123,	1,	0,	0,	0,	0,	0,	AVRImpOpBase + 0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #123 = G_INTRINSIC_W_SIDE_EFFECTS
    { 122,	1,	0,	0,	0,	0,	0,	AVRImpOpBase + 0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #122 = G_INTRINSIC
    { 121,	0,	0,	0,	0,	0,	0,	AVRImpOpBase + 0,	1,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #121 = G_INVOKE_REGION_START
    { 120,	1,	0,	0,	0,	0,	0,	AVRImpOpBase + 0,	50,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #120 = G_BRINDIRECT
    { 119,	2,	0,	0,	0,	0,	0,	AVRImpOpBase + 0,	51,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #119 = G_BRCOND
    { 118,	4,	0,	0,	0,	0,	0,	AVRImpOpBase + 0,	94,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #118 = G_PREFETCH
    { 117,	2,	0,	0,	0,	0,	0,	AVRImpOpBase + 0,	21,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #117 = G_FENCE
    { 116,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #116 = G_ATOMICRMW_UDEC_WRAP
    { 115,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #115 = G_ATOMICRMW_UINC_WRAP
    { 114,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #114 = G_ATOMICRMW_FMIN
    { 113,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #113 = G_ATOMICRMW_FMAX
    { 112,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #112 = G_ATOMICRMW_FSUB
    { 111,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #111 = G_ATOMICRMW_FADD
    { 110,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #110 = G_ATOMICRMW_UMIN
    { 109,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #109 = G_ATOMICRMW_UMAX
    { 108,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #108 = G_ATOMICRMW_MIN
    { 107,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #107 = G_ATOMICRMW_MAX
    { 106,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #106 = G_ATOMICRMW_XOR
    { 105,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #105 = G_ATOMICRMW_OR
    { 104,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #104 = G_ATOMICRMW_NAND
    { 103,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #103 = G_ATOMICRMW_AND
    { 102,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #102 = G_ATOMICRMW_SUB
    { 101,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #101 = G_ATOMICRMW_ADD
    { 100,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #100 = G_ATOMICRMW_XCHG
    { 99,	4,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	87,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #99 = G_ATOMIC_CMPXCHG
    { 98,	5,	2,	0,	0,	0,	0,	AVRImpOpBase + 0,	82,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #98 = G_ATOMIC_CMPXCHG_WITH_SUCCESS
    { 97,	5,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	77,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #97 = G_INDEXED_STORE
    { 96,	2,	0,	0,	0,	0,	0,	AVRImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #96 = G_STORE
    { 95,	5,	2,	0,	0,	0,	0,	AVRImpOpBase + 0,	72,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #95 = G_INDEXED_ZEXTLOAD
    { 94,	5,	2,	0,	0,	0,	0,	AVRImpOpBase + 0,	72,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #94 = G_INDEXED_SEXTLOAD
    { 93,	5,	2,	0,	0,	0,	0,	AVRImpOpBase + 0,	72,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #93 = G_INDEXED_LOAD
    { 92,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #92 = G_ZEXTLOAD
    { 91,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #91 = G_SEXTLOAD
    { 90,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #90 = G_LOAD
    { 89,	1,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	50,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #89 = G_READSTEADYCOUNTER
    { 88,	1,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	50,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #88 = G_READCYCLECOUNTER
    { 87,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #87 = G_INTRINSIC_ROUNDEVEN
    { 86,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #86 = G_INTRINSIC_LLRINT
    { 85,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #85 = G_INTRINSIC_LRINT
    { 84,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #84 = G_INTRINSIC_ROUND
    { 83,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #83 = G_INTRINSIC_TRUNC
    { 82,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	69,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #82 = G_INTRINSIC_FPTRUNC_ROUND
    { 81,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #81 = G_CONSTANT_FOLD_BARRIER
    { 80,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #80 = G_FREEZE
    { 79,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #79 = G_BITCAST
    { 78,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #78 = G_INTTOPTR
    { 77,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #77 = G_PTRTOINT
    { 76,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #76 = G_CONCAT_VECTORS
    { 75,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #75 = G_BUILD_VECTOR_TRUNC
    { 74,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #74 = G_BUILD_VECTOR
    { 73,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #73 = G_MERGE_VALUES
    { 72,	4,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	63,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #72 = G_INSERT
    { 71,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #71 = G_UNMERGE_VALUES
    { 70,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	58,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #70 = G_EXTRACT
    { 69,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	51,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #69 = G_CONSTANT_POOL
    { 68,	5,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	53,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #68 = G_PTRAUTH_GLOBAL_VALUE
    { 67,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	51,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #67 = G_GLOBAL_VALUE
    { 66,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	51,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #66 = G_FRAME_INDEX
    { 65,	1,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	50,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #65 = G_PHI
    { 64,	1,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	50,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #64 = G_IMPLICIT_DEF
    { 63,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #63 = G_XOR
    { 62,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #62 = G_OR
    { 61,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #61 = G_AND
    { 60,	4,	2,	0,	0,	0,	0,	AVRImpOpBase + 0,	46,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #60 = G_UDIVREM
    { 59,	4,	2,	0,	0,	0,	0,	AVRImpOpBase + 0,	46,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #59 = G_SDIVREM
    { 58,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #58 = G_UREM
    { 57,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #57 = G_SREM
    { 56,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #56 = G_UDIV
    { 55,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #55 = G_SDIV
    { 54,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #54 = G_MUL
    { 53,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #53 = G_SUB
    { 52,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #52 = G_ADD
    { 51,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	40,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #51 = G_ASSERT_ALIGN
    { 50,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	40,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #50 = G_ASSERT_ZEXT
    { 49,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	40,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #49 = G_ASSERT_SEXT
    { 48,	1,	0,	0,	0,	0,	0,	AVRImpOpBase + 0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL },  // Inst #48 = CONVERGENCECTRL_GLUE
    { 47,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	13,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL },  // Inst #47 = CONVERGENCECTRL_LOOP
    { 46,	1,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL },  // Inst #46 = CONVERGENCECTRL_ANCHOR
    { 45,	1,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL },  // Inst #45 = CONVERGENCECTRL_ENTRY
    { 44,	1,	0,	0,	0,	0,	0,	AVRImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #44 = JUMP_TABLE_DEBUG_INFO
    { 43,	0,	0,	0,	0,	0,	0,	AVRImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #43 = MEMBARRIER
    { 42,	0,	0,	0,	0,	0,	0,	AVRImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #42 = FAKE_USE
    { 41,	0,	0,	0,	0,	0,	0,	AVRImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #41 = ICALL_BRANCH_FUNNEL
    { 40,	3,	0,	0,	0,	0,	0,	AVRImpOpBase + 0,	37,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #40 = PATCHABLE_TYPED_EVENT_CALL
    { 39,	2,	0,	0,	0,	0,	0,	AVRImpOpBase + 0,	35,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #39 = PATCHABLE_EVENT_CALL
    { 38,	0,	0,	0,	0,	0,	0,	AVRImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #38 = PATCHABLE_TAIL_CALL
    { 37,	0,	0,	0,	0,	0,	0,	AVRImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #37 = PATCHABLE_FUNCTION_EXIT
    { 36,	0,	0,	0,	0,	0,	0,	AVRImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #36 = PATCHABLE_RET
    { 35,	0,	0,	0,	0,	0,	0,	AVRImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #35 = PATCHABLE_FUNCTION_ENTER
    { 34,	0,	0,	0,	0,	0,	0,	AVRImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #34 = PATCHABLE_OP
    { 33,	1,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #33 = FAULTING_OP
    { 32,	2,	0,	0,	0,	0,	0,	AVRImpOpBase + 0,	33,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #32 = LOCAL_ESCAPE
    { 31,	0,	0,	0,	0,	0,	0,	AVRImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #31 = STATEPOINT
    { 30,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	30,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #30 = PREALLOCATED_ARG
    { 29,	1,	0,	0,	0,	0,	0,	AVRImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #29 = PREALLOCATED_SETUP
    { 28,	1,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	29,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #28 = LOAD_STACK_GUARD
    { 27,	6,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	23,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #27 = PATCHPOINT
    { 26,	0,	0,	0,	0,	0,	0,	AVRImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #26 = FENTRY_CALL
    { 25,	2,	0,	0,	0,	0,	0,	AVRImpOpBase + 0,	21,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #25 = STACKMAP
    { 24,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	19,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #24 = ARITH_FENCE
    { 23,	4,	0,	0,	0,	0,	0,	AVRImpOpBase + 0,	15,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #23 = PSEUDO_PROBE
    { 22,	1,	0,	0,	0,	0,	0,	AVRImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #22 = LIFETIME_END
    { 21,	1,	0,	0,	0,	0,	0,	AVRImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #21 = LIFETIME_START
    { 20,	0,	0,	0,	0,	0,	0,	AVRImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #20 = BUNDLE
    { 19,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	13,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #19 = COPY
    { 18,	2,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	13,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #18 = REG_SEQUENCE
    { 17,	1,	0,	0,	0,	0,	0,	AVRImpOpBase + 0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #17 = DBG_LABEL
    { 16,	0,	0,	0,	0,	0,	0,	AVRImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #16 = DBG_PHI
    { 15,	0,	0,	0,	0,	0,	0,	AVRImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #15 = DBG_INSTR_REF
    { 14,	0,	0,	0,	0,	0,	0,	AVRImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #14 = DBG_VALUE_LIST
    { 13,	0,	0,	0,	0,	0,	0,	AVRImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #13 = DBG_VALUE
    { 12,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #12 = COPY_TO_REGCLASS
    { 11,	4,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	9,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #11 = SUBREG_TO_REG
    { 10,	1,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #10 = IMPLICIT_DEF
    { 9,	4,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	5,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #9 = INSERT_SUBREG
    { 8,	3,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #8 = EXTRACT_SUBREG
    { 7,	0,	0,	0,	0,	0,	0,	AVRImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #7 = KILL
    { 6,	1,	0,	0,	0,	0,	0,	AVRImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #6 = ANNOTATION_LABEL
    { 5,	1,	0,	0,	0,	0,	0,	AVRImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #5 = GC_LABEL
    { 4,	1,	0,	0,	0,	0,	0,	AVRImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #4 = EH_LABEL
    { 3,	1,	0,	0,	0,	0,	0,	AVRImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #3 = CFI_INSTRUCTION
    { 2,	0,	0,	0,	0,	0,	0,	AVRImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #2 = INLINEASM_BR
    { 1,	0,	0,	0,	0,	0,	0,	AVRImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1 = INLINEASM
    { 0,	1,	1,	0,	0,	0,	0,	AVRImpOpBase + 0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #0 = PHI
  }, {
    /* 0 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 1 */
    /* 1 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 2 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 5 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 9 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 13 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 15 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 19 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) },
    /* 21 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 23 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 29 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 },
    /* 30 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 33 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 35 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 37 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 40 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
    /* 43 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
    /* 46 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
    /* 50 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
    /* 51 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 53 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 58 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
    /* 61 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
    /* 63 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
    /* 67 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
    /* 69 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 72 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 77 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 82 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
    /* 87 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
    /* 91 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
    /* 94 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 98 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 101 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
    /* 104 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
    /* 108 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
    /* 112 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
    /* 115 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
    /* 120 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
    /* 124 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
    /* 127 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
    /* 131 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
    /* 134 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 138 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
    /* 142 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
    /* 144 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
    /* 148 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
    /* 152 */ { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 155 */ { AVR::DLDREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::DLDREGSRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 158 */ { AVR::LD8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 161 */ { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
    /* 163 */ { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 166 */ { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 169 */ { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 174 */ { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 177 */ { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::PTRDISPREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 179 */ { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::PTRREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 181 */ { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::PTRDISPREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 184 */ { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::PTRREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 187 */ { AVR::PTRDISPREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 189 */ { AVR::PTRREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 191 */ { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 193 */ { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 194 */ { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::ZREGRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::LD8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 197 */ { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { AVR::ZREGRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::LD8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 200 */ { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::ZREGRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::LD8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 203 */ { AVR::DLDREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::DLDREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 206 */ { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 208 */ { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { AVR::PTRDISPREGSRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 211 */ { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::PTRDISPREGSRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 214 */ { AVR::DLDREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 216 */ { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 218 */ { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { AVR::PTRDISPREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 220 */ { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { AVR::PTRREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::PTRREGSRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) },
    /* 223 */ { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::ZREGRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 225 */ { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { AVR::ZREGRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 227 */ { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::ZREGRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 229 */ { AVR::DLDREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 232 */ { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 235 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 237 */ { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 238 */ { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
    /* 240 */ { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 242 */ { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::GPRSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 244 */ { AVR::GPRSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 246 */ { AVR::GPRSPRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 249 */ { AVR::PTRDISPREGSRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 252 */ { AVR::GPRSPRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 255 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 257 */ { AVR::PTRREGSRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { AVR::PTRREGSRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 261 */ { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::DREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 265 */ { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 269 */ { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 272 */ { AVR::IWREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::IWREGSRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 275 */ { AVR::LD8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::LD8RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 278 */ { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 281 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 283 */ { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 285 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 287 */ { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 289 */ { AVR::LD8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 291 */ { AVR::LD8loRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::LD8loRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 293 */ { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 295 */ { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::PTRDISPREGSRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 298 */ { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::PTRREGSRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 300 */ { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { AVR::PTRREGSRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::PTRREGSRegClassID, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(1) },
    /* 303 */ { AVR::LD8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AVR::LD8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 305 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 307 */ { AVR::ZREGRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 308 */ { AVR::PTRDISPREGSRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 311 */ { AVR::PTRREGSRegClassID, 0, MCOI::OPERAND_UNKNOWN, MCOI_EARLY_CLOBBER }, { AVR::PTRREGSRegClassID, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) }, { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 315 */ { AVR::PTRREGSRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { AVR::GPR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 317 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { AVR::LD8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
  }, {
    /* 0 */
    /* 0 */ AVR::SREG, AVR::SREG,
    /* 2 */ AVR::SREG,
    /* 3 */ AVR::SP, AVR::SP, AVR::SREG,
    /* 6 */ AVR::SP, AVR::R31R30,
    /* 8 */ AVR::R0,
    /* 9 */ AVR::R31R30,
    /* 10 */ AVR::SP, AVR::SP,
    /* 12 */ AVR::R1, AVR::SREG,
    /* 14 */ AVR::R17, AVR::SREG,
    /* 16 */ AVR::SP,
    /* 17 */ AVR::R15, AVR::R14, AVR::R13, AVR::R12, AVR::R11, AVR::R10, AVR::R9, AVR::R8, AVR::R7, AVR::R6, AVR::R5, AVR::R4, AVR::R3, AVR::R2, AVR::R1, AVR::R0,
    /* 33 */ AVR::R31R30, AVR::R0,
    /* 35 */ AVR::R1, AVR::R0, AVR::SREG,
    /* 38 */ AVR::R31R30, AVR::R1, AVR::R0,
    /* 41 */ AVR::R1, AVR::R0, AVR::R31R30,
  }
};


#ifdef __GNUC__
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Woverlength-strings"
#endif
extern const char AVRInstrNameData[] = {
  /* 0 */ "G_FLOG10\0"
  /* 9 */ "G_FEXP10\0"
  /* 18 */ "ROLBRdR1\0"
  /* 27 */ "Lsl32\0"
  /* 33 */ "Asr32\0"
  /* 39 */ "Lsr32\0"
  /* 45 */ "G_FLOG2\0"
  /* 53 */ "G_FEXP2\0"
  /* 61 */ "AtomicLoadSub16\0"
  /* 77 */ "AtomicLoad16\0"
  /* 90 */ "AtomicLoadAdd16\0"
  /* 106 */ "AtomicLoadAnd16\0"
  /* 122 */ "AtomicStore16\0"
  /* 136 */ "Rol16\0"
  /* 142 */ "Lsl16\0"
  /* 148 */ "AtomicLoadOr16\0"
  /* 163 */ "Ror16\0"
  /* 169 */ "AtomicLoadXor16\0"
  /* 185 */ "Asr16\0"
  /* 191 */ "Lsr16\0"
  /* 197 */ "Select16\0"
  /* 206 */ "ROLBRdR17\0"
  /* 216 */ "AtomicLoadSub8\0"
  /* 231 */ "AtomicLoad8\0"
  /* 243 */ "AtomicLoadAdd8\0"
  /* 258 */ "AtomicLoadAnd8\0"
  /* 273 */ "AtomicStore8\0"
  /* 286 */ "Rol8\0"
  /* 291 */ "Lsl8\0"
  /* 296 */ "AtomicLoadOr8\0"
  /* 310 */ "Ror8\0"
  /* 315 */ "AtomicLoadXor8\0"
  /* 330 */ "Asr8\0"
  /* 335 */ "Lsr8\0"
  /* 340 */ "Select8\0"
  /* 348 */ "G_FMA\0"
  /* 354 */ "G_STRICT_FMA\0"
  /* 367 */ "INRdA\0"
  /* 373 */ "INWRdA\0"
  /* 380 */ "G_FSUB\0"
  /* 387 */ "G_STRICT_FSUB\0"
  /* 401 */ "G_ATOMICRMW_FSUB\0"
  /* 418 */ "G_SUB\0"
  /* 424 */ "G_ATOMICRMW_SUB\0"
  /* 440 */ "SBRCRrB\0"
  /* 448 */ "SBRSRrB\0"
  /* 456 */ "G_INTRINSIC\0"
  /* 468 */ "G_FPTRUNC\0"
  /* 478 */ "G_INTRINSIC_TRUNC\0"
  /* 496 */ "G_TRUNC\0"
  /* 504 */ "G_BUILD_VECTOR_TRUNC\0"
  /* 525 */ "G_DYN_STACKALLOC\0"
  /* 542 */ "SPREAD\0"
  /* 549 */ "G_FMAD\0"
  /* 556 */ "G_INDEXED_SEXTLOAD\0"
  /* 575 */ "G_SEXTLOAD\0"
  /* 586 */ "G_INDEXED_ZEXTLOAD\0"
  /* 605 */ "G_ZEXTLOAD\0"
  /* 616 */ "G_INDEXED_LOAD\0"
  /* 631 */ "G_LOAD\0"
  /* 638 */ "G_VECREDUCE_FADD\0"
  /* 655 */ "G_FADD\0"
  /* 662 */ "G_VECREDUCE_SEQ_FADD\0"
  /* 683 */ "G_STRICT_FADD\0"
  /* 697 */ "G_ATOMICRMW_FADD\0"
  /* 714 */ "G_VECREDUCE_ADD\0"
  /* 730 */ "G_ADD\0"
  /* 736 */ "G_PTR_ADD\0"
  /* 746 */ "G_ATOMICRMW_ADD\0"
  /* 762 */ "BLD\0"
  /* 766 */ "G_ATOMICRMW_NAND\0"
  /* 783 */ "G_VECREDUCE_AND\0"
  /* 799 */ "G_AND\0"
  /* 805 */ "G_ATOMICRMW_AND\0"
  /* 821 */ "LIFETIME_END\0"
  /* 834 */ "G_BRCOND\0"
  /* 843 */ "G_LLROUND\0"
  /* 853 */ "G_LROUND\0"
  /* 862 */ "G_INTRINSIC_ROUND\0"
  /* 880 */ "G_INTRINSIC_FPTRUNC_ROUND\0"
  /* 906 */ "LOAD_STACK_GUARD\0"
  /* 923 */ "PSEUDO_PROBE\0"
  /* 936 */ "G_SSUBE\0"
  /* 944 */ "G_USUBE\0"
  /* 952 */ "G_FENCE\0"
  /* 960 */ "ARITH_FENCE\0"
  /* 972 */ "REG_SEQUENCE\0"
  /* 985 */ "G_SADDE\0"
  /* 993 */ "G_UADDE\0"
  /* 1001 */ "G_GET_FPMODE\0"
  /* 1014 */ "G_RESET_FPMODE\0"
  /* 1029 */ "G_SET_FPMODE\0"
  /* 1042 */ "G_FMINNUM_IEEE\0"
  /* 1057 */ "G_FMAXNUM_IEEE\0"
  /* 1072 */ "G_VSCALE\0"
  /* 1081 */ "G_JUMP_TABLE\0"
  /* 1094 */ "BUNDLE\0"
  /* 1101 */ "G_MEMCPY_INLINE\0"
  /* 1117 */ "LOCAL_ESCAPE\0"
  /* 1130 */ "G_STACKRESTORE\0"
  /* 1145 */ "G_INDEXED_STORE\0"
  /* 1161 */ "G_STORE\0"
  /* 1169 */ "CPSE\0"
  /* 1174 */ "G_BITREVERSE\0"
  /* 1187 */ "FAKE_USE\0"
  /* 1196 */ "SPWRITE\0"
  /* 1204 */ "DBG_VALUE\0"
  /* 1214 */ "G_GLOBAL_VALUE\0"
  /* 1229 */ "G_PTRAUTH_GLOBAL_VALUE\0"
  /* 1252 */ "CONVERGENCECTRL_GLUE\0"
  /* 1273 */ "G_STACKSAVE\0"
  /* 1285 */ "G_MEMMOVE\0"
  /* 1295 */ "G_FREEZE\0"
  /* 1304 */ "G_FCANONICALIZE\0"
  /* 1320 */ "G_CTLZ_ZERO_UNDEF\0"
  /* 1338 */ "G_CTTZ_ZERO_UNDEF\0"
  /* 1356 */ "G_IMPLICIT_DEF\0"
  /* 1371 */ "DBG_INSTR_REF\0"
  /* 1385 */ "G_FNEG\0"
  /* 1392 */ "EXTRACT_SUBREG\0"
  /* 1407 */ "INSERT_SUBREG\0"
  /* 1421 */ "G_SEXT_INREG\0"
  /* 1434 */ "SUBREG_TO_REG\0"
  /* 1448 */ "G_ATOMIC_CMPXCHG\0"
  /* 1465 */ "G_ATOMICRMW_XCHG\0"
  /* 1482 */ "G_FLOG\0"
  /* 1489 */ "G_VAARG\0"
  /* 1497 */ "PREALLOCATED_ARG\0"
  /* 1514 */ "G_PREFETCH\0"
  /* 1525 */ "G_SMULH\0"
  /* 1533 */ "G_UMULH\0"
  /* 1541 */ "G_FTANH\0"
  /* 1549 */ "G_FSINH\0"
  /* 1557 */ "G_FCOSH\0"
  /* 1565 */ "DBG_PHI\0"
  /* 1573 */ "G_FPTOSI\0"
  /* 1582 */ "RETI\0"
  /* 1587 */ "G_FPTOUI\0"
  /* 1596 */ "G_FPOWI\0"
  /* 1604 */ "BREAK\0"
  /* 1610 */ "G_PTRMASK\0"
  /* 1620 */ "DESK\0"
  /* 1625 */ "SUBIRdK\0"
  /* 1633 */ "SBCIRdK\0"
  /* 1641 */ "LDIRdK\0"
  /* 1648 */ "ANDIRdK\0"
  /* 1656 */ "CPIRdK\0"
  /* 1663 */ "ORIRdK\0"
  /* 1670 */ "LDSRdK\0"
  /* 1677 */ "SBIWRdK\0"
  /* 1685 */ "SUBIWRdK\0"
  /* 1694 */ "SBCIWRdK\0"
  /* 1703 */ "ADIWRdK\0"
  /* 1711 */ "LDIWRdK\0"
  /* 1719 */ "ANDIWRdK\0"
  /* 1728 */ "ORIWRdK\0"
  /* 1736 */ "LDSWRdK\0"
  /* 1744 */ "GC_LABEL\0"
  /* 1753 */ "DBG_LABEL\0"
  /* 1763 */ "EH_LABEL\0"
  /* 1772 */ "ANNOTATION_LABEL\0"
  /* 1789 */ "ICALL_BRANCH_FUNNEL\0"
  /* 1809 */ "G_FSHL\0"
  /* 1816 */ "G_SHL\0"
  /* 1822 */ "G_FCEIL\0"
  /* 1830 */ "EICALL\0"
  /* 1837 */ "PATCHABLE_TAIL_CALL\0"
  /* 1857 */ "PATCHABLE_TYPED_EVENT_CALL\0"
  /* 1884 */ "PATCHABLE_EVENT_CALL\0"
  /* 1905 */ "FENTRY_CALL\0"
  /* 1917 */ "KILL\0"
  /* 1922 */ "G_CONSTANT_POOL\0"
  /* 1938 */ "G_ROTL\0"
  /* 1945 */ "G_VECREDUCE_FMUL\0"
  /* 1962 */ "G_FMUL\0"
  /* 1969 */ "G_VECREDUCE_SEQ_FMUL\0"
  /* 1990 */ "G_STRICT_FMUL\0"
  /* 2004 */ "G_VECREDUCE_MUL\0"
  /* 2020 */ "G_MUL\0"
  /* 2026 */ "G_FREM\0"
  /* 2033 */ "G_STRICT_FREM\0"
  /* 2047 */ "G_SREM\0"
  /* 2054 */ "G_UREM\0"
  /* 2061 */ "G_SDIVREM\0"
  /* 2071 */ "G_UDIVREM\0"
  /* 2081 */ "ELPM\0"
  /* 2086 */ "SPM\0"
  /* 2090 */ "INLINEASM\0"
  /* 2100 */ "G_VECREDUCE_FMINIMUM\0"
  /* 2121 */ "G_FMINIMUM\0"
  /* 2132 */ "G_VECREDUCE_FMAXIMUM\0"
  /* 2153 */ "G_FMAXIMUM\0"
  /* 2164 */ "G_FMINNUM\0"
  /* 2174 */ "G_FMAXNUM\0"
  /* 2184 */ "G_FATAN\0"
  /* 2192 */ "G_FTAN\0"
  /* 2199 */ "G_INTRINSIC_ROUNDEVEN\0"
  /* 2221 */ "G_ASSERT_ALIGN\0"
  /* 2236 */ "G_FCOPYSIGN\0"
  /* 2248 */ "G_VECREDUCE_FMIN\0"
  /* 2265 */ "G_ATOMICRMW_FMIN\0"
  /* 2282 */ "G_VECREDUCE_SMIN\0"
  /* 2299 */ "G_SMIN\0"
  /* 2306 */ "G_VECREDUCE_UMIN\0"
  /* 2323 */ "G_UMIN\0"
  /* 2330 */ "G_ATOMICRMW_UMIN\0"
  /* 2347 */ "G_ATOMICRMW_MIN\0"
  /* 2363 */ "G_FASIN\0"
  /* 2371 */ "G_FSIN\0"
  /* 2378 */ "CFI_INSTRUCTION\0"
  /* 2394 */ "ADJCALLSTACKDOWN\0"
  /* 2411 */ "G_SSUBO\0"
  /* 2419 */ "G_USUBO\0"
  /* 2427 */ "G_SADDO\0"
  /* 2435 */ "G_UADDO\0"
  /* 2443 */ "JUMP_TABLE_DEBUG_INFO\0"
  /* 2465 */ "G_SMULO\0"
  /* 2473 */ "G_UMULO\0"
  /* 2481 */ "G_BZERO\0"
  /* 2489 */ "STACKMAP\0"
  /* 2498 */ "G_DEBUGTRAP\0"
  /* 2510 */ "G_UBSANTRAP\0"
  /* 2522 */ "G_TRAP\0"
  /* 2529 */ "G_ATOMICRMW_UDEC_WRAP\0"
  /* 2551 */ "G_ATOMICRMW_UINC_WRAP\0"
  /* 2573 */ "G_BSWAP\0"
  /* 2581 */ "SLEEP\0"
  /* 2587 */ "G_SITOFP\0"
  /* 2596 */ "G_UITOFP\0"
  /* 2605 */ "G_FCMP\0"
  /* 2612 */ "G_ICMP\0"
  /* 2619 */ "G_SCMP\0"
  /* 2626 */ "G_UCMP\0"
  /* 2633 */ "EIJMP\0"
  /* 2639 */ "NOP\0"
  /* 2643 */ "CONVERGENCECTRL_LOOP\0"
  /* 2664 */ "G_CTPOP\0"
  /* 2672 */ "PATCHABLE_OP\0"
  /* 2685 */ "FAULTING_OP\0"
  /* 2697 */ "ADJCALLSTACKUP\0"
  /* 2712 */ "PREALLOCATED_SETUP\0"
  /* 2731 */ "G_FLDEXP\0"
  /* 2740 */ "G_STRICT_FLDEXP\0"
  /* 2756 */ "G_FEXP\0"
  /* 2763 */ "G_FFREXP\0"
  /* 2772 */ "LDDWRdYQ\0"
  /* 2781 */ "LDDRdPtrQ\0"
  /* 2791 */ "LDDWRdPtrQ\0"
  /* 2802 */ "G_BR\0"
  /* 2807 */ "INLINEASM_BR\0"
  /* 2820 */ "G_BLOCK_ADDR\0"
  /* 2833 */ "WDR\0"
  /* 2837 */ "MEMBARRIER\0"
  /* 2848 */ "G_CONSTANT_FOLD_BARRIER\0"
  /* 2872 */ "PATCHABLE_FUNCTION_ENTER\0"
  /* 2897 */ "G_READCYCLECOUNTER\0"
  /* 2916 */ "G_READSTEADYCOUNTER\0"
  /* 2936 */ "G_READ_REGISTER\0"
  /* 2952 */ "G_WRITE_REGISTER\0"
  /* 2969 */ "G_ASHR\0"
  /* 2976 */ "G_FSHR\0"
  /* 2983 */ "G_LSHR\0"
  /* 2990 */ "CONVERGENCECTRL_ANCHOR\0"
  /* 3013 */ "G_FFLOOR\0"
  /* 3022 */ "G_EXTRACT_SUBVECTOR\0"
  /* 3042 */ "G_INSERT_SUBVECTOR\0"
  /* 3061 */ "G_BUILD_VECTOR\0"
  /* 3076 */ "G_SHUFFLE_VECTOR\0"
  /* 3093 */ "G_SPLAT_VECTOR\0"
  /* 3108 */ "G_VECREDUCE_XOR\0"
  /* 3124 */ "G_XOR\0"
  /* 3130 */ "G_ATOMICRMW_XOR\0"
  /* 3146 */ "G_VECREDUCE_OR\0"
  /* 3161 */ "G_OR\0"
  /* 3166 */ "G_ATOMICRMW_OR\0"
  /* 3181 */ "G_ROTR\0"
  /* 3188 */ "G_INTTOPTR\0"
  /* 3199 */ "G_FABS\0"
  /* 3206 */ "G_ABS\0"
  /* 3212 */ "G_UNMERGE_VALUES\0"
  /* 3229 */ "G_MERGE_VALUES\0"
  /* 3244 */ "FMULS\0"
  /* 3250 */ "G_FACOS\0"
  /* 3258 */ "G_FCOS\0"
  /* 3265 */ "G_CONCAT_VECTORS\0"
  /* 3282 */ "COPY_TO_REGCLASS\0"
  /* 3299 */ "G_IS_FPCLASS\0"
  /* 3312 */ "G_ATOMIC_CMPXCHG_WITH_SUCCESS\0"
  /* 3342 */ "G_VECTOR_COMPRESS\0"
  /* 3360 */ "G_INTRINSIC_W_SIDE_EFFECTS\0"
  /* 3387 */ "G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS\0"
  /* 3425 */ "G_SSUBSAT\0"
  /* 3435 */ "G_USUBSAT\0"
  /* 3445 */ "G_SADDSAT\0"
  /* 3455 */ "G_UADDSAT\0"
  /* 3465 */ "G_SSHLSAT\0"
  /* 3475 */ "G_USHLSAT\0"
  /* 3485 */ "G_SMULFIXSAT\0"
  /* 3498 */ "G_UMULFIXSAT\0"
  /* 3511 */ "G_SDIVFIXSAT\0"
  /* 3524 */ "G_UDIVFIXSAT\0"
  /* 3537 */ "G_EXTRACT\0"
  /* 3547 */ "G_SELECT\0"
  /* 3556 */ "G_BRINDIRECT\0"
  /* 3569 */ "PATCHABLE_RET\0"
  /* 3583 */ "G_MEMSET\0"
  /* 3592 */ "PATCHABLE_FUNCTION_EXIT\0"
  /* 3616 */ "G_BRJT\0"
  /* 3623 */ "G_EXTRACT_VECTOR_ELT\0"
  /* 3644 */ "G_INSERT_VECTOR_ELT\0"
  /* 3664 */ "G_FCONSTANT\0"
  /* 3676 */ "G_CONSTANT\0"
  /* 3687 */ "G_INTRINSIC_CONVERGENT\0"
  /* 3710 */ "STATEPOINT\0"
  /* 3721 */ "PATCHPOINT\0"
  /* 3732 */ "G_PTRTOINT\0"
  /* 3743 */ "G_FRINT\0"
  /* 3751 */ "G_INTRINSIC_LLRINT\0"
  /* 3770 */ "G_INTRINSIC_LRINT\0"
  /* 3788 */ "G_FNEARBYINT\0"
  /* 3801 */ "G_VASTART\0"
  /* 3811 */ "LIFETIME_START\0"
  /* 3826 */ "G_INVOKE_REGION_START\0"
  /* 3848 */ "G_INSERT\0"
  /* 3857 */ "G_FSQRT\0"
  /* 3865 */ "G_STRICT_FSQRT\0"
  /* 3880 */ "G_BITCAST\0"
  /* 3890 */ "G_ADDRSPACE_CAST\0"
  /* 3907 */ "BST\0"
  /* 3911 */ "DBG_VALUE_LIST\0"
  /* 3926 */ "G_FPEXT\0"
  /* 3934 */ "G_SEXT\0"
  /* 3941 */ "G_ASSERT_SEXT\0"
  /* 3955 */ "G_ANYEXT\0"
  /* 3964 */ "G_ZEXT\0"
  /* 3971 */ "G_ASSERT_ZEXT\0"
  /* 3985 */ "FMULSU\0"
  /* 3992 */ "G_FDIV\0"
  /* 3999 */ "G_STRICT_FDIV\0"
  /* 4013 */ "G_SDIV\0"
  /* 4020 */ "G_UDIV\0"
  /* 4027 */ "G_GET_FPENV\0"
  /* 4039 */ "G_RESET_FPENV\0"
  /* 4053 */ "G_SET_FPENV\0"
  /* 4065 */ "G_FPOW\0"
  /* 4072 */ "G_VECREDUCE_FMAX\0"
  /* 4089 */ "G_ATOMICRMW_FMAX\0"
  /* 4106 */ "G_VECREDUCE_SMAX\0"
  /* 4123 */ "G_SMAX\0"
  /* 4130 */ "G_VECREDUCE_UMAX\0"
  /* 4147 */ "G_UMAX\0"
  /* 4154 */ "G_ATOMICRMW_UMAX\0"
  /* 4171 */ "G_ATOMICRMW_MAX\0"
  /* 4187 */ "FRMIDX\0"
  /* 4194 */ "G_FRAME_INDEX\0"
  /* 4208 */ "G_SBFX\0"
  /* 4215 */ "G_UBFX\0"
  /* 4222 */ "G_SMULFIX\0"
  /* 4232 */ "G_UMULFIX\0"
  /* 4242 */ "G_SDIVFIX\0"
  /* 4252 */ "G_UDIVFIX\0"
  /* 4262 */ "G_MEMCPY\0"
  /* 4271 */ "COPY\0"
  /* 4276 */ "CONVERGENCECTRL_ENTRY\0"
  /* 4298 */ "G_CTLZ\0"
  /* 4305 */ "G_CTTZ\0"
  /* 4312 */ "ELPMBRdZ\0"
  /* 4321 */ "ELPMRdZ\0"
  /* 4329 */ "ELPMWRdZ\0"
  /* 4338 */ "SBICAb\0"
  /* 4345 */ "CBIAb\0"
  /* 4351 */ "SBIAb\0"
  /* 4357 */ "SBISAb\0"
  /* 4364 */ "LDRdPtrPd\0"
  /* 4374 */ "LDWRdPtrPd\0"
  /* 4385 */ "RORBRd\0"
  /* 4392 */ "DECRd\0"
  /* 4398 */ "INCRd\0"
  /* 4404 */ "NEGRd\0"
  /* 4410 */ "COMRd\0"
  /* 4416 */ "LSLBNRd\0"
  /* 4424 */ "ASRBNRd\0"
  /* 4432 */ "LSRBNRd\0"
  /* 4440 */ "LSLWNRd\0"
  /* 4448 */ "ASRWNRd\0"
  /* 4456 */ "LSRWNRd\0"
  /* 4464 */ "SWAPRd\0"
  /* 4471 */ "POPRd\0"
  /* 4477 */ "RORRd\0"
  /* 4483 */ "ASRRd\0"
  /* 4489 */ "LSRRd\0"
  /* 4495 */ "NEGWRd\0"
  /* 4502 */ "ROLWRd\0"
  /* 4509 */ "LSLWRd\0"
  /* 4516 */ "COMWRd\0"
  /* 4523 */ "POPWRd\0"
  /* 4530 */ "RORWRd\0"
  /* 4537 */ "ASRWRd\0"
  /* 4544 */ "LSRWRd\0"
  /* 4551 */ "LACZRd\0"
  /* 4558 */ "XCHZRd\0"
  /* 4565 */ "LASZRd\0"
  /* 4572 */ "LATZRd\0"
  /* 4579 */ "LSLWHiRd\0"
  /* 4588 */ "ASRWLoRd\0"
  /* 4597 */ "LSRWLoRd\0"
  /* 4606 */ "AtomicFence\0"
  /* 4618 */ "SPMZPi\0"
  /* 4625 */ "ELPMBRdZPi\0"
  /* 4636 */ "ELPMRdZPi\0"
  /* 4646 */ "ELPMWRdZPi\0"
  /* 4657 */ "LDRdPtrPi\0"
  /* 4667 */ "LDWRdPtrPi\0"
  /* 4678 */ "BRGEk\0"
  /* 4684 */ "BRNEk\0"
  /* 4690 */ "BRSHk\0"
  /* 4696 */ "BRMIk\0"
  /* 4702 */ "RCALLk\0"
  /* 4709 */ "BRPLk\0"
  /* 4715 */ "BRLOk\0"
  /* 4721 */ "RJMPk\0"
  /* 4727 */ "BREQk\0"
  /* 4733 */ "BRLTk\0"
  /* 4739 */ "BRBCsk\0"
  /* 4746 */ "BRBSsk\0"
  /* 4753 */ "CopyZero\0"
  /* 4762 */ "OUTARr\0"
  /* 4769 */ "OUTWARr\0"
  /* 4777 */ "PUSHRr\0"
  /* 4784 */ "STSKRr\0"
  /* 4791 */ "STSWKRr\0"
  /* 4799 */ "STDSPQRr\0"
  /* 4808 */ "STDWSPQRr\0"
  /* 4818 */ "STDPtrQRr\0"
  /* 4828 */ "STDWPtrQRr\0"
  /* 4839 */ "PUSHWRr\0"
  /* 4847 */ "STPtrPdRr\0"
  /* 4857 */ "STWPtrPdRr\0"
  /* 4868 */ "SUBRdRr\0"
  /* 4876 */ "SBCRdRr\0"
  /* 4884 */ "ADCRdRr\0"
  /* 4892 */ "CPCRdRr\0"
  /* 4900 */ "ADDRdRr\0"
  /* 4908 */ "ANDRdRr\0"
  /* 4916 */ "MULRdRr\0"
  /* 4924 */ "CPRdRr\0"
  /* 4931 */ "EORRdRr\0"
  /* 4939 */ "MULSRdRr\0"
  /* 4948 */ "MULSURdRr\0"
  /* 4958 */ "MOVRdRr\0"
  /* 4966 */ "SUBWRdRr\0"
  /* 4975 */ "SBCWRdRr\0"
  /* 4984 */ "ADCWRdRr\0"
  /* 4993 */ "CPCWRdRr\0"
  /* 5002 */ "ADDWRdRr\0"
  /* 5011 */ "ANDWRdRr\0"
  /* 5020 */ "CPWRdRr\0"
  /* 5028 */ "EORWRdRr\0"
  /* 5037 */ "MOVWRdRr\0"
  /* 5046 */ "STPtrPiRr\0"
  /* 5056 */ "STWPtrPiRr\0"
  /* 5067 */ "STPtrRr\0"
  /* 5075 */ "STWPtrRr\0"
  /* 5084 */ "LDRdPtr\0"
  /* 5092 */ "LDWRdPtr\0"
  /* 5101 */ "BCLRs\0"
  /* 5107 */ "BSETs\0"
  /* 5113 */ "LDSRdKTiny\0"
  /* 5124 */ "STSKRrTiny\0"
};
#ifdef __GNUC__
#pragma GCC diagnostic pop
#endif

extern const unsigned AVRInstrNameIndices[] = {
    1569U, 2090U, 2807U, 2378U, 1763U, 1744U, 1772U, 1917U, 
    1392U, 1407U, 1358U, 1434U, 3282U, 1204U, 3911U, 1371U, 
    1565U, 1753U, 972U, 4271U, 1094U, 3811U, 821U, 923U, 
    960U, 2489U, 1905U, 3721U, 906U, 2712U, 1497U, 3710U, 
    1117U, 2685U, 2672U, 2872U, 3569U, 3592U, 1837U, 1884U, 
    1857U, 1789U, 1187U, 2837U, 2443U, 4276U, 2990U, 2643U, 
    1252U, 3941U, 3971U, 2221U, 730U, 418U, 2020U, 4013U, 
    4020U, 2047U, 2054U, 2061U, 2071U, 799U, 3161U, 3124U, 
    1356U, 1567U, 4194U, 1214U, 1229U, 1922U, 3537U, 3212U, 
    3848U, 3229U, 3061U, 504U, 3265U, 3732U, 3188U, 3880U, 
    1295U, 2848U, 880U, 478U, 862U, 3770U, 3751U, 2199U, 
    2897U, 2916U, 631U, 575U, 605U, 616U, 556U, 586U, 
    1161U, 1145U, 3312U, 1448U, 1465U, 746U, 424U, 805U, 
    766U, 3166U, 3130U, 4171U, 2347U, 4154U, 2330U, 697U, 
    401U, 4089U, 2265U, 2551U, 2529U, 952U, 1514U, 834U, 
    3556U, 3826U, 456U, 3360U, 3687U, 3387U, 3955U, 496U, 
    3676U, 3664U, 3801U, 1489U, 3934U, 1421U, 3964U, 1816U, 
    2983U, 2969U, 1809U, 2976U, 3181U, 1938U, 2612U, 2605U, 
    2619U, 2626U, 3547U, 2435U, 993U, 2419U, 944U, 2427U, 
    985U, 2411U, 936U, 2473U, 2465U, 1533U, 1525U, 3455U, 
    3445U, 3435U, 3425U, 3475U, 3465U, 4222U, 4232U, 3485U, 
    3498U, 4242U, 4252U, 3511U, 3524U, 655U, 380U, 1962U, 
    348U, 549U, 3992U, 2026U, 4065U, 1596U, 2756U, 53U, 
    9U, 1482U, 45U, 0U, 2731U, 2763U, 1385U, 3926U, 
    468U, 1573U, 1587U, 2587U, 2596U, 3199U, 2236U, 3299U, 
    1304U, 2164U, 2174U, 1042U, 1057U, 2121U, 2153U, 4027U, 
    4053U, 4039U, 1001U, 1029U, 1014U, 736U, 1610U, 2299U, 
    4123U, 2323U, 4147U, 3206U, 853U, 843U, 2802U, 3616U, 
    1072U, 3042U, 3022U, 3644U, 3623U, 3076U, 3093U, 3342U, 
    4305U, 1338U, 4298U, 1320U, 2664U, 2573U, 1174U, 1822U, 
    3258U, 2371U, 2192U, 3250U, 2363U, 2184U, 1557U, 1549U, 
    1541U, 3857U, 3013U, 3743U, 3788U, 3890U, 2820U, 1081U, 
    525U, 1273U, 1130U, 683U, 387U, 1990U, 3999U, 2033U, 
    354U, 3865U, 2740U, 2936U, 2952U, 4262U, 1101U, 1285U, 
    3583U, 2481U, 2522U, 2498U, 2510U, 662U, 1969U, 638U, 
    1945U, 4072U, 2248U, 2132U, 2100U, 714U, 2004U, 783U, 
    3146U, 3108U, 4106U, 2282U, 4130U, 2306U, 4208U, 4215U, 
    4984U, 5002U, 2394U, 2697U, 1719U, 5011U, 4424U, 4588U, 
    4448U, 4537U, 185U, 33U, 330U, 4606U, 77U, 231U, 
    90U, 243U, 106U, 258U, 148U, 296U, 61U, 216U, 
    169U, 315U, 122U, 273U, 4516U, 4993U, 5020U, 4753U, 
    4312U, 4625U, 4329U, 4646U, 5028U, 4187U, 373U, 2791U, 
    2772U, 1711U, 1736U, 5092U, 4374U, 4667U, 4313U, 4330U, 
    4647U, 4416U, 4579U, 4440U, 4509U, 4432U, 4597U, 4456U, 
    4544U, 142U, 27U, 291U, 191U, 39U, 335U, 4495U, 
    1728U, 5029U, 4769U, 4523U, 4839U, 18U, 206U, 4502U, 
    4385U, 4530U, 136U, 286U, 163U, 310U, 1694U, 4975U, 
    3936U, 542U, 1196U, 4799U, 4828U, 4808U, 4791U, 4857U, 
    5056U, 5075U, 1685U, 4966U, 197U, 340U, 3966U, 4884U, 
    4900U, 1703U, 1648U, 4908U, 4483U, 5101U, 762U, 4739U, 
    4746U, 1604U, 4727U, 4678U, 4715U, 4733U, 4696U, 4684U, 
    4709U, 4690U, 5107U, 3907U, 4703U, 4345U, 4410U, 4892U, 
    1656U, 4924U, 1169U, 4392U, 1620U, 1830U, 2633U, 2081U, 
    4321U, 4636U, 4931U, 1957U, 3244U, 3985U, 1831U, 2634U, 
    4398U, 367U, 4722U, 4551U, 4565U, 4572U, 2781U, 1641U, 
    5084U, 4364U, 4657U, 1670U, 5113U, 2082U, 4322U, 4637U, 
    4489U, 4958U, 5037U, 4916U, 4939U, 4948U, 4404U, 2639U, 
    1663U, 4932U, 4762U, 4471U, 4777U, 4702U, 3579U, 1582U, 
    4721U, 4477U, 1633U, 4876U, 4351U, 4338U, 4357U, 1677U, 
    440U, 448U, 2581U, 2086U, 4618U, 4818U, 4847U, 5046U, 
    5067U, 4784U, 5124U, 1625U, 4868U, 4464U, 2833U, 4558U, 
};

static inline void InitAVRMCInstrInfo(MCInstrInfo *II) {
  II->InitMCInstrInfo(AVRDescs.Insts, AVRInstrNameIndices, AVRInstrNameData, nullptr, nullptr, 488);
}

} // end namespace llvm
#endif // GET_INSTRINFO_MC_DESC

#ifdef GET_INSTRINFO_HEADER
#undef GET_INSTRINFO_HEADER
namespace llvm {
struct AVRGenInstrInfo : public TargetInstrInfo { … };
} // end namespace llvm
#endif // GET_INSTRINFO_HEADER

#ifdef GET_INSTRINFO_HELPER_DECLS
#undef GET_INSTRINFO_HELPER_DECLS


#endif // GET_INSTRINFO_HELPER_DECLS

#ifdef GET_INSTRINFO_HELPERS
#undef GET_INSTRINFO_HELPERS

#endif // GET_INSTRINFO_HELPERS

#ifdef GET_INSTRINFO_CTOR_DTOR
#undef GET_INSTRINFO_CTOR_DTOR
namespace llvm {
extern const AVRInstrTable AVRDescs;
extern const unsigned AVRInstrNameIndices[];
extern const char AVRInstrNameData[];
AVRGenInstrInfo::AVRGenInstrInfo(unsigned CFSetupOpcode, unsigned CFDestroyOpcode, unsigned CatchRetOpcode, unsigned ReturnOpcode)
  : TargetInstrInfo(CFSetupOpcode, CFDestroyOpcode, CatchRetOpcode, ReturnOpcode) {
  InitMCInstrInfo(AVRDescs.Insts, AVRInstrNameIndices, AVRInstrNameData, nullptr, nullptr, 488);
}
} // end namespace llvm
#endif // GET_INSTRINFO_CTOR_DTOR

#ifdef GET_INSTRINFO_OPERAND_ENUM
#undef GET_INSTRINFO_OPERAND_ENUM
namespace llvm {
namespace AVR {
namespace OpName {
enum {
  OPERAND_LAST
};
} // end namespace OpName
} // end namespace AVR
} // end namespace llvm
#endif //GET_INSTRINFO_OPERAND_ENUM

#ifdef GET_INSTRINFO_NAMED_OPS
#undef GET_INSTRINFO_NAMED_OPS
namespace llvm {
namespace AVR {
LLVM_READONLY
int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx) {
  return -1;
}
} // end namespace AVR
} // end namespace llvm
#endif //GET_INSTRINFO_NAMED_OPS

#ifdef GET_INSTRINFO_OPERAND_TYPES_ENUM
#undef GET_INSTRINFO_OPERAND_TYPES_ENUM
namespace llvm {
namespace AVR {
namespace OpTypes {
enum OperandType {
  LDDSTDPtrReg = 0,
  LDSTPtrReg = 1,
  brtarget_13 = 2,
  call_target = 3,
  f32imm = 4,
  f64imm = 5,
  i1imm = 6,
  i8imm = 7,
  i16imm = 8,
  i32imm = 9,
  i64imm = 10,
  imm7tiny = 11,
  imm16 = 12,
  imm_arith6 = 13,
  imm_com8 = 14,
  imm_ldi8 = 15,
  imm_port5 = 16,
  imm_port6 = 17,
  memri = 18,
  memspi = 19,
  ptype0 = 20,
  ptype1 = 21,
  ptype2 = 22,
  ptype3 = 23,
  ptype4 = 24,
  ptype5 = 25,
  rcalltarget_13 = 26,
  relbrtarget_7 = 27,
  type0 = 28,
  type1 = 29,
  type2 = 30,
  type3 = 31,
  type4 = 32,
  type5 = 33,
  untyped_imm_0 = 34,
  CCR = 35,
  DLDREGS = 36,
  DREGS = 37,
  DREGSLD8lo = 38,
  DREGSMOVW = 39,
  DREGSlo = 40,
  GPR8 = 41,
  GPR8lo = 42,
  GPRSP = 43,
  IWREGS = 44,
  LD8 = 45,
  LD8lo = 46,
  PTRDISPREGS = 47,
  PTRREGS = 48,
  ZREG = 49,
  OPERAND_TYPE_LIST_END
};
} // end namespace OpTypes
} // end namespace AVR
} // end namespace llvm
#endif // GET_INSTRINFO_OPERAND_TYPES_ENUM

#ifdef GET_INSTRINFO_OPERAND_TYPE
#undef GET_INSTRINFO_OPERAND_TYPE
namespace llvm {
namespace AVR {
LLVM_READONLY
static int getOperandType(uint16_t Opcode, uint16_t OpIdx) {
  static const uint16_t Offsets[] = {
    /* PHI */
    0,
    /* INLINEASM */
    1,
    /* INLINEASM_BR */
    1,
    /* CFI_INSTRUCTION */
    1,
    /* EH_LABEL */
    2,
    /* GC_LABEL */
    3,
    /* ANNOTATION_LABEL */
    4,
    /* KILL */
    5,
    /* EXTRACT_SUBREG */
    5,
    /* INSERT_SUBREG */
    8,
    /* IMPLICIT_DEF */
    12,
    /* SUBREG_TO_REG */
    13,
    /* COPY_TO_REGCLASS */
    17,
    /* DBG_VALUE */
    20,
    /* DBG_VALUE_LIST */
    20,
    /* DBG_INSTR_REF */
    20,
    /* DBG_PHI */
    20,
    /* DBG_LABEL */
    20,
    /* REG_SEQUENCE */
    21,
    /* COPY */
    23,
    /* BUNDLE */
    25,
    /* LIFETIME_START */
    25,
    /* LIFETIME_END */
    26,
    /* PSEUDO_PROBE */
    27,
    /* ARITH_FENCE */
    31,
    /* STACKMAP */
    33,
    /* FENTRY_CALL */
    35,
    /* PATCHPOINT */
    35,
    /* LOAD_STACK_GUARD */
    41,
    /* PREALLOCATED_SETUP */
    42,
    /* PREALLOCATED_ARG */
    43,
    /* STATEPOINT */
    46,
    /* LOCAL_ESCAPE */
    46,
    /* FAULTING_OP */
    48,
    /* PATCHABLE_OP */
    49,
    /* PATCHABLE_FUNCTION_ENTER */
    49,
    /* PATCHABLE_RET */
    49,
    /* PATCHABLE_FUNCTION_EXIT */
    49,
    /* PATCHABLE_TAIL_CALL */
    49,
    /* PATCHABLE_EVENT_CALL */
    49,
    /* PATCHABLE_TYPED_EVENT_CALL */
    51,
    /* ICALL_BRANCH_FUNNEL */
    54,
    /* FAKE_USE */
    54,
    /* MEMBARRIER */
    54,
    /* JUMP_TABLE_DEBUG_INFO */
    54,
    /* CONVERGENCECTRL_ENTRY */
    55,
    /* CONVERGENCECTRL_ANCHOR */
    56,
    /* CONVERGENCECTRL_LOOP */
    57,
    /* CONVERGENCECTRL_GLUE */
    59,
    /* G_ASSERT_SEXT */
    60,
    /* G_ASSERT_ZEXT */
    63,
    /* G_ASSERT_ALIGN */
    66,
    /* G_ADD */
    69,
    /* G_SUB */
    72,
    /* G_MUL */
    75,
    /* G_SDIV */
    78,
    /* G_UDIV */
    81,
    /* G_SREM */
    84,
    /* G_UREM */
    87,
    /* G_SDIVREM */
    90,
    /* G_UDIVREM */
    94,
    /* G_AND */
    98,
    /* G_OR */
    101,
    /* G_XOR */
    104,
    /* G_IMPLICIT_DEF */
    107,
    /* G_PHI */
    108,
    /* G_FRAME_INDEX */
    109,
    /* G_GLOBAL_VALUE */
    111,
    /* G_PTRAUTH_GLOBAL_VALUE */
    113,
    /* G_CONSTANT_POOL */
    118,
    /* G_EXTRACT */
    120,
    /* G_UNMERGE_VALUES */
    123,
    /* G_INSERT */
    125,
    /* G_MERGE_VALUES */
    129,
    /* G_BUILD_VECTOR */
    131,
    /* G_BUILD_VECTOR_TRUNC */
    133,
    /* G_CONCAT_VECTORS */
    135,
    /* G_PTRTOINT */
    137,
    /* G_INTTOPTR */
    139,
    /* G_BITCAST */
    141,
    /* G_FREEZE */
    143,
    /* G_CONSTANT_FOLD_BARRIER */
    145,
    /* G_INTRINSIC_FPTRUNC_ROUND */
    147,
    /* G_INTRINSIC_TRUNC */
    150,
    /* G_INTRINSIC_ROUND */
    152,
    /* G_INTRINSIC_LRINT */
    154,
    /* G_INTRINSIC_LLRINT */
    156,
    /* G_INTRINSIC_ROUNDEVEN */
    158,
    /* G_READCYCLECOUNTER */
    160,
    /* G_READSTEADYCOUNTER */
    161,
    /* G_LOAD */
    162,
    /* G_SEXTLOAD */
    164,
    /* G_ZEXTLOAD */
    166,
    /* G_INDEXED_LOAD */
    168,
    /* G_INDEXED_SEXTLOAD */
    173,
    /* G_INDEXED_ZEXTLOAD */
    178,
    /* G_STORE */
    183,
    /* G_INDEXED_STORE */
    185,
    /* G_ATOMIC_CMPXCHG_WITH_SUCCESS */
    190,
    /* G_ATOMIC_CMPXCHG */
    195,
    /* G_ATOMICRMW_XCHG */
    199,
    /* G_ATOMICRMW_ADD */
    202,
    /* G_ATOMICRMW_SUB */
    205,
    /* G_ATOMICRMW_AND */
    208,
    /* G_ATOMICRMW_NAND */
    211,
    /* G_ATOMICRMW_OR */
    214,
    /* G_ATOMICRMW_XOR */
    217,
    /* G_ATOMICRMW_MAX */
    220,
    /* G_ATOMICRMW_MIN */
    223,
    /* G_ATOMICRMW_UMAX */
    226,
    /* G_ATOMICRMW_UMIN */
    229,
    /* G_ATOMICRMW_FADD */
    232,
    /* G_ATOMICRMW_FSUB */
    235,
    /* G_ATOMICRMW_FMAX */
    238,
    /* G_ATOMICRMW_FMIN */
    241,
    /* G_ATOMICRMW_UINC_WRAP */
    244,
    /* G_ATOMICRMW_UDEC_WRAP */
    247,
    /* G_FENCE */
    250,
    /* G_PREFETCH */
    252,
    /* G_BRCOND */
    256,
    /* G_BRINDIRECT */
    258,
    /* G_INVOKE_REGION_START */
    259,
    /* G_INTRINSIC */
    259,
    /* G_INTRINSIC_W_SIDE_EFFECTS */
    260,
    /* G_INTRINSIC_CONVERGENT */
    261,
    /* G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS */
    262,
    /* G_ANYEXT */
    263,
    /* G_TRUNC */
    265,
    /* G_CONSTANT */
    267,
    /* G_FCONSTANT */
    269,
    /* G_VASTART */
    271,
    /* G_VAARG */
    272,
    /* G_SEXT */
    275,
    /* G_SEXT_INREG */
    277,
    /* G_ZEXT */
    280,
    /* G_SHL */
    282,
    /* G_LSHR */
    285,
    /* G_ASHR */
    288,
    /* G_FSHL */
    291,
    /* G_FSHR */
    295,
    /* G_ROTR */
    299,
    /* G_ROTL */
    302,
    /* G_ICMP */
    305,
    /* G_FCMP */
    309,
    /* G_SCMP */
    313,
    /* G_UCMP */
    316,
    /* G_SELECT */
    319,
    /* G_UADDO */
    323,
    /* G_UADDE */
    327,
    /* G_USUBO */
    332,
    /* G_USUBE */
    336,
    /* G_SADDO */
    341,
    /* G_SADDE */
    345,
    /* G_SSUBO */
    350,
    /* G_SSUBE */
    354,
    /* G_UMULO */
    359,
    /* G_SMULO */
    363,
    /* G_UMULH */
    367,
    /* G_SMULH */
    370,
    /* G_UADDSAT */
    373,
    /* G_SADDSAT */
    376,
    /* G_USUBSAT */
    379,
    /* G_SSUBSAT */
    382,
    /* G_USHLSAT */
    385,
    /* G_SSHLSAT */
    388,
    /* G_SMULFIX */
    391,
    /* G_UMULFIX */
    395,
    /* G_SMULFIXSAT */
    399,
    /* G_UMULFIXSAT */
    403,
    /* G_SDIVFIX */
    407,
    /* G_UDIVFIX */
    411,
    /* G_SDIVFIXSAT */
    415,
    /* G_UDIVFIXSAT */
    419,
    /* G_FADD */
    423,
    /* G_FSUB */
    426,
    /* G_FMUL */
    429,
    /* G_FMA */
    432,
    /* G_FMAD */
    436,
    /* G_FDIV */
    440,
    /* G_FREM */
    443,
    /* G_FPOW */
    446,
    /* G_FPOWI */
    449,
    /* G_FEXP */
    452,
    /* G_FEXP2 */
    454,
    /* G_FEXP10 */
    456,
    /* G_FLOG */
    458,
    /* G_FLOG2 */
    460,
    /* G_FLOG10 */
    462,
    /* G_FLDEXP */
    464,
    /* G_FFREXP */
    467,
    /* G_FNEG */
    470,
    /* G_FPEXT */
    472,
    /* G_FPTRUNC */
    474,
    /* G_FPTOSI */
    476,
    /* G_FPTOUI */
    478,
    /* G_SITOFP */
    480,
    /* G_UITOFP */
    482,
    /* G_FABS */
    484,
    /* G_FCOPYSIGN */
    486,
    /* G_IS_FPCLASS */
    489,
    /* G_FCANONICALIZE */
    492,
    /* G_FMINNUM */
    494,
    /* G_FMAXNUM */
    497,
    /* G_FMINNUM_IEEE */
    500,
    /* G_FMAXNUM_IEEE */
    503,
    /* G_FMINIMUM */
    506,
    /* G_FMAXIMUM */
    509,
    /* G_GET_FPENV */
    512,
    /* G_SET_FPENV */
    513,
    /* G_RESET_FPENV */
    514,
    /* G_GET_FPMODE */
    514,
    /* G_SET_FPMODE */
    515,
    /* G_RESET_FPMODE */
    516,
    /* G_PTR_ADD */
    516,
    /* G_PTRMASK */
    519,
    /* G_SMIN */
    522,
    /* G_SMAX */
    525,
    /* G_UMIN */
    528,
    /* G_UMAX */
    531,
    /* G_ABS */
    534,
    /* G_LROUND */
    536,
    /* G_LLROUND */
    538,
    /* G_BR */
    540,
    /* G_BRJT */
    541,
    /* G_VSCALE */
    544,
    /* G_INSERT_SUBVECTOR */
    546,
    /* G_EXTRACT_SUBVECTOR */
    550,
    /* G_INSERT_VECTOR_ELT */
    553,
    /* G_EXTRACT_VECTOR_ELT */
    557,
    /* G_SHUFFLE_VECTOR */
    560,
    /* G_SPLAT_VECTOR */
    564,
    /* G_VECTOR_COMPRESS */
    566,
    /* G_CTTZ */
    570,
    /* G_CTTZ_ZERO_UNDEF */
    572,
    /* G_CTLZ */
    574,
    /* G_CTLZ_ZERO_UNDEF */
    576,
    /* G_CTPOP */
    578,
    /* G_BSWAP */
    580,
    /* G_BITREVERSE */
    582,
    /* G_FCEIL */
    584,
    /* G_FCOS */
    586,
    /* G_FSIN */
    588,
    /* G_FTAN */
    590,
    /* G_FACOS */
    592,
    /* G_FASIN */
    594,
    /* G_FATAN */
    596,
    /* G_FCOSH */
    598,
    /* G_FSINH */
    600,
    /* G_FTANH */
    602,
    /* G_FSQRT */
    604,
    /* G_FFLOOR */
    606,
    /* G_FRINT */
    608,
    /* G_FNEARBYINT */
    610,
    /* G_ADDRSPACE_CAST */
    612,
    /* G_BLOCK_ADDR */
    614,
    /* G_JUMP_TABLE */
    616,
    /* G_DYN_STACKALLOC */
    618,
    /* G_STACKSAVE */
    621,
    /* G_STACKRESTORE */
    622,
    /* G_STRICT_FADD */
    623,
    /* G_STRICT_FSUB */
    626,
    /* G_STRICT_FMUL */
    629,
    /* G_STRICT_FDIV */
    632,
    /* G_STRICT_FREM */
    635,
    /* G_STRICT_FMA */
    638,
    /* G_STRICT_FSQRT */
    642,
    /* G_STRICT_FLDEXP */
    644,
    /* G_READ_REGISTER */
    647,
    /* G_WRITE_REGISTER */
    649,
    /* G_MEMCPY */
    651,
    /* G_MEMCPY_INLINE */
    655,
    /* G_MEMMOVE */
    658,
    /* G_MEMSET */
    662,
    /* G_BZERO */
    666,
    /* G_TRAP */
    669,
    /* G_DEBUGTRAP */
    669,
    /* G_UBSANTRAP */
    669,
    /* G_VECREDUCE_SEQ_FADD */
    670,
    /* G_VECREDUCE_SEQ_FMUL */
    673,
    /* G_VECREDUCE_FADD */
    676,
    /* G_VECREDUCE_FMUL */
    678,
    /* G_VECREDUCE_FMAX */
    680,
    /* G_VECREDUCE_FMIN */
    682,
    /* G_VECREDUCE_FMAXIMUM */
    684,
    /* G_VECREDUCE_FMINIMUM */
    686,
    /* G_VECREDUCE_ADD */
    688,
    /* G_VECREDUCE_MUL */
    690,
    /* G_VECREDUCE_AND */
    692,
    /* G_VECREDUCE_OR */
    694,
    /* G_VECREDUCE_XOR */
    696,
    /* G_VECREDUCE_SMAX */
    698,
    /* G_VECREDUCE_SMIN */
    700,
    /* G_VECREDUCE_UMAX */
    702,
    /* G_VECREDUCE_UMIN */
    704,
    /* G_SBFX */
    706,
    /* G_UBFX */
    710,
    /* ADCWRdRr */
    714,
    /* ADDWRdRr */
    717,
    /* ADJCALLSTACKDOWN */
    720,
    /* ADJCALLSTACKUP */
    722,
    /* ANDIWRdK */
    724,
    /* ANDWRdRr */
    727,
    /* ASRBNRd */
    730,
    /* ASRWLoRd */
    733,
    /* ASRWNRd */
    735,
    /* ASRWRd */
    738,
    /* Asr16 */
    740,
    /* Asr32 */
    743,
    /* Asr8 */
    748,
    /* AtomicFence */
    751,
    /* AtomicLoad16 */
    751,
    /* AtomicLoad8 */
    753,
    /* AtomicLoadAdd16 */
    755,
    /* AtomicLoadAdd8 */
    758,
    /* AtomicLoadAnd16 */
    761,
    /* AtomicLoadAnd8 */
    764,
    /* AtomicLoadOr16 */
    767,
    /* AtomicLoadOr8 */
    770,
    /* AtomicLoadSub16 */
    773,
    /* AtomicLoadSub8 */
    776,
    /* AtomicLoadXor16 */
    779,
    /* AtomicLoadXor8 */
    782,
    /* AtomicStore16 */
    785,
    /* AtomicStore8 */
    787,
    /* COMWRd */
    789,
    /* CPCWRdRr */
    791,
    /* CPWRdRr */
    793,
    /* CopyZero */
    795,
    /* ELPMBRdZ */
    796,
    /* ELPMBRdZPi */
    799,
    /* ELPMWRdZ */
    802,
    /* ELPMWRdZPi */
    805,
    /* EORWRdRr */
    808,
    /* FRMIDX */
    811,
    /* INWRdA */
    814,
    /* LDDWRdPtrQ */
    816,
    /* LDDWRdYQ */
    819,
    /* LDIWRdK */
    822,
    /* LDSWRdK */
    824,
    /* LDWRdPtr */
    826,
    /* LDWRdPtrPd */
    828,
    /* LDWRdPtrPi */
    831,
    /* LPMBRdZ */
    834,
    /* LPMWRdZ */
    836,
    /* LPMWRdZPi */
    838,
    /* LSLBNRd */
    840,
    /* LSLWHiRd */
    843,
    /* LSLWNRd */
    845,
    /* LSLWRd */
    848,
    /* LSRBNRd */
    850,
    /* LSRWLoRd */
    853,
    /* LSRWNRd */
    855,
    /* LSRWRd */
    858,
    /* Lsl16 */
    860,
    /* Lsl32 */
    863,
    /* Lsl8 */
    868,
    /* Lsr16 */
    871,
    /* Lsr32 */
    874,
    /* Lsr8 */
    879,
    /* NEGWRd */
    882,
    /* ORIWRdK */
    885,
    /* ORWRdRr */
    888,
    /* OUTWARr */
    891,
    /* POPWRd */
    893,
    /* PUSHWRr */
    894,
    /* ROLBRdR1 */
    895,
    /* ROLBRdR17 */
    897,
    /* ROLWRd */
    899,
    /* RORBRd */
    901,
    /* RORWRd */
    903,
    /* Rol16 */
    905,
    /* Rol8 */
    908,
    /* Ror16 */
    911,
    /* Ror8 */
    914,
    /* SBCIWRdK */
    917,
    /* SBCWRdRr */
    920,
    /* SEXT */
    923,
    /* SPREAD */
    925,
    /* SPWRITE */
    927,
    /* STDSPQRr */
    929,
    /* STDWPtrQRr */
    932,
    /* STDWSPQRr */
    935,
    /* STSWKRr */
    938,
    /* STWPtrPdRr */
    940,
    /* STWPtrPiRr */
    944,
    /* STWPtrRr */
    948,
    /* SUBIWRdK */
    950,
    /* SUBWRdRr */
    953,
    /* Select16 */
    956,
    /* Select8 */
    960,
    /* ZEXT */
    964,
    /* ADCRdRr */
    966,
    /* ADDRdRr */
    969,
    /* ADIWRdK */
    972,
    /* ANDIRdK */
    975,
    /* ANDRdRr */
    978,
    /* ASRRd */
    981,
    /* BCLRs */
    983,
    /* BLD */
    984,
    /* BRBCsk */
    987,
    /* BRBSsk */
    989,
    /* BREAK */
    991,
    /* BREQk */
    991,
    /* BRGEk */
    992,
    /* BRLOk */
    993,
    /* BRLTk */
    994,
    /* BRMIk */
    995,
    /* BRNEk */
    996,
    /* BRPLk */
    997,
    /* BRSHk */
    998,
    /* BSETs */
    999,
    /* BST */
    1000,
    /* CALLk */
    1002,
    /* CBIAb */
    1003,
    /* COMRd */
    1005,
    /* CPCRdRr */
    1007,
    /* CPIRdK */
    1009,
    /* CPRdRr */
    1011,
    /* CPSE */
    1013,
    /* DECRd */
    1015,
    /* DESK */
    1017,
    /* EICALL */
    1018,
    /* EIJMP */
    1018,
    /* ELPM */
    1018,
    /* ELPMRdZ */
    1018,
    /* ELPMRdZPi */
    1020,
    /* EORRdRr */
    1022,
    /* FMUL */
    1025,
    /* FMULS */
    1027,
    /* FMULSU */
    1029,
    /* ICALL */
    1031,
    /* IJMP */
    1031,
    /* INCRd */
    1031,
    /* INRdA */
    1033,
    /* JMPk */
    1035,
    /* LACZRd */
    1036,
    /* LASZRd */
    1038,
    /* LATZRd */
    1040,
    /* LDDRdPtrQ */
    1042,
    /* LDIRdK */
    1045,
    /* LDRdPtr */
    1047,
    /* LDRdPtrPd */
    1049,
    /* LDRdPtrPi */
    1052,
    /* LDSRdK */
    1055,
    /* LDSRdKTiny */
    1057,
    /* LPM */
    1059,
    /* LPMRdZ */
    1059,
    /* LPMRdZPi */
    1061,
    /* LSRRd */
    1063,
    /* MOVRdRr */
    1065,
    /* MOVWRdRr */
    1067,
    /* MULRdRr */
    1069,
    /* MULSRdRr */
    1071,
    /* MULSURdRr */
    1073,
    /* NEGRd */
    1075,
    /* NOP */
    1077,
    /* ORIRdK */
    1077,
    /* ORRdRr */
    1080,
    /* OUTARr */
    1083,
    /* POPRd */
    1085,
    /* PUSHRr */
    1086,
    /* RCALLk */
    1087,
    /* RET */
    1088,
    /* RETI */
    1088,
    /* RJMPk */
    1088,
    /* RORRd */
    1089,
    /* SBCIRdK */
    1091,
    /* SBCRdRr */
    1094,
    /* SBIAb */
    1097,
    /* SBICAb */
    1099,
    /* SBISAb */
    1101,
    /* SBIWRdK */
    1103,
    /* SBRCRrB */
    1106,
    /* SBRSRrB */
    1108,
    /* SLEEP */
    1110,
    /* SPM */
    1110,
    /* SPMZPi */
    1110,
    /* STDPtrQRr */
    1111,
    /* STPtrPdRr */
    1114,
    /* STPtrPiRr */
    1118,
    /* STPtrRr */
    1122,
    /* STSKRr */
    1124,
    /* STSKRrTiny */
    1126,
    /* SUBIRdK */
    1128,
    /* SUBRdRr */
    1131,
    /* SWAPRd */
    1134,
    /* WDR */
    1136,
    /* XCHZRd */
    1136,
  };

  using namespace OpTypes;
  static const int8_t OpcodeOperandTypes[] = {
    
    /* PHI */
    -1, 
    /* INLINEASM */
    /* INLINEASM_BR */
    /* CFI_INSTRUCTION */
    i32imm, 
    /* EH_LABEL */
    i32imm, 
    /* GC_LABEL */
    i32imm, 
    /* ANNOTATION_LABEL */
    i32imm, 
    /* KILL */
    /* EXTRACT_SUBREG */
    -1, -1, i32imm, 
    /* INSERT_SUBREG */
    -1, -1, -1, i32imm, 
    /* IMPLICIT_DEF */
    -1, 
    /* SUBREG_TO_REG */
    -1, -1, -1, i32imm, 
    /* COPY_TO_REGCLASS */
    -1, -1, i32imm, 
    /* DBG_VALUE */
    /* DBG_VALUE_LIST */
    /* DBG_INSTR_REF */
    /* DBG_PHI */
    /* DBG_LABEL */
    -1, 
    /* REG_SEQUENCE */
    -1, -1, 
    /* COPY */
    -1, -1, 
    /* BUNDLE */
    /* LIFETIME_START */
    i32imm, 
    /* LIFETIME_END */
    i32imm, 
    /* PSEUDO_PROBE */
    i64imm, i64imm, i8imm, i32imm, 
    /* ARITH_FENCE */
    -1, -1, 
    /* STACKMAP */
    i64imm, i32imm, 
    /* FENTRY_CALL */
    /* PATCHPOINT */
    -1, i64imm, i32imm, -1, i32imm, i32imm, 
    /* LOAD_STACK_GUARD */
    -1, 
    /* PREALLOCATED_SETUP */
    i32imm, 
    /* PREALLOCATED_ARG */
    -1, i32imm, i32imm, 
    /* STATEPOINT */
    /* LOCAL_ESCAPE */
    -1, i32imm, 
    /* FAULTING_OP */
    -1, 
    /* PATCHABLE_OP */
    /* PATCHABLE_FUNCTION_ENTER */
    /* PATCHABLE_RET */
    /* PATCHABLE_FUNCTION_EXIT */
    /* PATCHABLE_TAIL_CALL */
    /* PATCHABLE_EVENT_CALL */
    -1, -1, 
    /* PATCHABLE_TYPED_EVENT_CALL */
    -1, -1, -1, 
    /* ICALL_BRANCH_FUNNEL */
    /* FAKE_USE */
    /* MEMBARRIER */
    /* JUMP_TABLE_DEBUG_INFO */
    i64imm, 
    /* CONVERGENCECTRL_ENTRY */
    -1, 
    /* CONVERGENCECTRL_ANCHOR */
    -1, 
    /* CONVERGENCECTRL_LOOP */
    -1, -1, 
    /* CONVERGENCECTRL_GLUE */
    -1, 
    /* G_ASSERT_SEXT */
    type0, type0, untyped_imm_0, 
    /* G_ASSERT_ZEXT */
    type0, type0, untyped_imm_0, 
    /* G_ASSERT_ALIGN */
    type0, type0, untyped_imm_0, 
    /* G_ADD */
    type0, type0, type0, 
    /* G_SUB */
    type0, type0, type0, 
    /* G_MUL */
    type0, type0, type0, 
    /* G_SDIV */
    type0, type0, type0, 
    /* G_UDIV */
    type0, type0, type0, 
    /* G_SREM */
    type0, type0, type0, 
    /* G_UREM */
    type0, type0, type0, 
    /* G_SDIVREM */
    type0, type0, type0, type0, 
    /* G_UDIVREM */
    type0, type0, type0, type0, 
    /* G_AND */
    type0, type0, type0, 
    /* G_OR */
    type0, type0, type0, 
    /* G_XOR */
    type0, type0, type0, 
    /* G_IMPLICIT_DEF */
    type0, 
    /* G_PHI */
    type0, 
    /* G_FRAME_INDEX */
    type0, -1, 
    /* G_GLOBAL_VALUE */
    type0, -1, 
    /* G_PTRAUTH_GLOBAL_VALUE */
    type0, -1, i32imm, type1, i64imm, 
    /* G_CONSTANT_POOL */
    type0, -1, 
    /* G_EXTRACT */
    type0, type1, untyped_imm_0, 
    /* G_UNMERGE_VALUES */
    type0, type1, 
    /* G_INSERT */
    type0, type0, type1, untyped_imm_0, 
    /* G_MERGE_VALUES */
    type0, type1, 
    /* G_BUILD_VECTOR */
    type0, type1, 
    /* G_BUILD_VECTOR_TRUNC */
    type0, type1, 
    /* G_CONCAT_VECTORS */
    type0, type1, 
    /* G_PTRTOINT */
    type0, type1, 
    /* G_INTTOPTR */
    type0, type1, 
    /* G_BITCAST */
    type0, type1, 
    /* G_FREEZE */
    type0, type0, 
    /* G_CONSTANT_FOLD_BARRIER */
    type0, type0, 
    /* G_INTRINSIC_FPTRUNC_ROUND */
    type0, type1, i32imm, 
    /* G_INTRINSIC_TRUNC */
    type0, type0, 
    /* G_INTRINSIC_ROUND */
    type0, type0, 
    /* G_INTRINSIC_LRINT */
    type0, type1, 
    /* G_INTRINSIC_LLRINT */
    type0, type1, 
    /* G_INTRINSIC_ROUNDEVEN */
    type0, type0, 
    /* G_READCYCLECOUNTER */
    type0, 
    /* G_READSTEADYCOUNTER */
    type0, 
    /* G_LOAD */
    type0, ptype1, 
    /* G_SEXTLOAD */
    type0, ptype1, 
    /* G_ZEXTLOAD */
    type0, ptype1, 
    /* G_INDEXED_LOAD */
    type0, ptype1, ptype1, type2, -1, 
    /* G_INDEXED_SEXTLOAD */
    type0, ptype1, ptype1, type2, -1, 
    /* G_INDEXED_ZEXTLOAD */
    type0, ptype1, ptype1, type2, -1, 
    /* G_STORE */
    type0, ptype1, 
    /* G_INDEXED_STORE */
    ptype0, type1, ptype0, ptype2, -1, 
    /* G_ATOMIC_CMPXCHG_WITH_SUCCESS */
    type0, type1, type2, type0, type0, 
    /* G_ATOMIC_CMPXCHG */
    type0, ptype1, type0, type0, 
    /* G_ATOMICRMW_XCHG */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_ADD */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_SUB */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_AND */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_NAND */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_OR */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_XOR */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_MAX */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_MIN */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_UMAX */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_UMIN */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_FADD */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_FSUB */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_FMAX */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_FMIN */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_UINC_WRAP */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_UDEC_WRAP */
    type0, ptype1, type0, 
    /* G_FENCE */
    i32imm, i32imm, 
    /* G_PREFETCH */
    ptype0, i32imm, i32imm, i32imm, 
    /* G_BRCOND */
    type0, -1, 
    /* G_BRINDIRECT */
    type0, 
    /* G_INVOKE_REGION_START */
    /* G_INTRINSIC */
    -1, 
    /* G_INTRINSIC_W_SIDE_EFFECTS */
    -1, 
    /* G_INTRINSIC_CONVERGENT */
    -1, 
    /* G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS */
    -1, 
    /* G_ANYEXT */
    type0, type1, 
    /* G_TRUNC */
    type0, type1, 
    /* G_CONSTANT */
    type0, -1, 
    /* G_FCONSTANT */
    type0, -1, 
    /* G_VASTART */
    type0, 
    /* G_VAARG */
    type0, type1, -1, 
    /* G_SEXT */
    type0, type1, 
    /* G_SEXT_INREG */
    type0, type0, untyped_imm_0, 
    /* G_ZEXT */
    type0, type1, 
    /* G_SHL */
    type0, type0, type1, 
    /* G_LSHR */
    type0, type0, type1, 
    /* G_ASHR */
    type0, type0, type1, 
    /* G_FSHL */
    type0, type0, type0, type1, 
    /* G_FSHR */
    type0, type0, type0, type1, 
    /* G_ROTR */
    type0, type0, type1, 
    /* G_ROTL */
    type0, type0, type1, 
    /* G_ICMP */
    type0, -1, type1, type1, 
    /* G_FCMP */
    type0, -1, type1, type1, 
    /* G_SCMP */
    type0, type1, type1, 
    /* G_UCMP */
    type0, type1, type1, 
    /* G_SELECT */
    type0, type1, type0, type0, 
    /* G_UADDO */
    type0, type1, type0, type0, 
    /* G_UADDE */
    type0, type1, type0, type0, type1, 
    /* G_USUBO */
    type0, type1, type0, type0, 
    /* G_USUBE */
    type0, type1, type0, type0, type1, 
    /* G_SADDO */
    type0, type1, type0, type0, 
    /* G_SADDE */
    type0, type1, type0, type0, type1, 
    /* G_SSUBO */
    type0, type1, type0, type0, 
    /* G_SSUBE */
    type0, type1, type0, type0, type1, 
    /* G_UMULO */
    type0, type1, type0, type0, 
    /* G_SMULO */
    type0, type1, type0, type0, 
    /* G_UMULH */
    type0, type0, type0, 
    /* G_SMULH */
    type0, type0, type0, 
    /* G_UADDSAT */
    type0, type0, type0, 
    /* G_SADDSAT */
    type0, type0, type0, 
    /* G_USUBSAT */
    type0, type0, type0, 
    /* G_SSUBSAT */
    type0, type0, type0, 
    /* G_USHLSAT */
    type0, type0, type1, 
    /* G_SSHLSAT */
    type0, type0, type1, 
    /* G_SMULFIX */
    type0, type0, type0, untyped_imm_0, 
    /* G_UMULFIX */
    type0, type0, type0, untyped_imm_0, 
    /* G_SMULFIXSAT */
    type0, type0, type0, untyped_imm_0, 
    /* G_UMULFIXSAT */
    type0, type0, type0, untyped_imm_0, 
    /* G_SDIVFIX */
    type0, type0, type0, untyped_imm_0, 
    /* G_UDIVFIX */
    type0, type0, type0, untyped_imm_0, 
    /* G_SDIVFIXSAT */
    type0, type0, type0, untyped_imm_0, 
    /* G_UDIVFIXSAT */
    type0, type0, type0, untyped_imm_0, 
    /* G_FADD */
    type0, type0, type0, 
    /* G_FSUB */
    type0, type0, type0, 
    /* G_FMUL */
    type0, type0, type0, 
    /* G_FMA */
    type0, type0, type0, type0, 
    /* G_FMAD */
    type0, type0, type0, type0, 
    /* G_FDIV */
    type0, type0, type0, 
    /* G_FREM */
    type0, type0, type0, 
    /* G_FPOW */
    type0, type0, type0, 
    /* G_FPOWI */
    type0, type0, type1, 
    /* G_FEXP */
    type0, type0, 
    /* G_FEXP2 */
    type0, type0, 
    /* G_FEXP10 */
    type0, type0, 
    /* G_FLOG */
    type0, type0, 
    /* G_FLOG2 */
    type0, type0, 
    /* G_FLOG10 */
    type0, type0, 
    /* G_FLDEXP */
    type0, type0, type1, 
    /* G_FFREXP */
    type0, type1, type0, 
    /* G_FNEG */
    type0, type0, 
    /* G_FPEXT */
    type0, type1, 
    /* G_FPTRUNC */
    type0, type1, 
    /* G_FPTOSI */
    type0, type1, 
    /* G_FPTOUI */
    type0, type1, 
    /* G_SITOFP */
    type0, type1, 
    /* G_UITOFP */
    type0, type1, 
    /* G_FABS */
    type0, type0, 
    /* G_FCOPYSIGN */
    type0, type0, type1, 
    /* G_IS_FPCLASS */
    type0, type1, -1, 
    /* G_FCANONICALIZE */
    type0, type0, 
    /* G_FMINNUM */
    type0, type0, type0, 
    /* G_FMAXNUM */
    type0, type0, type0, 
    /* G_FMINNUM_IEEE */
    type0, type0, type0, 
    /* G_FMAXNUM_IEEE */
    type0, type0, type0, 
    /* G_FMINIMUM */
    type0, type0, type0, 
    /* G_FMAXIMUM */
    type0, type0, type0, 
    /* G_GET_FPENV */
    type0, 
    /* G_SET_FPENV */
    type0, 
    /* G_RESET_FPENV */
    /* G_GET_FPMODE */
    type0, 
    /* G_SET_FPMODE */
    type0, 
    /* G_RESET_FPMODE */
    /* G_PTR_ADD */
    ptype0, ptype0, type1, 
    /* G_PTRMASK */
    ptype0, ptype0, type1, 
    /* G_SMIN */
    type0, type0, type0, 
    /* G_SMAX */
    type0, type0, type0, 
    /* G_UMIN */
    type0, type0, type0, 
    /* G_UMAX */
    type0, type0, type0, 
    /* G_ABS */
    type0, type0, 
    /* G_LROUND */
    type0, type1, 
    /* G_LLROUND */
    type0, type1, 
    /* G_BR */
    -1, 
    /* G_BRJT */
    ptype0, -1, type1, 
    /* G_VSCALE */
    type0, -1, 
    /* G_INSERT_SUBVECTOR */
    type0, type0, type1, untyped_imm_0, 
    /* G_EXTRACT_SUBVECTOR */
    type0, type0, untyped_imm_0, 
    /* G_INSERT_VECTOR_ELT */
    type0, type0, type1, type2, 
    /* G_EXTRACT_VECTOR_ELT */
    type0, type1, type2, 
    /* G_SHUFFLE_VECTOR */
    type0, type1, type1, -1, 
    /* G_SPLAT_VECTOR */
    type0, type1, 
    /* G_VECTOR_COMPRESS */
    type0, type0, type1, type0, 
    /* G_CTTZ */
    type0, type1, 
    /* G_CTTZ_ZERO_UNDEF */
    type0, type1, 
    /* G_CTLZ */
    type0, type1, 
    /* G_CTLZ_ZERO_UNDEF */
    type0, type1, 
    /* G_CTPOP */
    type0, type1, 
    /* G_BSWAP */
    type0, type0, 
    /* G_BITREVERSE */
    type0, type0, 
    /* G_FCEIL */
    type0, type0, 
    /* G_FCOS */
    type0, type0, 
    /* G_FSIN */
    type0, type0, 
    /* G_FTAN */
    type0, type0, 
    /* G_FACOS */
    type0, type0, 
    /* G_FASIN */
    type0, type0, 
    /* G_FATAN */
    type0, type0, 
    /* G_FCOSH */
    type0, type0, 
    /* G_FSINH */
    type0, type0, 
    /* G_FTANH */
    type0, type0, 
    /* G_FSQRT */
    type0, type0, 
    /* G_FFLOOR */
    type0, type0, 
    /* G_FRINT */
    type0, type0, 
    /* G_FNEARBYINT */
    type0, type0, 
    /* G_ADDRSPACE_CAST */
    type0, type1, 
    /* G_BLOCK_ADDR */
    type0, -1, 
    /* G_JUMP_TABLE */
    type0, -1, 
    /* G_DYN_STACKALLOC */
    ptype0, type1, i32imm, 
    /* G_STACKSAVE */
    ptype0, 
    /* G_STACKRESTORE */
    ptype0, 
    /* G_STRICT_FADD */
    type0, type0, type0, 
    /* G_STRICT_FSUB */
    type0, type0, type0, 
    /* G_STRICT_FMUL */
    type0, type0, type0, 
    /* G_STRICT_FDIV */
    type0, type0, type0, 
    /* G_STRICT_FREM */
    type0, type0, type0, 
    /* G_STRICT_FMA */
    type0, type0, type0, type0, 
    /* G_STRICT_FSQRT */
    type0, type0, 
    /* G_STRICT_FLDEXP */
    type0, type0, type1, 
    /* G_READ_REGISTER */
    type0, -1, 
    /* G_WRITE_REGISTER */
    -1, type0, 
    /* G_MEMCPY */
    ptype0, ptype1, type2, untyped_imm_0, 
    /* G_MEMCPY_INLINE */
    ptype0, ptype1, type2, 
    /* G_MEMMOVE */
    ptype0, ptype1, type2, untyped_imm_0, 
    /* G_MEMSET */
    ptype0, type1, type2, untyped_imm_0, 
    /* G_BZERO */
    ptype0, type1, untyped_imm_0, 
    /* G_TRAP */
    /* G_DEBUGTRAP */
    /* G_UBSANTRAP */
    i8imm, 
    /* G_VECREDUCE_SEQ_FADD */
    type0, type1, type2, 
    /* G_VECREDUCE_SEQ_FMUL */
    type0, type1, type2, 
    /* G_VECREDUCE_FADD */
    type0, type1, 
    /* G_VECREDUCE_FMUL */
    type0, type1, 
    /* G_VECREDUCE_FMAX */
    type0, type1, 
    /* G_VECREDUCE_FMIN */
    type0, type1, 
    /* G_VECREDUCE_FMAXIMUM */
    type0, type1, 
    /* G_VECREDUCE_FMINIMUM */
    type0, type1, 
    /* G_VECREDUCE_ADD */
    type0, type1, 
    /* G_VECREDUCE_MUL */
    type0, type1, 
    /* G_VECREDUCE_AND */
    type0, type1, 
    /* G_VECREDUCE_OR */
    type0, type1, 
    /* G_VECREDUCE_XOR */
    type0, type1, 
    /* G_VECREDUCE_SMAX */
    type0, type1, 
    /* G_VECREDUCE_SMIN */
    type0, type1, 
    /* G_VECREDUCE_UMAX */
    type0, type1, 
    /* G_VECREDUCE_UMIN */
    type0, type1, 
    /* G_SBFX */
    type0, type0, type1, type1, 
    /* G_UBFX */
    type0, type0, type1, type1, 
    /* ADCWRdRr */
    DREGS, DREGS, DREGS, 
    /* ADDWRdRr */
    DREGS, DREGS, DREGS, 
    /* ADJCALLSTACKDOWN */
    i16imm, i16imm, 
    /* ADJCALLSTACKUP */
    i16imm, i16imm, 
    /* ANDIWRdK */
    DLDREGS, DLDREGS, i16imm, 
    /* ANDWRdRr */
    DREGS, DREGS, DREGS, 
    /* ASRBNRd */
    LD8, GPR8, imm_ldi8, 
    /* ASRWLoRd */
    DREGS, DREGS, 
    /* ASRWNRd */
    DREGS, DREGS, imm16, 
    /* ASRWRd */
    DREGS, DREGS, 
    /* Asr16 */
    DREGS, DREGS, GPR8, 
    /* Asr32 */
    DREGS, DREGS, DREGS, DREGS, i8imm, 
    /* Asr8 */
    GPR8, GPR8, GPR8, 
    /* AtomicFence */
    /* AtomicLoad16 */
    DREGS, PTRDISPREGS, 
    /* AtomicLoad8 */
    GPR8, PTRREGS, 
    /* AtomicLoadAdd16 */
    DREGS, PTRDISPREGS, DREGS, 
    /* AtomicLoadAdd8 */
    GPR8, PTRREGS, GPR8, 
    /* AtomicLoadAnd16 */
    DREGS, PTRDISPREGS, DREGS, 
    /* AtomicLoadAnd8 */
    GPR8, PTRREGS, GPR8, 
    /* AtomicLoadOr16 */
    DREGS, PTRDISPREGS, DREGS, 
    /* AtomicLoadOr8 */
    GPR8, PTRREGS, GPR8, 
    /* AtomicLoadSub16 */
    DREGS, PTRDISPREGS, DREGS, 
    /* AtomicLoadSub8 */
    GPR8, PTRREGS, GPR8, 
    /* AtomicLoadXor16 */
    DREGS, PTRDISPREGS, DREGS, 
    /* AtomicLoadXor8 */
    GPR8, PTRREGS, GPR8, 
    /* AtomicStore16 */
    PTRDISPREGS, DREGS, 
    /* AtomicStore8 */
    PTRREGS, GPR8, 
    /* COMWRd */
    DREGS, DREGS, 
    /* CPCWRdRr */
    DREGS, DREGS, 
    /* CPWRdRr */
    DREGS, DREGS, 
    /* CopyZero */
    GPR8, 
    /* ELPMBRdZ */
    GPR8, ZREG, LD8, 
    /* ELPMBRdZPi */
    GPR8, ZREG, LD8, 
    /* ELPMWRdZ */
    DREGS, ZREG, LD8, 
    /* ELPMWRdZPi */
    DREGS, ZREG, LD8, 
    /* EORWRdRr */
    DREGS, DREGS, DREGS, 
    /* FRMIDX */
    DLDREGS, DLDREGS, i16imm, 
    /* INWRdA */
    DREGS, imm_port6, 
    /* LDDWRdPtrQ */
    DREGS, PTRDISPREGS, i16imm, 
    /* LDDWRdYQ */
    DREGS, PTRDISPREGS, i16imm, 
    /* LDIWRdK */
    DLDREGS, i16imm, 
    /* LDSWRdK */
    DREGS, i16imm, 
    /* LDWRdPtr */
    DREGS, PTRDISPREGS, 
    /* LDWRdPtrPd */
    DREGS, PTRREGS, PTRREGS, 
    /* LDWRdPtrPi */
    DREGS, PTRREGS, PTRREGS, 
    /* LPMBRdZ */
    GPR8, ZREG, 
    /* LPMWRdZ */
    DREGS, ZREG, 
    /* LPMWRdZPi */
    DREGS, ZREG, 
    /* LSLBNRd */
    LD8, GPR8, imm_ldi8, 
    /* LSLWHiRd */
    DREGS, DREGS, 
    /* LSLWNRd */
    DLDREGS, DREGS, imm16, 
    /* LSLWRd */
    DREGS, DREGS, 
    /* LSRBNRd */
    LD8, GPR8, imm_ldi8, 
    /* LSRWLoRd */
    DREGS, DREGS, 
    /* LSRWNRd */
    DLDREGS, DREGS, imm16, 
    /* LSRWRd */
    DREGS, DREGS, 
    /* Lsl16 */
    DREGS, DREGS, GPR8, 
    /* Lsl32 */
    DREGS, DREGS, DREGS, DREGS, i8imm, 
    /* Lsl8 */
    GPR8, GPR8, GPR8, 
    /* Lsr16 */
    DREGS, DREGS, GPR8, 
    /* Lsr32 */
    DREGS, DREGS, DREGS, DREGS, i8imm, 
    /* Lsr8 */
    GPR8, GPR8, GPR8, 
    /* NEGWRd */
    DREGS, DREGS, GPR8, 
    /* ORIWRdK */
    DLDREGS, DLDREGS, i16imm, 
    /* ORWRdRr */
    DREGS, DREGS, DREGS, 
    /* OUTWARr */
    imm_port6, DREGS, 
    /* POPWRd */
    DREGS, 
    /* PUSHWRr */
    DREGS, 
    /* ROLBRdR1 */
    GPR8, GPR8, 
    /* ROLBRdR17 */
    GPR8, GPR8, 
    /* ROLWRd */
    DREGS, DREGS, 
    /* RORBRd */
    GPR8, GPR8, 
    /* RORWRd */
    DREGS, DREGS, 
    /* Rol16 */
    DREGS, DREGS, GPR8, 
    /* Rol8 */
    GPR8, GPR8, GPR8, 
    /* Ror16 */
    DREGS, DREGS, GPR8, 
    /* Ror8 */
    GPR8, GPR8, GPR8, 
    /* SBCIWRdK */
    DLDREGS, DLDREGS, i16imm, 
    /* SBCWRdRr */
    DREGS, DREGS, DREGS, 
    /* SEXT */
    DREGS, GPR8, 
    /* SPREAD */
    DREGS, GPRSP, 
    /* SPWRITE */
    GPRSP, DREGS, 
    /* STDSPQRr */
    GPRSP, i16imm, GPR8, 
    /* STDWPtrQRr */
    PTRDISPREGS, i16imm, DREGS, 
    /* STDWSPQRr */
    GPRSP, i16imm, DREGS, 
    /* STSWKRr */
    i16imm, DREGS, 
    /* STWPtrPdRr */
    PTRREGS, PTRREGS, DREGS, i8imm, 
    /* STWPtrPiRr */
    PTRREGS, PTRREGS, DREGS, i8imm, 
    /* STWPtrRr */
    PTRDISPREGS, DREGS, 
    /* SUBIWRdK */
    DLDREGS, DLDREGS, i16imm, 
    /* SUBWRdRr */
    DREGS, DREGS, DREGS, 
    /* Select16 */
    DREGS, DREGS, DREGS, i8imm, 
    /* Select8 */
    GPR8, GPR8, GPR8, i8imm, 
    /* ZEXT */
    DREGS, GPR8, 
    /* ADCRdRr */
    GPR8, GPR8, GPR8, 
    /* ADDRdRr */
    GPR8, GPR8, GPR8, 
    /* ADIWRdK */
    IWREGS, IWREGS, imm_arith6, 
    /* ANDIRdK */
    LD8, LD8, imm_ldi8, 
    /* ANDRdRr */
    GPR8, GPR8, GPR8, 
    /* ASRRd */
    GPR8, GPR8, 
    /* BCLRs */
    i8imm, 
    /* BLD */
    GPR8, GPR8, i8imm, 
    /* BRBCsk */
    i8imm, relbrtarget_7, 
    /* BRBSsk */
    i8imm, relbrtarget_7, 
    /* BREAK */
    /* BREQk */
    relbrtarget_7, 
    /* BRGEk */
    relbrtarget_7, 
    /* BRLOk */
    relbrtarget_7, 
    /* BRLTk */
    relbrtarget_7, 
    /* BRMIk */
    relbrtarget_7, 
    /* BRNEk */
    relbrtarget_7, 
    /* BRPLk */
    relbrtarget_7, 
    /* BRSHk */
    relbrtarget_7, 
    /* BSETs */
    i8imm, 
    /* BST */
    GPR8, i8imm, 
    /* CALLk */
    call_target, 
    /* CBIAb */
    imm_port5, i8imm, 
    /* COMRd */
    GPR8, GPR8, 
    /* CPCRdRr */
    GPR8, GPR8, 
    /* CPIRdK */
    LD8, imm_ldi8, 
    /* CPRdRr */
    GPR8, GPR8, 
    /* CPSE */
    GPR8, GPR8, 
    /* DECRd */
    GPR8, GPR8, 
    /* DESK */
    i8imm, 
    /* EICALL */
    /* EIJMP */
    /* ELPM */
    /* ELPMRdZ */
    GPR8, ZREG, 
    /* ELPMRdZPi */
    GPR8, ZREG, 
    /* EORRdRr */
    GPR8, GPR8, GPR8, 
    /* FMUL */
    LD8lo, LD8lo, 
    /* FMULS */
    LD8lo, LD8lo, 
    /* FMULSU */
    LD8lo, LD8lo, 
    /* ICALL */
    /* IJMP */
    /* INCRd */
    GPR8, GPR8, 
    /* INRdA */
    GPR8, imm_port6, 
    /* JMPk */
    call_target, 
    /* LACZRd */
    GPR8, ZREG, 
    /* LASZRd */
    GPR8, ZREG, 
    /* LATZRd */
    GPR8, ZREG, 
    /* LDDRdPtrQ */
    GPR8, PTRDISPREGS, i16imm, 
    /* LDIRdK */
    LD8, imm_ldi8, 
    /* LDRdPtr */
    GPR8, PTRREGS, 
    /* LDRdPtrPd */
    GPR8, PTRREGS, PTRREGS, 
    /* LDRdPtrPi */
    GPR8, PTRREGS, PTRREGS, 
    /* LDSRdK */
    GPR8, imm16, 
    /* LDSRdKTiny */
    LD8, imm7tiny, 
    /* LPM */
    /* LPMRdZ */
    GPR8, ZREG, 
    /* LPMRdZPi */
    GPR8, ZREG, 
    /* LSRRd */
    GPR8, GPR8, 
    /* MOVRdRr */
    GPR8, GPR8, 
    /* MOVWRdRr */
    DREGS, DREGS, 
    /* MULRdRr */
    GPR8, GPR8, 
    /* MULSRdRr */
    LD8, LD8, 
    /* MULSURdRr */
    LD8lo, LD8lo, 
    /* NEGRd */
    GPR8, GPR8, 
    /* NOP */
    /* ORIRdK */
    LD8, LD8, imm_ldi8, 
    /* ORRdRr */
    GPR8, GPR8, GPR8, 
    /* OUTARr */
    imm_port6, GPR8, 
    /* POPRd */
    GPR8, 
    /* PUSHRr */
    GPR8, 
    /* RCALLk */
    rcalltarget_13, 
    /* RET */
    /* RETI */
    /* RJMPk */
    brtarget_13, 
    /* RORRd */
    GPR8, GPR8, 
    /* SBCIRdK */
    LD8, LD8, imm_ldi8, 
    /* SBCRdRr */
    GPR8, GPR8, GPR8, 
    /* SBIAb */
    imm_port5, i8imm, 
    /* SBICAb */
    imm_port5, i8imm, 
    /* SBISAb */
    imm_port5, i8imm, 
    /* SBIWRdK */
    IWREGS, IWREGS, imm_arith6, 
    /* SBRCRrB */
    GPR8, i8imm, 
    /* SBRSRrB */
    GPR8, i8imm, 
    /* SLEEP */
    /* SPM */
    /* SPMZPi */
    ZREG, 
    /* STDPtrQRr */
    PTRDISPREGS, i16imm, GPR8, 
    /* STPtrPdRr */
    PTRREGS, PTRREGS, GPR8, i8imm, 
    /* STPtrPiRr */
    PTRREGS, PTRREGS, GPR8, i8imm, 
    /* STPtrRr */
    PTRREGS, GPR8, 
    /* STSKRr */
    imm16, GPR8, 
    /* STSKRrTiny */
    imm7tiny, LD8, 
    /* SUBIRdK */
    LD8, LD8, imm_ldi8, 
    /* SUBRdRr */
    GPR8, GPR8, GPR8, 
    /* SWAPRd */
    GPR8, GPR8, 
    /* WDR */
    /* XCHZRd */
    GPR8, ZREG, 
  };
  return OpcodeOperandTypes[Offsets[Opcode] + OpIdx];
}
} // end namespace AVR
} // end namespace llvm
#endif // GET_INSTRINFO_OPERAND_TYPE

#ifdef GET_INSTRINFO_MEM_OPERAND_SIZE
#undef GET_INSTRINFO_MEM_OPERAND_SIZE
namespace llvm {
namespace AVR {
LLVM_READONLY
static int getMemOperandSize(int OpType) {
  switch (OpType) {
  default: return 0;
  }
}
} // end namespace AVR
} // end namespace llvm
#endif // GET_INSTRINFO_MEM_OPERAND_SIZE

#ifdef GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP
#undef GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP
namespace llvm {
namespace AVR {
LLVM_READONLY static unsigned
getLogicalOperandSize(uint16_t Opcode, uint16_t LogicalOpIdx) {
  return LogicalOpIdx;
}
LLVM_READONLY static inline unsigned
getLogicalOperandIdx(uint16_t Opcode, uint16_t LogicalOpIdx) {
  auto S = 0U;
  for (auto i = 0U; i < LogicalOpIdx; ++i)
    S += getLogicalOperandSize(Opcode, i);
  return S;
}
} // end namespace AVR
} // end namespace llvm
#endif // GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP

#ifdef GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP
#undef GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP
namespace llvm {
namespace AVR {
LLVM_READONLY static int
getLogicalOperandType(uint16_t Opcode, uint16_t LogicalOpIdx) {
  return -1;
}
} // end namespace AVR
} // end namespace llvm
#endif // GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP

#ifdef GET_INSTRINFO_MC_HELPER_DECLS
#undef GET_INSTRINFO_MC_HELPER_DECLS

namespace llvm {
class MCInst;
class FeatureBitset;

namespace AVR_MC {

void verifyInstructionPredicates(unsigned Opcode, const FeatureBitset &Features);

} // end namespace AVR_MC
} // end namespace llvm

#endif // GET_INSTRINFO_MC_HELPER_DECLS

#ifdef GET_INSTRINFO_MC_HELPERS
#undef GET_INSTRINFO_MC_HELPERS

namespace llvm {
namespace AVR_MC {

} // end namespace AVR_MC
} // end namespace llvm

#endif // GET_GENISTRINFO_MC_HELPERS

#if (defined(ENABLE_INSTR_PREDICATE_VERIFIER) && !defined(NDEBUG)) ||\
    defined(GET_AVAILABLE_OPCODE_CHECKER)
#define GET_COMPUTE_FEATURES
#endif
#ifdef GET_COMPUTE_FEATURES
#undef GET_COMPUTE_FEATURES
namespace llvm {
namespace AVR_MC {

// Bits for subtarget features that participate in instruction matching.
enum SubtargetFeatureBits : uint8_t {
  Feature_HasSRAMBit = 14,
  Feature_HasJMPCALLBit = 7,
  Feature_HasIJMPCALLBit = 6,
  Feature_HasEIJMPCALLBit = 3,
  Feature_HasADDSUBIWBit = 0,
  Feature_HasSmallStackBit = 15,
  Feature_HasMOVWBit = 10,
  Feature_HasLPMBit = 8,
  Feature_HasLPMXBit = 9,
  Feature_HasELPMBit = 4,
  Feature_HasELPMXBit = 5,
  Feature_HasSPMBit = 12,
  Feature_HasSPMXBit = 13,
  Feature_HasDESBit = 2,
  Feature_SupportsRMWBit = 18,
  Feature_SupportsMultiplicationBit = 17,
  Feature_HasBREAKBit = 1,
  Feature_HasTinyEncodingBit = 16,
  Feature_HasNonTinyEncodingBit = 11,
};

inline FeatureBitset computeAvailableFeatures(const FeatureBitset &FB) {
  FeatureBitset Features;
  if (FB[AVR::FeatureSRAM])
    Features.set(Feature_HasSRAMBit);
  if (FB[AVR::FeatureJMPCALL])
    Features.set(Feature_HasJMPCALLBit);
  if (FB[AVR::FeatureIJMPCALL])
    Features.set(Feature_HasIJMPCALLBit);
  if (FB[AVR::FeatureEIJMPCALL])
    Features.set(Feature_HasEIJMPCALLBit);
  if (FB[AVR::FeatureADDSUBIW])
    Features.set(Feature_HasADDSUBIWBit);
  if (FB[AVR::FeatureSmallStack])
    Features.set(Feature_HasSmallStackBit);
  if (FB[AVR::FeatureMOVW])
    Features.set(Feature_HasMOVWBit);
  if (FB[AVR::FeatureLPM])
    Features.set(Feature_HasLPMBit);
  if (FB[AVR::FeatureLPMX])
    Features.set(Feature_HasLPMXBit);
  if (FB[AVR::FeatureELPM])
    Features.set(Feature_HasELPMBit);
  if (FB[AVR::FeatureELPMX])
    Features.set(Feature_HasELPMXBit);
  if (FB[AVR::FeatureSPM])
    Features.set(Feature_HasSPMBit);
  if (FB[AVR::FeatureSPMX])
    Features.set(Feature_HasSPMXBit);
  if (FB[AVR::FeatureDES])
    Features.set(Feature_HasDESBit);
  if (FB[AVR::FeatureRMW])
    Features.set(Feature_SupportsRMWBit);
  if (FB[AVR::FeatureMultiplication])
    Features.set(Feature_SupportsMultiplicationBit);
  if (FB[AVR::FeatureBREAK])
    Features.set(Feature_HasBREAKBit);
  if (FB[AVR::FeatureTinyEncoding])
    Features.set(Feature_HasTinyEncodingBit);
  if (!FB[AVR::FeatureTinyEncoding])
    Features.set(Feature_HasNonTinyEncodingBit);
  return Features;
}

inline FeatureBitset computeRequiredFeatures(unsigned Opcode) {
  enum : uint8_t {
    CEFBS_None,
    CEFBS_HasADDSUBIW,
    CEFBS_HasBREAK,
    CEFBS_HasDES,
    CEFBS_HasEIJMPCALL,
    CEFBS_HasELPM,
    CEFBS_HasELPMX,
    CEFBS_HasIJMPCALL,
    CEFBS_HasJMPCALL,
    CEFBS_HasLPM,
    CEFBS_HasLPMX,
    CEFBS_HasMOVW,
    CEFBS_HasNonTinyEncoding,
    CEFBS_HasSPM,
    CEFBS_HasSPMX,
    CEFBS_HasSRAM,
    CEFBS_HasTinyEncoding,
    CEFBS_SupportsMultiplication,
    CEFBS_SupportsRMW,
    CEFBS_HasSRAM_HasNonTinyEncoding,
    CEFBS_HasSRAM_HasTinyEncoding,
  };

  static constexpr FeatureBitset FeatureBitsets[] = {
    {}, // CEFBS_None
    {Feature_HasADDSUBIWBit, },
    {Feature_HasBREAKBit, },
    {Feature_HasDESBit, },
    {Feature_HasEIJMPCALLBit, },
    {Feature_HasELPMBit, },
    {Feature_HasELPMXBit, },
    {Feature_HasIJMPCALLBit, },
    {Feature_HasJMPCALLBit, },
    {Feature_HasLPMBit, },
    {Feature_HasLPMXBit, },
    {Feature_HasMOVWBit, },
    {Feature_HasNonTinyEncodingBit, },
    {Feature_HasSPMBit, },
    {Feature_HasSPMXBit, },
    {Feature_HasSRAMBit, },
    {Feature_HasTinyEncodingBit, },
    {Feature_SupportsMultiplicationBit, },
    {Feature_SupportsRMWBit, },
    {Feature_HasSRAMBit, Feature_HasNonTinyEncodingBit, },
    {Feature_HasSRAMBit, Feature_HasTinyEncodingBit, },
  };
  static constexpr uint8_t RequiredFeaturesRefs[] = {
    CEFBS_None, // PHI = 0
    CEFBS_None, // INLINEASM = 1
    CEFBS_None, // INLINEASM_BR = 2
    CEFBS_None, // CFI_INSTRUCTION = 3
    CEFBS_None, // EH_LABEL = 4
    CEFBS_None, // GC_LABEL = 5
    CEFBS_None, // ANNOTATION_LABEL = 6
    CEFBS_None, // KILL = 7
    CEFBS_None, // EXTRACT_SUBREG = 8
    CEFBS_None, // INSERT_SUBREG = 9
    CEFBS_None, // IMPLICIT_DEF = 10
    CEFBS_None, // SUBREG_TO_REG = 11
    CEFBS_None, // COPY_TO_REGCLASS = 12
    CEFBS_None, // DBG_VALUE = 13
    CEFBS_None, // DBG_VALUE_LIST = 14
    CEFBS_None, // DBG_INSTR_REF = 15
    CEFBS_None, // DBG_PHI = 16
    CEFBS_None, // DBG_LABEL = 17
    CEFBS_None, // REG_SEQUENCE = 18
    CEFBS_None, // COPY = 19
    CEFBS_None, // BUNDLE = 20
    CEFBS_None, // LIFETIME_START = 21
    CEFBS_None, // LIFETIME_END = 22
    CEFBS_None, // PSEUDO_PROBE = 23
    CEFBS_None, // ARITH_FENCE = 24
    CEFBS_None, // STACKMAP = 25
    CEFBS_None, // FENTRY_CALL = 26
    CEFBS_None, // PATCHPOINT = 27
    CEFBS_None, // LOAD_STACK_GUARD = 28
    CEFBS_None, // PREALLOCATED_SETUP = 29
    CEFBS_None, // PREALLOCATED_ARG = 30
    CEFBS_None, // STATEPOINT = 31
    CEFBS_None, // LOCAL_ESCAPE = 32
    CEFBS_None, // FAULTING_OP = 33
    CEFBS_None, // PATCHABLE_OP = 34
    CEFBS_None, // PATCHABLE_FUNCTION_ENTER = 35
    CEFBS_None, // PATCHABLE_RET = 36
    CEFBS_None, // PATCHABLE_FUNCTION_EXIT = 37
    CEFBS_None, // PATCHABLE_TAIL_CALL = 38
    CEFBS_None, // PATCHABLE_EVENT_CALL = 39
    CEFBS_None, // PATCHABLE_TYPED_EVENT_CALL = 40
    CEFBS_None, // ICALL_BRANCH_FUNNEL = 41
    CEFBS_None, // FAKE_USE = 42
    CEFBS_None, // MEMBARRIER = 43
    CEFBS_None, // JUMP_TABLE_DEBUG_INFO = 44
    CEFBS_None, // CONVERGENCECTRL_ENTRY = 45
    CEFBS_None, // CONVERGENCECTRL_ANCHOR = 46
    CEFBS_None, // CONVERGENCECTRL_LOOP = 47
    CEFBS_None, // CONVERGENCECTRL_GLUE = 48
    CEFBS_None, // G_ASSERT_SEXT = 49
    CEFBS_None, // G_ASSERT_ZEXT = 50
    CEFBS_None, // G_ASSERT_ALIGN = 51
    CEFBS_None, // G_ADD = 52
    CEFBS_None, // G_SUB = 53
    CEFBS_None, // G_MUL = 54
    CEFBS_None, // G_SDIV = 55
    CEFBS_None, // G_UDIV = 56
    CEFBS_None, // G_SREM = 57
    CEFBS_None, // G_UREM = 58
    CEFBS_None, // G_SDIVREM = 59
    CEFBS_None, // G_UDIVREM = 60
    CEFBS_None, // G_AND = 61
    CEFBS_None, // G_OR = 62
    CEFBS_None, // G_XOR = 63
    CEFBS_None, // G_IMPLICIT_DEF = 64
    CEFBS_None, // G_PHI = 65
    CEFBS_None, // G_FRAME_INDEX = 66
    CEFBS_None, // G_GLOBAL_VALUE = 67
    CEFBS_None, // G_PTRAUTH_GLOBAL_VALUE = 68
    CEFBS_None, // G_CONSTANT_POOL = 69
    CEFBS_None, // G_EXTRACT = 70
    CEFBS_None, // G_UNMERGE_VALUES = 71
    CEFBS_None, // G_INSERT = 72
    CEFBS_None, // G_MERGE_VALUES = 73
    CEFBS_None, // G_BUILD_VECTOR = 74
    CEFBS_None, // G_BUILD_VECTOR_TRUNC = 75
    CEFBS_None, // G_CONCAT_VECTORS = 76
    CEFBS_None, // G_PTRTOINT = 77
    CEFBS_None, // G_INTTOPTR = 78
    CEFBS_None, // G_BITCAST = 79
    CEFBS_None, // G_FREEZE = 80
    CEFBS_None, // G_CONSTANT_FOLD_BARRIER = 81
    CEFBS_None, // G_INTRINSIC_FPTRUNC_ROUND = 82
    CEFBS_None, // G_INTRINSIC_TRUNC = 83
    CEFBS_None, // G_INTRINSIC_ROUND = 84
    CEFBS_None, // G_INTRINSIC_LRINT = 85
    CEFBS_None, // G_INTRINSIC_LLRINT = 86
    CEFBS_None, // G_INTRINSIC_ROUNDEVEN = 87
    CEFBS_None, // G_READCYCLECOUNTER = 88
    CEFBS_None, // G_READSTEADYCOUNTER = 89
    CEFBS_None, // G_LOAD = 90
    CEFBS_None, // G_SEXTLOAD = 91
    CEFBS_None, // G_ZEXTLOAD = 92
    CEFBS_None, // G_INDEXED_LOAD = 93
    CEFBS_None, // G_INDEXED_SEXTLOAD = 94
    CEFBS_None, // G_INDEXED_ZEXTLOAD = 95
    CEFBS_None, // G_STORE = 96
    CEFBS_None, // G_INDEXED_STORE = 97
    CEFBS_None, // G_ATOMIC_CMPXCHG_WITH_SUCCESS = 98
    CEFBS_None, // G_ATOMIC_CMPXCHG = 99
    CEFBS_None, // G_ATOMICRMW_XCHG = 100
    CEFBS_None, // G_ATOMICRMW_ADD = 101
    CEFBS_None, // G_ATOMICRMW_SUB = 102
    CEFBS_None, // G_ATOMICRMW_AND = 103
    CEFBS_None, // G_ATOMICRMW_NAND = 104
    CEFBS_None, // G_ATOMICRMW_OR = 105
    CEFBS_None, // G_ATOMICRMW_XOR = 106
    CEFBS_None, // G_ATOMICRMW_MAX = 107
    CEFBS_None, // G_ATOMICRMW_MIN = 108
    CEFBS_None, // G_ATOMICRMW_UMAX = 109
    CEFBS_None, // G_ATOMICRMW_UMIN = 110
    CEFBS_None, // G_ATOMICRMW_FADD = 111
    CEFBS_None, // G_ATOMICRMW_FSUB = 112
    CEFBS_None, // G_ATOMICRMW_FMAX = 113
    CEFBS_None, // G_ATOMICRMW_FMIN = 114
    CEFBS_None, // G_ATOMICRMW_UINC_WRAP = 115
    CEFBS_None, // G_ATOMICRMW_UDEC_WRAP = 116
    CEFBS_None, // G_FENCE = 117
    CEFBS_None, // G_PREFETCH = 118
    CEFBS_None, // G_BRCOND = 119
    CEFBS_None, // G_BRINDIRECT = 120
    CEFBS_None, // G_INVOKE_REGION_START = 121
    CEFBS_None, // G_INTRINSIC = 122
    CEFBS_None, // G_INTRINSIC_W_SIDE_EFFECTS = 123
    CEFBS_None, // G_INTRINSIC_CONVERGENT = 124
    CEFBS_None, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS = 125
    CEFBS_None, // G_ANYEXT = 126
    CEFBS_None, // G_TRUNC = 127
    CEFBS_None, // G_CONSTANT = 128
    CEFBS_None, // G_FCONSTANT = 129
    CEFBS_None, // G_VASTART = 130
    CEFBS_None, // G_VAARG = 131
    CEFBS_None, // G_SEXT = 132
    CEFBS_None, // G_SEXT_INREG = 133
    CEFBS_None, // G_ZEXT = 134
    CEFBS_None, // G_SHL = 135
    CEFBS_None, // G_LSHR = 136
    CEFBS_None, // G_ASHR = 137
    CEFBS_None, // G_FSHL = 138
    CEFBS_None, // G_FSHR = 139
    CEFBS_None, // G_ROTR = 140
    CEFBS_None, // G_ROTL = 141
    CEFBS_None, // G_ICMP = 142
    CEFBS_None, // G_FCMP = 143
    CEFBS_None, // G_SCMP = 144
    CEFBS_None, // G_UCMP = 145
    CEFBS_None, // G_SELECT = 146
    CEFBS_None, // G_UADDO = 147
    CEFBS_None, // G_UADDE = 148
    CEFBS_None, // G_USUBO = 149
    CEFBS_None, // G_USUBE = 150
    CEFBS_None, // G_SADDO = 151
    CEFBS_None, // G_SADDE = 152
    CEFBS_None, // G_SSUBO = 153
    CEFBS_None, // G_SSUBE = 154
    CEFBS_None, // G_UMULO = 155
    CEFBS_None, // G_SMULO = 156
    CEFBS_None, // G_UMULH = 157
    CEFBS_None, // G_SMULH = 158
    CEFBS_None, // G_UADDSAT = 159
    CEFBS_None, // G_SADDSAT = 160
    CEFBS_None, // G_USUBSAT = 161
    CEFBS_None, // G_SSUBSAT = 162
    CEFBS_None, // G_USHLSAT = 163
    CEFBS_None, // G_SSHLSAT = 164
    CEFBS_None, // G_SMULFIX = 165
    CEFBS_None, // G_UMULFIX = 166
    CEFBS_None, // G_SMULFIXSAT = 167
    CEFBS_None, // G_UMULFIXSAT = 168
    CEFBS_None, // G_SDIVFIX = 169
    CEFBS_None, // G_UDIVFIX = 170
    CEFBS_None, // G_SDIVFIXSAT = 171
    CEFBS_None, // G_UDIVFIXSAT = 172
    CEFBS_None, // G_FADD = 173
    CEFBS_None, // G_FSUB = 174
    CEFBS_None, // G_FMUL = 175
    CEFBS_None, // G_FMA = 176
    CEFBS_None, // G_FMAD = 177
    CEFBS_None, // G_FDIV = 178
    CEFBS_None, // G_FREM = 179
    CEFBS_None, // G_FPOW = 180
    CEFBS_None, // G_FPOWI = 181
    CEFBS_None, // G_FEXP = 182
    CEFBS_None, // G_FEXP2 = 183
    CEFBS_None, // G_FEXP10 = 184
    CEFBS_None, // G_FLOG = 185
    CEFBS_None, // G_FLOG2 = 186
    CEFBS_None, // G_FLOG10 = 187
    CEFBS_None, // G_FLDEXP = 188
    CEFBS_None, // G_FFREXP = 189
    CEFBS_None, // G_FNEG = 190
    CEFBS_None, // G_FPEXT = 191
    CEFBS_None, // G_FPTRUNC = 192
    CEFBS_None, // G_FPTOSI = 193
    CEFBS_None, // G_FPTOUI = 194
    CEFBS_None, // G_SITOFP = 195
    CEFBS_None, // G_UITOFP = 196
    CEFBS_None, // G_FABS = 197
    CEFBS_None, // G_FCOPYSIGN = 198
    CEFBS_None, // G_IS_FPCLASS = 199
    CEFBS_None, // G_FCANONICALIZE = 200
    CEFBS_None, // G_FMINNUM = 201
    CEFBS_None, // G_FMAXNUM = 202
    CEFBS_None, // G_FMINNUM_IEEE = 203
    CEFBS_None, // G_FMAXNUM_IEEE = 204
    CEFBS_None, // G_FMINIMUM = 205
    CEFBS_None, // G_FMAXIMUM = 206
    CEFBS_None, // G_GET_FPENV = 207
    CEFBS_None, // G_SET_FPENV = 208
    CEFBS_None, // G_RESET_FPENV = 209
    CEFBS_None, // G_GET_FPMODE = 210
    CEFBS_None, // G_SET_FPMODE = 211
    CEFBS_None, // G_RESET_FPMODE = 212
    CEFBS_None, // G_PTR_ADD = 213
    CEFBS_None, // G_PTRMASK = 214
    CEFBS_None, // G_SMIN = 215
    CEFBS_None, // G_SMAX = 216
    CEFBS_None, // G_UMIN = 217
    CEFBS_None, // G_UMAX = 218
    CEFBS_None, // G_ABS = 219
    CEFBS_None, // G_LROUND = 220
    CEFBS_None, // G_LLROUND = 221
    CEFBS_None, // G_BR = 222
    CEFBS_None, // G_BRJT = 223
    CEFBS_None, // G_VSCALE = 224
    CEFBS_None, // G_INSERT_SUBVECTOR = 225
    CEFBS_None, // G_EXTRACT_SUBVECTOR = 226
    CEFBS_None, // G_INSERT_VECTOR_ELT = 227
    CEFBS_None, // G_EXTRACT_VECTOR_ELT = 228
    CEFBS_None, // G_SHUFFLE_VECTOR = 229
    CEFBS_None, // G_SPLAT_VECTOR = 230
    CEFBS_None, // G_VECTOR_COMPRESS = 231
    CEFBS_None, // G_CTTZ = 232
    CEFBS_None, // G_CTTZ_ZERO_UNDEF = 233
    CEFBS_None, // G_CTLZ = 234
    CEFBS_None, // G_CTLZ_ZERO_UNDEF = 235
    CEFBS_None, // G_CTPOP = 236
    CEFBS_None, // G_BSWAP = 237
    CEFBS_None, // G_BITREVERSE = 238
    CEFBS_None, // G_FCEIL = 239
    CEFBS_None, // G_FCOS = 240
    CEFBS_None, // G_FSIN = 241
    CEFBS_None, // G_FTAN = 242
    CEFBS_None, // G_FACOS = 243
    CEFBS_None, // G_FASIN = 244
    CEFBS_None, // G_FATAN = 245
    CEFBS_None, // G_FCOSH = 246
    CEFBS_None, // G_FSINH = 247
    CEFBS_None, // G_FTANH = 248
    CEFBS_None, // G_FSQRT = 249
    CEFBS_None, // G_FFLOOR = 250
    CEFBS_None, // G_FRINT = 251
    CEFBS_None, // G_FNEARBYINT = 252
    CEFBS_None, // G_ADDRSPACE_CAST = 253
    CEFBS_None, // G_BLOCK_ADDR = 254
    CEFBS_None, // G_JUMP_TABLE = 255
    CEFBS_None, // G_DYN_STACKALLOC = 256
    CEFBS_None, // G_STACKSAVE = 257
    CEFBS_None, // G_STACKRESTORE = 258
    CEFBS_None, // G_STRICT_FADD = 259
    CEFBS_None, // G_STRICT_FSUB = 260
    CEFBS_None, // G_STRICT_FMUL = 261
    CEFBS_None, // G_STRICT_FDIV = 262
    CEFBS_None, // G_STRICT_FREM = 263
    CEFBS_None, // G_STRICT_FMA = 264
    CEFBS_None, // G_STRICT_FSQRT = 265
    CEFBS_None, // G_STRICT_FLDEXP = 266
    CEFBS_None, // G_READ_REGISTER = 267
    CEFBS_None, // G_WRITE_REGISTER = 268
    CEFBS_None, // G_MEMCPY = 269
    CEFBS_None, // G_MEMCPY_INLINE = 270
    CEFBS_None, // G_MEMMOVE = 271
    CEFBS_None, // G_MEMSET = 272
    CEFBS_None, // G_BZERO = 273
    CEFBS_None, // G_TRAP = 274
    CEFBS_None, // G_DEBUGTRAP = 275
    CEFBS_None, // G_UBSANTRAP = 276
    CEFBS_None, // G_VECREDUCE_SEQ_FADD = 277
    CEFBS_None, // G_VECREDUCE_SEQ_FMUL = 278
    CEFBS_None, // G_VECREDUCE_FADD = 279
    CEFBS_None, // G_VECREDUCE_FMUL = 280
    CEFBS_None, // G_VECREDUCE_FMAX = 281
    CEFBS_None, // G_VECREDUCE_FMIN = 282
    CEFBS_None, // G_VECREDUCE_FMAXIMUM = 283
    CEFBS_None, // G_VECREDUCE_FMINIMUM = 284
    CEFBS_None, // G_VECREDUCE_ADD = 285
    CEFBS_None, // G_VECREDUCE_MUL = 286
    CEFBS_None, // G_VECREDUCE_AND = 287
    CEFBS_None, // G_VECREDUCE_OR = 288
    CEFBS_None, // G_VECREDUCE_XOR = 289
    CEFBS_None, // G_VECREDUCE_SMAX = 290
    CEFBS_None, // G_VECREDUCE_SMIN = 291
    CEFBS_None, // G_VECREDUCE_UMAX = 292
    CEFBS_None, // G_VECREDUCE_UMIN = 293
    CEFBS_None, // G_SBFX = 294
    CEFBS_None, // G_UBFX = 295
    CEFBS_None, // ADCWRdRr = 296
    CEFBS_None, // ADDWRdRr = 297
    CEFBS_None, // ADJCALLSTACKDOWN = 298
    CEFBS_None, // ADJCALLSTACKUP = 299
    CEFBS_None, // ANDIWRdK = 300
    CEFBS_None, // ANDWRdRr = 301
    CEFBS_None, // ASRBNRd = 302
    CEFBS_None, // ASRWLoRd = 303
    CEFBS_None, // ASRWNRd = 304
    CEFBS_None, // ASRWRd = 305
    CEFBS_None, // Asr16 = 306
    CEFBS_None, // Asr32 = 307
    CEFBS_None, // Asr8 = 308
    CEFBS_None, // AtomicFence = 309
    CEFBS_None, // AtomicLoad16 = 310
    CEFBS_None, // AtomicLoad8 = 311
    CEFBS_None, // AtomicLoadAdd16 = 312
    CEFBS_None, // AtomicLoadAdd8 = 313
    CEFBS_None, // AtomicLoadAnd16 = 314
    CEFBS_None, // AtomicLoadAnd8 = 315
    CEFBS_None, // AtomicLoadOr16 = 316
    CEFBS_None, // AtomicLoadOr8 = 317
    CEFBS_None, // AtomicLoadSub16 = 318
    CEFBS_None, // AtomicLoadSub8 = 319
    CEFBS_None, // AtomicLoadXor16 = 320
    CEFBS_None, // AtomicLoadXor8 = 321
    CEFBS_None, // AtomicStore16 = 322
    CEFBS_None, // AtomicStore8 = 323
    CEFBS_None, // COMWRd = 324
    CEFBS_None, // CPCWRdRr = 325
    CEFBS_None, // CPWRdRr = 326
    CEFBS_None, // CopyZero = 327
    CEFBS_HasELPM, // ELPMBRdZ = 328
    CEFBS_HasELPMX, // ELPMBRdZPi = 329
    CEFBS_HasELPM, // ELPMWRdZ = 330
    CEFBS_HasELPMX, // ELPMWRdZPi = 331
    CEFBS_None, // EORWRdRr = 332
    CEFBS_None, // FRMIDX = 333
    CEFBS_None, // INWRdA = 334
    CEFBS_HasSRAM, // LDDWRdPtrQ = 335
    CEFBS_HasSRAM, // LDDWRdYQ = 336
    CEFBS_None, // LDIWRdK = 337
    CEFBS_HasSRAM_HasNonTinyEncoding, // LDSWRdK = 338
    CEFBS_HasSRAM, // LDWRdPtr = 339
    CEFBS_HasSRAM, // LDWRdPtrPd = 340
    CEFBS_HasSRAM, // LDWRdPtrPi = 341
    CEFBS_HasLPM, // LPMBRdZ = 342
    CEFBS_HasLPM, // LPMWRdZ = 343
    CEFBS_HasLPMX, // LPMWRdZPi = 344
    CEFBS_None, // LSLBNRd = 345
    CEFBS_None, // LSLWHiRd = 346
    CEFBS_None, // LSLWNRd = 347
    CEFBS_None, // LSLWRd = 348
    CEFBS_None, // LSRBNRd = 349
    CEFBS_None, // LSRWLoRd = 350
    CEFBS_None, // LSRWNRd = 351
    CEFBS_None, // LSRWRd = 352
    CEFBS_None, // Lsl16 = 353
    CEFBS_None, // Lsl32 = 354
    CEFBS_None, // Lsl8 = 355
    CEFBS_None, // Lsr16 = 356
    CEFBS_None, // Lsr32 = 357
    CEFBS_None, // Lsr8 = 358
    CEFBS_None, // NEGWRd = 359
    CEFBS_None, // ORIWRdK = 360
    CEFBS_None, // ORWRdRr = 361
    CEFBS_None, // OUTWARr = 362
    CEFBS_HasSRAM, // POPWRd = 363
    CEFBS_HasSRAM, // PUSHWRr = 364
    CEFBS_HasNonTinyEncoding, // ROLBRdR1 = 365
    CEFBS_HasTinyEncoding, // ROLBRdR17 = 366
    CEFBS_None, // ROLWRd = 367
    CEFBS_None, // RORBRd = 368
    CEFBS_None, // RORWRd = 369
    CEFBS_None, // Rol16 = 370
    CEFBS_None, // Rol8 = 371
    CEFBS_None, // Ror16 = 372
    CEFBS_None, // Ror8 = 373
    CEFBS_None, // SBCIWRdK = 374
    CEFBS_None, // SBCWRdRr = 375
    CEFBS_None, // SEXT = 376
    CEFBS_None, // SPREAD = 377
    CEFBS_None, // SPWRITE = 378
    CEFBS_None, // STDSPQRr = 379
    CEFBS_HasSRAM, // STDWPtrQRr = 380
    CEFBS_None, // STDWSPQRr = 381
    CEFBS_HasSRAM_HasNonTinyEncoding, // STSWKRr = 382
    CEFBS_HasSRAM, // STWPtrPdRr = 383
    CEFBS_HasSRAM, // STWPtrPiRr = 384
    CEFBS_HasSRAM, // STWPtrRr = 385
    CEFBS_None, // SUBIWRdK = 386
    CEFBS_None, // SUBWRdRr = 387
    CEFBS_None, // Select16 = 388
    CEFBS_None, // Select8 = 389
    CEFBS_None, // ZEXT = 390
    CEFBS_None, // ADCRdRr = 391
    CEFBS_None, // ADDRdRr = 392
    CEFBS_HasADDSUBIW, // ADIWRdK = 393
    CEFBS_None, // ANDIRdK = 394
    CEFBS_None, // ANDRdRr = 395
    CEFBS_None, // ASRRd = 396
    CEFBS_None, // BCLRs = 397
    CEFBS_None, // BLD = 398
    CEFBS_None, // BRBCsk = 399
    CEFBS_None, // BRBSsk = 400
    CEFBS_HasBREAK, // BREAK = 401
    CEFBS_None, // BREQk = 402
    CEFBS_None, // BRGEk = 403
    CEFBS_None, // BRLOk = 404
    CEFBS_None, // BRLTk = 405
    CEFBS_None, // BRMIk = 406
    CEFBS_None, // BRNEk = 407
    CEFBS_None, // BRPLk = 408
    CEFBS_None, // BRSHk = 409
    CEFBS_None, // BSETs = 410
    CEFBS_None, // BST = 411
    CEFBS_HasJMPCALL, // CALLk = 412
    CEFBS_None, // CBIAb = 413
    CEFBS_None, // COMRd = 414
    CEFBS_None, // CPCRdRr = 415
    CEFBS_None, // CPIRdK = 416
    CEFBS_None, // CPRdRr = 417
    CEFBS_None, // CPSE = 418
    CEFBS_None, // DECRd = 419
    CEFBS_HasDES, // DESK = 420
    CEFBS_HasEIJMPCALL, // EICALL = 421
    CEFBS_HasEIJMPCALL, // EIJMP = 422
    CEFBS_HasELPM, // ELPM = 423
    CEFBS_HasELPMX, // ELPMRdZ = 424
    CEFBS_HasELPMX, // ELPMRdZPi = 425
    CEFBS_None, // EORRdRr = 426
    CEFBS_SupportsMultiplication, // FMUL = 427
    CEFBS_SupportsMultiplication, // FMULS = 428
    CEFBS_SupportsMultiplication, // FMULSU = 429
    CEFBS_HasIJMPCALL, // ICALL = 430
    CEFBS_HasIJMPCALL, // IJMP = 431
    CEFBS_None, // INCRd = 432
    CEFBS_None, // INRdA = 433
    CEFBS_HasJMPCALL, // JMPk = 434
    CEFBS_SupportsRMW, // LACZRd = 435
    CEFBS_SupportsRMW, // LASZRd = 436
    CEFBS_SupportsRMW, // LATZRd = 437
    CEFBS_HasSRAM_HasNonTinyEncoding, // LDDRdPtrQ = 438
    CEFBS_None, // LDIRdK = 439
    CEFBS_HasSRAM, // LDRdPtr = 440
    CEFBS_HasSRAM, // LDRdPtrPd = 441
    CEFBS_HasSRAM, // LDRdPtrPi = 442
    CEFBS_HasSRAM_HasNonTinyEncoding, // LDSRdK = 443
    CEFBS_HasSRAM_HasTinyEncoding, // LDSRdKTiny = 444
    CEFBS_HasLPM, // LPM = 445
    CEFBS_HasLPMX, // LPMRdZ = 446
    CEFBS_HasLPMX, // LPMRdZPi = 447
    CEFBS_None, // LSRRd = 448
    CEFBS_None, // MOVRdRr = 449
    CEFBS_HasMOVW, // MOVWRdRr = 450
    CEFBS_SupportsMultiplication, // MULRdRr = 451
    CEFBS_SupportsMultiplication, // MULSRdRr = 452
    CEFBS_SupportsMultiplication, // MULSURdRr = 453
    CEFBS_None, // NEGRd = 454
    CEFBS_None, // NOP = 455
    CEFBS_None, // ORIRdK = 456
    CEFBS_None, // ORRdRr = 457
    CEFBS_None, // OUTARr = 458
    CEFBS_HasSRAM, // POPRd = 459
    CEFBS_HasSRAM, // PUSHRr = 460
    CEFBS_None, // RCALLk = 461
    CEFBS_None, // RET = 462
    CEFBS_None, // RETI = 463
    CEFBS_None, // RJMPk = 464
    CEFBS_None, // RORRd = 465
    CEFBS_None, // SBCIRdK = 466
    CEFBS_None, // SBCRdRr = 467
    CEFBS_None, // SBIAb = 468
    CEFBS_None, // SBICAb = 469
    CEFBS_None, // SBISAb = 470
    CEFBS_HasADDSUBIW, // SBIWRdK = 471
    CEFBS_None, // SBRCRrB = 472
    CEFBS_None, // SBRSRrB = 473
    CEFBS_None, // SLEEP = 474
    CEFBS_HasSPM, // SPM = 475
    CEFBS_HasSPMX, // SPMZPi = 476
    CEFBS_HasSRAM_HasNonTinyEncoding, // STDPtrQRr = 477
    CEFBS_HasSRAM, // STPtrPdRr = 478
    CEFBS_HasSRAM, // STPtrPiRr = 479
    CEFBS_HasSRAM, // STPtrRr = 480
    CEFBS_HasSRAM_HasNonTinyEncoding, // STSKRr = 481
    CEFBS_HasSRAM_HasTinyEncoding, // STSKRrTiny = 482
    CEFBS_None, // SUBIRdK = 483
    CEFBS_None, // SUBRdRr = 484
    CEFBS_None, // SWAPRd = 485
    CEFBS_None, // WDR = 486
    CEFBS_SupportsRMW, // XCHZRd = 487
  };

  assert(Opcode < 488);
  return FeatureBitsets[RequiredFeaturesRefs[Opcode]];
}

} // end namespace AVR_MC
} // end namespace llvm
#endif // GET_COMPUTE_FEATURES

#ifdef GET_AVAILABLE_OPCODE_CHECKER
#undef GET_AVAILABLE_OPCODE_CHECKER
namespace llvm {
namespace AVR_MC {
bool isOpcodeAvailable(unsigned Opcode, const FeatureBitset &Features) {
  FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
  FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
  FeatureBitset MissingFeatures =
      (AvailableFeatures & RequiredFeatures) ^
      RequiredFeatures;
  return !MissingFeatures.any();
}
} // end namespace AVR_MC
} // end namespace llvm
#endif // GET_AVAILABLE_OPCODE_CHECKER

#ifdef ENABLE_INSTR_PREDICATE_VERIFIER
#undef ENABLE_INSTR_PREDICATE_VERIFIER
#include <sstream>

namespace llvm {
namespace AVR_MC {

#ifndef NDEBUG
static const char *SubtargetFeatureNames[] = {
  "Feature_HasADDSUBIW",
  "Feature_HasBREAK",
  "Feature_HasDES",
  "Feature_HasEIJMPCALL",
  "Feature_HasELPM",
  "Feature_HasELPMX",
  "Feature_HasIJMPCALL",
  "Feature_HasJMPCALL",
  "Feature_HasLPM",
  "Feature_HasLPMX",
  "Feature_HasMOVW",
  "Feature_HasNonTinyEncoding",
  "Feature_HasSPM",
  "Feature_HasSPMX",
  "Feature_HasSRAM",
  "Feature_HasSmallStack",
  "Feature_HasTinyEncoding",
  "Feature_SupportsMultiplication",
  "Feature_SupportsRMW",
  nullptr
};

#endif // NDEBUG

void verifyInstructionPredicates(
    unsigned Opcode, const FeatureBitset &Features) {
#ifndef NDEBUG
  FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
  FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
  FeatureBitset MissingFeatures =
      (AvailableFeatures & RequiredFeatures) ^
      RequiredFeatures;
  if (MissingFeatures.any()) {
    std::ostringstream Msg;
    Msg << "Attempting to emit " << &AVRInstrNameData[AVRInstrNameIndices[Opcode]]
        << " instruction but the ";
    for (unsigned i = 0, e = MissingFeatures.size(); i != e; ++i)
      if (MissingFeatures.test(i))
        Msg << SubtargetFeatureNames[i] << " ";
    Msg << "predicate(s) are not met";
    report_fatal_error(Msg.str().c_str());
  }
#endif // NDEBUG
}
} // end namespace AVR_MC
} // end namespace llvm
#endif // ENABLE_INSTR_PREDICATE_VERIFIER