llvm/lib/Target/AVR/AVRGenMCCodeEmitter.inc

/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
|*                                                                            *|
|* Machine Code Emitter                                                       *|
|*                                                                            *|
|* Automatically generated file, do not edit!                                 *|
|*                                                                            *|
\*===----------------------------------------------------------------------===*/

uint64_t AVRMCCodeEmitter::getBinaryCodeForInstr(const MCInst &MI,
    SmallVectorImpl<MCFixup> &Fixups,
    const MCSubtargetInfo &STI) const { … }

#ifdef GET_OPERAND_BIT_OFFSET
#undef GET_OPERAND_BIT_OFFSET

uint32_t AVRMCCodeEmitter::getOperandBitOffset(const MCInst &MI,
    unsigned OpNum,
    const MCSubtargetInfo &STI) const {
  switch (MI.getOpcode()) {
    case AVR::BREAK:
    case AVR::EICALL:
    case AVR::EIJMP:
    case AVR::ELPM:
    case AVR::ICALL:
    case AVR::IJMP:
    case AVR::LPM:
    case AVR::NOP:
    case AVR::RET:
    case AVR::RETI:
    case AVR::SLEEP:
    case AVR::SPM:
    case AVR::SPMZPi:
    case AVR::WDR: {
      break;
    }
    case AVR::OUTARr: {
      switch (OpNum) {
      case 0:
        // op: A
        return 0;
      case 1:
        // op: rr
        return 4;
      }
      break;
    }
    case AVR::CBIAb:
    case AVR::SBIAb:
    case AVR::SBICAb:
    case AVR::SBISAb: {
      switch (OpNum) {
      case 0:
        // op: addr
        return 3;
      case 1:
        // op: b
        return 0;
      }
      break;
    }
    case AVR::CALLk:
    case AVR::JMPk:
    case AVR::RCALLk:
    case AVR::RJMPk: {
      switch (OpNum) {
      case 0:
        // op: k
        return 0;
      }
      break;
    }
    case AVR::BREQk:
    case AVR::BRGEk:
    case AVR::BRLOk:
    case AVR::BRLTk:
    case AVR::BRMIk:
    case AVR::BRNEk:
    case AVR::BRPLk:
    case AVR::BRSHk: {
      switch (OpNum) {
      case 0:
        // op: k
        return 3;
      }
      break;
    }
    case AVR::DESK: {
      switch (OpNum) {
      case 0:
        // op: k
        return 4;
      }
      break;
    }
    case AVR::STDPtrQRr: {
      switch (OpNum) {
      case 0:
        // op: memri
        return 0;
      case 2:
        // op: reg
        return 4;
      }
      break;
    }
    case AVR::STPtrRr: {
      switch (OpNum) {
      case 0:
        // op: ptrreg
        return 2;
      case 1:
        // op: reg
        return 4;
      }
      break;
    }
    case AVR::LDSRdK: {
      switch (OpNum) {
      case 0:
        // op: rd
        return 20;
      case 1:
        // op: k
        return 0;
      }
      break;
    }
    case AVR::INRdA: {
      switch (OpNum) {
      case 0:
        // op: rd
        return 4;
      case 1:
        // op: A
        return 0;
      }
      break;
    }
    case AVR::BST:
    case AVR::SBRCRrB:
    case AVR::SBRSRrB: {
      switch (OpNum) {
      case 0:
        // op: rd
        return 4;
      case 1:
        // op: b
        return 0;
      }
      break;
    }
    case AVR::CPIRdK:
    case AVR::LDIRdK:
    case AVR::LDSRdKTiny: {
      switch (OpNum) {
      case 0:
        // op: rd
        return 4;
      case 1:
        // op: k
        return 0;
      }
      break;
    }
    case AVR::CPCRdRr:
    case AVR::CPRdRr:
    case AVR::CPSE:
    case AVR::FMUL:
    case AVR::FMULS:
    case AVR::FMULSU:
    case AVR::MOVRdRr:
    case AVR::MOVWRdRr:
    case AVR::MULRdRr:
    case AVR::MULSRdRr:
    case AVR::MULSURdRr: {
      switch (OpNum) {
      case 0:
        // op: rd
        return 4;
      case 1:
        // op: rr
        return 0;
      }
      break;
    }
    case AVR::BLD: {
      switch (OpNum) {
      case 0:
        // op: rd
        return 4;
      case 2:
        // op: b
        return 0;
      }
      break;
    }
    case AVR::ADIWRdK:
    case AVR::ANDIRdK:
    case AVR::ORIRdK:
    case AVR::SBCIRdK:
    case AVR::SBIWRdK:
    case AVR::SUBIRdK: {
      switch (OpNum) {
      case 0:
        // op: rd
        return 4;
      case 2:
        // op: k
        return 0;
      }
      break;
    }
    case AVR::ADCRdRr:
    case AVR::ADDRdRr:
    case AVR::ANDRdRr:
    case AVR::EORRdRr:
    case AVR::ORRdRr:
    case AVR::SBCRdRr:
    case AVR::SUBRdRr: {
      switch (OpNum) {
      case 0:
        // op: rd
        return 4;
      case 2:
        // op: rr
        return 0;
      }
      break;
    }
    case AVR::ASRRd:
    case AVR::COMRd:
    case AVR::DECRd:
    case AVR::ELPMRdZ:
    case AVR::ELPMRdZPi:
    case AVR::INCRd:
    case AVR::LACZRd:
    case AVR::LASZRd:
    case AVR::LATZRd:
    case AVR::LPMRdZ:
    case AVR::LPMRdZPi:
    case AVR::LSRRd:
    case AVR::NEGRd:
    case AVR::POPRd:
    case AVR::PUSHRr:
    case AVR::RORRd:
    case AVR::SWAPRd:
    case AVR::XCHZRd: {
      switch (OpNum) {
      case 0:
        // op: rd
        return 4;
      }
      break;
    }
    case AVR::BCLRs:
    case AVR::BSETs: {
      switch (OpNum) {
      case 0:
        // op: s
        return 4;
      }
      break;
    }
    case AVR::BRBCsk:
    case AVR::BRBSsk: {
      switch (OpNum) {
      case 1:
        // op: k
        return 3;
      case 0:
        // op: s
        return 0;
      }
      break;
    }
    case AVR::LDDRdPtrQ: {
      switch (OpNum) {
      case 1:
        // op: memri
        return 0;
      case 0:
        // op: reg
        return 4;
      }
      break;
    }
    case AVR::LDRdPtr: {
      switch (OpNum) {
      case 1:
        // op: ptrreg
        return 2;
      case 0:
        // op: reg
        return 4;
      }
      break;
    }
    case AVR::STPtrPdRr:
    case AVR::STPtrPiRr: {
      switch (OpNum) {
      case 1:
        // op: ptrreg
        return 2;
      case 2:
        // op: reg
        return 4;
      }
      break;
    }
    case AVR::STSKRr: {
      switch (OpNum) {
      case 1:
        // op: rd
        return 20;
      case 0:
        // op: k
        return 0;
      }
      break;
    }
    case AVR::STSKRrTiny: {
      switch (OpNum) {
      case 1:
        // op: rd
        return 4;
      case 0:
        // op: k
        return 0;
      }
      break;
    }
    case AVR::LDRdPtrPd:
    case AVR::LDRdPtrPi: {
      switch (OpNum) {
      case 2:
        // op: ptrreg
        return 2;
      case 0:
        // op: reg
        return 4;
      }
      break;
    }
  }
  std::string msg;
  raw_string_ostream Msg(msg);
  Msg << "Not supported instr[opcode]: " << MI << "[" << OpNum << "]";
  report_fatal_error(Msg.str().c_str());
}

#endif // GET_OPERAND_BIT_OFFSET