llvm/lib/Target/BPF/BPFGenInstrInfo.inc

/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
|*                                                                            *|
|* Target Instruction Enum Values and Descriptors                             *|
|*                                                                            *|
|* Automatically generated file, do not edit!                                 *|
|*                                                                            *|
\*===----------------------------------------------------------------------===*/

#ifdef GET_INSTRINFO_ENUM
#undef GET_INSTRINFO_ENUM
namespace llvm {

namespace BPF {
  enum { … };

} // end namespace BPF
} // end namespace llvm
#endif // GET_INSTRINFO_ENUM

#ifdef GET_INSTRINFO_SCHED_ENUM
#undef GET_INSTRINFO_SCHED_ENUM
namespace llvm {

namespace BPF {
namespace Sched {
  enum {
    NoInstrModel	= 0,
    SCHED_LIST_END = 1
  };
} // end namespace Sched
} // end namespace BPF
} // end namespace llvm
#endif // GET_INSTRINFO_SCHED_ENUM

#if defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
namespace llvm {

struct BPFInstrTable {
  MCInstrDesc Insts[487];
  static_assert(alignof(MCInstrDesc) >= alignof(MCOperandInfo), "Unwanted padding between Insts and OperandInfo");
  MCOperandInfo OperandInfo[288];
  static_assert(alignof(MCOperandInfo) >= alignof(MCPhysReg), "Unwanted padding between OperandInfo and ImplicitOps");
  MCPhysReg ImplicitOps[14];
};

} // end namespace llvm
#endif // defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)

#ifdef GET_INSTRINFO_MC_DESC
#undef GET_INSTRINFO_MC_DESC
namespace llvm {

static_assert(sizeof(MCOperandInfo) % sizeof(MCPhysReg) == 0);
static constexpr unsigned BPFImpOpBase = sizeof BPFInstrTable::OperandInfo / (sizeof(MCPhysReg));

extern const BPFInstrTable BPFDescs = {
  {
    { 486,	4,	1,	8,	0,	0,	0,	BPFImpOpBase + 0,	280,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #486 = XXORW32
    { 485,	4,	1,	8,	0,	0,	0,	BPFImpOpBase + 0,	276,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #485 = XXORD
    { 484,	3,	1,	8,	0,	0,	0,	BPFImpOpBase + 0,	216,	0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #484 = XOR_rr_32
    { 483,	3,	1,	8,	0,	0,	0,	BPFImpOpBase + 0,	213,	0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #483 = XOR_rr
    { 482,	3,	1,	8,	0,	0,	0,	BPFImpOpBase + 0,	210,	0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #482 = XOR_ri_32
    { 481,	3,	1,	8,	0,	0,	0,	BPFImpOpBase + 0,	207,	0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #481 = XOR_ri
    { 480,	4,	1,	8,	0,	0,	0,	BPFImpOpBase + 0,	280,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #480 = XORW32
    { 479,	4,	1,	8,	0,	0,	0,	BPFImpOpBase + 0,	276,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #479 = XORD
    { 478,	4,	1,	8,	0,	0,	0,	BPFImpOpBase + 0,	284,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #478 = XFXORW32
    { 477,	4,	1,	8,	0,	0,	0,	BPFImpOpBase + 0,	276,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #477 = XFXORD
    { 476,	4,	1,	8,	0,	0,	0,	BPFImpOpBase + 0,	284,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #476 = XFORW32
    { 475,	4,	1,	8,	0,	0,	0,	BPFImpOpBase + 0,	276,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #475 = XFORD
    { 474,	4,	1,	8,	0,	0,	0,	BPFImpOpBase + 0,	284,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #474 = XFANDW32
    { 473,	4,	1,	8,	0,	0,	0,	BPFImpOpBase + 0,	276,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #473 = XFANDD
    { 472,	4,	1,	8,	0,	0,	0,	BPFImpOpBase + 0,	284,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #472 = XFADDW32
    { 471,	4,	1,	8,	0,	0,	0,	BPFImpOpBase + 0,	276,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #471 = XFADDD
    { 470,	4,	1,	8,	0,	0,	0,	BPFImpOpBase + 0,	284,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #470 = XCHGW32
    { 469,	4,	1,	8,	0,	0,	0,	BPFImpOpBase + 0,	276,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #469 = XCHGD
    { 468,	4,	1,	8,	0,	0,	0,	BPFImpOpBase + 0,	280,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #468 = XANDW32
    { 467,	4,	1,	8,	0,	0,	0,	BPFImpOpBase + 0,	276,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #467 = XANDD
    { 466,	4,	1,	8,	0,	0,	0,	BPFImpOpBase + 0,	280,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #466 = XADDW32
    { 465,	4,	1,	8,	0,	0,	0,	BPFImpOpBase + 0,	276,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #465 = XADDW
    { 464,	4,	1,	8,	0,	0,	0,	BPFImpOpBase + 0,	276,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #464 = XADDD
    { 463,	3,	1,	8,	0,	0,	0,	BPFImpOpBase + 0,	216,	0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #463 = SUB_rr_32
    { 462,	3,	1,	8,	0,	0,	0,	BPFImpOpBase + 0,	213,	0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #462 = SUB_rr
    { 461,	3,	1,	8,	0,	0,	0,	BPFImpOpBase + 0,	210,	0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #461 = SUB_ri_32
    { 460,	3,	1,	8,	0,	0,	0,	BPFImpOpBase + 0,	207,	0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #460 = SUB_ri
    { 459,	3,	0,	8,	0,	0,	0,	BPFImpOpBase + 0,	273,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #459 = STW_imm
    { 458,	3,	0,	8,	0,	0,	0,	BPFImpOpBase + 0,	256,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #458 = STW32
    { 457,	3,	0,	8,	0,	0,	0,	BPFImpOpBase + 0,	152,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #457 = STW
    { 456,	3,	0,	8,	0,	0,	0,	BPFImpOpBase + 0,	273,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #456 = STH_imm
    { 455,	3,	0,	8,	0,	0,	0,	BPFImpOpBase + 0,	256,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #455 = STH32
    { 454,	3,	0,	8,	0,	0,	0,	BPFImpOpBase + 0,	152,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #454 = STH
    { 453,	3,	0,	8,	0,	0,	0,	BPFImpOpBase + 0,	273,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #453 = STD_imm
    { 452,	3,	0,	8,	0,	0,	0,	BPFImpOpBase + 0,	152,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #452 = STD
    { 451,	3,	0,	8,	0,	0,	0,	BPFImpOpBase + 0,	273,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #451 = STB_imm
    { 450,	3,	0,	8,	0,	0,	0,	BPFImpOpBase + 0,	256,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #450 = STB32
    { 449,	3,	0,	8,	0,	0,	0,	BPFImpOpBase + 0,	152,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #449 = STB
    { 448,	3,	1,	8,	0,	0,	0,	BPFImpOpBase + 0,	216,	0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #448 = SRL_rr_32
    { 447,	3,	1,	8,	0,	0,	0,	BPFImpOpBase + 0,	213,	0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #447 = SRL_rr
    { 446,	3,	1,	8,	0,	0,	0,	BPFImpOpBase + 0,	210,	0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #446 = SRL_ri_32
    { 445,	3,	1,	8,	0,	0,	0,	BPFImpOpBase + 0,	207,	0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #445 = SRL_ri
    { 444,	3,	1,	8,	0,	0,	0,	BPFImpOpBase + 0,	216,	0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #444 = SRA_rr_32
    { 443,	3,	1,	8,	0,	0,	0,	BPFImpOpBase + 0,	213,	0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #443 = SRA_rr
    { 442,	3,	1,	8,	0,	0,	0,	BPFImpOpBase + 0,	210,	0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #442 = SRA_ri_32
    { 441,	3,	1,	8,	0,	0,	0,	BPFImpOpBase + 0,	207,	0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #441 = SRA_ri
    { 440,	3,	1,	8,	0,	0,	0,	BPFImpOpBase + 0,	216,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #440 = SMOD_rr_32
    { 439,	3,	1,	8,	0,	0,	0,	BPFImpOpBase + 0,	213,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #439 = SMOD_rr
    { 438,	3,	1,	8,	0,	0,	0,	BPFImpOpBase + 0,	210,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #438 = SMOD_ri_32
    { 437,	3,	1,	8,	0,	0,	0,	BPFImpOpBase + 0,	207,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #437 = SMOD_ri
    { 436,	3,	1,	8,	0,	0,	0,	BPFImpOpBase + 0,	216,	0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #436 = SLL_rr_32
    { 435,	3,	1,	8,	0,	0,	0,	BPFImpOpBase + 0,	213,	0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #435 = SLL_rr
    { 434,	3,	1,	8,	0,	0,	0,	BPFImpOpBase + 0,	210,	0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #434 = SLL_ri_32
    { 433,	3,	1,	8,	0,	0,	0,	BPFImpOpBase + 0,	207,	0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #433 = SLL_ri
    { 432,	3,	1,	8,	0,	0,	0,	BPFImpOpBase + 0,	216,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #432 = SDIV_rr_32
    { 431,	3,	1,	8,	0,	0,	0,	BPFImpOpBase + 0,	213,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #431 = SDIV_rr
    { 430,	3,	1,	8,	0,	0,	0,	BPFImpOpBase + 0,	210,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #430 = SDIV_ri_32
    { 429,	3,	1,	8,	0,	0,	0,	BPFImpOpBase + 0,	207,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #429 = SDIV_ri
    { 428,	0,	0,	8,	0,	0,	0,	BPFImpOpBase + 0,	1,	0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #428 = RET
    { 427,	3,	1,	8,	0,	0,	0,	BPFImpOpBase + 0,	216,	0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #427 = OR_rr_32
    { 426,	3,	1,	8,	0,	0,	0,	BPFImpOpBase + 0,	213,	0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #426 = OR_rr
    { 425,	3,	1,	8,	0,	0,	0,	BPFImpOpBase + 0,	210,	0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #425 = OR_ri_32
    { 424,	3,	1,	8,	0,	0,	0,	BPFImpOpBase + 0,	207,	0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #424 = OR_ri
    { 423,	1,	0,	8,	0,	0,	0,	BPFImpOpBase + 0,	1,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #423 = NOP
    { 422,	2,	1,	8,	0,	0,	0,	BPFImpOpBase + 0,	219,	0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #422 = NEG_64
    { 421,	2,	1,	8,	0,	0,	0,	BPFImpOpBase + 0,	271,	0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #421 = NEG_32
    { 420,	3,	1,	8,	0,	0,	0,	BPFImpOpBase + 0,	216,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #420 = MUL_rr_32
    { 419,	3,	1,	8,	0,	0,	0,	BPFImpOpBase + 0,	213,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #419 = MUL_rr
    { 418,	3,	1,	8,	0,	0,	0,	BPFImpOpBase + 0,	210,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #418 = MUL_ri_32
    { 417,	3,	1,	8,	0,	0,	0,	BPFImpOpBase + 0,	207,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #417 = MUL_ri
    { 416,	2,	1,	8,	0,	0,	0,	BPFImpOpBase + 0,	265,	0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #416 = MOV_rr_32
    { 415,	2,	1,	8,	0,	0,	0,	BPFImpOpBase + 0,	261,	0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #415 = MOV_rr
    { 414,	2,	1,	8,	0,	0,	0,	BPFImpOpBase + 0,	269,	0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #414 = MOV_ri_32
    { 413,	2,	1,	8,	0,	0,	0,	BPFImpOpBase + 0,	259,	0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #413 = MOV_ri
    { 412,	2,	1,	8,	0,	0,	0,	BPFImpOpBase + 0,	267,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #412 = MOV_32_64
    { 411,	2,	1,	8,	0,	0,	0,	BPFImpOpBase + 0,	261,	0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #411 = MOVSX_rr_8
    { 410,	2,	1,	8,	0,	0,	0,	BPFImpOpBase + 0,	265,	0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #410 = MOVSX_rr_32_8
    { 409,	2,	1,	8,	0,	0,	0,	BPFImpOpBase + 0,	265,	0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #409 = MOVSX_rr_32_16
    { 408,	2,	1,	8,	0,	0,	0,	BPFImpOpBase + 0,	261,	0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #408 = MOVSX_rr_32
    { 407,	2,	1,	8,	0,	0,	0,	BPFImpOpBase + 0,	261,	0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #407 = MOVSX_rr_16
    { 406,	3,	1,	8,	0,	0,	0,	BPFImpOpBase + 0,	216,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #406 = MOD_rr_32
    { 405,	3,	1,	8,	0,	0,	0,	BPFImpOpBase + 0,	213,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #405 = MOD_rr
    { 404,	3,	1,	8,	0,	0,	0,	BPFImpOpBase + 0,	210,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #404 = MOD_ri_32
    { 403,	3,	1,	8,	0,	0,	0,	BPFImpOpBase + 0,	207,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #403 = MOD_ri
    { 402,	2,	1,	8,	0,	0,	0,	BPFImpOpBase + 0,	219,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #402 = LE64
    { 401,	2,	1,	8,	0,	0,	0,	BPFImpOpBase + 0,	219,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #401 = LE32
    { 400,	2,	1,	8,	0,	0,	0,	BPFImpOpBase + 0,	219,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #400 = LE16
    { 399,	3,	1,	8,	0,	0,	0,	BPFImpOpBase + 0,	244,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #399 = LD_pseudo
    { 398,	2,	1,	8,	0,	0,	0,	BPFImpOpBase + 0,	263,	0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #398 = LD_imm64
    { 397,	2,	0,	8,	0,	1,	6,	BPFImpOpBase + 7,	261,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #397 = LD_IND_W
    { 396,	2,	0,	8,	0,	1,	6,	BPFImpOpBase + 7,	261,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #396 = LD_IND_H
    { 395,	2,	0,	8,	0,	1,	6,	BPFImpOpBase + 7,	261,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #395 = LD_IND_B
    { 394,	2,	0,	8,	0,	1,	6,	BPFImpOpBase + 7,	259,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #394 = LD_ABS_W
    { 393,	2,	0,	8,	0,	1,	6,	BPFImpOpBase + 7,	259,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #393 = LD_ABS_H
    { 392,	2,	0,	8,	0,	1,	6,	BPFImpOpBase + 7,	259,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #392 = LD_ABS_B
    { 391,	3,	1,	8,	0,	0,	0,	BPFImpOpBase + 0,	152,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #391 = LDWSX
    { 390,	3,	1,	8,	0,	0,	0,	BPFImpOpBase + 0,	256,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #390 = LDW32
    { 389,	3,	1,	8,	0,	0,	0,	BPFImpOpBase + 0,	152,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #389 = LDW
    { 388,	3,	1,	8,	0,	0,	0,	BPFImpOpBase + 0,	152,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #388 = LDHSX
    { 387,	3,	1,	8,	0,	0,	0,	BPFImpOpBase + 0,	256,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #387 = LDH32
    { 386,	3,	1,	8,	0,	0,	0,	BPFImpOpBase + 0,	152,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #386 = LDH
    { 385,	3,	1,	8,	0,	0,	0,	BPFImpOpBase + 0,	152,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #385 = LDD
    { 384,	3,	1,	8,	0,	0,	0,	BPFImpOpBase + 0,	152,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #384 = LDBSX
    { 383,	3,	1,	8,	0,	0,	0,	BPFImpOpBase + 0,	256,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #383 = LDB32
    { 382,	3,	1,	8,	0,	0,	0,	BPFImpOpBase + 0,	152,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #382 = LDB
    { 381,	3,	0,	8,	0,	0,	0,	BPFImpOpBase + 0,	253,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #381 = JULT_rr_32
    { 380,	3,	0,	8,	0,	0,	0,	BPFImpOpBase + 0,	250,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #380 = JULT_rr
    { 379,	3,	0,	8,	0,	0,	0,	BPFImpOpBase + 0,	247,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #379 = JULT_ri_32
    { 378,	3,	0,	8,	0,	0,	0,	BPFImpOpBase + 0,	244,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #378 = JULT_ri
    { 377,	3,	0,	8,	0,	0,	0,	BPFImpOpBase + 0,	253,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #377 = JULE_rr_32
    { 376,	3,	0,	8,	0,	0,	0,	BPFImpOpBase + 0,	250,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #376 = JULE_rr
    { 375,	3,	0,	8,	0,	0,	0,	BPFImpOpBase + 0,	247,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #375 = JULE_ri_32
    { 374,	3,	0,	8,	0,	0,	0,	BPFImpOpBase + 0,	244,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #374 = JULE_ri
    { 373,	3,	0,	8,	0,	0,	0,	BPFImpOpBase + 0,	253,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #373 = JUGT_rr_32
    { 372,	3,	0,	8,	0,	0,	0,	BPFImpOpBase + 0,	250,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #372 = JUGT_rr
    { 371,	3,	0,	8,	0,	0,	0,	BPFImpOpBase + 0,	247,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #371 = JUGT_ri_32
    { 370,	3,	0,	8,	0,	0,	0,	BPFImpOpBase + 0,	244,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #370 = JUGT_ri
    { 369,	3,	0,	8,	0,	0,	0,	BPFImpOpBase + 0,	253,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #369 = JUGE_rr_32
    { 368,	3,	0,	8,	0,	0,	0,	BPFImpOpBase + 0,	250,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #368 = JUGE_rr
    { 367,	3,	0,	8,	0,	0,	0,	BPFImpOpBase + 0,	247,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #367 = JUGE_ri_32
    { 366,	3,	0,	8,	0,	0,	0,	BPFImpOpBase + 0,	244,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #366 = JUGE_ri
    { 365,	3,	0,	8,	0,	0,	0,	BPFImpOpBase + 0,	253,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #365 = JSLT_rr_32
    { 364,	3,	0,	8,	0,	0,	0,	BPFImpOpBase + 0,	250,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #364 = JSLT_rr
    { 363,	3,	0,	8,	0,	0,	0,	BPFImpOpBase + 0,	247,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #363 = JSLT_ri_32
    { 362,	3,	0,	8,	0,	0,	0,	BPFImpOpBase + 0,	244,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #362 = JSLT_ri
    { 361,	3,	0,	8,	0,	0,	0,	BPFImpOpBase + 0,	253,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #361 = JSLE_rr_32
    { 360,	3,	0,	8,	0,	0,	0,	BPFImpOpBase + 0,	250,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #360 = JSLE_rr
    { 359,	3,	0,	8,	0,	0,	0,	BPFImpOpBase + 0,	247,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #359 = JSLE_ri_32
    { 358,	3,	0,	8,	0,	0,	0,	BPFImpOpBase + 0,	244,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #358 = JSLE_ri
    { 357,	3,	0,	8,	0,	0,	0,	BPFImpOpBase + 0,	253,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #357 = JSGT_rr_32
    { 356,	3,	0,	8,	0,	0,	0,	BPFImpOpBase + 0,	250,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #356 = JSGT_rr
    { 355,	3,	0,	8,	0,	0,	0,	BPFImpOpBase + 0,	247,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #355 = JSGT_ri_32
    { 354,	3,	0,	8,	0,	0,	0,	BPFImpOpBase + 0,	244,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #354 = JSGT_ri
    { 353,	3,	0,	8,	0,	0,	0,	BPFImpOpBase + 0,	253,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #353 = JSGE_rr_32
    { 352,	3,	0,	8,	0,	0,	0,	BPFImpOpBase + 0,	250,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #352 = JSGE_rr
    { 351,	3,	0,	8,	0,	0,	0,	BPFImpOpBase + 0,	247,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #351 = JSGE_ri_32
    { 350,	3,	0,	8,	0,	0,	0,	BPFImpOpBase + 0,	244,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #350 = JSGE_ri
    { 349,	3,	0,	8,	0,	0,	0,	BPFImpOpBase + 0,	253,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #349 = JSET_rr_32
    { 348,	3,	0,	8,	0,	0,	0,	BPFImpOpBase + 0,	250,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #348 = JSET_rr
    { 347,	3,	0,	8,	0,	0,	0,	BPFImpOpBase + 0,	247,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #347 = JSET_ri_32
    { 346,	3,	0,	8,	0,	0,	0,	BPFImpOpBase + 0,	244,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #346 = JSET_ri
    { 345,	3,	0,	8,	0,	0,	0,	BPFImpOpBase + 0,	253,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #345 = JNE_rr_32
    { 344,	3,	0,	8,	0,	0,	0,	BPFImpOpBase + 0,	250,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #344 = JNE_rr
    { 343,	3,	0,	8,	0,	0,	0,	BPFImpOpBase + 0,	247,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #343 = JNE_ri_32
    { 342,	3,	0,	8,	0,	0,	0,	BPFImpOpBase + 0,	244,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #342 = JNE_ri
    { 341,	1,	0,	8,	0,	0,	0,	BPFImpOpBase + 0,	0,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #341 = JMPL
    { 340,	1,	0,	8,	0,	0,	0,	BPFImpOpBase + 0,	0,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #340 = JMP
    { 339,	3,	0,	8,	0,	0,	0,	BPFImpOpBase + 0,	253,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #339 = JEQ_rr_32
    { 338,	3,	0,	8,	0,	0,	0,	BPFImpOpBase + 0,	250,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #338 = JEQ_rr
    { 337,	3,	0,	8,	0,	0,	0,	BPFImpOpBase + 0,	247,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #337 = JEQ_ri_32
    { 336,	3,	0,	8,	0,	0,	0,	BPFImpOpBase + 0,	244,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #336 = JEQ_ri
    { 335,	1,	0,	8,	0,	0,	0,	BPFImpOpBase + 0,	0,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #335 = JCOND
    { 334,	1,	0,	8,	0,	1,	0,	BPFImpOpBase + 6,	243,	0|(1ULL<<MCID::Call)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #334 = JALX
    { 333,	1,	0,	8,	0,	1,	0,	BPFImpOpBase + 6,	0,	0|(1ULL<<MCID::Call)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #333 = JAL
    { 332,	3,	1,	8,	0,	0,	0,	BPFImpOpBase + 0,	216,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #332 = DIV_rr_32
    { 331,	3,	1,	8,	0,	0,	0,	BPFImpOpBase + 0,	213,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #331 = DIV_rr
    { 330,	3,	1,	8,	0,	0,	0,	BPFImpOpBase + 0,	210,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #330 = DIV_ri_32
    { 329,	3,	1,	8,	0,	0,	0,	BPFImpOpBase + 0,	207,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #329 = DIV_ri
    { 328,	4,	0,	8,	0,	0,	0,	BPFImpOpBase + 0,	239,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #328 = CORE_ST
    { 327,	4,	1,	8,	0,	0,	0,	BPFImpOpBase + 0,	235,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #327 = CORE_SHIFT
    { 326,	4,	1,	8,	0,	0,	0,	BPFImpOpBase + 0,	231,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #326 = CORE_LD64
    { 325,	4,	1,	8,	0,	0,	0,	BPFImpOpBase + 0,	227,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #325 = CORE_LD32
    { 324,	3,	0,	8,	0,	1,	1,	BPFImpOpBase + 4,	224,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #324 = CMPXCHGW32
    { 323,	3,	0,	8,	0,	1,	1,	BPFImpOpBase + 2,	221,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #323 = CMPXCHGD
    { 322,	2,	1,	8,	0,	0,	0,	BPFImpOpBase + 0,	219,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #322 = BSWAP64
    { 321,	2,	1,	8,	0,	0,	0,	BPFImpOpBase + 0,	219,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #321 = BSWAP32
    { 320,	2,	1,	8,	0,	0,	0,	BPFImpOpBase + 0,	219,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #320 = BSWAP16
    { 319,	2,	1,	8,	0,	0,	0,	BPFImpOpBase + 0,	219,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #319 = BE64
    { 318,	2,	1,	8,	0,	0,	0,	BPFImpOpBase + 0,	219,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #318 = BE32
    { 317,	2,	1,	8,	0,	0,	0,	BPFImpOpBase + 0,	219,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #317 = BE16
    { 316,	3,	1,	8,	0,	0,	0,	BPFImpOpBase + 0,	216,	0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #316 = AND_rr_32
    { 315,	3,	1,	8,	0,	0,	0,	BPFImpOpBase + 0,	213,	0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #315 = AND_rr
    { 314,	3,	1,	8,	0,	0,	0,	BPFImpOpBase + 0,	210,	0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #314 = AND_ri_32
    { 313,	3,	1,	8,	0,	0,	0,	BPFImpOpBase + 0,	207,	0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #313 = AND_ri
    { 312,	3,	1,	8,	0,	0,	0,	BPFImpOpBase + 0,	216,	0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #312 = ADD_rr_32
    { 311,	3,	1,	8,	0,	0,	0,	BPFImpOpBase + 0,	213,	0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #311 = ADD_rr
    { 310,	3,	1,	8,	0,	0,	0,	BPFImpOpBase + 0,	210,	0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #310 = ADD_ri_32
    { 309,	3,	1,	8,	0,	0,	0,	BPFImpOpBase + 0,	207,	0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #309 = ADD_ri
    { 308,	4,	1,	8,	0,	0,	0,	BPFImpOpBase + 0,	155,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #308 = ADDR_SPACE_CAST
    { 307,	6,	1,	8,	0,	0,	0,	BPFImpOpBase + 0,	201,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #307 = Select_Ri_64_32
    { 306,	6,	1,	8,	0,	0,	0,	BPFImpOpBase + 0,	195,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #306 = Select_Ri_32_64
    { 305,	6,	1,	8,	0,	0,	0,	BPFImpOpBase + 0,	189,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #305 = Select_Ri_32
    { 304,	6,	1,	8,	0,	0,	0,	BPFImpOpBase + 0,	183,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #304 = Select_Ri
    { 303,	6,	1,	8,	0,	0,	0,	BPFImpOpBase + 0,	177,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #303 = Select_64_32
    { 302,	6,	1,	8,	0,	0,	0,	BPFImpOpBase + 0,	171,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #302 = Select_32_64
    { 301,	6,	1,	8,	0,	0,	0,	BPFImpOpBase + 0,	165,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #301 = Select_32
    { 300,	6,	1,	8,	0,	0,	0,	BPFImpOpBase + 0,	159,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #300 = Select
    { 299,	4,	0,	8,	0,	0,	0,	BPFImpOpBase + 0,	155,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #299 = MEMCPY
    { 298,	3,	1,	8,	0,	0,	0,	BPFImpOpBase + 0,	152,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #298 = FI_ri
    { 297,	2,	0,	8,	0,	1,	1,	BPFImpOpBase + 0,	21,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #297 = ADJCALLSTACKUP
    { 296,	2,	0,	8,	0,	1,	1,	BPFImpOpBase + 0,	21,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #296 = ADJCALLSTACKDOWN
    { 295,	4,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	148,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #295 = G_UBFX
    { 294,	4,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	148,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #294 = G_SBFX
    { 293,	2,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #293 = G_VECREDUCE_UMIN
    { 292,	2,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #292 = G_VECREDUCE_UMAX
    { 291,	2,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #291 = G_VECREDUCE_SMIN
    { 290,	2,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #290 = G_VECREDUCE_SMAX
    { 289,	2,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #289 = G_VECREDUCE_XOR
    { 288,	2,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #288 = G_VECREDUCE_OR
    { 287,	2,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #287 = G_VECREDUCE_AND
    { 286,	2,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #286 = G_VECREDUCE_MUL
    { 285,	2,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #285 = G_VECREDUCE_ADD
    { 284,	2,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #284 = G_VECREDUCE_FMINIMUM
    { 283,	2,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #283 = G_VECREDUCE_FMAXIMUM
    { 282,	2,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #282 = G_VECREDUCE_FMIN
    { 281,	2,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #281 = G_VECREDUCE_FMAX
    { 280,	2,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #280 = G_VECREDUCE_FMUL
    { 279,	2,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #279 = G_VECREDUCE_FADD
    { 278,	3,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	131,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #278 = G_VECREDUCE_SEQ_FMUL
    { 277,	3,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	131,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #277 = G_VECREDUCE_SEQ_FADD
    { 276,	1,	0,	0,	0,	0,	0,	BPFImpOpBase + 0,	1,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #276 = G_UBSANTRAP
    { 275,	0,	0,	0,	0,	0,	0,	BPFImpOpBase + 0,	1,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #275 = G_DEBUGTRAP
    { 274,	0,	0,	0,	0,	0,	0,	BPFImpOpBase + 0,	1,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #274 = G_TRAP
    { 273,	3,	0,	0,	0,	0,	0,	BPFImpOpBase + 0,	58,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #273 = G_BZERO
    { 272,	4,	0,	0,	0,	0,	0,	BPFImpOpBase + 0,	144,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #272 = G_MEMSET
    { 271,	4,	0,	0,	0,	0,	0,	BPFImpOpBase + 0,	144,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #271 = G_MEMMOVE
    { 270,	3,	0,	0,	0,	0,	0,	BPFImpOpBase + 0,	131,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #270 = G_MEMCPY_INLINE
    { 269,	4,	0,	0,	0,	0,	0,	BPFImpOpBase + 0,	144,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #269 = G_MEMCPY
    { 268,	2,	0,	0,	0,	0,	0,	BPFImpOpBase + 0,	142,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL },  // Inst #268 = G_WRITE_REGISTER
    { 267,	2,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	51,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL },  // Inst #267 = G_READ_REGISTER
    { 266,	3,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	101,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #266 = G_STRICT_FLDEXP
    { 265,	2,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #265 = G_STRICT_FSQRT
    { 264,	4,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	46,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #264 = G_STRICT_FMA
    { 263,	3,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #263 = G_STRICT_FREM
    { 262,	3,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #262 = G_STRICT_FDIV
    { 261,	3,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #261 = G_STRICT_FMUL
    { 260,	3,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #260 = G_STRICT_FSUB
    { 259,	3,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #259 = G_STRICT_FADD
    { 258,	1,	0,	0,	0,	0,	0,	BPFImpOpBase + 0,	50,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #258 = G_STACKRESTORE
    { 257,	1,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	50,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #257 = G_STACKSAVE
    { 256,	3,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	69,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #256 = G_DYN_STACKALLOC
    { 255,	2,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	51,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #255 = G_JUMP_TABLE
    { 254,	2,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	51,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #254 = G_BLOCK_ADDR
    { 253,	2,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #253 = G_ADDRSPACE_CAST
    { 252,	2,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #252 = G_FNEARBYINT
    { 251,	2,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #251 = G_FRINT
    { 250,	2,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #250 = G_FFLOOR
    { 249,	2,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #249 = G_FSQRT
    { 248,	2,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #248 = G_FTANH
    { 247,	2,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #247 = G_FSINH
    { 246,	2,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #246 = G_FCOSH
    { 245,	2,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #245 = G_FATAN
    { 244,	2,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #244 = G_FASIN
    { 243,	2,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #243 = G_FACOS
    { 242,	2,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #242 = G_FTAN
    { 241,	2,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #241 = G_FSIN
    { 240,	2,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #240 = G_FCOS
    { 239,	2,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #239 = G_FCEIL
    { 238,	2,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #238 = G_BITREVERSE
    { 237,	2,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #237 = G_BSWAP
    { 236,	2,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #236 = G_CTPOP
    { 235,	2,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #235 = G_CTLZ_ZERO_UNDEF
    { 234,	2,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #234 = G_CTLZ
    { 233,	2,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #233 = G_CTTZ_ZERO_UNDEF
    { 232,	2,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #232 = G_CTTZ
    { 231,	4,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	138,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #231 = G_VECTOR_COMPRESS
    { 230,	2,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #230 = G_SPLAT_VECTOR
    { 229,	4,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	134,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #229 = G_SHUFFLE_VECTOR
    { 228,	3,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	131,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #228 = G_EXTRACT_VECTOR_ELT
    { 227,	4,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	127,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #227 = G_INSERT_VECTOR_ELT
    { 226,	3,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	40,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #226 = G_EXTRACT_SUBVECTOR
    { 225,	4,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	63,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #225 = G_INSERT_SUBVECTOR
    { 224,	2,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	51,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #224 = G_VSCALE
    { 223,	3,	0,	0,	0,	0,	0,	BPFImpOpBase + 0,	124,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #223 = G_BRJT
    { 222,	1,	0,	0,	0,	0,	0,	BPFImpOpBase + 0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #222 = G_BR
    { 221,	2,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #221 = G_LLROUND
    { 220,	2,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #220 = G_LROUND
    { 219,	2,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #219 = G_ABS
    { 218,	3,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #218 = G_UMAX
    { 217,	3,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #217 = G_UMIN
    { 216,	3,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #216 = G_SMAX
    { 215,	3,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #215 = G_SMIN
    { 214,	3,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	101,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #214 = G_PTRMASK
    { 213,	3,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	101,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #213 = G_PTR_ADD
    { 212,	0,	0,	0,	0,	0,	0,	BPFImpOpBase + 0,	1,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #212 = G_RESET_FPMODE
    { 211,	1,	0,	0,	0,	0,	0,	BPFImpOpBase + 0,	50,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #211 = G_SET_FPMODE
    { 210,	1,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	50,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #210 = G_GET_FPMODE
    { 209,	0,	0,	0,	0,	0,	0,	BPFImpOpBase + 0,	1,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #209 = G_RESET_FPENV
    { 208,	1,	0,	0,	0,	0,	0,	BPFImpOpBase + 0,	50,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #208 = G_SET_FPENV
    { 207,	1,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	50,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #207 = G_GET_FPENV
    { 206,	3,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #206 = G_FMAXIMUM
    { 205,	3,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #205 = G_FMINIMUM
    { 204,	3,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #204 = G_FMAXNUM_IEEE
    { 203,	3,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #203 = G_FMINNUM_IEEE
    { 202,	3,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #202 = G_FMAXNUM
    { 201,	3,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #201 = G_FMINNUM
    { 200,	2,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #200 = G_FCANONICALIZE
    { 199,	3,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	98,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #199 = G_IS_FPCLASS
    { 198,	3,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	101,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #198 = G_FCOPYSIGN
    { 197,	2,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #197 = G_FABS
    { 196,	2,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #196 = G_UITOFP
    { 195,	2,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #195 = G_SITOFP
    { 194,	2,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #194 = G_FPTOUI
    { 193,	2,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #193 = G_FPTOSI
    { 192,	2,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #192 = G_FPTRUNC
    { 191,	2,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #191 = G_FPEXT
    { 190,	2,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #190 = G_FNEG
    { 189,	3,	2,	0,	0,	0,	0,	BPFImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #189 = G_FFREXP
    { 188,	3,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	101,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #188 = G_FLDEXP
    { 187,	2,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #187 = G_FLOG10
    { 186,	2,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #186 = G_FLOG2
    { 185,	2,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #185 = G_FLOG
    { 184,	2,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #184 = G_FEXP10
    { 183,	2,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #183 = G_FEXP2
    { 182,	2,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #182 = G_FEXP
    { 181,	3,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	101,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #181 = G_FPOWI
    { 180,	3,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #180 = G_FPOW
    { 179,	3,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #179 = G_FREM
    { 178,	3,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #178 = G_FDIV
    { 177,	4,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	46,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #177 = G_FMAD
    { 176,	4,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	46,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #176 = G_FMA
    { 175,	3,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #175 = G_FMUL
    { 174,	3,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #174 = G_FSUB
    { 173,	3,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #173 = G_FADD
    { 172,	4,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	120,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #172 = G_UDIVFIXSAT
    { 171,	4,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	120,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #171 = G_SDIVFIXSAT
    { 170,	4,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	120,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #170 = G_UDIVFIX
    { 169,	4,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	120,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #169 = G_SDIVFIX
    { 168,	4,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	120,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #168 = G_UMULFIXSAT
    { 167,	4,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	120,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #167 = G_SMULFIXSAT
    { 166,	4,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	120,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #166 = G_UMULFIX
    { 165,	4,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	120,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #165 = G_SMULFIX
    { 164,	3,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	101,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #164 = G_SSHLSAT
    { 163,	3,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	101,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #163 = G_USHLSAT
    { 162,	3,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #162 = G_SSUBSAT
    { 161,	3,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #161 = G_USUBSAT
    { 160,	3,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #160 = G_SADDSAT
    { 159,	3,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #159 = G_UADDSAT
    { 158,	3,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #158 = G_SMULH
    { 157,	3,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #157 = G_UMULH
    { 156,	4,	2,	0,	0,	0,	0,	BPFImpOpBase + 0,	87,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #156 = G_SMULO
    { 155,	4,	2,	0,	0,	0,	0,	BPFImpOpBase + 0,	87,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #155 = G_UMULO
    { 154,	5,	2,	0,	0,	0,	0,	BPFImpOpBase + 0,	115,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #154 = G_SSUBE
    { 153,	4,	2,	0,	0,	0,	0,	BPFImpOpBase + 0,	87,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #153 = G_SSUBO
    { 152,	5,	2,	0,	0,	0,	0,	BPFImpOpBase + 0,	115,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #152 = G_SADDE
    { 151,	4,	2,	0,	0,	0,	0,	BPFImpOpBase + 0,	87,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #151 = G_SADDO
    { 150,	5,	2,	0,	0,	0,	0,	BPFImpOpBase + 0,	115,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #150 = G_USUBE
    { 149,	4,	2,	0,	0,	0,	0,	BPFImpOpBase + 0,	87,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #149 = G_USUBO
    { 148,	5,	2,	0,	0,	0,	0,	BPFImpOpBase + 0,	115,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #148 = G_UADDE
    { 147,	4,	2,	0,	0,	0,	0,	BPFImpOpBase + 0,	87,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #147 = G_UADDO
    { 146,	4,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	87,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #146 = G_SELECT
    { 145,	3,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	112,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #145 = G_UCMP
    { 144,	3,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	112,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #144 = G_SCMP
    { 143,	4,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	108,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #143 = G_FCMP
    { 142,	4,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	108,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #142 = G_ICMP
    { 141,	3,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	101,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #141 = G_ROTL
    { 140,	3,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	101,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #140 = G_ROTR
    { 139,	4,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	104,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #139 = G_FSHR
    { 138,	4,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	104,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #138 = G_FSHL
    { 137,	3,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	101,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #137 = G_ASHR
    { 136,	3,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	101,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #136 = G_LSHR
    { 135,	3,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	101,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #135 = G_SHL
    { 134,	2,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #134 = G_ZEXT
    { 133,	3,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	40,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #133 = G_SEXT_INREG
    { 132,	2,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #132 = G_SEXT
    { 131,	3,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	98,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #131 = G_VAARG
    { 130,	1,	0,	0,	0,	0,	0,	BPFImpOpBase + 0,	50,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #130 = G_VASTART
    { 129,	2,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	51,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #129 = G_FCONSTANT
    { 128,	2,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	51,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #128 = G_CONSTANT
    { 127,	2,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #127 = G_TRUNC
    { 126,	2,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #126 = G_ANYEXT
    { 125,	1,	0,	0,	0,	0,	0,	BPFImpOpBase + 0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL },  // Inst #125 = G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
    { 124,	1,	0,	0,	0,	0,	0,	BPFImpOpBase + 0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL },  // Inst #124 = G_INTRINSIC_CONVERGENT
    { 123,	1,	0,	0,	0,	0,	0,	BPFImpOpBase + 0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #123 = G_INTRINSIC_W_SIDE_EFFECTS
    { 122,	1,	0,	0,	0,	0,	0,	BPFImpOpBase + 0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #122 = G_INTRINSIC
    { 121,	0,	0,	0,	0,	0,	0,	BPFImpOpBase + 0,	1,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #121 = G_INVOKE_REGION_START
    { 120,	1,	0,	0,	0,	0,	0,	BPFImpOpBase + 0,	50,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #120 = G_BRINDIRECT
    { 119,	2,	0,	0,	0,	0,	0,	BPFImpOpBase + 0,	51,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #119 = G_BRCOND
    { 118,	4,	0,	0,	0,	0,	0,	BPFImpOpBase + 0,	94,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #118 = G_PREFETCH
    { 117,	2,	0,	0,	0,	0,	0,	BPFImpOpBase + 0,	21,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #117 = G_FENCE
    { 116,	3,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #116 = G_ATOMICRMW_UDEC_WRAP
    { 115,	3,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #115 = G_ATOMICRMW_UINC_WRAP
    { 114,	3,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #114 = G_ATOMICRMW_FMIN
    { 113,	3,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #113 = G_ATOMICRMW_FMAX
    { 112,	3,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #112 = G_ATOMICRMW_FSUB
    { 111,	3,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #111 = G_ATOMICRMW_FADD
    { 110,	3,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #110 = G_ATOMICRMW_UMIN
    { 109,	3,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #109 = G_ATOMICRMW_UMAX
    { 108,	3,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #108 = G_ATOMICRMW_MIN
    { 107,	3,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #107 = G_ATOMICRMW_MAX
    { 106,	3,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #106 = G_ATOMICRMW_XOR
    { 105,	3,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #105 = G_ATOMICRMW_OR
    { 104,	3,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #104 = G_ATOMICRMW_NAND
    { 103,	3,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #103 = G_ATOMICRMW_AND
    { 102,	3,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #102 = G_ATOMICRMW_SUB
    { 101,	3,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #101 = G_ATOMICRMW_ADD
    { 100,	3,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #100 = G_ATOMICRMW_XCHG
    { 99,	4,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	87,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #99 = G_ATOMIC_CMPXCHG
    { 98,	5,	2,	0,	0,	0,	0,	BPFImpOpBase + 0,	82,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #98 = G_ATOMIC_CMPXCHG_WITH_SUCCESS
    { 97,	5,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	77,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #97 = G_INDEXED_STORE
    { 96,	2,	0,	0,	0,	0,	0,	BPFImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #96 = G_STORE
    { 95,	5,	2,	0,	0,	0,	0,	BPFImpOpBase + 0,	72,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #95 = G_INDEXED_ZEXTLOAD
    { 94,	5,	2,	0,	0,	0,	0,	BPFImpOpBase + 0,	72,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #94 = G_INDEXED_SEXTLOAD
    { 93,	5,	2,	0,	0,	0,	0,	BPFImpOpBase + 0,	72,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #93 = G_INDEXED_LOAD
    { 92,	2,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #92 = G_ZEXTLOAD
    { 91,	2,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #91 = G_SEXTLOAD
    { 90,	2,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #90 = G_LOAD
    { 89,	1,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	50,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #89 = G_READSTEADYCOUNTER
    { 88,	1,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	50,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #88 = G_READCYCLECOUNTER
    { 87,	2,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #87 = G_INTRINSIC_ROUNDEVEN
    { 86,	2,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #86 = G_INTRINSIC_LLRINT
    { 85,	2,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #85 = G_INTRINSIC_LRINT
    { 84,	2,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #84 = G_INTRINSIC_ROUND
    { 83,	2,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #83 = G_INTRINSIC_TRUNC
    { 82,	3,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	69,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #82 = G_INTRINSIC_FPTRUNC_ROUND
    { 81,	2,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #81 = G_CONSTANT_FOLD_BARRIER
    { 80,	2,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #80 = G_FREEZE
    { 79,	2,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #79 = G_BITCAST
    { 78,	2,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #78 = G_INTTOPTR
    { 77,	2,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #77 = G_PTRTOINT
    { 76,	2,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #76 = G_CONCAT_VECTORS
    { 75,	2,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #75 = G_BUILD_VECTOR_TRUNC
    { 74,	2,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #74 = G_BUILD_VECTOR
    { 73,	2,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #73 = G_MERGE_VALUES
    { 72,	4,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	63,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #72 = G_INSERT
    { 71,	2,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #71 = G_UNMERGE_VALUES
    { 70,	3,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	58,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #70 = G_EXTRACT
    { 69,	2,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	51,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #69 = G_CONSTANT_POOL
    { 68,	5,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	53,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #68 = G_PTRAUTH_GLOBAL_VALUE
    { 67,	2,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	51,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #67 = G_GLOBAL_VALUE
    { 66,	2,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	51,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #66 = G_FRAME_INDEX
    { 65,	1,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	50,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #65 = G_PHI
    { 64,	1,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	50,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #64 = G_IMPLICIT_DEF
    { 63,	3,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #63 = G_XOR
    { 62,	3,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #62 = G_OR
    { 61,	3,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #61 = G_AND
    { 60,	4,	2,	0,	0,	0,	0,	BPFImpOpBase + 0,	46,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #60 = G_UDIVREM
    { 59,	4,	2,	0,	0,	0,	0,	BPFImpOpBase + 0,	46,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #59 = G_SDIVREM
    { 58,	3,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #58 = G_UREM
    { 57,	3,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #57 = G_SREM
    { 56,	3,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #56 = G_UDIV
    { 55,	3,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #55 = G_SDIV
    { 54,	3,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #54 = G_MUL
    { 53,	3,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #53 = G_SUB
    { 52,	3,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #52 = G_ADD
    { 51,	3,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	40,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #51 = G_ASSERT_ALIGN
    { 50,	3,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	40,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #50 = G_ASSERT_ZEXT
    { 49,	3,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	40,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #49 = G_ASSERT_SEXT
    { 48,	1,	0,	0,	0,	0,	0,	BPFImpOpBase + 0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL },  // Inst #48 = CONVERGENCECTRL_GLUE
    { 47,	2,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	13,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL },  // Inst #47 = CONVERGENCECTRL_LOOP
    { 46,	1,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL },  // Inst #46 = CONVERGENCECTRL_ANCHOR
    { 45,	1,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL },  // Inst #45 = CONVERGENCECTRL_ENTRY
    { 44,	1,	0,	0,	0,	0,	0,	BPFImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #44 = JUMP_TABLE_DEBUG_INFO
    { 43,	0,	0,	0,	0,	0,	0,	BPFImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #43 = MEMBARRIER
    { 42,	0,	0,	0,	0,	0,	0,	BPFImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #42 = FAKE_USE
    { 41,	0,	0,	0,	0,	0,	0,	BPFImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #41 = ICALL_BRANCH_FUNNEL
    { 40,	3,	0,	0,	0,	0,	0,	BPFImpOpBase + 0,	37,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #40 = PATCHABLE_TYPED_EVENT_CALL
    { 39,	2,	0,	0,	0,	0,	0,	BPFImpOpBase + 0,	35,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #39 = PATCHABLE_EVENT_CALL
    { 38,	0,	0,	0,	0,	0,	0,	BPFImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #38 = PATCHABLE_TAIL_CALL
    { 37,	0,	0,	0,	0,	0,	0,	BPFImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #37 = PATCHABLE_FUNCTION_EXIT
    { 36,	0,	0,	0,	0,	0,	0,	BPFImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #36 = PATCHABLE_RET
    { 35,	0,	0,	0,	0,	0,	0,	BPFImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #35 = PATCHABLE_FUNCTION_ENTER
    { 34,	0,	0,	0,	0,	0,	0,	BPFImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #34 = PATCHABLE_OP
    { 33,	1,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #33 = FAULTING_OP
    { 32,	2,	0,	0,	0,	0,	0,	BPFImpOpBase + 0,	33,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #32 = LOCAL_ESCAPE
    { 31,	0,	0,	0,	0,	0,	0,	BPFImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #31 = STATEPOINT
    { 30,	3,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	30,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #30 = PREALLOCATED_ARG
    { 29,	1,	0,	0,	0,	0,	0,	BPFImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #29 = PREALLOCATED_SETUP
    { 28,	1,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	29,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #28 = LOAD_STACK_GUARD
    { 27,	6,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	23,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #27 = PATCHPOINT
    { 26,	0,	0,	0,	0,	0,	0,	BPFImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #26 = FENTRY_CALL
    { 25,	2,	0,	0,	0,	0,	0,	BPFImpOpBase + 0,	21,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #25 = STACKMAP
    { 24,	2,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	19,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #24 = ARITH_FENCE
    { 23,	4,	0,	0,	0,	0,	0,	BPFImpOpBase + 0,	15,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #23 = PSEUDO_PROBE
    { 22,	1,	0,	0,	0,	0,	0,	BPFImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #22 = LIFETIME_END
    { 21,	1,	0,	0,	0,	0,	0,	BPFImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #21 = LIFETIME_START
    { 20,	0,	0,	0,	0,	0,	0,	BPFImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #20 = BUNDLE
    { 19,	2,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	13,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #19 = COPY
    { 18,	2,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	13,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #18 = REG_SEQUENCE
    { 17,	1,	0,	0,	0,	0,	0,	BPFImpOpBase + 0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #17 = DBG_LABEL
    { 16,	0,	0,	0,	0,	0,	0,	BPFImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #16 = DBG_PHI
    { 15,	0,	0,	0,	0,	0,	0,	BPFImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #15 = DBG_INSTR_REF
    { 14,	0,	0,	0,	0,	0,	0,	BPFImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #14 = DBG_VALUE_LIST
    { 13,	0,	0,	0,	0,	0,	0,	BPFImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #13 = DBG_VALUE
    { 12,	3,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #12 = COPY_TO_REGCLASS
    { 11,	4,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	9,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #11 = SUBREG_TO_REG
    { 10,	1,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #10 = IMPLICIT_DEF
    { 9,	4,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	5,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #9 = INSERT_SUBREG
    { 8,	3,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #8 = EXTRACT_SUBREG
    { 7,	0,	0,	0,	0,	0,	0,	BPFImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #7 = KILL
    { 6,	1,	0,	0,	0,	0,	0,	BPFImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #6 = ANNOTATION_LABEL
    { 5,	1,	0,	0,	0,	0,	0,	BPFImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #5 = GC_LABEL
    { 4,	1,	0,	0,	0,	0,	0,	BPFImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #4 = EH_LABEL
    { 3,	1,	0,	0,	0,	0,	0,	BPFImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #3 = CFI_INSTRUCTION
    { 2,	0,	0,	0,	0,	0,	0,	BPFImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #2 = INLINEASM_BR
    { 1,	0,	0,	0,	0,	0,	0,	BPFImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1 = INLINEASM
    { 0,	1,	1,	0,	0,	0,	0,	BPFImpOpBase + 0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #0 = PHI
  }, {
    /* 0 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 1 */
    /* 1 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 2 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 5 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 9 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 13 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 15 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 19 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) },
    /* 21 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 23 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 29 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 },
    /* 30 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 33 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 35 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 37 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 40 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
    /* 43 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
    /* 46 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
    /* 50 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
    /* 51 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 53 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 58 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
    /* 61 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
    /* 63 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
    /* 67 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
    /* 69 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 72 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 77 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 82 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
    /* 87 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
    /* 91 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
    /* 94 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 98 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 101 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
    /* 104 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
    /* 108 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
    /* 112 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
    /* 115 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
    /* 120 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
    /* 124 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
    /* 127 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
    /* 131 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
    /* 134 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 138 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
    /* 142 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
    /* 144 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
    /* 148 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
    /* 152 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 155 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 159 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 165 */ { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 171 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 177 */ { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 183 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 189 */ { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 195 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 201 */ { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 207 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 210 */ { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 213 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 216 */ { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 219 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
    /* 221 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 224 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 227 */ { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 231 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 235 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 239 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 243 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 244 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 247 */ { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 250 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 253 */ { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 256 */ { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 259 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 261 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 263 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 265 */ { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 267 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 269 */ { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 271 */ { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
    /* 273 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 276 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
    /* 280 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
    /* 284 */ { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
  }, {
    /* 0 */
    /* 0 */ BPF::R11, BPF::R11,
    /* 2 */ BPF::R0, BPF::R0,
    /* 4 */ BPF::W0, BPF::W0,
    /* 6 */ BPF::R11,
    /* 7 */ BPF::R6, BPF::R0, BPF::R1, BPF::R2, BPF::R3, BPF::R4, BPF::R5,
  }
};


#ifdef __GNUC__
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Woverlength-strings"
#endif
extern const char BPFInstrNameData[] = {
  /* 0 */ "G_FLOG10\0"
  /* 9 */ "G_FEXP10\0"
  /* 18 */ "LDB32\0"
  /* 24 */ "STB32\0"
  /* 30 */ "CORE_LD32\0"
  /* 40 */ "BE32\0"
  /* 45 */ "LE32\0"
  /* 50 */ "LDH32\0"
  /* 56 */ "STH32\0"
  /* 62 */ "BSWAP32\0"
  /* 70 */ "XFADDW32\0"
  /* 79 */ "XADDW32\0"
  /* 87 */ "LDW32\0"
  /* 93 */ "XFANDW32\0"
  /* 102 */ "XANDW32\0"
  /* 110 */ "CMPXCHGW32\0"
  /* 121 */ "XFORW32\0"
  /* 129 */ "XFXORW32\0"
  /* 138 */ "XXORW32\0"
  /* 146 */ "STW32\0"
  /* 152 */ "Select_Ri_64_32\0"
  /* 168 */ "Select_64_32\0"
  /* 181 */ "NEG_32\0"
  /* 188 */ "Select_Ri_32\0"
  /* 201 */ "SRA_ri_32\0"
  /* 211 */ "SUB_ri_32\0"
  /* 221 */ "ADD_ri_32\0"
  /* 231 */ "AND_ri_32\0"
  /* 241 */ "SMOD_ri_32\0"
  /* 252 */ "JSGE_ri_32\0"
  /* 263 */ "JUGE_ri_32\0"
  /* 274 */ "JSLE_ri_32\0"
  /* 285 */ "JULE_ri_32\0"
  /* 296 */ "JNE_ri_32\0"
  /* 306 */ "SLL_ri_32\0"
  /* 316 */ "SRL_ri_32\0"
  /* 326 */ "MUL_ri_32\0"
  /* 336 */ "JEQ_ri_32\0"
  /* 346 */ "XOR_ri_32\0"
  /* 356 */ "JSET_ri_32\0"
  /* 367 */ "JSGT_ri_32\0"
  /* 378 */ "JUGT_ri_32\0"
  /* 389 */ "JSLT_ri_32\0"
  /* 400 */ "JULT_ri_32\0"
  /* 411 */ "SDIV_ri_32\0"
  /* 422 */ "MOV_ri_32\0"
  /* 432 */ "SRA_rr_32\0"
  /* 442 */ "SUB_rr_32\0"
  /* 452 */ "ADD_rr_32\0"
  /* 462 */ "AND_rr_32\0"
  /* 472 */ "SMOD_rr_32\0"
  /* 483 */ "JSGE_rr_32\0"
  /* 494 */ "JUGE_rr_32\0"
  /* 505 */ "JSLE_rr_32\0"
  /* 516 */ "JULE_rr_32\0"
  /* 527 */ "JNE_rr_32\0"
  /* 537 */ "SLL_rr_32\0"
  /* 547 */ "SRL_rr_32\0"
  /* 557 */ "MUL_rr_32\0"
  /* 567 */ "JEQ_rr_32\0"
  /* 577 */ "XOR_rr_32\0"
  /* 587 */ "JSET_rr_32\0"
  /* 598 */ "JSGT_rr_32\0"
  /* 609 */ "JUGT_rr_32\0"
  /* 620 */ "JSLT_rr_32\0"
  /* 631 */ "JULT_rr_32\0"
  /* 642 */ "SDIV_rr_32\0"
  /* 653 */ "MOV_rr_32\0"
  /* 663 */ "MOVSX_rr_32\0"
  /* 675 */ "Select_32\0"
  /* 685 */ "G_FLOG2\0"
  /* 693 */ "G_FEXP2\0"
  /* 701 */ "CORE_LD64\0"
  /* 711 */ "BE64\0"
  /* 716 */ "LE64\0"
  /* 721 */ "BSWAP64\0"
  /* 729 */ "MOV_32_64\0"
  /* 739 */ "Select_Ri_32_64\0"
  /* 755 */ "Select_32_64\0"
  /* 768 */ "NEG_64\0"
  /* 775 */ "LD_imm64\0"
  /* 784 */ "BE16\0"
  /* 789 */ "LE16\0"
  /* 794 */ "BSWAP16\0"
  /* 802 */ "MOVSX_rr_32_16\0"
  /* 817 */ "MOVSX_rr_16\0"
  /* 829 */ "MOVSX_rr_32_8\0"
  /* 843 */ "MOVSX_rr_8\0"
  /* 854 */ "G_FMA\0"
  /* 860 */ "G_STRICT_FMA\0"
  /* 873 */ "LDB\0"
  /* 877 */ "STB\0"
  /* 881 */ "G_FSUB\0"
  /* 888 */ "G_STRICT_FSUB\0"
  /* 902 */ "G_ATOMICRMW_FSUB\0"
  /* 919 */ "G_SUB\0"
  /* 925 */ "G_ATOMICRMW_SUB\0"
  /* 941 */ "LD_IND_B\0"
  /* 950 */ "LD_ABS_B\0"
  /* 959 */ "G_INTRINSIC\0"
  /* 971 */ "G_FPTRUNC\0"
  /* 981 */ "G_INTRINSIC_TRUNC\0"
  /* 999 */ "G_TRUNC\0"
  /* 1007 */ "G_BUILD_VECTOR_TRUNC\0"
  /* 1028 */ "G_DYN_STACKALLOC\0"
  /* 1045 */ "G_FMAD\0"
  /* 1052 */ "G_INDEXED_SEXTLOAD\0"
  /* 1071 */ "G_SEXTLOAD\0"
  /* 1082 */ "G_INDEXED_ZEXTLOAD\0"
  /* 1101 */ "G_ZEXTLOAD\0"
  /* 1112 */ "G_INDEXED_LOAD\0"
  /* 1127 */ "G_LOAD\0"
  /* 1134 */ "G_VECREDUCE_FADD\0"
  /* 1151 */ "G_FADD\0"
  /* 1158 */ "G_VECREDUCE_SEQ_FADD\0"
  /* 1179 */ "G_STRICT_FADD\0"
  /* 1193 */ "G_ATOMICRMW_FADD\0"
  /* 1210 */ "G_VECREDUCE_ADD\0"
  /* 1226 */ "G_ADD\0"
  /* 1232 */ "G_PTR_ADD\0"
  /* 1242 */ "G_ATOMICRMW_ADD\0"
  /* 1258 */ "XFADDD\0"
  /* 1265 */ "XADDD\0"
  /* 1271 */ "LDD\0"
  /* 1275 */ "XFANDD\0"
  /* 1282 */ "XANDD\0"
  /* 1288 */ "CMPXCHGD\0"
  /* 1297 */ "G_ATOMICRMW_NAND\0"
  /* 1314 */ "G_VECREDUCE_AND\0"
  /* 1330 */ "G_AND\0"
  /* 1336 */ "G_ATOMICRMW_AND\0"
  /* 1352 */ "LIFETIME_END\0"
  /* 1365 */ "JCOND\0"
  /* 1371 */ "G_BRCOND\0"
  /* 1380 */ "G_LLROUND\0"
  /* 1390 */ "G_LROUND\0"
  /* 1399 */ "G_INTRINSIC_ROUND\0"
  /* 1417 */ "G_INTRINSIC_FPTRUNC_ROUND\0"
  /* 1443 */ "LOAD_STACK_GUARD\0"
  /* 1460 */ "XFORD\0"
  /* 1466 */ "XFXORD\0"
  /* 1473 */ "XXORD\0"
  /* 1479 */ "STD\0"
  /* 1483 */ "PSEUDO_PROBE\0"
  /* 1496 */ "G_SSUBE\0"
  /* 1504 */ "G_USUBE\0"
  /* 1512 */ "G_FENCE\0"
  /* 1520 */ "ARITH_FENCE\0"
  /* 1532 */ "REG_SEQUENCE\0"
  /* 1545 */ "G_SADDE\0"
  /* 1553 */ "G_UADDE\0"
  /* 1561 */ "G_GET_FPMODE\0"
  /* 1574 */ "G_RESET_FPMODE\0"
  /* 1589 */ "G_SET_FPMODE\0"
  /* 1602 */ "G_FMINNUM_IEEE\0"
  /* 1617 */ "G_FMAXNUM_IEEE\0"
  /* 1632 */ "G_VSCALE\0"
  /* 1641 */ "G_JUMP_TABLE\0"
  /* 1654 */ "BUNDLE\0"
  /* 1661 */ "G_MEMCPY_INLINE\0"
  /* 1677 */ "LOCAL_ESCAPE\0"
  /* 1690 */ "G_STACKRESTORE\0"
  /* 1705 */ "G_INDEXED_STORE\0"
  /* 1721 */ "G_STORE\0"
  /* 1729 */ "G_BITREVERSE\0"
  /* 1742 */ "FAKE_USE\0"
  /* 1751 */ "DBG_VALUE\0"
  /* 1761 */ "G_GLOBAL_VALUE\0"
  /* 1776 */ "G_PTRAUTH_GLOBAL_VALUE\0"
  /* 1799 */ "CONVERGENCECTRL_GLUE\0"
  /* 1820 */ "G_STACKSAVE\0"
  /* 1832 */ "G_MEMMOVE\0"
  /* 1842 */ "G_FREEZE\0"
  /* 1851 */ "G_FCANONICALIZE\0"
  /* 1867 */ "G_CTLZ_ZERO_UNDEF\0"
  /* 1885 */ "G_CTTZ_ZERO_UNDEF\0"
  /* 1903 */ "G_IMPLICIT_DEF\0"
  /* 1918 */ "DBG_INSTR_REF\0"
  /* 1932 */ "G_FNEG\0"
  /* 1939 */ "EXTRACT_SUBREG\0"
  /* 1954 */ "INSERT_SUBREG\0"
  /* 1968 */ "G_SEXT_INREG\0"
  /* 1981 */ "SUBREG_TO_REG\0"
  /* 1995 */ "G_ATOMIC_CMPXCHG\0"
  /* 2012 */ "G_ATOMICRMW_XCHG\0"
  /* 2029 */ "G_FLOG\0"
  /* 2036 */ "G_VAARG\0"
  /* 2044 */ "PREALLOCATED_ARG\0"
  /* 2061 */ "G_PREFETCH\0"
  /* 2072 */ "LDH\0"
  /* 2076 */ "G_SMULH\0"
  /* 2084 */ "G_UMULH\0"
  /* 2092 */ "G_FTANH\0"
  /* 2100 */ "G_FSINH\0"
  /* 2108 */ "G_FCOSH\0"
  /* 2116 */ "STH\0"
  /* 2120 */ "LD_IND_H\0"
  /* 2129 */ "LD_ABS_H\0"
  /* 2138 */ "DBG_PHI\0"
  /* 2146 */ "G_FPTOSI\0"
  /* 2155 */ "G_FPTOUI\0"
  /* 2164 */ "G_FPOWI\0"
  /* 2172 */ "G_PTRMASK\0"
  /* 2182 */ "JAL\0"
  /* 2186 */ "GC_LABEL\0"
  /* 2195 */ "DBG_LABEL\0"
  /* 2205 */ "EH_LABEL\0"
  /* 2214 */ "ANNOTATION_LABEL\0"
  /* 2231 */ "ICALL_BRANCH_FUNNEL\0"
  /* 2251 */ "G_FSHL\0"
  /* 2258 */ "G_SHL\0"
  /* 2264 */ "G_FCEIL\0"
  /* 2272 */ "PATCHABLE_TAIL_CALL\0"
  /* 2292 */ "PATCHABLE_TYPED_EVENT_CALL\0"
  /* 2319 */ "PATCHABLE_EVENT_CALL\0"
  /* 2340 */ "FENTRY_CALL\0"
  /* 2352 */ "KILL\0"
  /* 2357 */ "G_CONSTANT_POOL\0"
  /* 2373 */ "JMPL\0"
  /* 2378 */ "G_ROTL\0"
  /* 2385 */ "G_VECREDUCE_FMUL\0"
  /* 2402 */ "G_FMUL\0"
  /* 2409 */ "G_VECREDUCE_SEQ_FMUL\0"
  /* 2430 */ "G_STRICT_FMUL\0"
  /* 2444 */ "G_VECREDUCE_MUL\0"
  /* 2460 */ "G_MUL\0"
  /* 2466 */ "G_FREM\0"
  /* 2473 */ "G_STRICT_FREM\0"
  /* 2487 */ "G_SREM\0"
  /* 2494 */ "G_UREM\0"
  /* 2501 */ "G_SDIVREM\0"
  /* 2511 */ "G_UDIVREM\0"
  /* 2521 */ "INLINEASM\0"
  /* 2531 */ "G_VECREDUCE_FMINIMUM\0"
  /* 2552 */ "G_FMINIMUM\0"
  /* 2563 */ "G_VECREDUCE_FMAXIMUM\0"
  /* 2584 */ "G_FMAXIMUM\0"
  /* 2595 */ "G_FMINNUM\0"
  /* 2605 */ "G_FMAXNUM\0"
  /* 2615 */ "G_FATAN\0"
  /* 2623 */ "G_FTAN\0"
  /* 2630 */ "G_INTRINSIC_ROUNDEVEN\0"
  /* 2652 */ "G_ASSERT_ALIGN\0"
  /* 2667 */ "G_FCOPYSIGN\0"
  /* 2679 */ "G_VECREDUCE_FMIN\0"
  /* 2696 */ "G_ATOMICRMW_FMIN\0"
  /* 2713 */ "G_VECREDUCE_SMIN\0"
  /* 2730 */ "G_SMIN\0"
  /* 2737 */ "G_VECREDUCE_UMIN\0"
  /* 2754 */ "G_UMIN\0"
  /* 2761 */ "G_ATOMICRMW_UMIN\0"
  /* 2778 */ "G_ATOMICRMW_MIN\0"
  /* 2794 */ "G_FASIN\0"
  /* 2802 */ "G_FSIN\0"
  /* 2809 */ "CFI_INSTRUCTION\0"
  /* 2825 */ "ADJCALLSTACKDOWN\0"
  /* 2842 */ "G_SSUBO\0"
  /* 2850 */ "G_USUBO\0"
  /* 2858 */ "G_SADDO\0"
  /* 2866 */ "G_UADDO\0"
  /* 2874 */ "JUMP_TABLE_DEBUG_INFO\0"
  /* 2896 */ "G_SMULO\0"
  /* 2904 */ "G_UMULO\0"
  /* 2912 */ "G_BZERO\0"
  /* 2920 */ "STACKMAP\0"
  /* 2929 */ "G_DEBUGTRAP\0"
  /* 2941 */ "G_UBSANTRAP\0"
  /* 2953 */ "G_TRAP\0"
  /* 2960 */ "G_ATOMICRMW_UDEC_WRAP\0"
  /* 2982 */ "G_ATOMICRMW_UINC_WRAP\0"
  /* 3004 */ "G_BSWAP\0"
  /* 3012 */ "G_SITOFP\0"
  /* 3021 */ "G_UITOFP\0"
  /* 3030 */ "G_FCMP\0"
  /* 3037 */ "G_ICMP\0"
  /* 3044 */ "G_SCMP\0"
  /* 3051 */ "G_UCMP\0"
  /* 3058 */ "JMP\0"
  /* 3062 */ "NOP\0"
  /* 3066 */ "CONVERGENCECTRL_LOOP\0"
  /* 3087 */ "G_CTPOP\0"
  /* 3095 */ "PATCHABLE_OP\0"
  /* 3108 */ "FAULTING_OP\0"
  /* 3120 */ "ADJCALLSTACKUP\0"
  /* 3135 */ "PREALLOCATED_SETUP\0"
  /* 3154 */ "G_FLDEXP\0"
  /* 3163 */ "G_STRICT_FLDEXP\0"
  /* 3179 */ "G_FEXP\0"
  /* 3186 */ "G_FFREXP\0"
  /* 3195 */ "G_BR\0"
  /* 3200 */ "INLINEASM_BR\0"
  /* 3213 */ "G_BLOCK_ADDR\0"
  /* 3226 */ "MEMBARRIER\0"
  /* 3237 */ "G_CONSTANT_FOLD_BARRIER\0"
  /* 3261 */ "PATCHABLE_FUNCTION_ENTER\0"
  /* 3286 */ "G_READCYCLECOUNTER\0"
  /* 3305 */ "G_READSTEADYCOUNTER\0"
  /* 3325 */ "G_READ_REGISTER\0"
  /* 3341 */ "G_WRITE_REGISTER\0"
  /* 3358 */ "G_ASHR\0"
  /* 3365 */ "G_FSHR\0"
  /* 3372 */ "G_LSHR\0"
  /* 3379 */ "CONVERGENCECTRL_ANCHOR\0"
  /* 3402 */ "G_FFLOOR\0"
  /* 3411 */ "G_EXTRACT_SUBVECTOR\0"
  /* 3431 */ "G_INSERT_SUBVECTOR\0"
  /* 3450 */ "G_BUILD_VECTOR\0"
  /* 3465 */ "G_SHUFFLE_VECTOR\0"
  /* 3482 */ "G_SPLAT_VECTOR\0"
  /* 3497 */ "G_VECREDUCE_XOR\0"
  /* 3513 */ "G_XOR\0"
  /* 3519 */ "G_ATOMICRMW_XOR\0"
  /* 3535 */ "G_VECREDUCE_OR\0"
  /* 3550 */ "G_OR\0"
  /* 3555 */ "G_ATOMICRMW_OR\0"
  /* 3570 */ "G_ROTR\0"
  /* 3577 */ "G_INTTOPTR\0"
  /* 3588 */ "G_FABS\0"
  /* 3595 */ "G_ABS\0"
  /* 3601 */ "G_UNMERGE_VALUES\0"
  /* 3618 */ "G_MERGE_VALUES\0"
  /* 3633 */ "G_FACOS\0"
  /* 3641 */ "G_FCOS\0"
  /* 3648 */ "G_CONCAT_VECTORS\0"
  /* 3665 */ "COPY_TO_REGCLASS\0"
  /* 3682 */ "G_IS_FPCLASS\0"
  /* 3695 */ "G_ATOMIC_CMPXCHG_WITH_SUCCESS\0"
  /* 3725 */ "G_VECTOR_COMPRESS\0"
  /* 3743 */ "G_INTRINSIC_W_SIDE_EFFECTS\0"
  /* 3770 */ "G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS\0"
  /* 3808 */ "G_SSUBSAT\0"
  /* 3818 */ "G_USUBSAT\0"
  /* 3828 */ "G_SADDSAT\0"
  /* 3838 */ "G_UADDSAT\0"
  /* 3848 */ "G_SSHLSAT\0"
  /* 3858 */ "G_USHLSAT\0"
  /* 3868 */ "G_SMULFIXSAT\0"
  /* 3881 */ "G_UMULFIXSAT\0"
  /* 3894 */ "G_SDIVFIXSAT\0"
  /* 3907 */ "G_UDIVFIXSAT\0"
  /* 3920 */ "G_EXTRACT\0"
  /* 3930 */ "G_SELECT\0"
  /* 3939 */ "G_BRINDIRECT\0"
  /* 3952 */ "PATCHABLE_RET\0"
  /* 3966 */ "G_MEMSET\0"
  /* 3975 */ "CORE_SHIFT\0"
  /* 3986 */ "PATCHABLE_FUNCTION_EXIT\0"
  /* 4010 */ "G_BRJT\0"
  /* 4017 */ "G_EXTRACT_VECTOR_ELT\0"
  /* 4038 */ "G_INSERT_VECTOR_ELT\0"
  /* 4058 */ "G_FCONSTANT\0"
  /* 4070 */ "G_CONSTANT\0"
  /* 4081 */ "G_INTRINSIC_CONVERGENT\0"
  /* 4104 */ "STATEPOINT\0"
  /* 4115 */ "PATCHPOINT\0"
  /* 4126 */ "G_PTRTOINT\0"
  /* 4137 */ "G_FRINT\0"
  /* 4145 */ "G_INTRINSIC_LLRINT\0"
  /* 4164 */ "G_INTRINSIC_LRINT\0"
  /* 4182 */ "G_FNEARBYINT\0"
  /* 4195 */ "G_VASTART\0"
  /* 4205 */ "LIFETIME_START\0"
  /* 4220 */ "G_INVOKE_REGION_START\0"
  /* 4242 */ "G_INSERT\0"
  /* 4251 */ "G_FSQRT\0"
  /* 4259 */ "G_STRICT_FSQRT\0"
  /* 4274 */ "G_BITCAST\0"
  /* 4284 */ "G_ADDRSPACE_CAST\0"
  /* 4301 */ "ADDR_SPACE_CAST\0"
  /* 4317 */ "DBG_VALUE_LIST\0"
  /* 4332 */ "CORE_ST\0"
  /* 4340 */ "G_FPEXT\0"
  /* 4348 */ "G_SEXT\0"
  /* 4355 */ "G_ASSERT_SEXT\0"
  /* 4369 */ "G_ANYEXT\0"
  /* 4378 */ "G_ZEXT\0"
  /* 4385 */ "G_ASSERT_ZEXT\0"
  /* 4399 */ "G_FDIV\0"
  /* 4406 */ "G_STRICT_FDIV\0"
  /* 4420 */ "G_SDIV\0"
  /* 4427 */ "G_UDIV\0"
  /* 4434 */ "G_GET_FPENV\0"
  /* 4446 */ "G_RESET_FPENV\0"
  /* 4460 */ "G_SET_FPENV\0"
  /* 4472 */ "XADDW\0"
  /* 4478 */ "LDW\0"
  /* 4482 */ "G_FPOW\0"
  /* 4489 */ "STW\0"
  /* 4493 */ "LD_IND_W\0"
  /* 4502 */ "LD_ABS_W\0"
  /* 4511 */ "G_VECREDUCE_FMAX\0"
  /* 4528 */ "G_ATOMICRMW_FMAX\0"
  /* 4545 */ "G_VECREDUCE_SMAX\0"
  /* 4562 */ "G_SMAX\0"
  /* 4569 */ "G_VECREDUCE_UMAX\0"
  /* 4586 */ "G_UMAX\0"
  /* 4593 */ "G_ATOMICRMW_UMAX\0"
  /* 4610 */ "G_ATOMICRMW_MAX\0"
  /* 4626 */ "G_FRAME_INDEX\0"
  /* 4640 */ "G_SBFX\0"
  /* 4647 */ "G_UBFX\0"
  /* 4654 */ "G_SMULFIX\0"
  /* 4664 */ "G_UMULFIX\0"
  /* 4674 */ "G_SDIVFIX\0"
  /* 4684 */ "G_UDIVFIX\0"
  /* 4694 */ "JALX\0"
  /* 4699 */ "LDBSX\0"
  /* 4705 */ "LDHSX\0"
  /* 4711 */ "LDWSX\0"
  /* 4717 */ "G_MEMCPY\0"
  /* 4726 */ "COPY\0"
  /* 4731 */ "CONVERGENCECTRL_ENTRY\0"
  /* 4753 */ "G_CTLZ\0"
  /* 4760 */ "G_CTTZ\0"
  /* 4767 */ "Select_Ri\0"
  /* 4777 */ "SRA_ri\0"
  /* 4784 */ "SUB_ri\0"
  /* 4791 */ "ADD_ri\0"
  /* 4798 */ "AND_ri\0"
  /* 4805 */ "SMOD_ri\0"
  /* 4813 */ "JSGE_ri\0"
  /* 4821 */ "JUGE_ri\0"
  /* 4829 */ "JSLE_ri\0"
  /* 4837 */ "JULE_ri\0"
  /* 4845 */ "JNE_ri\0"
  /* 4852 */ "FI_ri\0"
  /* 4858 */ "SLL_ri\0"
  /* 4865 */ "SRL_ri\0"
  /* 4872 */ "MUL_ri\0"
  /* 4879 */ "JEQ_ri\0"
  /* 4886 */ "XOR_ri\0"
  /* 4893 */ "JSET_ri\0"
  /* 4901 */ "JSGT_ri\0"
  /* 4909 */ "JUGT_ri\0"
  /* 4917 */ "JSLT_ri\0"
  /* 4925 */ "JULT_ri\0"
  /* 4933 */ "SDIV_ri\0"
  /* 4941 */ "MOV_ri\0"
  /* 4948 */ "STB_imm\0"
  /* 4956 */ "STD_imm\0"
  /* 4964 */ "STH_imm\0"
  /* 4972 */ "STW_imm\0"
  /* 4980 */ "LD_pseudo\0"
  /* 4990 */ "SRA_rr\0"
  /* 4997 */ "SUB_rr\0"
  /* 5004 */ "ADD_rr\0"
  /* 5011 */ "AND_rr\0"
  /* 5018 */ "SMOD_rr\0"
  /* 5026 */ "JSGE_rr\0"
  /* 5034 */ "JUGE_rr\0"
  /* 5042 */ "JSLE_rr\0"
  /* 5050 */ "JULE_rr\0"
  /* 5058 */ "JNE_rr\0"
  /* 5065 */ "SLL_rr\0"
  /* 5072 */ "SRL_rr\0"
  /* 5079 */ "MUL_rr\0"
  /* 5086 */ "JEQ_rr\0"
  /* 5093 */ "XOR_rr\0"
  /* 5100 */ "JSET_rr\0"
  /* 5108 */ "JSGT_rr\0"
  /* 5116 */ "JUGT_rr\0"
  /* 5124 */ "JSLT_rr\0"
  /* 5132 */ "JULT_rr\0"
  /* 5140 */ "SDIV_rr\0"
  /* 5148 */ "MOV_rr\0"
  /* 5155 */ "Select\0"
};
#ifdef __GNUC__
#pragma GCC diagnostic pop
#endif

extern const unsigned BPFInstrNameIndices[] = {
    2142U, 2521U, 3200U, 2809U, 2205U, 2186U, 2214U, 2352U, 
    1939U, 1954U, 1905U, 1981U, 3665U, 1751U, 4317U, 1918U, 
    2138U, 2195U, 1532U, 4726U, 1654U, 4205U, 1352U, 1483U, 
    1520U, 2920U, 2340U, 4115U, 1443U, 3135U, 2044U, 4104U, 
    1677U, 3108U, 3095U, 3261U, 3952U, 3986U, 2272U, 2319U, 
    2292U, 2231U, 1742U, 3226U, 2874U, 4731U, 3379U, 3066U, 
    1799U, 4355U, 4385U, 2652U, 1226U, 919U, 2460U, 4420U, 
    4427U, 2487U, 2494U, 2501U, 2511U, 1330U, 3550U, 3513U, 
    1903U, 2140U, 4626U, 1761U, 1776U, 2357U, 3920U, 3601U, 
    4242U, 3618U, 3450U, 1007U, 3648U, 4126U, 3577U, 4274U, 
    1842U, 3237U, 1417U, 981U, 1399U, 4164U, 4145U, 2630U, 
    3286U, 3305U, 1127U, 1071U, 1101U, 1112U, 1052U, 1082U, 
    1721U, 1705U, 3695U, 1995U, 2012U, 1242U, 925U, 1336U, 
    1297U, 3555U, 3519U, 4610U, 2778U, 4593U, 2761U, 1193U, 
    902U, 4528U, 2696U, 2982U, 2960U, 1512U, 2061U, 1371U, 
    3939U, 4220U, 959U, 3743U, 4081U, 3770U, 4369U, 999U, 
    4070U, 4058U, 4195U, 2036U, 4348U, 1968U, 4378U, 2258U, 
    3372U, 3358U, 2251U, 3365U, 3570U, 2378U, 3037U, 3030U, 
    3044U, 3051U, 3930U, 2866U, 1553U, 2850U, 1504U, 2858U, 
    1545U, 2842U, 1496U, 2904U, 2896U, 2084U, 2076U, 3838U, 
    3828U, 3818U, 3808U, 3858U, 3848U, 4654U, 4664U, 3868U, 
    3881U, 4674U, 4684U, 3894U, 3907U, 1151U, 881U, 2402U, 
    854U, 1045U, 4399U, 2466U, 4482U, 2164U, 3179U, 693U, 
    9U, 2029U, 685U, 0U, 3154U, 3186U, 1932U, 4340U, 
    971U, 2146U, 2155U, 3012U, 3021U, 3588U, 2667U, 3682U, 
    1851U, 2595U, 2605U, 1602U, 1617U, 2552U, 2584U, 4434U, 
    4460U, 4446U, 1561U, 1589U, 1574U, 1232U, 2172U, 2730U, 
    4562U, 2754U, 4586U, 3595U, 1390U, 1380U, 3195U, 4010U, 
    1632U, 3431U, 3411U, 4038U, 4017U, 3465U, 3482U, 3725U, 
    4760U, 1885U, 4753U, 1867U, 3087U, 3004U, 1729U, 2264U, 
    3641U, 2802U, 2623U, 3633U, 2794U, 2615U, 2108U, 2100U, 
    2092U, 4251U, 3402U, 4137U, 4182U, 4284U, 3213U, 1641U, 
    1028U, 1820U, 1690U, 1179U, 888U, 2430U, 4406U, 2473U, 
    860U, 4259U, 3163U, 3325U, 3341U, 4717U, 1661U, 1832U, 
    3966U, 2912U, 2953U, 2929U, 2941U, 1158U, 2409U, 1134U, 
    2385U, 4511U, 2679U, 2563U, 2531U, 1210U, 2444U, 1314U, 
    3535U, 3497U, 4545U, 2713U, 4569U, 2737U, 4640U, 4647U, 
    2825U, 3120U, 4852U, 4719U, 5155U, 675U, 755U, 168U, 
    4767U, 188U, 739U, 152U, 4301U, 4791U, 221U, 5004U, 
    452U, 4798U, 231U, 5011U, 462U, 784U, 40U, 711U, 
    794U, 62U, 721U, 1288U, 110U, 30U, 701U, 3975U, 
    4332U, 4934U, 412U, 5141U, 643U, 2182U, 4694U, 1365U, 
    4879U, 336U, 5086U, 567U, 3058U, 2373U, 4845U, 296U, 
    5058U, 527U, 4893U, 356U, 5100U, 587U, 4813U, 252U, 
    5026U, 483U, 4901U, 367U, 5108U, 598U, 4829U, 274U, 
    5042U, 505U, 4917U, 389U, 5124U, 620U, 4821U, 263U, 
    5034U, 494U, 4909U, 378U, 5116U, 609U, 4837U, 285U, 
    5050U, 516U, 4925U, 400U, 5132U, 631U, 873U, 18U, 
    4699U, 1271U, 2072U, 50U, 4705U, 4478U, 87U, 4711U, 
    950U, 2129U, 4502U, 941U, 2120U, 4493U, 775U, 4980U, 
    789U, 45U, 716U, 4806U, 242U, 5019U, 473U, 817U, 
    663U, 802U, 829U, 843U, 729U, 4941U, 422U, 5148U, 
    653U, 4872U, 326U, 5079U, 557U, 181U, 768U, 3062U, 
    4887U, 347U, 5094U, 578U, 3962U, 4933U, 411U, 5140U, 
    642U, 4858U, 306U, 5065U, 537U, 4805U, 241U, 5018U, 
    472U, 4777U, 201U, 4990U, 432U, 4865U, 316U, 5072U, 
    547U, 877U, 24U, 4948U, 1479U, 4956U, 2116U, 56U, 
    4964U, 4489U, 146U, 4972U, 4784U, 211U, 4997U, 442U, 
    1265U, 4472U, 79U, 1282U, 102U, 1291U, 113U, 1258U, 
    70U, 1275U, 93U, 1460U, 121U, 1466U, 129U, 1468U, 
    131U, 4886U, 346U, 5093U, 577U, 1473U, 138U, 
};

static inline void InitBPFMCInstrInfo(MCInstrInfo *II) {
  II->InitMCInstrInfo(BPFDescs.Insts, BPFInstrNameIndices, BPFInstrNameData, nullptr, nullptr, 487);
}

} // end namespace llvm
#endif // GET_INSTRINFO_MC_DESC

#ifdef GET_INSTRINFO_HEADER
#undef GET_INSTRINFO_HEADER
namespace llvm {
struct BPFGenInstrInfo : public TargetInstrInfo {
  explicit BPFGenInstrInfo(unsigned CFSetupOpcode = ~0u, unsigned CFDestroyOpcode = ~0u, unsigned CatchRetOpcode = ~0u, unsigned ReturnOpcode = ~0u);
  ~BPFGenInstrInfo() override = default;

};
} // end namespace llvm
#endif // GET_INSTRINFO_HEADER

#ifdef GET_INSTRINFO_HELPER_DECLS
#undef GET_INSTRINFO_HELPER_DECLS


#endif // GET_INSTRINFO_HELPER_DECLS

#ifdef GET_INSTRINFO_HELPERS
#undef GET_INSTRINFO_HELPERS

#endif // GET_INSTRINFO_HELPERS

#ifdef GET_INSTRINFO_CTOR_DTOR
#undef GET_INSTRINFO_CTOR_DTOR
namespace llvm {
extern const BPFInstrTable BPFDescs;
extern const unsigned BPFInstrNameIndices[];
extern const char BPFInstrNameData[];
BPFGenInstrInfo::BPFGenInstrInfo(unsigned CFSetupOpcode, unsigned CFDestroyOpcode, unsigned CatchRetOpcode, unsigned ReturnOpcode)
  : TargetInstrInfo(CFSetupOpcode, CFDestroyOpcode, CatchRetOpcode, ReturnOpcode) {
  InitMCInstrInfo(BPFDescs.Insts, BPFInstrNameIndices, BPFInstrNameData, nullptr, nullptr, 487);
}
} // end namespace llvm
#endif // GET_INSTRINFO_CTOR_DTOR

#ifdef GET_INSTRINFO_OPERAND_ENUM
#undef GET_INSTRINFO_OPERAND_ENUM
namespace llvm {
namespace BPF {
namespace OpName {
enum {
  OPERAND_LAST
};
} // end namespace OpName
} // end namespace BPF
} // end namespace llvm
#endif //GET_INSTRINFO_OPERAND_ENUM

#ifdef GET_INSTRINFO_NAMED_OPS
#undef GET_INSTRINFO_NAMED_OPS
namespace llvm {
namespace BPF {
LLVM_READONLY
int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx) {
  return -1;
}
} // end namespace BPF
} // end namespace llvm
#endif //GET_INSTRINFO_NAMED_OPS

#ifdef GET_INSTRINFO_OPERAND_TYPES_ENUM
#undef GET_INSTRINFO_OPERAND_TYPES_ENUM
namespace llvm {
namespace BPF {
namespace OpTypes {
enum OperandType {
  MEMri = 0,
  brtarget = 1,
  calltarget = 2,
  f32imm = 3,
  f64imm = 4,
  gpr_or_imm = 5,
  i1imm = 6,
  i8imm = 7,
  i16imm = 8,
  i32imm = 9,
  i64imm = 10,
  ptype0 = 11,
  ptype1 = 12,
  ptype2 = 13,
  ptype3 = 14,
  ptype4 = 15,
  ptype5 = 16,
  s16imm = 17,
  type0 = 18,
  type1 = 19,
  type2 = 20,
  type3 = 21,
  type4 = 22,
  type5 = 23,
  u64imm = 24,
  untyped_imm_0 = 25,
  GPR = 26,
  GPR32 = 27,
  OPERAND_TYPE_LIST_END
};
} // end namespace OpTypes
} // end namespace BPF
} // end namespace llvm
#endif // GET_INSTRINFO_OPERAND_TYPES_ENUM

#ifdef GET_INSTRINFO_OPERAND_TYPE
#undef GET_INSTRINFO_OPERAND_TYPE
namespace llvm {
namespace BPF {
LLVM_READONLY
static int getOperandType(uint16_t Opcode, uint16_t OpIdx) {
  static const uint16_t Offsets[] = {
    /* PHI */
    0,
    /* INLINEASM */
    1,
    /* INLINEASM_BR */
    1,
    /* CFI_INSTRUCTION */
    1,
    /* EH_LABEL */
    2,
    /* GC_LABEL */
    3,
    /* ANNOTATION_LABEL */
    4,
    /* KILL */
    5,
    /* EXTRACT_SUBREG */
    5,
    /* INSERT_SUBREG */
    8,
    /* IMPLICIT_DEF */
    12,
    /* SUBREG_TO_REG */
    13,
    /* COPY_TO_REGCLASS */
    17,
    /* DBG_VALUE */
    20,
    /* DBG_VALUE_LIST */
    20,
    /* DBG_INSTR_REF */
    20,
    /* DBG_PHI */
    20,
    /* DBG_LABEL */
    20,
    /* REG_SEQUENCE */
    21,
    /* COPY */
    23,
    /* BUNDLE */
    25,
    /* LIFETIME_START */
    25,
    /* LIFETIME_END */
    26,
    /* PSEUDO_PROBE */
    27,
    /* ARITH_FENCE */
    31,
    /* STACKMAP */
    33,
    /* FENTRY_CALL */
    35,
    /* PATCHPOINT */
    35,
    /* LOAD_STACK_GUARD */
    41,
    /* PREALLOCATED_SETUP */
    42,
    /* PREALLOCATED_ARG */
    43,
    /* STATEPOINT */
    46,
    /* LOCAL_ESCAPE */
    46,
    /* FAULTING_OP */
    48,
    /* PATCHABLE_OP */
    49,
    /* PATCHABLE_FUNCTION_ENTER */
    49,
    /* PATCHABLE_RET */
    49,
    /* PATCHABLE_FUNCTION_EXIT */
    49,
    /* PATCHABLE_TAIL_CALL */
    49,
    /* PATCHABLE_EVENT_CALL */
    49,
    /* PATCHABLE_TYPED_EVENT_CALL */
    51,
    /* ICALL_BRANCH_FUNNEL */
    54,
    /* FAKE_USE */
    54,
    /* MEMBARRIER */
    54,
    /* JUMP_TABLE_DEBUG_INFO */
    54,
    /* CONVERGENCECTRL_ENTRY */
    55,
    /* CONVERGENCECTRL_ANCHOR */
    56,
    /* CONVERGENCECTRL_LOOP */
    57,
    /* CONVERGENCECTRL_GLUE */
    59,
    /* G_ASSERT_SEXT */
    60,
    /* G_ASSERT_ZEXT */
    63,
    /* G_ASSERT_ALIGN */
    66,
    /* G_ADD */
    69,
    /* G_SUB */
    72,
    /* G_MUL */
    75,
    /* G_SDIV */
    78,
    /* G_UDIV */
    81,
    /* G_SREM */
    84,
    /* G_UREM */
    87,
    /* G_SDIVREM */
    90,
    /* G_UDIVREM */
    94,
    /* G_AND */
    98,
    /* G_OR */
    101,
    /* G_XOR */
    104,
    /* G_IMPLICIT_DEF */
    107,
    /* G_PHI */
    108,
    /* G_FRAME_INDEX */
    109,
    /* G_GLOBAL_VALUE */
    111,
    /* G_PTRAUTH_GLOBAL_VALUE */
    113,
    /* G_CONSTANT_POOL */
    118,
    /* G_EXTRACT */
    120,
    /* G_UNMERGE_VALUES */
    123,
    /* G_INSERT */
    125,
    /* G_MERGE_VALUES */
    129,
    /* G_BUILD_VECTOR */
    131,
    /* G_BUILD_VECTOR_TRUNC */
    133,
    /* G_CONCAT_VECTORS */
    135,
    /* G_PTRTOINT */
    137,
    /* G_INTTOPTR */
    139,
    /* G_BITCAST */
    141,
    /* G_FREEZE */
    143,
    /* G_CONSTANT_FOLD_BARRIER */
    145,
    /* G_INTRINSIC_FPTRUNC_ROUND */
    147,
    /* G_INTRINSIC_TRUNC */
    150,
    /* G_INTRINSIC_ROUND */
    152,
    /* G_INTRINSIC_LRINT */
    154,
    /* G_INTRINSIC_LLRINT */
    156,
    /* G_INTRINSIC_ROUNDEVEN */
    158,
    /* G_READCYCLECOUNTER */
    160,
    /* G_READSTEADYCOUNTER */
    161,
    /* G_LOAD */
    162,
    /* G_SEXTLOAD */
    164,
    /* G_ZEXTLOAD */
    166,
    /* G_INDEXED_LOAD */
    168,
    /* G_INDEXED_SEXTLOAD */
    173,
    /* G_INDEXED_ZEXTLOAD */
    178,
    /* G_STORE */
    183,
    /* G_INDEXED_STORE */
    185,
    /* G_ATOMIC_CMPXCHG_WITH_SUCCESS */
    190,
    /* G_ATOMIC_CMPXCHG */
    195,
    /* G_ATOMICRMW_XCHG */
    199,
    /* G_ATOMICRMW_ADD */
    202,
    /* G_ATOMICRMW_SUB */
    205,
    /* G_ATOMICRMW_AND */
    208,
    /* G_ATOMICRMW_NAND */
    211,
    /* G_ATOMICRMW_OR */
    214,
    /* G_ATOMICRMW_XOR */
    217,
    /* G_ATOMICRMW_MAX */
    220,
    /* G_ATOMICRMW_MIN */
    223,
    /* G_ATOMICRMW_UMAX */
    226,
    /* G_ATOMICRMW_UMIN */
    229,
    /* G_ATOMICRMW_FADD */
    232,
    /* G_ATOMICRMW_FSUB */
    235,
    /* G_ATOMICRMW_FMAX */
    238,
    /* G_ATOMICRMW_FMIN */
    241,
    /* G_ATOMICRMW_UINC_WRAP */
    244,
    /* G_ATOMICRMW_UDEC_WRAP */
    247,
    /* G_FENCE */
    250,
    /* G_PREFETCH */
    252,
    /* G_BRCOND */
    256,
    /* G_BRINDIRECT */
    258,
    /* G_INVOKE_REGION_START */
    259,
    /* G_INTRINSIC */
    259,
    /* G_INTRINSIC_W_SIDE_EFFECTS */
    260,
    /* G_INTRINSIC_CONVERGENT */
    261,
    /* G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS */
    262,
    /* G_ANYEXT */
    263,
    /* G_TRUNC */
    265,
    /* G_CONSTANT */
    267,
    /* G_FCONSTANT */
    269,
    /* G_VASTART */
    271,
    /* G_VAARG */
    272,
    /* G_SEXT */
    275,
    /* G_SEXT_INREG */
    277,
    /* G_ZEXT */
    280,
    /* G_SHL */
    282,
    /* G_LSHR */
    285,
    /* G_ASHR */
    288,
    /* G_FSHL */
    291,
    /* G_FSHR */
    295,
    /* G_ROTR */
    299,
    /* G_ROTL */
    302,
    /* G_ICMP */
    305,
    /* G_FCMP */
    309,
    /* G_SCMP */
    313,
    /* G_UCMP */
    316,
    /* G_SELECT */
    319,
    /* G_UADDO */
    323,
    /* G_UADDE */
    327,
    /* G_USUBO */
    332,
    /* G_USUBE */
    336,
    /* G_SADDO */
    341,
    /* G_SADDE */
    345,
    /* G_SSUBO */
    350,
    /* G_SSUBE */
    354,
    /* G_UMULO */
    359,
    /* G_SMULO */
    363,
    /* G_UMULH */
    367,
    /* G_SMULH */
    370,
    /* G_UADDSAT */
    373,
    /* G_SADDSAT */
    376,
    /* G_USUBSAT */
    379,
    /* G_SSUBSAT */
    382,
    /* G_USHLSAT */
    385,
    /* G_SSHLSAT */
    388,
    /* G_SMULFIX */
    391,
    /* G_UMULFIX */
    395,
    /* G_SMULFIXSAT */
    399,
    /* G_UMULFIXSAT */
    403,
    /* G_SDIVFIX */
    407,
    /* G_UDIVFIX */
    411,
    /* G_SDIVFIXSAT */
    415,
    /* G_UDIVFIXSAT */
    419,
    /* G_FADD */
    423,
    /* G_FSUB */
    426,
    /* G_FMUL */
    429,
    /* G_FMA */
    432,
    /* G_FMAD */
    436,
    /* G_FDIV */
    440,
    /* G_FREM */
    443,
    /* G_FPOW */
    446,
    /* G_FPOWI */
    449,
    /* G_FEXP */
    452,
    /* G_FEXP2 */
    454,
    /* G_FEXP10 */
    456,
    /* G_FLOG */
    458,
    /* G_FLOG2 */
    460,
    /* G_FLOG10 */
    462,
    /* G_FLDEXP */
    464,
    /* G_FFREXP */
    467,
    /* G_FNEG */
    470,
    /* G_FPEXT */
    472,
    /* G_FPTRUNC */
    474,
    /* G_FPTOSI */
    476,
    /* G_FPTOUI */
    478,
    /* G_SITOFP */
    480,
    /* G_UITOFP */
    482,
    /* G_FABS */
    484,
    /* G_FCOPYSIGN */
    486,
    /* G_IS_FPCLASS */
    489,
    /* G_FCANONICALIZE */
    492,
    /* G_FMINNUM */
    494,
    /* G_FMAXNUM */
    497,
    /* G_FMINNUM_IEEE */
    500,
    /* G_FMAXNUM_IEEE */
    503,
    /* G_FMINIMUM */
    506,
    /* G_FMAXIMUM */
    509,
    /* G_GET_FPENV */
    512,
    /* G_SET_FPENV */
    513,
    /* G_RESET_FPENV */
    514,
    /* G_GET_FPMODE */
    514,
    /* G_SET_FPMODE */
    515,
    /* G_RESET_FPMODE */
    516,
    /* G_PTR_ADD */
    516,
    /* G_PTRMASK */
    519,
    /* G_SMIN */
    522,
    /* G_SMAX */
    525,
    /* G_UMIN */
    528,
    /* G_UMAX */
    531,
    /* G_ABS */
    534,
    /* G_LROUND */
    536,
    /* G_LLROUND */
    538,
    /* G_BR */
    540,
    /* G_BRJT */
    541,
    /* G_VSCALE */
    544,
    /* G_INSERT_SUBVECTOR */
    546,
    /* G_EXTRACT_SUBVECTOR */
    550,
    /* G_INSERT_VECTOR_ELT */
    553,
    /* G_EXTRACT_VECTOR_ELT */
    557,
    /* G_SHUFFLE_VECTOR */
    560,
    /* G_SPLAT_VECTOR */
    564,
    /* G_VECTOR_COMPRESS */
    566,
    /* G_CTTZ */
    570,
    /* G_CTTZ_ZERO_UNDEF */
    572,
    /* G_CTLZ */
    574,
    /* G_CTLZ_ZERO_UNDEF */
    576,
    /* G_CTPOP */
    578,
    /* G_BSWAP */
    580,
    /* G_BITREVERSE */
    582,
    /* G_FCEIL */
    584,
    /* G_FCOS */
    586,
    /* G_FSIN */
    588,
    /* G_FTAN */
    590,
    /* G_FACOS */
    592,
    /* G_FASIN */
    594,
    /* G_FATAN */
    596,
    /* G_FCOSH */
    598,
    /* G_FSINH */
    600,
    /* G_FTANH */
    602,
    /* G_FSQRT */
    604,
    /* G_FFLOOR */
    606,
    /* G_FRINT */
    608,
    /* G_FNEARBYINT */
    610,
    /* G_ADDRSPACE_CAST */
    612,
    /* G_BLOCK_ADDR */
    614,
    /* G_JUMP_TABLE */
    616,
    /* G_DYN_STACKALLOC */
    618,
    /* G_STACKSAVE */
    621,
    /* G_STACKRESTORE */
    622,
    /* G_STRICT_FADD */
    623,
    /* G_STRICT_FSUB */
    626,
    /* G_STRICT_FMUL */
    629,
    /* G_STRICT_FDIV */
    632,
    /* G_STRICT_FREM */
    635,
    /* G_STRICT_FMA */
    638,
    /* G_STRICT_FSQRT */
    642,
    /* G_STRICT_FLDEXP */
    644,
    /* G_READ_REGISTER */
    647,
    /* G_WRITE_REGISTER */
    649,
    /* G_MEMCPY */
    651,
    /* G_MEMCPY_INLINE */
    655,
    /* G_MEMMOVE */
    658,
    /* G_MEMSET */
    662,
    /* G_BZERO */
    666,
    /* G_TRAP */
    669,
    /* G_DEBUGTRAP */
    669,
    /* G_UBSANTRAP */
    669,
    /* G_VECREDUCE_SEQ_FADD */
    670,
    /* G_VECREDUCE_SEQ_FMUL */
    673,
    /* G_VECREDUCE_FADD */
    676,
    /* G_VECREDUCE_FMUL */
    678,
    /* G_VECREDUCE_FMAX */
    680,
    /* G_VECREDUCE_FMIN */
    682,
    /* G_VECREDUCE_FMAXIMUM */
    684,
    /* G_VECREDUCE_FMINIMUM */
    686,
    /* G_VECREDUCE_ADD */
    688,
    /* G_VECREDUCE_MUL */
    690,
    /* G_VECREDUCE_AND */
    692,
    /* G_VECREDUCE_OR */
    694,
    /* G_VECREDUCE_XOR */
    696,
    /* G_VECREDUCE_SMAX */
    698,
    /* G_VECREDUCE_SMIN */
    700,
    /* G_VECREDUCE_UMAX */
    702,
    /* G_VECREDUCE_UMIN */
    704,
    /* G_SBFX */
    706,
    /* G_UBFX */
    710,
    /* ADJCALLSTACKDOWN */
    714,
    /* ADJCALLSTACKUP */
    716,
    /* FI_ri */
    718,
    /* MEMCPY */
    721,
    /* Select */
    725,
    /* Select_32 */
    731,
    /* Select_32_64 */
    737,
    /* Select_64_32 */
    743,
    /* Select_Ri */
    749,
    /* Select_Ri_32 */
    755,
    /* Select_Ri_32_64 */
    761,
    /* Select_Ri_64_32 */
    767,
    /* ADDR_SPACE_CAST */
    773,
    /* ADD_ri */
    777,
    /* ADD_ri_32 */
    780,
    /* ADD_rr */
    783,
    /* ADD_rr_32 */
    786,
    /* AND_ri */
    789,
    /* AND_ri_32 */
    792,
    /* AND_rr */
    795,
    /* AND_rr_32 */
    798,
    /* BE16 */
    801,
    /* BE32 */
    803,
    /* BE64 */
    805,
    /* BSWAP16 */
    807,
    /* BSWAP32 */
    809,
    /* BSWAP64 */
    811,
    /* CMPXCHGD */
    813,
    /* CMPXCHGW32 */
    816,
    /* CORE_LD32 */
    819,
    /* CORE_LD64 */
    823,
    /* CORE_SHIFT */
    827,
    /* CORE_ST */
    831,
    /* DIV_ri */
    835,
    /* DIV_ri_32 */
    838,
    /* DIV_rr */
    841,
    /* DIV_rr_32 */
    844,
    /* JAL */
    847,
    /* JALX */
    848,
    /* JCOND */
    849,
    /* JEQ_ri */
    850,
    /* JEQ_ri_32 */
    853,
    /* JEQ_rr */
    856,
    /* JEQ_rr_32 */
    859,
    /* JMP */
    862,
    /* JMPL */
    863,
    /* JNE_ri */
    864,
    /* JNE_ri_32 */
    867,
    /* JNE_rr */
    870,
    /* JNE_rr_32 */
    873,
    /* JSET_ri */
    876,
    /* JSET_ri_32 */
    879,
    /* JSET_rr */
    882,
    /* JSET_rr_32 */
    885,
    /* JSGE_ri */
    888,
    /* JSGE_ri_32 */
    891,
    /* JSGE_rr */
    894,
    /* JSGE_rr_32 */
    897,
    /* JSGT_ri */
    900,
    /* JSGT_ri_32 */
    903,
    /* JSGT_rr */
    906,
    /* JSGT_rr_32 */
    909,
    /* JSLE_ri */
    912,
    /* JSLE_ri_32 */
    915,
    /* JSLE_rr */
    918,
    /* JSLE_rr_32 */
    921,
    /* JSLT_ri */
    924,
    /* JSLT_ri_32 */
    927,
    /* JSLT_rr */
    930,
    /* JSLT_rr_32 */
    933,
    /* JUGE_ri */
    936,
    /* JUGE_ri_32 */
    939,
    /* JUGE_rr */
    942,
    /* JUGE_rr_32 */
    945,
    /* JUGT_ri */
    948,
    /* JUGT_ri_32 */
    951,
    /* JUGT_rr */
    954,
    /* JUGT_rr_32 */
    957,
    /* JULE_ri */
    960,
    /* JULE_ri_32 */
    963,
    /* JULE_rr */
    966,
    /* JULE_rr_32 */
    969,
    /* JULT_ri */
    972,
    /* JULT_ri_32 */
    975,
    /* JULT_rr */
    978,
    /* JULT_rr_32 */
    981,
    /* LDB */
    984,
    /* LDB32 */
    987,
    /* LDBSX */
    990,
    /* LDD */
    993,
    /* LDH */
    996,
    /* LDH32 */
    999,
    /* LDHSX */
    1002,
    /* LDW */
    1005,
    /* LDW32 */
    1008,
    /* LDWSX */
    1011,
    /* LD_ABS_B */
    1014,
    /* LD_ABS_H */
    1016,
    /* LD_ABS_W */
    1018,
    /* LD_IND_B */
    1020,
    /* LD_IND_H */
    1022,
    /* LD_IND_W */
    1024,
    /* LD_imm64 */
    1026,
    /* LD_pseudo */
    1028,
    /* LE16 */
    1031,
    /* LE32 */
    1033,
    /* LE64 */
    1035,
    /* MOD_ri */
    1037,
    /* MOD_ri_32 */
    1040,
    /* MOD_rr */
    1043,
    /* MOD_rr_32 */
    1046,
    /* MOVSX_rr_16 */
    1049,
    /* MOVSX_rr_32 */
    1051,
    /* MOVSX_rr_32_16 */
    1053,
    /* MOVSX_rr_32_8 */
    1055,
    /* MOVSX_rr_8 */
    1057,
    /* MOV_32_64 */
    1059,
    /* MOV_ri */
    1061,
    /* MOV_ri_32 */
    1063,
    /* MOV_rr */
    1065,
    /* MOV_rr_32 */
    1067,
    /* MUL_ri */
    1069,
    /* MUL_ri_32 */
    1072,
    /* MUL_rr */
    1075,
    /* MUL_rr_32 */
    1078,
    /* NEG_32 */
    1081,
    /* NEG_64 */
    1083,
    /* NOP */
    1085,
    /* OR_ri */
    1086,
    /* OR_ri_32 */
    1089,
    /* OR_rr */
    1092,
    /* OR_rr_32 */
    1095,
    /* RET */
    1098,
    /* SDIV_ri */
    1098,
    /* SDIV_ri_32 */
    1101,
    /* SDIV_rr */
    1104,
    /* SDIV_rr_32 */
    1107,
    /* SLL_ri */
    1110,
    /* SLL_ri_32 */
    1113,
    /* SLL_rr */
    1116,
    /* SLL_rr_32 */
    1119,
    /* SMOD_ri */
    1122,
    /* SMOD_ri_32 */
    1125,
    /* SMOD_rr */
    1128,
    /* SMOD_rr_32 */
    1131,
    /* SRA_ri */
    1134,
    /* SRA_ri_32 */
    1137,
    /* SRA_rr */
    1140,
    /* SRA_rr_32 */
    1143,
    /* SRL_ri */
    1146,
    /* SRL_ri_32 */
    1149,
    /* SRL_rr */
    1152,
    /* SRL_rr_32 */
    1155,
    /* STB */
    1158,
    /* STB32 */
    1161,
    /* STB_imm */
    1164,
    /* STD */
    1167,
    /* STD_imm */
    1170,
    /* STH */
    1173,
    /* STH32 */
    1176,
    /* STH_imm */
    1179,
    /* STW */
    1182,
    /* STW32 */
    1185,
    /* STW_imm */
    1188,
    /* SUB_ri */
    1191,
    /* SUB_ri_32 */
    1194,
    /* SUB_rr */
    1197,
    /* SUB_rr_32 */
    1200,
    /* XADDD */
    1203,
    /* XADDW */
    1207,
    /* XADDW32 */
    1211,
    /* XANDD */
    1215,
    /* XANDW32 */
    1219,
    /* XCHGD */
    1223,
    /* XCHGW32 */
    1227,
    /* XFADDD */
    1231,
    /* XFADDW32 */
    1235,
    /* XFANDD */
    1239,
    /* XFANDW32 */
    1243,
    /* XFORD */
    1247,
    /* XFORW32 */
    1251,
    /* XFXORD */
    1255,
    /* XFXORW32 */
    1259,
    /* XORD */
    1263,
    /* XORW32 */
    1267,
    /* XOR_ri */
    1271,
    /* XOR_ri_32 */
    1274,
    /* XOR_rr */
    1277,
    /* XOR_rr_32 */
    1280,
    /* XXORD */
    1283,
    /* XXORW32 */
    1287,
  };

  using namespace OpTypes;
  static const int8_t OpcodeOperandTypes[] = {
    
    /* PHI */
    -1, 
    /* INLINEASM */
    /* INLINEASM_BR */
    /* CFI_INSTRUCTION */
    i32imm, 
    /* EH_LABEL */
    i32imm, 
    /* GC_LABEL */
    i32imm, 
    /* ANNOTATION_LABEL */
    i32imm, 
    /* KILL */
    /* EXTRACT_SUBREG */
    -1, -1, i32imm, 
    /* INSERT_SUBREG */
    -1, -1, -1, i32imm, 
    /* IMPLICIT_DEF */
    -1, 
    /* SUBREG_TO_REG */
    -1, -1, -1, i32imm, 
    /* COPY_TO_REGCLASS */
    -1, -1, i32imm, 
    /* DBG_VALUE */
    /* DBG_VALUE_LIST */
    /* DBG_INSTR_REF */
    /* DBG_PHI */
    /* DBG_LABEL */
    -1, 
    /* REG_SEQUENCE */
    -1, -1, 
    /* COPY */
    -1, -1, 
    /* BUNDLE */
    /* LIFETIME_START */
    i32imm, 
    /* LIFETIME_END */
    i32imm, 
    /* PSEUDO_PROBE */
    i64imm, i64imm, i8imm, i32imm, 
    /* ARITH_FENCE */
    -1, -1, 
    /* STACKMAP */
    i64imm, i32imm, 
    /* FENTRY_CALL */
    /* PATCHPOINT */
    -1, i64imm, i32imm, -1, i32imm, i32imm, 
    /* LOAD_STACK_GUARD */
    -1, 
    /* PREALLOCATED_SETUP */
    i32imm, 
    /* PREALLOCATED_ARG */
    -1, i32imm, i32imm, 
    /* STATEPOINT */
    /* LOCAL_ESCAPE */
    -1, i32imm, 
    /* FAULTING_OP */
    -1, 
    /* PATCHABLE_OP */
    /* PATCHABLE_FUNCTION_ENTER */
    /* PATCHABLE_RET */
    /* PATCHABLE_FUNCTION_EXIT */
    /* PATCHABLE_TAIL_CALL */
    /* PATCHABLE_EVENT_CALL */
    -1, -1, 
    /* PATCHABLE_TYPED_EVENT_CALL */
    -1, -1, -1, 
    /* ICALL_BRANCH_FUNNEL */
    /* FAKE_USE */
    /* MEMBARRIER */
    /* JUMP_TABLE_DEBUG_INFO */
    i64imm, 
    /* CONVERGENCECTRL_ENTRY */
    -1, 
    /* CONVERGENCECTRL_ANCHOR */
    -1, 
    /* CONVERGENCECTRL_LOOP */
    -1, -1, 
    /* CONVERGENCECTRL_GLUE */
    -1, 
    /* G_ASSERT_SEXT */
    type0, type0, untyped_imm_0, 
    /* G_ASSERT_ZEXT */
    type0, type0, untyped_imm_0, 
    /* G_ASSERT_ALIGN */
    type0, type0, untyped_imm_0, 
    /* G_ADD */
    type0, type0, type0, 
    /* G_SUB */
    type0, type0, type0, 
    /* G_MUL */
    type0, type0, type0, 
    /* G_SDIV */
    type0, type0, type0, 
    /* G_UDIV */
    type0, type0, type0, 
    /* G_SREM */
    type0, type0, type0, 
    /* G_UREM */
    type0, type0, type0, 
    /* G_SDIVREM */
    type0, type0, type0, type0, 
    /* G_UDIVREM */
    type0, type0, type0, type0, 
    /* G_AND */
    type0, type0, type0, 
    /* G_OR */
    type0, type0, type0, 
    /* G_XOR */
    type0, type0, type0, 
    /* G_IMPLICIT_DEF */
    type0, 
    /* G_PHI */
    type0, 
    /* G_FRAME_INDEX */
    type0, -1, 
    /* G_GLOBAL_VALUE */
    type0, -1, 
    /* G_PTRAUTH_GLOBAL_VALUE */
    type0, -1, i32imm, type1, i64imm, 
    /* G_CONSTANT_POOL */
    type0, -1, 
    /* G_EXTRACT */
    type0, type1, untyped_imm_0, 
    /* G_UNMERGE_VALUES */
    type0, type1, 
    /* G_INSERT */
    type0, type0, type1, untyped_imm_0, 
    /* G_MERGE_VALUES */
    type0, type1, 
    /* G_BUILD_VECTOR */
    type0, type1, 
    /* G_BUILD_VECTOR_TRUNC */
    type0, type1, 
    /* G_CONCAT_VECTORS */
    type0, type1, 
    /* G_PTRTOINT */
    type0, type1, 
    /* G_INTTOPTR */
    type0, type1, 
    /* G_BITCAST */
    type0, type1, 
    /* G_FREEZE */
    type0, type0, 
    /* G_CONSTANT_FOLD_BARRIER */
    type0, type0, 
    /* G_INTRINSIC_FPTRUNC_ROUND */
    type0, type1, i32imm, 
    /* G_INTRINSIC_TRUNC */
    type0, type0, 
    /* G_INTRINSIC_ROUND */
    type0, type0, 
    /* G_INTRINSIC_LRINT */
    type0, type1, 
    /* G_INTRINSIC_LLRINT */
    type0, type1, 
    /* G_INTRINSIC_ROUNDEVEN */
    type0, type0, 
    /* G_READCYCLECOUNTER */
    type0, 
    /* G_READSTEADYCOUNTER */
    type0, 
    /* G_LOAD */
    type0, ptype1, 
    /* G_SEXTLOAD */
    type0, ptype1, 
    /* G_ZEXTLOAD */
    type0, ptype1, 
    /* G_INDEXED_LOAD */
    type0, ptype1, ptype1, type2, -1, 
    /* G_INDEXED_SEXTLOAD */
    type0, ptype1, ptype1, type2, -1, 
    /* G_INDEXED_ZEXTLOAD */
    type0, ptype1, ptype1, type2, -1, 
    /* G_STORE */
    type0, ptype1, 
    /* G_INDEXED_STORE */
    ptype0, type1, ptype0, ptype2, -1, 
    /* G_ATOMIC_CMPXCHG_WITH_SUCCESS */
    type0, type1, type2, type0, type0, 
    /* G_ATOMIC_CMPXCHG */
    type0, ptype1, type0, type0, 
    /* G_ATOMICRMW_XCHG */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_ADD */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_SUB */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_AND */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_NAND */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_OR */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_XOR */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_MAX */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_MIN */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_UMAX */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_UMIN */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_FADD */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_FSUB */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_FMAX */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_FMIN */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_UINC_WRAP */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_UDEC_WRAP */
    type0, ptype1, type0, 
    /* G_FENCE */
    i32imm, i32imm, 
    /* G_PREFETCH */
    ptype0, i32imm, i32imm, i32imm, 
    /* G_BRCOND */
    type0, -1, 
    /* G_BRINDIRECT */
    type0, 
    /* G_INVOKE_REGION_START */
    /* G_INTRINSIC */
    -1, 
    /* G_INTRINSIC_W_SIDE_EFFECTS */
    -1, 
    /* G_INTRINSIC_CONVERGENT */
    -1, 
    /* G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS */
    -1, 
    /* G_ANYEXT */
    type0, type1, 
    /* G_TRUNC */
    type0, type1, 
    /* G_CONSTANT */
    type0, -1, 
    /* G_FCONSTANT */
    type0, -1, 
    /* G_VASTART */
    type0, 
    /* G_VAARG */
    type0, type1, -1, 
    /* G_SEXT */
    type0, type1, 
    /* G_SEXT_INREG */
    type0, type0, untyped_imm_0, 
    /* G_ZEXT */
    type0, type1, 
    /* G_SHL */
    type0, type0, type1, 
    /* G_LSHR */
    type0, type0, type1, 
    /* G_ASHR */
    type0, type0, type1, 
    /* G_FSHL */
    type0, type0, type0, type1, 
    /* G_FSHR */
    type0, type0, type0, type1, 
    /* G_ROTR */
    type0, type0, type1, 
    /* G_ROTL */
    type0, type0, type1, 
    /* G_ICMP */
    type0, -1, type1, type1, 
    /* G_FCMP */
    type0, -1, type1, type1, 
    /* G_SCMP */
    type0, type1, type1, 
    /* G_UCMP */
    type0, type1, type1, 
    /* G_SELECT */
    type0, type1, type0, type0, 
    /* G_UADDO */
    type0, type1, type0, type0, 
    /* G_UADDE */
    type0, type1, type0, type0, type1, 
    /* G_USUBO */
    type0, type1, type0, type0, 
    /* G_USUBE */
    type0, type1, type0, type0, type1, 
    /* G_SADDO */
    type0, type1, type0, type0, 
    /* G_SADDE */
    type0, type1, type0, type0, type1, 
    /* G_SSUBO */
    type0, type1, type0, type0, 
    /* G_SSUBE */
    type0, type1, type0, type0, type1, 
    /* G_UMULO */
    type0, type1, type0, type0, 
    /* G_SMULO */
    type0, type1, type0, type0, 
    /* G_UMULH */
    type0, type0, type0, 
    /* G_SMULH */
    type0, type0, type0, 
    /* G_UADDSAT */
    type0, type0, type0, 
    /* G_SADDSAT */
    type0, type0, type0, 
    /* G_USUBSAT */
    type0, type0, type0, 
    /* G_SSUBSAT */
    type0, type0, type0, 
    /* G_USHLSAT */
    type0, type0, type1, 
    /* G_SSHLSAT */
    type0, type0, type1, 
    /* G_SMULFIX */
    type0, type0, type0, untyped_imm_0, 
    /* G_UMULFIX */
    type0, type0, type0, untyped_imm_0, 
    /* G_SMULFIXSAT */
    type0, type0, type0, untyped_imm_0, 
    /* G_UMULFIXSAT */
    type0, type0, type0, untyped_imm_0, 
    /* G_SDIVFIX */
    type0, type0, type0, untyped_imm_0, 
    /* G_UDIVFIX */
    type0, type0, type0, untyped_imm_0, 
    /* G_SDIVFIXSAT */
    type0, type0, type0, untyped_imm_0, 
    /* G_UDIVFIXSAT */
    type0, type0, type0, untyped_imm_0, 
    /* G_FADD */
    type0, type0, type0, 
    /* G_FSUB */
    type0, type0, type0, 
    /* G_FMUL */
    type0, type0, type0, 
    /* G_FMA */
    type0, type0, type0, type0, 
    /* G_FMAD */
    type0, type0, type0, type0, 
    /* G_FDIV */
    type0, type0, type0, 
    /* G_FREM */
    type0, type0, type0, 
    /* G_FPOW */
    type0, type0, type0, 
    /* G_FPOWI */
    type0, type0, type1, 
    /* G_FEXP */
    type0, type0, 
    /* G_FEXP2 */
    type0, type0, 
    /* G_FEXP10 */
    type0, type0, 
    /* G_FLOG */
    type0, type0, 
    /* G_FLOG2 */
    type0, type0, 
    /* G_FLOG10 */
    type0, type0, 
    /* G_FLDEXP */
    type0, type0, type1, 
    /* G_FFREXP */
    type0, type1, type0, 
    /* G_FNEG */
    type0, type0, 
    /* G_FPEXT */
    type0, type1, 
    /* G_FPTRUNC */
    type0, type1, 
    /* G_FPTOSI */
    type0, type1, 
    /* G_FPTOUI */
    type0, type1, 
    /* G_SITOFP */
    type0, type1, 
    /* G_UITOFP */
    type0, type1, 
    /* G_FABS */
    type0, type0, 
    /* G_FCOPYSIGN */
    type0, type0, type1, 
    /* G_IS_FPCLASS */
    type0, type1, -1, 
    /* G_FCANONICALIZE */
    type0, type0, 
    /* G_FMINNUM */
    type0, type0, type0, 
    /* G_FMAXNUM */
    type0, type0, type0, 
    /* G_FMINNUM_IEEE */
    type0, type0, type0, 
    /* G_FMAXNUM_IEEE */
    type0, type0, type0, 
    /* G_FMINIMUM */
    type0, type0, type0, 
    /* G_FMAXIMUM */
    type0, type0, type0, 
    /* G_GET_FPENV */
    type0, 
    /* G_SET_FPENV */
    type0, 
    /* G_RESET_FPENV */
    /* G_GET_FPMODE */
    type0, 
    /* G_SET_FPMODE */
    type0, 
    /* G_RESET_FPMODE */
    /* G_PTR_ADD */
    ptype0, ptype0, type1, 
    /* G_PTRMASK */
    ptype0, ptype0, type1, 
    /* G_SMIN */
    type0, type0, type0, 
    /* G_SMAX */
    type0, type0, type0, 
    /* G_UMIN */
    type0, type0, type0, 
    /* G_UMAX */
    type0, type0, type0, 
    /* G_ABS */
    type0, type0, 
    /* G_LROUND */
    type0, type1, 
    /* G_LLROUND */
    type0, type1, 
    /* G_BR */
    -1, 
    /* G_BRJT */
    ptype0, -1, type1, 
    /* G_VSCALE */
    type0, -1, 
    /* G_INSERT_SUBVECTOR */
    type0, type0, type1, untyped_imm_0, 
    /* G_EXTRACT_SUBVECTOR */
    type0, type0, untyped_imm_0, 
    /* G_INSERT_VECTOR_ELT */
    type0, type0, type1, type2, 
    /* G_EXTRACT_VECTOR_ELT */
    type0, type1, type2, 
    /* G_SHUFFLE_VECTOR */
    type0, type1, type1, -1, 
    /* G_SPLAT_VECTOR */
    type0, type1, 
    /* G_VECTOR_COMPRESS */
    type0, type0, type1, type0, 
    /* G_CTTZ */
    type0, type1, 
    /* G_CTTZ_ZERO_UNDEF */
    type0, type1, 
    /* G_CTLZ */
    type0, type1, 
    /* G_CTLZ_ZERO_UNDEF */
    type0, type1, 
    /* G_CTPOP */
    type0, type1, 
    /* G_BSWAP */
    type0, type0, 
    /* G_BITREVERSE */
    type0, type0, 
    /* G_FCEIL */
    type0, type0, 
    /* G_FCOS */
    type0, type0, 
    /* G_FSIN */
    type0, type0, 
    /* G_FTAN */
    type0, type0, 
    /* G_FACOS */
    type0, type0, 
    /* G_FASIN */
    type0, type0, 
    /* G_FATAN */
    type0, type0, 
    /* G_FCOSH */
    type0, type0, 
    /* G_FSINH */
    type0, type0, 
    /* G_FTANH */
    type0, type0, 
    /* G_FSQRT */
    type0, type0, 
    /* G_FFLOOR */
    type0, type0, 
    /* G_FRINT */
    type0, type0, 
    /* G_FNEARBYINT */
    type0, type0, 
    /* G_ADDRSPACE_CAST */
    type0, type1, 
    /* G_BLOCK_ADDR */
    type0, -1, 
    /* G_JUMP_TABLE */
    type0, -1, 
    /* G_DYN_STACKALLOC */
    ptype0, type1, i32imm, 
    /* G_STACKSAVE */
    ptype0, 
    /* G_STACKRESTORE */
    ptype0, 
    /* G_STRICT_FADD */
    type0, type0, type0, 
    /* G_STRICT_FSUB */
    type0, type0, type0, 
    /* G_STRICT_FMUL */
    type0, type0, type0, 
    /* G_STRICT_FDIV */
    type0, type0, type0, 
    /* G_STRICT_FREM */
    type0, type0, type0, 
    /* G_STRICT_FMA */
    type0, type0, type0, type0, 
    /* G_STRICT_FSQRT */
    type0, type0, 
    /* G_STRICT_FLDEXP */
    type0, type0, type1, 
    /* G_READ_REGISTER */
    type0, -1, 
    /* G_WRITE_REGISTER */
    -1, type0, 
    /* G_MEMCPY */
    ptype0, ptype1, type2, untyped_imm_0, 
    /* G_MEMCPY_INLINE */
    ptype0, ptype1, type2, 
    /* G_MEMMOVE */
    ptype0, ptype1, type2, untyped_imm_0, 
    /* G_MEMSET */
    ptype0, type1, type2, untyped_imm_0, 
    /* G_BZERO */
    ptype0, type1, untyped_imm_0, 
    /* G_TRAP */
    /* G_DEBUGTRAP */
    /* G_UBSANTRAP */
    i8imm, 
    /* G_VECREDUCE_SEQ_FADD */
    type0, type1, type2, 
    /* G_VECREDUCE_SEQ_FMUL */
    type0, type1, type2, 
    /* G_VECREDUCE_FADD */
    type0, type1, 
    /* G_VECREDUCE_FMUL */
    type0, type1, 
    /* G_VECREDUCE_FMAX */
    type0, type1, 
    /* G_VECREDUCE_FMIN */
    type0, type1, 
    /* G_VECREDUCE_FMAXIMUM */
    type0, type1, 
    /* G_VECREDUCE_FMINIMUM */
    type0, type1, 
    /* G_VECREDUCE_ADD */
    type0, type1, 
    /* G_VECREDUCE_MUL */
    type0, type1, 
    /* G_VECREDUCE_AND */
    type0, type1, 
    /* G_VECREDUCE_OR */
    type0, type1, 
    /* G_VECREDUCE_XOR */
    type0, type1, 
    /* G_VECREDUCE_SMAX */
    type0, type1, 
    /* G_VECREDUCE_SMIN */
    type0, type1, 
    /* G_VECREDUCE_UMAX */
    type0, type1, 
    /* G_VECREDUCE_UMIN */
    type0, type1, 
    /* G_SBFX */
    type0, type0, type1, type1, 
    /* G_UBFX */
    type0, type0, type1, type1, 
    /* ADJCALLSTACKDOWN */
    i64imm, i64imm, 
    /* ADJCALLSTACKUP */
    i64imm, i64imm, 
    /* FI_ri */
    GPR, GPR, s16imm, 
    /* MEMCPY */
    GPR, GPR, i64imm, i64imm, 
    /* Select */
    GPR, GPR, GPR, i64imm, GPR, GPR, 
    /* Select_32 */
    GPR32, GPR32, GPR32, i32imm, GPR32, GPR32, 
    /* Select_32_64 */
    GPR, GPR32, GPR32, i32imm, GPR, GPR, 
    /* Select_64_32 */
    GPR32, GPR, GPR, i64imm, GPR32, GPR32, 
    /* Select_Ri */
    GPR, GPR, i64imm, i64imm, GPR, GPR, 
    /* Select_Ri_32 */
    GPR32, GPR32, i32imm, i32imm, GPR32, GPR32, 
    /* Select_Ri_32_64 */
    GPR, GPR32, i32imm, i32imm, GPR, GPR, 
    /* Select_Ri_64_32 */
    GPR32, GPR, i64imm, i64imm, GPR32, GPR32, 
    /* ADDR_SPACE_CAST */
    GPR, GPR, i64imm, i64imm, 
    /* ADD_ri */
    GPR, GPR, i64imm, 
    /* ADD_ri_32 */
    GPR32, GPR32, i32imm, 
    /* ADD_rr */
    GPR, GPR, GPR, 
    /* ADD_rr_32 */
    GPR32, GPR32, GPR32, 
    /* AND_ri */
    GPR, GPR, i64imm, 
    /* AND_ri_32 */
    GPR32, GPR32, i32imm, 
    /* AND_rr */
    GPR, GPR, GPR, 
    /* AND_rr_32 */
    GPR32, GPR32, GPR32, 
    /* BE16 */
    GPR, GPR, 
    /* BE32 */
    GPR, GPR, 
    /* BE64 */
    GPR, GPR, 
    /* BSWAP16 */
    GPR, GPR, 
    /* BSWAP32 */
    GPR, GPR, 
    /* BSWAP64 */
    GPR, GPR, 
    /* CMPXCHGD */
    GPR, s16imm, GPR, 
    /* CMPXCHGW32 */
    GPR, s16imm, GPR32, 
    /* CORE_LD32 */
    GPR32, u64imm, GPR, u64imm, 
    /* CORE_LD64 */
    GPR, u64imm, GPR, u64imm, 
    /* CORE_SHIFT */
    GPR, u64imm, GPR, u64imm, 
    /* CORE_ST */
    gpr_or_imm, u64imm, GPR, u64imm, 
    /* DIV_ri */
    GPR, GPR, i64imm, 
    /* DIV_ri_32 */
    GPR32, GPR32, i32imm, 
    /* DIV_rr */
    GPR, GPR, GPR, 
    /* DIV_rr_32 */
    GPR32, GPR32, GPR32, 
    /* JAL */
    calltarget, 
    /* JALX */
    GPR, 
    /* JCOND */
    brtarget, 
    /* JEQ_ri */
    GPR, i64imm, brtarget, 
    /* JEQ_ri_32 */
    GPR32, i32imm, brtarget, 
    /* JEQ_rr */
    GPR, GPR, brtarget, 
    /* JEQ_rr_32 */
    GPR32, GPR32, brtarget, 
    /* JMP */
    brtarget, 
    /* JMPL */
    brtarget, 
    /* JNE_ri */
    GPR, i64imm, brtarget, 
    /* JNE_ri_32 */
    GPR32, i32imm, brtarget, 
    /* JNE_rr */
    GPR, GPR, brtarget, 
    /* JNE_rr_32 */
    GPR32, GPR32, brtarget, 
    /* JSET_ri */
    GPR, i64imm, brtarget, 
    /* JSET_ri_32 */
    GPR32, i32imm, brtarget, 
    /* JSET_rr */
    GPR, GPR, brtarget, 
    /* JSET_rr_32 */
    GPR32, GPR32, brtarget, 
    /* JSGE_ri */
    GPR, i64imm, brtarget, 
    /* JSGE_ri_32 */
    GPR32, i32imm, brtarget, 
    /* JSGE_rr */
    GPR, GPR, brtarget, 
    /* JSGE_rr_32 */
    GPR32, GPR32, brtarget, 
    /* JSGT_ri */
    GPR, i64imm, brtarget, 
    /* JSGT_ri_32 */
    GPR32, i32imm, brtarget, 
    /* JSGT_rr */
    GPR, GPR, brtarget, 
    /* JSGT_rr_32 */
    GPR32, GPR32, brtarget, 
    /* JSLE_ri */
    GPR, i64imm, brtarget, 
    /* JSLE_ri_32 */
    GPR32, i32imm, brtarget, 
    /* JSLE_rr */
    GPR, GPR, brtarget, 
    /* JSLE_rr_32 */
    GPR32, GPR32, brtarget, 
    /* JSLT_ri */
    GPR, i64imm, brtarget, 
    /* JSLT_ri_32 */
    GPR32, i32imm, brtarget, 
    /* JSLT_rr */
    GPR, GPR, brtarget, 
    /* JSLT_rr_32 */
    GPR32, GPR32, brtarget, 
    /* JUGE_ri */
    GPR, i64imm, brtarget, 
    /* JUGE_ri_32 */
    GPR32, i32imm, brtarget, 
    /* JUGE_rr */
    GPR, GPR, brtarget, 
    /* JUGE_rr_32 */
    GPR32, GPR32, brtarget, 
    /* JUGT_ri */
    GPR, i64imm, brtarget, 
    /* JUGT_ri_32 */
    GPR32, i32imm, brtarget, 
    /* JUGT_rr */
    GPR, GPR, brtarget, 
    /* JUGT_rr_32 */
    GPR32, GPR32, brtarget, 
    /* JULE_ri */
    GPR, i64imm, brtarget, 
    /* JULE_ri_32 */
    GPR32, i32imm, brtarget, 
    /* JULE_rr */
    GPR, GPR, brtarget, 
    /* JULE_rr_32 */
    GPR32, GPR32, brtarget, 
    /* JULT_ri */
    GPR, i64imm, brtarget, 
    /* JULT_ri_32 */
    GPR32, i32imm, brtarget, 
    /* JULT_rr */
    GPR, GPR, brtarget, 
    /* JULT_rr_32 */
    GPR32, GPR32, brtarget, 
    /* LDB */
    GPR, GPR, s16imm, 
    /* LDB32 */
    GPR32, GPR, s16imm, 
    /* LDBSX */
    GPR, GPR, s16imm, 
    /* LDD */
    GPR, GPR, s16imm, 
    /* LDH */
    GPR, GPR, s16imm, 
    /* LDH32 */
    GPR32, GPR, s16imm, 
    /* LDHSX */
    GPR, GPR, s16imm, 
    /* LDW */
    GPR, GPR, s16imm, 
    /* LDW32 */
    GPR32, GPR, s16imm, 
    /* LDWSX */
    GPR, GPR, s16imm, 
    /* LD_ABS_B */
    GPR, i64imm, 
    /* LD_ABS_H */
    GPR, i64imm, 
    /* LD_ABS_W */
    GPR, i64imm, 
    /* LD_IND_B */
    GPR, GPR, 
    /* LD_IND_H */
    GPR, GPR, 
    /* LD_IND_W */
    GPR, GPR, 
    /* LD_imm64 */
    GPR, u64imm, 
    /* LD_pseudo */
    GPR, i64imm, u64imm, 
    /* LE16 */
    GPR, GPR, 
    /* LE32 */
    GPR, GPR, 
    /* LE64 */
    GPR, GPR, 
    /* MOD_ri */
    GPR, GPR, i64imm, 
    /* MOD_ri_32 */
    GPR32, GPR32, i32imm, 
    /* MOD_rr */
    GPR, GPR, GPR, 
    /* MOD_rr_32 */
    GPR32, GPR32, GPR32, 
    /* MOVSX_rr_16 */
    GPR, GPR, 
    /* MOVSX_rr_32 */
    GPR, GPR, 
    /* MOVSX_rr_32_16 */
    GPR32, GPR32, 
    /* MOVSX_rr_32_8 */
    GPR32, GPR32, 
    /* MOVSX_rr_8 */
    GPR, GPR, 
    /* MOV_32_64 */
    GPR, GPR32, 
    /* MOV_ri */
    GPR, i64imm, 
    /* MOV_ri_32 */
    GPR32, i32imm, 
    /* MOV_rr */
    GPR, GPR, 
    /* MOV_rr_32 */
    GPR32, GPR32, 
    /* MUL_ri */
    GPR, GPR, i64imm, 
    /* MUL_ri_32 */
    GPR32, GPR32, i32imm, 
    /* MUL_rr */
    GPR, GPR, GPR, 
    /* MUL_rr_32 */
    GPR32, GPR32, GPR32, 
    /* NEG_32 */
    GPR32, GPR32, 
    /* NEG_64 */
    GPR, GPR, 
    /* NOP */
    i32imm, 
    /* OR_ri */
    GPR, GPR, i64imm, 
    /* OR_ri_32 */
    GPR32, GPR32, i32imm, 
    /* OR_rr */
    GPR, GPR, GPR, 
    /* OR_rr_32 */
    GPR32, GPR32, GPR32, 
    /* RET */
    /* SDIV_ri */
    GPR, GPR, i64imm, 
    /* SDIV_ri_32 */
    GPR32, GPR32, i32imm, 
    /* SDIV_rr */
    GPR, GPR, GPR, 
    /* SDIV_rr_32 */
    GPR32, GPR32, GPR32, 
    /* SLL_ri */
    GPR, GPR, i64imm, 
    /* SLL_ri_32 */
    GPR32, GPR32, i32imm, 
    /* SLL_rr */
    GPR, GPR, GPR, 
    /* SLL_rr_32 */
    GPR32, GPR32, GPR32, 
    /* SMOD_ri */
    GPR, GPR, i64imm, 
    /* SMOD_ri_32 */
    GPR32, GPR32, i32imm, 
    /* SMOD_rr */
    GPR, GPR, GPR, 
    /* SMOD_rr_32 */
    GPR32, GPR32, GPR32, 
    /* SRA_ri */
    GPR, GPR, i64imm, 
    /* SRA_ri_32 */
    GPR32, GPR32, i32imm, 
    /* SRA_rr */
    GPR, GPR, GPR, 
    /* SRA_rr_32 */
    GPR32, GPR32, GPR32, 
    /* SRL_ri */
    GPR, GPR, i64imm, 
    /* SRL_ri_32 */
    GPR32, GPR32, i32imm, 
    /* SRL_rr */
    GPR, GPR, GPR, 
    /* SRL_rr_32 */
    GPR32, GPR32, GPR32, 
    /* STB */
    GPR, GPR, s16imm, 
    /* STB32 */
    GPR32, GPR, s16imm, 
    /* STB_imm */
    i64imm, GPR, s16imm, 
    /* STD */
    GPR, GPR, s16imm, 
    /* STD_imm */
    i64imm, GPR, s16imm, 
    /* STH */
    GPR, GPR, s16imm, 
    /* STH32 */
    GPR32, GPR, s16imm, 
    /* STH_imm */
    i64imm, GPR, s16imm, 
    /* STW */
    GPR, GPR, s16imm, 
    /* STW32 */
    GPR32, GPR, s16imm, 
    /* STW_imm */
    i64imm, GPR, s16imm, 
    /* SUB_ri */
    GPR, GPR, i64imm, 
    /* SUB_ri_32 */
    GPR32, GPR32, i32imm, 
    /* SUB_rr */
    GPR, GPR, GPR, 
    /* SUB_rr_32 */
    GPR32, GPR32, GPR32, 
    /* XADDD */
    GPR, GPR, s16imm, GPR, 
    /* XADDW */
    GPR, GPR, s16imm, GPR, 
    /* XADDW32 */
    GPR, GPR, s16imm, GPR32, 
    /* XANDD */
    GPR, GPR, s16imm, GPR, 
    /* XANDW32 */
    GPR, GPR, s16imm, GPR32, 
    /* XCHGD */
    GPR, GPR, s16imm, GPR, 
    /* XCHGW32 */
    GPR32, GPR, s16imm, GPR32, 
    /* XFADDD */
    GPR, GPR, s16imm, GPR, 
    /* XFADDW32 */
    GPR32, GPR, s16imm, GPR32, 
    /* XFANDD */
    GPR, GPR, s16imm, GPR, 
    /* XFANDW32 */
    GPR32, GPR, s16imm, GPR32, 
    /* XFORD */
    GPR, GPR, s16imm, GPR, 
    /* XFORW32 */
    GPR32, GPR, s16imm, GPR32, 
    /* XFXORD */
    GPR, GPR, s16imm, GPR, 
    /* XFXORW32 */
    GPR32, GPR, s16imm, GPR32, 
    /* XORD */
    GPR, GPR, s16imm, GPR, 
    /* XORW32 */
    GPR, GPR, s16imm, GPR32, 
    /* XOR_ri */
    GPR, GPR, i64imm, 
    /* XOR_ri_32 */
    GPR32, GPR32, i32imm, 
    /* XOR_rr */
    GPR, GPR, GPR, 
    /* XOR_rr_32 */
    GPR32, GPR32, GPR32, 
    /* XXORD */
    GPR, GPR, s16imm, GPR, 
    /* XXORW32 */
    GPR, GPR, s16imm, GPR32, 
  };
  return OpcodeOperandTypes[Offsets[Opcode] + OpIdx];
}
} // end namespace BPF
} // end namespace llvm
#endif // GET_INSTRINFO_OPERAND_TYPE

#ifdef GET_INSTRINFO_MEM_OPERAND_SIZE
#undef GET_INSTRINFO_MEM_OPERAND_SIZE
namespace llvm {
namespace BPF {
LLVM_READONLY
static int getMemOperandSize(int OpType) {
  switch (OpType) {
  default: return 0;
  }
}
} // end namespace BPF
} // end namespace llvm
#endif // GET_INSTRINFO_MEM_OPERAND_SIZE

#ifdef GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP
#undef GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP
namespace llvm {
namespace BPF {
LLVM_READONLY static unsigned
getLogicalOperandSize(uint16_t Opcode, uint16_t LogicalOpIdx) {
  return LogicalOpIdx;
}
LLVM_READONLY static inline unsigned
getLogicalOperandIdx(uint16_t Opcode, uint16_t LogicalOpIdx) {
  auto S = 0U;
  for (auto i = 0U; i < LogicalOpIdx; ++i)
    S += getLogicalOperandSize(Opcode, i);
  return S;
}
} // end namespace BPF
} // end namespace llvm
#endif // GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP

#ifdef GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP
#undef GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP
namespace llvm {
namespace BPF {
LLVM_READONLY static int
getLogicalOperandType(uint16_t Opcode, uint16_t LogicalOpIdx) {
  return -1;
}
} // end namespace BPF
} // end namespace llvm
#endif // GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP

#ifdef GET_INSTRINFO_MC_HELPER_DECLS
#undef GET_INSTRINFO_MC_HELPER_DECLS

namespace llvm {
class MCInst;
class FeatureBitset;

namespace BPF_MC {

void verifyInstructionPredicates(unsigned Opcode, const FeatureBitset &Features);

} // end namespace BPF_MC
} // end namespace llvm

#endif // GET_INSTRINFO_MC_HELPER_DECLS

#ifdef GET_INSTRINFO_MC_HELPERS
#undef GET_INSTRINFO_MC_HELPERS

namespace llvm {
namespace BPF_MC {

} // end namespace BPF_MC
} // end namespace llvm

#endif // GET_GENISTRINFO_MC_HELPERS

#if (defined(ENABLE_INSTR_PREDICATE_VERIFIER) && !defined(NDEBUG)) ||\
    defined(GET_AVAILABLE_OPCODE_CHECKER)
#define GET_COMPUTE_FEATURES
#endif
#ifdef GET_COMPUTE_FEATURES
#undef GET_COMPUTE_FEATURES
namespace llvm {
namespace BPF_MC {

// Bits for subtarget features that participate in instruction matching.
enum SubtargetFeatureBits : uint8_t {
};

inline FeatureBitset computeAvailableFeatures(const FeatureBitset &FB) {
  FeatureBitset Features;
  return Features;
}

inline FeatureBitset computeRequiredFeatures(unsigned Opcode) {
  enum : uint8_t {
    CEFBS_None,
  };

  static constexpr FeatureBitset FeatureBitsets[] = {
    {}, // CEFBS_None
  };
  static constexpr uint8_t RequiredFeaturesRefs[] = {
    CEFBS_None, // PHI = 0
    CEFBS_None, // INLINEASM = 1
    CEFBS_None, // INLINEASM_BR = 2
    CEFBS_None, // CFI_INSTRUCTION = 3
    CEFBS_None, // EH_LABEL = 4
    CEFBS_None, // GC_LABEL = 5
    CEFBS_None, // ANNOTATION_LABEL = 6
    CEFBS_None, // KILL = 7
    CEFBS_None, // EXTRACT_SUBREG = 8
    CEFBS_None, // INSERT_SUBREG = 9
    CEFBS_None, // IMPLICIT_DEF = 10
    CEFBS_None, // SUBREG_TO_REG = 11
    CEFBS_None, // COPY_TO_REGCLASS = 12
    CEFBS_None, // DBG_VALUE = 13
    CEFBS_None, // DBG_VALUE_LIST = 14
    CEFBS_None, // DBG_INSTR_REF = 15
    CEFBS_None, // DBG_PHI = 16
    CEFBS_None, // DBG_LABEL = 17
    CEFBS_None, // REG_SEQUENCE = 18
    CEFBS_None, // COPY = 19
    CEFBS_None, // BUNDLE = 20
    CEFBS_None, // LIFETIME_START = 21
    CEFBS_None, // LIFETIME_END = 22
    CEFBS_None, // PSEUDO_PROBE = 23
    CEFBS_None, // ARITH_FENCE = 24
    CEFBS_None, // STACKMAP = 25
    CEFBS_None, // FENTRY_CALL = 26
    CEFBS_None, // PATCHPOINT = 27
    CEFBS_None, // LOAD_STACK_GUARD = 28
    CEFBS_None, // PREALLOCATED_SETUP = 29
    CEFBS_None, // PREALLOCATED_ARG = 30
    CEFBS_None, // STATEPOINT = 31
    CEFBS_None, // LOCAL_ESCAPE = 32
    CEFBS_None, // FAULTING_OP = 33
    CEFBS_None, // PATCHABLE_OP = 34
    CEFBS_None, // PATCHABLE_FUNCTION_ENTER = 35
    CEFBS_None, // PATCHABLE_RET = 36
    CEFBS_None, // PATCHABLE_FUNCTION_EXIT = 37
    CEFBS_None, // PATCHABLE_TAIL_CALL = 38
    CEFBS_None, // PATCHABLE_EVENT_CALL = 39
    CEFBS_None, // PATCHABLE_TYPED_EVENT_CALL = 40
    CEFBS_None, // ICALL_BRANCH_FUNNEL = 41
    CEFBS_None, // FAKE_USE = 42
    CEFBS_None, // MEMBARRIER = 43
    CEFBS_None, // JUMP_TABLE_DEBUG_INFO = 44
    CEFBS_None, // CONVERGENCECTRL_ENTRY = 45
    CEFBS_None, // CONVERGENCECTRL_ANCHOR = 46
    CEFBS_None, // CONVERGENCECTRL_LOOP = 47
    CEFBS_None, // CONVERGENCECTRL_GLUE = 48
    CEFBS_None, // G_ASSERT_SEXT = 49
    CEFBS_None, // G_ASSERT_ZEXT = 50
    CEFBS_None, // G_ASSERT_ALIGN = 51
    CEFBS_None, // G_ADD = 52
    CEFBS_None, // G_SUB = 53
    CEFBS_None, // G_MUL = 54
    CEFBS_None, // G_SDIV = 55
    CEFBS_None, // G_UDIV = 56
    CEFBS_None, // G_SREM = 57
    CEFBS_None, // G_UREM = 58
    CEFBS_None, // G_SDIVREM = 59
    CEFBS_None, // G_UDIVREM = 60
    CEFBS_None, // G_AND = 61
    CEFBS_None, // G_OR = 62
    CEFBS_None, // G_XOR = 63
    CEFBS_None, // G_IMPLICIT_DEF = 64
    CEFBS_None, // G_PHI = 65
    CEFBS_None, // G_FRAME_INDEX = 66
    CEFBS_None, // G_GLOBAL_VALUE = 67
    CEFBS_None, // G_PTRAUTH_GLOBAL_VALUE = 68
    CEFBS_None, // G_CONSTANT_POOL = 69
    CEFBS_None, // G_EXTRACT = 70
    CEFBS_None, // G_UNMERGE_VALUES = 71
    CEFBS_None, // G_INSERT = 72
    CEFBS_None, // G_MERGE_VALUES = 73
    CEFBS_None, // G_BUILD_VECTOR = 74
    CEFBS_None, // G_BUILD_VECTOR_TRUNC = 75
    CEFBS_None, // G_CONCAT_VECTORS = 76
    CEFBS_None, // G_PTRTOINT = 77
    CEFBS_None, // G_INTTOPTR = 78
    CEFBS_None, // G_BITCAST = 79
    CEFBS_None, // G_FREEZE = 80
    CEFBS_None, // G_CONSTANT_FOLD_BARRIER = 81
    CEFBS_None, // G_INTRINSIC_FPTRUNC_ROUND = 82
    CEFBS_None, // G_INTRINSIC_TRUNC = 83
    CEFBS_None, // G_INTRINSIC_ROUND = 84
    CEFBS_None, // G_INTRINSIC_LRINT = 85
    CEFBS_None, // G_INTRINSIC_LLRINT = 86
    CEFBS_None, // G_INTRINSIC_ROUNDEVEN = 87
    CEFBS_None, // G_READCYCLECOUNTER = 88
    CEFBS_None, // G_READSTEADYCOUNTER = 89
    CEFBS_None, // G_LOAD = 90
    CEFBS_None, // G_SEXTLOAD = 91
    CEFBS_None, // G_ZEXTLOAD = 92
    CEFBS_None, // G_INDEXED_LOAD = 93
    CEFBS_None, // G_INDEXED_SEXTLOAD = 94
    CEFBS_None, // G_INDEXED_ZEXTLOAD = 95
    CEFBS_None, // G_STORE = 96
    CEFBS_None, // G_INDEXED_STORE = 97
    CEFBS_None, // G_ATOMIC_CMPXCHG_WITH_SUCCESS = 98
    CEFBS_None, // G_ATOMIC_CMPXCHG = 99
    CEFBS_None, // G_ATOMICRMW_XCHG = 100
    CEFBS_None, // G_ATOMICRMW_ADD = 101
    CEFBS_None, // G_ATOMICRMW_SUB = 102
    CEFBS_None, // G_ATOMICRMW_AND = 103
    CEFBS_None, // G_ATOMICRMW_NAND = 104
    CEFBS_None, // G_ATOMICRMW_OR = 105
    CEFBS_None, // G_ATOMICRMW_XOR = 106
    CEFBS_None, // G_ATOMICRMW_MAX = 107
    CEFBS_None, // G_ATOMICRMW_MIN = 108
    CEFBS_None, // G_ATOMICRMW_UMAX = 109
    CEFBS_None, // G_ATOMICRMW_UMIN = 110
    CEFBS_None, // G_ATOMICRMW_FADD = 111
    CEFBS_None, // G_ATOMICRMW_FSUB = 112
    CEFBS_None, // G_ATOMICRMW_FMAX = 113
    CEFBS_None, // G_ATOMICRMW_FMIN = 114
    CEFBS_None, // G_ATOMICRMW_UINC_WRAP = 115
    CEFBS_None, // G_ATOMICRMW_UDEC_WRAP = 116
    CEFBS_None, // G_FENCE = 117
    CEFBS_None, // G_PREFETCH = 118
    CEFBS_None, // G_BRCOND = 119
    CEFBS_None, // G_BRINDIRECT = 120
    CEFBS_None, // G_INVOKE_REGION_START = 121
    CEFBS_None, // G_INTRINSIC = 122
    CEFBS_None, // G_INTRINSIC_W_SIDE_EFFECTS = 123
    CEFBS_None, // G_INTRINSIC_CONVERGENT = 124
    CEFBS_None, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS = 125
    CEFBS_None, // G_ANYEXT = 126
    CEFBS_None, // G_TRUNC = 127
    CEFBS_None, // G_CONSTANT = 128
    CEFBS_None, // G_FCONSTANT = 129
    CEFBS_None, // G_VASTART = 130
    CEFBS_None, // G_VAARG = 131
    CEFBS_None, // G_SEXT = 132
    CEFBS_None, // G_SEXT_INREG = 133
    CEFBS_None, // G_ZEXT = 134
    CEFBS_None, // G_SHL = 135
    CEFBS_None, // G_LSHR = 136
    CEFBS_None, // G_ASHR = 137
    CEFBS_None, // G_FSHL = 138
    CEFBS_None, // G_FSHR = 139
    CEFBS_None, // G_ROTR = 140
    CEFBS_None, // G_ROTL = 141
    CEFBS_None, // G_ICMP = 142
    CEFBS_None, // G_FCMP = 143
    CEFBS_None, // G_SCMP = 144
    CEFBS_None, // G_UCMP = 145
    CEFBS_None, // G_SELECT = 146
    CEFBS_None, // G_UADDO = 147
    CEFBS_None, // G_UADDE = 148
    CEFBS_None, // G_USUBO = 149
    CEFBS_None, // G_USUBE = 150
    CEFBS_None, // G_SADDO = 151
    CEFBS_None, // G_SADDE = 152
    CEFBS_None, // G_SSUBO = 153
    CEFBS_None, // G_SSUBE = 154
    CEFBS_None, // G_UMULO = 155
    CEFBS_None, // G_SMULO = 156
    CEFBS_None, // G_UMULH = 157
    CEFBS_None, // G_SMULH = 158
    CEFBS_None, // G_UADDSAT = 159
    CEFBS_None, // G_SADDSAT = 160
    CEFBS_None, // G_USUBSAT = 161
    CEFBS_None, // G_SSUBSAT = 162
    CEFBS_None, // G_USHLSAT = 163
    CEFBS_None, // G_SSHLSAT = 164
    CEFBS_None, // G_SMULFIX = 165
    CEFBS_None, // G_UMULFIX = 166
    CEFBS_None, // G_SMULFIXSAT = 167
    CEFBS_None, // G_UMULFIXSAT = 168
    CEFBS_None, // G_SDIVFIX = 169
    CEFBS_None, // G_UDIVFIX = 170
    CEFBS_None, // G_SDIVFIXSAT = 171
    CEFBS_None, // G_UDIVFIXSAT = 172
    CEFBS_None, // G_FADD = 173
    CEFBS_None, // G_FSUB = 174
    CEFBS_None, // G_FMUL = 175
    CEFBS_None, // G_FMA = 176
    CEFBS_None, // G_FMAD = 177
    CEFBS_None, // G_FDIV = 178
    CEFBS_None, // G_FREM = 179
    CEFBS_None, // G_FPOW = 180
    CEFBS_None, // G_FPOWI = 181
    CEFBS_None, // G_FEXP = 182
    CEFBS_None, // G_FEXP2 = 183
    CEFBS_None, // G_FEXP10 = 184
    CEFBS_None, // G_FLOG = 185
    CEFBS_None, // G_FLOG2 = 186
    CEFBS_None, // G_FLOG10 = 187
    CEFBS_None, // G_FLDEXP = 188
    CEFBS_None, // G_FFREXP = 189
    CEFBS_None, // G_FNEG = 190
    CEFBS_None, // G_FPEXT = 191
    CEFBS_None, // G_FPTRUNC = 192
    CEFBS_None, // G_FPTOSI = 193
    CEFBS_None, // G_FPTOUI = 194
    CEFBS_None, // G_SITOFP = 195
    CEFBS_None, // G_UITOFP = 196
    CEFBS_None, // G_FABS = 197
    CEFBS_None, // G_FCOPYSIGN = 198
    CEFBS_None, // G_IS_FPCLASS = 199
    CEFBS_None, // G_FCANONICALIZE = 200
    CEFBS_None, // G_FMINNUM = 201
    CEFBS_None, // G_FMAXNUM = 202
    CEFBS_None, // G_FMINNUM_IEEE = 203
    CEFBS_None, // G_FMAXNUM_IEEE = 204
    CEFBS_None, // G_FMINIMUM = 205
    CEFBS_None, // G_FMAXIMUM = 206
    CEFBS_None, // G_GET_FPENV = 207
    CEFBS_None, // G_SET_FPENV = 208
    CEFBS_None, // G_RESET_FPENV = 209
    CEFBS_None, // G_GET_FPMODE = 210
    CEFBS_None, // G_SET_FPMODE = 211
    CEFBS_None, // G_RESET_FPMODE = 212
    CEFBS_None, // G_PTR_ADD = 213
    CEFBS_None, // G_PTRMASK = 214
    CEFBS_None, // G_SMIN = 215
    CEFBS_None, // G_SMAX = 216
    CEFBS_None, // G_UMIN = 217
    CEFBS_None, // G_UMAX = 218
    CEFBS_None, // G_ABS = 219
    CEFBS_None, // G_LROUND = 220
    CEFBS_None, // G_LLROUND = 221
    CEFBS_None, // G_BR = 222
    CEFBS_None, // G_BRJT = 223
    CEFBS_None, // G_VSCALE = 224
    CEFBS_None, // G_INSERT_SUBVECTOR = 225
    CEFBS_None, // G_EXTRACT_SUBVECTOR = 226
    CEFBS_None, // G_INSERT_VECTOR_ELT = 227
    CEFBS_None, // G_EXTRACT_VECTOR_ELT = 228
    CEFBS_None, // G_SHUFFLE_VECTOR = 229
    CEFBS_None, // G_SPLAT_VECTOR = 230
    CEFBS_None, // G_VECTOR_COMPRESS = 231
    CEFBS_None, // G_CTTZ = 232
    CEFBS_None, // G_CTTZ_ZERO_UNDEF = 233
    CEFBS_None, // G_CTLZ = 234
    CEFBS_None, // G_CTLZ_ZERO_UNDEF = 235
    CEFBS_None, // G_CTPOP = 236
    CEFBS_None, // G_BSWAP = 237
    CEFBS_None, // G_BITREVERSE = 238
    CEFBS_None, // G_FCEIL = 239
    CEFBS_None, // G_FCOS = 240
    CEFBS_None, // G_FSIN = 241
    CEFBS_None, // G_FTAN = 242
    CEFBS_None, // G_FACOS = 243
    CEFBS_None, // G_FASIN = 244
    CEFBS_None, // G_FATAN = 245
    CEFBS_None, // G_FCOSH = 246
    CEFBS_None, // G_FSINH = 247
    CEFBS_None, // G_FTANH = 248
    CEFBS_None, // G_FSQRT = 249
    CEFBS_None, // G_FFLOOR = 250
    CEFBS_None, // G_FRINT = 251
    CEFBS_None, // G_FNEARBYINT = 252
    CEFBS_None, // G_ADDRSPACE_CAST = 253
    CEFBS_None, // G_BLOCK_ADDR = 254
    CEFBS_None, // G_JUMP_TABLE = 255
    CEFBS_None, // G_DYN_STACKALLOC = 256
    CEFBS_None, // G_STACKSAVE = 257
    CEFBS_None, // G_STACKRESTORE = 258
    CEFBS_None, // G_STRICT_FADD = 259
    CEFBS_None, // G_STRICT_FSUB = 260
    CEFBS_None, // G_STRICT_FMUL = 261
    CEFBS_None, // G_STRICT_FDIV = 262
    CEFBS_None, // G_STRICT_FREM = 263
    CEFBS_None, // G_STRICT_FMA = 264
    CEFBS_None, // G_STRICT_FSQRT = 265
    CEFBS_None, // G_STRICT_FLDEXP = 266
    CEFBS_None, // G_READ_REGISTER = 267
    CEFBS_None, // G_WRITE_REGISTER = 268
    CEFBS_None, // G_MEMCPY = 269
    CEFBS_None, // G_MEMCPY_INLINE = 270
    CEFBS_None, // G_MEMMOVE = 271
    CEFBS_None, // G_MEMSET = 272
    CEFBS_None, // G_BZERO = 273
    CEFBS_None, // G_TRAP = 274
    CEFBS_None, // G_DEBUGTRAP = 275
    CEFBS_None, // G_UBSANTRAP = 276
    CEFBS_None, // G_VECREDUCE_SEQ_FADD = 277
    CEFBS_None, // G_VECREDUCE_SEQ_FMUL = 278
    CEFBS_None, // G_VECREDUCE_FADD = 279
    CEFBS_None, // G_VECREDUCE_FMUL = 280
    CEFBS_None, // G_VECREDUCE_FMAX = 281
    CEFBS_None, // G_VECREDUCE_FMIN = 282
    CEFBS_None, // G_VECREDUCE_FMAXIMUM = 283
    CEFBS_None, // G_VECREDUCE_FMINIMUM = 284
    CEFBS_None, // G_VECREDUCE_ADD = 285
    CEFBS_None, // G_VECREDUCE_MUL = 286
    CEFBS_None, // G_VECREDUCE_AND = 287
    CEFBS_None, // G_VECREDUCE_OR = 288
    CEFBS_None, // G_VECREDUCE_XOR = 289
    CEFBS_None, // G_VECREDUCE_SMAX = 290
    CEFBS_None, // G_VECREDUCE_SMIN = 291
    CEFBS_None, // G_VECREDUCE_UMAX = 292
    CEFBS_None, // G_VECREDUCE_UMIN = 293
    CEFBS_None, // G_SBFX = 294
    CEFBS_None, // G_UBFX = 295
    CEFBS_None, // ADJCALLSTACKDOWN = 296
    CEFBS_None, // ADJCALLSTACKUP = 297
    CEFBS_None, // FI_ri = 298
    CEFBS_None, // MEMCPY = 299
    CEFBS_None, // Select = 300
    CEFBS_None, // Select_32 = 301
    CEFBS_None, // Select_32_64 = 302
    CEFBS_None, // Select_64_32 = 303
    CEFBS_None, // Select_Ri = 304
    CEFBS_None, // Select_Ri_32 = 305
    CEFBS_None, // Select_Ri_32_64 = 306
    CEFBS_None, // Select_Ri_64_32 = 307
    CEFBS_None, // ADDR_SPACE_CAST = 308
    CEFBS_None, // ADD_ri = 309
    CEFBS_None, // ADD_ri_32 = 310
    CEFBS_None, // ADD_rr = 311
    CEFBS_None, // ADD_rr_32 = 312
    CEFBS_None, // AND_ri = 313
    CEFBS_None, // AND_ri_32 = 314
    CEFBS_None, // AND_rr = 315
    CEFBS_None, // AND_rr_32 = 316
    CEFBS_None, // BE16 = 317
    CEFBS_None, // BE32 = 318
    CEFBS_None, // BE64 = 319
    CEFBS_None, // BSWAP16 = 320
    CEFBS_None, // BSWAP32 = 321
    CEFBS_None, // BSWAP64 = 322
    CEFBS_None, // CMPXCHGD = 323
    CEFBS_None, // CMPXCHGW32 = 324
    CEFBS_None, // CORE_LD32 = 325
    CEFBS_None, // CORE_LD64 = 326
    CEFBS_None, // CORE_SHIFT = 327
    CEFBS_None, // CORE_ST = 328
    CEFBS_None, // DIV_ri = 329
    CEFBS_None, // DIV_ri_32 = 330
    CEFBS_None, // DIV_rr = 331
    CEFBS_None, // DIV_rr_32 = 332
    CEFBS_None, // JAL = 333
    CEFBS_None, // JALX = 334
    CEFBS_None, // JCOND = 335
    CEFBS_None, // JEQ_ri = 336
    CEFBS_None, // JEQ_ri_32 = 337
    CEFBS_None, // JEQ_rr = 338
    CEFBS_None, // JEQ_rr_32 = 339
    CEFBS_None, // JMP = 340
    CEFBS_None, // JMPL = 341
    CEFBS_None, // JNE_ri = 342
    CEFBS_None, // JNE_ri_32 = 343
    CEFBS_None, // JNE_rr = 344
    CEFBS_None, // JNE_rr_32 = 345
    CEFBS_None, // JSET_ri = 346
    CEFBS_None, // JSET_ri_32 = 347
    CEFBS_None, // JSET_rr = 348
    CEFBS_None, // JSET_rr_32 = 349
    CEFBS_None, // JSGE_ri = 350
    CEFBS_None, // JSGE_ri_32 = 351
    CEFBS_None, // JSGE_rr = 352
    CEFBS_None, // JSGE_rr_32 = 353
    CEFBS_None, // JSGT_ri = 354
    CEFBS_None, // JSGT_ri_32 = 355
    CEFBS_None, // JSGT_rr = 356
    CEFBS_None, // JSGT_rr_32 = 357
    CEFBS_None, // JSLE_ri = 358
    CEFBS_None, // JSLE_ri_32 = 359
    CEFBS_None, // JSLE_rr = 360
    CEFBS_None, // JSLE_rr_32 = 361
    CEFBS_None, // JSLT_ri = 362
    CEFBS_None, // JSLT_ri_32 = 363
    CEFBS_None, // JSLT_rr = 364
    CEFBS_None, // JSLT_rr_32 = 365
    CEFBS_None, // JUGE_ri = 366
    CEFBS_None, // JUGE_ri_32 = 367
    CEFBS_None, // JUGE_rr = 368
    CEFBS_None, // JUGE_rr_32 = 369
    CEFBS_None, // JUGT_ri = 370
    CEFBS_None, // JUGT_ri_32 = 371
    CEFBS_None, // JUGT_rr = 372
    CEFBS_None, // JUGT_rr_32 = 373
    CEFBS_None, // JULE_ri = 374
    CEFBS_None, // JULE_ri_32 = 375
    CEFBS_None, // JULE_rr = 376
    CEFBS_None, // JULE_rr_32 = 377
    CEFBS_None, // JULT_ri = 378
    CEFBS_None, // JULT_ri_32 = 379
    CEFBS_None, // JULT_rr = 380
    CEFBS_None, // JULT_rr_32 = 381
    CEFBS_None, // LDB = 382
    CEFBS_None, // LDB32 = 383
    CEFBS_None, // LDBSX = 384
    CEFBS_None, // LDD = 385
    CEFBS_None, // LDH = 386
    CEFBS_None, // LDH32 = 387
    CEFBS_None, // LDHSX = 388
    CEFBS_None, // LDW = 389
    CEFBS_None, // LDW32 = 390
    CEFBS_None, // LDWSX = 391
    CEFBS_None, // LD_ABS_B = 392
    CEFBS_None, // LD_ABS_H = 393
    CEFBS_None, // LD_ABS_W = 394
    CEFBS_None, // LD_IND_B = 395
    CEFBS_None, // LD_IND_H = 396
    CEFBS_None, // LD_IND_W = 397
    CEFBS_None, // LD_imm64 = 398
    CEFBS_None, // LD_pseudo = 399
    CEFBS_None, // LE16 = 400
    CEFBS_None, // LE32 = 401
    CEFBS_None, // LE64 = 402
    CEFBS_None, // MOD_ri = 403
    CEFBS_None, // MOD_ri_32 = 404
    CEFBS_None, // MOD_rr = 405
    CEFBS_None, // MOD_rr_32 = 406
    CEFBS_None, // MOVSX_rr_16 = 407
    CEFBS_None, // MOVSX_rr_32 = 408
    CEFBS_None, // MOVSX_rr_32_16 = 409
    CEFBS_None, // MOVSX_rr_32_8 = 410
    CEFBS_None, // MOVSX_rr_8 = 411
    CEFBS_None, // MOV_32_64 = 412
    CEFBS_None, // MOV_ri = 413
    CEFBS_None, // MOV_ri_32 = 414
    CEFBS_None, // MOV_rr = 415
    CEFBS_None, // MOV_rr_32 = 416
    CEFBS_None, // MUL_ri = 417
    CEFBS_None, // MUL_ri_32 = 418
    CEFBS_None, // MUL_rr = 419
    CEFBS_None, // MUL_rr_32 = 420
    CEFBS_None, // NEG_32 = 421
    CEFBS_None, // NEG_64 = 422
    CEFBS_None, // NOP = 423
    CEFBS_None, // OR_ri = 424
    CEFBS_None, // OR_ri_32 = 425
    CEFBS_None, // OR_rr = 426
    CEFBS_None, // OR_rr_32 = 427
    CEFBS_None, // RET = 428
    CEFBS_None, // SDIV_ri = 429
    CEFBS_None, // SDIV_ri_32 = 430
    CEFBS_None, // SDIV_rr = 431
    CEFBS_None, // SDIV_rr_32 = 432
    CEFBS_None, // SLL_ri = 433
    CEFBS_None, // SLL_ri_32 = 434
    CEFBS_None, // SLL_rr = 435
    CEFBS_None, // SLL_rr_32 = 436
    CEFBS_None, // SMOD_ri = 437
    CEFBS_None, // SMOD_ri_32 = 438
    CEFBS_None, // SMOD_rr = 439
    CEFBS_None, // SMOD_rr_32 = 440
    CEFBS_None, // SRA_ri = 441
    CEFBS_None, // SRA_ri_32 = 442
    CEFBS_None, // SRA_rr = 443
    CEFBS_None, // SRA_rr_32 = 444
    CEFBS_None, // SRL_ri = 445
    CEFBS_None, // SRL_ri_32 = 446
    CEFBS_None, // SRL_rr = 447
    CEFBS_None, // SRL_rr_32 = 448
    CEFBS_None, // STB = 449
    CEFBS_None, // STB32 = 450
    CEFBS_None, // STB_imm = 451
    CEFBS_None, // STD = 452
    CEFBS_None, // STD_imm = 453
    CEFBS_None, // STH = 454
    CEFBS_None, // STH32 = 455
    CEFBS_None, // STH_imm = 456
    CEFBS_None, // STW = 457
    CEFBS_None, // STW32 = 458
    CEFBS_None, // STW_imm = 459
    CEFBS_None, // SUB_ri = 460
    CEFBS_None, // SUB_ri_32 = 461
    CEFBS_None, // SUB_rr = 462
    CEFBS_None, // SUB_rr_32 = 463
    CEFBS_None, // XADDD = 464
    CEFBS_None, // XADDW = 465
    CEFBS_None, // XADDW32 = 466
    CEFBS_None, // XANDD = 467
    CEFBS_None, // XANDW32 = 468
    CEFBS_None, // XCHGD = 469
    CEFBS_None, // XCHGW32 = 470
    CEFBS_None, // XFADDD = 471
    CEFBS_None, // XFADDW32 = 472
    CEFBS_None, // XFANDD = 473
    CEFBS_None, // XFANDW32 = 474
    CEFBS_None, // XFORD = 475
    CEFBS_None, // XFORW32 = 476
    CEFBS_None, // XFXORD = 477
    CEFBS_None, // XFXORW32 = 478
    CEFBS_None, // XORD = 479
    CEFBS_None, // XORW32 = 480
    CEFBS_None, // XOR_ri = 481
    CEFBS_None, // XOR_ri_32 = 482
    CEFBS_None, // XOR_rr = 483
    CEFBS_None, // XOR_rr_32 = 484
    CEFBS_None, // XXORD = 485
    CEFBS_None, // XXORW32 = 486
  };

  assert(Opcode < 487);
  return FeatureBitsets[RequiredFeaturesRefs[Opcode]];
}

} // end namespace BPF_MC
} // end namespace llvm
#endif // GET_COMPUTE_FEATURES

#ifdef GET_AVAILABLE_OPCODE_CHECKER
#undef GET_AVAILABLE_OPCODE_CHECKER
namespace llvm {
namespace BPF_MC {
bool isOpcodeAvailable(unsigned Opcode, const FeatureBitset &Features) {
  FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
  FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
  FeatureBitset MissingFeatures =
      (AvailableFeatures & RequiredFeatures) ^
      RequiredFeatures;
  return !MissingFeatures.any();
}
} // end namespace BPF_MC
} // end namespace llvm
#endif // GET_AVAILABLE_OPCODE_CHECKER

#ifdef ENABLE_INSTR_PREDICATE_VERIFIER
#undef ENABLE_INSTR_PREDICATE_VERIFIER
#include <sstream>

namespace llvm {
namespace BPF_MC {

#ifndef NDEBUG
static const char *SubtargetFeatureNames[] = {
  nullptr
};

#endif // NDEBUG

void verifyInstructionPredicates(
    unsigned Opcode, const FeatureBitset &Features) {
#ifndef NDEBUG
  FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
  FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
  FeatureBitset MissingFeatures =
      (AvailableFeatures & RequiredFeatures) ^
      RequiredFeatures;
  if (MissingFeatures.any()) {
    std::ostringstream Msg;
    Msg << "Attempting to emit " << &BPFInstrNameData[BPFInstrNameIndices[Opcode]]
        << " instruction but the ";
    for (unsigned i = 0, e = MissingFeatures.size(); i != e; ++i)
      if (MissingFeatures.test(i))
        Msg << SubtargetFeatureNames[i] << " ";
    Msg << "predicate(s) are not met";
    report_fatal_error(Msg.str().c_str());
  }
#endif // NDEBUG
}
} // end namespace BPF_MC
} // end namespace llvm
#endif // ENABLE_INSTR_PREDICATE_VERIFIER