llvm/lib/Target/Hexagon/HexagonGenAsmWriter.inc

/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
|*                                                                            *|
|* Assembly Writer Source Fragment                                            *|
|*                                                                            *|
|* Automatically generated file, do not edit!                                 *|
|* From: Hexagon.td                                                           *|
|*                                                                            *|
\*===----------------------------------------------------------------------===*/

/// getMnemonic - This method is automatically generated by tablegen
/// from the instruction set description.
std::pair<const char *, uint64_t> HexagonInstPrinter::getMnemonic(const MCInst *MI) { … }
/// printInstruction - This method is automatically generated by tablegen
/// from the instruction set description.
LLVM_NO_PROFILE_INSTRUMENT_FUNCTION
void HexagonInstPrinter::printInstruction(const MCInst *MI, uint64_t Address, raw_ostream &O) { … }


/// getRegisterName - This method is automatically generated by tblgen
/// from the register set description.  This returns the assembler name
/// for the specified register.
const char *HexagonInstPrinter::getRegisterName(MCRegister Reg) { … }

#ifdef PRINT_ALIAS_INSTR
#undef PRINT_ALIAS_INSTR

bool HexagonInstPrinter::printAliasInstr(const MCInst *MI, uint64_t Address, raw_ostream &OS) {
  static const PatternsForOpcode OpToPatterns[] = {
    {Hexagon::A2_andir, 0, 1 },
    {Hexagon::A2_paddif, 1, 1 },
    {Hexagon::A2_paddifnew, 2, 1 },
    {Hexagon::A2_paddit, 3, 1 },
    {Hexagon::A2_padditnew, 4, 1 },
    {Hexagon::A2_subri, 5, 2 },
    {Hexagon::A2_vaddub, 7, 1 },
    {Hexagon::A2_vsubub, 8, 1 },
    {Hexagon::C2_cmpgt, 9, 1 },
    {Hexagon::C2_cmpgtu, 10, 1 },
    {Hexagon::C2_or, 11, 1 },
    {Hexagon::J2_jumpf, 12, 1 },
    {Hexagon::J2_jumprf, 13, 1 },
    {Hexagon::J2_jumprt, 14, 1 },
    {Hexagon::J2_jumpt, 15, 1 },
    {Hexagon::J2_trap1, 16, 1 },
    {Hexagon::L2_deallocframe, 17, 1 },
    {Hexagon::L2_loadalignb_io, 18, 1 },
    {Hexagon::L2_loadalignh_io, 19, 1 },
    {Hexagon::L2_loadbsw2_io, 20, 1 },
    {Hexagon::L2_loadbsw4_io, 21, 1 },
    {Hexagon::L2_loadbzw2_io, 22, 1 },
    {Hexagon::L2_loadbzw4_io, 23, 1 },
    {Hexagon::L2_loadrb_io, 24, 1 },
    {Hexagon::L2_loadrd_io, 25, 1 },
    {Hexagon::L2_loadrh_io, 26, 1 },
    {Hexagon::L2_loadri_io, 27, 1 },
    {Hexagon::L2_loadrub_io, 28, 1 },
    {Hexagon::L2_loadruh_io, 29, 1 },
    {Hexagon::L2_ploadrbf_io, 30, 1 },
    {Hexagon::L2_ploadrbfnew_io, 31, 1 },
    {Hexagon::L2_ploadrbt_io, 32, 1 },
    {Hexagon::L2_ploadrbtnew_io, 33, 1 },
    {Hexagon::L2_ploadrdf_io, 34, 1 },
    {Hexagon::L2_ploadrdfnew_io, 35, 1 },
    {Hexagon::L2_ploadrdt_io, 36, 1 },
    {Hexagon::L2_ploadrdtnew_io, 37, 1 },
    {Hexagon::L2_ploadrhf_io, 38, 1 },
    {Hexagon::L2_ploadrhfnew_io, 39, 1 },
    {Hexagon::L2_ploadrht_io, 40, 1 },
    {Hexagon::L2_ploadrhtnew_io, 41, 1 },
    {Hexagon::L2_ploadrif_io, 42, 1 },
    {Hexagon::L2_ploadrifnew_io, 43, 1 },
    {Hexagon::L2_ploadrit_io, 44, 1 },
    {Hexagon::L2_ploadritnew_io, 45, 1 },
    {Hexagon::L2_ploadrubf_io, 46, 1 },
    {Hexagon::L2_ploadrubfnew_io, 47, 1 },
    {Hexagon::L2_ploadrubt_io, 48, 1 },
    {Hexagon::L2_ploadrubtnew_io, 49, 1 },
    {Hexagon::L2_ploadruhf_io, 50, 1 },
    {Hexagon::L2_ploadruhfnew_io, 51, 1 },
    {Hexagon::L2_ploadruht_io, 52, 1 },
    {Hexagon::L2_ploadruhtnew_io, 53, 1 },
    {Hexagon::L4_add_memopb_io, 54, 1 },
    {Hexagon::L4_add_memoph_io, 55, 1 },
    {Hexagon::L4_add_memopw_io, 56, 1 },
    {Hexagon::L4_and_memopb_io, 57, 1 },
    {Hexagon::L4_and_memoph_io, 58, 1 },
    {Hexagon::L4_and_memopw_io, 59, 1 },
    {Hexagon::L4_iadd_memopb_io, 60, 1 },
    {Hexagon::L4_iadd_memoph_io, 61, 1 },
    {Hexagon::L4_iadd_memopw_io, 62, 1 },
    {Hexagon::L4_iand_memopb_io, 63, 1 },
    {Hexagon::L4_iand_memoph_io, 64, 1 },
    {Hexagon::L4_iand_memopw_io, 65, 1 },
    {Hexagon::L4_ior_memopb_io, 66, 1 },
    {Hexagon::L4_ior_memoph_io, 67, 1 },
    {Hexagon::L4_ior_memopw_io, 68, 1 },
    {Hexagon::L4_isub_memopb_io, 69, 1 },
    {Hexagon::L4_isub_memoph_io, 70, 1 },
    {Hexagon::L4_isub_memopw_io, 71, 1 },
    {Hexagon::L4_or_memopb_io, 72, 1 },
    {Hexagon::L4_or_memoph_io, 73, 1 },
    {Hexagon::L4_or_memopw_io, 74, 1 },
    {Hexagon::L4_return, 75, 1 },
    {Hexagon::L4_return_f, 76, 1 },
    {Hexagon::L4_return_fnew_pnt, 77, 1 },
    {Hexagon::L4_return_fnew_pt, 78, 1 },
    {Hexagon::L4_return_t, 79, 1 },
    {Hexagon::L4_return_tnew_pnt, 80, 1 },
    {Hexagon::L4_return_tnew_pt, 81, 1 },
    {Hexagon::L4_sub_memopb_io, 82, 1 },
    {Hexagon::L4_sub_memoph_io, 83, 1 },
    {Hexagon::L4_sub_memopw_io, 84, 1 },
    {Hexagon::M2_mpyi, 85, 1 },
    {Hexagon::M7_dcmpyrwc, 86, 1 },
    {Hexagon::M7_dcmpyrwc_acc, 87, 1 },
    {Hexagon::S2_allocframe, 88, 1 },
    {Hexagon::S2_pstorerbf_io, 89, 1 },
    {Hexagon::S2_pstorerbnewf_io, 90, 1 },
    {Hexagon::S2_pstorerbnewt_io, 91, 1 },
    {Hexagon::S2_pstorerbt_io, 92, 1 },
    {Hexagon::S2_pstorerdf_io, 93, 1 },
    {Hexagon::S2_pstorerdt_io, 94, 1 },
    {Hexagon::S2_pstorerff_io, 95, 1 },
    {Hexagon::S2_pstorerft_io, 96, 1 },
    {Hexagon::S2_pstorerhf_io, 97, 1 },
    {Hexagon::S2_pstorerhnewf_io, 98, 1 },
    {Hexagon::S2_pstorerhnewt_io, 99, 1 },
    {Hexagon::S2_pstorerht_io, 100, 1 },
    {Hexagon::S2_pstorerif_io, 101, 1 },
    {Hexagon::S2_pstorerinewf_io, 102, 1 },
    {Hexagon::S2_pstorerinewt_io, 103, 1 },
    {Hexagon::S2_pstorerit_io, 104, 1 },
    {Hexagon::S2_storerb_io, 105, 1 },
    {Hexagon::S2_storerbnew_io, 106, 1 },
    {Hexagon::S2_storerd_io, 107, 1 },
    {Hexagon::S2_storerf_io, 108, 1 },
    {Hexagon::S2_storerh_io, 109, 1 },
    {Hexagon::S2_storerhnew_io, 110, 1 },
    {Hexagon::S2_storeri_io, 111, 1 },
    {Hexagon::S2_storerinew_io, 112, 1 },
    {Hexagon::S2_tableidxb, 113, 1 },
    {Hexagon::S4_pstorerbfnew_io, 114, 1 },
    {Hexagon::S4_pstorerbnewfnew_io, 115, 1 },
    {Hexagon::S4_pstorerbnewtnew_io, 116, 1 },
    {Hexagon::S4_pstorerbtnew_io, 117, 1 },
    {Hexagon::S4_pstorerdfnew_io, 118, 1 },
    {Hexagon::S4_pstorerdtnew_io, 119, 1 },
    {Hexagon::S4_pstorerffnew_io, 120, 1 },
    {Hexagon::S4_pstorerftnew_io, 121, 1 },
    {Hexagon::S4_pstorerhfnew_io, 122, 1 },
    {Hexagon::S4_pstorerhnewfnew_io, 123, 1 },
    {Hexagon::S4_pstorerhnewtnew_io, 124, 1 },
    {Hexagon::S4_pstorerhtnew_io, 125, 1 },
    {Hexagon::S4_pstorerifnew_io, 126, 1 },
    {Hexagon::S4_pstorerinewfnew_io, 127, 1 },
    {Hexagon::S4_pstorerinewtnew_io, 128, 1 },
    {Hexagon::S4_pstoreritnew_io, 129, 1 },
    {Hexagon::S4_storeirb_io, 130, 1 },
    {Hexagon::S4_storeirbf_io, 131, 1 },
    {Hexagon::S4_storeirbfnew_io, 132, 1 },
    {Hexagon::S4_storeirbt_io, 133, 1 },
    {Hexagon::S4_storeirbtnew_io, 134, 1 },
    {Hexagon::S4_storeirh_io, 135, 1 },
    {Hexagon::S4_storeirhf_io, 136, 1 },
    {Hexagon::S4_storeirhfnew_io, 137, 1 },
    {Hexagon::S4_storeirht_io, 138, 1 },
    {Hexagon::S4_storeirhtnew_io, 139, 1 },
    {Hexagon::S4_storeiri_io, 140, 1 },
    {Hexagon::S4_storeirif_io, 141, 1 },
    {Hexagon::S4_storeirifnew_io, 142, 1 },
    {Hexagon::S4_storeirit_io, 143, 1 },
    {Hexagon::S4_storeiritnew_io, 144, 1 },
    {Hexagon::V6_extractw, 145, 1 },
    {Hexagon::V6_v6mpyhubs10, 146, 1 },
    {Hexagon::V6_v6mpyvubs10, 147, 1 },
    {Hexagon::V6_vL32Ub_ai, 148, 1 },
    {Hexagon::V6_vL32b_ai, 149, 1 },
    {Hexagon::V6_vL32b_cur_npred_pi, 150, 1 },
    {Hexagon::V6_vL32b_cur_pred_pi, 151, 1 },
    {Hexagon::V6_vL32b_npred_ai, 152, 1 },
    {Hexagon::V6_vL32b_npred_pi, 153, 1 },
    {Hexagon::V6_vL32b_nt_ai, 154, 1 },
    {Hexagon::V6_vL32b_nt_cur_npred_pi, 155, 1 },
    {Hexagon::V6_vL32b_nt_cur_pred_pi, 156, 1 },
    {Hexagon::V6_vL32b_nt_npred_ai, 157, 1 },
    {Hexagon::V6_vL32b_nt_npred_pi, 158, 1 },
    {Hexagon::V6_vL32b_nt_pred_ai, 159, 1 },
    {Hexagon::V6_vL32b_nt_tmp_pred_ai, 160, 1 },
    {Hexagon::V6_vL32b_pred_ai, 161, 1 },
    {Hexagon::V6_vL32b_tmp_pred_ai, 162, 1 },
    {Hexagon::V6_vS32Ub_ai, 163, 1 },
    {Hexagon::V6_vS32Ub_npred_ai, 164, 1 },
    {Hexagon::V6_vS32Ub_pred_ai, 165, 1 },
    {Hexagon::V6_vS32b_ai, 166, 1 },
    {Hexagon::V6_vS32b_new_ai, 167, 1 },
    {Hexagon::V6_vS32b_npred_ai, 168, 1 },
    {Hexagon::V6_vS32b_nqpred_ai, 169, 1 },
    {Hexagon::V6_vS32b_nt_ai, 170, 1 },
    {Hexagon::V6_vS32b_nt_new_ai, 171, 1 },
    {Hexagon::V6_vS32b_nt_npred_ai, 172, 1 },
    {Hexagon::V6_vS32b_nt_nqpred_ai, 173, 1 },
    {Hexagon::V6_vS32b_nt_pred_ai, 174, 1 },
    {Hexagon::V6_vS32b_nt_qpred_ai, 175, 1 },
    {Hexagon::V6_vS32b_pred_ai, 176, 1 },
    {Hexagon::V6_vS32b_qpred_ai, 177, 1 },
    {Hexagon::V6_vabsb_sat, 178, 1 },
    {Hexagon::V6_vabsdiffh, 179, 1 },
    {Hexagon::V6_vabsdiffub, 180, 1 },
    {Hexagon::V6_vabsdiffuh, 181, 1 },
    {Hexagon::V6_vabsdiffw, 182, 1 },
    {Hexagon::V6_vabsh_sat, 183, 1 },
    {Hexagon::V6_vabsw_sat, 184, 1 },
    {Hexagon::V6_vaddb, 185, 1 },
    {Hexagon::V6_vaddb_dv, 186, 1 },
    {Hexagon::V6_vaddbnq, 187, 1 },
    {Hexagon::V6_vaddbq, 188, 1 },
    {Hexagon::V6_vaddbsat, 189, 1 },
    {Hexagon::V6_vaddbsat_dv, 190, 1 },
    {Hexagon::V6_vaddh, 191, 1 },
    {Hexagon::V6_vaddh_dv, 192, 1 },
    {Hexagon::V6_vaddhnq, 193, 1 },
    {Hexagon::V6_vaddhq, 194, 1 },
    {Hexagon::V6_vaddhsat, 195, 1 },
    {Hexagon::V6_vaddhsat_dv, 196, 1 },
    {Hexagon::V6_vaddhw, 197, 1 },
    {Hexagon::V6_vaddhw_acc, 198, 1 },
    {Hexagon::V6_vaddubh, 199, 1 },
    {Hexagon::V6_vaddubh_acc, 200, 1 },
    {Hexagon::V6_vaddubsat, 201, 1 },
    {Hexagon::V6_vaddubsat_dv, 202, 1 },
    {Hexagon::V6_vadduhsat, 203, 1 },
    {Hexagon::V6_vadduhsat_dv, 204, 1 },
    {Hexagon::V6_vadduhw, 205, 1 },
    {Hexagon::V6_vadduhw_acc, 206, 1 },
    {Hexagon::V6_vadduwsat, 207, 1 },
    {Hexagon::V6_vadduwsat_dv, 208, 1 },
    {Hexagon::V6_vaddw, 209, 1 },
    {Hexagon::V6_vaddw_dv, 210, 1 },
    {Hexagon::V6_vaddwnq, 211, 1 },
    {Hexagon::V6_vaddwq, 212, 1 },
    {Hexagon::V6_vaddwsat, 213, 1 },
    {Hexagon::V6_vaddwsat_dv, 214, 1 },
    {Hexagon::V6_vandnqrt, 215, 1 },
    {Hexagon::V6_vandnqrt_acc, 216, 1 },
    {Hexagon::V6_vandqrt, 217, 1 },
    {Hexagon::V6_vandqrt_acc, 218, 1 },
    {Hexagon::V6_vandvrt, 219, 1 },
    {Hexagon::V6_vandvrt_acc, 220, 1 },
    {Hexagon::V6_vaslh, 221, 1 },
    {Hexagon::V6_vaslh_acc, 222, 1 },
    {Hexagon::V6_vaslhv, 223, 1 },
    {Hexagon::V6_vaslw, 224, 1 },
    {Hexagon::V6_vaslw_acc, 225, 1 },
    {Hexagon::V6_vaslwv, 226, 1 },
    {Hexagon::V6_vasr_into, 227, 1 },
    {Hexagon::V6_vasrh, 228, 1 },
    {Hexagon::V6_vasrh_acc, 229, 1 },
    {Hexagon::V6_vasrhv, 230, 1 },
    {Hexagon::V6_vasrw, 231, 1 },
    {Hexagon::V6_vasrw_acc, 232, 1 },
    {Hexagon::V6_vasrwv, 233, 1 },
    {Hexagon::V6_vavgb, 234, 1 },
    {Hexagon::V6_vavgbrnd, 235, 1 },
    {Hexagon::V6_vavgh, 236, 1 },
    {Hexagon::V6_vavghrnd, 237, 1 },
    {Hexagon::V6_vavgub, 238, 1 },
    {Hexagon::V6_vavgubrnd, 239, 1 },
    {Hexagon::V6_vavguh, 240, 1 },
    {Hexagon::V6_vavguhrnd, 241, 1 },
    {Hexagon::V6_vavguw, 242, 1 },
    {Hexagon::V6_vavguwrnd, 243, 1 },
    {Hexagon::V6_vavgw, 244, 1 },
    {Hexagon::V6_vavgwrnd, 245, 1 },
    {Hexagon::V6_vcl0h, 246, 1 },
    {Hexagon::V6_vcl0w, 247, 1 },
    {Hexagon::V6_vdealb, 248, 1 },
    {Hexagon::V6_vdealb4w, 249, 1 },
    {Hexagon::V6_vdealh, 250, 1 },
    {Hexagon::V6_vdmpybus, 251, 1 },
    {Hexagon::V6_vdmpybus_acc, 252, 1 },
    {Hexagon::V6_vdmpybus_dv, 253, 1 },
    {Hexagon::V6_vdmpybus_dv_acc, 254, 1 },
    {Hexagon::V6_vdmpyhb, 255, 1 },
    {Hexagon::V6_vdmpyhb_acc, 256, 1 },
    {Hexagon::V6_vdmpyhb_dv, 257, 1 },
    {Hexagon::V6_vdmpyhb_dv_acc, 258, 1 },
    {Hexagon::V6_vdmpyhisat, 259, 1 },
    {Hexagon::V6_vdmpyhisat_acc, 260, 1 },
    {Hexagon::V6_vdmpyhsat, 261, 1 },
    {Hexagon::V6_vdmpyhsat_acc, 262, 1 },
    {Hexagon::V6_vdmpyhsuisat, 263, 1 },
    {Hexagon::V6_vdmpyhsuisat_acc, 264, 1 },
    {Hexagon::V6_vdmpyhsusat, 265, 1 },
    {Hexagon::V6_vdmpyhsusat_acc, 266, 1 },
    {Hexagon::V6_vdmpyhvsat, 267, 1 },
    {Hexagon::V6_vdmpyhvsat_acc, 268, 1 },
    {Hexagon::V6_vdsaduh, 269, 1 },
    {Hexagon::V6_vdsaduh_acc, 270, 1 },
    {Hexagon::V6_veqb, 271, 1 },
    {Hexagon::V6_veqb_and, 272, 1 },
    {Hexagon::V6_veqb_or, 273, 1 },
    {Hexagon::V6_veqb_xor, 274, 1 },
    {Hexagon::V6_veqh, 275, 1 },
    {Hexagon::V6_veqh_and, 276, 1 },
    {Hexagon::V6_veqh_or, 277, 1 },
    {Hexagon::V6_veqh_xor, 278, 1 },
    {Hexagon::V6_veqw, 279, 1 },
    {Hexagon::V6_veqw_and, 280, 1 },
    {Hexagon::V6_veqw_or, 281, 1 },
    {Hexagon::V6_veqw_xor, 282, 1 },
    {Hexagon::V6_vlsrh, 283, 1 },
    {Hexagon::V6_vlsrhv, 284, 1 },
    {Hexagon::V6_vlsrw, 285, 1 },
    {Hexagon::V6_vlsrwv, 286, 1 },
    {Hexagon::V6_vmaxb, 287, 1 },
    {Hexagon::V6_vmaxh, 288, 1 },
    {Hexagon::V6_vmaxub, 289, 1 },
    {Hexagon::V6_vmaxuh, 290, 1 },
    {Hexagon::V6_vmaxw, 291, 1 },
    {Hexagon::V6_vminb, 292, 1 },
    {Hexagon::V6_vminh, 293, 1 },
    {Hexagon::V6_vminub, 294, 1 },
    {Hexagon::V6_vminuh, 295, 1 },
    {Hexagon::V6_vminw, 296, 1 },
    {Hexagon::V6_vmpabus, 297, 1 },
    {Hexagon::V6_vmpabus_acc, 298, 1 },
    {Hexagon::V6_vmpabusv, 299, 1 },
    {Hexagon::V6_vmpabuu, 300, 1 },
    {Hexagon::V6_vmpabuu_acc, 301, 1 },
    {Hexagon::V6_vmpabuuv, 302, 1 },
    {Hexagon::V6_vmpahb, 303, 1 },
    {Hexagon::V6_vmpahb_acc, 304, 1 },
    {Hexagon::V6_vmpauhb, 305, 1 },
    {Hexagon::V6_vmpauhb_acc, 306, 1 },
    {Hexagon::V6_vmpybus, 307, 1 },
    {Hexagon::V6_vmpybus_acc, 308, 1 },
    {Hexagon::V6_vmpybusv, 309, 1 },
    {Hexagon::V6_vmpybusv_acc, 310, 1 },
    {Hexagon::V6_vmpybv, 311, 1 },
    {Hexagon::V6_vmpybv_acc, 312, 1 },
    {Hexagon::V6_vmpyewuh, 313, 1 },
    {Hexagon::V6_vmpyh, 314, 1 },
    {Hexagon::V6_vmpyh_acc, 315, 1 },
    {Hexagon::V6_vmpyhsat_acc, 316, 1 },
    {Hexagon::V6_vmpyhsrs, 317, 1 },
    {Hexagon::V6_vmpyhss, 318, 1 },
    {Hexagon::V6_vmpyhus, 319, 1 },
    {Hexagon::V6_vmpyhus_acc, 320, 1 },
    {Hexagon::V6_vmpyhv, 321, 1 },
    {Hexagon::V6_vmpyhv_acc, 322, 1 },
    {Hexagon::V6_vmpyhvsrs, 323, 1 },
    {Hexagon::V6_vmpyiewh_acc, 324, 1 },
    {Hexagon::V6_vmpyiewuh, 325, 1 },
    {Hexagon::V6_vmpyiewuh_acc, 326, 1 },
    {Hexagon::V6_vmpyih, 327, 1 },
    {Hexagon::V6_vmpyih_acc, 328, 1 },
    {Hexagon::V6_vmpyihb, 329, 1 },
    {Hexagon::V6_vmpyihb_acc, 330, 1 },
    {Hexagon::V6_vmpyiowh, 331, 1 },
    {Hexagon::V6_vmpyiwb, 332, 1 },
    {Hexagon::V6_vmpyiwb_acc, 333, 1 },
    {Hexagon::V6_vmpyiwh, 334, 1 },
    {Hexagon::V6_vmpyiwh_acc, 335, 1 },
    {Hexagon::V6_vmpyiwub, 336, 1 },
    {Hexagon::V6_vmpyiwub_acc, 337, 1 },
    {Hexagon::V6_vmpyowh, 338, 1 },
    {Hexagon::V6_vmpyowh_rnd, 339, 1 },
    {Hexagon::V6_vmpyub, 340, 1 },
    {Hexagon::V6_vmpyub_acc, 341, 1 },
    {Hexagon::V6_vmpyubv, 342, 1 },
    {Hexagon::V6_vmpyubv_acc, 343, 1 },
    {Hexagon::V6_vmpyuh, 344, 1 },
    {Hexagon::V6_vmpyuh_acc, 345, 1 },
    {Hexagon::V6_vmpyuhv, 346, 1 },
    {Hexagon::V6_vmpyuhv_acc, 347, 1 },
    {Hexagon::V6_vnavgb, 348, 1 },
    {Hexagon::V6_vnavgh, 349, 1 },
    {Hexagon::V6_vnavgub, 350, 1 },
    {Hexagon::V6_vnavgw, 351, 1 },
    {Hexagon::V6_vnormamth, 352, 1 },
    {Hexagon::V6_vnormamtw, 353, 1 },
    {Hexagon::V6_vpackeb, 354, 1 },
    {Hexagon::V6_vpackeh, 355, 1 },
    {Hexagon::V6_vpackhb_sat, 356, 1 },
    {Hexagon::V6_vpackhub_sat, 357, 1 },
    {Hexagon::V6_vpackob, 358, 1 },
    {Hexagon::V6_vpackoh, 359, 1 },
    {Hexagon::V6_vpackwh_sat, 360, 1 },
    {Hexagon::V6_vpackwuh_sat, 361, 1 },
    {Hexagon::V6_vpopcounth, 362, 1 },
    {Hexagon::V6_vrmpybub_rtt, 363, 1 },
    {Hexagon::V6_vrmpybub_rtt_acc, 364, 1 },
    {Hexagon::V6_vrmpybus, 365, 1 },
    {Hexagon::V6_vrmpybus_acc, 366, 1 },
    {Hexagon::V6_vrmpybusi, 367, 1 },
    {Hexagon::V6_vrmpybusi_acc, 368, 1 },
    {Hexagon::V6_vrmpybusv, 369, 1 },
    {Hexagon::V6_vrmpybusv_acc, 370, 1 },
    {Hexagon::V6_vrmpybv, 371, 1 },
    {Hexagon::V6_vrmpybv_acc, 372, 1 },
    {Hexagon::V6_vrmpyub, 373, 1 },
    {Hexagon::V6_vrmpyub_acc, 374, 1 },
    {Hexagon::V6_vrmpyub_rtt, 375, 1 },
    {Hexagon::V6_vrmpyub_rtt_acc, 376, 1 },
    {Hexagon::V6_vrmpyubi, 377, 1 },
    {Hexagon::V6_vrmpyubi_acc, 378, 1 },
    {Hexagon::V6_vrmpyubv, 379, 1 },
    {Hexagon::V6_vrmpyubv_acc, 380, 1 },
    {Hexagon::V6_vrotr, 381, 1 },
    {Hexagon::V6_vroundhb, 382, 1 },
    {Hexagon::V6_vroundhub, 383, 1 },
    {Hexagon::V6_vrounduhub, 384, 1 },
    {Hexagon::V6_vrounduwuh, 385, 1 },
    {Hexagon::V6_vroundwh, 386, 1 },
    {Hexagon::V6_vroundwuh, 387, 1 },
    {Hexagon::V6_vrsadubi, 388, 1 },
    {Hexagon::V6_vrsadubi_acc, 389, 1 },
    {Hexagon::V6_vsathub, 390, 1 },
    {Hexagon::V6_vsatuwuh, 391, 1 },
    {Hexagon::V6_vsatwh, 392, 1 },
    {Hexagon::V6_vsb, 393, 1 },
    {Hexagon::V6_vscattermh, 394, 1 },
    {Hexagon::V6_vscattermh_add, 395, 1 },
    {Hexagon::V6_vscattermhq, 396, 1 },
    {Hexagon::V6_vscattermhw, 397, 1 },
    {Hexagon::V6_vscattermhw_add, 398, 1 },
    {Hexagon::V6_vscattermhwq, 399, 1 },
    {Hexagon::V6_vscattermw, 400, 1 },
    {Hexagon::V6_vscattermw_add, 401, 1 },
    {Hexagon::V6_vscattermwq, 402, 1 },
    {Hexagon::V6_vsh, 403, 1 },
    {Hexagon::V6_vshufeh, 404, 1 },
    {Hexagon::V6_vshuff, 405, 1 },
    {Hexagon::V6_vshuffb, 406, 1 },
    {Hexagon::V6_vshuffeb, 407, 1 },
    {Hexagon::V6_vshuffh, 408, 1 },
    {Hexagon::V6_vshuffob, 409, 1 },
    {Hexagon::V6_vshufoeb, 410, 1 },
    {Hexagon::V6_vshufoeh, 411, 1 },
    {Hexagon::V6_vshufoh, 412, 1 },
    {Hexagon::V6_vsubb, 413, 1 },
    {Hexagon::V6_vsubb_dv, 414, 1 },
    {Hexagon::V6_vsubbnq, 415, 1 },
    {Hexagon::V6_vsubbq, 416, 1 },
    {Hexagon::V6_vsubbsat, 417, 1 },
    {Hexagon::V6_vsubbsat_dv, 418, 1 },
    {Hexagon::V6_vsubh, 419, 1 },
    {Hexagon::V6_vsubh_dv, 420, 1 },
    {Hexagon::V6_vsubhnq, 421, 1 },
    {Hexagon::V6_vsubhq, 422, 1 },
    {Hexagon::V6_vsubhsat, 423, 1 },
    {Hexagon::V6_vsubhsat_dv, 424, 1 },
    {Hexagon::V6_vsubhw, 425, 1 },
    {Hexagon::V6_vsububh, 426, 1 },
    {Hexagon::V6_vsububsat, 427, 1 },
    {Hexagon::V6_vsububsat_dv, 428, 1 },
    {Hexagon::V6_vsubuhsat, 429, 1 },
    {Hexagon::V6_vsubuhsat_dv, 430, 1 },
    {Hexagon::V6_vsubuhw, 431, 1 },
    {Hexagon::V6_vsubuwsat, 432, 1 },
    {Hexagon::V6_vsubuwsat_dv, 433, 1 },
    {Hexagon::V6_vsubw, 434, 1 },
    {Hexagon::V6_vsubw_dv, 435, 2 },
    {Hexagon::V6_vsubwnq, 437, 1 },
    {Hexagon::V6_vsubwq, 438, 1 },
    {Hexagon::V6_vsubwsat, 439, 1 },
    {Hexagon::V6_vsubwsat_dv, 440, 1 },
    {Hexagon::V6_vtmpyb, 441, 1 },
    {Hexagon::V6_vtmpyb_acc, 442, 1 },
    {Hexagon::V6_vtmpybus, 443, 1 },
    {Hexagon::V6_vtmpybus_acc, 444, 1 },
    {Hexagon::V6_vtmpyhb, 445, 1 },
    {Hexagon::V6_vtmpyhb_acc, 446, 1 },
    {Hexagon::V6_vunpackb, 447, 1 },
    {Hexagon::V6_vunpackh, 448, 1 },
    {Hexagon::V6_vunpackoh, 449, 1 },
    {Hexagon::V6_vunpackub, 450, 1 },
    {Hexagon::V6_vunpackuh, 451, 1 },
    {Hexagon::V6_vxor, 452, 1 },
    {Hexagon::V6_vzb, 453, 1 },
    {Hexagon::V6_vzh, 454, 1 },
    {Hexagon::V6_zLd_ai, 455, 1 },
    {Hexagon::V6_zLd_pred_ai, 456, 1 },
    {Hexagon::Y2_crswap0, 457, 1 },
    {Hexagon::Y2_dcfetchbo, 458, 1 },
  };

  static const AliasPattern Patterns[] = {
    // Hexagon::A2_andir - 0
    {0, 0, 3, 3 },
    // Hexagon::A2_paddif - 1
    {14, 3, 4, 4 },
    // Hexagon::A2_paddifnew - 2
    {31, 7, 4, 4 },
    // Hexagon::A2_paddit - 3
    {52, 11, 4, 4 },
    // Hexagon::A2_padditnew - 4
    {68, 15, 4, 4 },
    // Hexagon::A2_subri - 5
    {88, 19, 3, 3 },
    {101, 22, 3, 3 },
    // Hexagon::A2_vaddub - 7
    {114, 25, 3, 3 },
    // Hexagon::A2_vsubub - 8
    {132, 28, 3, 3 },
    // Hexagon::C2_cmpgt - 9
    {150, 31, 3, 3 },
    // Hexagon::C2_cmpgtu - 10
    {169, 34, 3, 3 },
    // Hexagon::C2_or - 11
    {189, 37, 3, 3 },
    // Hexagon::J2_jumpf - 12
    {197, 40, 2, 1 },
    // Hexagon::J2_jumprf - 13
    {216, 41, 2, 2 },
    // Hexagon::J2_jumprt - 14
    {234, 43, 2, 2 },
    // Hexagon::J2_jumpt - 15
    {251, 45, 2, 1 },
    // Hexagon::J2_trap1 - 16
    {269, 46, 3, 2 },
    // Hexagon::L2_deallocframe - 17
    {280, 48, 2, 2 },
    // Hexagon::L2_loadalignb_io - 18
    {293, 50, 4, 4 },
    // Hexagon::L2_loadalignh_io - 19
    {312, 54, 4, 4 },
    // Hexagon::L2_loadbsw2_io - 20
    {331, 58, 3, 3 },
    // Hexagon::L2_loadbsw4_io - 21
    {331, 61, 3, 3 },
    // Hexagon::L2_loadbzw2_io - 22
    {346, 64, 3, 3 },
    // Hexagon::L2_loadbzw4_io - 23
    {346, 67, 3, 3 },
    // Hexagon::L2_loadrb_io - 24
    {362, 70, 3, 3 },
    // Hexagon::L2_loadrd_io - 25
    {376, 73, 3, 3 },
    // Hexagon::L2_loadrh_io - 26
    {390, 76, 3, 3 },
    // Hexagon::L2_loadri_io - 27
    {404, 79, 3, 3 },
    // Hexagon::L2_loadrub_io - 28
    {418, 82, 3, 3 },
    // Hexagon::L2_loadruh_io - 29
    {433, 85, 3, 3 },
    // Hexagon::L2_ploadrbf_io - 30
    {448, 88, 4, 4 },
    // Hexagon::L2_ploadrbfnew_io - 31
    {471, 92, 4, 4 },
    // Hexagon::L2_ploadrbt_io - 32
    {498, 96, 4, 4 },
    // Hexagon::L2_ploadrbtnew_io - 33
    {520, 100, 4, 4 },
    // Hexagon::L2_ploadrdf_io - 34
    {546, 104, 4, 4 },
    // Hexagon::L2_ploadrdfnew_io - 35
    {569, 108, 4, 4 },
    // Hexagon::L2_ploadrdt_io - 36
    {596, 112, 4, 4 },
    // Hexagon::L2_ploadrdtnew_io - 37
    {618, 116, 4, 4 },
    // Hexagon::L2_ploadrhf_io - 38
    {644, 120, 4, 4 },
    // Hexagon::L2_ploadrhfnew_io - 39
    {667, 124, 4, 4 },
    // Hexagon::L2_ploadrht_io - 40
    {694, 128, 4, 4 },
    // Hexagon::L2_ploadrhtnew_io - 41
    {716, 132, 4, 4 },
    // Hexagon::L2_ploadrif_io - 42
    {742, 136, 4, 4 },
    // Hexagon::L2_ploadrifnew_io - 43
    {765, 140, 4, 4 },
    // Hexagon::L2_ploadrit_io - 44
    {792, 144, 4, 4 },
    // Hexagon::L2_ploadritnew_io - 45
    {814, 148, 4, 4 },
    // Hexagon::L2_ploadrubf_io - 46
    {840, 152, 4, 4 },
    // Hexagon::L2_ploadrubfnew_io - 47
    {864, 156, 4, 4 },
    // Hexagon::L2_ploadrubt_io - 48
    {892, 160, 4, 4 },
    // Hexagon::L2_ploadrubtnew_io - 49
    {915, 164, 4, 4 },
    // Hexagon::L2_ploadruhf_io - 50
    {942, 168, 4, 4 },
    // Hexagon::L2_ploadruhfnew_io - 51
    {966, 172, 4, 4 },
    // Hexagon::L2_ploadruht_io - 52
    {994, 176, 4, 4 },
    // Hexagon::L2_ploadruhtnew_io - 53
    {1017, 180, 4, 4 },
    // Hexagon::L4_add_memopb_io - 54
    {1044, 184, 3, 3 },
    // Hexagon::L4_add_memoph_io - 55
    {1059, 187, 3, 3 },
    // Hexagon::L4_add_memopw_io - 56
    {1074, 190, 3, 3 },
    // Hexagon::L4_and_memopb_io - 57
    {1089, 193, 3, 3 },
    // Hexagon::L4_and_memoph_io - 58
    {1104, 196, 3, 3 },
    // Hexagon::L4_and_memopw_io - 59
    {1119, 199, 3, 3 },
    // Hexagon::L4_iadd_memopb_io - 60
    {1134, 202, 3, 2 },
    // Hexagon::L4_iadd_memoph_io - 61
    {1150, 204, 3, 2 },
    // Hexagon::L4_iadd_memopw_io - 62
    {1166, 206, 3, 2 },
    // Hexagon::L4_iand_memopb_io - 63
    {1182, 208, 3, 2 },
    // Hexagon::L4_iand_memoph_io - 64
    {1205, 210, 3, 2 },
    // Hexagon::L4_iand_memopw_io - 65
    {1228, 212, 3, 2 },
    // Hexagon::L4_ior_memopb_io - 66
    {1251, 214, 3, 2 },
    // Hexagon::L4_ior_memoph_io - 67
    {1274, 216, 3, 2 },
    // Hexagon::L4_ior_memopw_io - 68
    {1297, 218, 3, 2 },
    // Hexagon::L4_isub_memopb_io - 69
    {1320, 220, 3, 2 },
    // Hexagon::L4_isub_memoph_io - 70
    {1336, 222, 3, 2 },
    // Hexagon::L4_isub_memopw_io - 71
    {1352, 224, 3, 2 },
    // Hexagon::L4_or_memopb_io - 72
    {1368, 226, 3, 3 },
    // Hexagon::L4_or_memoph_io - 73
    {1383, 229, 3, 3 },
    // Hexagon::L4_or_memopw_io - 74
    {1398, 232, 3, 3 },
    // Hexagon::L4_return - 75
    {1413, 235, 2, 2 },
    // Hexagon::L4_return_f - 76
    {1428, 237, 3, 3 },
    // Hexagon::L4_return_fnew_pnt - 77
    {1452, 240, 3, 3 },
    // Hexagon::L4_return_fnew_pt - 78
    {1483, 243, 3, 3 },
    // Hexagon::L4_return_t - 79
    {1513, 246, 3, 3 },
    // Hexagon::L4_return_tnew_pnt - 80
    {1536, 249, 3, 3 },
    // Hexagon::L4_return_tnew_pt - 81
    {1566, 252, 3, 3 },
    // Hexagon::L4_sub_memopb_io - 82
    {1595, 255, 3, 3 },
    // Hexagon::L4_sub_memoph_io - 83
    {1610, 258, 3, 3 },
    // Hexagon::L4_sub_memopw_io - 84
    {1625, 261, 3, 3 },
    // Hexagon::M2_mpyi - 85
    {1640, 264, 3, 3 },
    // Hexagon::M7_dcmpyrwc - 86
    {1658, 267, 3, 3 },
    // Hexagon::M7_dcmpyrwc_acc - 87
    {1677, 270, 4, 4 },
    // Hexagon::S2_allocframe - 88
    {1697, 274, 3, 2 },
    // Hexagon::S2_pstorerbf_io - 89
    {1713, 276, 4, 4 },
    // Hexagon::S2_pstorerbnewf_io - 90
    {1736, 280, 4, 4 },
    // Hexagon::S2_pstorerbnewt_io - 91
    {1763, 284, 4, 4 },
    // Hexagon::S2_pstorerbt_io - 92
    {1789, 288, 4, 4 },
    // Hexagon::S2_pstorerdf_io - 93
    {1811, 292, 4, 4 },
    // Hexagon::S2_pstorerdt_io - 94
    {1834, 296, 4, 4 },
    // Hexagon::S2_pstorerff_io - 95
    {1856, 300, 4, 4 },
    // Hexagon::S2_pstorerft_io - 96
    {1881, 304, 4, 4 },
    // Hexagon::S2_pstorerhf_io - 97
    {1905, 308, 4, 4 },
    // Hexagon::S2_pstorerhnewf_io - 98
    {1928, 312, 4, 4 },
    // Hexagon::S2_pstorerhnewt_io - 99
    {1955, 316, 4, 4 },
    // Hexagon::S2_pstorerht_io - 100
    {1981, 320, 4, 4 },
    // Hexagon::S2_pstorerif_io - 101
    {2003, 324, 4, 4 },
    // Hexagon::S2_pstorerinewf_io - 102
    {2026, 328, 4, 4 },
    // Hexagon::S2_pstorerinewt_io - 103
    {2053, 332, 4, 4 },
    // Hexagon::S2_pstorerit_io - 104
    {2079, 336, 4, 4 },
    // Hexagon::S2_storerb_io - 105
    {2101, 340, 3, 3 },
    // Hexagon::S2_storerbnew_io - 106
    {2115, 343, 3, 3 },
    // Hexagon::S2_storerd_io - 107
    {2133, 346, 3, 3 },
    // Hexagon::S2_storerf_io - 108
    {2147, 349, 3, 3 },
    // Hexagon::S2_storerh_io - 109
    {2163, 352, 3, 3 },
    // Hexagon::S2_storerhnew_io - 110
    {2177, 355, 3, 3 },
    // Hexagon::S2_storeri_io - 111
    {2195, 358, 3, 3 },
    // Hexagon::S2_storerinew_io - 112
    {2209, 361, 3, 3 },
    // Hexagon::S2_tableidxb - 113
    {2227, 364, 5, 4 },
    // Hexagon::S4_pstorerbfnew_io - 114
    {2254, 368, 4, 4 },
    // Hexagon::S4_pstorerbnewfnew_io - 115
    {2281, 372, 4, 4 },
    // Hexagon::S4_pstorerbnewtnew_io - 116
    {2312, 376, 4, 4 },
    // Hexagon::S4_pstorerbtnew_io - 117
    {2342, 380, 4, 4 },
    // Hexagon::S4_pstorerdfnew_io - 118
    {2368, 384, 4, 4 },
    // Hexagon::S4_pstorerdtnew_io - 119
    {2395, 388, 4, 4 },
    // Hexagon::S4_pstorerffnew_io - 120
    {2421, 392, 4, 4 },
    // Hexagon::S4_pstorerftnew_io - 121
    {2450, 396, 4, 4 },
    // Hexagon::S4_pstorerhfnew_io - 122
    {2478, 400, 4, 4 },
    // Hexagon::S4_pstorerhnewfnew_io - 123
    {2505, 404, 4, 4 },
    // Hexagon::S4_pstorerhnewtnew_io - 124
    {2536, 408, 4, 4 },
    // Hexagon::S4_pstorerhtnew_io - 125
    {2566, 412, 4, 4 },
    // Hexagon::S4_pstorerifnew_io - 126
    {2592, 416, 4, 4 },
    // Hexagon::S4_pstorerinewfnew_io - 127
    {2619, 420, 4, 4 },
    // Hexagon::S4_pstorerinewtnew_io - 128
    {2650, 424, 4, 4 },
    // Hexagon::S4_pstoreritnew_io - 129
    {2680, 428, 4, 4 },
    // Hexagon::S4_storeirb_io - 130
    {2706, 432, 3, 2 },
    // Hexagon::S4_storeirbf_io - 131
    {2721, 434, 4, 3 },
    // Hexagon::S4_storeirbfnew_io - 132
    {2745, 437, 4, 3 },
    // Hexagon::S4_storeirbt_io - 133
    {2773, 440, 4, 3 },
    // Hexagon::S4_storeirbtnew_io - 134
    {2796, 443, 4, 3 },
    // Hexagon::S4_storeirh_io - 135
    {2823, 446, 3, 2 },
    // Hexagon::S4_storeirhf_io - 136
    {2838, 448, 4, 3 },
    // Hexagon::S4_storeirhfnew_io - 137
    {2862, 451, 4, 3 },
    // Hexagon::S4_storeirht_io - 138
    {2890, 454, 4, 3 },
    // Hexagon::S4_storeirhtnew_io - 139
    {2913, 457, 4, 3 },
    // Hexagon::S4_storeiri_io - 140
    {2940, 460, 3, 2 },
    // Hexagon::S4_storeirif_io - 141
    {2955, 462, 4, 3 },
    // Hexagon::S4_storeirifnew_io - 142
    {2979, 465, 4, 3 },
    // Hexagon::S4_storeirit_io - 143
    {3007, 468, 4, 3 },
    // Hexagon::S4_storeiritnew_io - 144
    {3030, 471, 4, 3 },
    // Hexagon::V6_extractw - 145
    {3057, 474, 3, 3 },
    // Hexagon::V6_v6mpyhubs10 - 146
    {3080, 477, 4, 3 },
    // Hexagon::V6_v6mpyvubs10 - 147
    {3113, 480, 4, 3 },
    // Hexagon::V6_vL32Ub_ai - 148
    {3146, 483, 3, 3 },
    // Hexagon::V6_vL32b_ai - 149
    {3161, 486, 3, 3 },
    // Hexagon::V6_vL32b_cur_npred_pi - 150
    {3175, 489, 5, 5 },
    // Hexagon::V6_vL32b_cur_pred_pi - 151
    {3202, 494, 5, 5 },
    // Hexagon::V6_vL32b_npred_ai - 152
    {3228, 499, 4, 4 },
    // Hexagon::V6_vL32b_npred_pi - 153
    {3255, 503, 5, 5 },
    // Hexagon::V6_vL32b_nt_ai - 154
    {3278, 508, 3, 3 },
    // Hexagon::V6_vL32b_nt_cur_npred_pi - 155
    {3295, 511, 5, 5 },
    // Hexagon::V6_vL32b_nt_cur_pred_pi - 156
    {3325, 516, 5, 5 },
    // Hexagon::V6_vL32b_nt_npred_ai - 157
    {3354, 521, 4, 4 },
    // Hexagon::V6_vL32b_nt_npred_pi - 158
    {3384, 525, 5, 5 },
    // Hexagon::V6_vL32b_nt_pred_ai - 159
    {3410, 530, 4, 4 },
    // Hexagon::V6_vL32b_nt_tmp_pred_ai - 160
    {3435, 534, 4, 4 },
    // Hexagon::V6_vL32b_pred_ai - 161
    {3464, 538, 4, 4 },
    // Hexagon::V6_vL32b_tmp_pred_ai - 162
    {3486, 542, 4, 4 },
    // Hexagon::V6_vS32Ub_ai - 163
    {3512, 546, 3, 3 },
    // Hexagon::V6_vS32Ub_npred_ai - 164
    {3527, 549, 4, 4 },
    // Hexagon::V6_vS32Ub_pred_ai - 165
    {3551, 553, 4, 4 },
    // Hexagon::V6_vS32b_ai - 166
    {3574, 557, 3, 3 },
    // Hexagon::V6_vS32b_new_ai - 167
    {3588, 560, 3, 3 },
    // Hexagon::V6_vS32b_npred_ai - 168
    {3606, 563, 4, 4 },
    // Hexagon::V6_vS32b_nqpred_ai - 169
    {3606, 567, 4, 4 },
    // Hexagon::V6_vS32b_nt_ai - 170
    {3629, 571, 3, 3 },
    // Hexagon::V6_vS32b_nt_new_ai - 171
    {3646, 574, 3, 3 },
    // Hexagon::V6_vS32b_nt_npred_ai - 172
    {3667, 577, 4, 4 },
    // Hexagon::V6_vS32b_nt_nqpred_ai - 173
    {3667, 581, 4, 4 },
    // Hexagon::V6_vS32b_nt_pred_ai - 174
    {3693, 585, 4, 4 },
    // Hexagon::V6_vS32b_nt_qpred_ai - 175
    {3693, 589, 4, 4 },
    // Hexagon::V6_vS32b_pred_ai - 176
    {3718, 593, 4, 4 },
    // Hexagon::V6_vS32b_qpred_ai - 177
    {3718, 597, 4, 4 },
    // Hexagon::V6_vabsb_sat - 178
    {3740, 601, 2, 2 },
    // Hexagon::V6_vabsdiffh - 179
    {3759, 603, 3, 3 },
    // Hexagon::V6_vabsdiffub - 180
    {3781, 606, 3, 3 },
    // Hexagon::V6_vabsdiffuh - 181
    {3804, 609, 3, 3 },
    // Hexagon::V6_vabsdiffw - 182
    {3827, 612, 3, 3 },
    // Hexagon::V6_vabsh_sat - 183
    {3849, 615, 2, 2 },
    // Hexagon::V6_vabsw_sat - 184
    {3868, 617, 2, 2 },
    // Hexagon::V6_vaddb - 185
    {114, 619, 3, 3 },
    // Hexagon::V6_vaddb_dv - 186
    {114, 622, 3, 3 },
    // Hexagon::V6_vaddbnq - 187
    {3887, 625, 4, 4 },
    // Hexagon::V6_vaddbq - 188
    {3911, 629, 4, 4 },
    // Hexagon::V6_vaddbsat - 189
    {3934, 633, 3, 3 },
    // Hexagon::V6_vaddbsat_dv - 190
    {3934, 636, 3, 3 },
    // Hexagon::V6_vaddh - 191
    {3956, 639, 3, 3 },
    // Hexagon::V6_vaddh_dv - 192
    {3956, 642, 3, 3 },
    // Hexagon::V6_vaddhnq - 193
    {3974, 645, 4, 4 },
    // Hexagon::V6_vaddhq - 194
    {3998, 649, 4, 4 },
    // Hexagon::V6_vaddhsat - 195
    {4021, 653, 3, 3 },
    // Hexagon::V6_vaddhsat_dv - 196
    {4021, 656, 3, 3 },
    // Hexagon::V6_vaddhw - 197
    {3956, 659, 3, 3 },
    // Hexagon::V6_vaddhw_acc - 198
    {4043, 662, 4, 4 },
    // Hexagon::V6_vaddubh - 199
    {4062, 666, 3, 3 },
    // Hexagon::V6_vaddubh_acc - 200
    {4081, 669, 4, 4 },
    // Hexagon::V6_vaddubsat - 201
    {4101, 673, 3, 3 },
    // Hexagon::V6_vaddubsat_dv - 202
    {4101, 676, 3, 3 },
    // Hexagon::V6_vadduhsat - 203
    {4124, 679, 3, 3 },
    // Hexagon::V6_vadduhsat_dv - 204
    {4124, 682, 3, 3 },
    // Hexagon::V6_vadduhw - 205
    {4147, 685, 3, 3 },
    // Hexagon::V6_vadduhw_acc - 206
    {4166, 688, 4, 4 },
    // Hexagon::V6_vadduwsat - 207
    {4186, 692, 3, 3 },
    // Hexagon::V6_vadduwsat_dv - 208
    {4186, 695, 3, 3 },
    // Hexagon::V6_vaddw - 209
    {4209, 698, 3, 3 },
    // Hexagon::V6_vaddw_dv - 210
    {4209, 701, 3, 3 },
    // Hexagon::V6_vaddwnq - 211
    {4227, 704, 4, 4 },
    // Hexagon::V6_vaddwq - 212
    {4251, 708, 4, 4 },
    // Hexagon::V6_vaddwsat - 213
    {4274, 712, 3, 3 },
    // Hexagon::V6_vaddwsat_dv - 214
    {4274, 715, 3, 3 },
    // Hexagon::V6_vandnqrt - 215
    {4296, 718, 3, 3 },
    // Hexagon::V6_vandnqrt_acc - 216
    {4323, 721, 4, 4 },
    // Hexagon::V6_vandqrt - 217
    {4351, 725, 3, 3 },
    // Hexagon::V6_vandqrt_acc - 218
    {4377, 728, 4, 4 },
    // Hexagon::V6_vandvrt - 219
    {4351, 732, 3, 3 },
    // Hexagon::V6_vandvrt_acc - 220
    {4377, 735, 4, 4 },
    // Hexagon::V6_vaslh - 221
    {4404, 739, 3, 3 },
    // Hexagon::V6_vaslh_acc - 222
    {4422, 742, 4, 4 },
    // Hexagon::V6_vaslhv - 223
    {4404, 746, 3, 3 },
    // Hexagon::V6_vaslw - 224
    {4441, 749, 3, 3 },
    // Hexagon::V6_vaslw_acc - 225
    {4459, 752, 4, 4 },
    // Hexagon::V6_vaslwv - 226
    {4441, 756, 3, 3 },
    // Hexagon::V6_vasr_into - 227
    {4478, 759, 4, 4 },
    // Hexagon::V6_vasrh - 228
    {4499, 763, 3, 3 },
    // Hexagon::V6_vasrh_acc - 229
    {4517, 766, 4, 4 },
    // Hexagon::V6_vasrhv - 230
    {4499, 770, 3, 3 },
    // Hexagon::V6_vasrw - 231
    {4536, 773, 3, 3 },
    // Hexagon::V6_vasrw_acc - 232
    {4554, 776, 4, 4 },
    // Hexagon::V6_vasrwv - 233
    {4536, 780, 3, 3 },
    // Hexagon::V6_vavgb - 234
    {4573, 783, 3, 3 },
    // Hexagon::V6_vavgbrnd - 235
    {4591, 786, 3, 3 },
    // Hexagon::V6_vavgh - 236
    {4613, 789, 3, 3 },
    // Hexagon::V6_vavghrnd - 237
    {4631, 792, 3, 3 },
    // Hexagon::V6_vavgub - 238
    {4653, 795, 3, 3 },
    // Hexagon::V6_vavgubrnd - 239
    {4672, 798, 3, 3 },
    // Hexagon::V6_vavguh - 240
    {4695, 801, 3, 3 },
    // Hexagon::V6_vavguhrnd - 241
    {4714, 804, 3, 3 },
    // Hexagon::V6_vavguw - 242
    {4737, 807, 3, 3 },
    // Hexagon::V6_vavguwrnd - 243
    {4756, 810, 3, 3 },
    // Hexagon::V6_vavgw - 244
    {4779, 813, 3, 3 },
    // Hexagon::V6_vavgwrnd - 245
    {4797, 816, 3, 3 },
    // Hexagon::V6_vcl0h - 246
    {4819, 819, 2, 2 },
    // Hexagon::V6_vcl0w - 247
    {4834, 821, 2, 2 },
    // Hexagon::V6_vdealb - 248
    {4849, 823, 2, 2 },
    // Hexagon::V6_vdealb4w - 249
    {4865, 825, 3, 3 },
    // Hexagon::V6_vdealh - 250
    {4886, 828, 2, 2 },
    // Hexagon::V6_vdmpybus - 251
    {4902, 830, 3, 3 },
    // Hexagon::V6_vdmpybus_acc - 252
    {4923, 833, 4, 4 },
    // Hexagon::V6_vdmpybus_dv - 253
    {4902, 837, 3, 3 },
    // Hexagon::V6_vdmpybus_dv_acc - 254
    {4923, 840, 4, 4 },
    // Hexagon::V6_vdmpyhb - 255
    {4945, 844, 3, 3 },
    // Hexagon::V6_vdmpyhb_acc - 256
    {4965, 847, 4, 4 },
    // Hexagon::V6_vdmpyhb_dv - 257
    {4945, 851, 3, 3 },
    // Hexagon::V6_vdmpyhb_dv_acc - 258
    {4965, 854, 4, 4 },
    // Hexagon::V6_vdmpyhisat - 259
    {4986, 858, 3, 3 },
    // Hexagon::V6_vdmpyhisat_acc - 260
    {5009, 861, 4, 4 },
    // Hexagon::V6_vdmpyhsat - 261
    {4986, 865, 3, 3 },
    // Hexagon::V6_vdmpyhsat_acc - 262
    {5009, 868, 4, 4 },
    // Hexagon::V6_vdmpyhsuisat - 263
    {5033, 872, 3, 3 },
    // Hexagon::V6_vdmpyhsuisat_acc - 264
    {5061, 875, 4, 4 },
    // Hexagon::V6_vdmpyhsusat - 265
    {5090, 879, 3, 3 },
    // Hexagon::V6_vdmpyhsusat_acc - 266
    {5115, 882, 4, 4 },
    // Hexagon::V6_vdmpyhvsat - 267
    {4986, 886, 3, 3 },
    // Hexagon::V6_vdmpyhvsat_acc - 268
    {5009, 889, 4, 4 },
    // Hexagon::V6_vdsaduh - 269
    {5141, 893, 3, 3 },
    // Hexagon::V6_vdsaduh_acc - 270
    {5161, 896, 4, 4 },
    // Hexagon::V6_veqb - 271
    {5182, 900, 3, 3 },
    // Hexagon::V6_veqb_and - 272
    {5208, 903, 4, 4 },
    // Hexagon::V6_veqb_or - 273
    {5235, 907, 4, 4 },
    // Hexagon::V6_veqb_xor - 274
    {5262, 911, 4, 4 },
    // Hexagon::V6_veqh - 275
    {5289, 915, 3, 3 },
    // Hexagon::V6_veqh_and - 276
    {5315, 918, 4, 4 },
    // Hexagon::V6_veqh_or - 277
    {5342, 922, 4, 4 },
    // Hexagon::V6_veqh_xor - 278
    {5369, 926, 4, 4 },
    // Hexagon::V6_veqw - 279
    {5396, 930, 3, 3 },
    // Hexagon::V6_veqw_and - 280
    {5422, 933, 4, 4 },
    // Hexagon::V6_veqw_or - 281
    {5449, 937, 4, 4 },
    // Hexagon::V6_veqw_xor - 282
    {5476, 941, 4, 4 },
    // Hexagon::V6_vlsrh - 283
    {5503, 945, 3, 3 },
    // Hexagon::V6_vlsrhv - 284
    {5503, 948, 3, 3 },
    // Hexagon::V6_vlsrw - 285
    {5521, 951, 3, 3 },
    // Hexagon::V6_vlsrwv - 286
    {5521, 954, 3, 3 },
    // Hexagon::V6_vmaxb - 287
    {5539, 957, 3, 3 },
    // Hexagon::V6_vmaxh - 288
    {5557, 960, 3, 3 },
    // Hexagon::V6_vmaxub - 289
    {5575, 963, 3, 3 },
    // Hexagon::V6_vmaxuh - 290
    {5594, 966, 3, 3 },
    // Hexagon::V6_vmaxw - 291
    {5613, 969, 3, 3 },
    // Hexagon::V6_vminb - 292
    {5631, 972, 3, 3 },
    // Hexagon::V6_vminh - 293
    {5649, 975, 3, 3 },
    // Hexagon::V6_vminub - 294
    {5667, 978, 3, 3 },
    // Hexagon::V6_vminuh - 295
    {5686, 981, 3, 3 },
    // Hexagon::V6_vminw - 296
    {5705, 984, 3, 3 },
    // Hexagon::V6_vmpabus - 297
    {5723, 987, 3, 3 },
    // Hexagon::V6_vmpabus_acc - 298
    {5743, 990, 4, 4 },
    // Hexagon::V6_vmpabusv - 299
    {5723, 994, 3, 3 },
    // Hexagon::V6_vmpabuu - 300
    {5764, 997, 3, 3 },
    // Hexagon::V6_vmpabuu_acc - 301
    {5784, 1000, 4, 4 },
    // Hexagon::V6_vmpabuuv - 302
    {5764, 1004, 3, 3 },
    // Hexagon::V6_vmpahb - 303
    {5805, 1007, 3, 3 },
    // Hexagon::V6_vmpahb_acc - 304
    {5824, 1010, 4, 4 },
    // Hexagon::V6_vmpauhb - 305
    {5844, 1014, 3, 3 },
    // Hexagon::V6_vmpauhb_acc - 306
    {5864, 1017, 4, 4 },
    // Hexagon::V6_vmpybus - 307
    {5885, 1021, 3, 3 },
    // Hexagon::V6_vmpybus_acc - 308
    {5905, 1024, 4, 4 },
    // Hexagon::V6_vmpybusv - 309
    {5885, 1028, 3, 3 },
    // Hexagon::V6_vmpybusv_acc - 310
    {5905, 1031, 4, 4 },
    // Hexagon::V6_vmpybv - 311
    {5926, 1035, 3, 3 },
    // Hexagon::V6_vmpybv_acc - 312
    {5944, 1038, 4, 4 },
    // Hexagon::V6_vmpyewuh - 313
    {5963, 1042, 3, 3 },
    // Hexagon::V6_vmpyh - 314
    {5984, 1045, 3, 3 },
    // Hexagon::V6_vmpyh_acc - 315
    {6002, 1048, 4, 4 },
    // Hexagon::V6_vmpyhsat_acc - 316
    {6021, 1052, 4, 4 },
    // Hexagon::V6_vmpyhsrs - 317
    {6044, 1056, 3, 3 },
    // Hexagon::V6_vmpyhss - 318
    {6074, 1059, 3, 3 },
    // Hexagon::V6_vmpyhus - 319
    {6100, 1062, 3, 3 },
    // Hexagon::V6_vmpyhus_acc - 320
    {6120, 1065, 4, 4 },
    // Hexagon::V6_vmpyhv - 321
    {5984, 1069, 3, 3 },
    // Hexagon::V6_vmpyhv_acc - 322
    {6002, 1072, 4, 4 },
    // Hexagon::V6_vmpyhvsrs - 323
    {6044, 1076, 3, 3 },
    // Hexagon::V6_vmpyiewh_acc - 324
    {6141, 1079, 4, 4 },
    // Hexagon::V6_vmpyiewuh - 325
    {6163, 1083, 3, 3 },
    // Hexagon::V6_vmpyiewuh_acc - 326
    {6185, 1086, 4, 4 },
    // Hexagon::V6_vmpyih - 327
    {6208, 1090, 3, 3 },
    // Hexagon::V6_vmpyih_acc - 328
    {6227, 1093, 4, 4 },
    // Hexagon::V6_vmpyihb - 329
    {6247, 1097, 3, 3 },
    // Hexagon::V6_vmpyihb_acc - 330
    {6267, 1100, 4, 4 },
    // Hexagon::V6_vmpyiowh - 331
    {6288, 1104, 3, 3 },
    // Hexagon::V6_vmpyiwb - 332
    {6309, 1107, 3, 3 },
    // Hexagon::V6_vmpyiwb_acc - 333
    {6329, 1110, 4, 4 },
    // Hexagon::V6_vmpyiwh - 334
    {6350, 1114, 3, 3 },
    // Hexagon::V6_vmpyiwh_acc - 335
    {6370, 1117, 4, 4 },
    // Hexagon::V6_vmpyiwub - 336
    {6391, 1121, 3, 3 },
    // Hexagon::V6_vmpyiwub_acc - 337
    {6412, 1124, 4, 4 },
    // Hexagon::V6_vmpyowh - 338
    {6434, 1128, 3, 3 },
    // Hexagon::V6_vmpyowh_rnd - 339
    {6462, 1131, 3, 3 },
    // Hexagon::V6_vmpyub - 340
    {6494, 1134, 3, 3 },
    // Hexagon::V6_vmpyub_acc - 341
    {6513, 1137, 4, 4 },
    // Hexagon::V6_vmpyubv - 342
    {6494, 1141, 3, 3 },
    // Hexagon::V6_vmpyubv_acc - 343
    {6513, 1144, 4, 4 },
    // Hexagon::V6_vmpyuh - 344
    {6533, 1148, 3, 3 },
    // Hexagon::V6_vmpyuh_acc - 345
    {6552, 1151, 4, 4 },
    // Hexagon::V6_vmpyuhv - 346
    {6533, 1155, 3, 3 },
    // Hexagon::V6_vmpyuhv_acc - 347
    {6552, 1158, 4, 4 },
    // Hexagon::V6_vnavgb - 348
    {6572, 1162, 3, 3 },
    // Hexagon::V6_vnavgh - 349
    {6591, 1165, 3, 3 },
    // Hexagon::V6_vnavgub - 350
    {6610, 1168, 3, 3 },
    // Hexagon::V6_vnavgw - 351
    {6630, 1171, 3, 3 },
    // Hexagon::V6_vnormamth - 352
    {6649, 1174, 2, 2 },
    // Hexagon::V6_vnormamtw - 353
    {6668, 1176, 2, 2 },
    // Hexagon::V6_vpackeb - 354
    {6687, 1178, 3, 3 },
    // Hexagon::V6_vpackeh - 355
    {6707, 1181, 3, 3 },
    // Hexagon::V6_vpackhb_sat - 356
    {6727, 1184, 3, 3 },
    // Hexagon::V6_vpackhub_sat - 357
    {6751, 1187, 3, 3 },
    // Hexagon::V6_vpackob - 358
    {6776, 1190, 3, 3 },
    // Hexagon::V6_vpackoh - 359
    {6796, 1193, 3, 3 },
    // Hexagon::V6_vpackwh_sat - 360
    {6816, 1196, 3, 3 },
    // Hexagon::V6_vpackwuh_sat - 361
    {6840, 1199, 3, 3 },
    // Hexagon::V6_vpopcounth - 362
    {6865, 1202, 2, 2 },
    // Hexagon::V6_vrmpybub_rtt - 363
    {6885, 1204, 3, 3 },
    // Hexagon::V6_vrmpybub_rtt_acc - 364
    {6910, 1207, 4, 4 },
    // Hexagon::V6_vrmpybus - 365
    {6936, 1211, 3, 3 },
    // Hexagon::V6_vrmpybus_acc - 366
    {6957, 1214, 4, 4 },
    // Hexagon::V6_vrmpybusi - 367
    {6979, 1218, 4, 3 },
    // Hexagon::V6_vrmpybusi_acc - 368
    {7004, 1221, 5, 4 },
    // Hexagon::V6_vrmpybusv - 369
    {6936, 1225, 3, 3 },
    // Hexagon::V6_vrmpybusv_acc - 370
    {6957, 1228, 4, 4 },
    // Hexagon::V6_vrmpybv - 371
    {7030, 1232, 3, 3 },
    // Hexagon::V6_vrmpybv_acc - 372
    {7049, 1235, 4, 4 },
    // Hexagon::V6_vrmpyub - 373
    {7069, 1239, 3, 3 },
    // Hexagon::V6_vrmpyub_acc - 374
    {7089, 1242, 4, 4 },
    // Hexagon::V6_vrmpyub_rtt - 375
    {7110, 1246, 3, 3 },
    // Hexagon::V6_vrmpyub_rtt_acc - 376
    {7137, 1249, 4, 4 },
    // Hexagon::V6_vrmpyubi - 377
    {7165, 1253, 4, 3 },
    // Hexagon::V6_vrmpyubi_acc - 378
    {7189, 1256, 5, 4 },
    // Hexagon::V6_vrmpyubv - 379
    {7069, 1260, 3, 3 },
    // Hexagon::V6_vrmpyubv_acc - 380
    {7089, 1263, 4, 4 },
    // Hexagon::V6_vrotr - 381
    {7214, 1267, 3, 3 },
    // Hexagon::V6_vroundhb - 382
    {7232, 1270, 3, 3 },
    // Hexagon::V6_vroundhub - 383
    {7257, 1273, 3, 3 },
    // Hexagon::V6_vrounduhub - 384
    {7283, 1276, 3, 3 },
    // Hexagon::V6_vrounduwuh - 385
    {7310, 1279, 3, 3 },
    // Hexagon::V6_vroundwh - 386
    {7337, 1282, 3, 3 },
    // Hexagon::V6_vroundwuh - 387
    {7362, 1285, 3, 3 },
    // Hexagon::V6_vrsadubi - 388
    {7388, 1288, 4, 3 },
    // Hexagon::V6_vrsadubi_acc - 389
    {7412, 1291, 5, 4 },
    // Hexagon::V6_vsathub - 390
    {7437, 1295, 3, 3 },
    // Hexagon::V6_vsatuwuh - 391
    {7457, 1298, 3, 3 },
    // Hexagon::V6_vsatwh - 392
    {7478, 1301, 3, 3 },
    // Hexagon::V6_vsb - 393
    {7497, 1304, 2, 2 },
    // Hexagon::V6_vscattermh - 394
    {7512, 1306, 4, 4 },
    // Hexagon::V6_vscattermh_add - 395
    {7540, 1310, 4, 4 },
    // Hexagon::V6_vscattermhq - 396
    {7569, 1314, 5, 5 },
    // Hexagon::V6_vscattermhw - 397
    {7605, 1319, 4, 4 },
    // Hexagon::V6_vscattermhw_add - 398
    {7633, 1323, 4, 4 },
    // Hexagon::V6_vscattermhwq - 399
    {7662, 1327, 5, 5 },
    // Hexagon::V6_vscattermw - 400
    {7698, 1332, 4, 4 },
    // Hexagon::V6_vscattermw_add - 401
    {7726, 1336, 4, 4 },
    // Hexagon::V6_vscattermwq - 402
    {7755, 1340, 5, 5 },
    // Hexagon::V6_vsh - 403
    {7791, 1345, 2, 2 },
    // Hexagon::V6_vshufeh - 404
    {7806, 1347, 3, 3 },
    // Hexagon::V6_vshuff - 405
    {7827, 1350, 5, 5 },
    // Hexagon::V6_vshuffb - 406
    {7847, 1355, 2, 2 },
    // Hexagon::V6_vshuffeb - 407
    {7864, 1357, 3, 3 },
    // Hexagon::V6_vshuffh - 408
    {7885, 1360, 2, 2 },
    // Hexagon::V6_vshuffob - 409
    {7902, 1362, 3, 3 },
    // Hexagon::V6_vshufoeb - 410
    {7923, 1365, 3, 3 },
    // Hexagon::V6_vshufoeh - 411
    {7945, 1368, 3, 3 },
    // Hexagon::V6_vshufoh - 412
    {7967, 1371, 3, 3 },
    // Hexagon::V6_vsubb - 413
    {132, 1374, 3, 3 },
    // Hexagon::V6_vsubb_dv - 414
    {132, 1377, 3, 3 },
    // Hexagon::V6_vsubbnq - 415
    {7988, 1380, 4, 4 },
    // Hexagon::V6_vsubbq - 416
    {8012, 1384, 4, 4 },
    // Hexagon::V6_vsubbsat - 417
    {8035, 1388, 3, 3 },
    // Hexagon::V6_vsubbsat_dv - 418
    {8035, 1391, 3, 3 },
    // Hexagon::V6_vsubh - 419
    {8057, 1394, 3, 3 },
    // Hexagon::V6_vsubh_dv - 420
    {8057, 1397, 3, 3 },
    // Hexagon::V6_vsubhnq - 421
    {8075, 1400, 4, 4 },
    // Hexagon::V6_vsubhq - 422
    {8099, 1404, 4, 4 },
    // Hexagon::V6_vsubhsat - 423
    {8122, 1408, 3, 3 },
    // Hexagon::V6_vsubhsat_dv - 424
    {8122, 1411, 3, 3 },
    // Hexagon::V6_vsubhw - 425
    {8057, 1414, 3, 3 },
    // Hexagon::V6_vsububh - 426
    {8144, 1417, 3, 3 },
    // Hexagon::V6_vsububsat - 427
    {8163, 1420, 3, 3 },
    // Hexagon::V6_vsububsat_dv - 428
    {8163, 1423, 3, 3 },
    // Hexagon::V6_vsubuhsat - 429
    {8186, 1426, 3, 3 },
    // Hexagon::V6_vsubuhsat_dv - 430
    {8186, 1429, 3, 3 },
    // Hexagon::V6_vsubuhw - 431
    {8209, 1432, 3, 3 },
    // Hexagon::V6_vsubuwsat - 432
    {8228, 1435, 3, 3 },
    // Hexagon::V6_vsubuwsat_dv - 433
    {8228, 1438, 3, 3 },
    // Hexagon::V6_vsubw - 434
    {8251, 1441, 3, 3 },
    // Hexagon::V6_vsubw_dv - 435
    {8269, 1444, 3, 3 },
    {8251, 1447, 3, 3 },
    // Hexagon::V6_vsubwnq - 437
    {8277, 1450, 4, 4 },
    // Hexagon::V6_vsubwq - 438
    {8301, 1454, 4, 4 },
    // Hexagon::V6_vsubwsat - 439
    {8324, 1458, 3, 3 },
    // Hexagon::V6_vsubwsat_dv - 440
    {8324, 1461, 3, 3 },
    // Hexagon::V6_vtmpyb - 441
    {8346, 1464, 3, 3 },
    // Hexagon::V6_vtmpyb_acc - 442
    {8365, 1467, 4, 4 },
    // Hexagon::V6_vtmpybus - 443
    {8385, 1471, 3, 3 },
    // Hexagon::V6_vtmpybus_acc - 444
    {8406, 1474, 4, 4 },
    // Hexagon::V6_vtmpyhb - 445
    {8428, 1478, 3, 3 },
    // Hexagon::V6_vtmpyhb_acc - 446
    {8448, 1481, 4, 4 },
    // Hexagon::V6_vunpackb - 447
    {8469, 1485, 2, 2 },
    // Hexagon::V6_vunpackh - 448
    {8487, 1487, 2, 2 },
    // Hexagon::V6_vunpackoh - 449
    {8505, 1489, 3, 3 },
    // Hexagon::V6_vunpackub - 450
    {8525, 1492, 2, 2 },
    // Hexagon::V6_vunpackuh - 451
    {8544, 1494, 2, 2 },
    // Hexagon::V6_vxor - 452
    {8269, 1496, 3, 3 },
    // Hexagon::V6_vzb - 453
    {8563, 1499, 2, 2 },
    // Hexagon::V6_vzh - 454
    {8578, 1501, 2, 2 },
    // Hexagon::V6_zLd_ai - 455
    {8593, 1503, 2, 2 },
    // Hexagon::V6_zLd_pred_ai - 456
    {8606, 1505, 3, 3 },
    // Hexagon::Y2_crswap0 - 457
    {8627, 1508, 2, 1 },
    // Hexagon::Y2_dcfetchbo - 458
    {8642, 1509, 2, 2 },
  };

  static const AliasPatternCond Conds[] = {
    // (A2_andir IntRegs:$Rd32, IntRegs:$Rs32, 255) - 0
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(255)},
    // (A2_paddif IntRegs:$Rd32, PredRegs:$Pu4, IntRegs:$Rs32, 0) - 3
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    // (A2_paddifnew IntRegs:$Rd32, PredRegs:$Pu4, IntRegs:$Rs32, 0) - 7
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    // (A2_paddit IntRegs:$Rd32, PredRegs:$Pu4, IntRegs:$Rs32, 0) - 11
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    // (A2_padditnew IntRegs:$Rd32, PredRegs:$Pu4, IntRegs:$Rs32, 0) - 15
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    // (A2_subri IntRegs:$Rd32, 0, IntRegs:$Rs32) - 19
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    // (A2_subri IntRegs:$Rd32, -1, IntRegs:$Rs32) - 22
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(-1)},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    // (A2_vaddub DoubleRegs:$Rdd32, DoubleRegs:$Rss32, DoubleRegs:$Rtt32) - 25
    {AliasPatternCond::K_RegClass, Hexagon::DoubleRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::DoubleRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::DoubleRegsRegClassID},
    // (A2_vsubub DoubleRegs:$Rdd32, DoubleRegs:$Rss32, DoubleRegs:$Rtt32) - 28
    {AliasPatternCond::K_RegClass, Hexagon::DoubleRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::DoubleRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::DoubleRegsRegClassID},
    // (C2_cmpgt PredRegs:$Pd4, IntRegs:$Rt32, IntRegs:$Rs32) - 31
    {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    // (C2_cmpgtu PredRegs:$Pd4, IntRegs:$Rt32, IntRegs:$Rs32) - 34
    {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    // (C2_or PredRegs:$Pd4, PredRegs:$Ps4, PredRegs:$Ps4) - 37
    {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID},
    {AliasPatternCond::K_TiedReg, 1},
    // (J2_jumpf PredRegs:$Pu4, b30_2Imm:$Ii) - 40
    {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID},
    // (J2_jumprf PredRegs:$Pu4, IntRegs:$Rs32) - 41
    {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    // (J2_jumprt PredRegs:$Pu4, IntRegs:$Rs32) - 43
    {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    // (J2_jumpt PredRegs:$Pu4, b30_2Imm:$Ii) - 45
    {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID},
    // (J2_trap1 R0, u8_0Imm:$Ii) - 46
    {AliasPatternCond::K_Reg, Hexagon::R0},
    {AliasPatternCond::K_Ignore, 0},
    // (L2_deallocframe D15, R30) - 48
    {AliasPatternCond::K_Reg, Hexagon::D15},
    {AliasPatternCond::K_Reg, Hexagon::R30},
    // (L2_loadalignb_io DoubleRegs:$Ryy32, IntRegs:$Rs32, 0) - 50
    {AliasPatternCond::K_RegClass, Hexagon::DoubleRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    // (L2_loadalignh_io DoubleRegs:$Ryy32, IntRegs:$Rs32, 0) - 54
    {AliasPatternCond::K_RegClass, Hexagon::DoubleRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    // (L2_loadbsw2_io IntRegs:$Rd32, IntRegs:$Rs32, 0) - 58
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    // (L2_loadbsw4_io DoubleRegs:$Rdd32, IntRegs:$Rs32, 0) - 61
    {AliasPatternCond::K_RegClass, Hexagon::DoubleRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    // (L2_loadbzw2_io IntRegs:$Rd32, IntRegs:$Rs32, 0) - 64
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    // (L2_loadbzw4_io DoubleRegs:$Rdd32, IntRegs:$Rs32, 0) - 67
    {AliasPatternCond::K_RegClass, Hexagon::DoubleRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    // (L2_loadrb_io IntRegs:$Rd32, IntRegs:$Rs32, 0) - 70
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    // (L2_loadrd_io DoubleRegs:$Rdd32, IntRegs:$Rs32, 0) - 73
    {AliasPatternCond::K_RegClass, Hexagon::DoubleRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    // (L2_loadrh_io IntRegs:$Rd32, IntRegs:$Rs32, 0) - 76
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    // (L2_loadri_io IntRegs:$Rd32, IntRegs:$Rs32, 0) - 79
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    // (L2_loadrub_io IntRegs:$Rd32, IntRegs:$Rs32, 0) - 82
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    // (L2_loadruh_io IntRegs:$Rd32, IntRegs:$Rs32, 0) - 85
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    // (L2_ploadrbf_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0) - 88
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    // (L2_ploadrbfnew_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0) - 92
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    // (L2_ploadrbt_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0) - 96
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    // (L2_ploadrbtnew_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0) - 100
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    // (L2_ploadrdf_io DoubleRegs:$Rdd32, PredRegs:$Pt4, IntRegs:$Rs32, 0) - 104
    {AliasPatternCond::K_RegClass, Hexagon::DoubleRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    // (L2_ploadrdfnew_io DoubleRegs:$Rdd32, PredRegs:$Pt4, IntRegs:$Rs32, 0) - 108
    {AliasPatternCond::K_RegClass, Hexagon::DoubleRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    // (L2_ploadrdt_io DoubleRegs:$Rdd32, PredRegs:$Pt4, IntRegs:$Rs32, 0) - 112
    {AliasPatternCond::K_RegClass, Hexagon::DoubleRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    // (L2_ploadrdtnew_io DoubleRegs:$Rdd32, PredRegs:$Pt4, IntRegs:$Rs32, 0) - 116
    {AliasPatternCond::K_RegClass, Hexagon::DoubleRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    // (L2_ploadrhf_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0) - 120
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    // (L2_ploadrhfnew_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0) - 124
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    // (L2_ploadrht_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0) - 128
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    // (L2_ploadrhtnew_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0) - 132
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    // (L2_ploadrif_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0) - 136
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    // (L2_ploadrifnew_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0) - 140
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    // (L2_ploadrit_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0) - 144
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    // (L2_ploadritnew_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0) - 148
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    // (L2_ploadrubf_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0) - 152
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    // (L2_ploadrubfnew_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0) - 156
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    // (L2_ploadrubt_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0) - 160
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    // (L2_ploadrubtnew_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0) - 164
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    // (L2_ploadruhf_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0) - 168
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    // (L2_ploadruhfnew_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0) - 172
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    // (L2_ploadruht_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0) - 176
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    // (L2_ploadruhtnew_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0) - 180
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    // (L4_add_memopb_io IntRegs:$Rs32, 0, IntRegs:$Rt32) - 184
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    // (L4_add_memoph_io IntRegs:$Rs32, 0, IntRegs:$Rt32) - 187
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    // (L4_add_memopw_io IntRegs:$Rs32, 0, IntRegs:$Rt32) - 190
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    // (L4_and_memopb_io IntRegs:$Rs32, 0, IntRegs:$Rt32) - 193
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    // (L4_and_memoph_io IntRegs:$Rs32, 0, IntRegs:$Rt32) - 196
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    // (L4_and_memopw_io IntRegs:$Rs32, 0, IntRegs:$Rt32) - 199
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    // (L4_iadd_memopb_io IntRegs:$Rs32, 0, u5_0Imm:$II) - 202
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    // (L4_iadd_memoph_io IntRegs:$Rs32, 0, u5_0Imm:$II) - 204
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    // (L4_iadd_memopw_io IntRegs:$Rs32, 0, u5_0Imm:$II) - 206
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    // (L4_iand_memopb_io IntRegs:$Rs32, 0, u5_0Imm:$II) - 208
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    // (L4_iand_memoph_io IntRegs:$Rs32, 0, u5_0Imm:$II) - 210
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    // (L4_iand_memopw_io IntRegs:$Rs32, 0, u5_0Imm:$II) - 212
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    // (L4_ior_memopb_io IntRegs:$Rs32, 0, u5_0Imm:$II) - 214
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    // (L4_ior_memoph_io IntRegs:$Rs32, 0, u5_0Imm:$II) - 216
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    // (L4_ior_memopw_io IntRegs:$Rs32, 0, u5_0Imm:$II) - 218
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    // (L4_isub_memopb_io IntRegs:$Rs32, 0, u5_0Imm:$II) - 220
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    // (L4_isub_memoph_io IntRegs:$Rs32, 0, u5_0Imm:$II) - 222
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    // (L4_isub_memopw_io IntRegs:$Rs32, 0, u5_0Imm:$II) - 224
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    // (L4_or_memopb_io IntRegs:$Rs32, 0, IntRegs:$Rt32) - 226
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    // (L4_or_memoph_io IntRegs:$Rs32, 0, IntRegs:$Rt32) - 229
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    // (L4_or_memopw_io IntRegs:$Rs32, 0, IntRegs:$Rt32) - 232
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    // (L4_return D15, R30) - 235
    {AliasPatternCond::K_Reg, Hexagon::D15},
    {AliasPatternCond::K_Reg, Hexagon::R30},
    // (L4_return_f D15, PredRegs:$Pv4, R30) - 237
    {AliasPatternCond::K_Reg, Hexagon::D15},
    {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID},
    {AliasPatternCond::K_Reg, Hexagon::R30},
    // (L4_return_fnew_pnt D15, PredRegs:$Pv4, R30) - 240
    {AliasPatternCond::K_Reg, Hexagon::D15},
    {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID},
    {AliasPatternCond::K_Reg, Hexagon::R30},
    // (L4_return_fnew_pt D15, PredRegs:$Pv4, R30) - 243
    {AliasPatternCond::K_Reg, Hexagon::D15},
    {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID},
    {AliasPatternCond::K_Reg, Hexagon::R30},
    // (L4_return_t D15, PredRegs:$Pv4, R30) - 246
    {AliasPatternCond::K_Reg, Hexagon::D15},
    {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID},
    {AliasPatternCond::K_Reg, Hexagon::R30},
    // (L4_return_tnew_pnt D15, PredRegs:$Pv4, R30) - 249
    {AliasPatternCond::K_Reg, Hexagon::D15},
    {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID},
    {AliasPatternCond::K_Reg, Hexagon::R30},
    // (L4_return_tnew_pt D15, PredRegs:$Pv4, R30) - 252
    {AliasPatternCond::K_Reg, Hexagon::D15},
    {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID},
    {AliasPatternCond::K_Reg, Hexagon::R30},
    // (L4_sub_memopb_io IntRegs:$Rs32, 0, IntRegs:$Rt32) - 255
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    // (L4_sub_memoph_io IntRegs:$Rs32, 0, IntRegs:$Rt32) - 258
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    // (L4_sub_memopw_io IntRegs:$Rs32, 0, IntRegs:$Rt32) - 261
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    // (M2_mpyi IntRegs:$Rd32, IntRegs:$Rs32, IntRegs:$Rt32) - 264
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    // (M7_dcmpyrwc DoubleRegs:$Rdd32, DoubleRegs:$Rss32, DoubleRegs:$Rtt32) - 267
    {AliasPatternCond::K_RegClass, Hexagon::DoubleRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::DoubleRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::DoubleRegsRegClassID},
    // (M7_dcmpyrwc_acc DoubleRegs:$Rxx32, DoubleRegs:$Rss32, DoubleRegs:$Rtt32) - 270
    {AliasPatternCond::K_RegClass, Hexagon::DoubleRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_RegClass, Hexagon::DoubleRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::DoubleRegsRegClassID},
    // (S2_allocframe R29, u11_3Imm:$Ii) - 274
    {AliasPatternCond::K_Reg, Hexagon::R29},
    {AliasPatternCond::K_Ignore, 0},
    // (S2_pstorerbf_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Rt32) - 276
    {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    // (S2_pstorerbnewf_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Nt8) - 280
    {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    // (S2_pstorerbnewt_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Nt8) - 284
    {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    // (S2_pstorerbt_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Rt32) - 288
    {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    // (S2_pstorerdf_io PredRegs:$Pv4, IntRegs:$Rs32, 0, DoubleRegs:$Rtt32) - 292
    {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    {AliasPatternCond::K_RegClass, Hexagon::DoubleRegsRegClassID},
    // (S2_pstorerdt_io PredRegs:$Pv4, IntRegs:$Rs32, 0, DoubleRegs:$Rtt32) - 296
    {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    {AliasPatternCond::K_RegClass, Hexagon::DoubleRegsRegClassID},
    // (S2_pstorerff_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Rt32) - 300
    {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    // (S2_pstorerft_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Rt32) - 304
    {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    // (S2_pstorerhf_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Rt32) - 308
    {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    // (S2_pstorerhnewf_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Nt8) - 312
    {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    // (S2_pstorerhnewt_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Nt8) - 316
    {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    // (S2_pstorerht_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Rt32) - 320
    {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    // (S2_pstorerif_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Rt32) - 324
    {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    // (S2_pstorerinewf_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Nt8) - 328
    {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    // (S2_pstorerinewt_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Nt8) - 332
    {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    // (S2_pstorerit_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Rt32) - 336
    {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    // (S2_storerb_io IntRegs:$Rs32, 0, IntRegs:$Rt32) - 340
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    // (S2_storerbnew_io IntRegs:$Rs32, 0, IntRegs:$Nt8) - 343
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    // (S2_storerd_io IntRegs:$Rs32, 0, DoubleRegs:$Rtt32) - 346
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    {AliasPatternCond::K_RegClass, Hexagon::DoubleRegsRegClassID},
    // (S2_storerf_io IntRegs:$Rs32, 0, IntRegs:$Rt32) - 349
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    // (S2_storerh_io IntRegs:$Rs32, 0, IntRegs:$Rt32) - 352
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    // (S2_storerhnew_io IntRegs:$Rs32, 0, IntRegs:$Nt8) - 355
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    // (S2_storeri_io IntRegs:$Rs32, 0, IntRegs:$Rt32) - 358
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    // (S2_storerinew_io IntRegs:$Rs32, 0, IntRegs:$Nt8) - 361
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    // (S2_tableidxb IntRegs:$Rx32, IntRegs:$Rs32, u4_0Imm:$Ii, u5_0Imm:$II) - 364
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    // (S4_pstorerbfnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Rt32) - 368
    {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    // (S4_pstorerbnewfnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Nt8) - 372
    {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    // (S4_pstorerbnewtnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Nt8) - 376
    {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    // (S4_pstorerbtnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Rt32) - 380
    {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    // (S4_pstorerdfnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, DoubleRegs:$Rtt32) - 384
    {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    {AliasPatternCond::K_RegClass, Hexagon::DoubleRegsRegClassID},
    // (S4_pstorerdtnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, DoubleRegs:$Rtt32) - 388
    {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    {AliasPatternCond::K_RegClass, Hexagon::DoubleRegsRegClassID},
    // (S4_pstorerffnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Rt32) - 392
    {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    // (S4_pstorerftnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Rt32) - 396
    {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    // (S4_pstorerhfnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Rt32) - 400
    {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    // (S4_pstorerhnewfnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Nt8) - 404
    {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    // (S4_pstorerhnewtnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Nt8) - 408
    {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    // (S4_pstorerhtnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Rt32) - 412
    {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    // (S4_pstorerifnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Rt32) - 416
    {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    // (S4_pstorerinewfnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Nt8) - 420
    {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    // (S4_pstorerinewtnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Nt8) - 424
    {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    // (S4_pstoreritnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Rt32) - 428
    {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    // (S4_storeirb_io IntRegs:$Rs32, 0, s32_0Imm:$II) - 432
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    // (S4_storeirbf_io PredRegs:$Pv4, IntRegs:$Rs32, 0, s32_0Imm:$II) - 434
    {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    // (S4_storeirbfnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, s32_0Imm:$II) - 437
    {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    // (S4_storeirbt_io PredRegs:$Pv4, IntRegs:$Rs32, 0, s32_0Imm:$II) - 440
    {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    // (S4_storeirbtnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, s32_0Imm:$II) - 443
    {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    // (S4_storeirh_io IntRegs:$Rs32, 0, s32_0Imm:$II) - 446
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    // (S4_storeirhf_io PredRegs:$Pv4, IntRegs:$Rs32, 0, s32_0Imm:$II) - 448
    {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    // (S4_storeirhfnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, s32_0Imm:$II) - 451
    {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    // (S4_storeirht_io PredRegs:$Pv4, IntRegs:$Rs32, 0, s32_0Imm:$II) - 454
    {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    // (S4_storeirhtnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, s32_0Imm:$II) - 457
    {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    // (S4_storeiri_io IntRegs:$Rs32, 0, s32_0Imm:$II) - 460
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    // (S4_storeirif_io PredRegs:$Pv4, IntRegs:$Rs32, 0, s32_0Imm:$II) - 462
    {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    // (S4_storeirifnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, s32_0Imm:$II) - 465
    {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    // (S4_storeirit_io PredRegs:$Pv4, IntRegs:$Rs32, 0, s32_0Imm:$II) - 468
    {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    // (S4_storeiritnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, s32_0Imm:$II) - 471
    {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    // (V6_extractw IntRegs:$Rd32, HvxVR:$Vu32, IntRegs:$Rs32) - 474
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    // (V6_v6mpyhubs10 HvxWR:$Vdd32, HvxWR:$Vuu32, HvxWR:$Vvv32, u2_0Imm:$Ii) - 477
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    // (V6_v6mpyvubs10 HvxWR:$Vdd32, HvxWR:$Vuu32, HvxWR:$Vvv32, u2_0Imm:$Ii) - 480
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    // (V6_vL32Ub_ai HvxVR:$Vd32, IntRegs:$Rt32, 0) - 483
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    // (V6_vL32b_ai HvxVR:$Vd32, IntRegs:$Rt32, 0) - 486
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    // (V6_vL32b_cur_npred_pi HvxVR:$Vd32, IntRegs:$Rt32, PredRegs:$Pv4, 0) - 489
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    // (V6_vL32b_cur_pred_pi HvxVR:$Vd32, IntRegs:$Rt32, PredRegs:$Pv4, 0) - 494
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    // (V6_vL32b_npred_ai HvxVR:$Vd32, PredRegs:$Pv4, IntRegs:$Rt32, 0) - 499
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    // (V6_vL32b_npred_pi HvxVR:$Vd32, IntRegs:$Rt32, PredRegs:$Pv4, 0) - 503
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    // (V6_vL32b_nt_ai HvxVR:$Vd32, IntRegs:$Rt32, 0) - 508
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    // (V6_vL32b_nt_cur_npred_pi HvxVR:$Vd32, IntRegs:$Rt32, PredRegs:$Pv4, 0) - 511
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    // (V6_vL32b_nt_cur_pred_pi HvxVR:$Vd32, IntRegs:$Rt32, PredRegs:$Pv4, 0) - 516
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    // (V6_vL32b_nt_npred_ai HvxVR:$Vd32, PredRegs:$Pv4, IntRegs:$Rt32, 0) - 521
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    // (V6_vL32b_nt_npred_pi HvxVR:$Vd32, IntRegs:$Rt32, PredRegs:$Pv4, 0) - 525
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    // (V6_vL32b_nt_pred_ai HvxVR:$Vd32, PredRegs:$Pv4, IntRegs:$Rt32, 0) - 530
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    // (V6_vL32b_nt_tmp_pred_ai HvxVR:$Vd32, PredRegs:$Pv4, IntRegs:$Rt32, 0) - 534
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    // (V6_vL32b_pred_ai HvxVR:$Vd32, PredRegs:$Pv4, IntRegs:$Rt32, 0) - 538
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    // (V6_vL32b_tmp_pred_ai HvxVR:$Vd32, PredRegs:$Pv4, IntRegs:$Rt32, 0) - 542
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    // (V6_vS32Ub_ai IntRegs:$Rt32, 0, HvxVR:$Vs32) - 546
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vS32Ub_npred_ai PredRegs:$Pv4, IntRegs:$Rt32, 0, HvxVR:$Vs32) - 549
    {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vS32Ub_pred_ai PredRegs:$Pv4, IntRegs:$Rt32, 0, HvxVR:$Vs32) - 553
    {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vS32b_ai IntRegs:$Rt32, 0, HvxVR:$Vs32) - 557
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vS32b_new_ai IntRegs:$Rt32, 0, HvxVR:$Os8) - 560
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vS32b_npred_ai PredRegs:$Pv4, IntRegs:$Rt32, 0, HvxVR:$Vs32) - 563
    {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vS32b_nqpred_ai HvxQR:$Qv4, IntRegs:$Rt32, 0, HvxVR:$Vs32) - 567
    {AliasPatternCond::K_RegClass, Hexagon::HvxQRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vS32b_nt_ai IntRegs:$Rt32, 0, HvxVR:$Vs32) - 571
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vS32b_nt_new_ai IntRegs:$Rt32, 0, HvxVR:$Os8) - 574
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vS32b_nt_npred_ai PredRegs:$Pv4, IntRegs:$Rt32, 0, HvxVR:$Vs32) - 577
    {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vS32b_nt_nqpred_ai HvxQR:$Qv4, IntRegs:$Rt32, 0, HvxVR:$Vs32) - 581
    {AliasPatternCond::K_RegClass, Hexagon::HvxQRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vS32b_nt_pred_ai PredRegs:$Pv4, IntRegs:$Rt32, 0, HvxVR:$Vs32) - 585
    {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vS32b_nt_qpred_ai HvxQR:$Qv4, IntRegs:$Rt32, 0, HvxVR:$Vs32) - 589
    {AliasPatternCond::K_RegClass, Hexagon::HvxQRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vS32b_pred_ai PredRegs:$Pv4, IntRegs:$Rt32, 0, HvxVR:$Vs32) - 593
    {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vS32b_qpred_ai HvxQR:$Qv4, IntRegs:$Rt32, 0, HvxVR:$Vs32) - 597
    {AliasPatternCond::K_RegClass, Hexagon::HvxQRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vabsb_sat HvxVR:$Vd32, HvxVR:$Vu32) - 601
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vabsdiffh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 603
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vabsdiffub HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 606
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vabsdiffuh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 609
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vabsdiffw HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 612
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vabsh_sat HvxVR:$Vd32, HvxVR:$Vu32) - 615
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vabsw_sat HvxVR:$Vd32, HvxVR:$Vu32) - 617
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vaddb HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 619
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vaddb_dv HvxWR:$Vdd32, HvxWR:$Vuu32, HvxWR:$Vvv32) - 622
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    // (V6_vaddbnq HvxVR:$Vx32, HvxQR:$Qv4, HvxVR:$Vu32) - 625
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxQRRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vaddbq HvxVR:$Vx32, HvxQR:$Qv4, HvxVR:$Vu32) - 629
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxQRRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vaddbsat HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 633
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vaddbsat_dv HvxWR:$Vdd32, HvxWR:$Vuu32, HvxWR:$Vvv32) - 636
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    // (V6_vaddh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 639
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vaddh_dv HvxWR:$Vdd32, HvxWR:$Vuu32, HvxWR:$Vvv32) - 642
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    // (V6_vaddhnq HvxVR:$Vx32, HvxQR:$Qv4, HvxVR:$Vu32) - 645
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxQRRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vaddhq HvxVR:$Vx32, HvxQR:$Qv4, HvxVR:$Vu32) - 649
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxQRRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vaddhsat HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 653
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vaddhsat_dv HvxWR:$Vdd32, HvxWR:$Vuu32, HvxWR:$Vvv32) - 656
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    // (V6_vaddhw HvxWR:$Vdd32, HvxVR:$Vu32, HvxVR:$Vv32) - 659
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vaddhw_acc HvxWR:$Vxx32, HvxVR:$Vu32, HvxVR:$Vv32) - 662
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vaddubh HvxWR:$Vdd32, HvxVR:$Vu32, HvxVR:$Vv32) - 666
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vaddubh_acc HvxWR:$Vxx32, HvxVR:$Vu32, HvxVR:$Vv32) - 669
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vaddubsat HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 673
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vaddubsat_dv HvxWR:$Vdd32, HvxWR:$Vuu32, HvxWR:$Vvv32) - 676
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    // (V6_vadduhsat HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 679
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vadduhsat_dv HvxWR:$Vdd32, HvxWR:$Vuu32, HvxWR:$Vvv32) - 682
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    // (V6_vadduhw HvxWR:$Vdd32, HvxVR:$Vu32, HvxVR:$Vv32) - 685
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vadduhw_acc HvxWR:$Vxx32, HvxVR:$Vu32, HvxVR:$Vv32) - 688
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vadduwsat HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 692
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vadduwsat_dv HvxWR:$Vdd32, HvxWR:$Vuu32, HvxWR:$Vvv32) - 695
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    // (V6_vaddw HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 698
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vaddw_dv HvxWR:$Vdd32, HvxWR:$Vuu32, HvxWR:$Vvv32) - 701
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    // (V6_vaddwnq HvxVR:$Vx32, HvxQR:$Qv4, HvxVR:$Vu32) - 704
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxQRRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vaddwq HvxVR:$Vx32, HvxQR:$Qv4, HvxVR:$Vu32) - 708
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxQRRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vaddwsat HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 712
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vaddwsat_dv HvxWR:$Vdd32, HvxWR:$Vuu32, HvxWR:$Vvv32) - 715
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    // (V6_vandnqrt HvxVR:$Vd32, HvxQR:$Qu4, IntRegs:$Rt32) - 718
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxQRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    // (V6_vandnqrt_acc HvxVR:$Vx32, HvxQR:$Qu4, IntRegs:$Rt32) - 721
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_RegClass, Hexagon::HvxQRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    // (V6_vandqrt HvxVR:$Vd32, HvxQR:$Qu4, IntRegs:$Rt32) - 725
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxQRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    // (V6_vandqrt_acc HvxVR:$Vx32, HvxQR:$Qu4, IntRegs:$Rt32) - 728
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_RegClass, Hexagon::HvxQRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    // (V6_vandvrt HvxQR:$Qd4, HvxVR:$Vu32, IntRegs:$Rt32) - 732
    {AliasPatternCond::K_RegClass, Hexagon::HvxQRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    // (V6_vandvrt_acc HvxQR:$Qx4, HvxVR:$Vu32, IntRegs:$Rt32) - 735
    {AliasPatternCond::K_RegClass, Hexagon::HvxQRRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    // (V6_vaslh HvxVR:$Vd32, HvxVR:$Vu32, IntRegs:$Rt32) - 739
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    // (V6_vaslh_acc HvxVR:$Vx32, HvxVR:$Vu32, IntRegs:$Rt32) - 742
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    // (V6_vaslhv HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 746
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vaslw HvxVR:$Vd32, HvxVR:$Vu32, IntRegs:$Rt32) - 749
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    // (V6_vaslw_acc HvxVR:$Vx32, HvxVR:$Vu32, IntRegs:$Rt32) - 752
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    // (V6_vaslwv HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 756
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vasr_into HvxWR:$Vxx32, HvxVR:$Vu32, HvxVR:$Vv32) - 759
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vasrh HvxVR:$Vd32, HvxVR:$Vu32, IntRegs:$Rt32) - 763
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    // (V6_vasrh_acc HvxVR:$Vx32, HvxVR:$Vu32, IntRegs:$Rt32) - 766
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    // (V6_vasrhv HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 770
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vasrw HvxVR:$Vd32, HvxVR:$Vu32, IntRegs:$Rt32) - 773
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    // (V6_vasrw_acc HvxVR:$Vx32, HvxVR:$Vu32, IntRegs:$Rt32) - 776
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    // (V6_vasrwv HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 780
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vavgb HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 783
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vavgbrnd HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 786
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vavgh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 789
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vavghrnd HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 792
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vavgub HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 795
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vavgubrnd HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 798
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vavguh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 801
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vavguhrnd HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 804
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vavguw HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 807
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vavguwrnd HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 810
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vavgw HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 813
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vavgwrnd HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 816
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vcl0h HvxVR:$Vd32, HvxVR:$Vu32) - 819
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vcl0w HvxVR:$Vd32, HvxVR:$Vu32) - 821
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vdealb HvxVR:$Vd32, HvxVR:$Vu32) - 823
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vdealb4w HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 825
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vdealh HvxVR:$Vd32, HvxVR:$Vu32) - 828
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vdmpybus HvxVR:$Vd32, HvxVR:$Vu32, IntRegs:$Rt32) - 830
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    // (V6_vdmpybus_acc HvxVR:$Vx32, HvxVR:$Vu32, IntRegs:$Rt32) - 833
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    // (V6_vdmpybus_dv HvxWR:$Vdd32, HvxWR:$Vuu32, IntRegs:$Rt32) - 837
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    // (V6_vdmpybus_dv_acc HvxWR:$Vxx32, HvxWR:$Vuu32, IntRegs:$Rt32) - 840
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    // (V6_vdmpyhb HvxVR:$Vd32, HvxVR:$Vu32, IntRegs:$Rt32) - 844
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    // (V6_vdmpyhb_acc HvxVR:$Vx32, HvxVR:$Vu32, IntRegs:$Rt32) - 847
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    // (V6_vdmpyhb_dv HvxWR:$Vdd32, HvxWR:$Vuu32, IntRegs:$Rt32) - 851
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    // (V6_vdmpyhb_dv_acc HvxWR:$Vxx32, HvxWR:$Vuu32, IntRegs:$Rt32) - 854
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    // (V6_vdmpyhisat HvxVR:$Vd32, HvxWR:$Vuu32, IntRegs:$Rt32) - 858
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    // (V6_vdmpyhisat_acc HvxVR:$Vx32, HvxWR:$Vuu32, IntRegs:$Rt32) - 861
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    // (V6_vdmpyhsat HvxVR:$Vd32, HvxVR:$Vu32, IntRegs:$Rt32) - 865
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    // (V6_vdmpyhsat_acc HvxVR:$Vx32, HvxVR:$Vu32, IntRegs:$Rt32) - 868
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    // (V6_vdmpyhsuisat HvxVR:$Vd32, HvxWR:$Vuu32, IntRegs:$Rt32) - 872
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    // (V6_vdmpyhsuisat_acc HvxVR:$Vx32, HvxWR:$Vuu32, IntRegs:$Rt32) - 875
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    // (V6_vdmpyhsusat HvxVR:$Vd32, HvxVR:$Vu32, IntRegs:$Rt32) - 879
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    // (V6_vdmpyhsusat_acc HvxVR:$Vx32, HvxVR:$Vu32, IntRegs:$Rt32) - 882
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    // (V6_vdmpyhvsat HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 886
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vdmpyhvsat_acc HvxVR:$Vx32, HvxVR:$Vu32, HvxVR:$Vv32) - 889
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vdsaduh HvxWR:$Vdd32, HvxWR:$Vuu32, IntRegs:$Rt32) - 893
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    // (V6_vdsaduh_acc HvxWR:$Vxx32, HvxWR:$Vuu32, IntRegs:$Rt32) - 896
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    // (V6_veqb HvxQR:$Qd4, HvxVR:$Vu32, HvxVR:$Vv32) - 900
    {AliasPatternCond::K_RegClass, Hexagon::HvxQRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_veqb_and HvxQR:$Qx4, HvxVR:$Vu32, HvxVR:$Vv32) - 903
    {AliasPatternCond::K_RegClass, Hexagon::HvxQRRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_veqb_or HvxQR:$Qx4, HvxVR:$Vu32, HvxVR:$Vv32) - 907
    {AliasPatternCond::K_RegClass, Hexagon::HvxQRRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_veqb_xor HvxQR:$Qx4, HvxVR:$Vu32, HvxVR:$Vv32) - 911
    {AliasPatternCond::K_RegClass, Hexagon::HvxQRRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_veqh HvxQR:$Qd4, HvxVR:$Vu32, HvxVR:$Vv32) - 915
    {AliasPatternCond::K_RegClass, Hexagon::HvxQRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_veqh_and HvxQR:$Qx4, HvxVR:$Vu32, HvxVR:$Vv32) - 918
    {AliasPatternCond::K_RegClass, Hexagon::HvxQRRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_veqh_or HvxQR:$Qx4, HvxVR:$Vu32, HvxVR:$Vv32) - 922
    {AliasPatternCond::K_RegClass, Hexagon::HvxQRRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_veqh_xor HvxQR:$Qx4, HvxVR:$Vu32, HvxVR:$Vv32) - 926
    {AliasPatternCond::K_RegClass, Hexagon::HvxQRRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_veqw HvxQR:$Qd4, HvxVR:$Vu32, HvxVR:$Vv32) - 930
    {AliasPatternCond::K_RegClass, Hexagon::HvxQRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_veqw_and HvxQR:$Qx4, HvxVR:$Vu32, HvxVR:$Vv32) - 933
    {AliasPatternCond::K_RegClass, Hexagon::HvxQRRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_veqw_or HvxQR:$Qx4, HvxVR:$Vu32, HvxVR:$Vv32) - 937
    {AliasPatternCond::K_RegClass, Hexagon::HvxQRRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_veqw_xor HvxQR:$Qx4, HvxVR:$Vu32, HvxVR:$Vv32) - 941
    {AliasPatternCond::K_RegClass, Hexagon::HvxQRRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vlsrh HvxVR:$Vd32, HvxVR:$Vu32, IntRegs:$Rt32) - 945
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    // (V6_vlsrhv HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 948
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vlsrw HvxVR:$Vd32, HvxVR:$Vu32, IntRegs:$Rt32) - 951
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    // (V6_vlsrwv HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 954
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vmaxb HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 957
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vmaxh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 960
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vmaxub HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 963
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vmaxuh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 966
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vmaxw HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 969
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vminb HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 972
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vminh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 975
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vminub HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 978
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vminuh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 981
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vminw HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 984
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vmpabus HvxWR:$Vdd32, HvxWR:$Vuu32, IntRegs:$Rt32) - 987
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    // (V6_vmpabus_acc HvxWR:$Vxx32, HvxWR:$Vuu32, IntRegs:$Rt32) - 990
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    // (V6_vmpabusv HvxWR:$Vdd32, HvxWR:$Vuu32, HvxWR:$Vvv32) - 994
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    // (V6_vmpabuu HvxWR:$Vdd32, HvxWR:$Vuu32, IntRegs:$Rt32) - 997
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    // (V6_vmpabuu_acc HvxWR:$Vxx32, HvxWR:$Vuu32, IntRegs:$Rt32) - 1000
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    // (V6_vmpabuuv HvxWR:$Vdd32, HvxWR:$Vuu32, HvxWR:$Vvv32) - 1004
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    // (V6_vmpahb HvxWR:$Vdd32, HvxWR:$Vuu32, IntRegs:$Rt32) - 1007
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    // (V6_vmpahb_acc HvxWR:$Vxx32, HvxWR:$Vuu32, IntRegs:$Rt32) - 1010
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    // (V6_vmpauhb HvxWR:$Vdd32, HvxWR:$Vuu32, IntRegs:$Rt32) - 1014
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    // (V6_vmpauhb_acc HvxWR:$Vxx32, HvxWR:$Vuu32, IntRegs:$Rt32) - 1017
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    // (V6_vmpybus HvxWR:$Vdd32, HvxVR:$Vu32, IntRegs:$Rt32) - 1021
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    // (V6_vmpybus_acc HvxWR:$Vxx32, HvxVR:$Vu32, IntRegs:$Rt32) - 1024
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    // (V6_vmpybusv HvxWR:$Vdd32, HvxVR:$Vu32, HvxVR:$Vv32) - 1028
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vmpybusv_acc HvxWR:$Vxx32, HvxVR:$Vu32, HvxVR:$Vv32) - 1031
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vmpybv HvxWR:$Vdd32, HvxVR:$Vu32, HvxVR:$Vv32) - 1035
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vmpybv_acc HvxWR:$Vxx32, HvxVR:$Vu32, HvxVR:$Vv32) - 1038
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vmpyewuh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 1042
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vmpyh HvxWR:$Vdd32, HvxVR:$Vu32, IntRegs:$Rt32) - 1045
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    // (V6_vmpyh_acc HvxWR:$Vxx32, HvxVR:$Vu32, IntRegs:$Rt32) - 1048
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    // (V6_vmpyhsat_acc HvxWR:$Vxx32, HvxVR:$Vu32, IntRegs:$Rt32) - 1052
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    // (V6_vmpyhsrs HvxVR:$Vd32, HvxVR:$Vu32, IntRegs:$Rt32) - 1056
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    // (V6_vmpyhss HvxVR:$Vd32, HvxVR:$Vu32, IntRegs:$Rt32) - 1059
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    // (V6_vmpyhus HvxWR:$Vdd32, HvxVR:$Vu32, HvxVR:$Vv32) - 1062
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vmpyhus_acc HvxWR:$Vxx32, HvxVR:$Vu32, HvxVR:$Vv32) - 1065
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vmpyhv HvxWR:$Vdd32, HvxVR:$Vu32, HvxVR:$Vv32) - 1069
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vmpyhv_acc HvxWR:$Vxx32, HvxVR:$Vu32, HvxVR:$Vv32) - 1072
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vmpyhvsrs HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 1076
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vmpyiewh_acc HvxVR:$Vx32, HvxVR:$Vu32, HvxVR:$Vv32) - 1079
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vmpyiewuh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 1083
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vmpyiewuh_acc HvxVR:$Vx32, HvxVR:$Vu32, HvxVR:$Vv32) - 1086
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vmpyih HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 1090
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vmpyih_acc HvxVR:$Vx32, HvxVR:$Vu32, HvxVR:$Vv32) - 1093
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vmpyihb HvxVR:$Vd32, HvxVR:$Vu32, IntRegs:$Rt32) - 1097
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    // (V6_vmpyihb_acc HvxVR:$Vx32, HvxVR:$Vu32, IntRegs:$Rt32) - 1100
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    // (V6_vmpyiowh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 1104
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vmpyiwb HvxVR:$Vd32, HvxVR:$Vu32, IntRegs:$Rt32) - 1107
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    // (V6_vmpyiwb_acc HvxVR:$Vx32, HvxVR:$Vu32, IntRegs:$Rt32) - 1110
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    // (V6_vmpyiwh HvxVR:$Vd32, HvxVR:$Vu32, IntRegs:$Rt32) - 1114
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    // (V6_vmpyiwh_acc HvxVR:$Vx32, HvxVR:$Vu32, IntRegs:$Rt32) - 1117
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    // (V6_vmpyiwub HvxVR:$Vd32, HvxVR:$Vu32, IntRegs:$Rt32) - 1121
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    // (V6_vmpyiwub_acc HvxVR:$Vx32, HvxVR:$Vu32, IntRegs:$Rt32) - 1124
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    // (V6_vmpyowh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 1128
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vmpyowh_rnd HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 1131
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vmpyub HvxWR:$Vdd32, HvxVR:$Vu32, IntRegs:$Rt32) - 1134
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    // (V6_vmpyub_acc HvxWR:$Vxx32, HvxVR:$Vu32, IntRegs:$Rt32) - 1137
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    // (V6_vmpyubv HvxWR:$Vdd32, HvxVR:$Vu32, HvxVR:$Vv32) - 1141
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vmpyubv_acc HvxWR:$Vxx32, HvxVR:$Vu32, HvxVR:$Vv32) - 1144
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vmpyuh HvxWR:$Vdd32, HvxVR:$Vu32, IntRegs:$Rt32) - 1148
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    // (V6_vmpyuh_acc HvxWR:$Vxx32, HvxVR:$Vu32, IntRegs:$Rt32) - 1151
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    // (V6_vmpyuhv HvxWR:$Vdd32, HvxVR:$Vu32, HvxVR:$Vv32) - 1155
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vmpyuhv_acc HvxWR:$Vxx32, HvxVR:$Vu32, HvxVR:$Vv32) - 1158
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vnavgb HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 1162
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vnavgh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 1165
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vnavgub HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 1168
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vnavgw HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 1171
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vnormamth HvxVR:$Vd32, HvxVR:$Vu32) - 1174
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vnormamtw HvxVR:$Vd32, HvxVR:$Vu32) - 1176
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vpackeb HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 1178
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vpackeh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 1181
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vpackhb_sat HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 1184
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vpackhub_sat HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 1187
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vpackob HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 1190
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vpackoh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 1193
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vpackwh_sat HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 1196
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vpackwuh_sat HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 1199
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vpopcounth HvxVR:$Vd32, HvxVR:$Vu32) - 1202
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vrmpybub_rtt HvxWR:$Vdd32, HvxVR:$Vu32, DoubleRegs:$Rtt32) - 1204
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::DoubleRegsRegClassID},
    // (V6_vrmpybub_rtt_acc HvxWR:$Vxx32, HvxVR:$Vu32, DoubleRegs:$Rtt32) - 1207
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::DoubleRegsRegClassID},
    // (V6_vrmpybus HvxVR:$Vd32, HvxVR:$Vu32, IntRegs:$Rt32) - 1211
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    // (V6_vrmpybus_acc HvxVR:$Vx32, HvxVR:$Vu32, IntRegs:$Rt32) - 1214
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    // (V6_vrmpybusi HvxWR:$Vdd32, HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii) - 1218
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    // (V6_vrmpybusi_acc HvxWR:$Vxx32, HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii) - 1221
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    // (V6_vrmpybusv HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 1225
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vrmpybusv_acc HvxVR:$Vx32, HvxVR:$Vu32, HvxVR:$Vv32) - 1228
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vrmpybv HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 1232
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vrmpybv_acc HvxVR:$Vx32, HvxVR:$Vu32, HvxVR:$Vv32) - 1235
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vrmpyub HvxVR:$Vd32, HvxVR:$Vu32, IntRegs:$Rt32) - 1239
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    // (V6_vrmpyub_acc HvxVR:$Vx32, HvxVR:$Vu32, IntRegs:$Rt32) - 1242
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    // (V6_vrmpyub_rtt HvxWR:$Vdd32, HvxVR:$Vu32, DoubleRegs:$Rtt32) - 1246
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::DoubleRegsRegClassID},
    // (V6_vrmpyub_rtt_acc HvxWR:$Vxx32, HvxVR:$Vu32, DoubleRegs:$Rtt32) - 1249
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::DoubleRegsRegClassID},
    // (V6_vrmpyubi HvxWR:$Vdd32, HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii) - 1253
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    // (V6_vrmpyubi_acc HvxWR:$Vxx32, HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii) - 1256
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    // (V6_vrmpyubv HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 1260
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vrmpyubv_acc HvxVR:$Vx32, HvxVR:$Vu32, HvxVR:$Vv32) - 1263
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vrotr HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 1267
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vroundhb HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 1270
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vroundhub HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 1273
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vrounduhub HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 1276
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vrounduwuh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 1279
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vroundwh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 1282
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vroundwuh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 1285
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vrsadubi HvxWR:$Vdd32, HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii) - 1288
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    // (V6_vrsadubi_acc HvxWR:$Vxx32, HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii) - 1291
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    // (V6_vsathub HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 1295
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vsatuwuh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 1298
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vsatwh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 1301
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vsb HvxWR:$Vdd32, HvxVR:$Vu32) - 1304
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vscattermh IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32) - 1306
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::ModRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vscattermh_add IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32) - 1310
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::ModRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vscattermhq HvxQR:$Qs4, IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32) - 1314
    {AliasPatternCond::K_RegClass, Hexagon::HvxQRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::ModRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vscattermhw IntRegs:$Rt32, ModRegs:$Mu2, HvxWR:$Vvv32, HvxVR:$Vw32) - 1319
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::ModRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vscattermhw_add IntRegs:$Rt32, ModRegs:$Mu2, HvxWR:$Vvv32, HvxVR:$Vw32) - 1323
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::ModRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vscattermhwq HvxQR:$Qs4, IntRegs:$Rt32, ModRegs:$Mu2, HvxWR:$Vvv32, HvxVR:$Vw32) - 1327
    {AliasPatternCond::K_RegClass, Hexagon::HvxQRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::ModRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vscattermw IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32) - 1332
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::ModRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vscattermw_add IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32) - 1336
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::ModRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vscattermwq HvxQR:$Qs4, IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32) - 1340
    {AliasPatternCond::K_RegClass, Hexagon::HvxQRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::ModRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vsh HvxWR:$Vdd32, HvxVR:$Vu32) - 1345
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vshufeh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 1347
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vshuff HvxVR:$Vy32, HvxVR:$Vx32, IntRegs:$Rt32) - 1350
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    // (V6_vshuffb HvxVR:$Vd32, HvxVR:$Vu32) - 1355
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vshuffeb HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 1357
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vshuffh HvxVR:$Vd32, HvxVR:$Vu32) - 1360
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vshuffob HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 1362
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vshufoeb HvxWR:$Vdd32, HvxVR:$Vu32, HvxVR:$Vv32) - 1365
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vshufoeh HvxWR:$Vdd32, HvxVR:$Vu32, HvxVR:$Vv32) - 1368
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vshufoh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 1371
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vsubb HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 1374
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vsubb_dv HvxWR:$Vdd32, HvxWR:$Vuu32, HvxWR:$Vvv32) - 1377
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    // (V6_vsubbnq HvxVR:$Vx32, HvxQR:$Qv4, HvxVR:$Vu32) - 1380
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxQRRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vsubbq HvxVR:$Vx32, HvxQR:$Qv4, HvxVR:$Vu32) - 1384
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxQRRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vsubbsat HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 1388
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vsubbsat_dv HvxWR:$Vdd32, HvxWR:$Vuu32, HvxWR:$Vvv32) - 1391
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    // (V6_vsubh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 1394
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vsubh_dv HvxWR:$Vdd32, HvxWR:$Vuu32, HvxWR:$Vvv32) - 1397
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    // (V6_vsubhnq HvxVR:$Vx32, HvxQR:$Qv4, HvxVR:$Vu32) - 1400
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxQRRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vsubhq HvxVR:$Vx32, HvxQR:$Qv4, HvxVR:$Vu32) - 1404
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxQRRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vsubhsat HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 1408
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vsubhsat_dv HvxWR:$Vdd32, HvxWR:$Vuu32, HvxWR:$Vvv32) - 1411
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    // (V6_vsubhw HvxWR:$Vdd32, HvxVR:$Vu32, HvxVR:$Vv32) - 1414
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vsububh HvxWR:$Vdd32, HvxVR:$Vu32, HvxVR:$Vv32) - 1417
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vsububsat HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 1420
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vsububsat_dv HvxWR:$Vdd32, HvxWR:$Vuu32, HvxWR:$Vvv32) - 1423
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    // (V6_vsubuhsat HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 1426
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vsubuhsat_dv HvxWR:$Vdd32, HvxWR:$Vuu32, HvxWR:$Vvv32) - 1429
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    // (V6_vsubuhw HvxWR:$Vdd32, HvxVR:$Vu32, HvxVR:$Vv32) - 1432
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vsubuwsat HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 1435
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vsubuwsat_dv HvxWR:$Vdd32, HvxWR:$Vuu32, HvxWR:$Vvv32) - 1438
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    // (V6_vsubw HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 1441
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vsubw_dv HvxWR:$Vdd32, W15, W15) - 1444
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    {AliasPatternCond::K_Reg, Hexagon::W15},
    {AliasPatternCond::K_Reg, Hexagon::W15},
    // (V6_vsubw_dv HvxWR:$Vdd32, HvxWR:$Vuu32, HvxWR:$Vvv32) - 1447
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    // (V6_vsubwnq HvxVR:$Vx32, HvxQR:$Qv4, HvxVR:$Vu32) - 1450
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxQRRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vsubwq HvxVR:$Vx32, HvxQR:$Qv4, HvxVR:$Vu32) - 1454
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxQRRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vsubwsat HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32) - 1458
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vsubwsat_dv HvxWR:$Vdd32, HvxWR:$Vuu32, HvxWR:$Vvv32) - 1461
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    // (V6_vtmpyb HvxWR:$Vdd32, HvxWR:$Vuu32, IntRegs:$Rt32) - 1464
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    // (V6_vtmpyb_acc HvxWR:$Vxx32, HvxWR:$Vuu32, IntRegs:$Rt32) - 1467
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    // (V6_vtmpybus HvxWR:$Vdd32, HvxWR:$Vuu32, IntRegs:$Rt32) - 1471
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    // (V6_vtmpybus_acc HvxWR:$Vxx32, HvxWR:$Vuu32, IntRegs:$Rt32) - 1474
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    // (V6_vtmpyhb HvxWR:$Vdd32, HvxWR:$Vuu32, IntRegs:$Rt32) - 1478
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    // (V6_vtmpyhb_acc HvxWR:$Vxx32, HvxWR:$Vuu32, IntRegs:$Rt32) - 1481
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    // (V6_vunpackb HvxWR:$Vdd32, HvxVR:$Vu32) - 1485
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vunpackh HvxWR:$Vdd32, HvxVR:$Vu32) - 1487
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vunpackoh HvxWR:$Vxx32, HvxVR:$Vu32) - 1489
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vunpackub HvxWR:$Vdd32, HvxVR:$Vu32) - 1492
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vunpackuh HvxWR:$Vdd32, HvxVR:$Vu32) - 1494
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vxor HvxVR:$Vd32, HvxVR:$Vd32, HvxVR:$Vd32) - 1496
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    {AliasPatternCond::K_TiedReg, 0},
    {AliasPatternCond::K_TiedReg, 0},
    // (V6_vzb HvxWR:$Vdd32, HvxVR:$Vu32) - 1499
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_vzh HvxWR:$Vdd32, HvxVR:$Vu32) - 1501
    {AliasPatternCond::K_RegClass, Hexagon::HvxWRRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::HvxVRRegClassID},
    // (V6_zLd_ai IntRegs:$Rt32, 0) - 1503
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    // (V6_zLd_pred_ai PredRegs:$Pv4, IntRegs:$Rt32, 0) - 1505
    {AliasPatternCond::K_RegClass, Hexagon::PredRegsRegClassID},
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    // (Y2_crswap0 IntRegs:$Rx32) - 1508
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    // (Y2_dcfetchbo IntRegs:$Rs32, 0) - 1509
    {AliasPatternCond::K_RegClass, Hexagon::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
  };

  static const char AsmStrings[] =
    /* 0 */ "$\x01 = zxtb($\x02)\0"
    /* 14 */ "if (!$\x02) $\x01 = $\x03\0"
    /* 31 */ "if (!$\x02.new) $\x01 = $\x03\0"
    /* 52 */ "if ($\x02) $\x01 = $\x03\0"
    /* 68 */ "if ($\x02.new) $\x01 = $\x03\0"
    /* 88 */ "$\x01 = neg($\x03)\0"
    /* 101 */ "$\x01 = not($\x03)\0"
    /* 114 */ "$\x01 = vaddb($\x02,$\x03)\0"
    /* 132 */ "$\x01 = vsubb($\x02,$\x03)\0"
    /* 150 */ "$\x01 = cmp.lt($\x03,$\x02)\0"
    /* 169 */ "$\x01 = cmp.ltu($\x03,$\x02)\0"
    /* 189 */ "$\x01 = $\x02\0"
    /* 197 */ "if (!$\x01) jump $\xFF\x02\x01\0"
    /* 216 */ "if (!$\x01) jumpr $\x02\0"
    /* 234 */ "if ($\x01) jumpr $\x02\0"
    /* 251 */ "if ($\x01) jump $\xFF\x02\x01\0"
    /* 269 */ "trap1(#$\x03)\0"
    /* 280 */ "deallocframe\0"
    /* 293 */ "$\x01 = memb_fifo($\x03)\0"
    /* 312 */ "$\x01 = memh_fifo($\x03)\0"
    /* 331 */ "$\x01 = membh($\x02)\0"
    /* 346 */ "$\x01 = memubh($\x02)\0"
    /* 362 */ "$\x01 = memb($\x02)\0"
    /* 376 */ "$\x01 = memd($\x02)\0"
    /* 390 */ "$\x01 = memh($\x02)\0"
    /* 404 */ "$\x01 = memw($\x02)\0"
    /* 418 */ "$\x01 = memub($\x02)\0"
    /* 433 */ "$\x01 = memuh($\x02)\0"
    /* 448 */ "if (!$\x02) $\x01 = memb($\x03)\0"
    /* 471 */ "if (!$\x02.new) $\x01 = memb($\x03)\0"
    /* 498 */ "if ($\x02) $\x01 = memb($\x03)\0"
    /* 520 */ "if ($\x02.new) $\x01 = memb($\x03)\0"
    /* 546 */ "if (!$\x02) $\x01 = memd($\x03)\0"
    /* 569 */ "if (!$\x02.new) $\x01 = memd($\x03)\0"
    /* 596 */ "if ($\x02) $\x01 = memd($\x03)\0"
    /* 618 */ "if ($\x02.new) $\x01 = memd($\x03)\0"
    /* 644 */ "if (!$\x02) $\x01 = memh($\x03)\0"
    /* 667 */ "if (!$\x02.new) $\x01 = memh($\x03)\0"
    /* 694 */ "if ($\x02) $\x01 = memh($\x03)\0"
    /* 716 */ "if ($\x02.new) $\x01 = memh($\x03)\0"
    /* 742 */ "if (!$\x02) $\x01 = memw($\x03)\0"
    /* 765 */ "if (!$\x02.new) $\x01 = memw($\x03)\0"
    /* 792 */ "if ($\x02) $\x01 = memw($\x03)\0"
    /* 814 */ "if ($\x02.new) $\x01 = memw($\x03)\0"
    /* 840 */ "if (!$\x02) $\x01 = memub($\x03)\0"
    /* 864 */ "if (!$\x02.new) $\x01 = memub($\x03)\0"
    /* 892 */ "if ($\x02) $\x01 = memub($\x03)\0"
    /* 915 */ "if ($\x02.new) $\x01 = memub($\x03)\0"
    /* 942 */ "if (!$\x02) $\x01 = memuh($\x03)\0"
    /* 966 */ "if (!$\x02.new) $\x01 = memuh($\x03)\0"
    /* 994 */ "if ($\x02) $\x01 = memuh($\x03)\0"
    /* 1017 */ "if ($\x02.new) $\x01 = memuh($\x03)\0"
    /* 1044 */ "memb($\x01) += $\x03\0"
    /* 1059 */ "memh($\x01) += $\x03\0"
    /* 1074 */ "memw($\x01) += $\x03\0"
    /* 1089 */ "memb($\x01) &= $\x03\0"
    /* 1104 */ "memh($\x01) &= $\x03\0"
    /* 1119 */ "memw($\x01) &= $\x03\0"
    /* 1134 */ "memb($\x01) += #$\x03\0"
    /* 1150 */ "memh($\x01) += #$\x03\0"
    /* 1166 */ "memw($\x01) += #$\x03\0"
    /* 1182 */ "memb($\x01) = clrbit(#$\x03)\0"
    /* 1205 */ "memh($\x01) = clrbit(#$\x03)\0"
    /* 1228 */ "memw($\x01) = clrbit(#$\x03)\0"
    /* 1251 */ "memb($\x01) = setbit(#$\x03)\0"
    /* 1274 */ "memh($\x01) = setbit(#$\x03)\0"
    /* 1297 */ "memw($\x01) = setbit(#$\x03)\0"
    /* 1320 */ "memb($\x01) -= #$\x03\0"
    /* 1336 */ "memh($\x01) -= #$\x03\0"
    /* 1352 */ "memw($\x01) -= #$\x03\0"
    /* 1368 */ "memb($\x01) |= $\x03\0"
    /* 1383 */ "memh($\x01) |= $\x03\0"
    /* 1398 */ "memw($\x01) |= $\x03\0"
    /* 1413 */ "dealloc_return\0"
    /* 1428 */ "if (!$\x02) dealloc_return\0"
    /* 1452 */ "if (!$\x02.new) dealloc_return:nt\0"
    /* 1483 */ "if (!$\x02.new) dealloc_return:t\0"
    /* 1513 */ "if ($\x02) dealloc_return\0"
    /* 1536 */ "if ($\x02.new) dealloc_return:nt\0"
    /* 1566 */ "if ($\x02.new) dealloc_return:t\0"
    /* 1595 */ "memb($\x01) -= $\x03\0"
    /* 1610 */ "memh($\x01) -= $\x03\0"
    /* 1625 */ "memw($\x01) -= $\x03\0"
    /* 1640 */ "$\x01 = mpyui($\x02,$\x03)\0"
    /* 1658 */ "$\x01 = vdmpyw($\x02,$\x03)\0"
    /* 1677 */ "$\x01 += vdmpyw($\x03,$\x04)\0"
    /* 1697 */ "allocframe(#$\x03)\0"
    /* 1713 */ "if (!$\x01) memb($\x02) = $\x04\0"
    /* 1736 */ "if (!$\x01) memb($\x02) = $\x04.new\0"
    /* 1763 */ "if ($\x01) memb($\x02) = $\x04.new\0"
    /* 1789 */ "if ($\x01) memb($\x02) = $\x04\0"
    /* 1811 */ "if (!$\x01) memd($\x02) = $\x04\0"
    /* 1834 */ "if ($\x01) memd($\x02) = $\x04\0"
    /* 1856 */ "if (!$\x01) memh($\x02) = $\x04.h\0"
    /* 1881 */ "if ($\x01) memh($\x02) = $\x04.h\0"
    /* 1905 */ "if (!$\x01) memh($\x02) = $\x04\0"
    /* 1928 */ "if (!$\x01) memh($\x02) = $\x04.new\0"
    /* 1955 */ "if ($\x01) memh($\x02) = $\x04.new\0"
    /* 1981 */ "if ($\x01) memh($\x02) = $\x04\0"
    /* 2003 */ "if (!$\x01) memw($\x02) = $\x04\0"
    /* 2026 */ "if (!$\x01) memw($\x02) = $\x04.new\0"
    /* 2053 */ "if ($\x01) memw($\x02) = $\x04.new\0"
    /* 2079 */ "if ($\x01) memw($\x02) = $\x04\0"
    /* 2101 */ "memb($\x01) = $\x03\0"
    /* 2115 */ "memb($\x01) = $\x03.new\0"
    /* 2133 */ "memd($\x01) = $\x03\0"
    /* 2147 */ "memh($\x01) = $\x03.h\0"
    /* 2163 */ "memh($\x01) = $\x03\0"
    /* 2177 */ "memh($\x01) = $\x03.new\0"
    /* 2195 */ "memw($\x01) = $\x03\0"
    /* 2209 */ "memw($\x01) = $\x03.new\0"
    /* 2227 */ "$\x01 = tableidxb($\x03,#$\x04,#$\x05)\0"
    /* 2254 */ "if (!$\x01.new) memb($\x02) = $\x04\0"
    /* 2281 */ "if (!$\x01.new) memb($\x02) = $\x04.new\0"
    /* 2312 */ "if ($\x01.new) memb($\x02) = $\x04.new\0"
    /* 2342 */ "if ($\x01.new) memb($\x02) = $\x04\0"
    /* 2368 */ "if (!$\x01.new) memd($\x02) = $\x04\0"
    /* 2395 */ "if ($\x01.new) memd($\x02) = $\x04\0"
    /* 2421 */ "if (!$\x01.new) memh($\x02) = $\x04.h\0"
    /* 2450 */ "if ($\x01.new) memh($\x02) = $\x04.h\0"
    /* 2478 */ "if (!$\x01.new) memh($\x02) = $\x04\0"
    /* 2505 */ "if (!$\x01.new) memh($\x02) = $\x04.new\0"
    /* 2536 */ "if ($\x01.new) memh($\x02) = $\x04.new\0"
    /* 2566 */ "if ($\x01.new) memh($\x02) = $\x04\0"
    /* 2592 */ "if (!$\x01.new) memw($\x02) = $\x04\0"
    /* 2619 */ "if (!$\x01.new) memw($\x02) = $\x04.new\0"
    /* 2650 */ "if ($\x01.new) memw($\x02) = $\x04.new\0"
    /* 2680 */ "if ($\x01.new) memw($\x02) = $\x04\0"
    /* 2706 */ "memb($\x01) = #$\x03\0"
    /* 2721 */ "if (!$\x01) memb($\x02) = #$\x04\0"
    /* 2745 */ "if (!$\x01.new) memb($\x02) = #$\x04\0"
    /* 2773 */ "if ($\x01) memb($\x02) = #$\x04\0"
    /* 2796 */ "if ($\x01.new) memb($\x02) = #$\x04\0"
    /* 2823 */ "memh($\x01) = #$\x03\0"
    /* 2838 */ "if (!$\x01) memh($\x02) = #$\x04\0"
    /* 2862 */ "if (!$\x01.new) memh($\x02) = #$\x04\0"
    /* 2890 */ "if ($\x01) memh($\x02) = #$\x04\0"
    /* 2913 */ "if ($\x01.new) memh($\x02) = #$\x04\0"
    /* 2940 */ "memw($\x01) = #$\x03\0"
    /* 2955 */ "if (!$\x01) memw($\x02) = #$\x04\0"
    /* 2979 */ "if (!$\x01.new) memw($\x02) = #$\x04\0"
    /* 3007 */ "if ($\x01) memw($\x02) = #$\x04\0"
    /* 3030 */ "if ($\x01.new) memw($\x02) = #$\x04\0"
    /* 3057 */ "$\x01.w = vextract($\x02,$\x03)\0"
    /* 3080 */ "$\x01.w = v6mpy($\x02.ub,$\x03.b10,#$\x04):h\0"
    /* 3113 */ "$\x01.w = v6mpy($\x02.ub,$\x03.b10,#$\x04):v\0"
    /* 3146 */ "$\x01 = vmemu($\x02)\0"
    /* 3161 */ "$\x01 = vmem($\x02)\0"
    /* 3175 */ "if (!$\x03) $\x01.cur = vmem($\x02)\0"
    /* 3202 */ "if ($\x03) $\x01.cur = vmem($\x02)\0"
    /* 3228 */ "if (!$\x02) $\x01.tmp = vmem($\x03)\0"
    /* 3255 */ "if (!$\x03) $\x01 = vmem($\x02)\0"
    /* 3278 */ "$\x01 = vmem($\x02):nt\0"
    /* 3295 */ "if (!$\x03) $\x01.cur = vmem($\x02):nt\0"
    /* 3325 */ "if ($\x03) $\x01.cur = vmem($\x02):nt\0"
    /* 3354 */ "if (!$\x02) $\x01.tmp = vmem($\x03):nt\0"
    /* 3384 */ "if (!$\x03) $\x01 = vmem($\x02):nt\0"
    /* 3410 */ "if ($\x02) $\x01 = vmem($\x03):nt\0"
    /* 3435 */ "if ($\x02) $\x01.tmp = vmem($\x03):nt\0"
    /* 3464 */ "if ($\x02) $\x01 = vmem($\x03)\0"
    /* 3486 */ "if ($\x02) $\x01.tmp = vmem($\x03)\0"
    /* 3512 */ "vmemu($\x01) = $\x03\0"
    /* 3527 */ "if (!$\x01) vmemu($\x02) = $\x04\0"
    /* 3551 */ "if ($\x01) vmemu($\x02) = $\x04\0"
    /* 3574 */ "vmem($\x01) = $\x03\0"
    /* 3588 */ "vmem($\x01) = $\x03.new\0"
    /* 3606 */ "if (!$\x01) vmem($\x02) = $\x04\0"
    /* 3629 */ "vmem($\x01):nt = $\x03\0"
    /* 3646 */ "vmem($\x01):nt = $\x03.new\0"
    /* 3667 */ "if (!$\x01) vmem($\x02):nt = $\x04\0"
    /* 3693 */ "if ($\x01) vmem($\x02):nt = $\x04\0"
    /* 3718 */ "if ($\x01) vmem($\x02) = $\x04\0"
    /* 3740 */ "$\x01 = vabsb($\x02):sat\0"
    /* 3759 */ "$\x01 = vabsdiffh($\x02,$\x03)\0"
    /* 3781 */ "$\x01 = vabsdiffub($\x02,$\x03)\0"
    /* 3804 */ "$\x01 = vabsdiffuh($\x02,$\x03)\0"
    /* 3827 */ "$\x01 = vabsdiffw($\x02,$\x03)\0"
    /* 3849 */ "$\x01 = vabsh($\x02):sat\0"
    /* 3868 */ "$\x01 = vabsw($\x02):sat\0"
    /* 3887 */ "if (!$\x02.b) $\x01.b += $\x04.b\0"
    /* 3911 */ "if ($\x02.b) $\x01.b += $\x04.b\0"
    /* 3934 */ "$\x01 = vaddb($\x02,$\x03):sat\0"
    /* 3956 */ "$\x01 = vaddh($\x02,$\x03)\0"
    /* 3974 */ "if (!$\x02.h) $\x01.h += $\x04.h\0"
    /* 3998 */ "if ($\x02.h) $\x01.h += $\x04.h\0"
    /* 4021 */ "$\x01 = vaddh($\x02,$\x03):sat\0"
    /* 4043 */ "$\x01 += vaddh($\x03,$\x04)\0"
    /* 4062 */ "$\x01 = vaddub($\x02,$\x03)\0"
    /* 4081 */ "$\x01 += vaddub($\x03,$\x04)\0"
    /* 4101 */ "$\x01 = vaddub($\x02,$\x03):sat\0"
    /* 4124 */ "$\x01 = vadduh($\x02,$\x03):sat\0"
    /* 4147 */ "$\x01 = vadduh($\x02,$\x03)\0"
    /* 4166 */ "$\x01 += vadduh($\x03,$\x04)\0"
    /* 4186 */ "$\x01 = vadduw($\x02,$\x03):sat\0"
    /* 4209 */ "$\x01 = vaddw($\x02,$\x03)\0"
    /* 4227 */ "if (!$\x02.w) $\x01.w += $\x04.w\0"
    /* 4251 */ "if ($\x02.w) $\x01.w += $\x04.w\0"
    /* 4274 */ "$\x01 = vaddw($\x02,$\x03):sat\0"
    /* 4296 */ "$\x01.ub = vand(!$\x02.ub,$\x03.ub)\0"
    /* 4323 */ "$\x01.ub |= vand(!$\x03.ub,$\x04.ub)\0"
    /* 4351 */ "$\x01.ub = vand($\x02.ub,$\x03.ub)\0"
    /* 4377 */ "$\x01.ub |= vand($\x03.ub,$\x04.ub)\0"
    /* 4404 */ "$\x01 = vaslh($\x02,$\x03)\0"
    /* 4422 */ "$\x01 += vaslh($\x03,$\x04)\0"
    /* 4441 */ "$\x01 = vaslw($\x02,$\x03)\0"
    /* 4459 */ "$\x01 += vaslw($\x03,$\x04)\0"
    /* 4478 */ "$\x01 = vasrinto($\x03,$\x04)\0"
    /* 4499 */ "$\x01 = vasrh($\x02,$\x03)\0"
    /* 4517 */ "$\x01 += vasrh($\x03,$\x04)\0"
    /* 4536 */ "$\x01 = vasrw($\x02,$\x03)\0"
    /* 4554 */ "$\x01 += vasrw($\x03,$\x04)\0"
    /* 4573 */ "$\x01 = vavgb($\x02,$\x03)\0"
    /* 4591 */ "$\x01 = vavgb($\x02,$\x03):rnd\0"
    /* 4613 */ "$\x01 = vavgh($\x02,$\x03)\0"
    /* 4631 */ "$\x01 = vavgh($\x02,$\x03):rnd\0"
    /* 4653 */ "$\x01 = vavgub($\x02,$\x03)\0"
    /* 4672 */ "$\x01 = vavgub($\x02,$\x03):rnd\0"
    /* 4695 */ "$\x01 = vavguh($\x02,$\x03)\0"
    /* 4714 */ "$\x01 = vavguh($\x02,$\x03):rnd\0"
    /* 4737 */ "$\x01 = vavguw($\x02,$\x03)\0"
    /* 4756 */ "$\x01 = vavguw($\x02,$\x03):rnd\0"
    /* 4779 */ "$\x01 = vavgw($\x02,$\x03)\0"
    /* 4797 */ "$\x01 = vavgw($\x02,$\x03):rnd\0"
    /* 4819 */ "$\x01 = vcl0h($\x02)\0"
    /* 4834 */ "$\x01 = vcl0w($\x02)\0"
    /* 4849 */ "$\x01 = vdealb($\x02)\0"
    /* 4865 */ "$\x01 = vdealb4w($\x02,$\x03)\0"
    /* 4886 */ "$\x01 = vdealh($\x02)\0"
    /* 4902 */ "$\x01 = vdmpybus($\x02,$\x03)\0"
    /* 4923 */ "$\x01 += vdmpybus($\x03,$\x04)\0"
    /* 4945 */ "$\x01 = vdmpyhb($\x02,$\x03)\0"
    /* 4965 */ "$\x01 += vdmpyhb($\x03,$\x04)\0"
    /* 4986 */ "$\x01 = vdmpyh($\x02,$\x03):sat\0"
    /* 5009 */ "$\x01 += vdmpyh($\x03,$\x04):sat\0"
    /* 5033 */ "$\x01 = vdmpyhsu($\x02,$\x03,#1):sat\0"
    /* 5061 */ "$\x01 += vdmpyhsu($\x03,$\x04,#1):sat\0"
    /* 5090 */ "$\x01 = vdmpyhsu($\x02,$\x03):sat\0"
    /* 5115 */ "$\x01 += vdmpyhsu($\x03,$\x04):sat\0"
    /* 5141 */ "$\x01 = vdsaduh($\x02,$\x03)\0"
    /* 5161 */ "$\x01 += vdsaduh($\x03,$\x04)\0"
    /* 5182 */ "$\x01 = vcmp.eq($\x02.ub,$\x03.ub)\0"
    /* 5208 */ "$\x01 &= vcmp.eq($\x03.ub,$\x04.ub)\0"
    /* 5235 */ "$\x01 |= vcmp.eq($\x03.ub,$\x04.ub)\0"
    /* 5262 */ "$\x01 ^= vcmp.eq($\x03.ub,$\x04.ub)\0"
    /* 5289 */ "$\x01 = vcmp.eq($\x02.uh,$\x03.uh)\0"
    /* 5315 */ "$\x01 &= vcmp.eq($\x03.uh,$\x04.uh)\0"
    /* 5342 */ "$\x01 |= vcmp.eq($\x03.uh,$\x04.uh)\0"
    /* 5369 */ "$\x01 ^= vcmp.eq($\x03.uh,$\x04.uh)\0"
    /* 5396 */ "$\x01 = vcmp.eq($\x02.uw,$\x03.uw)\0"
    /* 5422 */ "$\x01 &= vcmp.eq($\x03.uw,$\x04.uw)\0"
    /* 5449 */ "$\x01 |= vcmp.eq($\x03.uw,$\x04.uw)\0"
    /* 5476 */ "$\x01 ^= vcmp.eq($\x03.uw,$\x04.uw)\0"
    /* 5503 */ "$\x01 = vlsrh($\x02,$\x03)\0"
    /* 5521 */ "$\x01 = vlsrw($\x02,$\x03)\0"
    /* 5539 */ "$\x01 = vmaxb($\x02,$\x03)\0"
    /* 5557 */ "$\x01 = vmaxh($\x02,$\x03)\0"
    /* 5575 */ "$\x01 = vmaxub($\x02,$\x03)\0"
    /* 5594 */ "$\x01 = vmaxuh($\x02,$\x03)\0"
    /* 5613 */ "$\x01 = vmaxw($\x02,$\x03)\0"
    /* 5631 */ "$\x01 = vminb($\x02,$\x03)\0"
    /* 5649 */ "$\x01 = vminh($\x02,$\x03)\0"
    /* 5667 */ "$\x01 = vminub($\x02,$\x03)\0"
    /* 5686 */ "$\x01 = vminuh($\x02,$\x03)\0"
    /* 5705 */ "$\x01 = vminw($\x02,$\x03)\0"
    /* 5723 */ "$\x01 = vmpabus($\x02,$\x03)\0"
    /* 5743 */ "$\x01 += vmpabus($\x03,$\x04)\0"
    /* 5764 */ "$\x01 = vmpabuu($\x02,$\x03)\0"
    /* 5784 */ "$\x01 += vmpabuu($\x03,$\x04)\0"
    /* 5805 */ "$\x01 = vmpahb($\x02,$\x03)\0"
    /* 5824 */ "$\x01 += vmpahb($\x03,$\x04)\0"
    /* 5844 */ "$\x01 = vmpauhb($\x02,$\x03)\0"
    /* 5864 */ "$\x01 += vmpauhb($\x03,$\x04)\0"
    /* 5885 */ "$\x01 = vmpybus($\x02,$\x03)\0"
    /* 5905 */ "$\x01 += vmpybus($\x03,$\x04)\0"
    /* 5926 */ "$\x01 = vmpyb($\x02,$\x03)\0"
    /* 5944 */ "$\x01 += vmpyb($\x03,$\x04)\0"
    /* 5963 */ "$\x01 = vmpyewuh($\x02,$\x03)\0"
    /* 5984 */ "$\x01 = vmpyh($\x02,$\x03)\0"
    /* 6002 */ "$\x01 += vmpyh($\x03,$\x04)\0"
    /* 6021 */ "$\x01 += vmpyh($\x03,$\x04):sat\0"
    /* 6044 */ "$\x01 = vmpyh($\x02,$\x03):<<1:rnd:sat\0"
    /* 6074 */ "$\x01 = vmpyh($\x02,$\x03):<<1:sat\0"
    /* 6100 */ "$\x01 = vmpyhus($\x02,$\x03)\0"
    /* 6120 */ "$\x01 += vmpyhus($\x03,$\x04)\0"
    /* 6141 */ "$\x01 += vmpyiewh($\x03,$\x04)\0"
    /* 6163 */ "$\x01 = vmpyiewuh($\x02,$\x03)\0"
    /* 6185 */ "$\x01 += vmpyiewuh($\x03,$\x04)\0"
    /* 6208 */ "$\x01 = vmpyih($\x02,$\x03)\0"
    /* 6227 */ "$\x01 += vmpyih($\x03,$\x04)\0"
    /* 6247 */ "$\x01 = vmpyihb($\x02,$\x03)\0"
    /* 6267 */ "$\x01 += vmpyihb($\x03,$\x04)\0"
    /* 6288 */ "$\x01 = vmpyiowh($\x02,$\x03)\0"
    /* 6309 */ "$\x01 = vmpyiwb($\x02,$\x03)\0"
    /* 6329 */ "$\x01 += vmpyiwb($\x03,$\x04)\0"
    /* 6350 */ "$\x01 = vmpyiwh($\x02,$\x03)\0"
    /* 6370 */ "$\x01 += vmpyiwh($\x03,$\x04)\0"
    /* 6391 */ "$\x01 = vmpyiwub($\x02,$\x03)\0"
    /* 6412 */ "$\x01 += vmpyiwub($\x03,$\x04)\0"
    /* 6434 */ "$\x01 = vmpyowh($\x02,$\x03):<<1:sat\0"
    /* 6462 */ "$\x01 = vmpyowh($\x02,$\x03):<<1:rnd:sat\0"
    /* 6494 */ "$\x01 = vmpyub($\x02,$\x03)\0"
    /* 6513 */ "$\x01 += vmpyub($\x03,$\x04)\0"
    /* 6533 */ "$\x01 = vmpyuh($\x02,$\x03)\0"
    /* 6552 */ "$\x01 += vmpyuh($\x03,$\x04)\0"
    /* 6572 */ "$\x01 = vnavgb($\x02,$\x03)\0"
    /* 6591 */ "$\x01 = vnavgh($\x02,$\x03)\0"
    /* 6610 */ "$\x01 = vnavgub($\x02,$\x03)\0"
    /* 6630 */ "$\x01 = vnavgw($\x02,$\x03)\0"
    /* 6649 */ "$\x01 = vnormamth($\x02)\0"
    /* 6668 */ "$\x01 = vnormamtw($\x02)\0"
    /* 6687 */ "$\x01 = vpackeb($\x02,$\x03)\0"
    /* 6707 */ "$\x01 = vpackeh($\x02,$\x03)\0"
    /* 6727 */ "$\x01 = vpackhb($\x02,$\x03):sat\0"
    /* 6751 */ "$\x01 = vpackhub($\x02,$\x03):sat\0"
    /* 6776 */ "$\x01 = vpackob($\x02,$\x03)\0"
    /* 6796 */ "$\x01 = vpackoh($\x02,$\x03)\0"
    /* 6816 */ "$\x01 = vpackwh($\x02,$\x03):sat\0"
    /* 6840 */ "$\x01 = vpackwuh($\x02,$\x03):sat\0"
    /* 6865 */ "$\x01 = vpopcounth($\x02)\0"
    /* 6885 */ "$\x01.w = vrmpy($\x02.b,$\x03.ub)\0"
    /* 6910 */ "$\x01.w += vrmpy($\x03.b,$\x04.ub)\0"
    /* 6936 */ "$\x01 = vrmpybus($\x02,$\x03)\0"
    /* 6957 */ "$\x01 += vrmpybus($\x03,$\x04)\0"
    /* 6979 */ "$\x01 = vrmpybus($\x02,$\x03,#$\x04)\0"
    /* 7004 */ "$\x01 += vrmpybus($\x03,$\x04,#$\x05)\0"
    /* 7030 */ "$\x01 = vrmpyb($\x02,$\x03)\0"
    /* 7049 */ "$\x01 += vrmpyb($\x03,$\x04)\0"
    /* 7069 */ "$\x01 = vrmpyub($\x02,$\x03)\0"
    /* 7089 */ "$\x01 += vrmpyub($\x03,$\x04)\0"
    /* 7110 */ "$\x01.uw = vrmpy($\x02.ub,$\x03.ub)\0"
    /* 7137 */ "$\x01.uw += vrmpy($\x03.ub,$\x04.ub)\0"
    /* 7165 */ "$\x01 = vrmpyub($\x02,$\x03,#$\x04)\0"
    /* 7189 */ "$\x01 += vrmpyub($\x03,$\x04,#$\x05)\0"
    /* 7214 */ "$\x01 = vrotr($\x02,$\x03)\0"
    /* 7232 */ "$\x01 = vroundhb($\x02,$\x03):sat\0"
    /* 7257 */ "$\x01 = vroundhub($\x02,$\x03):sat\0"
    /* 7283 */ "$\x01 = vrounduhub($\x02,$\x03):sat\0"
    /* 7310 */ "$\x01 = vrounduwuh($\x02,$\x03):sat\0"
    /* 7337 */ "$\x01 = vroundwh($\x02,$\x03):sat\0"
    /* 7362 */ "$\x01 = vroundwuh($\x02,$\x03):sat\0"
    /* 7388 */ "$\x01 = vrsadub($\x02,$\x03,#$\x04)\0"
    /* 7412 */ "$\x01 += vrsadub($\x03,$\x04,#$\x05)\0"
    /* 7437 */ "$\x01 = vsathub($\x02,$\x03)\0"
    /* 7457 */ "$\x01 = vsatuwuh($\x02,$\x03)\0"
    /* 7478 */ "$\x01 = vsatwh($\x02,$\x03)\0"
    /* 7497 */ "$\x01 = vsxtb($\x02)\0"
    /* 7512 */ "vscatter($\x01,$\x02,$\x03.h) = $\x04.h\0"
    /* 7540 */ "vscatter($\x01,$\x02,$\x03.h) += $\x04.h\0"
    /* 7569 */ "if ($\x01) vscatter($\x02,$\x03,$\x04.h) = $\x05.h\0"
    /* 7605 */ "vscatter($\x01,$\x02,$\x03.w) = $\x04.h\0"
    /* 7633 */ "vscatter($\x01,$\x02,$\x03.w) += $\x04.h\0"
    /* 7662 */ "if ($\x01) vscatter($\x02,$\x03,$\x04.w) = $\x05.h\0"
    /* 7698 */ "vscatter($\x01,$\x02,$\x03.w) = $\x04.w\0"
    /* 7726 */ "vscatter($\x01,$\x02,$\x03.w) += $\x04.w\0"
    /* 7755 */ "if ($\x01) vscatter($\x02,$\x03,$\x04.w) = $\x05.w\0"
    /* 7791 */ "$\x01 = vsxth($\x02)\0"
    /* 7806 */ "$\x01 = vshuffeh($\x02,$\x03)\0"
    /* 7827 */ "vtrans2x2($\x01,$\x02,$\x05)\0"
    /* 7847 */ "$\x01 = vshuffb($\x02)\0"
    /* 7864 */ "$\x01 = vshuffeb($\x02,$\x03)\0"
    /* 7885 */ "$\x01 = vshuffh($\x02)\0"
    /* 7902 */ "$\x01 = vshuffob($\x02,$\x03)\0"
    /* 7923 */ "$\x01 = vshuffoeb($\x02,$\x03)\0"
    /* 7945 */ "$\x01 = vshuffoeh($\x02,$\x03)\0"
    /* 7967 */ "$\x01 = vshuffoh($\x02,$\x03)\0"
    /* 7988 */ "if (!$\x02.b) $\x01.b -= $\x04.b\0"
    /* 8012 */ "if ($\x02.b) $\x01.b -= $\x04.b\0"
    /* 8035 */ "$\x01 = vsubb($\x02,$\x03):sat\0"
    /* 8057 */ "$\x01 = vsubh($\x02,$\x03)\0"
    /* 8075 */ "if (!$\x02.h) $\x01.h -= $\x04.h\0"
    /* 8099 */ "if ($\x02.h) $\x01.h -= $\x04.h\0"
    /* 8122 */ "$\x01 = vsubh($\x02,$\x03):sat\0"
    /* 8144 */ "$\x01 = vsubub($\x02,$\x03)\0"
    /* 8163 */ "$\x01 = vsubub($\x02,$\x03):sat\0"
    /* 8186 */ "$\x01 = vsubuh($\x02,$\x03):sat\0"
    /* 8209 */ "$\x01 = vsubuh($\x02,$\x03)\0"
    /* 8228 */ "$\x01 = vsubuw($\x02,$\x03):sat\0"
    /* 8251 */ "$\x01 = vsubw($\x02,$\x03)\0"
    /* 8269 */ "$\x01 = #0\0"
    /* 8277 */ "if (!$\x02.w) $\x01.w -= $\x04.w\0"
    /* 8301 */ "if ($\x02.w) $\x01.w -= $\x04.w\0"
    /* 8324 */ "$\x01 = vsubw($\x02,$\x03):sat\0"
    /* 8346 */ "$\x01 = vtmpyb($\x02,$\x03)\0"
    /* 8365 */ "$\x01 += vtmpyb($\x03,$\x04)\0"
    /* 8385 */ "$\x01 = vtmpybus($\x02,$\x03)\0"
    /* 8406 */ "$\x01 += vtmpybus($\x03,$\x04)\0"
    /* 8428 */ "$\x01 = vtmpyhb($\x02,$\x03)\0"
    /* 8448 */ "$\x01 += vtmpyhb($\x03,$\x04)\0"
    /* 8469 */ "$\x01 = vunpackb($\x02)\0"
    /* 8487 */ "$\x01 = vunpackh($\x02)\0"
    /* 8505 */ "$\x01 |= vunpackoh($\x03)\0"
    /* 8525 */ "$\x01 = vunpackub($\x02)\0"
    /* 8544 */ "$\x01 = vunpackuh($\x02)\0"
    /* 8563 */ "$\x01 = vzxtb($\x02)\0"
    /* 8578 */ "$\x01 = vzxth($\x02)\0"
    /* 8593 */ "z = vmem($\x01)\0"
    /* 8606 */ "if ($\x01) z = vmem($\x02)\0"
    /* 8627 */ "crswap($\x01,sgp)\0"
    /* 8642 */ "dcfetch($\x01)\0"
  ;

#ifndef NDEBUG
  static struct SortCheck {
    SortCheck(ArrayRef<PatternsForOpcode> OpToPatterns) {
      assert(std::is_sorted(
                 OpToPatterns.begin(), OpToPatterns.end(),
                 [](const PatternsForOpcode &L, const PatternsForOpcode &R) {
                   return L.Opcode < R.Opcode;
                 }) &&
             "tablegen failed to sort opcode patterns");
    }
  } sortCheckVar(OpToPatterns);
#endif

  AliasMatchingData M {
    ArrayRef(OpToPatterns),
    ArrayRef(Patterns),
    ArrayRef(Conds),
    StringRef(AsmStrings, std::size(AsmStrings)),
    nullptr,
  };
  const char *AsmString = matchAliasPatterns(MI, nullptr, M);
  if (!AsmString) return false;

  unsigned I = 0;
  while (AsmString[I] != ' ' && AsmString[I] != '\t' &&
         AsmString[I] != '$' && AsmString[I] != '\0')
    ++I;
  OS << '\t' << StringRef(AsmString, I);
  if (AsmString[I] != '\0') {
    if (AsmString[I] == ' ' || AsmString[I] == '\t') {
      OS << '\t';
      ++I;
    }
    do {
      if (AsmString[I] == '$') {
        ++I;
        if (AsmString[I] == (char)0xff) {
          ++I;
          int OpIdx = AsmString[I++] - 1;
          int PrintMethodIdx = AsmString[I++] - 1;
          printCustomAliasOperand(MI, Address, OpIdx, PrintMethodIdx, OS);
        } else
          printOperand(MI, unsigned(AsmString[I++]) - 1, OS);
      } else {
        OS << AsmString[I++];
      }
    } while (AsmString[I] != '\0');
  }

  return true;
}

void HexagonInstPrinter::printCustomAliasOperand(
         const MCInst *MI, uint64_t Address, unsigned OpIdx,
         unsigned PrintMethodIdx,
         raw_ostream &OS) {
  switch (PrintMethodIdx) {
  default:
    llvm_unreachable("Unknown PrintMethod kind");
    break;
  case 0:
    printBrtarget(MI, OpIdx, OS);
    break;
  }
}

#endif // PRINT_ALIAS_INSTR