llvm/lib/Target/Hexagon/HexagonGenMCCodeEmitter.inc

/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
|*                                                                            *|
|* Machine Code Emitter                                                       *|
|*                                                                            *|
|* Automatically generated file, do not edit!                                 *|
|*                                                                            *|
\*===----------------------------------------------------------------------===*/

uint64_t HexagonMCCodeEmitter::getBinaryCodeForInstr(const MCInst &MI,
    SmallVectorImpl<MCFixup> &Fixups,
    const MCSubtargetInfo &STI) const { … }

#ifdef GET_OPERAND_BIT_OFFSET
#undef GET_OPERAND_BIT_OFFSET

uint32_t HexagonMCCodeEmitter::getOperandBitOffset(const MCInst &MI,
    unsigned OpNum,
    const MCSubtargetInfo &STI) const {
  switch (MI.getOpcode()) {
    case Hexagon::A2_nop:
    case Hexagon::CONST32:
    case Hexagon::CONST64:
    case Hexagon::DuplexIClass0:
    case Hexagon::DuplexIClass1:
    case Hexagon::DuplexIClass2:
    case Hexagon::DuplexIClass3:
    case Hexagon::DuplexIClass4:
    case Hexagon::DuplexIClass5:
    case Hexagon::DuplexIClass6:
    case Hexagon::DuplexIClass7:
    case Hexagon::DuplexIClass8:
    case Hexagon::DuplexIClass9:
    case Hexagon::DuplexIClassA:
    case Hexagon::DuplexIClassB:
    case Hexagon::DuplexIClassC:
    case Hexagon::DuplexIClassD:
    case Hexagon::DuplexIClassE:
    case Hexagon::DuplexIClassF:
    case Hexagon::J2_rte:
    case Hexagon::J2_unpause:
    case Hexagon::SL2_deallocframe:
    case Hexagon::SL2_jumpr31:
    case Hexagon::SL2_jumpr31_f:
    case Hexagon::SL2_jumpr31_fnew:
    case Hexagon::SL2_jumpr31_t:
    case Hexagon::SL2_jumpr31_tnew:
    case Hexagon::SL2_return:
    case Hexagon::SL2_return_f:
    case Hexagon::SL2_return_fnew:
    case Hexagon::SL2_return_t:
    case Hexagon::SL2_return_tnew:
    case Hexagon::TFRI64_V2_ext:
    case Hexagon::TFRI64_V4:
    case Hexagon::V6_vhist:
    case Hexagon::V6_vwhist128:
    case Hexagon::V6_vwhist256:
    case Hexagon::V6_vwhist256_sat:
    case Hexagon::Y2_barrier:
    case Hexagon::Y2_break:
    case Hexagon::Y2_dckill:
    case Hexagon::Y2_ickill:
    case Hexagon::Y2_isync:
    case Hexagon::Y2_k0lock:
    case Hexagon::Y2_k0unlock:
    case Hexagon::Y2_l2kill:
    case Hexagon::Y2_syncht:
    case Hexagon::Y2_tlblock:
    case Hexagon::Y2_tlbunlock:
    case Hexagon::Y5_l2gclean:
    case Hexagon::Y5_l2gcleaninv:
    case Hexagon::Y5_l2gunlock:
    case Hexagon::invalid_decode: {
      break;
    }
    case Hexagon::PS_storerbnewabs:
    case Hexagon::PS_storerhnewabs:
    case Hexagon::PS_storerinewabs:
    case Hexagon::S2_storerbnewgp:
    case Hexagon::S2_storerhnewgp:
    case Hexagon::S2_storerinewgp: {
      switch (OpNum) {
      case 0:
        // op: Ii
        return 0;
      case 1:
        // op: Nt8
        return 8;
      }
      break;
    }
    case Hexagon::PS_storerbabs:
    case Hexagon::PS_storerfabs:
    case Hexagon::PS_storerhabs:
    case Hexagon::PS_storeriabs:
    case Hexagon::S2_storerbgp:
    case Hexagon::S2_storerfgp:
    case Hexagon::S2_storerhgp:
    case Hexagon::S2_storerigp: {
      switch (OpNum) {
      case 0:
        // op: Ii
        return 0;
      case 1:
        // op: Rt32
        return 8;
      }
      break;
    }
    case Hexagon::PS_storerdabs:
    case Hexagon::S2_storerdgp: {
      switch (OpNum) {
      case 0:
        // op: Ii
        return 0;
      case 1:
        // op: Rtt32
        return 8;
      }
      break;
    }
    case Hexagon::A4_ext: {
      switch (OpNum) {
      case 0:
        // op: Ii
        return 0;
      }
      break;
    }
    case Hexagon::J2_call:
    case Hexagon::J2_jump: {
      switch (OpNum) {
      case 0:
        // op: Ii
        return 1;
      }
      break;
    }
    case Hexagon::J2_pause:
    case Hexagon::J2_trap0:
    case Hexagon::PS_trap1: {
      switch (OpNum) {
      case 0:
        // op: Ii
        return 2;
      }
      break;
    }
    case Hexagon::J2_loop0i:
    case Hexagon::J2_loop1i:
    case Hexagon::J2_ploop1si:
    case Hexagon::J2_ploop2si:
    case Hexagon::J2_ploop3si: {
      switch (OpNum) {
      case 0:
        // op: Ii
        return 3;
      case 1:
        // op: II
        return 0;
      }
      break;
    }
    case Hexagon::J2_loop0r:
    case Hexagon::J2_loop1r:
    case Hexagon::J2_ploop1sr:
    case Hexagon::J2_ploop2sr:
    case Hexagon::J2_ploop3sr: {
      switch (OpNum) {
      case 0:
        // op: Ii
        return 3;
      case 1:
        // op: Rs32
        return 16;
      }
      break;
    }
    case Hexagon::SS2_stored_sp: {
      switch (OpNum) {
      case 0:
        // op: Ii
        return 3;
      case 1:
        // op: Rtt8
        return 0;
      }
      break;
    }
    case Hexagon::SS2_storew_sp: {
      switch (OpNum) {
      case 0:
        // op: Ii
        return 4;
      case 1:
        // op: Rt16
        return 0;
      }
      break;
    }
    case Hexagon::SS2_allocframe: {
      switch (OpNum) {
      case 0:
        // op: Ii
        return 4;
      }
      break;
    }
    case Hexagon::V6_vwhist128m: {
      switch (OpNum) {
      case 0:
        // op: Ii
        return 8;
      }
      break;
    }
    case Hexagon::Y2_setimask:
    case Hexagon::Y2_setprio: {
      switch (OpNum) {
      case 0:
        // op: Pt4
        return 8;
      case 1:
        // op: Rs32
        return 16;
      }
      break;
    }
    case Hexagon::J2_callrf:
    case Hexagon::J2_callrt:
    case Hexagon::J2_jumprf:
    case Hexagon::J2_jumprfnew:
    case Hexagon::J2_jumprfnewpt:
    case Hexagon::J2_jumprfpt:
    case Hexagon::J2_jumprt:
    case Hexagon::J2_jumprtnew:
    case Hexagon::J2_jumprtnewpt:
    case Hexagon::J2_jumprtpt: {
      switch (OpNum) {
      case 0:
        // op: Pu4
        return 8;
      case 1:
        // op: Rs32
        return 16;
      }
      break;
    }
    case Hexagon::V6_vgathermhq:
    case Hexagon::V6_vgathermwq: {
      switch (OpNum) {
      case 0:
        // op: Qs4
        return 5;
      case 1:
        // op: Rt32
        return 16;
      case 2:
        // op: Mu2
        return 13;
      case 3:
        // op: Vv32
        return 0;
      }
      break;
    }
    case Hexagon::V6_vscattermhq:
    case Hexagon::V6_vscattermwq: {
      switch (OpNum) {
      case 0:
        // op: Qs4
        return 5;
      case 1:
        // op: Rt32
        return 16;
      case 2:
        // op: Mu2
        return 13;
      case 3:
        // op: Vv32
        return 8;
      case 4:
        // op: Vw32
        return 0;
      }
      break;
    }
    case Hexagon::V6_vgathermhwq: {
      switch (OpNum) {
      case 0:
        // op: Qs4
        return 5;
      case 1:
        // op: Rt32
        return 16;
      case 2:
        // op: Mu2
        return 13;
      case 3:
        // op: Vvv32
        return 0;
      }
      break;
    }
    case Hexagon::V6_vscattermhwq: {
      switch (OpNum) {
      case 0:
        // op: Qs4
        return 5;
      case 1:
        // op: Rt32
        return 16;
      case 2:
        // op: Mu2
        return 13;
      case 3:
        // op: Vvv32
        return 8;
      case 4:
        // op: Vw32
        return 0;
      }
      break;
    }
    case Hexagon::V6_vhistq:
    case Hexagon::V6_vwhist128q:
    case Hexagon::V6_vwhist256q:
    case Hexagon::V6_vwhist256q_sat: {
      switch (OpNum) {
      case 0:
        // op: Qv4
        return 22;
      }
      break;
    }
    case Hexagon::SA1_clrf:
    case Hexagon::SA1_clrfnew:
    case Hexagon::SA1_clrt:
    case Hexagon::SA1_clrtnew:
    case Hexagon::SA1_setin1: {
      switch (OpNum) {
      case 0:
        // op: Rd16
        return 0;
      }
      break;
    }
    case Hexagon::Y6_dmpause:
    case Hexagon::Y6_dmpoll:
    case Hexagon::Y6_dmwait: {
      switch (OpNum) {
      case 0:
        // op: Rd32
        return 0;
      }
      break;
    }
    case Hexagon::PS_callr_nr: {
      switch (OpNum) {
      case 0:
        // op: Rs
        return 16;
      }
      break;
    }
    case Hexagon::L6_memcpy: {
      switch (OpNum) {
      case 0:
        // op: Rs32
        return 16;
      case 1:
        // op: Rt32
        return 8;
      case 2:
        // op: Mu2
        return 13;
      }
      break;
    }
    case Hexagon::S2_storew_rl_at_vi:
    case Hexagon::S2_storew_rl_st_vi:
    case Hexagon::Y2_dctagw:
    case Hexagon::Y2_icdataw:
    case Hexagon::Y2_ictagw:
    case Hexagon::Y4_l2fetch:
    case Hexagon::Y4_l2tagw:
    case Hexagon::Y6_dmlink: {
      switch (OpNum) {
      case 0:
        // op: Rs32
        return 16;
      case 1:
        // op: Rt32
        return 8;
      }
      break;
    }
    case Hexagon::S4_stored_rl_at_vi:
    case Hexagon::S4_stored_rl_st_vi:
    case Hexagon::Y5_l2fetch: {
      switch (OpNum) {
      case 0:
        // op: Rs32
        return 16;
      case 1:
        // op: Rtt32
        return 8;
      }
      break;
    }
    case Hexagon::J2_callr:
    case Hexagon::J2_callrh:
    case Hexagon::J2_jumpr:
    case Hexagon::J2_jumprh:
    case Hexagon::J4_hintjumpr:
    case Hexagon::R6_release_at_vi:
    case Hexagon::R6_release_st_vi:
    case Hexagon::Y2_ciad:
    case Hexagon::Y2_cswi:
    case Hexagon::Y2_dccleana:
    case Hexagon::Y2_dccleanidx:
    case Hexagon::Y2_dccleaninva:
    case Hexagon::Y2_dccleaninvidx:
    case Hexagon::Y2_dcinva:
    case Hexagon::Y2_dcinvidx:
    case Hexagon::Y2_dczeroa:
    case Hexagon::Y2_iassignw:
    case Hexagon::Y2_icinva:
    case Hexagon::Y2_icinvidx:
    case Hexagon::Y2_l2cleaninvidx:
    case Hexagon::Y2_resume:
    case Hexagon::Y2_start:
    case Hexagon::Y2_stop:
    case Hexagon::Y2_swi:
    case Hexagon::Y2_wait:
    case Hexagon::Y4_nmi:
    case Hexagon::Y4_siad:
    case Hexagon::Y4_trace:
    case Hexagon::Y5_l2cleanidx:
    case Hexagon::Y5_l2invidx:
    case Hexagon::Y5_l2unlocka:
    case Hexagon::Y5_tlbasidi:
    case Hexagon::Y6_diag:
    case Hexagon::Y6_dmresume:
    case Hexagon::Y6_dmstart: {
      switch (OpNum) {
      case 0:
        // op: Rs32
        return 16;
      }
      break;
    }
    case Hexagon::Y2_tlbw: {
      switch (OpNum) {
      case 0:
        // op: Rss32
        return 16;
      case 1:
        // op: Rt32
        return 8;
      }
      break;
    }
    case Hexagon::Y6_diag0:
    case Hexagon::Y6_diag1: {
      switch (OpNum) {
      case 0:
        // op: Rss32
        return 16;
      case 1:
        // op: Rtt32
        return 8;
      }
      break;
    }
    case Hexagon::V6_vgathermh:
    case Hexagon::V6_vgathermw: {
      switch (OpNum) {
      case 0:
        // op: Rt32
        return 16;
      case 1:
        // op: Mu2
        return 13;
      case 2:
        // op: Vv32
        return 0;
      }
      break;
    }
    case Hexagon::V6_vscattermh:
    case Hexagon::V6_vscattermh_add:
    case Hexagon::V6_vscattermw:
    case Hexagon::V6_vscattermw_add: {
      switch (OpNum) {
      case 0:
        // op: Rt32
        return 16;
      case 1:
        // op: Mu2
        return 13;
      case 2:
        // op: Vv32
        return 8;
      case 3:
        // op: Vw32
        return 0;
      }
      break;
    }
    case Hexagon::V6_vgathermhw: {
      switch (OpNum) {
      case 0:
        // op: Rt32
        return 16;
      case 1:
        // op: Mu2
        return 13;
      case 2:
        // op: Vvv32
        return 0;
      }
      break;
    }
    case Hexagon::V6_vscattermhw:
    case Hexagon::V6_vscattermhw_add: {
      switch (OpNum) {
      case 0:
        // op: Rt32
        return 16;
      case 1:
        // op: Mu2
        return 13;
      case 2:
        // op: Vvv32
        return 8;
      case 3:
        // op: Vw32
        return 0;
      }
      break;
    }
    case Hexagon::Y6_l2gcleaninvpa:
    case Hexagon::Y6_l2gcleanpa: {
      switch (OpNum) {
      case 0:
        // op: Rtt32
        return 8;
      }
      break;
    }
    case Hexagon::Y2_crswap0:
    case Hexagon::Y4_crswap1: {
      switch (OpNum) {
      case 0:
        // op: Rx32
        return 16;
      }
      break;
    }
    case Hexagon::Y4_crswap10: {
      switch (OpNum) {
      case 0:
        // op: Rxx32
        return 16;
      }
      break;
    }
    case Hexagon::HI:
    case Hexagon::LO: {
      switch (OpNum) {
      case 0:
        // op: dst
        return 16;
      case 1:
        // op: imm_value
        return 0;
      }
      break;
    }
    case Hexagon::EH_RETURN_JMPR:
    case Hexagon::PS_jmpret: {
      switch (OpNum) {
      case 0:
        // op: dst
        return 16;
      }
      break;
    }
    case Hexagon::CALLProfile:
    case Hexagon::PS_call_stk:
    case Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4:
    case Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT:
    case Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT_PIC:
    case Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_PIC:
    case Hexagon::RESTORE_DEALLOC_RET_JMP_V4:
    case Hexagon::RESTORE_DEALLOC_RET_JMP_V4_EXT:
    case Hexagon::RESTORE_DEALLOC_RET_JMP_V4_EXT_PIC:
    case Hexagon::RESTORE_DEALLOC_RET_JMP_V4_PIC:
    case Hexagon::SAVE_REGISTERS_CALL_V4:
    case Hexagon::SAVE_REGISTERS_CALL_V4STK:
    case Hexagon::SAVE_REGISTERS_CALL_V4STK_EXT:
    case Hexagon::SAVE_REGISTERS_CALL_V4STK_EXT_PIC:
    case Hexagon::SAVE_REGISTERS_CALL_V4STK_PIC:
    case Hexagon::SAVE_REGISTERS_CALL_V4_EXT:
    case Hexagon::SAVE_REGISTERS_CALL_V4_EXT_PIC:
    case Hexagon::SAVE_REGISTERS_CALL_V4_PIC: {
      switch (OpNum) {
      case 0:
        // op: dst
        return 1;
      }
      break;
    }
    case Hexagon::J2_loop0iext:
    case Hexagon::J2_loop1iext: {
      switch (OpNum) {
      case 0:
        // op: offset
        return 3;
      case 1:
        // op: src2
        return 0;
      }
      break;
    }
    case Hexagon::J2_loop0rext:
    case Hexagon::J2_loop1rext: {
      switch (OpNum) {
      case 0:
        // op: offset
        return 3;
      case 1:
        // op: src2
        return 16;
      }
      break;
    }
    case Hexagon::PS_jmpretf:
    case Hexagon::PS_jmpretfnew:
    case Hexagon::PS_jmpretfnewpt:
    case Hexagon::PS_jmprett:
    case Hexagon::PS_jmprettnew:
    case Hexagon::PS_jmprettnewpt: {
      switch (OpNum) {
      case 0:
        // op: src
        return 8;
      case 1:
        // op: dst
        return 16;
      }
      break;
    }
    case Hexagon::A2_tfrcrr: {
      switch (OpNum) {
      case 1:
        // op: Cs32
        return 16;
      case 0:
        // op: Rd32
        return 0;
      }
      break;
    }
    case Hexagon::A4_tfrcpp: {
      switch (OpNum) {
      case 1:
        // op: Css32
        return 16;
      case 0:
        // op: Rdd32
        return 0;
      }
      break;
    }
    case Hexagon::G4_tfrgcrr: {
      switch (OpNum) {
      case 1:
        // op: Gs32
        return 16;
      case 0:
        // op: Rd32
        return 0;
      }
      break;
    }
    case Hexagon::G4_tfrgcpp: {
      switch (OpNum) {
      case 1:
        // op: Gss32
        return 16;
      case 0:
        // op: Rdd32
        return 0;
      }
      break;
    }
    case Hexagon::S4_storerbnew_ap:
    case Hexagon::S4_storerhnew_ap:
    case Hexagon::S4_storerinew_ap: {
      switch (OpNum) {
      case 1:
        // op: II
        return 0;
      case 2:
        // op: Nt8
        return 8;
      case 0:
        // op: Re32
        return 16;
      }
      break;
    }
    case Hexagon::S4_storerb_ap:
    case Hexagon::S4_storerf_ap:
    case Hexagon::S4_storerh_ap:
    case Hexagon::S4_storeri_ap: {
      switch (OpNum) {
      case 1:
        // op: II
        return 0;
      case 2:
        // op: Rt32
        return 8;
      case 0:
        // op: Re32
        return 16;
      }
      break;
    }
    case Hexagon::S4_storerd_ap: {
      switch (OpNum) {
      case 1:
        // op: II
        return 0;
      case 2:
        // op: Rtt32
        return 8;
      case 0:
        // op: Re32
        return 16;
      }
      break;
    }
    case Hexagon::J4_cmpeqi_f_jumpnv_nt:
    case Hexagon::J4_cmpeqi_f_jumpnv_t:
    case Hexagon::J4_cmpeqi_t_jumpnv_nt:
    case Hexagon::J4_cmpeqi_t_jumpnv_t:
    case Hexagon::J4_cmpgti_f_jumpnv_nt:
    case Hexagon::J4_cmpgti_f_jumpnv_t:
    case Hexagon::J4_cmpgti_t_jumpnv_nt:
    case Hexagon::J4_cmpgti_t_jumpnv_t:
    case Hexagon::J4_cmpgtui_f_jumpnv_nt:
    case Hexagon::J4_cmpgtui_f_jumpnv_t:
    case Hexagon::J4_cmpgtui_t_jumpnv_nt:
    case Hexagon::J4_cmpgtui_t_jumpnv_t: {
      switch (OpNum) {
      case 1:
        // op: II
        return 8;
      case 2:
        // op: Ii
        return 1;
      case 0:
        // op: Ns8
        return 16;
      }
      break;
    }
    case Hexagon::J4_jumpseti: {
      switch (OpNum) {
      case 1:
        // op: II
        return 8;
      case 2:
        // op: Ii
        return 1;
      case 0:
        // op: Rd16
        return 16;
      }
      break;
    }
    case Hexagon::J4_cmpeqi_fp0_jump_nt:
    case Hexagon::J4_cmpeqi_fp0_jump_t:
    case Hexagon::J4_cmpeqi_fp1_jump_nt:
    case Hexagon::J4_cmpeqi_fp1_jump_t:
    case Hexagon::J4_cmpeqi_tp0_jump_nt:
    case Hexagon::J4_cmpeqi_tp0_jump_t:
    case Hexagon::J4_cmpeqi_tp1_jump_nt:
    case Hexagon::J4_cmpeqi_tp1_jump_t:
    case Hexagon::J4_cmpgti_fp0_jump_nt:
    case Hexagon::J4_cmpgti_fp0_jump_t:
    case Hexagon::J4_cmpgti_fp1_jump_nt:
    case Hexagon::J4_cmpgti_fp1_jump_t:
    case Hexagon::J4_cmpgti_tp0_jump_nt:
    case Hexagon::J4_cmpgti_tp0_jump_t:
    case Hexagon::J4_cmpgti_tp1_jump_nt:
    case Hexagon::J4_cmpgti_tp1_jump_t:
    case Hexagon::J4_cmpgtui_fp0_jump_nt:
    case Hexagon::J4_cmpgtui_fp0_jump_t:
    case Hexagon::J4_cmpgtui_fp1_jump_nt:
    case Hexagon::J4_cmpgtui_fp1_jump_t:
    case Hexagon::J4_cmpgtui_tp0_jump_nt:
    case Hexagon::J4_cmpgtui_tp0_jump_t:
    case Hexagon::J4_cmpgtui_tp1_jump_nt:
    case Hexagon::J4_cmpgtui_tp1_jump_t: {
      switch (OpNum) {
      case 1:
        // op: II
        return 8;
      case 2:
        // op: Ii
        return 1;
      case 0:
        // op: Rs16
        return 16;
      }
      break;
    }
    case Hexagon::SA1_cmpeqi:
    case Hexagon::SS2_storebi0:
    case Hexagon::SS2_storebi1:
    case Hexagon::SS2_storewi0:
    case Hexagon::SS2_storewi1: {
      switch (OpNum) {
      case 1:
        // op: Ii
        return 0;
      case 0:
        // op: Rs16
        return 4;
      }
      break;
    }
    case Hexagon::S2_storerbnew_io:
    case Hexagon::S2_storerhnew_io:
    case Hexagon::S2_storerinew_io: {
      switch (OpNum) {
      case 1:
        // op: Ii
        return 0;
      case 0:
        // op: Rs32
        return 16;
      case 2:
        // op: Nt8
        return 8;
      }
      break;
    }
    case Hexagon::S2_storerb_io:
    case Hexagon::S2_storerf_io:
    case Hexagon::S2_storerh_io:
    case Hexagon::S2_storeri_io: {
      switch (OpNum) {
      case 1:
        // op: Ii
        return 0;
      case 0:
        // op: Rs32
        return 16;
      case 2:
        // op: Rt32
        return 8;
      }
      break;
    }
    case Hexagon::S2_storerd_io: {
      switch (OpNum) {
      case 1:
        // op: Ii
        return 0;
      case 0:
        // op: Rs32
        return 16;
      case 2:
        // op: Rtt32
        return 8;
      }
      break;
    }
    case Hexagon::Y2_dcfetchbo: {
      switch (OpNum) {
      case 1:
        // op: Ii
        return 0;
      case 0:
        // op: Rs32
        return 16;
      }
      break;
    }
    case Hexagon::J4_tstbit0_f_jumpnv_nt:
    case Hexagon::J4_tstbit0_f_jumpnv_t:
    case Hexagon::J4_tstbit0_t_jumpnv_nt:
    case Hexagon::J4_tstbit0_t_jumpnv_t: {
      switch (OpNum) {
      case 1:
        // op: Ii
        return 1;
      case 0:
        // op: Ns8
        return 16;
      }
      break;
    }
    case Hexagon::J2_callf:
    case Hexagon::J2_callt:
    case Hexagon::J2_jumpf:
    case Hexagon::J2_jumpfnew:
    case Hexagon::J2_jumpfnewpt:
    case Hexagon::J2_jumpfpt:
    case Hexagon::J2_jumpt:
    case Hexagon::J2_jumptnew:
    case Hexagon::J2_jumptnewpt:
    case Hexagon::J2_jumptpt: {
      switch (OpNum) {
      case 1:
        // op: Ii
        return 1;
      case 0:
        // op: Pu4
        return 8;
      }
      break;
    }
    case Hexagon::J4_tstbit0_fp0_jump_nt:
    case Hexagon::J4_tstbit0_fp0_jump_t:
    case Hexagon::J4_tstbit0_fp1_jump_nt:
    case Hexagon::J4_tstbit0_fp1_jump_t:
    case Hexagon::J4_tstbit0_tp0_jump_nt:
    case Hexagon::J4_tstbit0_tp0_jump_t:
    case Hexagon::J4_tstbit0_tp1_jump_nt:
    case Hexagon::J4_tstbit0_tp1_jump_t: {
      switch (OpNum) {
      case 1:
        // op: Ii
        return 1;
      case 0:
        // op: Rs16
        return 16;
      }
      break;
    }
    case Hexagon::J2_jumprgtez:
    case Hexagon::J2_jumprgtezpt:
    case Hexagon::J2_jumprltez:
    case Hexagon::J2_jumprltezpt:
    case Hexagon::J2_jumprnz:
    case Hexagon::J2_jumprnzpt:
    case Hexagon::J2_jumprz:
    case Hexagon::J2_jumprzpt: {
      switch (OpNum) {
      case 1:
        // op: Ii
        return 1;
      case 0:
        // op: Rs32
        return 16;
      }
      break;
    }
    case Hexagon::S4_pstorerbnewf_abs:
    case Hexagon::S4_pstorerbnewfnew_abs:
    case Hexagon::S4_pstorerbnewt_abs:
    case Hexagon::S4_pstorerbnewtnew_abs:
    case Hexagon::S4_pstorerhnewf_abs:
    case Hexagon::S4_pstorerhnewfnew_abs:
    case Hexagon::S4_pstorerhnewt_abs:
    case Hexagon::S4_pstorerhnewtnew_abs:
    case Hexagon::S4_pstorerinewf_abs:
    case Hexagon::S4_pstorerinewfnew_abs:
    case Hexagon::S4_pstorerinewt_abs:
    case Hexagon::S4_pstorerinewtnew_abs: {
      switch (OpNum) {
      case 1:
        // op: Ii
        return 3;
      case 0:
        // op: Pv4
        return 0;
      case 2:
        // op: Nt8
        return 8;
      }
      break;
    }
    case Hexagon::S4_pstorerbf_abs:
    case Hexagon::S4_pstorerbfnew_abs:
    case Hexagon::S4_pstorerbt_abs:
    case Hexagon::S4_pstorerbtnew_abs:
    case Hexagon::S4_pstorerff_abs:
    case Hexagon::S4_pstorerffnew_abs:
    case Hexagon::S4_pstorerft_abs:
    case Hexagon::S4_pstorerftnew_abs:
    case Hexagon::S4_pstorerhf_abs:
    case Hexagon::S4_pstorerhfnew_abs:
    case Hexagon::S4_pstorerht_abs:
    case Hexagon::S4_pstorerhtnew_abs:
    case Hexagon::S4_pstorerif_abs:
    case Hexagon::S4_pstorerifnew_abs:
    case Hexagon::S4_pstorerit_abs:
    case Hexagon::S4_pstoreritnew_abs: {
      switch (OpNum) {
      case 1:
        // op: Ii
        return 3;
      case 0:
        // op: Pv4
        return 0;
      case 2:
        // op: Rt32
        return 8;
      }
      break;
    }
    case Hexagon::S4_pstorerdf_abs:
    case Hexagon::S4_pstorerdfnew_abs:
    case Hexagon::S4_pstorerdt_abs:
    case Hexagon::S4_pstorerdtnew_abs: {
      switch (OpNum) {
      case 1:
        // op: Ii
        return 3;
      case 0:
        // op: Pv4
        return 0;
      case 2:
        // op: Rtt32
        return 8;
      }
      break;
    }
    case Hexagon::SL2_loadrd_sp: {
      switch (OpNum) {
      case 1:
        // op: Ii
        return 3;
      case 0:
        // op: Rdd8
        return 0;
      }
      break;
    }
    case Hexagon::S4_addi_asl_ri:
    case Hexagon::S4_addi_lsr_ri:
    case Hexagon::S4_andi_asl_ri:
    case Hexagon::S4_andi_lsr_ri:
    case Hexagon::S4_ori_asl_ri:
    case Hexagon::S4_ori_lsr_ri:
    case Hexagon::S4_subi_asl_ri:
    case Hexagon::S4_subi_lsr_ri: {
      switch (OpNum) {
      case 1:
        // op: Ii
        return 3;
      case 3:
        // op: II
        return 8;
      case 0:
        // op: Rx32
        return 16;
      }
      break;
    }
    case Hexagon::SA1_addsp:
    case Hexagon::SA1_seti:
    case Hexagon::SL2_loadri_sp: {
      switch (OpNum) {
      case 1:
        // op: Ii
        return 4;
      case 0:
        // op: Rd16
        return 0;
      }
      break;
    }
    case Hexagon::A2_tfrsi:
    case Hexagon::F2_sfimm_n:
    case Hexagon::F2_sfimm_p:
    case Hexagon::L2_loadrbgp:
    case Hexagon::L2_loadrhgp:
    case Hexagon::L2_loadrigp:
    case Hexagon::L2_loadrubgp:
    case Hexagon::L2_loadruhgp:
    case Hexagon::PS_loadrbabs:
    case Hexagon::PS_loadrhabs:
    case Hexagon::PS_loadriabs:
    case Hexagon::PS_loadrubabs:
    case Hexagon::PS_loadruhabs: {
      switch (OpNum) {
      case 1:
        // op: Ii
        return 5;
      case 0:
        // op: Rd32
        return 0;
      }
      break;
    }
    case Hexagon::F2_dfimm_n:
    case Hexagon::F2_dfimm_p:
    case Hexagon::L2_loadrdgp:
    case Hexagon::PS_loadrdabs: {
      switch (OpNum) {
      case 1:
        // op: Ii
        return 5;
      case 0:
        // op: Rdd32
        return 0;
      }
      break;
    }
    case Hexagon::SA1_combine0i:
    case Hexagon::SA1_combine1i:
    case Hexagon::SA1_combine2i:
    case Hexagon::SA1_combine3i: {
      switch (OpNum) {
      case 1:
        // op: Ii
        return 5;
      case 0:
        // op: Rdd8
        return 0;
      }
      break;
    }
    case Hexagon::A2_combineii:
    case Hexagon::A4_combineii: {
      switch (OpNum) {
      case 1:
        // op: Ii
        return 5;
      case 2:
        // op: II
        return 13;
      case 0:
        // op: Rdd32
        return 0;
      }
      break;
    }
    case Hexagon::A2_subri: {
      switch (OpNum) {
      case 1:
        // op: Ii
        return 5;
      case 2:
        // op: Rs32
        return 16;
      case 0:
        // op: Rd32
        return 0;
      }
      break;
    }
    case Hexagon::A4_combineir: {
      switch (OpNum) {
      case 1:
        // op: Ii
        return 5;
      case 2:
        // op: Rs32
        return 16;
      case 0:
        // op: Rdd32
        return 0;
      }
      break;
    }
    case Hexagon::M4_mpyrr_addi: {
      switch (OpNum) {
      case 1:
        // op: Ii
        return 5;
      case 2:
        // op: Rs32
        return 16;
      case 3:
        // op: Rt32
        return 8;
      case 0:
        // op: Rd32
        return 0;
      }
      break;
    }
    case Hexagon::S4_lsli: {
      switch (OpNum) {
      case 1:
        // op: Ii
        return 5;
      case 2:
        // op: Rt32
        return 8;
      case 0:
        // op: Rd32
        return 0;
      }
      break;
    }
    case Hexagon::M4_mpyri_addi: {
      switch (OpNum) {
      case 1:
        // op: Ii
        return 5;
      case 3:
        // op: II
        return 0;
      case 2:
        // op: Rs32
        return 16;
      case 0:
        // op: Rd32
        return 8;
      }
      break;
    }
    case Hexagon::S4_storerbnew_ur:
    case Hexagon::S4_storerhnew_ur:
    case Hexagon::S4_storerinew_ur: {
      switch (OpNum) {
      case 1:
        // op: Ii
        return 6;
      case 2:
        // op: II
        return 0;
      case 0:
        // op: Ru32
        return 16;
      case 3:
        // op: Nt8
        return 8;
      }
      break;
    }
    case Hexagon::S4_storerb_ur:
    case Hexagon::S4_storerf_ur:
    case Hexagon::S4_storerh_ur:
    case Hexagon::S4_storeri_ur: {
      switch (OpNum) {
      case 1:
        // op: Ii
        return 6;
      case 2:
        // op: II
        return 0;
      case 0:
        // op: Ru32
        return 16;
      case 3:
        // op: Rt32
        return 8;
      }
      break;
    }
    case Hexagon::S4_storerd_ur: {
      switch (OpNum) {
      case 1:
        // op: Ii
        return 6;
      case 2:
        // op: II
        return 0;
      case 0:
        // op: Ru32
        return 16;
      case 3:
        // op: Rtt32
        return 8;
      }
      break;
    }
    case Hexagon::C4_addipc: {
      switch (OpNum) {
      case 1:
        // op: Ii
        return 7;
      case 0:
        // op: Rd32
        return 0;
      }
      break;
    }
    case Hexagon::L4_add_memopb_io:
    case Hexagon::L4_add_memoph_io:
    case Hexagon::L4_add_memopw_io:
    case Hexagon::L4_and_memopb_io:
    case Hexagon::L4_and_memoph_io:
    case Hexagon::L4_and_memopw_io:
    case Hexagon::L4_or_memopb_io:
    case Hexagon::L4_or_memoph_io:
    case Hexagon::L4_or_memopw_io:
    case Hexagon::L4_sub_memopb_io:
    case Hexagon::L4_sub_memoph_io:
    case Hexagon::L4_sub_memopw_io: {
      switch (OpNum) {
      case 1:
        // op: Ii
        return 7;
      case 0:
        // op: Rs32
        return 16;
      case 2:
        // op: Rt32
        return 0;
      }
      break;
    }
    case Hexagon::L4_iadd_memopb_io:
    case Hexagon::L4_iadd_memoph_io:
    case Hexagon::L4_iadd_memopw_io:
    case Hexagon::L4_iand_memopb_io:
    case Hexagon::L4_iand_memoph_io:
    case Hexagon::L4_iand_memopw_io:
    case Hexagon::L4_ior_memopb_io:
    case Hexagon::L4_ior_memoph_io:
    case Hexagon::L4_ior_memopw_io:
    case Hexagon::L4_isub_memopb_io:
    case Hexagon::L4_isub_memoph_io:
    case Hexagon::L4_isub_memopw_io:
    case Hexagon::S4_storeirb_io:
    case Hexagon::S4_storeirh_io:
    case Hexagon::S4_storeiri_io: {
      switch (OpNum) {
      case 1:
        // op: Ii
        return 7;
      case 2:
        // op: II
        return 0;
      case 0:
        // op: Rs32
        return 16;
      }
      break;
    }
    case Hexagon::V6_vwhist128qm: {
      switch (OpNum) {
      case 1:
        // op: Ii
        return 8;
      case 0:
        // op: Qv4
        return 22;
      }
      break;
    }
    case Hexagon::SS1_storeb_io:
    case Hexagon::SS1_storew_io:
    case Hexagon::SS2_storeh_io: {
      switch (OpNum) {
      case 1:
        // op: Ii
        return 8;
      case 0:
        // op: Rs16
        return 4;
      case 2:
        // op: Rt16
        return 0;
      }
      break;
    }
    case Hexagon::V6_vS32b_new_ai:
    case Hexagon::V6_vS32b_nt_new_ai: {
      switch (OpNum) {
      case 1:
        // op: Ii
        return 8;
      case 0:
        // op: Rt32
        return 16;
      case 2:
        // op: Os8
        return 0;
      }
      break;
    }
    case Hexagon::V6_vS32Ub_ai:
    case Hexagon::V6_vS32b_ai:
    case Hexagon::V6_vS32b_nt_ai: {
      switch (OpNum) {
      case 1:
        // op: Ii
        return 8;
      case 0:
        // op: Rt32
        return 16;
      case 2:
        // op: Vs32
        return 0;
      }
      break;
    }
    case Hexagon::V6_vS32b_srls_ai:
    case Hexagon::V6_zLd_ai: {
      switch (OpNum) {
      case 1:
        // op: Ii
        return 8;
      case 0:
        // op: Rt32
        return 16;
      }
      break;
    }
    case Hexagon::S2_mask: {
      switch (OpNum) {
      case 1:
        // op: Ii
        return 8;
      case 2:
        // op: II
        return 5;
      case 0:
        // op: Rd32
        return 0;
      }
      break;
    }
    case Hexagon::C2_all8:
    case Hexagon::C2_any8:
    case Hexagon::C2_not: {
      switch (OpNum) {
      case 1:
        // op: Ps4
        return 16;
      case 0:
        // op: Pd4
        return 0;
      }
      break;
    }
    case Hexagon::C2_tfrpr: {
      switch (OpNum) {
      case 1:
        // op: Ps4
        return 16;
      case 0:
        // op: Rd32
        return 0;
      }
      break;
    }
    case Hexagon::C2_xor:
    case Hexagon::C4_fastcorner9:
    case Hexagon::C4_fastcorner9_not: {
      switch (OpNum) {
      case 1:
        // op: Ps4
        return 16;
      case 2:
        // op: Pt4
        return 8;
      case 0:
        // op: Pd4
        return 0;
      }
      break;
    }
    case Hexagon::C2_vitpack: {
      switch (OpNum) {
      case 1:
        // op: Ps4
        return 16;
      case 2:
        // op: Pt4
        return 8;
      case 0:
        // op: Rd32
        return 0;
      }
      break;
    }
    case Hexagon::C4_and_and:
    case Hexagon::C4_and_andn:
    case Hexagon::C4_and_or:
    case Hexagon::C4_and_orn:
    case Hexagon::C4_or_and:
    case Hexagon::C4_or_andn:
    case Hexagon::C4_or_or:
    case Hexagon::C4_or_orn: {
      switch (OpNum) {
      case 1:
        // op: Ps4
        return 16;
      case 2:
        // op: Pt4
        return 8;
      case 3:
        // op: Pu4
        return 6;
      case 0:
        // op: Pd4
        return 0;
      }
      break;
    }
    case Hexagon::V6_vcmov:
    case Hexagon::V6_vncmov: {
      switch (OpNum) {
      case 1:
        // op: Ps4
        return 5;
      case 2:
        // op: Vu32
        return 8;
      case 0:
        // op: Vd32
        return 0;
      }
      break;
    }
    case Hexagon::V6_vccombine:
    case Hexagon::V6_vnccombine: {
      switch (OpNum) {
      case 1:
        // op: Ps4
        return 5;
      case 2:
        // op: Vu32
        return 8;
      case 3:
        // op: Vv32
        return 16;
      case 0:
        // op: Vdd32
        return 0;
      }
      break;
    }
    case Hexagon::C2_mask: {
      switch (OpNum) {
      case 1:
        // op: Pt4
        return 8;
      case 0:
        // op: Rdd32
        return 0;
      }
      break;
    }
    case Hexagon::C2_and:
    case Hexagon::C2_andn:
    case Hexagon::C2_or:
    case Hexagon::C2_orn: {
      switch (OpNum) {
      case 1:
        // op: Pt4
        return 8;
      case 2:
        // op: Ps4
        return 16;
      case 0:
        // op: Pd4
        return 0;
      }
      break;
    }
    case Hexagon::A2_paddf:
    case Hexagon::A2_paddfnew:
    case Hexagon::A2_paddt:
    case Hexagon::A2_paddtnew:
    case Hexagon::A2_pandf:
    case Hexagon::A2_pandfnew:
    case Hexagon::A2_pandt:
    case Hexagon::A2_pandtnew:
    case Hexagon::A2_porf:
    case Hexagon::A2_porfnew:
    case Hexagon::A2_port:
    case Hexagon::A2_portnew:
    case Hexagon::A2_pxorf:
    case Hexagon::A2_pxorfnew:
    case Hexagon::A2_pxort:
    case Hexagon::A2_pxortnew:
    case Hexagon::C2_mux: {
      switch (OpNum) {
      case 1:
        // op: Pu4
        return 5;
      case 2:
        // op: Rs32
        return 16;
      case 3:
        // op: Rt32
        return 8;
      case 0:
        // op: Rd32
        return 0;
      }
      break;
    }
    case Hexagon::C2_ccombinewf:
    case Hexagon::C2_ccombinewnewf:
    case Hexagon::C2_ccombinewnewt:
    case Hexagon::C2_ccombinewt: {
      switch (OpNum) {
      case 1:
        // op: Pu4
        return 5;
      case 2:
        // op: Rs32
        return 16;
      case 3:
        // op: Rt32
        return 8;
      case 0:
        // op: Rdd32
        return 0;
      }
      break;
    }
    case Hexagon::C2_vmux: {
      switch (OpNum) {
      case 1:
        // op: Pu4
        return 5;
      case 2:
        // op: Rss32
        return 16;
      case 3:
        // op: Rtt32
        return 8;
      case 0:
        // op: Rdd32
        return 0;
      }
      break;
    }
    case Hexagon::A2_psubf:
    case Hexagon::A2_psubfnew:
    case Hexagon::A2_psubt:
    case Hexagon::A2_psubtnew: {
      switch (OpNum) {
      case 1:
        // op: Pu4
        return 5;
      case 2:
        // op: Rt32
        return 8;
      case 3:
        // op: Rs32
        return 16;
      case 0:
        // op: Rd32
        return 0;
      }
      break;
    }
    case Hexagon::A4_paslhf:
    case Hexagon::A4_paslhfnew:
    case Hexagon::A4_paslht:
    case Hexagon::A4_paslhtnew:
    case Hexagon::A4_pasrhf:
    case Hexagon::A4_pasrhfnew:
    case Hexagon::A4_pasrht:
    case Hexagon::A4_pasrhtnew:
    case Hexagon::A4_psxtbf:
    case Hexagon::A4_psxtbfnew:
    case Hexagon::A4_psxtbt:
    case Hexagon::A4_psxtbtnew:
    case Hexagon::A4_psxthf:
    case Hexagon::A4_psxthfnew:
    case Hexagon::A4_psxtht:
    case Hexagon::A4_psxthtnew:
    case Hexagon::A4_pzxtbf:
    case Hexagon::A4_pzxtbfnew:
    case Hexagon::A4_pzxtbt:
    case Hexagon::A4_pzxtbtnew:
    case Hexagon::A4_pzxthf:
    case Hexagon::A4_pzxthfnew:
    case Hexagon::A4_pzxtht:
    case Hexagon::A4_pzxthtnew: {
      switch (OpNum) {
      case 1:
        // op: Pu4
        return 8;
      case 2:
        // op: Rs32
        return 16;
      case 0:
        // op: Rd32
        return 0;
      }
      break;
    }
    case Hexagon::V6_zLd_pred_ppu: {
      switch (OpNum) {
      case 1:
        // op: Pv4
        return 11;
      case 3:
        // op: Mu2
        return 13;
      case 0:
        // op: Rx32
        return 16;
      }
      break;
    }
    case Hexagon::V6_vS32b_new_npred_ppu:
    case Hexagon::V6_vS32b_new_pred_ppu:
    case Hexagon::V6_vS32b_nt_new_npred_ppu:
    case Hexagon::V6_vS32b_nt_new_pred_ppu: {
      switch (OpNum) {
      case 1:
        // op: Pv4
        return 11;
      case 3:
        // op: Mu2
        return 13;
      case 4:
        // op: Os8
        return 0;
      case 0:
        // op: Rx32
        return 16;
      }
      break;
    }
    case Hexagon::V6_vS32Ub_npred_ppu:
    case Hexagon::V6_vS32Ub_pred_ppu:
    case Hexagon::V6_vS32b_npred_ppu:
    case Hexagon::V6_vS32b_nt_npred_ppu:
    case Hexagon::V6_vS32b_nt_pred_ppu:
    case Hexagon::V6_vS32b_pred_ppu: {
      switch (OpNum) {
      case 1:
        // op: Pv4
        return 11;
      case 3:
        // op: Mu2
        return 13;
      case 4:
        // op: Vs32
        return 0;
      case 0:
        // op: Rx32
        return 16;
      }
      break;
    }
    case Hexagon::L4_return_f:
    case Hexagon::L4_return_fnew_pnt:
    case Hexagon::L4_return_fnew_pt:
    case Hexagon::L4_return_t:
    case Hexagon::L4_return_tnew_pnt:
    case Hexagon::L4_return_tnew_pt: {
      switch (OpNum) {
      case 1:
        // op: Pv4
        return 8;
      case 2:
        // op: Rs32
        return 16;
      case 0:
        // op: Rdd32
        return 0;
      }
      break;
    }
    case Hexagon::V6_pred_not: {
      switch (OpNum) {
      case 1:
        // op: Qs4
        return 8;
      case 0:
        // op: Qd4
        return 0;
      }
      break;
    }
    case Hexagon::V6_pred_and:
    case Hexagon::V6_pred_and_n:
    case Hexagon::V6_pred_or:
    case Hexagon::V6_pred_or_n:
    case Hexagon::V6_pred_xor:
    case Hexagon::V6_shuffeqh:
    case Hexagon::V6_shuffeqw: {
      switch (OpNum) {
      case 1:
        // op: Qs4
        return 8;
      case 2:
        // op: Qt4
        return 22;
      case 0:
        // op: Qd4
        return 0;
      }
      break;
    }
    case Hexagon::V6_vmux: {
      switch (OpNum) {
      case 1:
        // op: Qt4
        return 5;
      case 2:
        // op: Vu32
        return 8;
      case 3:
        // op: Vv32
        return 16;
      case 0:
        // op: Vd32
        return 0;
      }
      break;
    }
    case Hexagon::V6_vswap: {
      switch (OpNum) {
      case 1:
        // op: Qt4
        return 5;
      case 2:
        // op: Vu32
        return 8;
      case 3:
        // op: Vv32
        return 16;
      case 0:
        // op: Vdd32
        return 0;
      }
      break;
    }
    case Hexagon::V6_vandnqrt:
    case Hexagon::V6_vandqrt: {
      switch (OpNum) {
      case 1:
        // op: Qu4
        return 8;
      case 2:
        // op: Rt32
        return 16;
      case 0:
        // op: Vd32
        return 0;
      }
      break;
    }
    case Hexagon::V6_vS32b_nqpred_ppu:
    case Hexagon::V6_vS32b_nt_nqpred_ppu:
    case Hexagon::V6_vS32b_nt_qpred_ppu:
    case Hexagon::V6_vS32b_qpred_ppu: {
      switch (OpNum) {
      case 1:
        // op: Qv4
        return 11;
      case 3:
        // op: Mu2
        return 13;
      case 4:
        // op: Vs32
        return 0;
      case 0:
        // op: Rx32
        return 16;
      }
      break;
    }
    case Hexagon::V6_vprefixqb:
    case Hexagon::V6_vprefixqh:
    case Hexagon::V6_vprefixqw: {
      switch (OpNum) {
      case 1:
        // op: Qv4
        return 22;
      case 0:
        // op: Vd32
        return 0;
      }
      break;
    }
    case Hexagon::V6_vandvnqv:
    case Hexagon::V6_vandvqv: {
      switch (OpNum) {
      case 1:
        // op: Qv4
        return 22;
      case 2:
        // op: Vu32
        return 8;
      case 0:
        // op: Vd32
        return 0;
      }
      break;
    }
    case Hexagon::V6_vaddbnq:
    case Hexagon::V6_vaddbq:
    case Hexagon::V6_vaddhnq:
    case Hexagon::V6_vaddhq:
    case Hexagon::V6_vaddwnq:
    case Hexagon::V6_vaddwq:
    case Hexagon::V6_vsubbnq:
    case Hexagon::V6_vsubbq:
    case Hexagon::V6_vsubhnq:
    case Hexagon::V6_vsubhq:
    case Hexagon::V6_vsubwnq:
    case Hexagon::V6_vsubwq: {
      switch (OpNum) {
      case 1:
        // op: Qv4
        return 22;
      case 3:
        // op: Vu32
        return 8;
      case 0:
        // op: Vx32
        return 0;
      }
      break;
    }
    case Hexagon::SA1_and1:
    case Hexagon::SA1_dec:
    case Hexagon::SA1_inc:
    case Hexagon::SA1_sxtb:
    case Hexagon::SA1_sxth:
    case Hexagon::SA1_tfr:
    case Hexagon::SA1_zxtb:
    case Hexagon::SA1_zxth: {
      switch (OpNum) {
      case 1:
        // op: Rs16
        return 4;
      case 0:
        // op: Rd16
        return 0;
      }
      break;
    }
    case Hexagon::SA1_combinerz:
    case Hexagon::SA1_combinezr: {
      switch (OpNum) {
      case 1:
        // op: Rs16
        return 4;
      case 0:
        // op: Rdd8
        return 0;
      }
      break;
    }
    case Hexagon::A2_tfrrcr: {
      switch (OpNum) {
      case 1:
        // op: Rs32
        return 16;
      case 0:
        // op: Cd32
        return 0;
      }
      break;
    }
    case Hexagon::G4_tfrgrcr: {
      switch (OpNum) {
      case 1:
        // op: Rs32
        return 16;
      case 0:
        // op: Gd32
        return 0;
      }
      break;
    }
    case Hexagon::C2_tfrrp:
    case Hexagon::Y5_l2locka: {
      switch (OpNum) {
      case 1:
        // op: Rs32
        return 16;
      case 0:
        // op: Pd4
        return 0;
      }
      break;
    }
    case Hexagon::A2_abs:
    case Hexagon::A2_abssat:
    case Hexagon::A2_aslh:
    case Hexagon::A2_asrh:
    case Hexagon::A2_negsat:
    case Hexagon::A2_satb:
    case Hexagon::A2_sath:
    case Hexagon::A2_satub:
    case Hexagon::A2_satuh:
    case Hexagon::A2_swiz:
    case Hexagon::A2_sxtb:
    case Hexagon::A2_sxth:
    case Hexagon::A2_tfr:
    case Hexagon::A2_zxth:
    case Hexagon::F2_conv_sf2uw:
    case Hexagon::F2_conv_sf2uw_chop:
    case Hexagon::F2_conv_sf2w:
    case Hexagon::F2_conv_sf2w_chop:
    case Hexagon::F2_conv_uw2sf:
    case Hexagon::F2_conv_w2sf:
    case Hexagon::F2_sffixupr:
    case Hexagon::L2_loadw_aq:
    case Hexagon::L2_loadw_locked:
    case Hexagon::S2_brev:
    case Hexagon::S2_cl0:
    case Hexagon::S2_cl1:
    case Hexagon::S2_clb:
    case Hexagon::S2_clbnorm:
    case Hexagon::S2_ct0:
    case Hexagon::S2_ct1:
    case Hexagon::S2_svsathb:
    case Hexagon::S2_svsathub:
    case Hexagon::S2_vsplatrb:
    case Hexagon::Y2_dctagr:
    case Hexagon::Y2_getimask:
    case Hexagon::Y2_iassignr:
    case Hexagon::Y2_icdatar:
    case Hexagon::Y2_ictagr:
    case Hexagon::Y2_tlbp:
    case Hexagon::Y4_l2tagr: {
      switch (OpNum) {
      case 1:
        // op: Rs32
        return 16;
      case 0:
        // op: Rd32
        return 0;
      }
      break;
    }
    case Hexagon::A2_sxtw:
    case Hexagon::F2_conv_sf2d:
    case Hexagon::F2_conv_sf2d_chop:
    case Hexagon::F2_conv_sf2df:
    case Hexagon::F2_conv_sf2ud:
    case Hexagon::F2_conv_sf2ud_chop:
    case Hexagon::F2_conv_uw2df:
    case Hexagon::F2_conv_w2df:
    case Hexagon::L2_deallocframe:
    case Hexagon::L4_loadd_aq:
    case Hexagon::L4_loadd_locked:
    case Hexagon::L4_return:
    case Hexagon::S2_vsplatrh:
    case Hexagon::S2_vsxtbh:
    case Hexagon::S2_vsxthw:
    case Hexagon::S2_vzxtbh:
    case Hexagon::S2_vzxthw:
    case Hexagon::S6_vsplatrbp:
    case Hexagon::Y2_tlbr: {
      switch (OpNum) {
      case 1:
        // op: Rs32
        return 16;
      case 0:
        // op: Rdd32
        return 0;
      }
      break;
    }
    case Hexagon::Y2_tfrsrcr: {
      switch (OpNum) {
      case 1:
        // op: Rs32
        return 16;
      case 0:
        // op: Sd128
        return 0;
      }
      break;
    }
    case Hexagon::A4_cmpbeq:
    case Hexagon::A4_cmpbgt:
    case Hexagon::A4_cmpbgtu:
    case Hexagon::A4_cmpheq:
    case Hexagon::A4_cmphgt:
    case Hexagon::A4_cmphgtu:
    case Hexagon::C2_bitsclr:
    case Hexagon::C2_bitsset:
    case Hexagon::C2_cmpeq:
    case Hexagon::C2_cmpgt:
    case Hexagon::C2_cmpgtu:
    case Hexagon::C4_cmplte:
    case Hexagon::C4_cmplteu:
    case Hexagon::C4_cmpneq:
    case Hexagon::C4_nbitsclr:
    case Hexagon::C4_nbitsset:
    case Hexagon::F2_sfcmpeq:
    case Hexagon::F2_sfcmpge:
    case Hexagon::F2_sfcmpgt:
    case Hexagon::F2_sfcmpuo:
    case Hexagon::S2_storew_locked:
    case Hexagon::S2_tstbit_r:
    case Hexagon::S4_ntstbit_r: {
      switch (OpNum) {
      case 1:
        // op: Rs32
        return 16;
      case 2:
        // op: Rt32
        return 8;
      case 0:
        // op: Pd4
        return 0;
      }
      break;
    }
    case Hexagon::A2_add:
    case Hexagon::A2_addsat:
    case Hexagon::A2_and:
    case Hexagon::A2_max:
    case Hexagon::A2_maxu:
    case Hexagon::A2_or:
    case Hexagon::A2_svaddh:
    case Hexagon::A2_svaddhs:
    case Hexagon::A2_svadduhs:
    case Hexagon::A2_svavgh:
    case Hexagon::A2_svavghs:
    case Hexagon::A2_xor:
    case Hexagon::A4_cround_rr:
    case Hexagon::A4_modwrapu:
    case Hexagon::A4_rcmpeq:
    case Hexagon::A4_rcmpneq:
    case Hexagon::A4_round_rr:
    case Hexagon::A4_round_rr_sat:
    case Hexagon::F2_sfadd:
    case Hexagon::F2_sffixupd:
    case Hexagon::F2_sffixupn:
    case Hexagon::F2_sfmax:
    case Hexagon::F2_sfmin:
    case Hexagon::F2_sfmpy:
    case Hexagon::F2_sfsub:
    case Hexagon::L4_loadw_phys:
    case Hexagon::M2_cmpyrs_s0:
    case Hexagon::M2_cmpyrs_s1:
    case Hexagon::M2_cmpyrsc_s0:
    case Hexagon::M2_cmpyrsc_s1:
    case Hexagon::M2_dpmpyss_rnd_s0:
    case Hexagon::M2_hmmpyh_rs1:
    case Hexagon::M2_hmmpyh_s1:
    case Hexagon::M2_hmmpyl_rs1:
    case Hexagon::M2_hmmpyl_s1:
    case Hexagon::M2_mpy_hh_s0:
    case Hexagon::M2_mpy_hh_s1:
    case Hexagon::M2_mpy_hl_s0:
    case Hexagon::M2_mpy_hl_s1:
    case Hexagon::M2_mpy_lh_s0:
    case Hexagon::M2_mpy_lh_s1:
    case Hexagon::M2_mpy_ll_s0:
    case Hexagon::M2_mpy_ll_s1:
    case Hexagon::M2_mpy_rnd_hh_s0:
    case Hexagon::M2_mpy_rnd_hh_s1:
    case Hexagon::M2_mpy_rnd_hl_s0:
    case Hexagon::M2_mpy_rnd_hl_s1:
    case Hexagon::M2_mpy_rnd_lh_s0:
    case Hexagon::M2_mpy_rnd_lh_s1:
    case Hexagon::M2_mpy_rnd_ll_s0:
    case Hexagon::M2_mpy_rnd_ll_s1:
    case Hexagon::M2_mpy_sat_hh_s0:
    case Hexagon::M2_mpy_sat_hh_s1:
    case Hexagon::M2_mpy_sat_hl_s0:
    case Hexagon::M2_mpy_sat_hl_s1:
    case Hexagon::M2_mpy_sat_lh_s0:
    case Hexagon::M2_mpy_sat_lh_s1:
    case Hexagon::M2_mpy_sat_ll_s0:
    case Hexagon::M2_mpy_sat_ll_s1:
    case Hexagon::M2_mpy_sat_rnd_hh_s0:
    case Hexagon::M2_mpy_sat_rnd_hh_s1:
    case Hexagon::M2_mpy_sat_rnd_hl_s0:
    case Hexagon::M2_mpy_sat_rnd_hl_s1:
    case Hexagon::M2_mpy_sat_rnd_lh_s0:
    case Hexagon::M2_mpy_sat_rnd_lh_s1:
    case Hexagon::M2_mpy_sat_rnd_ll_s0:
    case Hexagon::M2_mpy_sat_rnd_ll_s1:
    case Hexagon::M2_mpy_up:
    case Hexagon::M2_mpy_up_s1:
    case Hexagon::M2_mpy_up_s1_sat:
    case Hexagon::M2_mpyi:
    case Hexagon::M2_mpysu_up:
    case Hexagon::M2_mpyu_hh_s0:
    case Hexagon::M2_mpyu_hh_s1:
    case Hexagon::M2_mpyu_hl_s0:
    case Hexagon::M2_mpyu_hl_s1:
    case Hexagon::M2_mpyu_lh_s0:
    case Hexagon::M2_mpyu_lh_s1:
    case Hexagon::M2_mpyu_ll_s0:
    case Hexagon::M2_mpyu_ll_s1:
    case Hexagon::M2_mpyu_up:
    case Hexagon::M2_vmpy2s_s0pack:
    case Hexagon::M2_vmpy2s_s1pack:
    case Hexagon::S2_asl_r_r:
    case Hexagon::S2_asl_r_r_sat:
    case Hexagon::S2_asr_r_r:
    case Hexagon::S2_asr_r_r_sat:
    case Hexagon::S2_clrbit_r:
    case Hexagon::S2_lsl_r_r:
    case Hexagon::S2_lsr_r_r:
    case Hexagon::S2_setbit_r:
    case Hexagon::S2_togglebit_r:
    case Hexagon::S4_parity:
    case Hexagon::dep_A2_addsat: {
      switch (OpNum) {
      case 1:
        // op: Rs32
        return 16;
      case 2:
        // op: Rt32
        return 8;
      case 0:
        // op: Rd32
        return 0;
      }
      break;
    }
    case Hexagon::A2_combinew:
    case Hexagon::A4_bitsplit:
    case Hexagon::M2_cmpyi_s0:
    case Hexagon::M2_cmpyr_s0:
    case Hexagon::M2_cmpys_s0:
    case Hexagon::M2_cmpys_s1:
    case Hexagon::M2_cmpysc_s0:
    case Hexagon::M2_cmpysc_s1:
    case Hexagon::M2_dpmpyss_s0:
    case Hexagon::M2_dpmpyuu_s0:
    case Hexagon::M2_mpyd_hh_s0:
    case Hexagon::M2_mpyd_hh_s1:
    case Hexagon::M2_mpyd_hl_s0:
    case Hexagon::M2_mpyd_hl_s1:
    case Hexagon::M2_mpyd_lh_s0:
    case Hexagon::M2_mpyd_lh_s1:
    case Hexagon::M2_mpyd_ll_s0:
    case Hexagon::M2_mpyd_ll_s1:
    case Hexagon::M2_mpyd_rnd_hh_s0:
    case Hexagon::M2_mpyd_rnd_hh_s1:
    case Hexagon::M2_mpyd_rnd_hl_s0:
    case Hexagon::M2_mpyd_rnd_hl_s1:
    case Hexagon::M2_mpyd_rnd_lh_s0:
    case Hexagon::M2_mpyd_rnd_lh_s1:
    case Hexagon::M2_mpyd_rnd_ll_s0:
    case Hexagon::M2_mpyd_rnd_ll_s1:
    case Hexagon::M2_mpyud_hh_s0:
    case Hexagon::M2_mpyud_hh_s1:
    case Hexagon::M2_mpyud_hl_s0:
    case Hexagon::M2_mpyud_hl_s1:
    case Hexagon::M2_mpyud_lh_s0:
    case Hexagon::M2_mpyud_lh_s1:
    case Hexagon::M2_mpyud_ll_s0:
    case Hexagon::M2_mpyud_ll_s1:
    case Hexagon::M2_vmpy2s_s0:
    case Hexagon::M2_vmpy2s_s1:
    case Hexagon::M2_vmpy2su_s0:
    case Hexagon::M2_vmpy2su_s1:
    case Hexagon::M4_pmpyw:
    case Hexagon::M4_vpmpyh:
    case Hexagon::M5_vmpybsu:
    case Hexagon::M5_vmpybuu:
    case Hexagon::S2_packhl:
    case Hexagon::dep_S2_packhl: {
      switch (OpNum) {
      case 1:
        // op: Rs32
        return 16;
      case 2:
        // op: Rt32
        return 8;
      case 0:
        // op: Rdd32
        return 0;
      }
      break;
    }
    case Hexagon::S4_stored_locked: {
      switch (OpNum) {
      case 1:
        // op: Rs32
        return 16;
      case 2:
        // op: Rtt32
        return 8;
      case 0:
        // op: Pd4
        return 0;
      }
      break;
    }
    case Hexagon::S2_extractu_rp:
    case Hexagon::S4_extract_rp: {
      switch (OpNum) {
      case 1:
        // op: Rs32
        return 16;
      case 2:
        // op: Rtt32
        return 8;
      case 0:
        // op: Rd32
        return 0;
      }
      break;
    }
    case Hexagon::A4_tfrpcp: {
      switch (OpNum) {
      case 1:
        // op: Rss32
        return 16;
      case 0:
        // op: Cdd32
        return 0;
      }
      break;
    }
    case Hexagon::G4_tfrgpcp: {
      switch (OpNum) {
      case 1:
        // op: Rss32
        return 16;
      case 0:
        // op: Gdd32
        return 0;
      }
      break;
    }
    case Hexagon::A2_roundsat:
    case Hexagon::A2_sat:
    case Hexagon::F2_conv_d2sf:
    case Hexagon::F2_conv_df2sf:
    case Hexagon::F2_conv_df2uw:
    case Hexagon::F2_conv_df2uw_chop:
    case Hexagon::F2_conv_df2w:
    case Hexagon::F2_conv_df2w_chop:
    case Hexagon::F2_conv_ud2sf:
    case Hexagon::S2_cl0p:
    case Hexagon::S2_cl1p:
    case Hexagon::S2_clbp:
    case Hexagon::S2_ct0p:
    case Hexagon::S2_ct1p:
    case Hexagon::S2_vrndpackwh:
    case Hexagon::S2_vrndpackwhs:
    case Hexagon::S2_vsathb:
    case Hexagon::S2_vsathub:
    case Hexagon::S2_vsatwh:
    case Hexagon::S2_vsatwuh:
    case Hexagon::S2_vtrunehb:
    case Hexagon::S2_vtrunohb:
    case Hexagon::S4_clbpnorm:
    case Hexagon::S5_popcountp:
    case Hexagon::Y5_tlboc: {
      switch (OpNum) {
      case 1:
        // op: Rss32
        return 16;
      case 0:
        // op: Rd32
        return 0;
      }
      break;
    }
    case Hexagon::A2_absp:
    case Hexagon::A2_negp:
    case Hexagon::A2_notp:
    case Hexagon::A2_vabsh:
    case Hexagon::A2_vabshsat:
    case Hexagon::A2_vabsw:
    case Hexagon::A2_vabswsat:
    case Hexagon::A2_vconj:
    case Hexagon::F2_conv_d2df:
    case Hexagon::F2_conv_df2d:
    case Hexagon::F2_conv_df2d_chop:
    case Hexagon::F2_conv_df2ud:
    case Hexagon::F2_conv_df2ud_chop:
    case Hexagon::F2_conv_ud2df:
    case Hexagon::S2_brevp:
    case Hexagon::S2_deinterleave:
    case Hexagon::S2_interleave:
    case Hexagon::S2_vsathb_nopack:
    case Hexagon::S2_vsathub_nopack:
    case Hexagon::S2_vsatwh_nopack:
    case Hexagon::S2_vsatwuh_nopack: {
      switch (OpNum) {
      case 1:
        // op: Rss32
        return 16;
      case 0:
        // op: Rdd32
        return 0;
      }
      break;
    }
    case Hexagon::Y4_tfrspcp: {
      switch (OpNum) {
      case 1:
        // op: Rss32
        return 16;
      case 0:
        // op: Sdd128
        return 0;
      }
      break;
    }
    case Hexagon::A4_tlbmatch: {
      switch (OpNum) {
      case 1:
        // op: Rss32
        return 16;
      case 2:
        // op: Rt32
        return 8;
      case 0:
        // op: Pd4
        return 0;
      }
      break;
    }
    case Hexagon::M4_cmpyi_wh:
    case Hexagon::M4_cmpyi_whc:
    case Hexagon::M4_cmpyr_wh:
    case Hexagon::M4_cmpyr_whc:
    case Hexagon::S2_asr_r_svw_trun:
    case Hexagon::Y5_ctlbw: {
      switch (OpNum) {
      case 1:
        // op: Rss32
        return 16;
      case 2:
        // op: Rt32
        return 8;
      case 0:
        // op: Rd32
        return 0;
      }
      break;
    }
    case Hexagon::A7_croundd_rr:
    case Hexagon::S2_asl_r_p:
    case Hexagon::S2_asl_r_vh:
    case Hexagon::S2_asl_r_vw:
    case Hexagon::S2_asr_r_p:
    case Hexagon::S2_asr_r_vh:
    case Hexagon::S2_asr_r_vw:
    case Hexagon::S2_lsl_r_p:
    case Hexagon::S2_lsl_r_vh:
    case Hexagon::S2_lsl_r_vw:
    case Hexagon::S2_lsr_r_p:
    case Hexagon::S2_lsr_r_vh:
    case Hexagon::S2_lsr_r_vw:
    case Hexagon::S2_vcnegh:
    case Hexagon::S2_vcrotate: {
      switch (OpNum) {
      case 1:
        // op: Rss32
        return 16;
      case 2:
        // op: Rt32
        return 8;
      case 0:
        // op: Rdd32
        return 0;
      }
      break;
    }
    case Hexagon::A2_vcmpbeq:
    case Hexagon::A2_vcmpbgtu:
    case Hexagon::A2_vcmpheq:
    case Hexagon::A2_vcmphgt:
    case Hexagon::A2_vcmphgtu:
    case Hexagon::A2_vcmpweq:
    case Hexagon::A2_vcmpwgt:
    case Hexagon::A2_vcmpwgtu:
    case Hexagon::A4_boundscheck_hi:
    case Hexagon::A4_boundscheck_lo:
    case Hexagon::A4_vcmpbeq_any:
    case Hexagon::A4_vcmpbgt:
    case Hexagon::A6_vcmpbeq_notany:
    case Hexagon::C2_cmpeqp:
    case Hexagon::C2_cmpgtp:
    case Hexagon::C2_cmpgtup:
    case Hexagon::F2_dfcmpeq:
    case Hexagon::F2_dfcmpge:
    case Hexagon::F2_dfcmpgt:
    case Hexagon::F2_dfcmpuo: {
      switch (OpNum) {
      case 1:
        // op: Rss32
        return 16;
      case 2:
        // op: Rtt32
        return 8;
      case 0:
        // op: Pd4
        return 0;
      }
      break;
    }
    case Hexagon::A5_vaddhubs:
    case Hexagon::M2_vdmpyrs_s0:
    case Hexagon::M2_vdmpyrs_s1:
    case Hexagon::M2_vraddh:
    case Hexagon::M2_vradduh:
    case Hexagon::M2_vrcmpys_s1rp_h:
    case Hexagon::M2_vrcmpys_s1rp_l:
    case Hexagon::M7_wcmpyiw:
    case Hexagon::M7_wcmpyiw_rnd:
    case Hexagon::M7_wcmpyiwc:
    case Hexagon::M7_wcmpyiwc_rnd:
    case Hexagon::M7_wcmpyrw:
    case Hexagon::M7_wcmpyrw_rnd:
    case Hexagon::M7_wcmpyrwc:
    case Hexagon::M7_wcmpyrwc_rnd:
    case Hexagon::S2_parityp: {
      switch (OpNum) {
      case 1:
        // op: Rss32
        return 16;
      case 2:
        // op: Rtt32
        return 8;
      case 0:
        // op: Rd32
        return 0;
      }
      break;
    }
    case Hexagon::A2_addp:
    case Hexagon::A2_addpsat:
    case Hexagon::A2_addsph:
    case Hexagon::A2_addspl:
    case Hexagon::A2_andp:
    case Hexagon::A2_maxp:
    case Hexagon::A2_maxup:
    case Hexagon::A2_orp:
    case Hexagon::A2_vaddh:
    case Hexagon::A2_vaddhs:
    case Hexagon::A2_vaddub:
    case Hexagon::A2_vaddubs:
    case Hexagon::A2_vadduhs:
    case Hexagon::A2_vaddw:
    case Hexagon::A2_vaddws:
    case Hexagon::A2_vavgh:
    case Hexagon::A2_vavghcr:
    case Hexagon::A2_vavghr:
    case Hexagon::A2_vavgub:
    case Hexagon::A2_vavgubr:
    case Hexagon::A2_vavguh:
    case Hexagon::A2_vavguhr:
    case Hexagon::A2_vavguw:
    case Hexagon::A2_vavguwr:
    case Hexagon::A2_vavgw:
    case Hexagon::A2_vavgwcr:
    case Hexagon::A2_vavgwr:
    case Hexagon::A2_vraddub:
    case Hexagon::A2_vrsadub:
    case Hexagon::A2_xorp:
    case Hexagon::F2_dfadd:
    case Hexagon::F2_dfmax:
    case Hexagon::F2_dfmin:
    case Hexagon::F2_dfmpyfix:
    case Hexagon::F2_dfmpyll:
    case Hexagon::F2_dfsub:
    case Hexagon::M2_mmpyh_rs0:
    case Hexagon::M2_mmpyh_rs1:
    case Hexagon::M2_mmpyh_s0:
    case Hexagon::M2_mmpyh_s1:
    case Hexagon::M2_mmpyl_rs0:
    case Hexagon::M2_mmpyl_rs1:
    case Hexagon::M2_mmpyl_s0:
    case Hexagon::M2_mmpyl_s1:
    case Hexagon::M2_mmpyuh_rs0:
    case Hexagon::M2_mmpyuh_rs1:
    case Hexagon::M2_mmpyuh_s0:
    case Hexagon::M2_mmpyuh_s1:
    case Hexagon::M2_mmpyul_rs0:
    case Hexagon::M2_mmpyul_rs1:
    case Hexagon::M2_mmpyul_s0:
    case Hexagon::M2_mmpyul_s1:
    case Hexagon::M2_vcmpy_s0_sat_i:
    case Hexagon::M2_vcmpy_s0_sat_r:
    case Hexagon::M2_vcmpy_s1_sat_i:
    case Hexagon::M2_vcmpy_s1_sat_r:
    case Hexagon::M2_vdmpys_s0:
    case Hexagon::M2_vdmpys_s1:
    case Hexagon::M2_vmpy2es_s0:
    case Hexagon::M2_vmpy2es_s1:
    case Hexagon::M2_vrcmpyi_s0:
    case Hexagon::M2_vrcmpyi_s0c:
    case Hexagon::M2_vrcmpyr_s0:
    case Hexagon::M2_vrcmpyr_s0c:
    case Hexagon::M2_vrcmpys_s1_h:
    case Hexagon::M2_vrcmpys_s1_l:
    case Hexagon::M2_vrmpy_s0:
    case Hexagon::M4_vrmpyeh_s0:
    case Hexagon::M4_vrmpyeh_s1:
    case Hexagon::M4_vrmpyoh_s0:
    case Hexagon::M4_vrmpyoh_s1:
    case Hexagon::M5_vdmpybsu:
    case Hexagon::M5_vrmpybsu:
    case Hexagon::M5_vrmpybuu:
    case Hexagon::M7_dcmpyiw:
    case Hexagon::M7_dcmpyiwc:
    case Hexagon::M7_dcmpyrw:
    case Hexagon::M7_dcmpyrwc:
    case Hexagon::S2_cabacdecbin:
    case Hexagon::S2_extractup_rp:
    case Hexagon::S2_lfsp:
    case Hexagon::S2_shuffeb:
    case Hexagon::S2_shuffeh:
    case Hexagon::S2_vtrunewh:
    case Hexagon::S2_vtrunowh:
    case Hexagon::S4_extractp_rp:
    case Hexagon::S4_vxaddsubh:
    case Hexagon::S4_vxaddsubhr:
    case Hexagon::S4_vxaddsubw:
    case Hexagon::S4_vxsubaddh:
    case Hexagon::S4_vxsubaddhr:
    case Hexagon::S4_vxsubaddw:
    case Hexagon::S6_vtrunehb_ppp:
    case Hexagon::S6_vtrunohb_ppp: {
      switch (OpNum) {
      case 1:
        // op: Rss32
        return 16;
      case 2:
        // op: Rtt32
        return 8;
      case 0:
        // op: Rdd32
        return 0;
      }
      break;
    }
    case Hexagon::S2_vsplicerb: {
      switch (OpNum) {
      case 1:
        // op: Rss32
        return 16;
      case 2:
        // op: Rtt32
        return 8;
      case 3:
        // op: Pu4
        return 5;
      case 0:
        // op: Rdd32
        return 0;
      }
      break;
    }
    case Hexagon::V6_pred_scalar2:
    case Hexagon::V6_pred_scalar2v2: {
      switch (OpNum) {
      case 1:
        // op: Rt32
        return 16;
      case 0:
        // op: Qd4
        return 0;
      }
      break;
    }
    case Hexagon::V6_lvsplatb:
    case Hexagon::V6_lvsplath:
    case Hexagon::V6_lvsplatw:
    case Hexagon::V6_zextract: {
      switch (OpNum) {
      case 1:
        // op: Rt32
        return 16;
      case 0:
        // op: Vd32
        return 0;
      }
      break;
    }
    case Hexagon::A2_addh_h16_hh:
    case Hexagon::A2_addh_h16_hl:
    case Hexagon::A2_addh_h16_lh:
    case Hexagon::A2_addh_h16_ll:
    case Hexagon::A2_addh_h16_sat_hh:
    case Hexagon::A2_addh_h16_sat_hl:
    case Hexagon::A2_addh_h16_sat_lh:
    case Hexagon::A2_addh_h16_sat_ll:
    case Hexagon::A2_addh_l16_hl:
    case Hexagon::A2_addh_l16_ll:
    case Hexagon::A2_addh_l16_sat_hl:
    case Hexagon::A2_addh_l16_sat_ll:
    case Hexagon::A2_combine_hh:
    case Hexagon::A2_combine_hl:
    case Hexagon::A2_combine_lh:
    case Hexagon::A2_combine_ll:
    case Hexagon::A2_min:
    case Hexagon::A2_minu:
    case Hexagon::A2_sub:
    case Hexagon::A2_subh_h16_hh:
    case Hexagon::A2_subh_h16_hl:
    case Hexagon::A2_subh_h16_lh:
    case Hexagon::A2_subh_h16_ll:
    case Hexagon::A2_subh_h16_sat_hh:
    case Hexagon::A2_subh_h16_sat_hl:
    case Hexagon::A2_subh_h16_sat_lh:
    case Hexagon::A2_subh_h16_sat_ll:
    case Hexagon::A2_subh_l16_hl:
    case Hexagon::A2_subh_l16_ll:
    case Hexagon::A2_subh_l16_sat_hl:
    case Hexagon::A2_subh_l16_sat_ll:
    case Hexagon::A2_subsat:
    case Hexagon::A2_svnavgh:
    case Hexagon::A2_svsubh:
    case Hexagon::A2_svsubhs:
    case Hexagon::A2_svsubuhs:
    case Hexagon::A4_andn:
    case Hexagon::A4_orn:
    case Hexagon::dep_A2_subsat: {
      switch (OpNum) {
      case 1:
        // op: Rt32
        return 8;
      case 2:
        // op: Rs32
        return 16;
      case 0:
        // op: Rd32
        return 0;
      }
      break;
    }
    case Hexagon::A2_minp:
    case Hexagon::A2_minup:
    case Hexagon::A2_subp:
    case Hexagon::A2_vmaxb:
    case Hexagon::A2_vmaxh:
    case Hexagon::A2_vmaxub:
    case Hexagon::A2_vmaxuh:
    case Hexagon::A2_vmaxuw:
    case Hexagon::A2_vmaxw:
    case Hexagon::A2_vminb:
    case Hexagon::A2_vminh:
    case Hexagon::A2_vminub:
    case Hexagon::A2_vminuh:
    case Hexagon::A2_vminuw:
    case Hexagon::A2_vminw:
    case Hexagon::A2_vnavgh:
    case Hexagon::A2_vnavghcr:
    case Hexagon::A2_vnavghr:
    case Hexagon::A2_vnavgw:
    case Hexagon::A2_vnavgwcr:
    case Hexagon::A2_vnavgwr:
    case Hexagon::A2_vsubh:
    case Hexagon::A2_vsubhs:
    case Hexagon::A2_vsubub:
    case Hexagon::A2_vsububs:
    case Hexagon::A2_vsubuhs:
    case Hexagon::A2_vsubw:
    case Hexagon::A2_vsubws:
    case Hexagon::A4_andnp:
    case Hexagon::A4_ornp:
    case Hexagon::M2_vabsdiffh:
    case Hexagon::M2_vabsdiffw:
    case Hexagon::M6_vabsdiffb:
    case Hexagon::M6_vabsdiffub:
    case Hexagon::S2_shuffob:
    case Hexagon::S2_shuffoh: {
      switch (OpNum) {
      case 1:
        // op: Rtt32
        return 8;
      case 2:
        // op: Rss32
        return 16;
      case 0:
        // op: Rdd32
        return 0;
      }
      break;
    }
    case Hexagon::S2_valignrb: {
      switch (OpNum) {
      case 1:
        // op: Rtt32
        return 8;
      case 2:
        // op: Rss32
        return 16;
      case 3:
        // op: Pu4
        return 5;
      case 0:
        // op: Rdd32
        return 0;
      }
      break;
    }
    case Hexagon::M4_mpyrr_addr: {
      switch (OpNum) {
      case 1:
        // op: Ru32
        return 0;
      case 3:
        // op: Rs32
        return 16;
      case 0:
        // op: Ry32
        return 8;
      }
      break;
    }
    case Hexagon::Y2_tfrscrr: {
      switch (OpNum) {
      case 1:
        // op: Ss128
        return 16;
      case 0:
        // op: Rd32
        return 0;
      }
      break;
    }
    case Hexagon::Y4_tfrscpp: {
      switch (OpNum) {
      case 1:
        // op: Sss128
        return 16;
      case 0:
        // op: Rdd32
        return 0;
      }
      break;
    }
    case Hexagon::V6_vabs_hf:
    case Hexagon::V6_vabs_sf:
    case Hexagon::V6_vabsb:
    case Hexagon::V6_vabsb_sat:
    case Hexagon::V6_vabsh:
    case Hexagon::V6_vabsh_sat:
    case Hexagon::V6_vabsw:
    case Hexagon::V6_vabsw_sat:
    case Hexagon::V6_vassign:
    case Hexagon::V6_vassign_fp:
    case Hexagon::V6_vassign_tmp:
    case Hexagon::V6_vcl0h:
    case Hexagon::V6_vcl0w:
    case Hexagon::V6_vconv_h_hf:
    case Hexagon::V6_vconv_hf_h:
    case Hexagon::V6_vconv_hf_qf16:
    case Hexagon::V6_vconv_sf_qf32:
    case Hexagon::V6_vconv_sf_w:
    case Hexagon::V6_vconv_w_sf:
    case Hexagon::V6_vcvt_h_hf:
    case Hexagon::V6_vcvt_hf_h:
    case Hexagon::V6_vcvt_hf_uh:
    case Hexagon::V6_vcvt_uh_hf:
    case Hexagon::V6_vdealb:
    case Hexagon::V6_vdealh:
    case Hexagon::V6_vfneg_hf:
    case Hexagon::V6_vfneg_sf:
    case Hexagon::V6_vnormamth:
    case Hexagon::V6_vnormamtw:
    case Hexagon::V6_vnot:
    case Hexagon::V6_vpopcounth:
    case Hexagon::V6_vshuffb:
    case Hexagon::V6_vshuffh: {
      switch (OpNum) {
      case 1:
        // op: Vu32
        return 8;
      case 0:
        // op: Vd32
        return 0;
      }
      break;
    }
    case Hexagon::V6_vcvt_hf_b:
    case Hexagon::V6_vcvt_hf_ub:
    case Hexagon::V6_vcvt_sf_hf:
    case Hexagon::V6_vsb:
    case Hexagon::V6_vsh:
    case Hexagon::V6_vunpackb:
    case Hexagon::V6_vunpackh:
    case Hexagon::V6_vunpackub:
    case Hexagon::V6_vunpackuh:
    case Hexagon::V6_vzb:
    case Hexagon::V6_vzh: {
      switch (OpNum) {
      case 1:
        // op: Vu32
        return 8;
      case 0:
        // op: Vdd32
        return 0;
      }
      break;
    }
    case Hexagon::V6_extractw: {
      switch (OpNum) {
      case 1:
        // op: Vu32
        return 8;
      case 2:
        // op: Rs32
        return 16;
      case 0:
        // op: Rd32
        return 0;
      }
      break;
    }
    case Hexagon::V6_vandvrt: {
      switch (OpNum) {
      case 1:
        // op: Vu32
        return 8;
      case 2:
        // op: Rt32
        return 16;
      case 0:
        // op: Qd4
        return 0;
      }
      break;
    }
    case Hexagon::V6_vaslh:
    case Hexagon::V6_vaslw:
    case Hexagon::V6_vasrh:
    case Hexagon::V6_vasrw:
    case Hexagon::V6_vdmpybus:
    case Hexagon::V6_vdmpyhb:
    case Hexagon::V6_vdmpyhsat:
    case Hexagon::V6_vdmpyhsusat:
    case Hexagon::V6_vlsrb:
    case Hexagon::V6_vlsrh:
    case Hexagon::V6_vlsrw:
    case Hexagon::V6_vmpyhsrs:
    case Hexagon::V6_vmpyhss:
    case Hexagon::V6_vmpyihb:
    case Hexagon::V6_vmpyiwb:
    case Hexagon::V6_vmpyiwh:
    case Hexagon::V6_vmpyiwub:
    case Hexagon::V6_vmpyuhe:
    case Hexagon::V6_vrmpybus:
    case Hexagon::V6_vrmpyub:
    case Hexagon::V6_vror: {
      switch (OpNum) {
      case 1:
        // op: Vu32
        return 8;
      case 2:
        // op: Rt32
        return 16;
      case 0:
        // op: Vd32
        return 0;
      }
      break;
    }
    case Hexagon::V6_vmpybus:
    case Hexagon::V6_vmpyh:
    case Hexagon::V6_vmpyub:
    case Hexagon::V6_vmpyuh: {
      switch (OpNum) {
      case 1:
        // op: Vu32
        return 8;
      case 2:
        // op: Rt32
        return 16;
      case 0:
        // op: Vdd32
        return 0;
      }
      break;
    }
    case Hexagon::V6_vrmpyzbb_rt:
    case Hexagon::V6_vrmpyzbub_rt:
    case Hexagon::V6_vrmpyzcb_rt:
    case Hexagon::V6_vrmpyzcbs_rt:
    case Hexagon::V6_vrmpyznb_rt: {
      switch (OpNum) {
      case 1:
        // op: Vu32
        return 8;
      case 2:
        // op: Rt8
        return 16;
      case 0:
        // op: Vdddd32
        return 0;
      }
      break;
    }
    case Hexagon::V6_vlut4: {
      switch (OpNum) {
      case 1:
        // op: Vu32
        return 8;
      case 2:
        // op: Rtt32
        return 16;
      case 0:
        // op: Vd32
        return 0;
      }
      break;
    }
    case Hexagon::V6_vrmpybub_rtt:
    case Hexagon::V6_vrmpyub_rtt: {
      switch (OpNum) {
      case 1:
        // op: Vu32
        return 8;
      case 2:
        // op: Rtt32
        return 16;
      case 0:
        // op: Vdd32
        return 0;
      }
      break;
    }
    case Hexagon::V6_veqb:
    case Hexagon::V6_veqh:
    case Hexagon::V6_veqw:
    case Hexagon::V6_vgtb:
    case Hexagon::V6_vgtbf:
    case Hexagon::V6_vgth:
    case Hexagon::V6_vgthf:
    case Hexagon::V6_vgtsf:
    case Hexagon::V6_vgtub:
    case Hexagon::V6_vgtuh:
    case Hexagon::V6_vgtuw:
    case Hexagon::V6_vgtw: {
      switch (OpNum) {
      case 1:
        // op: Vu32
        return 8;
      case 2:
        // op: Vv32
        return 16;
      case 0:
        // op: Qd4
        return 0;
      }
      break;
    }
    case Hexagon::V6_vabsdiffh:
    case Hexagon::V6_vabsdiffub:
    case Hexagon::V6_vabsdiffuh:
    case Hexagon::V6_vabsdiffw:
    case Hexagon::V6_vadd_hf:
    case Hexagon::V6_vadd_hf_hf:
    case Hexagon::V6_vadd_qf16:
    case Hexagon::V6_vadd_qf16_mix:
    case Hexagon::V6_vadd_qf32:
    case Hexagon::V6_vadd_qf32_mix:
    case Hexagon::V6_vadd_sf:
    case Hexagon::V6_vadd_sf_sf:
    case Hexagon::V6_vaddb:
    case Hexagon::V6_vaddbsat:
    case Hexagon::V6_vaddclbh:
    case Hexagon::V6_vaddclbw:
    case Hexagon::V6_vaddh:
    case Hexagon::V6_vaddhsat:
    case Hexagon::V6_vaddubsat:
    case Hexagon::V6_vaddububb_sat:
    case Hexagon::V6_vadduhsat:
    case Hexagon::V6_vadduwsat:
    case Hexagon::V6_vaddw:
    case Hexagon::V6_vaddwsat:
    case Hexagon::V6_vand:
    case Hexagon::V6_vaslhv:
    case Hexagon::V6_vaslwv:
    case Hexagon::V6_vasrhv:
    case Hexagon::V6_vasrwv:
    case Hexagon::V6_vavgb:
    case Hexagon::V6_vavgbrnd:
    case Hexagon::V6_vavgh:
    case Hexagon::V6_vavghrnd:
    case Hexagon::V6_vavgub:
    case Hexagon::V6_vavgubrnd:
    case Hexagon::V6_vavguh:
    case Hexagon::V6_vavguhrnd:
    case Hexagon::V6_vavguw:
    case Hexagon::V6_vavguwrnd:
    case Hexagon::V6_vavgw:
    case Hexagon::V6_vavgwrnd:
    case Hexagon::V6_vcvt_b_hf:
    case Hexagon::V6_vcvt_bf_sf:
    case Hexagon::V6_vcvt_hf_sf:
    case Hexagon::V6_vcvt_ub_hf:
    case Hexagon::V6_vdealb4w:
    case Hexagon::V6_vdelta:
    case Hexagon::V6_vdmpy_sf_hf:
    case Hexagon::V6_vdmpyhvsat:
    case Hexagon::V6_vfmax_hf:
    case Hexagon::V6_vfmax_sf:
    case Hexagon::V6_vfmin_hf:
    case Hexagon::V6_vfmin_sf:
    case Hexagon::V6_vlsrhv:
    case Hexagon::V6_vlsrwv:
    case Hexagon::V6_vmax_bf:
    case Hexagon::V6_vmax_hf:
    case Hexagon::V6_vmax_sf:
    case Hexagon::V6_vmaxb:
    case Hexagon::V6_vmaxh:
    case Hexagon::V6_vmaxub:
    case Hexagon::V6_vmaxuh:
    case Hexagon::V6_vmaxw:
    case Hexagon::V6_vmin_bf:
    case Hexagon::V6_vmin_hf:
    case Hexagon::V6_vmin_sf:
    case Hexagon::V6_vminb:
    case Hexagon::V6_vminh:
    case Hexagon::V6_vminub:
    case Hexagon::V6_vminuh:
    case Hexagon::V6_vminw:
    case Hexagon::V6_vmpy_hf_hf:
    case Hexagon::V6_vmpy_qf16:
    case Hexagon::V6_vmpy_qf16_hf:
    case Hexagon::V6_vmpy_qf16_mix_hf:
    case Hexagon::V6_vmpy_qf32:
    case Hexagon::V6_vmpy_qf32_sf:
    case Hexagon::V6_vmpy_sf_sf:
    case Hexagon::V6_vmpyewuh:
    case Hexagon::V6_vmpyhvsrs:
    case Hexagon::V6_vmpyieoh:
    case Hexagon::V6_vmpyiewuh:
    case Hexagon::V6_vmpyih:
    case Hexagon::V6_vmpyiowh:
    case Hexagon::V6_vmpyowh:
    case Hexagon::V6_vmpyowh_rnd:
    case Hexagon::V6_vmpyuhvs:
    case Hexagon::V6_vnavgb:
    case Hexagon::V6_vnavgh:
    case Hexagon::V6_vnavgub:
    case Hexagon::V6_vnavgw:
    case Hexagon::V6_vor:
    case Hexagon::V6_vpackeb:
    case Hexagon::V6_vpackeh:
    case Hexagon::V6_vpackhb_sat:
    case Hexagon::V6_vpackhub_sat:
    case Hexagon::V6_vpackob:
    case Hexagon::V6_vpackoh:
    case Hexagon::V6_vpackwh_sat:
    case Hexagon::V6_vpackwuh_sat:
    case Hexagon::V6_vrdelta:
    case Hexagon::V6_vrmpybusv:
    case Hexagon::V6_vrmpybv:
    case Hexagon::V6_vrmpyubv:
    case Hexagon::V6_vrotr:
    case Hexagon::V6_vroundhb:
    case Hexagon::V6_vroundhub:
    case Hexagon::V6_vrounduhub:
    case Hexagon::V6_vrounduwuh:
    case Hexagon::V6_vroundwh:
    case Hexagon::V6_vroundwuh:
    case Hexagon::V6_vsatdw:
    case Hexagon::V6_vsathub:
    case Hexagon::V6_vsatuwuh:
    case Hexagon::V6_vsatwh:
    case Hexagon::V6_vshufeh:
    case Hexagon::V6_vshuffeb:
    case Hexagon::V6_vshuffob:
    case Hexagon::V6_vshufoh:
    case Hexagon::V6_vsub_hf:
    case Hexagon::V6_vsub_hf_hf:
    case Hexagon::V6_vsub_qf16:
    case Hexagon::V6_vsub_qf16_mix:
    case Hexagon::V6_vsub_qf32:
    case Hexagon::V6_vsub_qf32_mix:
    case Hexagon::V6_vsub_sf:
    case Hexagon::V6_vsub_sf_sf:
    case Hexagon::V6_vsubb:
    case Hexagon::V6_vsubbsat:
    case Hexagon::V6_vsubh:
    case Hexagon::V6_vsubhsat:
    case Hexagon::V6_vsububsat:
    case Hexagon::V6_vsubububb_sat:
    case Hexagon::V6_vsubuhsat:
    case Hexagon::V6_vsubuwsat:
    case Hexagon::V6_vsubw:
    case Hexagon::V6_vsubwsat:
    case Hexagon::V6_vxor: {
      switch (OpNum) {
      case 1:
        // op: Vu32
        return 8;
      case 2:
        // op: Vv32
        return 16;
      case 0:
        // op: Vd32
        return 0;
      }
      break;
    }
    case Hexagon::V6_vadd_sf_bf:
    case Hexagon::V6_vadd_sf_hf:
    case Hexagon::V6_vaddhw:
    case Hexagon::V6_vaddubh:
    case Hexagon::V6_vadduhw:
    case Hexagon::V6_vcombine:
    case Hexagon::V6_vcombine_tmp:
    case Hexagon::V6_vmpy_qf32_hf:
    case Hexagon::V6_vmpy_qf32_mix_hf:
    case Hexagon::V6_vmpy_qf32_qf16:
    case Hexagon::V6_vmpy_sf_bf:
    case Hexagon::V6_vmpy_sf_hf:
    case Hexagon::V6_vmpybusv:
    case Hexagon::V6_vmpybv:
    case Hexagon::V6_vmpyewuh_64:
    case Hexagon::V6_vmpyhus:
    case Hexagon::V6_vmpyhv:
    case Hexagon::V6_vmpyubv:
    case Hexagon::V6_vmpyuhv:
    case Hexagon::V6_vshufoeb:
    case Hexagon::V6_vshufoeh:
    case Hexagon::V6_vsub_sf_bf:
    case Hexagon::V6_vsub_sf_hf:
    case Hexagon::V6_vsubhw:
    case Hexagon::V6_vsububh:
    case Hexagon::V6_vsubuhw: {
      switch (OpNum) {
      case 1:
        // op: Vu32
        return 8;
      case 2:
        // op: Vv32
        return 16;
      case 0:
        // op: Vdd32
        return 0;
      }
      break;
    }
    case Hexagon::V6_vaddcarrysat: {
      switch (OpNum) {
      case 1:
        // op: Vu32
        return 8;
      case 2:
        // op: Vv32
        return 16;
      case 3:
        // op: Qs4
        return 5;
      case 0:
        // op: Vd32
        return 0;
      }
      break;
    }
    case Hexagon::V6_valignb:
    case Hexagon::V6_vasrhbrndsat:
    case Hexagon::V6_vasrhbsat:
    case Hexagon::V6_vasrhubrndsat:
    case Hexagon::V6_vasrhubsat:
    case Hexagon::V6_vasruhubrndsat:
    case Hexagon::V6_vasruhubsat:
    case Hexagon::V6_vasruwuhrndsat:
    case Hexagon::V6_vasruwuhsat:
    case Hexagon::V6_vasrwh:
    case Hexagon::V6_vasrwhrndsat:
    case Hexagon::V6_vasrwhsat:
    case Hexagon::V6_vasrwuhrndsat:
    case Hexagon::V6_vasrwuhsat:
    case Hexagon::V6_vlalignb:
    case Hexagon::V6_vlutvvb:
    case Hexagon::V6_vlutvvb_nm: {
      switch (OpNum) {
      case 1:
        // op: Vu32
        return 8;
      case 2:
        // op: Vv32
        return 19;
      case 3:
        // op: Rt8
        return 16;
      case 0:
        // op: Vd32
        return 0;
      }
      break;
    }
    case Hexagon::V6_vdealvdd:
    case Hexagon::V6_vlutvwh:
    case Hexagon::V6_vlutvwh_nm:
    case Hexagon::V6_vshuffvdd: {
      switch (OpNum) {
      case 1:
        // op: Vu32
        return 8;
      case 2:
        // op: Vv32
        return 19;
      case 3:
        // op: Rt8
        return 16;
      case 0:
        // op: Vdd32
        return 0;
      }
      break;
    }
    case Hexagon::V6_vconv_hf_qf32: {
      switch (OpNum) {
      case 1:
        // op: Vuu32
        return 8;
      case 0:
        // op: Vd32
        return 0;
      }
      break;
    }
    case Hexagon::V6_vdmpyhisat:
    case Hexagon::V6_vdmpyhsuisat: {
      switch (OpNum) {
      case 1:
        // op: Vuu32
        return 8;
      case 2:
        // op: Rt32
        return 16;
      case 0:
        // op: Vd32
        return 0;
      }
      break;
    }
    case Hexagon::V6_vdmpybus_dv:
    case Hexagon::V6_vdmpyhb_dv:
    case Hexagon::V6_vdsaduh:
    case Hexagon::V6_vmpabus:
    case Hexagon::V6_vmpabuu:
    case Hexagon::V6_vmpahb:
    case Hexagon::V6_vmpauhb:
    case Hexagon::V6_vtmpyb:
    case Hexagon::V6_vtmpybus:
    case Hexagon::V6_vtmpyhb: {
      switch (OpNum) {
      case 1:
        // op: Vuu32
        return 8;
      case 2:
        // op: Rt32
        return 16;
      case 0:
        // op: Vdd32
        return 0;
      }
      break;
    }
    case Hexagon::V6_vasrvuhubrndsat:
    case Hexagon::V6_vasrvuhubsat:
    case Hexagon::V6_vasrvwuhrndsat:
    case Hexagon::V6_vasrvwuhsat: {
      switch (OpNum) {
      case 1:
        // op: Vuu32
        return 8;
      case 2:
        // op: Vv32
        return 16;
      case 0:
        // op: Vd32
        return 0;
      }
      break;
    }
    case Hexagon::V6_vaddb_dv:
    case Hexagon::V6_vaddbsat_dv:
    case Hexagon::V6_vaddh_dv:
    case Hexagon::V6_vaddhsat_dv:
    case Hexagon::V6_vaddubsat_dv:
    case Hexagon::V6_vadduhsat_dv:
    case Hexagon::V6_vadduwsat_dv:
    case Hexagon::V6_vaddw_dv:
    case Hexagon::V6_vaddwsat_dv:
    case Hexagon::V6_vmpabusv:
    case Hexagon::V6_vmpabuuv:
    case Hexagon::V6_vsubb_dv:
    case Hexagon::V6_vsubbsat_dv:
    case Hexagon::V6_vsubh_dv:
    case Hexagon::V6_vsubhsat_dv:
    case Hexagon::V6_vsububsat_dv:
    case Hexagon::V6_vsubuhsat_dv:
    case Hexagon::V6_vsubuwsat_dv:
    case Hexagon::V6_vsubw_dv:
    case Hexagon::V6_vsubwsat_dv: {
      switch (OpNum) {
      case 1:
        // op: Vuu32
        return 8;
      case 2:
        // op: Vvv32
        return 16;
      case 0:
        // op: Vdd32
        return 0;
      }
      break;
    }
    case Hexagon::L4_loadbsw2_ap:
    case Hexagon::L4_loadbzw2_ap:
    case Hexagon::L4_loadrb_ap:
    case Hexagon::L4_loadrh_ap:
    case Hexagon::L4_loadri_ap:
    case Hexagon::L4_loadrub_ap:
    case Hexagon::L4_loadruh_ap: {
      switch (OpNum) {
      case 2:
        // op: II
        return 5;
      case 0:
        // op: Rd32
        return 0;
      case 1:
        // op: Re32
        return 16;
      }
      break;
    }
    case Hexagon::L4_loadbsw4_ap:
    case Hexagon::L4_loadbzw4_ap:
    case Hexagon::L4_loadrd_ap: {
      switch (OpNum) {
      case 2:
        // op: II
        return 5;
      case 0:
        // op: Rdd32
        return 0;
      case 1:
        // op: Re32
        return 16;
      }
      break;
    }
    case Hexagon::A2_tfrih:
    case Hexagon::A2_tfril:
    case Hexagon::S2_allocframe: {
      switch (OpNum) {
      case 2:
        // op: Ii
        return 0;
      case 0:
        // op: Rx32
        return 16;
      }
      break;
    }
    case Hexagon::J4_cmpeq_f_jumpnv_nt:
    case Hexagon::J4_cmpeq_f_jumpnv_t:
    case Hexagon::J4_cmpeq_t_jumpnv_nt:
    case Hexagon::J4_cmpeq_t_jumpnv_t:
    case Hexagon::J4_cmpgt_f_jumpnv_nt:
    case Hexagon::J4_cmpgt_f_jumpnv_t:
    case Hexagon::J4_cmpgt_t_jumpnv_nt:
    case Hexagon::J4_cmpgt_t_jumpnv_t:
    case Hexagon::J4_cmpgtu_f_jumpnv_nt:
    case Hexagon::J4_cmpgtu_f_jumpnv_t:
    case Hexagon::J4_cmpgtu_t_jumpnv_nt:
    case Hexagon::J4_cmpgtu_t_jumpnv_t: {
      switch (OpNum) {
      case 2:
        // op: Ii
        return 1;
      case 0:
        // op: Ns8
        return 16;
      case 1:
        // op: Rt32
        return 8;
      }
      break;
    }
    case Hexagon::J4_cmpeqn1_f_jumpnv_nt:
    case Hexagon::J4_cmpeqn1_f_jumpnv_t:
    case Hexagon::J4_cmpeqn1_t_jumpnv_nt:
    case Hexagon::J4_cmpeqn1_t_jumpnv_t:
    case Hexagon::J4_cmpgtn1_f_jumpnv_nt:
    case Hexagon::J4_cmpgtn1_f_jumpnv_t:
    case Hexagon::J4_cmpgtn1_t_jumpnv_nt:
    case Hexagon::J4_cmpgtn1_t_jumpnv_t: {
      switch (OpNum) {
      case 2:
        // op: Ii
        return 1;
      case 0:
        // op: Ns8
        return 16;
      }
      break;
    }
    case Hexagon::J4_cmpeq_fp0_jump_nt:
    case Hexagon::J4_cmpeq_fp0_jump_t:
    case Hexagon::J4_cmpeq_fp1_jump_nt:
    case Hexagon::J4_cmpeq_fp1_jump_t:
    case Hexagon::J4_cmpeq_tp0_jump_nt:
    case Hexagon::J4_cmpeq_tp0_jump_t:
    case Hexagon::J4_cmpeq_tp1_jump_nt:
    case Hexagon::J4_cmpeq_tp1_jump_t:
    case Hexagon::J4_cmpgt_fp0_jump_nt:
    case Hexagon::J4_cmpgt_fp0_jump_t:
    case Hexagon::J4_cmpgt_fp1_jump_nt:
    case Hexagon::J4_cmpgt_fp1_jump_t:
    case Hexagon::J4_cmpgt_tp0_jump_nt:
    case Hexagon::J4_cmpgt_tp0_jump_t:
    case Hexagon::J4_cmpgt_tp1_jump_nt:
    case Hexagon::J4_cmpgt_tp1_jump_t:
    case Hexagon::J4_cmpgtu_fp0_jump_nt:
    case Hexagon::J4_cmpgtu_fp0_jump_t:
    case Hexagon::J4_cmpgtu_fp1_jump_nt:
    case Hexagon::J4_cmpgtu_fp1_jump_t:
    case Hexagon::J4_cmpgtu_tp0_jump_nt:
    case Hexagon::J4_cmpgtu_tp0_jump_t:
    case Hexagon::J4_cmpgtu_tp1_jump_nt:
    case Hexagon::J4_cmpgtu_tp1_jump_t: {
      switch (OpNum) {
      case 2:
        // op: Ii
        return 1;
      case 0:
        // op: Rs16
        return 16;
      case 1:
        // op: Rt16
        return 8;
      }
      break;
    }
    case Hexagon::J4_cmpeqn1_fp0_jump_nt:
    case Hexagon::J4_cmpeqn1_fp0_jump_t:
    case Hexagon::J4_cmpeqn1_fp1_jump_nt:
    case Hexagon::J4_cmpeqn1_fp1_jump_t:
    case Hexagon::J4_cmpeqn1_tp0_jump_nt:
    case Hexagon::J4_cmpeqn1_tp0_jump_t:
    case Hexagon::J4_cmpeqn1_tp1_jump_nt:
    case Hexagon::J4_cmpeqn1_tp1_jump_t:
    case Hexagon::J4_cmpgtn1_fp0_jump_nt:
    case Hexagon::J4_cmpgtn1_fp0_jump_t:
    case Hexagon::J4_cmpgtn1_fp1_jump_nt:
    case Hexagon::J4_cmpgtn1_fp1_jump_t:
    case Hexagon::J4_cmpgtn1_tp0_jump_nt:
    case Hexagon::J4_cmpgtn1_tp0_jump_t:
    case Hexagon::J4_cmpgtn1_tp1_jump_nt:
    case Hexagon::J4_cmpgtn1_tp1_jump_t: {
      switch (OpNum) {
      case 2:
        // op: Ii
        return 1;
      case 0:
        // op: Rs16
        return 16;
      }
      break;
    }
    case Hexagon::J4_cmplt_f_jumpnv_nt:
    case Hexagon::J4_cmplt_f_jumpnv_t:
    case Hexagon::J4_cmplt_t_jumpnv_nt:
    case Hexagon::J4_cmplt_t_jumpnv_t:
    case Hexagon::J4_cmpltu_f_jumpnv_nt:
    case Hexagon::J4_cmpltu_f_jumpnv_t:
    case Hexagon::J4_cmpltu_t_jumpnv_nt:
    case Hexagon::J4_cmpltu_t_jumpnv_t: {
      switch (OpNum) {
      case 2:
        // op: Ii
        return 1;
      case 0:
        // op: Rt32
        return 8;
      case 1:
        // op: Ns8
        return 16;
      }
      break;
    }
    case Hexagon::J4_jumpsetr: {
      switch (OpNum) {
      case 2:
        // op: Ii
        return 1;
      case 1:
        // op: Rs16
        return 16;
      case 0:
        // op: Rd16
        return 8;
      }
      break;
    }
    case Hexagon::J2_trap1: {
      switch (OpNum) {
      case 2:
        // op: Ii
        return 2;
      case 0:
        // op: Rx32
        return 16;
      }
      break;
    }
    case Hexagon::S2_pstorerbnewf_io:
    case Hexagon::S2_pstorerbnewt_io:
    case Hexagon::S2_pstorerhnewf_io:
    case Hexagon::S2_pstorerhnewt_io:
    case Hexagon::S2_pstorerinewf_io:
    case Hexagon::S2_pstorerinewt_io:
    case Hexagon::S4_pstorerbnewfnew_io:
    case Hexagon::S4_pstorerbnewtnew_io:
    case Hexagon::S4_pstorerhnewfnew_io:
    case Hexagon::S4_pstorerhnewtnew_io:
    case Hexagon::S4_pstorerinewfnew_io:
    case Hexagon::S4_pstorerinewtnew_io: {
      switch (OpNum) {
      case 2:
        // op: Ii
        return 3;
      case 0:
        // op: Pv4
        return 0;
      case 1:
        // op: Rs32
        return 16;
      case 3:
        // op: Nt8
        return 8;
      }
      break;
    }
    case Hexagon::S2_pstorerbf_io:
    case Hexagon::S2_pstorerbt_io:
    case Hexagon::S2_pstorerff_io:
    case Hexagon::S2_pstorerft_io:
    case Hexagon::S2_pstorerhf_io:
    case Hexagon::S2_pstorerht_io:
    case Hexagon::S2_pstorerif_io:
    case Hexagon::S2_pstorerit_io:
    case Hexagon::S4_pstorerbfnew_io:
    case Hexagon::S4_pstorerbtnew_io:
    case Hexagon::S4_pstorerffnew_io:
    case Hexagon::S4_pstorerftnew_io:
    case Hexagon::S4_pstorerhfnew_io:
    case Hexagon::S4_pstorerhtnew_io:
    case Hexagon::S4_pstorerifnew_io:
    case Hexagon::S4_pstoreritnew_io: {
      switch (OpNum) {
      case 2:
        // op: Ii
        return 3;
      case 0:
        // op: Pv4
        return 0;
      case 1:
        // op: Rs32
        return 16;
      case 3:
        // op: Rt32
        return 8;
      }
      break;
    }
    case Hexagon::S2_pstorerdf_io:
    case Hexagon::S2_pstorerdt_io:
    case Hexagon::S4_pstorerdfnew_io:
    case Hexagon::S4_pstorerdtnew_io: {
      switch (OpNum) {
      case 2:
        // op: Ii
        return 3;
      case 0:
        // op: Pv4
        return 0;
      case 1:
        // op: Rs32
        return 16;
      case 3:
        // op: Rtt32
        return 8;
      }
      break;
    }
    case Hexagon::S2_storerbnew_pci:
    case Hexagon::S2_storerhnew_pci:
    case Hexagon::S2_storerinew_pci: {
      switch (OpNum) {
      case 2:
        // op: Ii
        return 3;
      case 3:
        // op: Mu2
        return 13;
      case 4:
        // op: Nt8
        return 8;
      case 0:
        // op: Rx32
        return 16;
      }
      break;
    }
    case Hexagon::S2_storerb_pci:
    case Hexagon::S2_storerf_pci:
    case Hexagon::S2_storerh_pci:
    case Hexagon::S2_storeri_pci: {
      switch (OpNum) {
      case 2:
        // op: Ii
        return 3;
      case 3:
        // op: Mu2
        return 13;
      case 4:
        // op: Rt32
        return 8;
      case 0:
        // op: Rx32
        return 16;
      }
      break;
    }
    case Hexagon::S2_storerd_pci: {
      switch (OpNum) {
      case 2:
        // op: Ii
        return 3;
      case 3:
        // op: Mu2
        return 13;
      case 4:
        // op: Rtt32
        return 8;
      case 0:
        // op: Rx32
        return 16;
      }
      break;
    }
    case Hexagon::S2_storerbnew_pi:
    case Hexagon::S2_storerhnew_pi:
    case Hexagon::S2_storerinew_pi: {
      switch (OpNum) {
      case 2:
        // op: Ii
        return 3;
      case 3:
        // op: Nt8
        return 8;
      case 0:
        // op: Rx32
        return 16;
      }
      break;
    }
    case Hexagon::S2_storerb_pi:
    case Hexagon::S2_storerf_pi:
    case Hexagon::S2_storerh_pi:
    case Hexagon::S2_storeri_pi: {
      switch (OpNum) {
      case 2:
        // op: Ii
        return 3;
      case 3:
        // op: Rt32
        return 8;
      case 0:
        // op: Rx32
        return 16;
      }
      break;
    }
    case Hexagon::S2_storerd_pi: {
      switch (OpNum) {
      case 2:
        // op: Ii
        return 3;
      case 3:
        // op: Rtt32
        return 8;
      case 0:
        // op: Rx32
        return 16;
      }
      break;
    }
    case Hexagon::SA1_addi: {
      switch (OpNum) {
      case 2:
        // op: Ii
        return 4;
      case 0:
        // op: Rx16
        return 0;
      }
      break;
    }
    case Hexagon::C2_cmoveif:
    case Hexagon::C2_cmoveit:
    case Hexagon::C2_cmovenewif:
    case Hexagon::C2_cmovenewit: {
      switch (OpNum) {
      case 2:
        // op: Ii
        return 5;
      case 1:
        // op: Pu4
        return 21;
      case 0:
        // op: Rd32
        return 0;
      }
      break;
    }
    case Hexagon::C2_muxri: {
      switch (OpNum) {
      case 2:
        // op: Ii
        return 5;
      case 1:
        // op: Pu4
        return 21;
      case 3:
        // op: Rs32
        return 16;
      case 0:
        // op: Rd32
        return 0;
      }
      break;
    }
    case Hexagon::A4_cmpbeqi:
    case Hexagon::A4_cmpbgti:
    case Hexagon::A4_cmpbgtui:
    case Hexagon::A4_cmpheqi:
    case Hexagon::A4_cmphgti:
    case Hexagon::A4_cmphgtui:
    case Hexagon::C2_cmpeqi:
    case Hexagon::C2_cmpgti:
    case Hexagon::C2_cmpgtui:
    case Hexagon::C4_cmpltei:
    case Hexagon::C4_cmplteui:
    case Hexagon::C4_cmpneqi: {
      switch (OpNum) {
      case 2:
        // op: Ii
        return 5;
      case 1:
        // op: Rs32
        return 16;
      case 0:
        // op: Pd4
        return 0;
      }
      break;
    }
    case Hexagon::A2_addi:
    case Hexagon::A2_andir:
    case Hexagon::A2_orir:
    case Hexagon::A4_rcmpeqi:
    case Hexagon::A4_rcmpneqi:
    case Hexagon::L2_loadbsw2_io:
    case Hexagon::L2_loadbzw2_io:
    case Hexagon::L2_loadrb_io:
    case Hexagon::L2_loadrh_io:
    case Hexagon::L2_loadri_io:
    case Hexagon::L2_loadrub_io:
    case Hexagon::L2_loadruh_io:
    case Hexagon::M2_mpysin:
    case Hexagon::M2_mpysip: {
      switch (OpNum) {
      case 2:
        // op: Ii
        return 5;
      case 1:
        // op: Rs32
        return 16;
      case 0:
        // op: Rd32
        return 0;
      }
      break;
    }
    case Hexagon::A4_combineri:
    case Hexagon::L2_loadbsw4_io:
    case Hexagon::L2_loadbzw4_io:
    case Hexagon::L2_loadrd_io: {
      switch (OpNum) {
      case 2:
        // op: Ii
        return 5;
      case 1:
        // op: Rs32
        return 16;
      case 0:
        // op: Rdd32
        return 0;
      }
      break;
    }
    case Hexagon::S4_subaddi: {
      switch (OpNum) {
      case 2:
        // op: Ii
        return 5;
      case 1:
        // op: Rs32
        return 16;
      case 3:
        // op: Ru32
        return 0;
      case 0:
        // op: Rd32
        return 8;
      }
      break;
    }
    case Hexagon::A4_vcmpbeqi:
    case Hexagon::A4_vcmpbgti:
    case Hexagon::A4_vcmpbgtui:
    case Hexagon::A4_vcmpheqi:
    case Hexagon::A4_vcmphgti:
    case Hexagon::A4_vcmphgtui:
    case Hexagon::A4_vcmpweqi:
    case Hexagon::A4_vcmpwgti:
    case Hexagon::A4_vcmpwgtui:
    case Hexagon::F2_dfclass: {
      switch (OpNum) {
      case 2:
        // op: Ii
        return 5;
      case 1:
        // op: Rss32
        return 16;
      case 0:
        // op: Pd4
        return 0;
      }
      break;
    }
    case Hexagon::M4_mpyri_addr_u2: {
      switch (OpNum) {
      case 2:
        // op: Ii
        return 5;
      case 1:
        // op: Ru32
        return 0;
      case 3:
        // op: Rs32
        return 16;
      case 0:
        // op: Rd32
        return 8;
      }
      break;
    }
    case Hexagon::C2_muxii: {
      switch (OpNum) {
      case 2:
        // op: Ii
        return 5;
      case 3:
        // op: II
        return 13;
      case 1:
        // op: Pu4
        return 23;
      case 0:
        // op: Rd32
        return 0;
      }
      break;
    }
    case Hexagon::S4_storerbnew_rr:
    case Hexagon::S4_storerhnew_rr:
    case Hexagon::S4_storerinew_rr: {
      switch (OpNum) {
      case 2:
        // op: Ii
        return 7;
      case 0:
        // op: Rs32
        return 16;
      case 1:
        // op: Ru32
        return 8;
      case 3:
        // op: Nt8
        return 0;
      }
      break;
    }
    case Hexagon::S4_storerb_rr:
    case Hexagon::S4_storerf_rr:
    case Hexagon::S4_storerh_rr:
    case Hexagon::S4_storeri_rr: {
      switch (OpNum) {
      case 2:
        // op: Ii
        return 7;
      case 0:
        // op: Rs32
        return 16;
      case 1:
        // op: Ru32
        return 8;
      case 3:
        // op: Rt32
        return 0;
      }
      break;
    }
    case Hexagon::S4_storerd_rr: {
      switch (OpNum) {
      case 2:
        // op: Ii
        return 7;
      case 0:
        // op: Rs32
        return 16;
      case 1:
        // op: Ru32
        return 8;
      case 3:
        // op: Rtt32
        return 0;
      }
      break;
    }
    case Hexagon::S4_storeirbf_io:
    case Hexagon::S4_storeirbfnew_io:
    case Hexagon::S4_storeirbt_io:
    case Hexagon::S4_storeirbtnew_io:
    case Hexagon::S4_storeirhf_io:
    case Hexagon::S4_storeirhfnew_io:
    case Hexagon::S4_storeirht_io:
    case Hexagon::S4_storeirhtnew_io:
    case Hexagon::S4_storeirif_io:
    case Hexagon::S4_storeirifnew_io:
    case Hexagon::S4_storeirit_io:
    case Hexagon::S4_storeiritnew_io: {
      switch (OpNum) {
      case 2:
        // op: Ii
        return 7;
      case 3:
        // op: II
        return 0;
      case 0:
        // op: Pv4
        return 5;
      case 1:
        // op: Rs32
        return 16;
      }
      break;
    }
    case Hexagon::L4_loadbsw2_ur:
    case Hexagon::L4_loadbzw2_ur:
    case Hexagon::L4_loadrb_ur:
    case Hexagon::L4_loadrh_ur:
    case Hexagon::L4_loadri_ur:
    case Hexagon::L4_loadrub_ur:
    case Hexagon::L4_loadruh_ur: {
      switch (OpNum) {
      case 2:
        // op: Ii
        return 7;
      case 3:
        // op: II
        return 5;
      case 1:
        // op: Rt32
        return 16;
      case 0:
        // op: Rd32
        return 0;
      }
      break;
    }
    case Hexagon::L4_loadbsw4_ur:
    case Hexagon::L4_loadbzw4_ur:
    case Hexagon::L4_loadrd_ur: {
      switch (OpNum) {
      case 2:
        // op: Ii
        return 7;
      case 3:
        // op: II
        return 5;
      case 1:
        // op: Rt32
        return 16;
      case 0:
        // op: Rdd32
        return 0;
      }
      break;
    }
    case Hexagon::V6_vS32b_new_npred_ai:
    case Hexagon::V6_vS32b_new_pred_ai:
    case Hexagon::V6_vS32b_nt_new_npred_ai:
    case Hexagon::V6_vS32b_nt_new_pred_ai: {
      switch (OpNum) {
      case 2:
        // op: Ii
        return 8;
      case 0:
        // op: Pv4
        return 11;
      case 1:
        // op: Rt32
        return 16;
      case 3:
        // op: Os8
        return 0;
      }
      break;
    }
    case Hexagon::V6_vS32Ub_npred_ai:
    case Hexagon::V6_vS32Ub_pred_ai:
    case Hexagon::V6_vS32b_npred_ai:
    case Hexagon::V6_vS32b_nt_npred_ai:
    case Hexagon::V6_vS32b_nt_pred_ai:
    case Hexagon::V6_vS32b_pred_ai: {
      switch (OpNum) {
      case 2:
        // op: Ii
        return 8;
      case 0:
        // op: Pv4
        return 11;
      case 1:
        // op: Rt32
        return 16;
      case 3:
        // op: Vs32
        return 0;
      }
      break;
    }
    case Hexagon::V6_zLd_pred_ai: {
      switch (OpNum) {
      case 2:
        // op: Ii
        return 8;
      case 0:
        // op: Pv4
        return 11;
      case 1:
        // op: Rt32
        return 16;
      }
      break;
    }
    case Hexagon::V6_vS32b_nqpred_ai:
    case Hexagon::V6_vS32b_nt_nqpred_ai:
    case Hexagon::V6_vS32b_nt_qpred_ai:
    case Hexagon::V6_vS32b_qpred_ai: {
      switch (OpNum) {
      case 2:
        // op: Ii
        return 8;
      case 0:
        // op: Qv4
        return 11;
      case 1:
        // op: Rt32
        return 16;
      case 3:
        // op: Vs32
        return 0;
      }
      break;
    }
    case Hexagon::V6_vS32b_srls_pi:
    case Hexagon::V6_zLd_pi: {
      switch (OpNum) {
      case 2:
        // op: Ii
        return 8;
      case 0:
        // op: Rx32
        return 16;
      }
      break;
    }
    case Hexagon::L4_ploadrbf_abs:
    case Hexagon::L4_ploadrbfnew_abs:
    case Hexagon::L4_ploadrbt_abs:
    case Hexagon::L4_ploadrbtnew_abs:
    case Hexagon::L4_ploadrhf_abs:
    case Hexagon::L4_ploadrhfnew_abs:
    case Hexagon::L4_ploadrht_abs:
    case Hexagon::L4_ploadrhtnew_abs:
    case Hexagon::L4_ploadrif_abs:
    case Hexagon::L4_ploadrifnew_abs:
    case Hexagon::L4_ploadrit_abs:
    case Hexagon::L4_ploadritnew_abs:
    case Hexagon::L4_ploadrubf_abs:
    case Hexagon::L4_ploadrubfnew_abs:
    case Hexagon::L4_ploadrubt_abs:
    case Hexagon::L4_ploadrubtnew_abs:
    case Hexagon::L4_ploadruhf_abs:
    case Hexagon::L4_ploadruhfnew_abs:
    case Hexagon::L4_ploadruht_abs:
    case Hexagon::L4_ploadruhtnew_abs: {
      switch (OpNum) {
      case 2:
        // op: Ii
        return 8;
      case 1:
        // op: Pt4
        return 9;
      case 0:
        // op: Rd32
        return 0;
      }
      break;
    }
    case Hexagon::L4_ploadrdf_abs:
    case Hexagon::L4_ploadrdfnew_abs:
    case Hexagon::L4_ploadrdt_abs:
    case Hexagon::L4_ploadrdtnew_abs: {
      switch (OpNum) {
      case 2:
        // op: Ii
        return 8;
      case 1:
        // op: Pt4
        return 9;
      case 0:
        // op: Rdd32
        return 0;
      }
      break;
    }
    case Hexagon::SL1_loadri_io:
    case Hexagon::SL1_loadrub_io:
    case Hexagon::SL2_loadrb_io:
    case Hexagon::SL2_loadrh_io:
    case Hexagon::SL2_loadruh_io: {
      switch (OpNum) {
      case 2:
        // op: Ii
        return 8;
      case 1:
        // op: Rs16
        return 4;
      case 0:
        // op: Rd16
        return 0;
      }
      break;
    }
    case Hexagon::C2_bitsclri:
    case Hexagon::C4_nbitsclri:
    case Hexagon::F2_sfclass:
    case Hexagon::S2_tstbit_i:
    case Hexagon::S4_ntstbit_i: {
      switch (OpNum) {
      case 2:
        // op: Ii
        return 8;
      case 1:
        // op: Rs32
        return 16;
      case 0:
        // op: Pd4
        return 0;
      }
      break;
    }
    case Hexagon::A4_cround_ri:
    case Hexagon::A4_round_ri:
    case Hexagon::A4_round_ri_sat:
    case Hexagon::A7_clip:
    case Hexagon::S2_asl_i_r:
    case Hexagon::S2_asl_i_r_sat:
    case Hexagon::S2_asr_i_r:
    case Hexagon::S2_asr_i_r_rnd:
    case Hexagon::S2_clrbit_i:
    case Hexagon::S2_lsr_i_r:
    case Hexagon::S2_setbit_i:
    case Hexagon::S2_togglebit_i:
    case Hexagon::S4_clbaddi:
    case Hexagon::S6_rol_i_r: {
      switch (OpNum) {
      case 2:
        // op: Ii
        return 8;
      case 1:
        // op: Rs32
        return 16;
      case 0:
        // op: Rd32
        return 0;
      }
      break;
    }
    case Hexagon::A4_bitspliti: {
      switch (OpNum) {
      case 2:
        // op: Ii
        return 8;
      case 1:
        // op: Rs32
        return 16;
      case 0:
        // op: Rdd32
        return 0;
      }
      break;
    }
    case Hexagon::S2_asr_i_svw_trun:
    case Hexagon::S4_clbpaddi:
    case Hexagon::S5_asrhub_rnd_sat:
    case Hexagon::S5_asrhub_sat: {
      switch (OpNum) {
      case 2:
        // op: Ii
        return 8;
      case 1:
        // op: Rss32
        return 16;
      case 0:
        // op: Rd32
        return 0;
      }
      break;
    }
    case Hexagon::A7_croundd_ri:
    case Hexagon::A7_vclip:
    case Hexagon::S2_asl_i_p:
    case Hexagon::S2_asl_i_vh:
    case Hexagon::S2_asl_i_vw:
    case Hexagon::S2_asr_i_p:
    case Hexagon::S2_asr_i_p_rnd:
    case Hexagon::S2_asr_i_vh:
    case Hexagon::S2_asr_i_vw:
    case Hexagon::S2_lsr_i_p:
    case Hexagon::S2_lsr_i_vh:
    case Hexagon::S2_lsr_i_vw:
    case Hexagon::S5_vasrhrnd:
    case Hexagon::S6_rol_i_p: {
      switch (OpNum) {
      case 2:
        // op: Ii
        return 8;
      case 1:
        // op: Rss32
        return 16;
      case 0:
        // op: Rdd32
        return 0;
      }
      break;
    }
    case Hexagon::V6_vL32Ub_ai:
    case Hexagon::V6_vL32b_ai:
    case Hexagon::V6_vL32b_cur_ai:
    case Hexagon::V6_vL32b_nt_ai:
    case Hexagon::V6_vL32b_nt_cur_ai:
    case Hexagon::V6_vL32b_nt_tmp_ai:
    case Hexagon::V6_vL32b_tmp_ai: {
      switch (OpNum) {
      case 2:
        // op: Ii
        return 8;
      case 1:
        // op: Rt32
        return 16;
      case 0:
        // op: Vd32
        return 0;
      }
      break;
    }
    case Hexagon::S2_extractu:
    case Hexagon::S4_extract: {
      switch (OpNum) {
      case 2:
        // op: Ii
        return 8;
      case 3:
        // op: II
        return 5;
      case 1:
        // op: Rs32
        return 16;
      case 0:
        // op: Rd32
        return 0;
      }
      break;
    }
    case Hexagon::S2_extractup:
    case Hexagon::S4_extractp: {
      switch (OpNum) {
      case 2:
        // op: Ii
        return 8;
      case 3:
        // op: II
        return 5;
      case 1:
        // op: Rss32
        return 16;
      case 0:
        // op: Rdd32
        return 0;
      }
      break;
    }
    case Hexagon::V6_vS32b_new_pi:
    case Hexagon::V6_vS32b_nt_new_pi: {
      switch (OpNum) {
      case 2:
        // op: Ii
        return 8;
      case 3:
        // op: Os8
        return 0;
      case 0:
        // op: Rx32
        return 16;
      }
      break;
    }
    case Hexagon::V6_vS32Ub_pi:
    case Hexagon::V6_vS32b_nt_pi:
    case Hexagon::V6_vS32b_pi: {
      switch (OpNum) {
      case 2:
        // op: Ii
        return 8;
      case 3:
        // op: Vs32
        return 0;
      case 0:
        // op: Rx32
        return 16;
      }
      break;
    }
    case Hexagon::V6_vS32b_srls_ppu:
    case Hexagon::V6_zLd_ppu: {
      switch (OpNum) {
      case 2:
        // op: Mu2
        return 13;
      case 0:
        // op: Rx32
        return 16;
      }
      break;
    }
    case Hexagon::S2_storerbnew_pbr:
    case Hexagon::S2_storerbnew_pcr:
    case Hexagon::S2_storerbnew_pr:
    case Hexagon::S2_storerhnew_pbr:
    case Hexagon::S2_storerhnew_pcr:
    case Hexagon::S2_storerhnew_pr:
    case Hexagon::S2_storerinew_pbr:
    case Hexagon::S2_storerinew_pcr:
    case Hexagon::S2_storerinew_pr: {
      switch (OpNum) {
      case 2:
        // op: Mu2
        return 13;
      case 3:
        // op: Nt8
        return 8;
      case 0:
        // op: Rx32
        return 16;
      }
      break;
    }
    case Hexagon::V6_vS32b_new_ppu:
    case Hexagon::V6_vS32b_nt_new_ppu: {
      switch (OpNum) {
      case 2:
        // op: Mu2
        return 13;
      case 3:
        // op: Os8
        return 0;
      case 0:
        // op: Rx32
        return 16;
      }
      break;
    }
    case Hexagon::S2_storerb_pbr:
    case Hexagon::S2_storerb_pcr:
    case Hexagon::S2_storerb_pr:
    case Hexagon::S2_storerf_pbr:
    case Hexagon::S2_storerf_pcr:
    case Hexagon::S2_storerf_pr:
    case Hexagon::S2_storerh_pbr:
    case Hexagon::S2_storerh_pcr:
    case Hexagon::S2_storerh_pr:
    case Hexagon::S2_storeri_pbr:
    case Hexagon::S2_storeri_pcr:
    case Hexagon::S2_storeri_pr: {
      switch (OpNum) {
      case 2:
        // op: Mu2
        return 13;
      case 3:
        // op: Rt32
        return 8;
      case 0:
        // op: Rx32
        return 16;
      }
      break;
    }
    case Hexagon::S2_storerd_pbr:
    case Hexagon::S2_storerd_pcr:
    case Hexagon::S2_storerd_pr: {
      switch (OpNum) {
      case 2:
        // op: Mu2
        return 13;
      case 3:
        // op: Rtt32
        return 8;
      case 0:
        // op: Rx32
        return 16;
      }
      break;
    }
    case Hexagon::V6_vS32Ub_ppu:
    case Hexagon::V6_vS32b_nt_ppu:
    case Hexagon::V6_vS32b_ppu: {
      switch (OpNum) {
      case 2:
        // op: Mu2
        return 13;
      case 3:
        // op: Vs32
        return 0;
      case 0:
        // op: Rx32
        return 16;
      }
      break;
    }
    case Hexagon::V6_vL32b_cur_npred_ppu:
    case Hexagon::V6_vL32b_cur_pred_ppu:
    case Hexagon::V6_vL32b_npred_ppu:
    case Hexagon::V6_vL32b_nt_cur_npred_ppu:
    case Hexagon::V6_vL32b_nt_cur_pred_ppu:
    case Hexagon::V6_vL32b_nt_npred_ppu:
    case Hexagon::V6_vL32b_nt_pred_ppu:
    case Hexagon::V6_vL32b_nt_tmp_npred_ppu:
    case Hexagon::V6_vL32b_nt_tmp_pred_ppu:
    case Hexagon::V6_vL32b_pred_ppu:
    case Hexagon::V6_vL32b_tmp_npred_ppu:
    case Hexagon::V6_vL32b_tmp_pred_ppu: {
      switch (OpNum) {
      case 2:
        // op: Pv4
        return 11;
      case 4:
        // op: Mu2
        return 13;
      case 0:
        // op: Vd32
        return 0;
      case 1:
        // op: Rx32
        return 16;
      }
      break;
    }
    case Hexagon::V6_vandnqrt_acc:
    case Hexagon::V6_vandqrt_acc: {
      switch (OpNum) {
      case 2:
        // op: Qu4
        return 8;
      case 3:
        // op: Rt32
        return 16;
      case 0:
        // op: Vx32
        return 0;
      }
      break;
    }
    case Hexagon::SA1_addrx: {
      switch (OpNum) {
      case 2:
        // op: Rs16
        return 4;
      case 0:
        // op: Rx16
        return 0;
      }
      break;
    }
    case Hexagon::F2_sfinvsqrta: {
      switch (OpNum) {
      case 2:
        // op: Rs32
        return 16;
      case 0:
        // op: Rd32
        return 0;
      case 1:
        // op: Pe4
        return 5;
      }
      break;
    }
    case Hexagon::F2_sfrecipa: {
      switch (OpNum) {
      case 2:
        // op: Rs32
        return 16;
      case 3:
        // op: Rt32
        return 8;
      case 0:
        // op: Rd32
        return 0;
      case 1:
        // op: Pe4
        return 5;
      }
      break;
    }
    case Hexagon::F2_sffma:
    case Hexagon::F2_sffma_lib:
    case Hexagon::F2_sffms:
    case Hexagon::F2_sffms_lib:
    case Hexagon::M2_acci:
    case Hexagon::M2_maci:
    case Hexagon::M2_mnaci:
    case Hexagon::M2_mpy_acc_hh_s0:
    case Hexagon::M2_mpy_acc_hh_s1:
    case Hexagon::M2_mpy_acc_hl_s0:
    case Hexagon::M2_mpy_acc_hl_s1:
    case Hexagon::M2_mpy_acc_lh_s0:
    case Hexagon::M2_mpy_acc_lh_s1:
    case Hexagon::M2_mpy_acc_ll_s0:
    case Hexagon::M2_mpy_acc_ll_s1:
    case Hexagon::M2_mpy_acc_sat_hh_s0:
    case Hexagon::M2_mpy_acc_sat_hh_s1:
    case Hexagon::M2_mpy_acc_sat_hl_s0:
    case Hexagon::M2_mpy_acc_sat_hl_s1:
    case Hexagon::M2_mpy_acc_sat_lh_s0:
    case Hexagon::M2_mpy_acc_sat_lh_s1:
    case Hexagon::M2_mpy_acc_sat_ll_s0:
    case Hexagon::M2_mpy_acc_sat_ll_s1:
    case Hexagon::M2_mpy_nac_hh_s0:
    case Hexagon::M2_mpy_nac_hh_s1:
    case Hexagon::M2_mpy_nac_hl_s0:
    case Hexagon::M2_mpy_nac_hl_s1:
    case Hexagon::M2_mpy_nac_lh_s0:
    case Hexagon::M2_mpy_nac_lh_s1:
    case Hexagon::M2_mpy_nac_ll_s0:
    case Hexagon::M2_mpy_nac_ll_s1:
    case Hexagon::M2_mpy_nac_sat_hh_s0:
    case Hexagon::M2_mpy_nac_sat_hh_s1:
    case Hexagon::M2_mpy_nac_sat_hl_s0:
    case Hexagon::M2_mpy_nac_sat_hl_s1:
    case Hexagon::M2_mpy_nac_sat_lh_s0:
    case Hexagon::M2_mpy_nac_sat_lh_s1:
    case Hexagon::M2_mpy_nac_sat_ll_s0:
    case Hexagon::M2_mpy_nac_sat_ll_s1:
    case Hexagon::M2_mpyu_acc_hh_s0:
    case Hexagon::M2_mpyu_acc_hh_s1:
    case Hexagon::M2_mpyu_acc_hl_s0:
    case Hexagon::M2_mpyu_acc_hl_s1:
    case Hexagon::M2_mpyu_acc_lh_s0:
    case Hexagon::M2_mpyu_acc_lh_s1:
    case Hexagon::M2_mpyu_acc_ll_s0:
    case Hexagon::M2_mpyu_acc_ll_s1:
    case Hexagon::M2_mpyu_nac_hh_s0:
    case Hexagon::M2_mpyu_nac_hh_s1:
    case Hexagon::M2_mpyu_nac_hl_s0:
    case Hexagon::M2_mpyu_nac_hl_s1:
    case Hexagon::M2_mpyu_nac_lh_s0:
    case Hexagon::M2_mpyu_nac_lh_s1:
    case Hexagon::M2_mpyu_nac_ll_s0:
    case Hexagon::M2_mpyu_nac_ll_s1:
    case Hexagon::M2_nacci:
    case Hexagon::M2_xor_xacc:
    case Hexagon::M4_and_and:
    case Hexagon::M4_and_andn:
    case Hexagon::M4_and_or:
    case Hexagon::M4_and_xor:
    case Hexagon::M4_mac_up_s1_sat:
    case Hexagon::M4_nac_up_s1_sat:
    case Hexagon::M4_or_and:
    case Hexagon::M4_or_andn:
    case Hexagon::M4_or_or:
    case Hexagon::M4_or_xor:
    case Hexagon::M4_xor_and:
    case Hexagon::M4_xor_andn:
    case Hexagon::M4_xor_or:
    case Hexagon::S2_asl_r_r_acc:
    case Hexagon::S2_asl_r_r_and:
    case Hexagon::S2_asl_r_r_nac:
    case Hexagon::S2_asl_r_r_or:
    case Hexagon::S2_asr_r_r_acc:
    case Hexagon::S2_asr_r_r_and:
    case Hexagon::S2_asr_r_r_nac:
    case Hexagon::S2_asr_r_r_or:
    case Hexagon::S2_lsl_r_r_acc:
    case Hexagon::S2_lsl_r_r_and:
    case Hexagon::S2_lsl_r_r_nac:
    case Hexagon::S2_lsl_r_r_or:
    case Hexagon::S2_lsr_r_r_acc:
    case Hexagon::S2_lsr_r_r_and:
    case Hexagon::S2_lsr_r_r_nac:
    case Hexagon::S2_lsr_r_r_or: {
      switch (OpNum) {
      case 2:
        // op: Rs32
        return 16;
      case 3:
        // op: Rt32
        return 8;
      case 0:
        // op: Rx32
        return 0;
      }
      break;
    }
    case Hexagon::M2_cmaci_s0:
    case Hexagon::M2_cmacr_s0:
    case Hexagon::M2_cmacs_s0:
    case Hexagon::M2_cmacs_s1:
    case Hexagon::M2_cmacsc_s0:
    case Hexagon::M2_cmacsc_s1:
    case Hexagon::M2_cnacs_s0:
    case Hexagon::M2_cnacs_s1:
    case Hexagon::M2_cnacsc_s0:
    case Hexagon::M2_cnacsc_s1:
    case Hexagon::M2_dpmpyss_acc_s0:
    case Hexagon::M2_dpmpyss_nac_s0:
    case Hexagon::M2_dpmpyuu_acc_s0:
    case Hexagon::M2_dpmpyuu_nac_s0:
    case Hexagon::M2_mpyd_acc_hh_s0:
    case Hexagon::M2_mpyd_acc_hh_s1:
    case Hexagon::M2_mpyd_acc_hl_s0:
    case Hexagon::M2_mpyd_acc_hl_s1:
    case Hexagon::M2_mpyd_acc_lh_s0:
    case Hexagon::M2_mpyd_acc_lh_s1:
    case Hexagon::M2_mpyd_acc_ll_s0:
    case Hexagon::M2_mpyd_acc_ll_s1:
    case Hexagon::M2_mpyd_nac_hh_s0:
    case Hexagon::M2_mpyd_nac_hh_s1:
    case Hexagon::M2_mpyd_nac_hl_s0:
    case Hexagon::M2_mpyd_nac_hl_s1:
    case Hexagon::M2_mpyd_nac_lh_s0:
    case Hexagon::M2_mpyd_nac_lh_s1:
    case Hexagon::M2_mpyd_nac_ll_s0:
    case Hexagon::M2_mpyd_nac_ll_s1:
    case Hexagon::M2_mpyud_acc_hh_s0:
    case Hexagon::M2_mpyud_acc_hh_s1:
    case Hexagon::M2_mpyud_acc_hl_s0:
    case Hexagon::M2_mpyud_acc_hl_s1:
    case Hexagon::M2_mpyud_acc_lh_s0:
    case Hexagon::M2_mpyud_acc_lh_s1:
    case Hexagon::M2_mpyud_acc_ll_s0:
    case Hexagon::M2_mpyud_acc_ll_s1:
    case Hexagon::M2_mpyud_nac_hh_s0:
    case Hexagon::M2_mpyud_nac_hh_s1:
    case Hexagon::M2_mpyud_nac_hl_s0:
    case Hexagon::M2_mpyud_nac_hl_s1:
    case Hexagon::M2_mpyud_nac_lh_s0:
    case Hexagon::M2_mpyud_nac_lh_s1:
    case Hexagon::M2_mpyud_nac_ll_s0:
    case Hexagon::M2_mpyud_nac_ll_s1:
    case Hexagon::M2_vmac2:
    case Hexagon::M2_vmac2s_s0:
    case Hexagon::M2_vmac2s_s1:
    case Hexagon::M2_vmac2su_s0:
    case Hexagon::M2_vmac2su_s1:
    case Hexagon::M4_pmpyw_acc:
    case Hexagon::M4_vpmpyh_acc:
    case Hexagon::M5_vmacbsu:
    case Hexagon::M5_vmacbuu: {
      switch (OpNum) {
      case 2:
        // op: Rs32
        return 16;
      case 3:
        // op: Rt32
        return 8;
      case 0:
        // op: Rxx32
        return 0;
      }
      break;
    }
    case Hexagon::F2_sffma_sc: {
      switch (OpNum) {
      case 2:
        // op: Rs32
        return 16;
      case 3:
        // op: Rt32
        return 8;
      case 4:
        // op: Pu4
        return 5;
      case 0:
        // op: Rx32
        return 0;
      }
      break;
    }
    case Hexagon::S2_insert_rp: {
      switch (OpNum) {
      case 2:
        // op: Rs32
        return 16;
      case 3:
        // op: Rtt32
        return 8;
      case 0:
        // op: Rx32
        return 0;
      }
      break;
    }
    case Hexagon::S2_asl_r_p_acc:
    case Hexagon::S2_asl_r_p_and:
    case Hexagon::S2_asl_r_p_nac:
    case Hexagon::S2_asl_r_p_or:
    case Hexagon::S2_asl_r_p_xor:
    case Hexagon::S2_asr_r_p_acc:
    case Hexagon::S2_asr_r_p_and:
    case Hexagon::S2_asr_r_p_nac:
    case Hexagon::S2_asr_r_p_or:
    case Hexagon::S2_asr_r_p_xor:
    case Hexagon::S2_lsl_r_p_acc:
    case Hexagon::S2_lsl_r_p_and:
    case Hexagon::S2_lsl_r_p_nac:
    case Hexagon::S2_lsl_r_p_or:
    case Hexagon::S2_lsl_r_p_xor:
    case Hexagon::S2_lsr_r_p_acc:
    case Hexagon::S2_lsr_r_p_and:
    case Hexagon::S2_lsr_r_p_nac:
    case Hexagon::S2_lsr_r_p_or:
    case Hexagon::S2_lsr_r_p_xor:
    case Hexagon::S2_vrcnegh: {
      switch (OpNum) {
      case 2:
        // op: Rss32
        return 16;
      case 3:
        // op: Rt32
        return 8;
      case 0:
        // op: Rxx32
        return 0;
      }
      break;
    }
    case Hexagon::A4_addp_c:
    case Hexagon::A4_subp_c: {
      switch (OpNum) {
      case 2:
        // op: Rss32
        return 16;
      case 3:
        // op: Rtt32
        return 8;
      case 0:
        // op: Rdd32
        return 0;
      case 1:
        // op: Px4
        return 5;
      }
      break;
    }
    case Hexagon::A2_vraddub_acc:
    case Hexagon::A2_vrsadub_acc:
    case Hexagon::F2_dfmpyhh:
    case Hexagon::F2_dfmpylh:
    case Hexagon::M2_mmachs_rs0:
    case Hexagon::M2_mmachs_rs1:
    case Hexagon::M2_mmachs_s0:
    case Hexagon::M2_mmachs_s1:
    case Hexagon::M2_mmacls_rs0:
    case Hexagon::M2_mmacls_rs1:
    case Hexagon::M2_mmacls_s0:
    case Hexagon::M2_mmacls_s1:
    case Hexagon::M2_mmacuhs_rs0:
    case Hexagon::M2_mmacuhs_rs1:
    case Hexagon::M2_mmacuhs_s0:
    case Hexagon::M2_mmacuhs_s1:
    case Hexagon::M2_mmaculs_rs0:
    case Hexagon::M2_mmaculs_rs1:
    case Hexagon::M2_mmaculs_s0:
    case Hexagon::M2_mmaculs_s1:
    case Hexagon::M2_vcmac_s0_sat_i:
    case Hexagon::M2_vcmac_s0_sat_r:
    case Hexagon::M2_vdmacs_s0:
    case Hexagon::M2_vdmacs_s1:
    case Hexagon::M2_vmac2es:
    case Hexagon::M2_vmac2es_s0:
    case Hexagon::M2_vmac2es_s1:
    case Hexagon::M2_vrcmaci_s0:
    case Hexagon::M2_vrcmaci_s0c:
    case Hexagon::M2_vrcmacr_s0:
    case Hexagon::M2_vrcmacr_s0c:
    case Hexagon::M2_vrcmpys_acc_s1_h:
    case Hexagon::M2_vrcmpys_acc_s1_l:
    case Hexagon::M2_vrmac_s0:
    case Hexagon::M4_vrmpyeh_acc_s0:
    case Hexagon::M4_vrmpyeh_acc_s1:
    case Hexagon::M4_vrmpyoh_acc_s0:
    case Hexagon::M4_vrmpyoh_acc_s1:
    case Hexagon::M4_xor_xacc:
    case Hexagon::M5_vdmacbsu:
    case Hexagon::M5_vrmacbsu:
    case Hexagon::M5_vrmacbuu:
    case Hexagon::M7_dcmpyiw_acc:
    case Hexagon::M7_dcmpyiwc_acc:
    case Hexagon::M7_dcmpyrw_acc:
    case Hexagon::M7_dcmpyrwc_acc:
    case Hexagon::S2_insertp_rp: {
      switch (OpNum) {
      case 2:
        // op: Rss32
        return 16;
      case 3:
        // op: Rtt32
        return 8;
      case 0:
        // op: Rxx32
        return 0;
      }
      break;
    }
    case Hexagon::A4_vrmaxh:
    case Hexagon::A4_vrmaxuh:
    case Hexagon::A4_vrmaxuw:
    case Hexagon::A4_vrmaxw:
    case Hexagon::A4_vrminh:
    case Hexagon::A4_vrminuh:
    case Hexagon::A4_vrminuw:
    case Hexagon::A4_vrminw: {
      switch (OpNum) {
      case 2:
        // op: Rss32
        return 16;
      case 3:
        // op: Ru32
        return 0;
      case 0:
        // op: Rxx32
        return 8;
      }
      break;
    }
    case Hexagon::V6_vinsertwr: {
      switch (OpNum) {
      case 2:
        // op: Rt32
        return 16;
      case 0:
        // op: Vx32
        return 0;
      }
      break;
    }
    case Hexagon::M2_subacc: {
      switch (OpNum) {
      case 2:
        // op: Rt32
        return 8;
      case 3:
        // op: Rs32
        return 16;
      case 0:
        // op: Rx32
        return 0;
      }
      break;
    }
    case Hexagon::A6_vminub_RdP: {
      switch (OpNum) {
      case 2:
        // op: Rtt32
        return 8;
      case 3:
        // op: Rss32
        return 16;
      case 0:
        // op: Rdd32
        return 0;
      case 1:
        // op: Pe4
        return 5;
      }
      break;
    }
    case Hexagon::V6_vrmpyzbb_rx:
    case Hexagon::V6_vrmpyzbub_rx:
    case Hexagon::V6_vrmpyzcb_rx:
    case Hexagon::V6_vrmpyzcbs_rx:
    case Hexagon::V6_vrmpyznb_rx: {
      switch (OpNum) {
      case 2:
        // op: Vu32
        return 8;
      case 0:
        // op: Vdddd32
        return 0;
      case 1:
        // op: Rx8
        return 16;
      }
      break;
    }
    case Hexagon::V6_vunpackob:
    case Hexagon::V6_vunpackoh: {
      switch (OpNum) {
      case 2:
        // op: Vu32
        return 8;
      case 0:
        // op: Vxx32
        return 0;
      }
      break;
    }
    case Hexagon::V6_vandvrt_acc: {
      switch (OpNum) {
      case 2:
        // op: Vu32
        return 8;
      case 3:
        // op: Rt32
        return 16;
      case 0:
        // op: Qx4
        return 0;
      }
      break;
    }
    case Hexagon::V6_vaslh_acc:
    case Hexagon::V6_vaslw_acc:
    case Hexagon::V6_vasrh_acc:
    case Hexagon::V6_vasrw_acc:
    case Hexagon::V6_vdmpybus_acc:
    case Hexagon::V6_vdmpyhb_acc:
    case Hexagon::V6_vdmpyhsat_acc:
    case Hexagon::V6_vdmpyhsusat_acc:
    case Hexagon::V6_vmpyihb_acc:
    case Hexagon::V6_vmpyiwb_acc:
    case Hexagon::V6_vmpyiwh_acc:
    case Hexagon::V6_vmpyiwub_acc:
    case Hexagon::V6_vmpyuhe_acc:
    case Hexagon::V6_vrmpybus_acc:
    case Hexagon::V6_vrmpyub_acc: {
      switch (OpNum) {
      case 2:
        // op: Vu32
        return 8;
      case 3:
        // op: Rt32
        return 16;
      case 0:
        // op: Vx32
        return 0;
      }
      break;
    }
    case Hexagon::V6_vmpybus_acc:
    case Hexagon::V6_vmpyh_acc:
    case Hexagon::V6_vmpyhsat_acc:
    case Hexagon::V6_vmpyub_acc:
    case Hexagon::V6_vmpyuh_acc: {
      switch (OpNum) {
      case 2:
        // op: Vu32
        return 8;
      case 3:
        // op: Rt32
        return 16;
      case 0:
        // op: Vxx32
        return 0;
      }
      break;
    }
    case Hexagon::V6_vrmpyzbb_rt_acc:
    case Hexagon::V6_vrmpyzbub_rt_acc:
    case Hexagon::V6_vrmpyzcb_rt_acc:
    case Hexagon::V6_vrmpyzcbs_rt_acc:
    case Hexagon::V6_vrmpyznb_rt_acc: {
      switch (OpNum) {
      case 2:
        // op: Vu32
        return 8;
      case 3:
        // op: Rt8
        return 16;
      case 0:
        // op: Vyyyy32
        return 0;
      }
      break;
    }
    case Hexagon::V6_vmpahhsat:
    case Hexagon::V6_vmpauhuhsat:
    case Hexagon::V6_vmpsuhuhsat: {
      switch (OpNum) {
      case 2:
        // op: Vu32
        return 8;
      case 3:
        // op: Rtt32
        return 16;
      case 0:
        // op: Vx32
        return 0;
      }
      break;
    }
    case Hexagon::V6_vrmpybub_rtt_acc:
    case Hexagon::V6_vrmpyub_rtt_acc: {
      switch (OpNum) {
      case 2:
        // op: Vu32
        return 8;
      case 3:
        // op: Rtt32
        return 16;
      case 0:
        // op: Vxx32
        return 0;
      }
      break;
    }
    case Hexagon::V6_veqb_and:
    case Hexagon::V6_veqb_or:
    case Hexagon::V6_veqb_xor:
    case Hexagon::V6_veqh_and:
    case Hexagon::V6_veqh_or:
    case Hexagon::V6_veqh_xor:
    case Hexagon::V6_veqw_and:
    case Hexagon::V6_veqw_or:
    case Hexagon::V6_veqw_xor:
    case Hexagon::V6_vgtb_and:
    case Hexagon::V6_vgtb_or:
    case Hexagon::V6_vgtb_xor:
    case Hexagon::V6_vgtbf_and:
    case Hexagon::V6_vgtbf_or:
    case Hexagon::V6_vgtbf_xor:
    case Hexagon::V6_vgth_and:
    case Hexagon::V6_vgth_or:
    case Hexagon::V6_vgth_xor:
    case Hexagon::V6_vgthf_and:
    case Hexagon::V6_vgthf_or:
    case Hexagon::V6_vgthf_xor:
    case Hexagon::V6_vgtsf_and:
    case Hexagon::V6_vgtsf_or:
    case Hexagon::V6_vgtsf_xor:
    case Hexagon::V6_vgtub_and:
    case Hexagon::V6_vgtub_or:
    case Hexagon::V6_vgtub_xor:
    case Hexagon::V6_vgtuh_and:
    case Hexagon::V6_vgtuh_or:
    case Hexagon::V6_vgtuh_xor:
    case Hexagon::V6_vgtuw_and:
    case Hexagon::V6_vgtuw_or:
    case Hexagon::V6_vgtuw_xor:
    case Hexagon::V6_vgtw_and:
    case Hexagon::V6_vgtw_or:
    case Hexagon::V6_vgtw_xor: {
      switch (OpNum) {
      case 2:
        // op: Vu32
        return 8;
      case 3:
        // op: Vv32
        return 16;
      case 0:
        // op: Qx4
        return 0;
      }
      break;
    }
    case Hexagon::V6_vaddcarryo:
    case Hexagon::V6_vsubcarryo: {
      switch (OpNum) {
      case 2:
        // op: Vu32
        return 8;
      case 3:
        // op: Vv32
        return 16;
      case 0:
        // op: Vd32
        return 0;
      case 1:
        // op: Qe4
        return 5;
      }
      break;
    }
    case Hexagon::V6_vaddcarry:
    case Hexagon::V6_vsubcarry: {
      switch (OpNum) {
      case 2:
        // op: Vu32
        return 8;
      case 3:
        // op: Vv32
        return 16;
      case 0:
        // op: Vd32
        return 0;
      case 1:
        // op: Qx4
        return 5;
      }
      break;
    }
    case Hexagon::V6_vdmpy_sf_hf_acc:
    case Hexagon::V6_vdmpyhvsat_acc:
    case Hexagon::V6_vmpy_hf_hf_acc:
    case Hexagon::V6_vmpyiewh_acc:
    case Hexagon::V6_vmpyiewuh_acc:
    case Hexagon::V6_vmpyih_acc:
    case Hexagon::V6_vmpyowh_rnd_sacc:
    case Hexagon::V6_vmpyowh_sacc:
    case Hexagon::V6_vrmpybusv_acc:
    case Hexagon::V6_vrmpybv_acc:
    case Hexagon::V6_vrmpyubv_acc: {
      switch (OpNum) {
      case 2:
        // op: Vu32
        return 8;
      case 3:
        // op: Vv32
        return 16;
      case 0:
        // op: Vx32
        return 0;
      }
      break;
    }
    case Hexagon::V6_vaddhw_acc:
    case Hexagon::V6_vaddubh_acc:
    case Hexagon::V6_vadduhw_acc:
    case Hexagon::V6_vasr_into:
    case Hexagon::V6_vmpy_sf_bf_acc:
    case Hexagon::V6_vmpy_sf_hf_acc:
    case Hexagon::V6_vmpybusv_acc:
    case Hexagon::V6_vmpybv_acc:
    case Hexagon::V6_vmpyhus_acc:
    case Hexagon::V6_vmpyhv_acc:
    case Hexagon::V6_vmpyowh_64_acc:
    case Hexagon::V6_vmpyubv_acc:
    case Hexagon::V6_vmpyuhv_acc: {
      switch (OpNum) {
      case 2:
        // op: Vu32
        return 8;
      case 3:
        // op: Vv32
        return 16;
      case 0:
        // op: Vxx32
        return 0;
      }
      break;
    }
    case Hexagon::V6_vlutvvb_oracc: {
      switch (OpNum) {
      case 2:
        // op: Vu32
        return 8;
      case 3:
        // op: Vv32
        return 19;
      case 4:
        // op: Rt8
        return 16;
      case 0:
        // op: Vx32
        return 0;
      }
      break;
    }
    case Hexagon::V6_vlutvwh_oracc: {
      switch (OpNum) {
      case 2:
        // op: Vu32
        return 8;
      case 3:
        // op: Vv32
        return 19;
      case 4:
        // op: Rt8
        return 16;
      case 0:
        // op: Vxx32
        return 0;
      }
      break;
    }
    case Hexagon::V6_vdmpyhisat_acc:
    case Hexagon::V6_vdmpyhsuisat_acc: {
      switch (OpNum) {
      case 2:
        // op: Vuu32
        return 8;
      case 3:
        // op: Rt32
        return 16;
      case 0:
        // op: Vx32
        return 0;
      }
      break;
    }
    case Hexagon::V6_vdmpybus_dv_acc:
    case Hexagon::V6_vdmpyhb_dv_acc:
    case Hexagon::V6_vdsaduh_acc:
    case Hexagon::V6_vmpabus_acc:
    case Hexagon::V6_vmpabuu_acc:
    case Hexagon::V6_vmpahb_acc:
    case Hexagon::V6_vmpauhb_acc:
    case Hexagon::V6_vtmpyb_acc:
    case Hexagon::V6_vtmpybus_acc:
    case Hexagon::V6_vtmpyhb_acc: {
      switch (OpNum) {
      case 2:
        // op: Vuu32
        return 8;
      case 3:
        // op: Rt32
        return 16;
      case 0:
        // op: Vxx32
        return 0;
      }
      break;
    }
    case Hexagon::L4_loadalignb_ap:
    case Hexagon::L4_loadalignh_ap: {
      switch (OpNum) {
      case 3:
        // op: II
        return 5;
      case 0:
        // op: Ryy32
        return 0;
      case 1:
        // op: Re32
        return 16;
      }
      break;
    }
    case Hexagon::S2_pstorerbnewf_pi:
    case Hexagon::S2_pstorerbnewfnew_pi:
    case Hexagon::S2_pstorerbnewt_pi:
    case Hexagon::S2_pstorerbnewtnew_pi:
    case Hexagon::S2_pstorerhnewf_pi:
    case Hexagon::S2_pstorerhnewfnew_pi:
    case Hexagon::S2_pstorerhnewt_pi:
    case Hexagon::S2_pstorerhnewtnew_pi:
    case Hexagon::S2_pstorerinewf_pi:
    case Hexagon::S2_pstorerinewfnew_pi:
    case Hexagon::S2_pstorerinewt_pi:
    case Hexagon::S2_pstorerinewtnew_pi: {
      switch (OpNum) {
      case 3:
        // op: Ii
        return 3;
      case 1:
        // op: Pv4
        return 0;
      case 4:
        // op: Nt8
        return 8;
      case 0:
        // op: Rx32
        return 16;
      }
      break;
    }
    case Hexagon::S2_pstorerbf_pi:
    case Hexagon::S2_pstorerbfnew_pi:
    case Hexagon::S2_pstorerbt_pi:
    case Hexagon::S2_pstorerbtnew_pi:
    case Hexagon::S2_pstorerff_pi:
    case Hexagon::S2_pstorerffnew_pi:
    case Hexagon::S2_pstorerft_pi:
    case Hexagon::S2_pstorerftnew_pi:
    case Hexagon::S2_pstorerhf_pi:
    case Hexagon::S2_pstorerhfnew_pi:
    case Hexagon::S2_pstorerht_pi:
    case Hexagon::S2_pstorerhtnew_pi:
    case Hexagon::S2_pstorerif_pi:
    case Hexagon::S2_pstorerifnew_pi:
    case Hexagon::S2_pstorerit_pi:
    case Hexagon::S2_pstoreritnew_pi: {
      switch (OpNum) {
      case 3:
        // op: Ii
        return 3;
      case 1:
        // op: Pv4
        return 0;
      case 4:
        // op: Rt32
        return 8;
      case 0:
        // op: Rx32
        return 16;
      }
      break;
    }
    case Hexagon::S2_pstorerdf_pi:
    case Hexagon::S2_pstorerdfnew_pi:
    case Hexagon::S2_pstorerdt_pi:
    case Hexagon::S2_pstorerdtnew_pi: {
      switch (OpNum) {
      case 3:
        // op: Ii
        return 3;
      case 1:
        // op: Pv4
        return 0;
      case 4:
        // op: Rtt32
        return 8;
      case 0:
        // op: Rx32
        return 16;
      }
      break;
    }
    case Hexagon::L2_loadbsw2_pi:
    case Hexagon::L2_loadbzw2_pi:
    case Hexagon::L2_loadrb_pi:
    case Hexagon::L2_loadrh_pi:
    case Hexagon::L2_loadri_pi:
    case Hexagon::L2_loadrub_pi:
    case Hexagon::L2_loadruh_pi: {
      switch (OpNum) {
      case 3:
        // op: Ii
        return 5;
      case 0:
        // op: Rd32
        return 0;
      case 1:
        // op: Rx32
        return 16;
      }
      break;
    }
    case Hexagon::L2_loadbsw4_pi:
    case Hexagon::L2_loadbzw4_pi:
    case Hexagon::L2_loadrd_pi: {
      switch (OpNum) {
      case 3:
        // op: Ii
        return 5;
      case 0:
        // op: Rdd32
        return 0;
      case 1:
        // op: Rx32
        return 16;
      }
      break;
    }
    case Hexagon::L2_ploadrbf_io:
    case Hexagon::L2_ploadrbfnew_io:
    case Hexagon::L2_ploadrbt_io:
    case Hexagon::L2_ploadrbtnew_io:
    case Hexagon::L2_ploadrhf_io:
    case Hexagon::L2_ploadrhfnew_io:
    case Hexagon::L2_ploadrht_io:
    case Hexagon::L2_ploadrhtnew_io:
    case Hexagon::L2_ploadrif_io:
    case Hexagon::L2_ploadrifnew_io:
    case Hexagon::L2_ploadrit_io:
    case Hexagon::L2_ploadritnew_io:
    case Hexagon::L2_ploadrubf_io:
    case Hexagon::L2_ploadrubfnew_io:
    case Hexagon::L2_ploadrubt_io:
    case Hexagon::L2_ploadrubtnew_io:
    case Hexagon::L2_ploadruhf_io:
    case Hexagon::L2_ploadruhfnew_io:
    case Hexagon::L2_ploadruht_io:
    case Hexagon::L2_ploadruhtnew_io: {
      switch (OpNum) {
      case 3:
        // op: Ii
        return 5;
      case 1:
        // op: Pt4
        return 11;
      case 2:
        // op: Rs32
        return 16;
      case 0:
        // op: Rd32
        return 0;
      }
      break;
    }
    case Hexagon::L2_ploadrdf_io:
    case Hexagon::L2_ploadrdfnew_io:
    case Hexagon::L2_ploadrdt_io:
    case Hexagon::L2_ploadrdtnew_io: {
      switch (OpNum) {
      case 3:
        // op: Ii
        return 5;
      case 1:
        // op: Pt4
        return 11;
      case 2:
        // op: Rs32
        return 16;
      case 0:
        // op: Rdd32
        return 0;
      }
      break;
    }
    case Hexagon::A2_paddif:
    case Hexagon::A2_paddifnew:
    case Hexagon::A2_paddit:
    case Hexagon::A2_padditnew:
    case Hexagon::C2_muxir: {
      switch (OpNum) {
      case 3:
        // op: Ii
        return 5;
      case 1:
        // op: Pu4
        return 21;
      case 2:
        // op: Rs32
        return 16;
      case 0:
        // op: Rd32
        return 0;
      }
      break;
    }
    case Hexagon::S4_addaddi: {
      switch (OpNum) {
      case 3:
        // op: Ii
        return 5;
      case 1:
        // op: Rs32
        return 16;
      case 2:
        // op: Ru32
        return 0;
      case 0:
        // op: Rd32
        return 8;
      }
      break;
    }
    case Hexagon::S4_vrcrotate: {
      switch (OpNum) {
      case 3:
        // op: Ii
        return 5;
      case 1:
        // op: Rss32
        return 16;
      case 2:
        // op: Rt32
        return 8;
      case 0:
        // op: Rdd32
        return 0;
      }
      break;
    }
    case Hexagon::S2_vspliceib: {
      switch (OpNum) {
      case 3:
        // op: Ii
        return 5;
      case 1:
        // op: Rss32
        return 16;
      case 2:
        // op: Rtt32
        return 8;
      case 0:
        // op: Rdd32
        return 0;
      }
      break;
    }
    case Hexagon::S2_addasl_rrri: {
      switch (OpNum) {
      case 3:
        // op: Ii
        return 5;
      case 1:
        // op: Rt32
        return 8;
      case 2:
        // op: Rs32
        return 16;
      case 0:
        // op: Rd32
        return 0;
      }
      break;
    }
    case Hexagon::S2_valignib: {
      switch (OpNum) {
      case 3:
        // op: Ii
        return 5;
      case 1:
        // op: Rtt32
        return 8;
      case 2:
        // op: Rss32
        return 16;
      case 0:
        // op: Rdd32
        return 0;
      }
      break;
    }
    case Hexagon::S4_or_andix: {
      switch (OpNum) {
      case 3:
        // op: Ii
        return 5;
      case 1:
        // op: Ru32
        return 0;
      case 0:
        // op: Rx32
        return 16;
      }
      break;
    }
    case Hexagon::M4_mpyri_addr: {
      switch (OpNum) {
      case 3:
        // op: Ii
        return 5;
      case 1:
        // op: Ru32
        return 0;
      case 2:
        // op: Rs32
        return 16;
      case 0:
        // op: Rd32
        return 8;
      }
      break;
    }
    case Hexagon::V6_valignbi:
    case Hexagon::V6_vlalignbi:
    case Hexagon::V6_vlutvvbi: {
      switch (OpNum) {
      case 3:
        // op: Ii
        return 5;
      case 1:
        // op: Vu32
        return 8;
      case 2:
        // op: Vv32
        return 16;
      case 0:
        // op: Vd32
        return 0;
      }
      break;
    }
    case Hexagon::V6_vlutvwhi: {
      switch (OpNum) {
      case 3:
        // op: Ii
        return 5;
      case 1:
        // op: Vu32
        return 8;
      case 2:
        // op: Vv32
        return 16;
      case 0:
        // op: Vdd32
        return 0;
      }
      break;
    }
    case Hexagon::V6_vrmpybusi:
    case Hexagon::V6_vrmpyubi:
    case Hexagon::V6_vrsadubi: {
      switch (OpNum) {
      case 3:
        // op: Ii
        return 5;
      case 1:
        // op: Vuu32
        return 8;
      case 2:
        // op: Rt32
        return 16;
      case 0:
        // op: Vdd32
        return 0;
      }
      break;
    }
    case Hexagon::V6_v6mpyhubs10:
    case Hexagon::V6_v6mpyvubs10: {
      switch (OpNum) {
      case 3:
        // op: Ii
        return 5;
      case 1:
        // op: Vuu32
        return 8;
      case 2:
        // op: Vvv32
        return 16;
      case 0:
        // op: Vdd32
        return 0;
      }
      break;
    }
    case Hexagon::M2_accii:
    case Hexagon::M2_macsin:
    case Hexagon::M2_macsip:
    case Hexagon::M2_naccii:
    case Hexagon::S4_or_andi:
    case Hexagon::S4_or_ori: {
      switch (OpNum) {
      case 3:
        // op: Ii
        return 5;
      case 2:
        // op: Rs32
        return 16;
      case 0:
        // op: Rx32
        return 0;
      }
      break;
    }
    case Hexagon::L2_loadalignb_io:
    case Hexagon::L2_loadalignh_io: {
      switch (OpNum) {
      case 3:
        // op: Ii
        return 5;
      case 2:
        // op: Rs32
        return 16;
      case 0:
        // op: Ryy32
        return 0;
      }
      break;
    }
    case Hexagon::S2_tableidxb:
    case Hexagon::S2_tableidxd:
    case Hexagon::S2_tableidxh:
    case Hexagon::S2_tableidxw: {
      switch (OpNum) {
      case 3:
        // op: Ii
        return 5;
      case 4:
        // op: II
        return 8;
      case 2:
        // op: Rs32
        return 16;
      case 0:
        // op: Rx32
        return 0;
      }
      break;
    }
    case Hexagon::L2_loadbsw2_pci:
    case Hexagon::L2_loadbzw2_pci:
    case Hexagon::L2_loadrb_pci:
    case Hexagon::L2_loadrh_pci:
    case Hexagon::L2_loadri_pci:
    case Hexagon::L2_loadrub_pci:
    case Hexagon::L2_loadruh_pci: {
      switch (OpNum) {
      case 3:
        // op: Ii
        return 5;
      case 4:
        // op: Mu2
        return 13;
      case 0:
        // op: Rd32
        return 0;
      case 1:
        // op: Rx32
        return 16;
      }
      break;
    }
    case Hexagon::L2_loadbsw4_pci:
    case Hexagon::L2_loadbzw4_pci:
    case Hexagon::L2_loadrd_pci: {
      switch (OpNum) {
      case 3:
        // op: Ii
        return 5;
      case 4:
        // op: Mu2
        return 13;
      case 0:
        // op: Rdd32
        return 0;
      case 1:
        // op: Rx32
        return 16;
      }
      break;
    }
    case Hexagon::S4_pstorerbnewf_rr:
    case Hexagon::S4_pstorerbnewfnew_rr:
    case Hexagon::S4_pstorerbnewt_rr:
    case Hexagon::S4_pstorerbnewtnew_rr:
    case Hexagon::S4_pstorerhnewf_rr:
    case Hexagon::S4_pstorerhnewfnew_rr:
    case Hexagon::S4_pstorerhnewt_rr:
    case Hexagon::S4_pstorerhnewtnew_rr:
    case Hexagon::S4_pstorerinewf_rr:
    case Hexagon::S4_pstorerinewfnew_rr:
    case Hexagon::S4_pstorerinewt_rr:
    case Hexagon::S4_pstorerinewtnew_rr: {
      switch (OpNum) {
      case 3:
        // op: Ii
        return 7;
      case 0:
        // op: Pv4
        return 5;
      case 1:
        // op: Rs32
        return 16;
      case 2:
        // op: Ru32
        return 8;
      case 4:
        // op: Nt8
        return 0;
      }
      break;
    }
    case Hexagon::S4_pstorerbf_rr:
    case Hexagon::S4_pstorerbfnew_rr:
    case Hexagon::S4_pstorerbt_rr:
    case Hexagon::S4_pstorerbtnew_rr:
    case Hexagon::S4_pstorerff_rr:
    case Hexagon::S4_pstorerffnew_rr:
    case Hexagon::S4_pstorerft_rr:
    case Hexagon::S4_pstorerftnew_rr:
    case Hexagon::S4_pstorerhf_rr:
    case Hexagon::S4_pstorerhfnew_rr:
    case Hexagon::S4_pstorerht_rr:
    case Hexagon::S4_pstorerhtnew_rr:
    case Hexagon::S4_pstorerif_rr:
    case Hexagon::S4_pstorerifnew_rr:
    case Hexagon::S4_pstorerit_rr:
    case Hexagon::S4_pstoreritnew_rr: {
      switch (OpNum) {
      case 3:
        // op: Ii
        return 7;
      case 0:
        // op: Pv4
        return 5;
      case 1:
        // op: Rs32
        return 16;
      case 2:
        // op: Ru32
        return 8;
      case 4:
        // op: Rt32
        return 0;
      }
      break;
    }
    case Hexagon::S4_pstorerdf_rr:
    case Hexagon::S4_pstorerdfnew_rr:
    case Hexagon::S4_pstorerdt_rr:
    case Hexagon::S4_pstorerdtnew_rr: {
      switch (OpNum) {
      case 3:
        // op: Ii
        return 7;
      case 0:
        // op: Pv4
        return 5;
      case 1:
        // op: Rs32
        return 16;
      case 2:
        // op: Ru32
        return 8;
      case 4:
        // op: Rtt32
        return 0;
      }
      break;
    }
    case Hexagon::L4_loadrb_rr:
    case Hexagon::L4_loadrh_rr:
    case Hexagon::L4_loadri_rr:
    case Hexagon::L4_loadrub_rr:
    case Hexagon::L4_loadruh_rr: {
      switch (OpNum) {
      case 3:
        // op: Ii
        return 7;
      case 1:
        // op: Rs32
        return 16;
      case 2:
        // op: Rt32
        return 8;
      case 0:
        // op: Rd32
        return 0;
      }
      break;
    }
    case Hexagon::L4_loadrd_rr: {
      switch (OpNum) {
      case 3:
        // op: Ii
        return 7;
      case 1:
        // op: Rs32
        return 16;
      case 2:
        // op: Rt32
        return 8;
      case 0:
        // op: Rdd32
        return 0;
      }
      break;
    }
    case Hexagon::L4_loadalignb_ur:
    case Hexagon::L4_loadalignh_ur: {
      switch (OpNum) {
      case 3:
        // op: Ii
        return 7;
      case 4:
        // op: II
        return 5;
      case 2:
        // op: Rt32
        return 16;
      case 0:
        // op: Ryy32
        return 0;
      }
      break;
    }
    case Hexagon::V6_vL32Ub_pi:
    case Hexagon::V6_vL32b_cur_pi:
    case Hexagon::V6_vL32b_nt_cur_pi:
    case Hexagon::V6_vL32b_nt_pi:
    case Hexagon::V6_vL32b_nt_tmp_pi:
    case Hexagon::V6_vL32b_pi:
    case Hexagon::V6_vL32b_tmp_pi: {
      switch (OpNum) {
      case 3:
        // op: Ii
        return 8;
      case 0:
        // op: Vd32
        return 0;
      case 1:
        // op: Rx32
        return 16;
      }
      break;
    }
    case Hexagon::V6_zLd_pred_pi: {
      switch (OpNum) {
      case 3:
        // op: Ii
        return 8;
      case 1:
        // op: Pv4
        return 11;
      case 0:
        // op: Rx32
        return 16;
      }
      break;
    }
    case Hexagon::V6_vL32b_cur_npred_ai:
    case Hexagon::V6_vL32b_cur_pred_ai:
    case Hexagon::V6_vL32b_npred_ai:
    case Hexagon::V6_vL32b_nt_cur_npred_ai:
    case Hexagon::V6_vL32b_nt_cur_pred_ai:
    case Hexagon::V6_vL32b_nt_npred_ai:
    case Hexagon::V6_vL32b_nt_pred_ai:
    case Hexagon::V6_vL32b_nt_tmp_npred_ai:
    case Hexagon::V6_vL32b_nt_tmp_pred_ai:
    case Hexagon::V6_vL32b_pred_ai:
    case Hexagon::V6_vL32b_tmp_npred_ai:
    case Hexagon::V6_vL32b_tmp_pred_ai: {
      switch (OpNum) {
      case 3:
        // op: Ii
        return 8;
      case 1:
        // op: Pv4
        return 11;
      case 2:
        // op: Rt32
        return 16;
      case 0:
        // op: Vd32
        return 0;
      }
      break;
    }
    case Hexagon::V6_vS32b_new_npred_pi:
    case Hexagon::V6_vS32b_new_pred_pi:
    case Hexagon::V6_vS32b_nt_new_npred_pi:
    case Hexagon::V6_vS32b_nt_new_pred_pi: {
      switch (OpNum) {
      case 3:
        // op: Ii
        return 8;
      case 1:
        // op: Pv4
        return 11;
      case 4:
        // op: Os8
        return 0;
      case 0:
        // op: Rx32
        return 16;
      }
      break;
    }
    case Hexagon::V6_vS32Ub_npred_pi:
    case Hexagon::V6_vS32Ub_pred_pi:
    case Hexagon::V6_vS32b_npred_pi:
    case Hexagon::V6_vS32b_nt_npred_pi:
    case Hexagon::V6_vS32b_nt_pred_pi:
    case Hexagon::V6_vS32b_pred_pi: {
      switch (OpNum) {
      case 3:
        // op: Ii
        return 8;
      case 1:
        // op: Pv4
        return 11;
      case 4:
        // op: Vs32
        return 0;
      case 0:
        // op: Rx32
        return 16;
      }
      break;
    }
    case Hexagon::V6_vS32b_nqpred_pi:
    case Hexagon::V6_vS32b_nt_nqpred_pi:
    case Hexagon::V6_vS32b_nt_qpred_pi:
    case Hexagon::V6_vS32b_qpred_pi: {
      switch (OpNum) {
      case 3:
        // op: Ii
        return 8;
      case 1:
        // op: Qv4
        return 11;
      case 4:
        // op: Vs32
        return 0;
      case 0:
        // op: Rx32
        return 16;
      }
      break;
    }
    case Hexagon::S2_asl_i_r_acc:
    case Hexagon::S2_asl_i_r_and:
    case Hexagon::S2_asl_i_r_nac:
    case Hexagon::S2_asl_i_r_or:
    case Hexagon::S2_asl_i_r_xacc:
    case Hexagon::S2_asr_i_r_acc:
    case Hexagon::S2_asr_i_r_and:
    case Hexagon::S2_asr_i_r_nac:
    case Hexagon::S2_asr_i_r_or:
    case Hexagon::S2_lsr_i_r_acc:
    case Hexagon::S2_lsr_i_r_and:
    case Hexagon::S2_lsr_i_r_nac:
    case Hexagon::S2_lsr_i_r_or:
    case Hexagon::S2_lsr_i_r_xacc:
    case Hexagon::S6_rol_i_r_acc:
    case Hexagon::S6_rol_i_r_and:
    case Hexagon::S6_rol_i_r_nac:
    case Hexagon::S6_rol_i_r_or:
    case Hexagon::S6_rol_i_r_xacc: {
      switch (OpNum) {
      case 3:
        // op: Ii
        return 8;
      case 2:
        // op: Rs32
        return 16;
      case 0:
        // op: Rx32
        return 0;
      }
      break;
    }
    case Hexagon::S2_asl_i_p_acc:
    case Hexagon::S2_asl_i_p_and:
    case Hexagon::S2_asl_i_p_nac:
    case Hexagon::S2_asl_i_p_or:
    case Hexagon::S2_asl_i_p_xacc:
    case Hexagon::S2_asr_i_p_acc:
    case Hexagon::S2_asr_i_p_and:
    case Hexagon::S2_asr_i_p_nac:
    case Hexagon::S2_asr_i_p_or:
    case Hexagon::S2_lsr_i_p_acc:
    case Hexagon::S2_lsr_i_p_and:
    case Hexagon::S2_lsr_i_p_nac:
    case Hexagon::S2_lsr_i_p_or:
    case Hexagon::S2_lsr_i_p_xacc:
    case Hexagon::S6_rol_i_p_acc:
    case Hexagon::S6_rol_i_p_and:
    case Hexagon::S6_rol_i_p_nac:
    case Hexagon::S6_rol_i_p_or:
    case Hexagon::S6_rol_i_p_xacc: {
      switch (OpNum) {
      case 3:
        // op: Ii
        return 8;
      case 2:
        // op: Rss32
        return 16;
      case 0:
        // op: Rxx32
        return 0;
      }
      break;
    }
    case Hexagon::S2_insert: {
      switch (OpNum) {
      case 3:
        // op: Ii
        return 8;
      case 4:
        // op: II
        return 5;
      case 2:
        // op: Rs32
        return 16;
      case 0:
        // op: Rx32
        return 0;
      }
      break;
    }
    case Hexagon::S2_insertp: {
      switch (OpNum) {
      case 3:
        // op: Ii
        return 8;
      case 4:
        // op: II
        return 5;
      case 2:
        // op: Rss32
        return 16;
      case 0:
        // op: Rxx32
        return 0;
      }
      break;
    }
    case Hexagon::L2_loadbsw2_pbr:
    case Hexagon::L2_loadbsw2_pcr:
    case Hexagon::L2_loadbsw2_pr:
    case Hexagon::L2_loadbzw2_pbr:
    case Hexagon::L2_loadbzw2_pcr:
    case Hexagon::L2_loadbzw2_pr:
    case Hexagon::L2_loadrb_pbr:
    case Hexagon::L2_loadrb_pcr:
    case Hexagon::L2_loadrb_pr:
    case Hexagon::L2_loadrh_pbr:
    case Hexagon::L2_loadrh_pcr:
    case Hexagon::L2_loadrh_pr:
    case Hexagon::L2_loadri_pbr:
    case Hexagon::L2_loadri_pcr:
    case Hexagon::L2_loadri_pr:
    case Hexagon::L2_loadrub_pbr:
    case Hexagon::L2_loadrub_pcr:
    case Hexagon::L2_loadrub_pr:
    case Hexagon::L2_loadruh_pbr:
    case Hexagon::L2_loadruh_pcr:
    case Hexagon::L2_loadruh_pr: {
      switch (OpNum) {
      case 3:
        // op: Mu2
        return 13;
      case 0:
        // op: Rd32
        return 0;
      case 1:
        // op: Rx32
        return 16;
      }
      break;
    }
    case Hexagon::L2_loadbsw4_pbr:
    case Hexagon::L2_loadbsw4_pcr:
    case Hexagon::L2_loadbsw4_pr:
    case Hexagon::L2_loadbzw4_pbr:
    case Hexagon::L2_loadbzw4_pcr:
    case Hexagon::L2_loadbzw4_pr:
    case Hexagon::L2_loadrd_pbr:
    case Hexagon::L2_loadrd_pcr:
    case Hexagon::L2_loadrd_pr: {
      switch (OpNum) {
      case 3:
        // op: Mu2
        return 13;
      case 0:
        // op: Rdd32
        return 0;
      case 1:
        // op: Rx32
        return 16;
      }
      break;
    }
    case Hexagon::V6_vL32Ub_ppu:
    case Hexagon::V6_vL32b_cur_ppu:
    case Hexagon::V6_vL32b_nt_cur_ppu:
    case Hexagon::V6_vL32b_nt_ppu:
    case Hexagon::V6_vL32b_nt_tmp_ppu:
    case Hexagon::V6_vL32b_ppu:
    case Hexagon::V6_vL32b_tmp_ppu: {
      switch (OpNum) {
      case 3:
        // op: Mu2
        return 13;
      case 0:
        // op: Vd32
        return 0;
      case 1:
        // op: Rx32
        return 16;
      }
      break;
    }
    case Hexagon::A5_ACS: {
      switch (OpNum) {
      case 3:
        // op: Rss32
        return 16;
      case 4:
        // op: Rtt32
        return 8;
      case 0:
        // op: Rxx32
        return 0;
      case 1:
        // op: Pe4
        return 5;
      }
      break;
    }
    case Hexagon::V6_vrmpyzbb_rx_acc:
    case Hexagon::V6_vrmpyzbub_rx_acc:
    case Hexagon::V6_vrmpyzcb_rx_acc:
    case Hexagon::V6_vrmpyzcbs_rx_acc:
    case Hexagon::V6_vrmpyznb_rx_acc: {
      switch (OpNum) {
      case 3:
        // op: Vu32
        return 8;
      case 0:
        // op: Vyyyy32
        return 0;
      case 1:
        // op: Rx8
        return 16;
      }
      break;
    }
    case Hexagon::L2_loadalignb_pi:
    case Hexagon::L2_loadalignh_pi: {
      switch (OpNum) {
      case 4:
        // op: Ii
        return 5;
      case 0:
        // op: Ryy32
        return 0;
      case 1:
        // op: Rx32
        return 16;
      }
      break;
    }
    case Hexagon::L2_ploadrbf_pi:
    case Hexagon::L2_ploadrbfnew_pi:
    case Hexagon::L2_ploadrbt_pi:
    case Hexagon::L2_ploadrbtnew_pi:
    case Hexagon::L2_ploadrhf_pi:
    case Hexagon::L2_ploadrhfnew_pi:
    case Hexagon::L2_ploadrht_pi:
    case Hexagon::L2_ploadrhtnew_pi:
    case Hexagon::L2_ploadrif_pi:
    case Hexagon::L2_ploadrifnew_pi:
    case Hexagon::L2_ploadrit_pi:
    case Hexagon::L2_ploadritnew_pi:
    case Hexagon::L2_ploadrubf_pi:
    case Hexagon::L2_ploadrubfnew_pi:
    case Hexagon::L2_ploadrubt_pi:
    case Hexagon::L2_ploadrubtnew_pi:
    case Hexagon::L2_ploadruhf_pi:
    case Hexagon::L2_ploadruhfnew_pi:
    case Hexagon::L2_ploadruht_pi:
    case Hexagon::L2_ploadruhtnew_pi: {
      switch (OpNum) {
      case 4:
        // op: Ii
        return 5;
      case 2:
        // op: Pt4
        return 9;
      case 0:
        // op: Rd32
        return 0;
      case 1:
        // op: Rx32
        return 16;
      }
      break;
    }
    case Hexagon::L2_ploadrdf_pi:
    case Hexagon::L2_ploadrdfnew_pi:
    case Hexagon::L2_ploadrdt_pi:
    case Hexagon::L2_ploadrdtnew_pi: {
      switch (OpNum) {
      case 4:
        // op: Ii
        return 5;
      case 2:
        // op: Pt4
        return 9;
      case 0:
        // op: Rdd32
        return 0;
      case 1:
        // op: Rx32
        return 16;
      }
      break;
    }
    case Hexagon::S4_vrcrotate_acc: {
      switch (OpNum) {
      case 4:
        // op: Ii
        return 5;
      case 2:
        // op: Rss32
        return 16;
      case 3:
        // op: Rt32
        return 8;
      case 0:
        // op: Rxx32
        return 0;
      }
      break;
    }
    case Hexagon::V6_vlutvvb_oracci: {
      switch (OpNum) {
      case 4:
        // op: Ii
        return 5;
      case 2:
        // op: Vu32
        return 8;
      case 3:
        // op: Vv32
        return 16;
      case 0:
        // op: Vx32
        return 0;
      }
      break;
    }
    case Hexagon::V6_vlutvwh_oracci: {
      switch (OpNum) {
      case 4:
        // op: Ii
        return 5;
      case 2:
        // op: Vu32
        return 8;
      case 3:
        // op: Vv32
        return 16;
      case 0:
        // op: Vxx32
        return 0;
      }
      break;
    }
    case Hexagon::V6_vrmpybusi_acc:
    case Hexagon::V6_vrmpyubi_acc:
    case Hexagon::V6_vrsadubi_acc: {
      switch (OpNum) {
      case 4:
        // op: Ii
        return 5;
      case 2:
        // op: Vuu32
        return 8;
      case 3:
        // op: Rt32
        return 16;
      case 0:
        // op: Vxx32
        return 0;
      }
      break;
    }
    case Hexagon::V6_v6mpyhubs10_vxx:
    case Hexagon::V6_v6mpyvubs10_vxx: {
      switch (OpNum) {
      case 4:
        // op: Ii
        return 5;
      case 2:
        // op: Vuu32
        return 8;
      case 3:
        // op: Vvv32
        return 16;
      case 0:
        // op: Vxx32
        return 0;
      }
      break;
    }
    case Hexagon::L2_loadalignb_pci:
    case Hexagon::L2_loadalignh_pci: {
      switch (OpNum) {
      case 4:
        // op: Ii
        return 5;
      case 5:
        // op: Mu2
        return 13;
      case 0:
        // op: Ryy32
        return 0;
      case 1:
        // op: Rx32
        return 16;
      }
      break;
    }
    case Hexagon::L4_ploadrbf_rr:
    case Hexagon::L4_ploadrbfnew_rr:
    case Hexagon::L4_ploadrbt_rr:
    case Hexagon::L4_ploadrbtnew_rr:
    case Hexagon::L4_ploadrhf_rr:
    case Hexagon::L4_ploadrhfnew_rr:
    case Hexagon::L4_ploadrht_rr:
    case Hexagon::L4_ploadrhtnew_rr:
    case Hexagon::L4_ploadrif_rr:
    case Hexagon::L4_ploadrifnew_rr:
    case Hexagon::L4_ploadrit_rr:
    case Hexagon::L4_ploadritnew_rr:
    case Hexagon::L4_ploadrubf_rr:
    case Hexagon::L4_ploadrubfnew_rr:
    case Hexagon::L4_ploadrubt_rr:
    case Hexagon::L4_ploadrubtnew_rr:
    case Hexagon::L4_ploadruhf_rr:
    case Hexagon::L4_ploadruhfnew_rr:
    case Hexagon::L4_ploadruht_rr:
    case Hexagon::L4_ploadruhtnew_rr: {
      switch (OpNum) {
      case 4:
        // op: Ii
        return 7;
      case 1:
        // op: Pv4
        return 5;
      case 2:
        // op: Rs32
        return 16;
      case 3:
        // op: Rt32
        return 8;
      case 0:
        // op: Rd32
        return 0;
      }
      break;
    }
    case Hexagon::L4_ploadrdf_rr:
    case Hexagon::L4_ploadrdfnew_rr:
    case Hexagon::L4_ploadrdt_rr:
    case Hexagon::L4_ploadrdtnew_rr: {
      switch (OpNum) {
      case 4:
        // op: Ii
        return 7;
      case 1:
        // op: Pv4
        return 5;
      case 2:
        // op: Rs32
        return 16;
      case 3:
        // op: Rt32
        return 8;
      case 0:
        // op: Rdd32
        return 0;
      }
      break;
    }
    case Hexagon::V6_vL32b_cur_npred_pi:
    case Hexagon::V6_vL32b_cur_pred_pi:
    case Hexagon::V6_vL32b_npred_pi:
    case Hexagon::V6_vL32b_nt_cur_npred_pi:
    case Hexagon::V6_vL32b_nt_cur_pred_pi:
    case Hexagon::V6_vL32b_nt_npred_pi:
    case Hexagon::V6_vL32b_nt_pred_pi:
    case Hexagon::V6_vL32b_nt_tmp_npred_pi:
    case Hexagon::V6_vL32b_nt_tmp_pred_pi:
    case Hexagon::V6_vL32b_pred_pi:
    case Hexagon::V6_vL32b_tmp_npred_pi:
    case Hexagon::V6_vL32b_tmp_pred_pi: {
      switch (OpNum) {
      case 4:
        // op: Ii
        return 8;
      case 2:
        // op: Pv4
        return 11;
      case 0:
        // op: Vd32
        return 0;
      case 1:
        // op: Rx32
        return 16;
      }
      break;
    }
    case Hexagon::L2_loadalignb_pbr:
    case Hexagon::L2_loadalignb_pcr:
    case Hexagon::L2_loadalignb_pr:
    case Hexagon::L2_loadalignh_pbr:
    case Hexagon::L2_loadalignh_pcr:
    case Hexagon::L2_loadalignh_pr: {
      switch (OpNum) {
      case 4:
        // op: Mu2
        return 13;
      case 0:
        // op: Ryy32
        return 0;
      case 1:
        // op: Rx32
        return 16;
      }
      break;
    }
    case Hexagon::V6_vdeal:
    case Hexagon::V6_vshuff: {
      switch (OpNum) {
      case 4:
        // op: Rt32
        return 16;
      case 0:
        // op: Vy32
        return 8;
      case 1:
        // op: Vx32
        return 0;
      }
      break;
    }
  }
  std::string msg;
  raw_string_ostream Msg(msg);
  Msg << "Not supported instr[opcode]: " << MI << "[" << OpNum << "]";
  report_fatal_error(Msg.str().c_str());
}

#endif // GET_OPERAND_BIT_OFFSET