llvm/lib/Target/Lanai/LanaiGenInstrInfo.inc

/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
|*                                                                            *|
|* Target Instruction Enum Values and Descriptors                             *|
|*                                                                            *|
|* Automatically generated file, do not edit!                                 *|
|*                                                                            *|
\*===----------------------------------------------------------------------===*/

#ifdef GET_INSTRINFO_ENUM
#undef GET_INSTRINFO_ENUM
namespace llvm {

namespace Lanai {
  enum { … };

} // end namespace Lanai
} // end namespace llvm
#endif // GET_INSTRINFO_ENUM

#ifdef GET_INSTRINFO_SCHED_ENUM
#undef GET_INSTRINFO_SCHED_ENUM
namespace llvm {

namespace Lanai {
namespace Sched {
  enum {
    NoInstrModel	= 0,
    IIC_ALU_WriteALU	= 1,
    IIC_ALU	= 2,
    IIC_LD_WriteLD	= 3,
    IIC_LDSW_WriteLDSW	= 4,
    WriteLD	= 5,
    IIC_ST_WriteST	= 6,
    IIC_STSW_WriteSTSW	= 7,
    SCHED_LIST_END = 8
  };
} // end namespace Sched
} // end namespace Lanai
} // end namespace llvm
#endif // GET_INSTRINFO_SCHED_ENUM

#if defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
namespace llvm {

struct LanaiInstrTable {
  MCInstrDesc Insts[395];
  static_assert(alignof(MCInstrDesc) >= alignof(MCOperandInfo), "Unwanted padding between Insts and OperandInfo");
  MCOperandInfo OperandInfo[178];
  static_assert(alignof(MCOperandInfo) >= alignof(MCPhysReg), "Unwanted padding between OperandInfo and ImplicitOps");
  MCPhysReg ImplicitOps[8];
};

} // end namespace llvm
#endif // defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)

#ifdef GET_INSTRINFO_MC_DESC
#undef GET_INSTRINFO_MC_DESC
namespace llvm {

static_assert(sizeof(MCOperandInfo) % sizeof(MCPhysReg) == 0);
static constexpr unsigned LanaiImpOpBase = sizeof LanaiInstrTable::OperandInfo / (sizeof(MCPhysReg));

extern const LanaiInstrTable LanaiDescs = {
  {
    { 394,	4,	1,	4,	1,	0,	0,	LanaiImpOpBase + 0,	158,	0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #394 = XOR_R
    { 393,	3,	1,	4,	1,	0,	0,	LanaiImpOpBase + 0,	155,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #393 = XOR_I_LO
    { 392,	3,	1,	4,	1,	0,	0,	LanaiImpOpBase + 0,	155,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #392 = XOR_I_HI
    { 391,	4,	1,	4,	1,	0,	1,	LanaiImpOpBase + 6,	158,	0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #391 = XOR_F_R
    { 390,	3,	1,	4,	1,	0,	1,	LanaiImpOpBase + 6,	155,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #390 = XOR_F_I_LO
    { 389,	3,	1,	4,	1,	0,	1,	LanaiImpOpBase + 6,	155,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #389 = XOR_F_I_HI
    { 388,	2,	1,	4,	1,	0,	0,	LanaiImpOpBase + 0,	152,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #388 = TRAILZ
    { 387,	4,	0,	4,	6,	0,	0,	LanaiImpOpBase + 0,	170,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #387 = SW_RR
    { 386,	4,	0,	4,	6,	0,	0,	LanaiImpOpBase + 0,	166,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #386 = SW_RI
    { 385,	4,	1,	4,	1,	0,	0,	LanaiImpOpBase + 0,	158,	0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #385 = SUB_R
    { 384,	3,	1,	4,	1,	0,	0,	LanaiImpOpBase + 0,	155,	0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #384 = SUB_I_LO
    { 383,	3,	1,	4,	1,	0,	0,	LanaiImpOpBase + 0,	155,	0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #383 = SUB_I_HI
    { 382,	4,	1,	4,	1,	0,	1,	LanaiImpOpBase + 6,	158,	0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #382 = SUB_F_R
    { 381,	3,	1,	4,	1,	0,	1,	LanaiImpOpBase + 6,	155,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #381 = SUB_F_I_LO
    { 380,	3,	1,	4,	1,	0,	1,	LanaiImpOpBase + 6,	155,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #380 = SUB_F_I_HI
    { 379,	4,	1,	4,	1,	1,	0,	LanaiImpOpBase + 6,	158,	0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #379 = SUBB_R
    { 378,	3,	1,	4,	1,	1,	0,	LanaiImpOpBase + 6,	155,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #378 = SUBB_I_LO
    { 377,	3,	1,	4,	1,	1,	0,	LanaiImpOpBase + 6,	155,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #377 = SUBB_I_HI
    { 376,	4,	1,	4,	1,	1,	1,	LanaiImpOpBase + 4,	158,	0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #376 = SUBB_F_R
    { 375,	3,	1,	4,	1,	1,	1,	LanaiImpOpBase + 4,	155,	0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #375 = SUBB_F_I_LO
    { 374,	3,	1,	4,	1,	1,	1,	LanaiImpOpBase + 4,	155,	0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #374 = SUBB_F_I_HI
    { 373,	4,	0,	4,	6,	0,	0,	LanaiImpOpBase + 0,	170,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #373 = STH_RR
    { 372,	4,	0,	4,	7,	0,	0,	LanaiImpOpBase + 0,	166,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #372 = STH_RI
    { 371,	4,	0,	4,	6,	0,	0,	LanaiImpOpBase + 0,	170,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #371 = STB_RR
    { 370,	4,	0,	4,	7,	0,	0,	LanaiImpOpBase + 0,	166,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #370 = STB_RI
    { 369,	2,	0,	4,	6,	0,	0,	LanaiImpOpBase + 0,	162,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #369 = STADDR
    { 368,	4,	1,	4,	1,	0,	0,	LanaiImpOpBase + 0,	158,	0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #368 = SRL_R
    { 367,	4,	1,	4,	1,	0,	1,	LanaiImpOpBase + 6,	158,	0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #367 = SRL_F_R
    { 366,	4,	1,	4,	1,	0,	0,	LanaiImpOpBase + 0,	158,	0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #366 = SRA_R
    { 365,	4,	1,	4,	1,	0,	1,	LanaiImpOpBase + 6,	158,	0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #365 = SRA_F_R
    { 364,	3,	1,	4,	1,	0,	0,	LanaiImpOpBase + 0,	155,	0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #364 = SL_I
    { 363,	3,	1,	4,	1,	0,	1,	LanaiImpOpBase + 6,	155,	0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #363 = SL_F_I
    { 362,	2,	1,	4,	0,	0,	0,	LanaiImpOpBase + 0,	162,	0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #362 = SLI
    { 361,	4,	1,	4,	1,	0,	0,	LanaiImpOpBase + 0,	158,	0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #361 = SHL_R
    { 360,	4,	1,	4,	1,	0,	1,	LanaiImpOpBase + 6,	158,	0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #360 = SHL_F_R
    { 359,	2,	0,	4,	1,	0,	1,	LanaiImpOpBase + 6,	152,	0|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #359 = SFSUB_F_RR
    { 358,	2,	0,	4,	1,	0,	1,	LanaiImpOpBase + 6,	162,	0|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #358 = SFSUB_F_RI_LO
    { 357,	2,	0,	4,	1,	0,	1,	LanaiImpOpBase + 6,	162,	0|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #357 = SFSUB_F_RI_HI
    { 356,	4,	1,	4,	1,	1,	0,	LanaiImpOpBase + 6,	174,	0|(1ULL<<MCID::Select)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #356 = SELECT
    { 355,	2,	1,	4,	2,	1,	0,	LanaiImpOpBase + 6,	162,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #355 = SCC
    { 354,	3,	1,	4,	1,	0,	0,	LanaiImpOpBase + 0,	155,	0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #354 = SA_I
    { 353,	3,	1,	4,	1,	0,	1,	LanaiImpOpBase + 6,	155,	0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #353 = SA_F_I
    { 352,	0,	0,	4,	0,	1,	0,	LanaiImpOpBase + 7,	1,	0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #352 = RET
    { 351,	2,	1,	4,	1,	0,	0,	LanaiImpOpBase + 0,	152,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #351 = POPC
    { 350,	4,	1,	4,	1,	0,	0,	LanaiImpOpBase + 0,	158,	0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #350 = OR_R
    { 349,	3,	1,	4,	1,	0,	0,	LanaiImpOpBase + 0,	155,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #349 = OR_I_LO
    { 348,	3,	1,	4,	1,	0,	0,	LanaiImpOpBase + 0,	155,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #348 = OR_I_HI
    { 347,	4,	1,	4,	1,	0,	1,	LanaiImpOpBase + 6,	158,	0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #347 = OR_F_R
    { 346,	3,	1,	4,	1,	0,	1,	LanaiImpOpBase + 6,	155,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #346 = OR_F_I_LO
    { 345,	3,	1,	4,	1,	0,	1,	LanaiImpOpBase + 6,	155,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #345 = OR_F_I_HI
    { 344,	0,	0,	4,	0,	0,	0,	LanaiImpOpBase + 0,	1,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #344 = NOP
    { 343,	2,	1,	4,	1,	0,	0,	LanaiImpOpBase + 0,	162,	0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #343 = MOVHI
    { 342,	0,	0,	4,	0,	0,	0,	LanaiImpOpBase + 0,	1,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #342 = LOG4
    { 341,	0,	0,	4,	0,	0,	0,	LanaiImpOpBase + 0,	1,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #341 = LOG3
    { 340,	0,	0,	4,	0,	0,	0,	LanaiImpOpBase + 0,	1,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #340 = LOG2
    { 339,	0,	0,	4,	0,	0,	0,	LanaiImpOpBase + 0,	1,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #339 = LOG1
    { 338,	0,	0,	4,	0,	0,	0,	LanaiImpOpBase + 0,	1,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #338 = LOG0
    { 337,	2,	1,	4,	1,	0,	0,	LanaiImpOpBase + 0,	152,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #337 = LEADZ
    { 336,	4,	1,	4,	5,	0,	0,	LanaiImpOpBase + 0,	170,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #336 = LDWz_RR
    { 335,	4,	1,	4,	5,	0,	0,	LanaiImpOpBase + 0,	170,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #335 = LDW_RR
    { 334,	4,	1,	4,	3,	0,	0,	LanaiImpOpBase + 0,	166,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #334 = LDW_RI
    { 333,	4,	1,	4,	5,	0,	0,	LanaiImpOpBase + 0,	170,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #333 = LDHz_RR
    { 332,	4,	1,	4,	4,	0,	0,	LanaiImpOpBase + 0,	166,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #332 = LDHz_RI
    { 331,	4,	1,	4,	5,	0,	0,	LanaiImpOpBase + 0,	170,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #331 = LDHs_RR
    { 330,	4,	1,	4,	4,	0,	0,	LanaiImpOpBase + 0,	166,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #330 = LDHs_RI
    { 329,	4,	1,	4,	5,	0,	0,	LanaiImpOpBase + 0,	170,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #329 = LDBz_RR
    { 328,	4,	1,	4,	4,	0,	0,	LanaiImpOpBase + 0,	166,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #328 = LDBz_RI
    { 327,	4,	1,	4,	5,	0,	0,	LanaiImpOpBase + 0,	170,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #327 = LDBs_RR
    { 326,	4,	1,	4,	4,	0,	0,	LanaiImpOpBase + 0,	166,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #326 = LDBs_RI
    { 325,	2,	1,	4,	3,	0,	0,	LanaiImpOpBase + 0,	162,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #325 = LDADDR
    { 324,	1,	0,	4,	1,	0,	0,	LanaiImpOpBase + 0,	154,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #324 = JR
    { 323,	1,	0,	4,	2,	0,	0,	LanaiImpOpBase + 0,	0,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #323 = BT
    { 322,	2,	0,	4,	0,	1,	0,	LanaiImpOpBase + 6,	164,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #322 = BRR
    { 321,	3,	0,	4,	1,	1,	0,	LanaiImpOpBase + 6,	155,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #321 = BRIND_CCA
    { 320,	2,	0,	4,	1,	1,	0,	LanaiImpOpBase + 6,	162,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #320 = BRIND_CC
    { 319,	2,	0,	4,	2,	1,	0,	LanaiImpOpBase + 6,	13,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #319 = BRCC
    { 318,	4,	1,	4,	1,	0,	0,	LanaiImpOpBase + 0,	158,	0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #318 = AND_R
    { 317,	3,	1,	4,	1,	0,	0,	LanaiImpOpBase + 0,	155,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #317 = AND_I_LO
    { 316,	3,	1,	4,	1,	0,	0,	LanaiImpOpBase + 0,	155,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #316 = AND_I_HI
    { 315,	4,	1,	4,	1,	0,	1,	LanaiImpOpBase + 6,	158,	0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #315 = AND_F_R
    { 314,	3,	1,	4,	1,	0,	1,	LanaiImpOpBase + 6,	155,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #314 = AND_F_I_LO
    { 313,	3,	1,	4,	1,	0,	1,	LanaiImpOpBase + 6,	155,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #313 = AND_F_I_HI
    { 312,	4,	1,	4,	1,	0,	0,	LanaiImpOpBase + 0,	158,	0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #312 = ADD_R
    { 311,	3,	1,	4,	1,	0,	0,	LanaiImpOpBase + 0,	155,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #311 = ADD_I_LO
    { 310,	3,	1,	4,	1,	0,	0,	LanaiImpOpBase + 0,	155,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #310 = ADD_I_HI
    { 309,	4,	1,	4,	1,	0,	1,	LanaiImpOpBase + 6,	158,	0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #309 = ADD_F_R
    { 308,	3,	1,	4,	1,	0,	1,	LanaiImpOpBase + 6,	155,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #308 = ADD_F_I_LO
    { 307,	3,	1,	4,	1,	0,	1,	LanaiImpOpBase + 6,	155,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #307 = ADD_F_I_HI
    { 306,	4,	1,	4,	1,	1,	0,	LanaiImpOpBase + 6,	158,	0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #306 = ADDC_R
    { 305,	3,	1,	4,	1,	1,	0,	LanaiImpOpBase + 6,	155,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #305 = ADDC_I_LO
    { 304,	3,	1,	4,	1,	1,	0,	LanaiImpOpBase + 6,	155,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #304 = ADDC_I_HI
    { 303,	4,	1,	4,	1,	1,	1,	LanaiImpOpBase + 4,	158,	0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #303 = ADDC_F_R
    { 302,	3,	1,	4,	1,	1,	1,	LanaiImpOpBase + 4,	155,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #302 = ADDC_F_I_LO
    { 301,	3,	1,	4,	1,	1,	1,	LanaiImpOpBase + 4,	155,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #301 = ADDC_F_I_HI
    { 300,	1,	0,	4,	0,	1,	1,	LanaiImpOpBase + 2,	154,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #300 = CALLR
    { 299,	1,	0,	4,	0,	1,	1,	LanaiImpOpBase + 2,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #299 = CALL
    { 298,	2,	1,	4,	0,	1,	1,	LanaiImpOpBase + 0,	152,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #298 = ADJDYNALLOC
    { 297,	2,	0,	4,	0,	1,	1,	LanaiImpOpBase + 0,	21,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #297 = ADJCALLSTACKUP
    { 296,	2,	0,	4,	0,	1,	1,	LanaiImpOpBase + 0,	21,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #296 = ADJCALLSTACKDOWN
    { 295,	4,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	148,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #295 = G_UBFX
    { 294,	4,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	148,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #294 = G_SBFX
    { 293,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #293 = G_VECREDUCE_UMIN
    { 292,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #292 = G_VECREDUCE_UMAX
    { 291,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #291 = G_VECREDUCE_SMIN
    { 290,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #290 = G_VECREDUCE_SMAX
    { 289,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #289 = G_VECREDUCE_XOR
    { 288,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #288 = G_VECREDUCE_OR
    { 287,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #287 = G_VECREDUCE_AND
    { 286,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #286 = G_VECREDUCE_MUL
    { 285,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #285 = G_VECREDUCE_ADD
    { 284,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #284 = G_VECREDUCE_FMINIMUM
    { 283,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #283 = G_VECREDUCE_FMAXIMUM
    { 282,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #282 = G_VECREDUCE_FMIN
    { 281,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #281 = G_VECREDUCE_FMAX
    { 280,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #280 = G_VECREDUCE_FMUL
    { 279,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #279 = G_VECREDUCE_FADD
    { 278,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	131,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #278 = G_VECREDUCE_SEQ_FMUL
    { 277,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	131,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #277 = G_VECREDUCE_SEQ_FADD
    { 276,	1,	0,	0,	0,	0,	0,	LanaiImpOpBase + 0,	1,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #276 = G_UBSANTRAP
    { 275,	0,	0,	0,	0,	0,	0,	LanaiImpOpBase + 0,	1,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #275 = G_DEBUGTRAP
    { 274,	0,	0,	0,	0,	0,	0,	LanaiImpOpBase + 0,	1,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #274 = G_TRAP
    { 273,	3,	0,	0,	0,	0,	0,	LanaiImpOpBase + 0,	58,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #273 = G_BZERO
    { 272,	4,	0,	0,	0,	0,	0,	LanaiImpOpBase + 0,	144,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #272 = G_MEMSET
    { 271,	4,	0,	0,	0,	0,	0,	LanaiImpOpBase + 0,	144,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #271 = G_MEMMOVE
    { 270,	3,	0,	0,	0,	0,	0,	LanaiImpOpBase + 0,	131,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #270 = G_MEMCPY_INLINE
    { 269,	4,	0,	0,	0,	0,	0,	LanaiImpOpBase + 0,	144,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #269 = G_MEMCPY
    { 268,	2,	0,	0,	0,	0,	0,	LanaiImpOpBase + 0,	142,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL },  // Inst #268 = G_WRITE_REGISTER
    { 267,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	51,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL },  // Inst #267 = G_READ_REGISTER
    { 266,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	101,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #266 = G_STRICT_FLDEXP
    { 265,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #265 = G_STRICT_FSQRT
    { 264,	4,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	46,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #264 = G_STRICT_FMA
    { 263,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #263 = G_STRICT_FREM
    { 262,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #262 = G_STRICT_FDIV
    { 261,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #261 = G_STRICT_FMUL
    { 260,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #260 = G_STRICT_FSUB
    { 259,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #259 = G_STRICT_FADD
    { 258,	1,	0,	0,	0,	0,	0,	LanaiImpOpBase + 0,	50,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #258 = G_STACKRESTORE
    { 257,	1,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	50,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #257 = G_STACKSAVE
    { 256,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	69,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #256 = G_DYN_STACKALLOC
    { 255,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	51,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #255 = G_JUMP_TABLE
    { 254,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	51,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #254 = G_BLOCK_ADDR
    { 253,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #253 = G_ADDRSPACE_CAST
    { 252,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #252 = G_FNEARBYINT
    { 251,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #251 = G_FRINT
    { 250,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #250 = G_FFLOOR
    { 249,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #249 = G_FSQRT
    { 248,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #248 = G_FTANH
    { 247,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #247 = G_FSINH
    { 246,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #246 = G_FCOSH
    { 245,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #245 = G_FATAN
    { 244,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #244 = G_FASIN
    { 243,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #243 = G_FACOS
    { 242,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #242 = G_FTAN
    { 241,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #241 = G_FSIN
    { 240,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #240 = G_FCOS
    { 239,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #239 = G_FCEIL
    { 238,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #238 = G_BITREVERSE
    { 237,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #237 = G_BSWAP
    { 236,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #236 = G_CTPOP
    { 235,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #235 = G_CTLZ_ZERO_UNDEF
    { 234,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #234 = G_CTLZ
    { 233,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #233 = G_CTTZ_ZERO_UNDEF
    { 232,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #232 = G_CTTZ
    { 231,	4,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	138,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #231 = G_VECTOR_COMPRESS
    { 230,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #230 = G_SPLAT_VECTOR
    { 229,	4,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	134,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #229 = G_SHUFFLE_VECTOR
    { 228,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	131,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #228 = G_EXTRACT_VECTOR_ELT
    { 227,	4,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	127,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #227 = G_INSERT_VECTOR_ELT
    { 226,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	40,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #226 = G_EXTRACT_SUBVECTOR
    { 225,	4,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	63,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #225 = G_INSERT_SUBVECTOR
    { 224,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	51,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #224 = G_VSCALE
    { 223,	3,	0,	0,	0,	0,	0,	LanaiImpOpBase + 0,	124,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #223 = G_BRJT
    { 222,	1,	0,	0,	0,	0,	0,	LanaiImpOpBase + 0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #222 = G_BR
    { 221,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #221 = G_LLROUND
    { 220,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #220 = G_LROUND
    { 219,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #219 = G_ABS
    { 218,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #218 = G_UMAX
    { 217,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #217 = G_UMIN
    { 216,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #216 = G_SMAX
    { 215,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #215 = G_SMIN
    { 214,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	101,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #214 = G_PTRMASK
    { 213,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	101,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #213 = G_PTR_ADD
    { 212,	0,	0,	0,	0,	0,	0,	LanaiImpOpBase + 0,	1,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #212 = G_RESET_FPMODE
    { 211,	1,	0,	0,	0,	0,	0,	LanaiImpOpBase + 0,	50,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #211 = G_SET_FPMODE
    { 210,	1,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	50,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #210 = G_GET_FPMODE
    { 209,	0,	0,	0,	0,	0,	0,	LanaiImpOpBase + 0,	1,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #209 = G_RESET_FPENV
    { 208,	1,	0,	0,	0,	0,	0,	LanaiImpOpBase + 0,	50,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #208 = G_SET_FPENV
    { 207,	1,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	50,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #207 = G_GET_FPENV
    { 206,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #206 = G_FMAXIMUM
    { 205,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #205 = G_FMINIMUM
    { 204,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #204 = G_FMAXNUM_IEEE
    { 203,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #203 = G_FMINNUM_IEEE
    { 202,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #202 = G_FMAXNUM
    { 201,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #201 = G_FMINNUM
    { 200,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #200 = G_FCANONICALIZE
    { 199,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	98,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #199 = G_IS_FPCLASS
    { 198,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	101,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #198 = G_FCOPYSIGN
    { 197,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #197 = G_FABS
    { 196,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #196 = G_UITOFP
    { 195,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #195 = G_SITOFP
    { 194,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #194 = G_FPTOUI
    { 193,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #193 = G_FPTOSI
    { 192,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #192 = G_FPTRUNC
    { 191,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #191 = G_FPEXT
    { 190,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #190 = G_FNEG
    { 189,	3,	2,	0,	0,	0,	0,	LanaiImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #189 = G_FFREXP
    { 188,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	101,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #188 = G_FLDEXP
    { 187,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #187 = G_FLOG10
    { 186,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #186 = G_FLOG2
    { 185,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #185 = G_FLOG
    { 184,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #184 = G_FEXP10
    { 183,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #183 = G_FEXP2
    { 182,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #182 = G_FEXP
    { 181,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	101,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #181 = G_FPOWI
    { 180,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #180 = G_FPOW
    { 179,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #179 = G_FREM
    { 178,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #178 = G_FDIV
    { 177,	4,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	46,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #177 = G_FMAD
    { 176,	4,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	46,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #176 = G_FMA
    { 175,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #175 = G_FMUL
    { 174,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #174 = G_FSUB
    { 173,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #173 = G_FADD
    { 172,	4,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	120,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #172 = G_UDIVFIXSAT
    { 171,	4,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	120,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #171 = G_SDIVFIXSAT
    { 170,	4,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	120,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #170 = G_UDIVFIX
    { 169,	4,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	120,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #169 = G_SDIVFIX
    { 168,	4,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	120,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #168 = G_UMULFIXSAT
    { 167,	4,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	120,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #167 = G_SMULFIXSAT
    { 166,	4,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	120,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #166 = G_UMULFIX
    { 165,	4,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	120,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #165 = G_SMULFIX
    { 164,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	101,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #164 = G_SSHLSAT
    { 163,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	101,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #163 = G_USHLSAT
    { 162,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #162 = G_SSUBSAT
    { 161,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #161 = G_USUBSAT
    { 160,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #160 = G_SADDSAT
    { 159,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #159 = G_UADDSAT
    { 158,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #158 = G_SMULH
    { 157,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #157 = G_UMULH
    { 156,	4,	2,	0,	0,	0,	0,	LanaiImpOpBase + 0,	87,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #156 = G_SMULO
    { 155,	4,	2,	0,	0,	0,	0,	LanaiImpOpBase + 0,	87,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #155 = G_UMULO
    { 154,	5,	2,	0,	0,	0,	0,	LanaiImpOpBase + 0,	115,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #154 = G_SSUBE
    { 153,	4,	2,	0,	0,	0,	0,	LanaiImpOpBase + 0,	87,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #153 = G_SSUBO
    { 152,	5,	2,	0,	0,	0,	0,	LanaiImpOpBase + 0,	115,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #152 = G_SADDE
    { 151,	4,	2,	0,	0,	0,	0,	LanaiImpOpBase + 0,	87,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #151 = G_SADDO
    { 150,	5,	2,	0,	0,	0,	0,	LanaiImpOpBase + 0,	115,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #150 = G_USUBE
    { 149,	4,	2,	0,	0,	0,	0,	LanaiImpOpBase + 0,	87,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #149 = G_USUBO
    { 148,	5,	2,	0,	0,	0,	0,	LanaiImpOpBase + 0,	115,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #148 = G_UADDE
    { 147,	4,	2,	0,	0,	0,	0,	LanaiImpOpBase + 0,	87,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #147 = G_UADDO
    { 146,	4,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	87,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #146 = G_SELECT
    { 145,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	112,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #145 = G_UCMP
    { 144,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	112,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #144 = G_SCMP
    { 143,	4,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	108,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #143 = G_FCMP
    { 142,	4,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	108,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #142 = G_ICMP
    { 141,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	101,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #141 = G_ROTL
    { 140,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	101,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #140 = G_ROTR
    { 139,	4,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	104,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #139 = G_FSHR
    { 138,	4,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	104,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #138 = G_FSHL
    { 137,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	101,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #137 = G_ASHR
    { 136,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	101,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #136 = G_LSHR
    { 135,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	101,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #135 = G_SHL
    { 134,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #134 = G_ZEXT
    { 133,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	40,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #133 = G_SEXT_INREG
    { 132,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #132 = G_SEXT
    { 131,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	98,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #131 = G_VAARG
    { 130,	1,	0,	0,	0,	0,	0,	LanaiImpOpBase + 0,	50,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #130 = G_VASTART
    { 129,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	51,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #129 = G_FCONSTANT
    { 128,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	51,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #128 = G_CONSTANT
    { 127,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #127 = G_TRUNC
    { 126,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #126 = G_ANYEXT
    { 125,	1,	0,	0,	0,	0,	0,	LanaiImpOpBase + 0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL },  // Inst #125 = G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
    { 124,	1,	0,	0,	0,	0,	0,	LanaiImpOpBase + 0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL },  // Inst #124 = G_INTRINSIC_CONVERGENT
    { 123,	1,	0,	0,	0,	0,	0,	LanaiImpOpBase + 0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #123 = G_INTRINSIC_W_SIDE_EFFECTS
    { 122,	1,	0,	0,	0,	0,	0,	LanaiImpOpBase + 0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #122 = G_INTRINSIC
    { 121,	0,	0,	0,	0,	0,	0,	LanaiImpOpBase + 0,	1,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #121 = G_INVOKE_REGION_START
    { 120,	1,	0,	0,	0,	0,	0,	LanaiImpOpBase + 0,	50,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #120 = G_BRINDIRECT
    { 119,	2,	0,	0,	0,	0,	0,	LanaiImpOpBase + 0,	51,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #119 = G_BRCOND
    { 118,	4,	0,	0,	0,	0,	0,	LanaiImpOpBase + 0,	94,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #118 = G_PREFETCH
    { 117,	2,	0,	0,	0,	0,	0,	LanaiImpOpBase + 0,	21,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #117 = G_FENCE
    { 116,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #116 = G_ATOMICRMW_UDEC_WRAP
    { 115,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #115 = G_ATOMICRMW_UINC_WRAP
    { 114,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #114 = G_ATOMICRMW_FMIN
    { 113,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #113 = G_ATOMICRMW_FMAX
    { 112,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #112 = G_ATOMICRMW_FSUB
    { 111,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #111 = G_ATOMICRMW_FADD
    { 110,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #110 = G_ATOMICRMW_UMIN
    { 109,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #109 = G_ATOMICRMW_UMAX
    { 108,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #108 = G_ATOMICRMW_MIN
    { 107,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #107 = G_ATOMICRMW_MAX
    { 106,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #106 = G_ATOMICRMW_XOR
    { 105,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #105 = G_ATOMICRMW_OR
    { 104,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #104 = G_ATOMICRMW_NAND
    { 103,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #103 = G_ATOMICRMW_AND
    { 102,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #102 = G_ATOMICRMW_SUB
    { 101,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #101 = G_ATOMICRMW_ADD
    { 100,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #100 = G_ATOMICRMW_XCHG
    { 99,	4,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	87,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #99 = G_ATOMIC_CMPXCHG
    { 98,	5,	2,	0,	0,	0,	0,	LanaiImpOpBase + 0,	82,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #98 = G_ATOMIC_CMPXCHG_WITH_SUCCESS
    { 97,	5,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	77,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #97 = G_INDEXED_STORE
    { 96,	2,	0,	0,	0,	0,	0,	LanaiImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #96 = G_STORE
    { 95,	5,	2,	0,	0,	0,	0,	LanaiImpOpBase + 0,	72,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #95 = G_INDEXED_ZEXTLOAD
    { 94,	5,	2,	0,	0,	0,	0,	LanaiImpOpBase + 0,	72,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #94 = G_INDEXED_SEXTLOAD
    { 93,	5,	2,	0,	0,	0,	0,	LanaiImpOpBase + 0,	72,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #93 = G_INDEXED_LOAD
    { 92,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #92 = G_ZEXTLOAD
    { 91,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #91 = G_SEXTLOAD
    { 90,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #90 = G_LOAD
    { 89,	1,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	50,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #89 = G_READSTEADYCOUNTER
    { 88,	1,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	50,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #88 = G_READCYCLECOUNTER
    { 87,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #87 = G_INTRINSIC_ROUNDEVEN
    { 86,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #86 = G_INTRINSIC_LLRINT
    { 85,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #85 = G_INTRINSIC_LRINT
    { 84,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #84 = G_INTRINSIC_ROUND
    { 83,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #83 = G_INTRINSIC_TRUNC
    { 82,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	69,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #82 = G_INTRINSIC_FPTRUNC_ROUND
    { 81,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #81 = G_CONSTANT_FOLD_BARRIER
    { 80,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #80 = G_FREEZE
    { 79,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #79 = G_BITCAST
    { 78,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #78 = G_INTTOPTR
    { 77,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #77 = G_PTRTOINT
    { 76,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #76 = G_CONCAT_VECTORS
    { 75,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #75 = G_BUILD_VECTOR_TRUNC
    { 74,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #74 = G_BUILD_VECTOR
    { 73,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #73 = G_MERGE_VALUES
    { 72,	4,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	63,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #72 = G_INSERT
    { 71,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #71 = G_UNMERGE_VALUES
    { 70,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	58,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #70 = G_EXTRACT
    { 69,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	51,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #69 = G_CONSTANT_POOL
    { 68,	5,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	53,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #68 = G_PTRAUTH_GLOBAL_VALUE
    { 67,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	51,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #67 = G_GLOBAL_VALUE
    { 66,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	51,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #66 = G_FRAME_INDEX
    { 65,	1,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	50,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #65 = G_PHI
    { 64,	1,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	50,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #64 = G_IMPLICIT_DEF
    { 63,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #63 = G_XOR
    { 62,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #62 = G_OR
    { 61,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #61 = G_AND
    { 60,	4,	2,	0,	0,	0,	0,	LanaiImpOpBase + 0,	46,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #60 = G_UDIVREM
    { 59,	4,	2,	0,	0,	0,	0,	LanaiImpOpBase + 0,	46,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #59 = G_SDIVREM
    { 58,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #58 = G_UREM
    { 57,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #57 = G_SREM
    { 56,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #56 = G_UDIV
    { 55,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #55 = G_SDIV
    { 54,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #54 = G_MUL
    { 53,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #53 = G_SUB
    { 52,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #52 = G_ADD
    { 51,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	40,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #51 = G_ASSERT_ALIGN
    { 50,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	40,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #50 = G_ASSERT_ZEXT
    { 49,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	40,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #49 = G_ASSERT_SEXT
    { 48,	1,	0,	0,	0,	0,	0,	LanaiImpOpBase + 0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL },  // Inst #48 = CONVERGENCECTRL_GLUE
    { 47,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	13,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL },  // Inst #47 = CONVERGENCECTRL_LOOP
    { 46,	1,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL },  // Inst #46 = CONVERGENCECTRL_ANCHOR
    { 45,	1,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL },  // Inst #45 = CONVERGENCECTRL_ENTRY
    { 44,	1,	0,	0,	0,	0,	0,	LanaiImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #44 = JUMP_TABLE_DEBUG_INFO
    { 43,	0,	0,	0,	0,	0,	0,	LanaiImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #43 = MEMBARRIER
    { 42,	0,	0,	0,	0,	0,	0,	LanaiImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #42 = FAKE_USE
    { 41,	0,	0,	0,	0,	0,	0,	LanaiImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #41 = ICALL_BRANCH_FUNNEL
    { 40,	3,	0,	0,	0,	0,	0,	LanaiImpOpBase + 0,	37,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #40 = PATCHABLE_TYPED_EVENT_CALL
    { 39,	2,	0,	0,	0,	0,	0,	LanaiImpOpBase + 0,	35,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #39 = PATCHABLE_EVENT_CALL
    { 38,	0,	0,	0,	0,	0,	0,	LanaiImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #38 = PATCHABLE_TAIL_CALL
    { 37,	0,	0,	0,	0,	0,	0,	LanaiImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #37 = PATCHABLE_FUNCTION_EXIT
    { 36,	0,	0,	0,	0,	0,	0,	LanaiImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #36 = PATCHABLE_RET
    { 35,	0,	0,	0,	0,	0,	0,	LanaiImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #35 = PATCHABLE_FUNCTION_ENTER
    { 34,	0,	0,	0,	0,	0,	0,	LanaiImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #34 = PATCHABLE_OP
    { 33,	1,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #33 = FAULTING_OP
    { 32,	2,	0,	0,	0,	0,	0,	LanaiImpOpBase + 0,	33,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #32 = LOCAL_ESCAPE
    { 31,	0,	0,	0,	0,	0,	0,	LanaiImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #31 = STATEPOINT
    { 30,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	30,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #30 = PREALLOCATED_ARG
    { 29,	1,	0,	0,	0,	0,	0,	LanaiImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #29 = PREALLOCATED_SETUP
    { 28,	1,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	29,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #28 = LOAD_STACK_GUARD
    { 27,	6,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	23,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #27 = PATCHPOINT
    { 26,	0,	0,	0,	0,	0,	0,	LanaiImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #26 = FENTRY_CALL
    { 25,	2,	0,	0,	0,	0,	0,	LanaiImpOpBase + 0,	21,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #25 = STACKMAP
    { 24,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	19,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #24 = ARITH_FENCE
    { 23,	4,	0,	0,	0,	0,	0,	LanaiImpOpBase + 0,	15,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #23 = PSEUDO_PROBE
    { 22,	1,	0,	0,	0,	0,	0,	LanaiImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #22 = LIFETIME_END
    { 21,	1,	0,	0,	0,	0,	0,	LanaiImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #21 = LIFETIME_START
    { 20,	0,	0,	0,	0,	0,	0,	LanaiImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #20 = BUNDLE
    { 19,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	13,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #19 = COPY
    { 18,	2,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	13,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #18 = REG_SEQUENCE
    { 17,	1,	0,	0,	0,	0,	0,	LanaiImpOpBase + 0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #17 = DBG_LABEL
    { 16,	0,	0,	0,	0,	0,	0,	LanaiImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #16 = DBG_PHI
    { 15,	0,	0,	0,	0,	0,	0,	LanaiImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #15 = DBG_INSTR_REF
    { 14,	0,	0,	0,	0,	0,	0,	LanaiImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #14 = DBG_VALUE_LIST
    { 13,	0,	0,	0,	0,	0,	0,	LanaiImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #13 = DBG_VALUE
    { 12,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #12 = COPY_TO_REGCLASS
    { 11,	4,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	9,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #11 = SUBREG_TO_REG
    { 10,	1,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #10 = IMPLICIT_DEF
    { 9,	4,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	5,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #9 = INSERT_SUBREG
    { 8,	3,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #8 = EXTRACT_SUBREG
    { 7,	0,	0,	0,	0,	0,	0,	LanaiImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #7 = KILL
    { 6,	1,	0,	0,	0,	0,	0,	LanaiImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #6 = ANNOTATION_LABEL
    { 5,	1,	0,	0,	0,	0,	0,	LanaiImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #5 = GC_LABEL
    { 4,	1,	0,	0,	0,	0,	0,	LanaiImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #4 = EH_LABEL
    { 3,	1,	0,	0,	0,	0,	0,	LanaiImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #3 = CFI_INSTRUCTION
    { 2,	0,	0,	0,	0,	0,	0,	LanaiImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #2 = INLINEASM_BR
    { 1,	0,	0,	0,	0,	0,	0,	LanaiImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1 = INLINEASM
    { 0,	1,	1,	0,	0,	0,	0,	LanaiImpOpBase + 0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #0 = PHI
  }, {
    /* 0 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 1 */
    /* 1 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 2 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 5 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 9 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 13 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 15 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 19 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) },
    /* 21 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 23 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 29 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 },
    /* 30 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 33 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 35 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 37 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 40 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
    /* 43 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
    /* 46 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
    /* 50 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
    /* 51 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 53 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 58 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
    /* 61 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
    /* 63 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
    /* 67 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
    /* 69 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 72 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 77 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 82 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
    /* 87 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
    /* 91 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
    /* 94 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 98 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 101 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
    /* 104 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
    /* 108 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
    /* 112 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
    /* 115 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
    /* 120 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
    /* 124 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
    /* 127 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
    /* 131 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
    /* 134 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 138 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
    /* 142 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
    /* 144 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
    /* 148 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
    /* 152 */ { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 154 */ { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 155 */ { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 158 */ { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 },
    /* 162 */ { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 164 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 166 */ { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Lanai::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 170 */ { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Lanai::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Lanai::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 174 */ { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
  }, {
    /* 0 */
    /* 0 */ Lanai::SP, Lanai::SP,
    /* 2 */ Lanai::SP, Lanai::RCA,
    /* 4 */ Lanai::SR, Lanai::SR,
    /* 6 */ Lanai::SR,
    /* 7 */ Lanai::RCA,
  }
};


#ifdef __GNUC__
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Woverlength-strings"
#endif
extern const char LanaiInstrNameData[] = {
  /* 0 */ "G_FLOG10\0"
  /* 9 */ "G_FEXP10\0"
  /* 18 */ "LOG0\0"
  /* 23 */ "LOG1\0"
  /* 28 */ "G_FLOG2\0"
  /* 36 */ "G_FEXP2\0"
  /* 44 */ "LOG3\0"
  /* 49 */ "LOG4\0"
  /* 54 */ "BRIND_CCA\0"
  /* 64 */ "G_FMA\0"
  /* 70 */ "G_STRICT_FMA\0"
  /* 83 */ "G_FSUB\0"
  /* 90 */ "G_STRICT_FSUB\0"
  /* 104 */ "G_ATOMICRMW_FSUB\0"
  /* 121 */ "G_SUB\0"
  /* 127 */ "G_ATOMICRMW_SUB\0"
  /* 143 */ "BRCC\0"
  /* 148 */ "SCC\0"
  /* 152 */ "BRIND_CC\0"
  /* 161 */ "G_INTRINSIC\0"
  /* 173 */ "G_FPTRUNC\0"
  /* 183 */ "G_INTRINSIC_TRUNC\0"
  /* 201 */ "G_TRUNC\0"
  /* 209 */ "G_BUILD_VECTOR_TRUNC\0"
  /* 230 */ "G_DYN_STACKALLOC\0"
  /* 247 */ "ADJDYNALLOC\0"
  /* 259 */ "POPC\0"
  /* 264 */ "G_FMAD\0"
  /* 271 */ "G_INDEXED_SEXTLOAD\0"
  /* 290 */ "G_SEXTLOAD\0"
  /* 301 */ "G_INDEXED_ZEXTLOAD\0"
  /* 320 */ "G_ZEXTLOAD\0"
  /* 331 */ "G_INDEXED_LOAD\0"
  /* 346 */ "G_LOAD\0"
  /* 353 */ "G_VECREDUCE_FADD\0"
  /* 370 */ "G_FADD\0"
  /* 377 */ "G_VECREDUCE_SEQ_FADD\0"
  /* 398 */ "G_STRICT_FADD\0"
  /* 412 */ "G_ATOMICRMW_FADD\0"
  /* 429 */ "G_VECREDUCE_ADD\0"
  /* 445 */ "G_ADD\0"
  /* 451 */ "G_PTR_ADD\0"
  /* 461 */ "G_ATOMICRMW_ADD\0"
  /* 477 */ "G_ATOMICRMW_NAND\0"
  /* 494 */ "G_VECREDUCE_AND\0"
  /* 510 */ "G_AND\0"
  /* 516 */ "G_ATOMICRMW_AND\0"
  /* 532 */ "LIFETIME_END\0"
  /* 545 */ "G_BRCOND\0"
  /* 554 */ "G_LLROUND\0"
  /* 564 */ "G_LROUND\0"
  /* 573 */ "G_INTRINSIC_ROUND\0"
  /* 591 */ "G_INTRINSIC_FPTRUNC_ROUND\0"
  /* 617 */ "LOAD_STACK_GUARD\0"
  /* 634 */ "PSEUDO_PROBE\0"
  /* 647 */ "G_SSUBE\0"
  /* 655 */ "G_USUBE\0"
  /* 663 */ "G_FENCE\0"
  /* 671 */ "ARITH_FENCE\0"
  /* 683 */ "REG_SEQUENCE\0"
  /* 696 */ "G_SADDE\0"
  /* 704 */ "G_UADDE\0"
  /* 712 */ "G_GET_FPMODE\0"
  /* 725 */ "G_RESET_FPMODE\0"
  /* 740 */ "G_SET_FPMODE\0"
  /* 753 */ "G_FMINNUM_IEEE\0"
  /* 768 */ "G_FMAXNUM_IEEE\0"
  /* 783 */ "G_VSCALE\0"
  /* 792 */ "G_JUMP_TABLE\0"
  /* 805 */ "BUNDLE\0"
  /* 812 */ "G_MEMCPY_INLINE\0"
  /* 828 */ "LOCAL_ESCAPE\0"
  /* 841 */ "G_STACKRESTORE\0"
  /* 856 */ "G_INDEXED_STORE\0"
  /* 872 */ "G_STORE\0"
  /* 880 */ "G_BITREVERSE\0"
  /* 893 */ "FAKE_USE\0"
  /* 902 */ "DBG_VALUE\0"
  /* 912 */ "G_GLOBAL_VALUE\0"
  /* 927 */ "G_PTRAUTH_GLOBAL_VALUE\0"
  /* 950 */ "CONVERGENCECTRL_GLUE\0"
  /* 971 */ "G_STACKSAVE\0"
  /* 983 */ "G_MEMMOVE\0"
  /* 993 */ "G_FREEZE\0"
  /* 1002 */ "G_FCANONICALIZE\0"
  /* 1018 */ "G_CTLZ_ZERO_UNDEF\0"
  /* 1036 */ "G_CTTZ_ZERO_UNDEF\0"
  /* 1054 */ "G_IMPLICIT_DEF\0"
  /* 1069 */ "DBG_INSTR_REF\0"
  /* 1083 */ "G_FNEG\0"
  /* 1090 */ "EXTRACT_SUBREG\0"
  /* 1105 */ "INSERT_SUBREG\0"
  /* 1119 */ "G_SEXT_INREG\0"
  /* 1132 */ "SUBREG_TO_REG\0"
  /* 1146 */ "G_ATOMIC_CMPXCHG\0"
  /* 1163 */ "G_ATOMICRMW_XCHG\0"
  /* 1180 */ "G_FLOG\0"
  /* 1187 */ "G_VAARG\0"
  /* 1195 */ "PREALLOCATED_ARG\0"
  /* 1212 */ "G_PREFETCH\0"
  /* 1223 */ "G_SMULH\0"
  /* 1231 */ "G_UMULH\0"
  /* 1239 */ "G_FTANH\0"
  /* 1247 */ "G_FSINH\0"
  /* 1255 */ "G_FCOSH\0"
  /* 1263 */ "DBG_PHI\0"
  /* 1271 */ "MOVHI\0"
  /* 1277 */ "SFSUB_F_RI_HI\0"
  /* 1291 */ "SUBB_I_HI\0"
  /* 1301 */ "SUB_I_HI\0"
  /* 1310 */ "ADDC_I_HI\0"
  /* 1320 */ "ADD_I_HI\0"
  /* 1329 */ "AND_I_HI\0"
  /* 1338 */ "SUBB_F_I_HI\0"
  /* 1350 */ "SUB_F_I_HI\0"
  /* 1361 */ "ADDC_F_I_HI\0"
  /* 1373 */ "ADD_F_I_HI\0"
  /* 1384 */ "AND_F_I_HI\0"
  /* 1395 */ "XOR_F_I_HI\0"
  /* 1406 */ "XOR_I_HI\0"
  /* 1415 */ "SLI\0"
  /* 1419 */ "STB_RI\0"
  /* 1426 */ "STH_RI\0"
  /* 1433 */ "LDW_RI\0"
  /* 1440 */ "SW_RI\0"
  /* 1446 */ "LDBs_RI\0"
  /* 1454 */ "LDHs_RI\0"
  /* 1462 */ "LDBz_RI\0"
  /* 1470 */ "LDHz_RI\0"
  /* 1478 */ "G_FPTOSI\0"
  /* 1487 */ "G_FPTOUI\0"
  /* 1496 */ "G_FPOWI\0"
  /* 1504 */ "SA_I\0"
  /* 1509 */ "SA_F_I\0"
  /* 1516 */ "SL_F_I\0"
  /* 1523 */ "SL_I\0"
  /* 1528 */ "G_PTRMASK\0"
  /* 1538 */ "GC_LABEL\0"
  /* 1547 */ "DBG_LABEL\0"
  /* 1557 */ "EH_LABEL\0"
  /* 1566 */ "ANNOTATION_LABEL\0"
  /* 1583 */ "ICALL_BRANCH_FUNNEL\0"
  /* 1603 */ "G_FSHL\0"
  /* 1610 */ "G_SHL\0"
  /* 1616 */ "G_FCEIL\0"
  /* 1624 */ "PATCHABLE_TAIL_CALL\0"
  /* 1644 */ "PATCHABLE_TYPED_EVENT_CALL\0"
  /* 1671 */ "PATCHABLE_EVENT_CALL\0"
  /* 1692 */ "FENTRY_CALL\0"
  /* 1704 */ "KILL\0"
  /* 1709 */ "G_CONSTANT_POOL\0"
  /* 1725 */ "G_ROTL\0"
  /* 1732 */ "G_VECREDUCE_FMUL\0"
  /* 1749 */ "G_FMUL\0"
  /* 1756 */ "G_VECREDUCE_SEQ_FMUL\0"
  /* 1777 */ "G_STRICT_FMUL\0"
  /* 1791 */ "G_VECREDUCE_MUL\0"
  /* 1807 */ "G_MUL\0"
  /* 1813 */ "G_FREM\0"
  /* 1820 */ "G_STRICT_FREM\0"
  /* 1834 */ "G_SREM\0"
  /* 1841 */ "G_UREM\0"
  /* 1848 */ "G_SDIVREM\0"
  /* 1858 */ "G_UDIVREM\0"
  /* 1868 */ "INLINEASM\0"
  /* 1878 */ "G_VECREDUCE_FMINIMUM\0"
  /* 1899 */ "G_FMINIMUM\0"
  /* 1910 */ "G_VECREDUCE_FMAXIMUM\0"
  /* 1931 */ "G_FMAXIMUM\0"
  /* 1942 */ "G_FMINNUM\0"
  /* 1952 */ "G_FMAXNUM\0"
  /* 1962 */ "G_FATAN\0"
  /* 1970 */ "G_FTAN\0"
  /* 1977 */ "G_INTRINSIC_ROUNDEVEN\0"
  /* 1999 */ "G_ASSERT_ALIGN\0"
  /* 2014 */ "G_FCOPYSIGN\0"
  /* 2026 */ "G_VECREDUCE_FMIN\0"
  /* 2043 */ "G_ATOMICRMW_FMIN\0"
  /* 2060 */ "G_VECREDUCE_SMIN\0"
  /* 2077 */ "G_SMIN\0"
  /* 2084 */ "G_VECREDUCE_UMIN\0"
  /* 2101 */ "G_UMIN\0"
  /* 2108 */ "G_ATOMICRMW_UMIN\0"
  /* 2125 */ "G_ATOMICRMW_MIN\0"
  /* 2141 */ "G_FASIN\0"
  /* 2149 */ "G_FSIN\0"
  /* 2156 */ "CFI_INSTRUCTION\0"
  /* 2172 */ "ADJCALLSTACKDOWN\0"
  /* 2189 */ "G_SSUBO\0"
  /* 2197 */ "G_USUBO\0"
  /* 2205 */ "G_SADDO\0"
  /* 2213 */ "G_UADDO\0"
  /* 2221 */ "JUMP_TABLE_DEBUG_INFO\0"
  /* 2243 */ "G_SMULO\0"
  /* 2251 */ "G_UMULO\0"
  /* 2259 */ "SFSUB_F_RI_LO\0"
  /* 2273 */ "SUBB_I_LO\0"
  /* 2283 */ "SUB_I_LO\0"
  /* 2292 */ "ADDC_I_LO\0"
  /* 2302 */ "ADD_I_LO\0"
  /* 2311 */ "AND_I_LO\0"
  /* 2320 */ "SUBB_F_I_LO\0"
  /* 2332 */ "SUB_F_I_LO\0"
  /* 2343 */ "ADDC_F_I_LO\0"
  /* 2355 */ "ADD_F_I_LO\0"
  /* 2366 */ "AND_F_I_LO\0"
  /* 2377 */ "XOR_F_I_LO\0"
  /* 2388 */ "XOR_I_LO\0"
  /* 2397 */ "G_BZERO\0"
  /* 2405 */ "STACKMAP\0"
  /* 2414 */ "G_DEBUGTRAP\0"
  /* 2426 */ "G_UBSANTRAP\0"
  /* 2438 */ "G_TRAP\0"
  /* 2445 */ "G_ATOMICRMW_UDEC_WRAP\0"
  /* 2467 */ "G_ATOMICRMW_UINC_WRAP\0"
  /* 2489 */ "G_BSWAP\0"
  /* 2497 */ "G_SITOFP\0"
  /* 2506 */ "G_UITOFP\0"
  /* 2515 */ "G_FCMP\0"
  /* 2522 */ "G_ICMP\0"
  /* 2529 */ "G_SCMP\0"
  /* 2536 */ "G_UCMP\0"
  /* 2543 */ "NOP\0"
  /* 2547 */ "CONVERGENCECTRL_LOOP\0"
  /* 2568 */ "G_CTPOP\0"
  /* 2576 */ "PATCHABLE_OP\0"
  /* 2589 */ "FAULTING_OP\0"
  /* 2601 */ "ADJCALLSTACKUP\0"
  /* 2616 */ "PREALLOCATED_SETUP\0"
  /* 2635 */ "G_FLDEXP\0"
  /* 2644 */ "G_STRICT_FLDEXP\0"
  /* 2660 */ "G_FEXP\0"
  /* 2667 */ "G_FFREXP\0"
  /* 2676 */ "G_BR\0"
  /* 2681 */ "INLINEASM_BR\0"
  /* 2694 */ "LDADDR\0"
  /* 2701 */ "STADDR\0"
  /* 2708 */ "G_BLOCK_ADDR\0"
  /* 2721 */ "MEMBARRIER\0"
  /* 2732 */ "G_CONSTANT_FOLD_BARRIER\0"
  /* 2756 */ "PATCHABLE_FUNCTION_ENTER\0"
  /* 2781 */ "G_READCYCLECOUNTER\0"
  /* 2800 */ "G_READSTEADYCOUNTER\0"
  /* 2820 */ "G_READ_REGISTER\0"
  /* 2836 */ "G_WRITE_REGISTER\0"
  /* 2853 */ "G_ASHR\0"
  /* 2860 */ "G_FSHR\0"
  /* 2867 */ "G_LSHR\0"
  /* 2874 */ "JR\0"
  /* 2877 */ "CALLR\0"
  /* 2883 */ "CONVERGENCECTRL_ANCHOR\0"
  /* 2906 */ "G_FFLOOR\0"
  /* 2915 */ "G_EXTRACT_SUBVECTOR\0"
  /* 2935 */ "G_INSERT_SUBVECTOR\0"
  /* 2954 */ "G_BUILD_VECTOR\0"
  /* 2969 */ "G_SHUFFLE_VECTOR\0"
  /* 2986 */ "G_SPLAT_VECTOR\0"
  /* 3001 */ "G_VECREDUCE_XOR\0"
  /* 3017 */ "G_XOR\0"
  /* 3023 */ "G_ATOMICRMW_XOR\0"
  /* 3039 */ "G_VECREDUCE_OR\0"
  /* 3054 */ "G_OR\0"
  /* 3059 */ "G_ATOMICRMW_OR\0"
  /* 3074 */ "BRR\0"
  /* 3078 */ "STB_RR\0"
  /* 3085 */ "SFSUB_F_RR\0"
  /* 3096 */ "STH_RR\0"
  /* 3103 */ "LDW_RR\0"
  /* 3110 */ "SW_RR\0"
  /* 3116 */ "LDBs_RR\0"
  /* 3124 */ "LDHs_RR\0"
  /* 3132 */ "LDBz_RR\0"
  /* 3140 */ "LDHz_RR\0"
  /* 3148 */ "LDWz_RR\0"
  /* 3156 */ "G_ROTR\0"
  /* 3163 */ "G_INTTOPTR\0"
  /* 3174 */ "SRA_R\0"
  /* 3180 */ "SUBB_R\0"
  /* 3187 */ "SUB_R\0"
  /* 3193 */ "ADDC_R\0"
  /* 3200 */ "ADD_R\0"
  /* 3206 */ "AND_R\0"
  /* 3212 */ "SRA_F_R\0"
  /* 3220 */ "SUBB_F_R\0"
  /* 3229 */ "SUB_F_R\0"
  /* 3237 */ "ADDC_F_R\0"
  /* 3246 */ "ADD_F_R\0"
  /* 3254 */ "AND_F_R\0"
  /* 3262 */ "SHL_F_R\0"
  /* 3270 */ "SRL_F_R\0"
  /* 3278 */ "XOR_F_R\0"
  /* 3286 */ "SHL_R\0"
  /* 3292 */ "SRL_R\0"
  /* 3298 */ "XOR_R\0"
  /* 3304 */ "G_FABS\0"
  /* 3311 */ "G_ABS\0"
  /* 3317 */ "G_UNMERGE_VALUES\0"
  /* 3334 */ "G_MERGE_VALUES\0"
  /* 3349 */ "G_FACOS\0"
  /* 3357 */ "G_FCOS\0"
  /* 3364 */ "G_CONCAT_VECTORS\0"
  /* 3381 */ "COPY_TO_REGCLASS\0"
  /* 3398 */ "G_IS_FPCLASS\0"
  /* 3411 */ "G_ATOMIC_CMPXCHG_WITH_SUCCESS\0"
  /* 3441 */ "G_VECTOR_COMPRESS\0"
  /* 3459 */ "G_INTRINSIC_W_SIDE_EFFECTS\0"
  /* 3486 */ "G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS\0"
  /* 3524 */ "G_SSUBSAT\0"
  /* 3534 */ "G_USUBSAT\0"
  /* 3544 */ "G_SADDSAT\0"
  /* 3554 */ "G_UADDSAT\0"
  /* 3564 */ "G_SSHLSAT\0"
  /* 3574 */ "G_USHLSAT\0"
  /* 3584 */ "G_SMULFIXSAT\0"
  /* 3597 */ "G_UMULFIXSAT\0"
  /* 3610 */ "G_SDIVFIXSAT\0"
  /* 3623 */ "G_UDIVFIXSAT\0"
  /* 3636 */ "BT\0"
  /* 3639 */ "G_EXTRACT\0"
  /* 3649 */ "G_SELECT\0"
  /* 3658 */ "G_BRINDIRECT\0"
  /* 3671 */ "PATCHABLE_RET\0"
  /* 3685 */ "G_MEMSET\0"
  /* 3694 */ "PATCHABLE_FUNCTION_EXIT\0"
  /* 3718 */ "G_BRJT\0"
  /* 3725 */ "G_EXTRACT_VECTOR_ELT\0"
  /* 3746 */ "G_INSERT_VECTOR_ELT\0"
  /* 3766 */ "G_FCONSTANT\0"
  /* 3778 */ "G_CONSTANT\0"
  /* 3789 */ "G_INTRINSIC_CONVERGENT\0"
  /* 3812 */ "STATEPOINT\0"
  /* 3823 */ "PATCHPOINT\0"
  /* 3834 */ "G_PTRTOINT\0"
  /* 3845 */ "G_FRINT\0"
  /* 3853 */ "G_INTRINSIC_LLRINT\0"
  /* 3872 */ "G_INTRINSIC_LRINT\0"
  /* 3890 */ "G_FNEARBYINT\0"
  /* 3903 */ "G_VASTART\0"
  /* 3913 */ "LIFETIME_START\0"
  /* 3928 */ "G_INVOKE_REGION_START\0"
  /* 3950 */ "G_INSERT\0"
  /* 3959 */ "G_FSQRT\0"
  /* 3967 */ "G_STRICT_FSQRT\0"
  /* 3982 */ "G_BITCAST\0"
  /* 3992 */ "G_ADDRSPACE_CAST\0"
  /* 4009 */ "DBG_VALUE_LIST\0"
  /* 4024 */ "G_FPEXT\0"
  /* 4032 */ "G_SEXT\0"
  /* 4039 */ "G_ASSERT_SEXT\0"
  /* 4053 */ "G_ANYEXT\0"
  /* 4062 */ "G_ZEXT\0"
  /* 4069 */ "G_ASSERT_ZEXT\0"
  /* 4083 */ "G_FDIV\0"
  /* 4090 */ "G_STRICT_FDIV\0"
  /* 4104 */ "G_SDIV\0"
  /* 4111 */ "G_UDIV\0"
  /* 4118 */ "G_GET_FPENV\0"
  /* 4130 */ "G_RESET_FPENV\0"
  /* 4144 */ "G_SET_FPENV\0"
  /* 4156 */ "G_FPOW\0"
  /* 4163 */ "G_VECREDUCE_FMAX\0"
  /* 4180 */ "G_ATOMICRMW_FMAX\0"
  /* 4197 */ "G_VECREDUCE_SMAX\0"
  /* 4214 */ "G_SMAX\0"
  /* 4221 */ "G_VECREDUCE_UMAX\0"
  /* 4238 */ "G_UMAX\0"
  /* 4245 */ "G_ATOMICRMW_UMAX\0"
  /* 4262 */ "G_ATOMICRMW_MAX\0"
  /* 4278 */ "G_FRAME_INDEX\0"
  /* 4292 */ "G_SBFX\0"
  /* 4299 */ "G_UBFX\0"
  /* 4306 */ "G_SMULFIX\0"
  /* 4316 */ "G_UMULFIX\0"
  /* 4326 */ "G_SDIVFIX\0"
  /* 4336 */ "G_UDIVFIX\0"
  /* 4346 */ "G_MEMCPY\0"
  /* 4355 */ "COPY\0"
  /* 4360 */ "CONVERGENCECTRL_ENTRY\0"
  /* 4382 */ "LEADZ\0"
  /* 4388 */ "TRAILZ\0"
  /* 4395 */ "G_CTLZ\0"
  /* 4402 */ "G_CTTZ\0"
};
#ifdef __GNUC__
#pragma GCC diagnostic pop
#endif

extern const unsigned LanaiInstrNameIndices[] = {
    1267U, 1868U, 2681U, 2156U, 1557U, 1538U, 1566U, 1704U, 
    1090U, 1105U, 1056U, 1132U, 3381U, 902U, 4009U, 1069U, 
    1263U, 1547U, 683U, 4355U, 805U, 3913U, 532U, 634U, 
    671U, 2405U, 1692U, 3823U, 617U, 2616U, 1195U, 3812U, 
    828U, 2589U, 2576U, 2756U, 3671U, 3694U, 1624U, 1671U, 
    1644U, 1583U, 893U, 2721U, 2221U, 4360U, 2883U, 2547U, 
    950U, 4039U, 4069U, 1999U, 445U, 121U, 1807U, 4104U, 
    4111U, 1834U, 1841U, 1848U, 1858U, 510U, 3054U, 3017U, 
    1054U, 1265U, 4278U, 912U, 927U, 1709U, 3639U, 3317U, 
    3950U, 3334U, 2954U, 209U, 3364U, 3834U, 3163U, 3982U, 
    993U, 2732U, 591U, 183U, 573U, 3872U, 3853U, 1977U, 
    2781U, 2800U, 346U, 290U, 320U, 331U, 271U, 301U, 
    872U, 856U, 3411U, 1146U, 1163U, 461U, 127U, 516U, 
    477U, 3059U, 3023U, 4262U, 2125U, 4245U, 2108U, 412U, 
    104U, 4180U, 2043U, 2467U, 2445U, 663U, 1212U, 545U, 
    3658U, 3928U, 161U, 3459U, 3789U, 3486U, 4053U, 201U, 
    3778U, 3766U, 3903U, 1187U, 4032U, 1119U, 4062U, 1610U, 
    2867U, 2853U, 1603U, 2860U, 3156U, 1725U, 2522U, 2515U, 
    2529U, 2536U, 3649U, 2213U, 704U, 2197U, 655U, 2205U, 
    696U, 2189U, 647U, 2251U, 2243U, 1231U, 1223U, 3554U, 
    3544U, 3534U, 3524U, 3574U, 3564U, 4306U, 4316U, 3584U, 
    3597U, 4326U, 4336U, 3610U, 3623U, 370U, 83U, 1749U, 
    64U, 264U, 4083U, 1813U, 4156U, 1496U, 2660U, 36U, 
    9U, 1180U, 28U, 0U, 2635U, 2667U, 1083U, 4024U, 
    173U, 1478U, 1487U, 2497U, 2506U, 3304U, 2014U, 3398U, 
    1002U, 1942U, 1952U, 753U, 768U, 1899U, 1931U, 4118U, 
    4144U, 4130U, 712U, 740U, 725U, 451U, 1528U, 2077U, 
    4214U, 2101U, 4238U, 3311U, 564U, 554U, 2676U, 3718U, 
    783U, 2935U, 2915U, 3746U, 3725U, 2969U, 2986U, 3441U, 
    4402U, 1036U, 4395U, 1018U, 2568U, 2489U, 880U, 1616U, 
    3357U, 2149U, 1970U, 3349U, 2141U, 1962U, 1255U, 1247U, 
    1239U, 3959U, 2906U, 3845U, 3890U, 3992U, 2708U, 792U, 
    230U, 971U, 841U, 398U, 90U, 1777U, 4090U, 1820U, 
    70U, 3967U, 2644U, 2820U, 2836U, 4346U, 812U, 983U, 
    3685U, 2397U, 2438U, 2414U, 2426U, 377U, 1756U, 353U, 
    1732U, 4163U, 2026U, 1910U, 1878U, 429U, 1791U, 494U, 
    3039U, 3001U, 4197U, 2060U, 4221U, 2084U, 4292U, 4299U, 
    2172U, 2601U, 247U, 1639U, 2877U, 1361U, 2343U, 3237U, 
    1310U, 2292U, 3193U, 1373U, 2355U, 3246U, 1320U, 2302U, 
    3200U, 1384U, 2366U, 3254U, 1329U, 2311U, 3206U, 143U, 
    152U, 54U, 3074U, 3636U, 2874U, 2694U, 1446U, 3116U, 
    1462U, 3132U, 1454U, 3124U, 1470U, 3140U, 1433U, 3103U, 
    3148U, 4382U, 18U, 23U, 31U, 44U, 49U, 1271U, 
    2543U, 1396U, 2378U, 3279U, 1407U, 2389U, 3299U, 259U, 
    3681U, 1509U, 1504U, 148U, 3651U, 1277U, 2259U, 3085U, 
    3262U, 3286U, 1415U, 1516U, 1523U, 3212U, 3174U, 3270U, 
    3292U, 2701U, 1419U, 3078U, 1426U, 3096U, 1338U, 2320U, 
    3220U, 1291U, 2273U, 3180U, 1350U, 2332U, 3229U, 1301U, 
    2283U, 3187U, 1440U, 3110U, 4388U, 1395U, 2377U, 3278U, 
    1406U, 2388U, 3298U, 
};

static inline void InitLanaiMCInstrInfo(MCInstrInfo *II) {
  II->InitMCInstrInfo(LanaiDescs.Insts, LanaiInstrNameIndices, LanaiInstrNameData, nullptr, nullptr, 395);
}

} // end namespace llvm
#endif // GET_INSTRINFO_MC_DESC

#ifdef GET_INSTRINFO_HEADER
#undef GET_INSTRINFO_HEADER
namespace llvm {
struct LanaiGenInstrInfo : public TargetInstrInfo {
  explicit LanaiGenInstrInfo(unsigned CFSetupOpcode = ~0u, unsigned CFDestroyOpcode = ~0u, unsigned CatchRetOpcode = ~0u, unsigned ReturnOpcode = ~0u);
  ~LanaiGenInstrInfo() override = default;

};
} // end namespace llvm
#endif // GET_INSTRINFO_HEADER

#ifdef GET_INSTRINFO_HELPER_DECLS
#undef GET_INSTRINFO_HELPER_DECLS


#endif // GET_INSTRINFO_HELPER_DECLS

#ifdef GET_INSTRINFO_HELPERS
#undef GET_INSTRINFO_HELPERS

#endif // GET_INSTRINFO_HELPERS

#ifdef GET_INSTRINFO_CTOR_DTOR
#undef GET_INSTRINFO_CTOR_DTOR
namespace llvm {
extern const LanaiInstrTable LanaiDescs;
extern const unsigned LanaiInstrNameIndices[];
extern const char LanaiInstrNameData[];
LanaiGenInstrInfo::LanaiGenInstrInfo(unsigned CFSetupOpcode, unsigned CFDestroyOpcode, unsigned CatchRetOpcode, unsigned ReturnOpcode)
  : TargetInstrInfo(CFSetupOpcode, CFDestroyOpcode, CatchRetOpcode, ReturnOpcode) {
  InitMCInstrInfo(LanaiDescs.Insts, LanaiInstrNameIndices, LanaiInstrNameData, nullptr, nullptr, 395);
}
} // end namespace llvm
#endif // GET_INSTRINFO_CTOR_DTOR

#ifdef GET_INSTRINFO_OPERAND_ENUM
#undef GET_INSTRINFO_OPERAND_ENUM
namespace llvm {
namespace Lanai {
namespace OpName {
enum {
  OPERAND_LAST
};
} // end namespace OpName
} // end namespace Lanai
} // end namespace llvm
#endif //GET_INSTRINFO_OPERAND_ENUM

#ifdef GET_INSTRINFO_NAMED_OPS
#undef GET_INSTRINFO_NAMED_OPS
namespace llvm {
namespace Lanai {
LLVM_READONLY
int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx) {
  return -1;
}
} // end namespace Lanai
} // end namespace llvm
#endif //GET_INSTRINFO_NAMED_OPS

#ifdef GET_INSTRINFO_OPERAND_TYPES_ENUM
#undef GET_INSTRINFO_OPERAND_TYPES_ENUM
namespace llvm {
namespace Lanai {
namespace OpTypes {
enum OperandType {
  AluOp = 0,
  BrTarget = 1,
  CCOp = 2,
  CallTarget = 3,
  MEMi = 4,
  MEMri = 5,
  MEMrr = 6,
  MEMspls = 7,
  f32imm = 8,
  f64imm = 9,
  i1imm = 10,
  i8imm = 11,
  i16imm = 12,
  i32hi16 = 13,
  i32hi16and = 14,
  i32imm = 15,
  i32lo16and = 16,
  i32lo16s = 17,
  i32lo16z = 18,
  i32lo21 = 19,
  i32neg16 = 20,
  i64imm = 21,
  imm10 = 22,
  immShift = 23,
  pred = 24,
  ptype0 = 25,
  ptype1 = 26,
  ptype2 = 27,
  ptype3 = 28,
  ptype4 = 29,
  ptype5 = 30,
  type0 = 31,
  type1 = 32,
  type2 = 33,
  type3 = 34,
  type4 = 35,
  type5 = 36,
  untyped_imm_0 = 37,
  CCR = 38,
  GPR = 39,
  OPERAND_TYPE_LIST_END
};
} // end namespace OpTypes
} // end namespace Lanai
} // end namespace llvm
#endif // GET_INSTRINFO_OPERAND_TYPES_ENUM

#ifdef GET_INSTRINFO_OPERAND_TYPE
#undef GET_INSTRINFO_OPERAND_TYPE
namespace llvm {
namespace Lanai {
LLVM_READONLY
static int getOperandType(uint16_t Opcode, uint16_t OpIdx) {
  static const uint16_t Offsets[] = {
    /* PHI */
    0,
    /* INLINEASM */
    1,
    /* INLINEASM_BR */
    1,
    /* CFI_INSTRUCTION */
    1,
    /* EH_LABEL */
    2,
    /* GC_LABEL */
    3,
    /* ANNOTATION_LABEL */
    4,
    /* KILL */
    5,
    /* EXTRACT_SUBREG */
    5,
    /* INSERT_SUBREG */
    8,
    /* IMPLICIT_DEF */
    12,
    /* SUBREG_TO_REG */
    13,
    /* COPY_TO_REGCLASS */
    17,
    /* DBG_VALUE */
    20,
    /* DBG_VALUE_LIST */
    20,
    /* DBG_INSTR_REF */
    20,
    /* DBG_PHI */
    20,
    /* DBG_LABEL */
    20,
    /* REG_SEQUENCE */
    21,
    /* COPY */
    23,
    /* BUNDLE */
    25,
    /* LIFETIME_START */
    25,
    /* LIFETIME_END */
    26,
    /* PSEUDO_PROBE */
    27,
    /* ARITH_FENCE */
    31,
    /* STACKMAP */
    33,
    /* FENTRY_CALL */
    35,
    /* PATCHPOINT */
    35,
    /* LOAD_STACK_GUARD */
    41,
    /* PREALLOCATED_SETUP */
    42,
    /* PREALLOCATED_ARG */
    43,
    /* STATEPOINT */
    46,
    /* LOCAL_ESCAPE */
    46,
    /* FAULTING_OP */
    48,
    /* PATCHABLE_OP */
    49,
    /* PATCHABLE_FUNCTION_ENTER */
    49,
    /* PATCHABLE_RET */
    49,
    /* PATCHABLE_FUNCTION_EXIT */
    49,
    /* PATCHABLE_TAIL_CALL */
    49,
    /* PATCHABLE_EVENT_CALL */
    49,
    /* PATCHABLE_TYPED_EVENT_CALL */
    51,
    /* ICALL_BRANCH_FUNNEL */
    54,
    /* FAKE_USE */
    54,
    /* MEMBARRIER */
    54,
    /* JUMP_TABLE_DEBUG_INFO */
    54,
    /* CONVERGENCECTRL_ENTRY */
    55,
    /* CONVERGENCECTRL_ANCHOR */
    56,
    /* CONVERGENCECTRL_LOOP */
    57,
    /* CONVERGENCECTRL_GLUE */
    59,
    /* G_ASSERT_SEXT */
    60,
    /* G_ASSERT_ZEXT */
    63,
    /* G_ASSERT_ALIGN */
    66,
    /* G_ADD */
    69,
    /* G_SUB */
    72,
    /* G_MUL */
    75,
    /* G_SDIV */
    78,
    /* G_UDIV */
    81,
    /* G_SREM */
    84,
    /* G_UREM */
    87,
    /* G_SDIVREM */
    90,
    /* G_UDIVREM */
    94,
    /* G_AND */
    98,
    /* G_OR */
    101,
    /* G_XOR */
    104,
    /* G_IMPLICIT_DEF */
    107,
    /* G_PHI */
    108,
    /* G_FRAME_INDEX */
    109,
    /* G_GLOBAL_VALUE */
    111,
    /* G_PTRAUTH_GLOBAL_VALUE */
    113,
    /* G_CONSTANT_POOL */
    118,
    /* G_EXTRACT */
    120,
    /* G_UNMERGE_VALUES */
    123,
    /* G_INSERT */
    125,
    /* G_MERGE_VALUES */
    129,
    /* G_BUILD_VECTOR */
    131,
    /* G_BUILD_VECTOR_TRUNC */
    133,
    /* G_CONCAT_VECTORS */
    135,
    /* G_PTRTOINT */
    137,
    /* G_INTTOPTR */
    139,
    /* G_BITCAST */
    141,
    /* G_FREEZE */
    143,
    /* G_CONSTANT_FOLD_BARRIER */
    145,
    /* G_INTRINSIC_FPTRUNC_ROUND */
    147,
    /* G_INTRINSIC_TRUNC */
    150,
    /* G_INTRINSIC_ROUND */
    152,
    /* G_INTRINSIC_LRINT */
    154,
    /* G_INTRINSIC_LLRINT */
    156,
    /* G_INTRINSIC_ROUNDEVEN */
    158,
    /* G_READCYCLECOUNTER */
    160,
    /* G_READSTEADYCOUNTER */
    161,
    /* G_LOAD */
    162,
    /* G_SEXTLOAD */
    164,
    /* G_ZEXTLOAD */
    166,
    /* G_INDEXED_LOAD */
    168,
    /* G_INDEXED_SEXTLOAD */
    173,
    /* G_INDEXED_ZEXTLOAD */
    178,
    /* G_STORE */
    183,
    /* G_INDEXED_STORE */
    185,
    /* G_ATOMIC_CMPXCHG_WITH_SUCCESS */
    190,
    /* G_ATOMIC_CMPXCHG */
    195,
    /* G_ATOMICRMW_XCHG */
    199,
    /* G_ATOMICRMW_ADD */
    202,
    /* G_ATOMICRMW_SUB */
    205,
    /* G_ATOMICRMW_AND */
    208,
    /* G_ATOMICRMW_NAND */
    211,
    /* G_ATOMICRMW_OR */
    214,
    /* G_ATOMICRMW_XOR */
    217,
    /* G_ATOMICRMW_MAX */
    220,
    /* G_ATOMICRMW_MIN */
    223,
    /* G_ATOMICRMW_UMAX */
    226,
    /* G_ATOMICRMW_UMIN */
    229,
    /* G_ATOMICRMW_FADD */
    232,
    /* G_ATOMICRMW_FSUB */
    235,
    /* G_ATOMICRMW_FMAX */
    238,
    /* G_ATOMICRMW_FMIN */
    241,
    /* G_ATOMICRMW_UINC_WRAP */
    244,
    /* G_ATOMICRMW_UDEC_WRAP */
    247,
    /* G_FENCE */
    250,
    /* G_PREFETCH */
    252,
    /* G_BRCOND */
    256,
    /* G_BRINDIRECT */
    258,
    /* G_INVOKE_REGION_START */
    259,
    /* G_INTRINSIC */
    259,
    /* G_INTRINSIC_W_SIDE_EFFECTS */
    260,
    /* G_INTRINSIC_CONVERGENT */
    261,
    /* G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS */
    262,
    /* G_ANYEXT */
    263,
    /* G_TRUNC */
    265,
    /* G_CONSTANT */
    267,
    /* G_FCONSTANT */
    269,
    /* G_VASTART */
    271,
    /* G_VAARG */
    272,
    /* G_SEXT */
    275,
    /* G_SEXT_INREG */
    277,
    /* G_ZEXT */
    280,
    /* G_SHL */
    282,
    /* G_LSHR */
    285,
    /* G_ASHR */
    288,
    /* G_FSHL */
    291,
    /* G_FSHR */
    295,
    /* G_ROTR */
    299,
    /* G_ROTL */
    302,
    /* G_ICMP */
    305,
    /* G_FCMP */
    309,
    /* G_SCMP */
    313,
    /* G_UCMP */
    316,
    /* G_SELECT */
    319,
    /* G_UADDO */
    323,
    /* G_UADDE */
    327,
    /* G_USUBO */
    332,
    /* G_USUBE */
    336,
    /* G_SADDO */
    341,
    /* G_SADDE */
    345,
    /* G_SSUBO */
    350,
    /* G_SSUBE */
    354,
    /* G_UMULO */
    359,
    /* G_SMULO */
    363,
    /* G_UMULH */
    367,
    /* G_SMULH */
    370,
    /* G_UADDSAT */
    373,
    /* G_SADDSAT */
    376,
    /* G_USUBSAT */
    379,
    /* G_SSUBSAT */
    382,
    /* G_USHLSAT */
    385,
    /* G_SSHLSAT */
    388,
    /* G_SMULFIX */
    391,
    /* G_UMULFIX */
    395,
    /* G_SMULFIXSAT */
    399,
    /* G_UMULFIXSAT */
    403,
    /* G_SDIVFIX */
    407,
    /* G_UDIVFIX */
    411,
    /* G_SDIVFIXSAT */
    415,
    /* G_UDIVFIXSAT */
    419,
    /* G_FADD */
    423,
    /* G_FSUB */
    426,
    /* G_FMUL */
    429,
    /* G_FMA */
    432,
    /* G_FMAD */
    436,
    /* G_FDIV */
    440,
    /* G_FREM */
    443,
    /* G_FPOW */
    446,
    /* G_FPOWI */
    449,
    /* G_FEXP */
    452,
    /* G_FEXP2 */
    454,
    /* G_FEXP10 */
    456,
    /* G_FLOG */
    458,
    /* G_FLOG2 */
    460,
    /* G_FLOG10 */
    462,
    /* G_FLDEXP */
    464,
    /* G_FFREXP */
    467,
    /* G_FNEG */
    470,
    /* G_FPEXT */
    472,
    /* G_FPTRUNC */
    474,
    /* G_FPTOSI */
    476,
    /* G_FPTOUI */
    478,
    /* G_SITOFP */
    480,
    /* G_UITOFP */
    482,
    /* G_FABS */
    484,
    /* G_FCOPYSIGN */
    486,
    /* G_IS_FPCLASS */
    489,
    /* G_FCANONICALIZE */
    492,
    /* G_FMINNUM */
    494,
    /* G_FMAXNUM */
    497,
    /* G_FMINNUM_IEEE */
    500,
    /* G_FMAXNUM_IEEE */
    503,
    /* G_FMINIMUM */
    506,
    /* G_FMAXIMUM */
    509,
    /* G_GET_FPENV */
    512,
    /* G_SET_FPENV */
    513,
    /* G_RESET_FPENV */
    514,
    /* G_GET_FPMODE */
    514,
    /* G_SET_FPMODE */
    515,
    /* G_RESET_FPMODE */
    516,
    /* G_PTR_ADD */
    516,
    /* G_PTRMASK */
    519,
    /* G_SMIN */
    522,
    /* G_SMAX */
    525,
    /* G_UMIN */
    528,
    /* G_UMAX */
    531,
    /* G_ABS */
    534,
    /* G_LROUND */
    536,
    /* G_LLROUND */
    538,
    /* G_BR */
    540,
    /* G_BRJT */
    541,
    /* G_VSCALE */
    544,
    /* G_INSERT_SUBVECTOR */
    546,
    /* G_EXTRACT_SUBVECTOR */
    550,
    /* G_INSERT_VECTOR_ELT */
    553,
    /* G_EXTRACT_VECTOR_ELT */
    557,
    /* G_SHUFFLE_VECTOR */
    560,
    /* G_SPLAT_VECTOR */
    564,
    /* G_VECTOR_COMPRESS */
    566,
    /* G_CTTZ */
    570,
    /* G_CTTZ_ZERO_UNDEF */
    572,
    /* G_CTLZ */
    574,
    /* G_CTLZ_ZERO_UNDEF */
    576,
    /* G_CTPOP */
    578,
    /* G_BSWAP */
    580,
    /* G_BITREVERSE */
    582,
    /* G_FCEIL */
    584,
    /* G_FCOS */
    586,
    /* G_FSIN */
    588,
    /* G_FTAN */
    590,
    /* G_FACOS */
    592,
    /* G_FASIN */
    594,
    /* G_FATAN */
    596,
    /* G_FCOSH */
    598,
    /* G_FSINH */
    600,
    /* G_FTANH */
    602,
    /* G_FSQRT */
    604,
    /* G_FFLOOR */
    606,
    /* G_FRINT */
    608,
    /* G_FNEARBYINT */
    610,
    /* G_ADDRSPACE_CAST */
    612,
    /* G_BLOCK_ADDR */
    614,
    /* G_JUMP_TABLE */
    616,
    /* G_DYN_STACKALLOC */
    618,
    /* G_STACKSAVE */
    621,
    /* G_STACKRESTORE */
    622,
    /* G_STRICT_FADD */
    623,
    /* G_STRICT_FSUB */
    626,
    /* G_STRICT_FMUL */
    629,
    /* G_STRICT_FDIV */
    632,
    /* G_STRICT_FREM */
    635,
    /* G_STRICT_FMA */
    638,
    /* G_STRICT_FSQRT */
    642,
    /* G_STRICT_FLDEXP */
    644,
    /* G_READ_REGISTER */
    647,
    /* G_WRITE_REGISTER */
    649,
    /* G_MEMCPY */
    651,
    /* G_MEMCPY_INLINE */
    655,
    /* G_MEMMOVE */
    658,
    /* G_MEMSET */
    662,
    /* G_BZERO */
    666,
    /* G_TRAP */
    669,
    /* G_DEBUGTRAP */
    669,
    /* G_UBSANTRAP */
    669,
    /* G_VECREDUCE_SEQ_FADD */
    670,
    /* G_VECREDUCE_SEQ_FMUL */
    673,
    /* G_VECREDUCE_FADD */
    676,
    /* G_VECREDUCE_FMUL */
    678,
    /* G_VECREDUCE_FMAX */
    680,
    /* G_VECREDUCE_FMIN */
    682,
    /* G_VECREDUCE_FMAXIMUM */
    684,
    /* G_VECREDUCE_FMINIMUM */
    686,
    /* G_VECREDUCE_ADD */
    688,
    /* G_VECREDUCE_MUL */
    690,
    /* G_VECREDUCE_AND */
    692,
    /* G_VECREDUCE_OR */
    694,
    /* G_VECREDUCE_XOR */
    696,
    /* G_VECREDUCE_SMAX */
    698,
    /* G_VECREDUCE_SMIN */
    700,
    /* G_VECREDUCE_UMAX */
    702,
    /* G_VECREDUCE_UMIN */
    704,
    /* G_SBFX */
    706,
    /* G_UBFX */
    710,
    /* ADJCALLSTACKDOWN */
    714,
    /* ADJCALLSTACKUP */
    716,
    /* ADJDYNALLOC */
    718,
    /* CALL */
    720,
    /* CALLR */
    721,
    /* ADDC_F_I_HI */
    722,
    /* ADDC_F_I_LO */
    725,
    /* ADDC_F_R */
    728,
    /* ADDC_I_HI */
    732,
    /* ADDC_I_LO */
    735,
    /* ADDC_R */
    738,
    /* ADD_F_I_HI */
    742,
    /* ADD_F_I_LO */
    745,
    /* ADD_F_R */
    748,
    /* ADD_I_HI */
    752,
    /* ADD_I_LO */
    755,
    /* ADD_R */
    758,
    /* AND_F_I_HI */
    762,
    /* AND_F_I_LO */
    765,
    /* AND_F_R */
    768,
    /* AND_I_HI */
    772,
    /* AND_I_LO */
    775,
    /* AND_R */
    778,
    /* BRCC */
    782,
    /* BRIND_CC */
    784,
    /* BRIND_CCA */
    786,
    /* BRR */
    789,
    /* BT */
    791,
    /* JR */
    792,
    /* LDADDR */
    793,
    /* LDBs_RI */
    795,
    /* LDBs_RR */
    799,
    /* LDBz_RI */
    803,
    /* LDBz_RR */
    807,
    /* LDHs_RI */
    811,
    /* LDHs_RR */
    815,
    /* LDHz_RI */
    819,
    /* LDHz_RR */
    823,
    /* LDW_RI */
    827,
    /* LDW_RR */
    831,
    /* LDWz_RR */
    835,
    /* LEADZ */
    839,
    /* LOG0 */
    841,
    /* LOG1 */
    841,
    /* LOG2 */
    841,
    /* LOG3 */
    841,
    /* LOG4 */
    841,
    /* MOVHI */
    841,
    /* NOP */
    843,
    /* OR_F_I_HI */
    843,
    /* OR_F_I_LO */
    846,
    /* OR_F_R */
    849,
    /* OR_I_HI */
    853,
    /* OR_I_LO */
    856,
    /* OR_R */
    859,
    /* POPC */
    863,
    /* RET */
    865,
    /* SA_F_I */
    865,
    /* SA_I */
    868,
    /* SCC */
    871,
    /* SELECT */
    873,
    /* SFSUB_F_RI_HI */
    877,
    /* SFSUB_F_RI_LO */
    879,
    /* SFSUB_F_RR */
    881,
    /* SHL_F_R */
    883,
    /* SHL_R */
    887,
    /* SLI */
    891,
    /* SL_F_I */
    893,
    /* SL_I */
    896,
    /* SRA_F_R */
    899,
    /* SRA_R */
    903,
    /* SRL_F_R */
    907,
    /* SRL_R */
    911,
    /* STADDR */
    915,
    /* STB_RI */
    917,
    /* STB_RR */
    921,
    /* STH_RI */
    925,
    /* STH_RR */
    929,
    /* SUBB_F_I_HI */
    933,
    /* SUBB_F_I_LO */
    936,
    /* SUBB_F_R */
    939,
    /* SUBB_I_HI */
    943,
    /* SUBB_I_LO */
    946,
    /* SUBB_R */
    949,
    /* SUB_F_I_HI */
    953,
    /* SUB_F_I_LO */
    956,
    /* SUB_F_R */
    959,
    /* SUB_I_HI */
    963,
    /* SUB_I_LO */
    966,
    /* SUB_R */
    969,
    /* SW_RI */
    973,
    /* SW_RR */
    977,
    /* TRAILZ */
    981,
    /* XOR_F_I_HI */
    983,
    /* XOR_F_I_LO */
    986,
    /* XOR_F_R */
    989,
    /* XOR_I_HI */
    993,
    /* XOR_I_LO */
    996,
    /* XOR_R */
    999,
  };

  using namespace OpTypes;
  static const int8_t OpcodeOperandTypes[] = {
    
    /* PHI */
    -1, 
    /* INLINEASM */
    /* INLINEASM_BR */
    /* CFI_INSTRUCTION */
    i32imm, 
    /* EH_LABEL */
    i32imm, 
    /* GC_LABEL */
    i32imm, 
    /* ANNOTATION_LABEL */
    i32imm, 
    /* KILL */
    /* EXTRACT_SUBREG */
    -1, -1, i32imm, 
    /* INSERT_SUBREG */
    -1, -1, -1, i32imm, 
    /* IMPLICIT_DEF */
    -1, 
    /* SUBREG_TO_REG */
    -1, -1, -1, i32imm, 
    /* COPY_TO_REGCLASS */
    -1, -1, i32imm, 
    /* DBG_VALUE */
    /* DBG_VALUE_LIST */
    /* DBG_INSTR_REF */
    /* DBG_PHI */
    /* DBG_LABEL */
    -1, 
    /* REG_SEQUENCE */
    -1, -1, 
    /* COPY */
    -1, -1, 
    /* BUNDLE */
    /* LIFETIME_START */
    i32imm, 
    /* LIFETIME_END */
    i32imm, 
    /* PSEUDO_PROBE */
    i64imm, i64imm, i8imm, i32imm, 
    /* ARITH_FENCE */
    -1, -1, 
    /* STACKMAP */
    i64imm, i32imm, 
    /* FENTRY_CALL */
    /* PATCHPOINT */
    -1, i64imm, i32imm, -1, i32imm, i32imm, 
    /* LOAD_STACK_GUARD */
    -1, 
    /* PREALLOCATED_SETUP */
    i32imm, 
    /* PREALLOCATED_ARG */
    -1, i32imm, i32imm, 
    /* STATEPOINT */
    /* LOCAL_ESCAPE */
    -1, i32imm, 
    /* FAULTING_OP */
    -1, 
    /* PATCHABLE_OP */
    /* PATCHABLE_FUNCTION_ENTER */
    /* PATCHABLE_RET */
    /* PATCHABLE_FUNCTION_EXIT */
    /* PATCHABLE_TAIL_CALL */
    /* PATCHABLE_EVENT_CALL */
    -1, -1, 
    /* PATCHABLE_TYPED_EVENT_CALL */
    -1, -1, -1, 
    /* ICALL_BRANCH_FUNNEL */
    /* FAKE_USE */
    /* MEMBARRIER */
    /* JUMP_TABLE_DEBUG_INFO */
    i64imm, 
    /* CONVERGENCECTRL_ENTRY */
    -1, 
    /* CONVERGENCECTRL_ANCHOR */
    -1, 
    /* CONVERGENCECTRL_LOOP */
    -1, -1, 
    /* CONVERGENCECTRL_GLUE */
    -1, 
    /* G_ASSERT_SEXT */
    type0, type0, untyped_imm_0, 
    /* G_ASSERT_ZEXT */
    type0, type0, untyped_imm_0, 
    /* G_ASSERT_ALIGN */
    type0, type0, untyped_imm_0, 
    /* G_ADD */
    type0, type0, type0, 
    /* G_SUB */
    type0, type0, type0, 
    /* G_MUL */
    type0, type0, type0, 
    /* G_SDIV */
    type0, type0, type0, 
    /* G_UDIV */
    type0, type0, type0, 
    /* G_SREM */
    type0, type0, type0, 
    /* G_UREM */
    type0, type0, type0, 
    /* G_SDIVREM */
    type0, type0, type0, type0, 
    /* G_UDIVREM */
    type0, type0, type0, type0, 
    /* G_AND */
    type0, type0, type0, 
    /* G_OR */
    type0, type0, type0, 
    /* G_XOR */
    type0, type0, type0, 
    /* G_IMPLICIT_DEF */
    type0, 
    /* G_PHI */
    type0, 
    /* G_FRAME_INDEX */
    type0, -1, 
    /* G_GLOBAL_VALUE */
    type0, -1, 
    /* G_PTRAUTH_GLOBAL_VALUE */
    type0, -1, i32imm, type1, i64imm, 
    /* G_CONSTANT_POOL */
    type0, -1, 
    /* G_EXTRACT */
    type0, type1, untyped_imm_0, 
    /* G_UNMERGE_VALUES */
    type0, type1, 
    /* G_INSERT */
    type0, type0, type1, untyped_imm_0, 
    /* G_MERGE_VALUES */
    type0, type1, 
    /* G_BUILD_VECTOR */
    type0, type1, 
    /* G_BUILD_VECTOR_TRUNC */
    type0, type1, 
    /* G_CONCAT_VECTORS */
    type0, type1, 
    /* G_PTRTOINT */
    type0, type1, 
    /* G_INTTOPTR */
    type0, type1, 
    /* G_BITCAST */
    type0, type1, 
    /* G_FREEZE */
    type0, type0, 
    /* G_CONSTANT_FOLD_BARRIER */
    type0, type0, 
    /* G_INTRINSIC_FPTRUNC_ROUND */
    type0, type1, i32imm, 
    /* G_INTRINSIC_TRUNC */
    type0, type0, 
    /* G_INTRINSIC_ROUND */
    type0, type0, 
    /* G_INTRINSIC_LRINT */
    type0, type1, 
    /* G_INTRINSIC_LLRINT */
    type0, type1, 
    /* G_INTRINSIC_ROUNDEVEN */
    type0, type0, 
    /* G_READCYCLECOUNTER */
    type0, 
    /* G_READSTEADYCOUNTER */
    type0, 
    /* G_LOAD */
    type0, ptype1, 
    /* G_SEXTLOAD */
    type0, ptype1, 
    /* G_ZEXTLOAD */
    type0, ptype1, 
    /* G_INDEXED_LOAD */
    type0, ptype1, ptype1, type2, -1, 
    /* G_INDEXED_SEXTLOAD */
    type0, ptype1, ptype1, type2, -1, 
    /* G_INDEXED_ZEXTLOAD */
    type0, ptype1, ptype1, type2, -1, 
    /* G_STORE */
    type0, ptype1, 
    /* G_INDEXED_STORE */
    ptype0, type1, ptype0, ptype2, -1, 
    /* G_ATOMIC_CMPXCHG_WITH_SUCCESS */
    type0, type1, type2, type0, type0, 
    /* G_ATOMIC_CMPXCHG */
    type0, ptype1, type0, type0, 
    /* G_ATOMICRMW_XCHG */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_ADD */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_SUB */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_AND */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_NAND */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_OR */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_XOR */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_MAX */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_MIN */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_UMAX */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_UMIN */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_FADD */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_FSUB */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_FMAX */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_FMIN */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_UINC_WRAP */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_UDEC_WRAP */
    type0, ptype1, type0, 
    /* G_FENCE */
    i32imm, i32imm, 
    /* G_PREFETCH */
    ptype0, i32imm, i32imm, i32imm, 
    /* G_BRCOND */
    type0, -1, 
    /* G_BRINDIRECT */
    type0, 
    /* G_INVOKE_REGION_START */
    /* G_INTRINSIC */
    -1, 
    /* G_INTRINSIC_W_SIDE_EFFECTS */
    -1, 
    /* G_INTRINSIC_CONVERGENT */
    -1, 
    /* G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS */
    -1, 
    /* G_ANYEXT */
    type0, type1, 
    /* G_TRUNC */
    type0, type1, 
    /* G_CONSTANT */
    type0, -1, 
    /* G_FCONSTANT */
    type0, -1, 
    /* G_VASTART */
    type0, 
    /* G_VAARG */
    type0, type1, -1, 
    /* G_SEXT */
    type0, type1, 
    /* G_SEXT_INREG */
    type0, type0, untyped_imm_0, 
    /* G_ZEXT */
    type0, type1, 
    /* G_SHL */
    type0, type0, type1, 
    /* G_LSHR */
    type0, type0, type1, 
    /* G_ASHR */
    type0, type0, type1, 
    /* G_FSHL */
    type0, type0, type0, type1, 
    /* G_FSHR */
    type0, type0, type0, type1, 
    /* G_ROTR */
    type0, type0, type1, 
    /* G_ROTL */
    type0, type0, type1, 
    /* G_ICMP */
    type0, -1, type1, type1, 
    /* G_FCMP */
    type0, -1, type1, type1, 
    /* G_SCMP */
    type0, type1, type1, 
    /* G_UCMP */
    type0, type1, type1, 
    /* G_SELECT */
    type0, type1, type0, type0, 
    /* G_UADDO */
    type0, type1, type0, type0, 
    /* G_UADDE */
    type0, type1, type0, type0, type1, 
    /* G_USUBO */
    type0, type1, type0, type0, 
    /* G_USUBE */
    type0, type1, type0, type0, type1, 
    /* G_SADDO */
    type0, type1, type0, type0, 
    /* G_SADDE */
    type0, type1, type0, type0, type1, 
    /* G_SSUBO */
    type0, type1, type0, type0, 
    /* G_SSUBE */
    type0, type1, type0, type0, type1, 
    /* G_UMULO */
    type0, type1, type0, type0, 
    /* G_SMULO */
    type0, type1, type0, type0, 
    /* G_UMULH */
    type0, type0, type0, 
    /* G_SMULH */
    type0, type0, type0, 
    /* G_UADDSAT */
    type0, type0, type0, 
    /* G_SADDSAT */
    type0, type0, type0, 
    /* G_USUBSAT */
    type0, type0, type0, 
    /* G_SSUBSAT */
    type0, type0, type0, 
    /* G_USHLSAT */
    type0, type0, type1, 
    /* G_SSHLSAT */
    type0, type0, type1, 
    /* G_SMULFIX */
    type0, type0, type0, untyped_imm_0, 
    /* G_UMULFIX */
    type0, type0, type0, untyped_imm_0, 
    /* G_SMULFIXSAT */
    type0, type0, type0, untyped_imm_0, 
    /* G_UMULFIXSAT */
    type0, type0, type0, untyped_imm_0, 
    /* G_SDIVFIX */
    type0, type0, type0, untyped_imm_0, 
    /* G_UDIVFIX */
    type0, type0, type0, untyped_imm_0, 
    /* G_SDIVFIXSAT */
    type0, type0, type0, untyped_imm_0, 
    /* G_UDIVFIXSAT */
    type0, type0, type0, untyped_imm_0, 
    /* G_FADD */
    type0, type0, type0, 
    /* G_FSUB */
    type0, type0, type0, 
    /* G_FMUL */
    type0, type0, type0, 
    /* G_FMA */
    type0, type0, type0, type0, 
    /* G_FMAD */
    type0, type0, type0, type0, 
    /* G_FDIV */
    type0, type0, type0, 
    /* G_FREM */
    type0, type0, type0, 
    /* G_FPOW */
    type0, type0, type0, 
    /* G_FPOWI */
    type0, type0, type1, 
    /* G_FEXP */
    type0, type0, 
    /* G_FEXP2 */
    type0, type0, 
    /* G_FEXP10 */
    type0, type0, 
    /* G_FLOG */
    type0, type0, 
    /* G_FLOG2 */
    type0, type0, 
    /* G_FLOG10 */
    type0, type0, 
    /* G_FLDEXP */
    type0, type0, type1, 
    /* G_FFREXP */
    type0, type1, type0, 
    /* G_FNEG */
    type0, type0, 
    /* G_FPEXT */
    type0, type1, 
    /* G_FPTRUNC */
    type0, type1, 
    /* G_FPTOSI */
    type0, type1, 
    /* G_FPTOUI */
    type0, type1, 
    /* G_SITOFP */
    type0, type1, 
    /* G_UITOFP */
    type0, type1, 
    /* G_FABS */
    type0, type0, 
    /* G_FCOPYSIGN */
    type0, type0, type1, 
    /* G_IS_FPCLASS */
    type0, type1, -1, 
    /* G_FCANONICALIZE */
    type0, type0, 
    /* G_FMINNUM */
    type0, type0, type0, 
    /* G_FMAXNUM */
    type0, type0, type0, 
    /* G_FMINNUM_IEEE */
    type0, type0, type0, 
    /* G_FMAXNUM_IEEE */
    type0, type0, type0, 
    /* G_FMINIMUM */
    type0, type0, type0, 
    /* G_FMAXIMUM */
    type0, type0, type0, 
    /* G_GET_FPENV */
    type0, 
    /* G_SET_FPENV */
    type0, 
    /* G_RESET_FPENV */
    /* G_GET_FPMODE */
    type0, 
    /* G_SET_FPMODE */
    type0, 
    /* G_RESET_FPMODE */
    /* G_PTR_ADD */
    ptype0, ptype0, type1, 
    /* G_PTRMASK */
    ptype0, ptype0, type1, 
    /* G_SMIN */
    type0, type0, type0, 
    /* G_SMAX */
    type0, type0, type0, 
    /* G_UMIN */
    type0, type0, type0, 
    /* G_UMAX */
    type0, type0, type0, 
    /* G_ABS */
    type0, type0, 
    /* G_LROUND */
    type0, type1, 
    /* G_LLROUND */
    type0, type1, 
    /* G_BR */
    -1, 
    /* G_BRJT */
    ptype0, -1, type1, 
    /* G_VSCALE */
    type0, -1, 
    /* G_INSERT_SUBVECTOR */
    type0, type0, type1, untyped_imm_0, 
    /* G_EXTRACT_SUBVECTOR */
    type0, type0, untyped_imm_0, 
    /* G_INSERT_VECTOR_ELT */
    type0, type0, type1, type2, 
    /* G_EXTRACT_VECTOR_ELT */
    type0, type1, type2, 
    /* G_SHUFFLE_VECTOR */
    type0, type1, type1, -1, 
    /* G_SPLAT_VECTOR */
    type0, type1, 
    /* G_VECTOR_COMPRESS */
    type0, type0, type1, type0, 
    /* G_CTTZ */
    type0, type1, 
    /* G_CTTZ_ZERO_UNDEF */
    type0, type1, 
    /* G_CTLZ */
    type0, type1, 
    /* G_CTLZ_ZERO_UNDEF */
    type0, type1, 
    /* G_CTPOP */
    type0, type1, 
    /* G_BSWAP */
    type0, type0, 
    /* G_BITREVERSE */
    type0, type0, 
    /* G_FCEIL */
    type0, type0, 
    /* G_FCOS */
    type0, type0, 
    /* G_FSIN */
    type0, type0, 
    /* G_FTAN */
    type0, type0, 
    /* G_FACOS */
    type0, type0, 
    /* G_FASIN */
    type0, type0, 
    /* G_FATAN */
    type0, type0, 
    /* G_FCOSH */
    type0, type0, 
    /* G_FSINH */
    type0, type0, 
    /* G_FTANH */
    type0, type0, 
    /* G_FSQRT */
    type0, type0, 
    /* G_FFLOOR */
    type0, type0, 
    /* G_FRINT */
    type0, type0, 
    /* G_FNEARBYINT */
    type0, type0, 
    /* G_ADDRSPACE_CAST */
    type0, type1, 
    /* G_BLOCK_ADDR */
    type0, -1, 
    /* G_JUMP_TABLE */
    type0, -1, 
    /* G_DYN_STACKALLOC */
    ptype0, type1, i32imm, 
    /* G_STACKSAVE */
    ptype0, 
    /* G_STACKRESTORE */
    ptype0, 
    /* G_STRICT_FADD */
    type0, type0, type0, 
    /* G_STRICT_FSUB */
    type0, type0, type0, 
    /* G_STRICT_FMUL */
    type0, type0, type0, 
    /* G_STRICT_FDIV */
    type0, type0, type0, 
    /* G_STRICT_FREM */
    type0, type0, type0, 
    /* G_STRICT_FMA */
    type0, type0, type0, type0, 
    /* G_STRICT_FSQRT */
    type0, type0, 
    /* G_STRICT_FLDEXP */
    type0, type0, type1, 
    /* G_READ_REGISTER */
    type0, -1, 
    /* G_WRITE_REGISTER */
    -1, type0, 
    /* G_MEMCPY */
    ptype0, ptype1, type2, untyped_imm_0, 
    /* G_MEMCPY_INLINE */
    ptype0, ptype1, type2, 
    /* G_MEMMOVE */
    ptype0, ptype1, type2, untyped_imm_0, 
    /* G_MEMSET */
    ptype0, type1, type2, untyped_imm_0, 
    /* G_BZERO */
    ptype0, type1, untyped_imm_0, 
    /* G_TRAP */
    /* G_DEBUGTRAP */
    /* G_UBSANTRAP */
    i8imm, 
    /* G_VECREDUCE_SEQ_FADD */
    type0, type1, type2, 
    /* G_VECREDUCE_SEQ_FMUL */
    type0, type1, type2, 
    /* G_VECREDUCE_FADD */
    type0, type1, 
    /* G_VECREDUCE_FMUL */
    type0, type1, 
    /* G_VECREDUCE_FMAX */
    type0, type1, 
    /* G_VECREDUCE_FMIN */
    type0, type1, 
    /* G_VECREDUCE_FMAXIMUM */
    type0, type1, 
    /* G_VECREDUCE_FMINIMUM */
    type0, type1, 
    /* G_VECREDUCE_ADD */
    type0, type1, 
    /* G_VECREDUCE_MUL */
    type0, type1, 
    /* G_VECREDUCE_AND */
    type0, type1, 
    /* G_VECREDUCE_OR */
    type0, type1, 
    /* G_VECREDUCE_XOR */
    type0, type1, 
    /* G_VECREDUCE_SMAX */
    type0, type1, 
    /* G_VECREDUCE_SMIN */
    type0, type1, 
    /* G_VECREDUCE_UMAX */
    type0, type1, 
    /* G_VECREDUCE_UMIN */
    type0, type1, 
    /* G_SBFX */
    type0, type0, type1, type1, 
    /* G_UBFX */
    type0, type0, type1, type1, 
    /* ADJCALLSTACKDOWN */
    i32imm, i32imm, 
    /* ADJCALLSTACKUP */
    i32imm, i32imm, 
    /* ADJDYNALLOC */
    GPR, GPR, 
    /* CALL */
    CallTarget, 
    /* CALLR */
    GPR, 
    /* ADDC_F_I_HI */
    GPR, GPR, i32hi16, 
    /* ADDC_F_I_LO */
    GPR, GPR, i32lo16z, 
    /* ADDC_F_R */
    GPR, GPR, GPR, i32imm, 
    /* ADDC_I_HI */
    GPR, GPR, i32hi16, 
    /* ADDC_I_LO */
    GPR, GPR, i32lo16z, 
    /* ADDC_R */
    GPR, GPR, GPR, i32imm, 
    /* ADD_F_I_HI */
    GPR, GPR, i32hi16, 
    /* ADD_F_I_LO */
    GPR, GPR, i32lo16z, 
    /* ADD_F_R */
    GPR, GPR, GPR, i32imm, 
    /* ADD_I_HI */
    GPR, GPR, i32hi16, 
    /* ADD_I_LO */
    GPR, GPR, i32lo16z, 
    /* ADD_R */
    GPR, GPR, GPR, i32imm, 
    /* AND_F_I_HI */
    GPR, GPR, i32hi16and, 
    /* AND_F_I_LO */
    GPR, GPR, i32lo16and, 
    /* AND_F_R */
    GPR, GPR, GPR, i32imm, 
    /* AND_I_HI */
    GPR, GPR, i32hi16and, 
    /* AND_I_LO */
    GPR, GPR, i32lo16and, 
    /* AND_R */
    GPR, GPR, GPR, i32imm, 
    /* BRCC */
    BrTarget, CCOp, 
    /* BRIND_CC */
    GPR, CCOp, 
    /* BRIND_CCA */
    GPR, GPR, CCOp, 
    /* BRR */
    i16imm, CCOp, 
    /* BT */
    BrTarget, 
    /* JR */
    GPR, 
    /* LDADDR */
    GPR, i32lo21, 
    /* LDBs_RI */
    GPR, GPR, imm10, AluOp, 
    /* LDBs_RR */
    GPR, GPR, GPR, AluOp, 
    /* LDBz_RI */
    GPR, GPR, imm10, AluOp, 
    /* LDBz_RR */
    GPR, GPR, GPR, AluOp, 
    /* LDHs_RI */
    GPR, GPR, imm10, AluOp, 
    /* LDHs_RR */
    GPR, GPR, GPR, AluOp, 
    /* LDHz_RI */
    GPR, GPR, imm10, AluOp, 
    /* LDHz_RR */
    GPR, GPR, GPR, AluOp, 
    /* LDW_RI */
    GPR, GPR, i32lo16s, AluOp, 
    /* LDW_RR */
    GPR, GPR, GPR, AluOp, 
    /* LDWz_RR */
    GPR, GPR, GPR, AluOp, 
    /* LEADZ */
    GPR, GPR, 
    /* LOG0 */
    /* LOG1 */
    /* LOG2 */
    /* LOG3 */
    /* LOG4 */
    /* MOVHI */
    GPR, i32hi16, 
    /* NOP */
    /* OR_F_I_HI */
    GPR, GPR, i32hi16, 
    /* OR_F_I_LO */
    GPR, GPR, i32lo16z, 
    /* OR_F_R */
    GPR, GPR, GPR, i32imm, 
    /* OR_I_HI */
    GPR, GPR, i32hi16, 
    /* OR_I_LO */
    GPR, GPR, i32lo16z, 
    /* OR_R */
    GPR, GPR, GPR, i32imm, 
    /* POPC */
    GPR, GPR, 
    /* RET */
    /* SA_F_I */
    GPR, GPR, immShift, 
    /* SA_I */
    GPR, GPR, immShift, 
    /* SCC */
    GPR, CCOp, 
    /* SELECT */
    GPR, GPR, GPR, CCOp, 
    /* SFSUB_F_RI_HI */
    GPR, i32hi16, 
    /* SFSUB_F_RI_LO */
    GPR, i32lo16z, 
    /* SFSUB_F_RR */
    GPR, GPR, 
    /* SHL_F_R */
    GPR, GPR, GPR, i32imm, 
    /* SHL_R */
    GPR, GPR, GPR, i32imm, 
    /* SLI */
    GPR, i32lo21, 
    /* SL_F_I */
    GPR, GPR, immShift, 
    /* SL_I */
    GPR, GPR, immShift, 
    /* SRA_F_R */
    GPR, GPR, GPR, i32imm, 
    /* SRA_R */
    GPR, GPR, GPR, i32imm, 
    /* SRL_F_R */
    GPR, GPR, GPR, i32imm, 
    /* SRL_R */
    GPR, GPR, GPR, i32imm, 
    /* STADDR */
    GPR, i32lo21, 
    /* STB_RI */
    GPR, GPR, imm10, AluOp, 
    /* STB_RR */
    GPR, GPR, GPR, AluOp, 
    /* STH_RI */
    GPR, GPR, imm10, AluOp, 
    /* STH_RR */
    GPR, GPR, GPR, AluOp, 
    /* SUBB_F_I_HI */
    GPR, GPR, i32hi16, 
    /* SUBB_F_I_LO */
    GPR, GPR, i32lo16z, 
    /* SUBB_F_R */
    GPR, GPR, GPR, i32imm, 
    /* SUBB_I_HI */
    GPR, GPR, i32hi16, 
    /* SUBB_I_LO */
    GPR, GPR, i32lo16z, 
    /* SUBB_R */
    GPR, GPR, GPR, i32imm, 
    /* SUB_F_I_HI */
    GPR, GPR, i32hi16, 
    /* SUB_F_I_LO */
    GPR, GPR, i32lo16z, 
    /* SUB_F_R */
    GPR, GPR, GPR, i32imm, 
    /* SUB_I_HI */
    GPR, GPR, i32hi16, 
    /* SUB_I_LO */
    GPR, GPR, i32lo16z, 
    /* SUB_R */
    GPR, GPR, GPR, i32imm, 
    /* SW_RI */
    GPR, GPR, i32lo16s, AluOp, 
    /* SW_RR */
    GPR, GPR, GPR, AluOp, 
    /* TRAILZ */
    GPR, GPR, 
    /* XOR_F_I_HI */
    GPR, GPR, i32hi16, 
    /* XOR_F_I_LO */
    GPR, GPR, i32lo16z, 
    /* XOR_F_R */
    GPR, GPR, GPR, i32imm, 
    /* XOR_I_HI */
    GPR, GPR, i32hi16, 
    /* XOR_I_LO */
    GPR, GPR, i32lo16z, 
    /* XOR_R */
    GPR, GPR, GPR, i32imm, 
  };
  return OpcodeOperandTypes[Offsets[Opcode] + OpIdx];
}
} // end namespace Lanai
} // end namespace llvm
#endif // GET_INSTRINFO_OPERAND_TYPE

#ifdef GET_INSTRINFO_MEM_OPERAND_SIZE
#undef GET_INSTRINFO_MEM_OPERAND_SIZE
namespace llvm {
namespace Lanai {
LLVM_READONLY
static int getMemOperandSize(int OpType) {
  switch (OpType) {
  default: return 0;
  }
}
} // end namespace Lanai
} // end namespace llvm
#endif // GET_INSTRINFO_MEM_OPERAND_SIZE

#ifdef GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP
#undef GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP
namespace llvm {
namespace Lanai {
LLVM_READONLY static unsigned
getLogicalOperandSize(uint16_t Opcode, uint16_t LogicalOpIdx) {
  return LogicalOpIdx;
}
LLVM_READONLY static inline unsigned
getLogicalOperandIdx(uint16_t Opcode, uint16_t LogicalOpIdx) {
  auto S = 0U;
  for (auto i = 0U; i < LogicalOpIdx; ++i)
    S += getLogicalOperandSize(Opcode, i);
  return S;
}
} // end namespace Lanai
} // end namespace llvm
#endif // GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP

#ifdef GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP
#undef GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP
namespace llvm {
namespace Lanai {
LLVM_READONLY static int
getLogicalOperandType(uint16_t Opcode, uint16_t LogicalOpIdx) {
  return -1;
}
} // end namespace Lanai
} // end namespace llvm
#endif // GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP

#ifdef GET_INSTRINFO_MC_HELPER_DECLS
#undef GET_INSTRINFO_MC_HELPER_DECLS

namespace llvm {
class MCInst;
class FeatureBitset;

namespace Lanai_MC {

void verifyInstructionPredicates(unsigned Opcode, const FeatureBitset &Features);

} // end namespace Lanai_MC
} // end namespace llvm

#endif // GET_INSTRINFO_MC_HELPER_DECLS

#ifdef GET_INSTRINFO_MC_HELPERS
#undef GET_INSTRINFO_MC_HELPERS

namespace llvm {
namespace Lanai_MC {

} // end namespace Lanai_MC
} // end namespace llvm

#endif // GET_GENISTRINFO_MC_HELPERS

#if (defined(ENABLE_INSTR_PREDICATE_VERIFIER) && !defined(NDEBUG)) ||\
    defined(GET_AVAILABLE_OPCODE_CHECKER)
#define GET_COMPUTE_FEATURES
#endif
#ifdef GET_COMPUTE_FEATURES
#undef GET_COMPUTE_FEATURES
namespace llvm {
namespace Lanai_MC {

// Bits for subtarget features that participate in instruction matching.
enum SubtargetFeatureBits : uint8_t {
};

inline FeatureBitset computeAvailableFeatures(const FeatureBitset &FB) {
  FeatureBitset Features;
  return Features;
}

inline FeatureBitset computeRequiredFeatures(unsigned Opcode) {
  enum : uint8_t {
    CEFBS_None,
  };

  static constexpr FeatureBitset FeatureBitsets[] = {
    {}, // CEFBS_None
  };
  static constexpr uint8_t RequiredFeaturesRefs[] = {
    CEFBS_None, // PHI = 0
    CEFBS_None, // INLINEASM = 1
    CEFBS_None, // INLINEASM_BR = 2
    CEFBS_None, // CFI_INSTRUCTION = 3
    CEFBS_None, // EH_LABEL = 4
    CEFBS_None, // GC_LABEL = 5
    CEFBS_None, // ANNOTATION_LABEL = 6
    CEFBS_None, // KILL = 7
    CEFBS_None, // EXTRACT_SUBREG = 8
    CEFBS_None, // INSERT_SUBREG = 9
    CEFBS_None, // IMPLICIT_DEF = 10
    CEFBS_None, // SUBREG_TO_REG = 11
    CEFBS_None, // COPY_TO_REGCLASS = 12
    CEFBS_None, // DBG_VALUE = 13
    CEFBS_None, // DBG_VALUE_LIST = 14
    CEFBS_None, // DBG_INSTR_REF = 15
    CEFBS_None, // DBG_PHI = 16
    CEFBS_None, // DBG_LABEL = 17
    CEFBS_None, // REG_SEQUENCE = 18
    CEFBS_None, // COPY = 19
    CEFBS_None, // BUNDLE = 20
    CEFBS_None, // LIFETIME_START = 21
    CEFBS_None, // LIFETIME_END = 22
    CEFBS_None, // PSEUDO_PROBE = 23
    CEFBS_None, // ARITH_FENCE = 24
    CEFBS_None, // STACKMAP = 25
    CEFBS_None, // FENTRY_CALL = 26
    CEFBS_None, // PATCHPOINT = 27
    CEFBS_None, // LOAD_STACK_GUARD = 28
    CEFBS_None, // PREALLOCATED_SETUP = 29
    CEFBS_None, // PREALLOCATED_ARG = 30
    CEFBS_None, // STATEPOINT = 31
    CEFBS_None, // LOCAL_ESCAPE = 32
    CEFBS_None, // FAULTING_OP = 33
    CEFBS_None, // PATCHABLE_OP = 34
    CEFBS_None, // PATCHABLE_FUNCTION_ENTER = 35
    CEFBS_None, // PATCHABLE_RET = 36
    CEFBS_None, // PATCHABLE_FUNCTION_EXIT = 37
    CEFBS_None, // PATCHABLE_TAIL_CALL = 38
    CEFBS_None, // PATCHABLE_EVENT_CALL = 39
    CEFBS_None, // PATCHABLE_TYPED_EVENT_CALL = 40
    CEFBS_None, // ICALL_BRANCH_FUNNEL = 41
    CEFBS_None, // FAKE_USE = 42
    CEFBS_None, // MEMBARRIER = 43
    CEFBS_None, // JUMP_TABLE_DEBUG_INFO = 44
    CEFBS_None, // CONVERGENCECTRL_ENTRY = 45
    CEFBS_None, // CONVERGENCECTRL_ANCHOR = 46
    CEFBS_None, // CONVERGENCECTRL_LOOP = 47
    CEFBS_None, // CONVERGENCECTRL_GLUE = 48
    CEFBS_None, // G_ASSERT_SEXT = 49
    CEFBS_None, // G_ASSERT_ZEXT = 50
    CEFBS_None, // G_ASSERT_ALIGN = 51
    CEFBS_None, // G_ADD = 52
    CEFBS_None, // G_SUB = 53
    CEFBS_None, // G_MUL = 54
    CEFBS_None, // G_SDIV = 55
    CEFBS_None, // G_UDIV = 56
    CEFBS_None, // G_SREM = 57
    CEFBS_None, // G_UREM = 58
    CEFBS_None, // G_SDIVREM = 59
    CEFBS_None, // G_UDIVREM = 60
    CEFBS_None, // G_AND = 61
    CEFBS_None, // G_OR = 62
    CEFBS_None, // G_XOR = 63
    CEFBS_None, // G_IMPLICIT_DEF = 64
    CEFBS_None, // G_PHI = 65
    CEFBS_None, // G_FRAME_INDEX = 66
    CEFBS_None, // G_GLOBAL_VALUE = 67
    CEFBS_None, // G_PTRAUTH_GLOBAL_VALUE = 68
    CEFBS_None, // G_CONSTANT_POOL = 69
    CEFBS_None, // G_EXTRACT = 70
    CEFBS_None, // G_UNMERGE_VALUES = 71
    CEFBS_None, // G_INSERT = 72
    CEFBS_None, // G_MERGE_VALUES = 73
    CEFBS_None, // G_BUILD_VECTOR = 74
    CEFBS_None, // G_BUILD_VECTOR_TRUNC = 75
    CEFBS_None, // G_CONCAT_VECTORS = 76
    CEFBS_None, // G_PTRTOINT = 77
    CEFBS_None, // G_INTTOPTR = 78
    CEFBS_None, // G_BITCAST = 79
    CEFBS_None, // G_FREEZE = 80
    CEFBS_None, // G_CONSTANT_FOLD_BARRIER = 81
    CEFBS_None, // G_INTRINSIC_FPTRUNC_ROUND = 82
    CEFBS_None, // G_INTRINSIC_TRUNC = 83
    CEFBS_None, // G_INTRINSIC_ROUND = 84
    CEFBS_None, // G_INTRINSIC_LRINT = 85
    CEFBS_None, // G_INTRINSIC_LLRINT = 86
    CEFBS_None, // G_INTRINSIC_ROUNDEVEN = 87
    CEFBS_None, // G_READCYCLECOUNTER = 88
    CEFBS_None, // G_READSTEADYCOUNTER = 89
    CEFBS_None, // G_LOAD = 90
    CEFBS_None, // G_SEXTLOAD = 91
    CEFBS_None, // G_ZEXTLOAD = 92
    CEFBS_None, // G_INDEXED_LOAD = 93
    CEFBS_None, // G_INDEXED_SEXTLOAD = 94
    CEFBS_None, // G_INDEXED_ZEXTLOAD = 95
    CEFBS_None, // G_STORE = 96
    CEFBS_None, // G_INDEXED_STORE = 97
    CEFBS_None, // G_ATOMIC_CMPXCHG_WITH_SUCCESS = 98
    CEFBS_None, // G_ATOMIC_CMPXCHG = 99
    CEFBS_None, // G_ATOMICRMW_XCHG = 100
    CEFBS_None, // G_ATOMICRMW_ADD = 101
    CEFBS_None, // G_ATOMICRMW_SUB = 102
    CEFBS_None, // G_ATOMICRMW_AND = 103
    CEFBS_None, // G_ATOMICRMW_NAND = 104
    CEFBS_None, // G_ATOMICRMW_OR = 105
    CEFBS_None, // G_ATOMICRMW_XOR = 106
    CEFBS_None, // G_ATOMICRMW_MAX = 107
    CEFBS_None, // G_ATOMICRMW_MIN = 108
    CEFBS_None, // G_ATOMICRMW_UMAX = 109
    CEFBS_None, // G_ATOMICRMW_UMIN = 110
    CEFBS_None, // G_ATOMICRMW_FADD = 111
    CEFBS_None, // G_ATOMICRMW_FSUB = 112
    CEFBS_None, // G_ATOMICRMW_FMAX = 113
    CEFBS_None, // G_ATOMICRMW_FMIN = 114
    CEFBS_None, // G_ATOMICRMW_UINC_WRAP = 115
    CEFBS_None, // G_ATOMICRMW_UDEC_WRAP = 116
    CEFBS_None, // G_FENCE = 117
    CEFBS_None, // G_PREFETCH = 118
    CEFBS_None, // G_BRCOND = 119
    CEFBS_None, // G_BRINDIRECT = 120
    CEFBS_None, // G_INVOKE_REGION_START = 121
    CEFBS_None, // G_INTRINSIC = 122
    CEFBS_None, // G_INTRINSIC_W_SIDE_EFFECTS = 123
    CEFBS_None, // G_INTRINSIC_CONVERGENT = 124
    CEFBS_None, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS = 125
    CEFBS_None, // G_ANYEXT = 126
    CEFBS_None, // G_TRUNC = 127
    CEFBS_None, // G_CONSTANT = 128
    CEFBS_None, // G_FCONSTANT = 129
    CEFBS_None, // G_VASTART = 130
    CEFBS_None, // G_VAARG = 131
    CEFBS_None, // G_SEXT = 132
    CEFBS_None, // G_SEXT_INREG = 133
    CEFBS_None, // G_ZEXT = 134
    CEFBS_None, // G_SHL = 135
    CEFBS_None, // G_LSHR = 136
    CEFBS_None, // G_ASHR = 137
    CEFBS_None, // G_FSHL = 138
    CEFBS_None, // G_FSHR = 139
    CEFBS_None, // G_ROTR = 140
    CEFBS_None, // G_ROTL = 141
    CEFBS_None, // G_ICMP = 142
    CEFBS_None, // G_FCMP = 143
    CEFBS_None, // G_SCMP = 144
    CEFBS_None, // G_UCMP = 145
    CEFBS_None, // G_SELECT = 146
    CEFBS_None, // G_UADDO = 147
    CEFBS_None, // G_UADDE = 148
    CEFBS_None, // G_USUBO = 149
    CEFBS_None, // G_USUBE = 150
    CEFBS_None, // G_SADDO = 151
    CEFBS_None, // G_SADDE = 152
    CEFBS_None, // G_SSUBO = 153
    CEFBS_None, // G_SSUBE = 154
    CEFBS_None, // G_UMULO = 155
    CEFBS_None, // G_SMULO = 156
    CEFBS_None, // G_UMULH = 157
    CEFBS_None, // G_SMULH = 158
    CEFBS_None, // G_UADDSAT = 159
    CEFBS_None, // G_SADDSAT = 160
    CEFBS_None, // G_USUBSAT = 161
    CEFBS_None, // G_SSUBSAT = 162
    CEFBS_None, // G_USHLSAT = 163
    CEFBS_None, // G_SSHLSAT = 164
    CEFBS_None, // G_SMULFIX = 165
    CEFBS_None, // G_UMULFIX = 166
    CEFBS_None, // G_SMULFIXSAT = 167
    CEFBS_None, // G_UMULFIXSAT = 168
    CEFBS_None, // G_SDIVFIX = 169
    CEFBS_None, // G_UDIVFIX = 170
    CEFBS_None, // G_SDIVFIXSAT = 171
    CEFBS_None, // G_UDIVFIXSAT = 172
    CEFBS_None, // G_FADD = 173
    CEFBS_None, // G_FSUB = 174
    CEFBS_None, // G_FMUL = 175
    CEFBS_None, // G_FMA = 176
    CEFBS_None, // G_FMAD = 177
    CEFBS_None, // G_FDIV = 178
    CEFBS_None, // G_FREM = 179
    CEFBS_None, // G_FPOW = 180
    CEFBS_None, // G_FPOWI = 181
    CEFBS_None, // G_FEXP = 182
    CEFBS_None, // G_FEXP2 = 183
    CEFBS_None, // G_FEXP10 = 184
    CEFBS_None, // G_FLOG = 185
    CEFBS_None, // G_FLOG2 = 186
    CEFBS_None, // G_FLOG10 = 187
    CEFBS_None, // G_FLDEXP = 188
    CEFBS_None, // G_FFREXP = 189
    CEFBS_None, // G_FNEG = 190
    CEFBS_None, // G_FPEXT = 191
    CEFBS_None, // G_FPTRUNC = 192
    CEFBS_None, // G_FPTOSI = 193
    CEFBS_None, // G_FPTOUI = 194
    CEFBS_None, // G_SITOFP = 195
    CEFBS_None, // G_UITOFP = 196
    CEFBS_None, // G_FABS = 197
    CEFBS_None, // G_FCOPYSIGN = 198
    CEFBS_None, // G_IS_FPCLASS = 199
    CEFBS_None, // G_FCANONICALIZE = 200
    CEFBS_None, // G_FMINNUM = 201
    CEFBS_None, // G_FMAXNUM = 202
    CEFBS_None, // G_FMINNUM_IEEE = 203
    CEFBS_None, // G_FMAXNUM_IEEE = 204
    CEFBS_None, // G_FMINIMUM = 205
    CEFBS_None, // G_FMAXIMUM = 206
    CEFBS_None, // G_GET_FPENV = 207
    CEFBS_None, // G_SET_FPENV = 208
    CEFBS_None, // G_RESET_FPENV = 209
    CEFBS_None, // G_GET_FPMODE = 210
    CEFBS_None, // G_SET_FPMODE = 211
    CEFBS_None, // G_RESET_FPMODE = 212
    CEFBS_None, // G_PTR_ADD = 213
    CEFBS_None, // G_PTRMASK = 214
    CEFBS_None, // G_SMIN = 215
    CEFBS_None, // G_SMAX = 216
    CEFBS_None, // G_UMIN = 217
    CEFBS_None, // G_UMAX = 218
    CEFBS_None, // G_ABS = 219
    CEFBS_None, // G_LROUND = 220
    CEFBS_None, // G_LLROUND = 221
    CEFBS_None, // G_BR = 222
    CEFBS_None, // G_BRJT = 223
    CEFBS_None, // G_VSCALE = 224
    CEFBS_None, // G_INSERT_SUBVECTOR = 225
    CEFBS_None, // G_EXTRACT_SUBVECTOR = 226
    CEFBS_None, // G_INSERT_VECTOR_ELT = 227
    CEFBS_None, // G_EXTRACT_VECTOR_ELT = 228
    CEFBS_None, // G_SHUFFLE_VECTOR = 229
    CEFBS_None, // G_SPLAT_VECTOR = 230
    CEFBS_None, // G_VECTOR_COMPRESS = 231
    CEFBS_None, // G_CTTZ = 232
    CEFBS_None, // G_CTTZ_ZERO_UNDEF = 233
    CEFBS_None, // G_CTLZ = 234
    CEFBS_None, // G_CTLZ_ZERO_UNDEF = 235
    CEFBS_None, // G_CTPOP = 236
    CEFBS_None, // G_BSWAP = 237
    CEFBS_None, // G_BITREVERSE = 238
    CEFBS_None, // G_FCEIL = 239
    CEFBS_None, // G_FCOS = 240
    CEFBS_None, // G_FSIN = 241
    CEFBS_None, // G_FTAN = 242
    CEFBS_None, // G_FACOS = 243
    CEFBS_None, // G_FASIN = 244
    CEFBS_None, // G_FATAN = 245
    CEFBS_None, // G_FCOSH = 246
    CEFBS_None, // G_FSINH = 247
    CEFBS_None, // G_FTANH = 248
    CEFBS_None, // G_FSQRT = 249
    CEFBS_None, // G_FFLOOR = 250
    CEFBS_None, // G_FRINT = 251
    CEFBS_None, // G_FNEARBYINT = 252
    CEFBS_None, // G_ADDRSPACE_CAST = 253
    CEFBS_None, // G_BLOCK_ADDR = 254
    CEFBS_None, // G_JUMP_TABLE = 255
    CEFBS_None, // G_DYN_STACKALLOC = 256
    CEFBS_None, // G_STACKSAVE = 257
    CEFBS_None, // G_STACKRESTORE = 258
    CEFBS_None, // G_STRICT_FADD = 259
    CEFBS_None, // G_STRICT_FSUB = 260
    CEFBS_None, // G_STRICT_FMUL = 261
    CEFBS_None, // G_STRICT_FDIV = 262
    CEFBS_None, // G_STRICT_FREM = 263
    CEFBS_None, // G_STRICT_FMA = 264
    CEFBS_None, // G_STRICT_FSQRT = 265
    CEFBS_None, // G_STRICT_FLDEXP = 266
    CEFBS_None, // G_READ_REGISTER = 267
    CEFBS_None, // G_WRITE_REGISTER = 268
    CEFBS_None, // G_MEMCPY = 269
    CEFBS_None, // G_MEMCPY_INLINE = 270
    CEFBS_None, // G_MEMMOVE = 271
    CEFBS_None, // G_MEMSET = 272
    CEFBS_None, // G_BZERO = 273
    CEFBS_None, // G_TRAP = 274
    CEFBS_None, // G_DEBUGTRAP = 275
    CEFBS_None, // G_UBSANTRAP = 276
    CEFBS_None, // G_VECREDUCE_SEQ_FADD = 277
    CEFBS_None, // G_VECREDUCE_SEQ_FMUL = 278
    CEFBS_None, // G_VECREDUCE_FADD = 279
    CEFBS_None, // G_VECREDUCE_FMUL = 280
    CEFBS_None, // G_VECREDUCE_FMAX = 281
    CEFBS_None, // G_VECREDUCE_FMIN = 282
    CEFBS_None, // G_VECREDUCE_FMAXIMUM = 283
    CEFBS_None, // G_VECREDUCE_FMINIMUM = 284
    CEFBS_None, // G_VECREDUCE_ADD = 285
    CEFBS_None, // G_VECREDUCE_MUL = 286
    CEFBS_None, // G_VECREDUCE_AND = 287
    CEFBS_None, // G_VECREDUCE_OR = 288
    CEFBS_None, // G_VECREDUCE_XOR = 289
    CEFBS_None, // G_VECREDUCE_SMAX = 290
    CEFBS_None, // G_VECREDUCE_SMIN = 291
    CEFBS_None, // G_VECREDUCE_UMAX = 292
    CEFBS_None, // G_VECREDUCE_UMIN = 293
    CEFBS_None, // G_SBFX = 294
    CEFBS_None, // G_UBFX = 295
    CEFBS_None, // ADJCALLSTACKDOWN = 296
    CEFBS_None, // ADJCALLSTACKUP = 297
    CEFBS_None, // ADJDYNALLOC = 298
    CEFBS_None, // CALL = 299
    CEFBS_None, // CALLR = 300
    CEFBS_None, // ADDC_F_I_HI = 301
    CEFBS_None, // ADDC_F_I_LO = 302
    CEFBS_None, // ADDC_F_R = 303
    CEFBS_None, // ADDC_I_HI = 304
    CEFBS_None, // ADDC_I_LO = 305
    CEFBS_None, // ADDC_R = 306
    CEFBS_None, // ADD_F_I_HI = 307
    CEFBS_None, // ADD_F_I_LO = 308
    CEFBS_None, // ADD_F_R = 309
    CEFBS_None, // ADD_I_HI = 310
    CEFBS_None, // ADD_I_LO = 311
    CEFBS_None, // ADD_R = 312
    CEFBS_None, // AND_F_I_HI = 313
    CEFBS_None, // AND_F_I_LO = 314
    CEFBS_None, // AND_F_R = 315
    CEFBS_None, // AND_I_HI = 316
    CEFBS_None, // AND_I_LO = 317
    CEFBS_None, // AND_R = 318
    CEFBS_None, // BRCC = 319
    CEFBS_None, // BRIND_CC = 320
    CEFBS_None, // BRIND_CCA = 321
    CEFBS_None, // BRR = 322
    CEFBS_None, // BT = 323
    CEFBS_None, // JR = 324
    CEFBS_None, // LDADDR = 325
    CEFBS_None, // LDBs_RI = 326
    CEFBS_None, // LDBs_RR = 327
    CEFBS_None, // LDBz_RI = 328
    CEFBS_None, // LDBz_RR = 329
    CEFBS_None, // LDHs_RI = 330
    CEFBS_None, // LDHs_RR = 331
    CEFBS_None, // LDHz_RI = 332
    CEFBS_None, // LDHz_RR = 333
    CEFBS_None, // LDW_RI = 334
    CEFBS_None, // LDW_RR = 335
    CEFBS_None, // LDWz_RR = 336
    CEFBS_None, // LEADZ = 337
    CEFBS_None, // LOG0 = 338
    CEFBS_None, // LOG1 = 339
    CEFBS_None, // LOG2 = 340
    CEFBS_None, // LOG3 = 341
    CEFBS_None, // LOG4 = 342
    CEFBS_None, // MOVHI = 343
    CEFBS_None, // NOP = 344
    CEFBS_None, // OR_F_I_HI = 345
    CEFBS_None, // OR_F_I_LO = 346
    CEFBS_None, // OR_F_R = 347
    CEFBS_None, // OR_I_HI = 348
    CEFBS_None, // OR_I_LO = 349
    CEFBS_None, // OR_R = 350
    CEFBS_None, // POPC = 351
    CEFBS_None, // RET = 352
    CEFBS_None, // SA_F_I = 353
    CEFBS_None, // SA_I = 354
    CEFBS_None, // SCC = 355
    CEFBS_None, // SELECT = 356
    CEFBS_None, // SFSUB_F_RI_HI = 357
    CEFBS_None, // SFSUB_F_RI_LO = 358
    CEFBS_None, // SFSUB_F_RR = 359
    CEFBS_None, // SHL_F_R = 360
    CEFBS_None, // SHL_R = 361
    CEFBS_None, // SLI = 362
    CEFBS_None, // SL_F_I = 363
    CEFBS_None, // SL_I = 364
    CEFBS_None, // SRA_F_R = 365
    CEFBS_None, // SRA_R = 366
    CEFBS_None, // SRL_F_R = 367
    CEFBS_None, // SRL_R = 368
    CEFBS_None, // STADDR = 369
    CEFBS_None, // STB_RI = 370
    CEFBS_None, // STB_RR = 371
    CEFBS_None, // STH_RI = 372
    CEFBS_None, // STH_RR = 373
    CEFBS_None, // SUBB_F_I_HI = 374
    CEFBS_None, // SUBB_F_I_LO = 375
    CEFBS_None, // SUBB_F_R = 376
    CEFBS_None, // SUBB_I_HI = 377
    CEFBS_None, // SUBB_I_LO = 378
    CEFBS_None, // SUBB_R = 379
    CEFBS_None, // SUB_F_I_HI = 380
    CEFBS_None, // SUB_F_I_LO = 381
    CEFBS_None, // SUB_F_R = 382
    CEFBS_None, // SUB_I_HI = 383
    CEFBS_None, // SUB_I_LO = 384
    CEFBS_None, // SUB_R = 385
    CEFBS_None, // SW_RI = 386
    CEFBS_None, // SW_RR = 387
    CEFBS_None, // TRAILZ = 388
    CEFBS_None, // XOR_F_I_HI = 389
    CEFBS_None, // XOR_F_I_LO = 390
    CEFBS_None, // XOR_F_R = 391
    CEFBS_None, // XOR_I_HI = 392
    CEFBS_None, // XOR_I_LO = 393
    CEFBS_None, // XOR_R = 394
  };

  assert(Opcode < 395);
  return FeatureBitsets[RequiredFeaturesRefs[Opcode]];
}

} // end namespace Lanai_MC
} // end namespace llvm
#endif // GET_COMPUTE_FEATURES

#ifdef GET_AVAILABLE_OPCODE_CHECKER
#undef GET_AVAILABLE_OPCODE_CHECKER
namespace llvm {
namespace Lanai_MC {
bool isOpcodeAvailable(unsigned Opcode, const FeatureBitset &Features) {
  FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
  FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
  FeatureBitset MissingFeatures =
      (AvailableFeatures & RequiredFeatures) ^
      RequiredFeatures;
  return !MissingFeatures.any();
}
} // end namespace Lanai_MC
} // end namespace llvm
#endif // GET_AVAILABLE_OPCODE_CHECKER

#ifdef ENABLE_INSTR_PREDICATE_VERIFIER
#undef ENABLE_INSTR_PREDICATE_VERIFIER
#include <sstream>

namespace llvm {
namespace Lanai_MC {

#ifndef NDEBUG
static const char *SubtargetFeatureNames[] = {
  nullptr
};

#endif // NDEBUG

void verifyInstructionPredicates(
    unsigned Opcode, const FeatureBitset &Features) {
#ifndef NDEBUG
  FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
  FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
  FeatureBitset MissingFeatures =
      (AvailableFeatures & RequiredFeatures) ^
      RequiredFeatures;
  if (MissingFeatures.any()) {
    std::ostringstream Msg;
    Msg << "Attempting to emit " << &LanaiInstrNameData[LanaiInstrNameIndices[Opcode]]
        << " instruction but the ";
    for (unsigned i = 0, e = MissingFeatures.size(); i != e; ++i)
      if (MissingFeatures.test(i))
        Msg << SubtargetFeatureNames[i] << " ";
    Msg << "predicate(s) are not met";
    report_fatal_error(Msg.str().c_str());
  }
#endif // NDEBUG
}
} // end namespace Lanai_MC
} // end namespace llvm
#endif // ENABLE_INSTR_PREDICATE_VERIFIER

#ifdef GET_INSTRMAP_INFO
#undef GET_INSTRMAP_INFO
namespace llvm {

namespace Lanai {

enum PostEncoderMethod {
	PostEncoderMethod_adjustPqBitsSpls
};

// splsIdempotent
LLVM_READONLY
int splsIdempotent(uint16_t Opcode) {
static const uint16_t splsIdempotentTable[][2] = {
  { Lanai::LDBs_RI, Lanai::LDBs_RI },
  { Lanai::LDBz_RI, Lanai::LDBz_RI },
  { Lanai::LDHs_RI, Lanai::LDHs_RI },
  { Lanai::LDHz_RI, Lanai::LDHz_RI },
  { Lanai::STB_RI, Lanai::STB_RI },
  { Lanai::STH_RI, Lanai::STH_RI },
}; // End of splsIdempotentTable

  unsigned mid;
  unsigned start = 0;
  unsigned end = 6;
  while (start < end) {
    mid = start + (end - start) / 2;
    if (Opcode == splsIdempotentTable[mid][0]) {
      break;
    }
    if (Opcode < splsIdempotentTable[mid][0])
      end = mid;
    else
      start = mid + 1;
  }
  if (start == end)
    return -1; // Instruction doesn't exist in this table.

  return splsIdempotentTable[mid][1];
}

} // end namespace Lanai
} // end namespace llvm
#endif // GET_INSTRMAP_INFO