/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |* *| |* Target Instruction Enum Values and Descriptors *| |* *| |* Automatically generated file, do not edit! *| |* *| \*===----------------------------------------------------------------------===*/ #ifdef GET_INSTRINFO_ENUM #undef GET_INSTRINFO_ENUM namespace llvm { namespace LoongArch { enum { … }; } // end namespace LoongArch } // end namespace llvm #endif // GET_INSTRINFO_ENUM #ifdef GET_INSTRINFO_SCHED_ENUM #undef GET_INSTRINFO_SCHED_ENUM namespace llvm { namespace LoongArch { namespace Sched { enum { NoInstrModel = 0, SCHED_LIST_END = 1 }; } // end namespace Sched } // end namespace LoongArch } // end namespace llvm #endif // GET_INSTRINFO_SCHED_ENUM #if defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR) namespace llvm { struct LoongArchInstrTable { MCInstrDesc Insts[2429]; static_assert(alignof(MCInstrDesc) >= alignof(MCOperandInfo), "Unwanted padding between Insts and OperandInfo"); MCOperandInfo OperandInfo[417]; static_assert(alignof(MCOperandInfo) >= alignof(MCPhysReg), "Unwanted padding between OperandInfo and ImplicitOps"); MCPhysReg ImplicitOps[8]; }; } // end namespace llvm #endif // defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR) #ifdef GET_INSTRINFO_MC_DESC #undef GET_INSTRINFO_MC_DESC namespace llvm { static_assert(sizeof(MCOperandInfo) % sizeof(MCPhysReg) == 0); static constexpr unsigned LoongArchImpOpBase = sizeof LoongArchInstrTable::OperandInfo / (sizeof(MCPhysReg)); extern const LoongArchInstrTable LoongArchDescs = { { { 2428, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2428 = XVXOR_V { 2427, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2427 = XVXORI_B { 2426, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2426 = XVSUB_W { 2425, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2425 = XVSUB_Q { 2424, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2424 = XVSUB_H { 2423, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2423 = XVSUB_D { 2422, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2422 = XVSUB_B { 2421, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2421 = XVSUBWOD_W_HU { 2420, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2420 = XVSUBWOD_W_H { 2419, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2419 = XVSUBWOD_Q_DU { 2418, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2418 = XVSUBWOD_Q_D { 2417, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2417 = XVSUBWOD_H_BU { 2416, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2416 = XVSUBWOD_H_B { 2415, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2415 = XVSUBWOD_D_WU { 2414, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2414 = XVSUBWOD_D_W { 2413, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2413 = XVSUBWEV_W_HU { 2412, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2412 = XVSUBWEV_W_H { 2411, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2411 = XVSUBWEV_Q_DU { 2410, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2410 = XVSUBWEV_Q_D { 2409, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2409 = XVSUBWEV_H_BU { 2408, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2408 = XVSUBWEV_H_B { 2407, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2407 = XVSUBWEV_D_WU { 2406, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2406 = XVSUBWEV_D_W { 2405, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2405 = XVSUBI_WU { 2404, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2404 = XVSUBI_HU { 2403, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2403 = XVSUBI_DU { 2402, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2402 = XVSUBI_BU { 2401, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 400, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #2401 = XVSTX { 2400, 4, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 413, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #2400 = XVSTELM_W { 2399, 4, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 413, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #2399 = XVSTELM_H { 2398, 4, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 413, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #2398 = XVSTELM_D { 2397, 4, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 413, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #2397 = XVSTELM_B { 2396, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 397, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #2396 = XVST { 2395, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2395 = XVSSUB_WU { 2394, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2394 = XVSSUB_W { 2393, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2393 = XVSSUB_HU { 2392, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2392 = XVSSUB_H { 2391, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2391 = XVSSUB_DU { 2390, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2390 = XVSSUB_D { 2389, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2389 = XVSSUB_BU { 2388, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2388 = XVSSUB_B { 2387, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2387 = XVSSRLRN_W_D { 2386, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2386 = XVSSRLRN_WU_D { 2385, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2385 = XVSSRLRN_H_W { 2384, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2384 = XVSSRLRN_HU_W { 2383, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2383 = XVSSRLRN_B_H { 2382, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2382 = XVSSRLRN_BU_H { 2381, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #2381 = XVSSRLRNI_W_D { 2380, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #2380 = XVSSRLRNI_WU_D { 2379, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #2379 = XVSSRLRNI_H_W { 2378, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #2378 = XVSSRLRNI_HU_W { 2377, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #2377 = XVSSRLRNI_D_Q { 2376, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #2376 = XVSSRLRNI_DU_Q { 2375, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #2375 = XVSSRLRNI_B_H { 2374, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #2374 = XVSSRLRNI_BU_H { 2373, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2373 = XVSSRLN_W_D { 2372, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2372 = XVSSRLN_WU_D { 2371, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2371 = XVSSRLN_H_W { 2370, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2370 = XVSSRLN_HU_W { 2369, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2369 = XVSSRLN_B_H { 2368, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2368 = XVSSRLN_BU_H { 2367, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #2367 = XVSSRLNI_W_D { 2366, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #2366 = XVSSRLNI_WU_D { 2365, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #2365 = XVSSRLNI_H_W { 2364, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #2364 = XVSSRLNI_HU_W { 2363, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #2363 = XVSSRLNI_D_Q { 2362, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #2362 = XVSSRLNI_DU_Q { 2361, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #2361 = XVSSRLNI_B_H { 2360, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #2360 = XVSSRLNI_BU_H { 2359, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2359 = XVSSRARN_W_D { 2358, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2358 = XVSSRARN_WU_D { 2357, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2357 = XVSSRARN_H_W { 2356, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2356 = XVSSRARN_HU_W { 2355, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2355 = XVSSRARN_B_H { 2354, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2354 = XVSSRARN_BU_H { 2353, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #2353 = XVSSRARNI_W_D { 2352, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #2352 = XVSSRARNI_WU_D { 2351, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #2351 = XVSSRARNI_H_W { 2350, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #2350 = XVSSRARNI_HU_W { 2349, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #2349 = XVSSRARNI_D_Q { 2348, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #2348 = XVSSRARNI_DU_Q { 2347, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #2347 = XVSSRARNI_B_H { 2346, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #2346 = XVSSRARNI_BU_H { 2345, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2345 = XVSSRAN_W_D { 2344, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2344 = XVSSRAN_WU_D { 2343, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2343 = XVSSRAN_H_W { 2342, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2342 = XVSSRAN_HU_W { 2341, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2341 = XVSSRAN_B_H { 2340, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2340 = XVSSRAN_BU_H { 2339, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #2339 = XVSSRANI_W_D { 2338, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #2338 = XVSSRANI_WU_D { 2337, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #2337 = XVSSRANI_H_W { 2336, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #2336 = XVSSRANI_HU_W { 2335, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #2335 = XVSSRANI_D_Q { 2334, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #2334 = XVSSRANI_DU_Q { 2333, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #2333 = XVSSRANI_B_H { 2332, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #2332 = XVSSRANI_BU_H { 2331, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2331 = XVSRL_W { 2330, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2330 = XVSRL_H { 2329, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2329 = XVSRL_D { 2328, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2328 = XVSRL_B { 2327, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2327 = XVSRLR_W { 2326, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2326 = XVSRLR_H { 2325, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2325 = XVSRLR_D { 2324, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2324 = XVSRLR_B { 2323, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2323 = XVSRLRN_W_D { 2322, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2322 = XVSRLRN_H_W { 2321, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2321 = XVSRLRN_B_H { 2320, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #2320 = XVSRLRNI_W_D { 2319, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #2319 = XVSRLRNI_H_W { 2318, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #2318 = XVSRLRNI_D_Q { 2317, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #2317 = XVSRLRNI_B_H { 2316, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2316 = XVSRLRI_W { 2315, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2315 = XVSRLRI_H { 2314, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2314 = XVSRLRI_D { 2313, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2313 = XVSRLRI_B { 2312, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2312 = XVSRLN_W_D { 2311, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2311 = XVSRLN_H_W { 2310, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2310 = XVSRLN_B_H { 2309, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #2309 = XVSRLNI_W_D { 2308, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #2308 = XVSRLNI_H_W { 2307, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #2307 = XVSRLNI_D_Q { 2306, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #2306 = XVSRLNI_B_H { 2305, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2305 = XVSRLI_W { 2304, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2304 = XVSRLI_H { 2303, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2303 = XVSRLI_D { 2302, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2302 = XVSRLI_B { 2301, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2301 = XVSRA_W { 2300, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2300 = XVSRA_H { 2299, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2299 = XVSRA_D { 2298, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2298 = XVSRA_B { 2297, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2297 = XVSRAR_W { 2296, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2296 = XVSRAR_H { 2295, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2295 = XVSRAR_D { 2294, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2294 = XVSRAR_B { 2293, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2293 = XVSRARN_W_D { 2292, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2292 = XVSRARN_H_W { 2291, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2291 = XVSRARN_B_H { 2290, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #2290 = XVSRARNI_W_D { 2289, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #2289 = XVSRARNI_H_W { 2288, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #2288 = XVSRARNI_D_Q { 2287, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #2287 = XVSRARNI_B_H { 2286, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2286 = XVSRARI_W { 2285, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2285 = XVSRARI_H { 2284, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2284 = XVSRARI_D { 2283, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2283 = XVSRARI_B { 2282, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2282 = XVSRAN_W_D { 2281, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2281 = XVSRAN_H_W { 2280, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2280 = XVSRAN_B_H { 2279, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #2279 = XVSRANI_W_D { 2278, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #2278 = XVSRANI_H_W { 2277, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #2277 = XVSRANI_D_Q { 2276, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #2276 = XVSRANI_B_H { 2275, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2275 = XVSRAI_W { 2274, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2274 = XVSRAI_H { 2273, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2273 = XVSRAI_D { 2272, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2272 = XVSRAI_B { 2271, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2271 = XVSLT_WU { 2270, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2270 = XVSLT_W { 2269, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2269 = XVSLT_HU { 2268, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2268 = XVSLT_H { 2267, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2267 = XVSLT_DU { 2266, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2266 = XVSLT_D { 2265, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2265 = XVSLT_BU { 2264, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2264 = XVSLT_B { 2263, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2263 = XVSLTI_WU { 2262, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2262 = XVSLTI_W { 2261, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2261 = XVSLTI_HU { 2260, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2260 = XVSLTI_H { 2259, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2259 = XVSLTI_DU { 2258, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2258 = XVSLTI_D { 2257, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2257 = XVSLTI_BU { 2256, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2256 = XVSLTI_B { 2255, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2255 = XVSLL_W { 2254, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2254 = XVSLL_H { 2253, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2253 = XVSLL_D { 2252, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2252 = XVSLL_B { 2251, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2251 = XVSLLWIL_W_H { 2250, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2250 = XVSLLWIL_WU_HU { 2249, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2249 = XVSLLWIL_H_B { 2248, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2248 = XVSLLWIL_HU_BU { 2247, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2247 = XVSLLWIL_D_W { 2246, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2246 = XVSLLWIL_DU_WU { 2245, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2245 = XVSLLI_W { 2244, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2244 = XVSLLI_H { 2243, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2243 = XVSLLI_D { 2242, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2242 = XVSLLI_B { 2241, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2241 = XVSLE_WU { 2240, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2240 = XVSLE_W { 2239, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2239 = XVSLE_HU { 2238, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2238 = XVSLE_H { 2237, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2237 = XVSLE_DU { 2236, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2236 = XVSLE_D { 2235, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2235 = XVSLE_BU { 2234, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2234 = XVSLE_B { 2233, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2233 = XVSLEI_WU { 2232, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2232 = XVSLEI_W { 2231, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2231 = XVSLEI_HU { 2230, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2230 = XVSLEI_H { 2229, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2229 = XVSLEI_DU { 2228, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2228 = XVSLEI_D { 2227, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2227 = XVSLEI_BU { 2226, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2226 = XVSLEI_B { 2225, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2225 = XVSIGNCOV_W { 2224, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2224 = XVSIGNCOV_H { 2223, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2223 = XVSIGNCOV_D { 2222, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2222 = XVSIGNCOV_B { 2221, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 393, 0, 0x0ULL }, // Inst #2221 = XVSHUF_W { 2220, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 393, 0, 0x0ULL }, // Inst #2220 = XVSHUF_H { 2219, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 393, 0, 0x0ULL }, // Inst #2219 = XVSHUF_D { 2218, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 389, 0, 0x0ULL }, // Inst #2218 = XVSHUF_B { 2217, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2217 = XVSHUF4I_W { 2216, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2216 = XVSHUF4I_H { 2215, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #2215 = XVSHUF4I_D { 2214, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2214 = XVSHUF4I_B { 2213, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 411, 0, 0x0ULL }, // Inst #2213 = XVSETNEZ_V { 2212, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 411, 0, 0x0ULL }, // Inst #2212 = XVSETEQZ_V { 2211, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 411, 0, 0x0ULL }, // Inst #2211 = XVSETANYEQZ_W { 2210, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 411, 0, 0x0ULL }, // Inst #2210 = XVSETANYEQZ_H { 2209, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 411, 0, 0x0ULL }, // Inst #2209 = XVSETANYEQZ_D { 2208, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 411, 0, 0x0ULL }, // Inst #2208 = XVSETANYEQZ_B { 2207, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 411, 0, 0x0ULL }, // Inst #2207 = XVSETALLNEZ_W { 2206, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 411, 0, 0x0ULL }, // Inst #2206 = XVSETALLNEZ_H { 2205, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 411, 0, 0x0ULL }, // Inst #2205 = XVSETALLNEZ_D { 2204, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 411, 0, 0x0ULL }, // Inst #2204 = XVSETALLNEZ_B { 2203, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2203 = XVSEQ_W { 2202, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2202 = XVSEQ_H { 2201, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2201 = XVSEQ_D { 2200, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2200 = XVSEQ_B { 2199, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2199 = XVSEQI_W { 2198, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2198 = XVSEQI_H { 2197, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2197 = XVSEQI_D { 2196, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2196 = XVSEQI_B { 2195, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2195 = XVSAT_WU { 2194, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2194 = XVSAT_W { 2193, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2193 = XVSAT_HU { 2192, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2192 = XVSAT_H { 2191, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2191 = XVSAT_DU { 2190, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2190 = XVSAT_D { 2189, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2189 = XVSAT_BU { 2188, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2188 = XVSAT_B { 2187, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2187 = XVSADD_WU { 2186, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2186 = XVSADD_W { 2185, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2185 = XVSADD_HU { 2184, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2184 = XVSADD_H { 2183, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2183 = XVSADD_DU { 2182, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2182 = XVSADD_D { 2181, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2181 = XVSADD_BU { 2180, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2180 = XVSADD_B { 2179, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2179 = XVROTR_W { 2178, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2178 = XVROTR_H { 2177, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2177 = XVROTR_D { 2176, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2176 = XVROTR_B { 2175, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2175 = XVROTRI_W { 2174, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2174 = XVROTRI_H { 2173, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2173 = XVROTRI_D { 2172, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2172 = XVROTRI_B { 2171, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 408, 0, 0x0ULL }, // Inst #2171 = XVREPLVE_W { 2170, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 408, 0, 0x0ULL }, // Inst #2170 = XVREPLVE_H { 2169, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 408, 0, 0x0ULL }, // Inst #2169 = XVREPLVE_D { 2168, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 408, 0, 0x0ULL }, // Inst #2168 = XVREPLVE_B { 2167, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #2167 = XVREPLVE0_W { 2166, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #2166 = XVREPLVE0_Q { 2165, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #2165 = XVREPLVE0_H { 2164, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #2164 = XVREPLVE0_D { 2163, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #2163 = XVREPLVE0_B { 2162, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 406, 0, 0x0ULL }, // Inst #2162 = XVREPLGR2VR_W { 2161, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 406, 0, 0x0ULL }, // Inst #2161 = XVREPLGR2VR_H { 2160, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 406, 0, 0x0ULL }, // Inst #2160 = XVREPLGR2VR_D { 2159, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 406, 0, 0x0ULL }, // Inst #2159 = XVREPLGR2VR_B { 2158, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2158 = XVREPL128VEI_W { 2157, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2157 = XVREPL128VEI_H { 2156, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2156 = XVREPL128VEI_D { 2155, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2155 = XVREPL128VEI_B { 2154, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2154 = XVPICKVE_W { 2153, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2153 = XVPICKVE_D { 2152, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 403, 0, 0x0ULL }, // Inst #2152 = XVPICKVE2GR_WU { 2151, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 403, 0, 0x0ULL }, // Inst #2151 = XVPICKVE2GR_W { 2150, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 403, 0, 0x0ULL }, // Inst #2150 = XVPICKVE2GR_DU { 2149, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 403, 0, 0x0ULL }, // Inst #2149 = XVPICKVE2GR_D { 2148, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2148 = XVPICKOD_W { 2147, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2147 = XVPICKOD_H { 2146, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2146 = XVPICKOD_D { 2145, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2145 = XVPICKOD_B { 2144, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2144 = XVPICKEV_W { 2143, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2143 = XVPICKEV_H { 2142, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2142 = XVPICKEV_D { 2141, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2141 = XVPICKEV_B { 2140, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2140 = XVPERM_W { 2139, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #2139 = XVPERMI_W { 2138, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #2138 = XVPERMI_Q { 2137, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2137 = XVPERMI_D { 2136, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #2136 = XVPCNT_W { 2135, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #2135 = XVPCNT_H { 2134, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #2134 = XVPCNT_D { 2133, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #2133 = XVPCNT_B { 2132, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2132 = XVPACKOD_W { 2131, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2131 = XVPACKOD_H { 2130, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2130 = XVPACKOD_D { 2129, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2129 = XVPACKOD_B { 2128, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2128 = XVPACKEV_W { 2127, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2127 = XVPACKEV_H { 2126, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2126 = XVPACKEV_D { 2125, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2125 = XVPACKEV_B { 2124, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2124 = XVOR_V { 2123, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2123 = XVORN_V { 2122, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2122 = XVORI_B { 2121, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2121 = XVNOR_V { 2120, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2120 = XVNORI_B { 2119, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #2119 = XVNEG_W { 2118, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #2118 = XVNEG_H { 2117, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #2117 = XVNEG_D { 2116, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #2116 = XVNEG_B { 2115, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2115 = XVMUL_W { 2114, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2114 = XVMUL_H { 2113, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2113 = XVMUL_D { 2112, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2112 = XVMUL_B { 2111, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2111 = XVMULWOD_W_HU_H { 2110, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2110 = XVMULWOD_W_HU { 2109, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2109 = XVMULWOD_W_H { 2108, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2108 = XVMULWOD_Q_DU_D { 2107, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2107 = XVMULWOD_Q_DU { 2106, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2106 = XVMULWOD_Q_D { 2105, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2105 = XVMULWOD_H_BU_B { 2104, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2104 = XVMULWOD_H_BU { 2103, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2103 = XVMULWOD_H_B { 2102, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2102 = XVMULWOD_D_WU_W { 2101, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2101 = XVMULWOD_D_WU { 2100, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2100 = XVMULWOD_D_W { 2099, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2099 = XVMULWEV_W_HU_H { 2098, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2098 = XVMULWEV_W_HU { 2097, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2097 = XVMULWEV_W_H { 2096, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2096 = XVMULWEV_Q_DU_D { 2095, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2095 = XVMULWEV_Q_DU { 2094, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2094 = XVMULWEV_Q_D { 2093, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2093 = XVMULWEV_H_BU_B { 2092, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2092 = XVMULWEV_H_BU { 2091, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2091 = XVMULWEV_H_B { 2090, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2090 = XVMULWEV_D_WU_W { 2089, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2089 = XVMULWEV_D_WU { 2088, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2088 = XVMULWEV_D_W { 2087, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2087 = XVMUH_WU { 2086, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2086 = XVMUH_W { 2085, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2085 = XVMUH_HU { 2084, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2084 = XVMUH_H { 2083, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2083 = XVMUH_DU { 2082, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2082 = XVMUH_D { 2081, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2081 = XVMUH_BU { 2080, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2080 = XVMUH_B { 2079, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 393, 0, 0x0ULL }, // Inst #2079 = XVMSUB_W { 2078, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 393, 0, 0x0ULL }, // Inst #2078 = XVMSUB_H { 2077, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 393, 0, 0x0ULL }, // Inst #2077 = XVMSUB_D { 2076, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 393, 0, 0x0ULL }, // Inst #2076 = XVMSUB_B { 2075, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #2075 = XVMSKNZ_B { 2074, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #2074 = XVMSKLTZ_W { 2073, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #2073 = XVMSKLTZ_H { 2072, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #2072 = XVMSKLTZ_D { 2071, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #2071 = XVMSKLTZ_B { 2070, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #2070 = XVMSKGEZ_B { 2069, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2069 = XVMOD_WU { 2068, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2068 = XVMOD_W { 2067, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2067 = XVMOD_HU { 2066, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2066 = XVMOD_H { 2065, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2065 = XVMOD_DU { 2064, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2064 = XVMOD_D { 2063, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2063 = XVMOD_BU { 2062, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2062 = XVMOD_B { 2061, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2061 = XVMIN_WU { 2060, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2060 = XVMIN_W { 2059, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2059 = XVMIN_HU { 2058, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2058 = XVMIN_H { 2057, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2057 = XVMIN_DU { 2056, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2056 = XVMIN_D { 2055, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2055 = XVMIN_BU { 2054, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2054 = XVMIN_B { 2053, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2053 = XVMINI_WU { 2052, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2052 = XVMINI_W { 2051, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2051 = XVMINI_HU { 2050, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2050 = XVMINI_H { 2049, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2049 = XVMINI_DU { 2048, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2048 = XVMINI_D { 2047, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2047 = XVMINI_BU { 2046, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2046 = XVMINI_B { 2045, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2045 = XVMAX_WU { 2044, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2044 = XVMAX_W { 2043, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2043 = XVMAX_HU { 2042, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2042 = XVMAX_H { 2041, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2041 = XVMAX_DU { 2040, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2040 = XVMAX_D { 2039, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2039 = XVMAX_BU { 2038, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2038 = XVMAX_B { 2037, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2037 = XVMAXI_WU { 2036, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2036 = XVMAXI_W { 2035, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2035 = XVMAXI_HU { 2034, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2034 = XVMAXI_H { 2033, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2033 = XVMAXI_DU { 2032, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2032 = XVMAXI_D { 2031, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2031 = XVMAXI_BU { 2030, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2030 = XVMAXI_B { 2029, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 393, 0, 0x0ULL }, // Inst #2029 = XVMADD_W { 2028, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 393, 0, 0x0ULL }, // Inst #2028 = XVMADD_H { 2027, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 393, 0, 0x0ULL }, // Inst #2027 = XVMADD_D { 2026, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 393, 0, 0x0ULL }, // Inst #2026 = XVMADD_B { 2025, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 393, 0, 0x0ULL }, // Inst #2025 = XVMADDWOD_W_HU_H { 2024, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 393, 0, 0x0ULL }, // Inst #2024 = XVMADDWOD_W_HU { 2023, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 393, 0, 0x0ULL }, // Inst #2023 = XVMADDWOD_W_H { 2022, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 393, 0, 0x0ULL }, // Inst #2022 = XVMADDWOD_Q_DU_D { 2021, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 393, 0, 0x0ULL }, // Inst #2021 = XVMADDWOD_Q_DU { 2020, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 393, 0, 0x0ULL }, // Inst #2020 = XVMADDWOD_Q_D { 2019, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 393, 0, 0x0ULL }, // Inst #2019 = XVMADDWOD_H_BU_B { 2018, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 393, 0, 0x0ULL }, // Inst #2018 = XVMADDWOD_H_BU { 2017, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 393, 0, 0x0ULL }, // Inst #2017 = XVMADDWOD_H_B { 2016, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 393, 0, 0x0ULL }, // Inst #2016 = XVMADDWOD_D_WU_W { 2015, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 393, 0, 0x0ULL }, // Inst #2015 = XVMADDWOD_D_WU { 2014, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 393, 0, 0x0ULL }, // Inst #2014 = XVMADDWOD_D_W { 2013, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 393, 0, 0x0ULL }, // Inst #2013 = XVMADDWEV_W_HU_H { 2012, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 393, 0, 0x0ULL }, // Inst #2012 = XVMADDWEV_W_HU { 2011, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 393, 0, 0x0ULL }, // Inst #2011 = XVMADDWEV_W_H { 2010, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 393, 0, 0x0ULL }, // Inst #2010 = XVMADDWEV_Q_DU_D { 2009, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 393, 0, 0x0ULL }, // Inst #2009 = XVMADDWEV_Q_DU { 2008, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 393, 0, 0x0ULL }, // Inst #2008 = XVMADDWEV_Q_D { 2007, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 393, 0, 0x0ULL }, // Inst #2007 = XVMADDWEV_H_BU_B { 2006, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 393, 0, 0x0ULL }, // Inst #2006 = XVMADDWEV_H_BU { 2005, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 393, 0, 0x0ULL }, // Inst #2005 = XVMADDWEV_H_B { 2004, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 393, 0, 0x0ULL }, // Inst #2004 = XVMADDWEV_D_WU_W { 2003, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 393, 0, 0x0ULL }, // Inst #2003 = XVMADDWEV_D_WU { 2002, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 393, 0, 0x0ULL }, // Inst #2002 = XVMADDWEV_D_W { 2001, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 400, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #2001 = XVLDX { 2000, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 397, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #2000 = XVLDREPL_W { 1999, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 397, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #1999 = XVLDREPL_H { 1998, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 397, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #1998 = XVLDREPL_D { 1997, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 397, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #1997 = XVLDREPL_B { 1996, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 214, 0, 0x0ULL }, // Inst #1996 = XVLDI { 1995, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 397, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #1995 = XVLD { 1994, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #1994 = XVINSVE0_W { 1993, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #1993 = XVINSVE0_D { 1992, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 210, 0, 0x0ULL }, // Inst #1992 = XVINSGR2VR_W { 1991, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 210, 0, 0x0ULL }, // Inst #1991 = XVINSGR2VR_D { 1990, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1990 = XVILVL_W { 1989, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1989 = XVILVL_H { 1988, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1988 = XVILVL_D { 1987, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1987 = XVILVL_B { 1986, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1986 = XVILVH_W { 1985, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1985 = XVILVH_H { 1984, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1984 = XVILVH_D { 1983, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1983 = XVILVH_B { 1982, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1982 = XVHSUBW_W_H { 1981, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1981 = XVHSUBW_WU_HU { 1980, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1980 = XVHSUBW_Q_D { 1979, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1979 = XVHSUBW_QU_DU { 1978, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1978 = XVHSUBW_H_B { 1977, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1977 = XVHSUBW_HU_BU { 1976, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1976 = XVHSUBW_D_W { 1975, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1975 = XVHSUBW_DU_WU { 1974, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #1974 = XVHSELI_D { 1973, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1973 = XVHADDW_W_H { 1972, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1972 = XVHADDW_WU_HU { 1971, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1971 = XVHADDW_Q_D { 1970, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1970 = XVHADDW_QU_DU { 1969, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1969 = XVHADDW_H_B { 1968, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1968 = XVHADDW_HU_BU { 1967, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1967 = XVHADDW_D_W { 1966, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1966 = XVHADDW_DU_WU { 1965, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1965 = XVFTINT_W_S { 1964, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1964 = XVFTINT_W_D { 1963, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1963 = XVFTINT_WU_S { 1962, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1962 = XVFTINT_L_D { 1961, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1961 = XVFTINT_LU_D { 1960, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1960 = XVFTINTRZ_W_S { 1959, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1959 = XVFTINTRZ_W_D { 1958, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1958 = XVFTINTRZ_WU_S { 1957, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1957 = XVFTINTRZ_L_D { 1956, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1956 = XVFTINTRZ_LU_D { 1955, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1955 = XVFTINTRZL_L_S { 1954, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1954 = XVFTINTRZH_L_S { 1953, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1953 = XVFTINTRP_W_S { 1952, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1952 = XVFTINTRP_W_D { 1951, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1951 = XVFTINTRP_L_D { 1950, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1950 = XVFTINTRPL_L_S { 1949, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1949 = XVFTINTRPH_L_S { 1948, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1948 = XVFTINTRNE_W_S { 1947, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1947 = XVFTINTRNE_W_D { 1946, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1946 = XVFTINTRNE_L_D { 1945, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1945 = XVFTINTRNEL_L_S { 1944, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1944 = XVFTINTRNEH_L_S { 1943, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1943 = XVFTINTRM_W_S { 1942, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1942 = XVFTINTRM_W_D { 1941, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1941 = XVFTINTRM_L_D { 1940, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1940 = XVFTINTRML_L_S { 1939, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1939 = XVFTINTRMH_L_S { 1938, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1938 = XVFTINTL_L_S { 1937, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1937 = XVFTINTH_L_S { 1936, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1936 = XVFSUB_S { 1935, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1935 = XVFSUB_D { 1934, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1934 = XVFSQRT_S { 1933, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1933 = XVFSQRT_D { 1932, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 393, 0, 0x0ULL }, // Inst #1932 = XVFRSTP_H { 1931, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 393, 0, 0x0ULL }, // Inst #1931 = XVFRSTP_B { 1930, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #1930 = XVFRSTPI_H { 1929, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #1929 = XVFRSTPI_B { 1928, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1928 = XVFRSQRT_S { 1927, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1927 = XVFRSQRT_D { 1926, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1926 = XVFRSQRTE_S { 1925, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1925 = XVFRSQRTE_D { 1924, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1924 = XVFRINT_S { 1923, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1923 = XVFRINT_D { 1922, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1922 = XVFRINTRZ_S { 1921, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1921 = XVFRINTRZ_D { 1920, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1920 = XVFRINTRP_S { 1919, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1919 = XVFRINTRP_D { 1918, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1918 = XVFRINTRNE_S { 1917, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1917 = XVFRINTRNE_D { 1916, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1916 = XVFRINTRM_S { 1915, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1915 = XVFRINTRM_D { 1914, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1914 = XVFRECIP_S { 1913, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1913 = XVFRECIP_D { 1912, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1912 = XVFRECIPE_S { 1911, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1911 = XVFRECIPE_D { 1910, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 389, 0, 0x0ULL }, // Inst #1910 = XVFNMSUB_S { 1909, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 389, 0, 0x0ULL }, // Inst #1909 = XVFNMSUB_D { 1908, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 389, 0, 0x0ULL }, // Inst #1908 = XVFNMADD_S { 1907, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 389, 0, 0x0ULL }, // Inst #1907 = XVFNMADD_D { 1906, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1906 = XVFMUL_S { 1905, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1905 = XVFMUL_D { 1904, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 389, 0, 0x0ULL }, // Inst #1904 = XVFMSUB_S { 1903, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 389, 0, 0x0ULL }, // Inst #1903 = XVFMSUB_D { 1902, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1902 = XVFMIN_S { 1901, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1901 = XVFMIN_D { 1900, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1900 = XVFMINA_S { 1899, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1899 = XVFMINA_D { 1898, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1898 = XVFMAX_S { 1897, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1897 = XVFMAX_D { 1896, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1896 = XVFMAXA_S { 1895, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1895 = XVFMAXA_D { 1894, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 389, 0, 0x0ULL }, // Inst #1894 = XVFMADD_S { 1893, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 389, 0, 0x0ULL }, // Inst #1893 = XVFMADD_D { 1892, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1892 = XVFLOGB_S { 1891, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1891 = XVFLOGB_D { 1890, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1890 = XVFFINT_S_WU { 1889, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1889 = XVFFINT_S_W { 1888, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1888 = XVFFINT_S_L { 1887, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1887 = XVFFINT_D_LU { 1886, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1886 = XVFFINT_D_L { 1885, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1885 = XVFFINTL_D_W { 1884, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1884 = XVFFINTH_D_W { 1883, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1883 = XVFDIV_S { 1882, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1882 = XVFDIV_D { 1881, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1881 = XVFCVT_S_D { 1880, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1880 = XVFCVT_H_S { 1879, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1879 = XVFCVTL_S_H { 1878, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1878 = XVFCVTL_D_S { 1877, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1877 = XVFCVTH_S_H { 1876, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1876 = XVFCVTH_D_S { 1875, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1875 = XVFCMP_SUN_S { 1874, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1874 = XVFCMP_SUN_D { 1873, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1873 = XVFCMP_SUNE_S { 1872, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1872 = XVFCMP_SUNE_D { 1871, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1871 = XVFCMP_SULT_S { 1870, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1870 = XVFCMP_SULT_D { 1869, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1869 = XVFCMP_SULE_S { 1868, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1868 = XVFCMP_SULE_D { 1867, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1867 = XVFCMP_SUEQ_S { 1866, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1866 = XVFCMP_SUEQ_D { 1865, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1865 = XVFCMP_SOR_S { 1864, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1864 = XVFCMP_SOR_D { 1863, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1863 = XVFCMP_SNE_S { 1862, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1862 = XVFCMP_SNE_D { 1861, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1861 = XVFCMP_SLT_S { 1860, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1860 = XVFCMP_SLT_D { 1859, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1859 = XVFCMP_SLE_S { 1858, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1858 = XVFCMP_SLE_D { 1857, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1857 = XVFCMP_SEQ_S { 1856, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1856 = XVFCMP_SEQ_D { 1855, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1855 = XVFCMP_SAF_S { 1854, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1854 = XVFCMP_SAF_D { 1853, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1853 = XVFCMP_CUN_S { 1852, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1852 = XVFCMP_CUN_D { 1851, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1851 = XVFCMP_CUNE_S { 1850, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1850 = XVFCMP_CUNE_D { 1849, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1849 = XVFCMP_CULT_S { 1848, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1848 = XVFCMP_CULT_D { 1847, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1847 = XVFCMP_CULE_S { 1846, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1846 = XVFCMP_CULE_D { 1845, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1845 = XVFCMP_CUEQ_S { 1844, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1844 = XVFCMP_CUEQ_D { 1843, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1843 = XVFCMP_COR_S { 1842, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1842 = XVFCMP_COR_D { 1841, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1841 = XVFCMP_CNE_S { 1840, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1840 = XVFCMP_CNE_D { 1839, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1839 = XVFCMP_CLT_S { 1838, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1838 = XVFCMP_CLT_D { 1837, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1837 = XVFCMP_CLE_S { 1836, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1836 = XVFCMP_CLE_D { 1835, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1835 = XVFCMP_CEQ_S { 1834, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1834 = XVFCMP_CEQ_D { 1833, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1833 = XVFCMP_CAF_S { 1832, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1832 = XVFCMP_CAF_D { 1831, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1831 = XVFCLASS_S { 1830, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1830 = XVFCLASS_D { 1829, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1829 = XVFADD_S { 1828, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1828 = XVFADD_D { 1827, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #1827 = XVEXTRINS_W { 1826, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #1826 = XVEXTRINS_H { 1825, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #1825 = XVEXTRINS_D { 1824, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #1824 = XVEXTRINS_B { 1823, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1823 = XVEXTL_Q_D { 1822, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1822 = XVEXTL_QU_DU { 1821, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1821 = XVEXTH_W_H { 1820, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1820 = XVEXTH_WU_HU { 1819, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1819 = XVEXTH_Q_D { 1818, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1818 = XVEXTH_QU_DU { 1817, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1817 = XVEXTH_H_B { 1816, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1816 = XVEXTH_HU_BU { 1815, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1815 = XVEXTH_D_W { 1814, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1814 = XVEXTH_DU_WU { 1813, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1813 = XVDIV_WU { 1812, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1812 = XVDIV_W { 1811, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1811 = XVDIV_HU { 1810, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1810 = XVDIV_H { 1809, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1809 = XVDIV_DU { 1808, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1808 = XVDIV_D { 1807, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1807 = XVDIV_BU { 1806, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1806 = XVDIV_B { 1805, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1805 = XVCLZ_W { 1804, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1804 = XVCLZ_H { 1803, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1803 = XVCLZ_D { 1802, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1802 = XVCLZ_B { 1801, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1801 = XVCLO_W { 1800, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1800 = XVCLO_H { 1799, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1799 = XVCLO_D { 1798, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1798 = XVCLO_B { 1797, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #1797 = XVBSRL_V { 1796, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #1796 = XVBSLL_V { 1795, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1795 = XVBITSET_W { 1794, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1794 = XVBITSET_H { 1793, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1793 = XVBITSET_D { 1792, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1792 = XVBITSET_B { 1791, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #1791 = XVBITSETI_W { 1790, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #1790 = XVBITSETI_H { 1789, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #1789 = XVBITSETI_D { 1788, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #1788 = XVBITSETI_B { 1787, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 389, 0, 0x0ULL }, // Inst #1787 = XVBITSEL_V { 1786, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #1786 = XVBITSELI_B { 1785, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1785 = XVBITREV_W { 1784, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1784 = XVBITREV_H { 1783, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1783 = XVBITREV_D { 1782, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1782 = XVBITREV_B { 1781, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #1781 = XVBITREVI_W { 1780, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #1780 = XVBITREVI_H { 1779, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #1779 = XVBITREVI_D { 1778, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #1778 = XVBITREVI_B { 1777, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1777 = XVBITCLR_W { 1776, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1776 = XVBITCLR_H { 1775, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1775 = XVBITCLR_D { 1774, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1774 = XVBITCLR_B { 1773, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #1773 = XVBITCLRI_W { 1772, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #1772 = XVBITCLRI_H { 1771, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #1771 = XVBITCLRI_D { 1770, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #1770 = XVBITCLRI_B { 1769, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1769 = XVAVG_WU { 1768, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1768 = XVAVG_W { 1767, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1767 = XVAVG_HU { 1766, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1766 = XVAVG_H { 1765, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1765 = XVAVG_DU { 1764, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1764 = XVAVG_D { 1763, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1763 = XVAVG_BU { 1762, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1762 = XVAVG_B { 1761, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1761 = XVAVGR_WU { 1760, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1760 = XVAVGR_W { 1759, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1759 = XVAVGR_HU { 1758, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1758 = XVAVGR_H { 1757, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1757 = XVAVGR_DU { 1756, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1756 = XVAVGR_D { 1755, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1755 = XVAVGR_BU { 1754, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1754 = XVAVGR_B { 1753, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1753 = XVAND_V { 1752, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1752 = XVANDN_V { 1751, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #1751 = XVANDI_B { 1750, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1750 = XVADD_W { 1749, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1749 = XVADD_Q { 1748, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1748 = XVADD_H { 1747, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1747 = XVADD_D { 1746, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1746 = XVADD_B { 1745, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1745 = XVADDWOD_W_HU_H { 1744, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1744 = XVADDWOD_W_HU { 1743, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1743 = XVADDWOD_W_H { 1742, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1742 = XVADDWOD_Q_DU_D { 1741, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1741 = XVADDWOD_Q_DU { 1740, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1740 = XVADDWOD_Q_D { 1739, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1739 = XVADDWOD_H_BU_B { 1738, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1738 = XVADDWOD_H_BU { 1737, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1737 = XVADDWOD_H_B { 1736, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1736 = XVADDWOD_D_WU_W { 1735, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1735 = XVADDWOD_D_WU { 1734, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1734 = XVADDWOD_D_W { 1733, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1733 = XVADDWEV_W_HU_H { 1732, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1732 = XVADDWEV_W_HU { 1731, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1731 = XVADDWEV_W_H { 1730, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1730 = XVADDWEV_Q_DU_D { 1729, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1729 = XVADDWEV_Q_DU { 1728, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1728 = XVADDWEV_Q_D { 1727, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1727 = XVADDWEV_H_BU_B { 1726, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1726 = XVADDWEV_H_BU { 1725, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1725 = XVADDWEV_H_B { 1724, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1724 = XVADDWEV_D_WU_W { 1723, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1723 = XVADDWEV_D_WU { 1722, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1722 = XVADDWEV_D_W { 1721, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #1721 = XVADDI_WU { 1720, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #1720 = XVADDI_HU { 1719, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #1719 = XVADDI_DU { 1718, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #1718 = XVADDI_BU { 1717, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1717 = XVADDA_W { 1716, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1716 = XVADDA_H { 1715, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1715 = XVADDA_D { 1714, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1714 = XVADDA_B { 1713, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1713 = XVABSD_WU { 1712, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1712 = XVABSD_W { 1711, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1711 = XVABSD_HU { 1710, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1710 = XVABSD_H { 1709, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1709 = XVABSD_DU { 1708, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1708 = XVABSD_D { 1707, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1707 = XVABSD_BU { 1706, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1706 = XVABSD_B { 1705, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 175, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // Inst #1705 = XORI { 1704, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0, 0x0ULL }, // Inst #1704 = XOR { 1703, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #1703 = X86XOR_W { 1702, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #1702 = X86XOR_H { 1701, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #1701 = X86XOR_D { 1700, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #1700 = X86XOR_B { 1699, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #1699 = X86SUB_WU { 1698, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #1698 = X86SUB_W { 1697, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #1697 = X86SUB_H { 1696, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #1696 = X86SUB_DU { 1695, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #1695 = X86SUB_D { 1694, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #1694 = X86SUB_B { 1693, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #1693 = X86SRL_W { 1692, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #1692 = X86SRL_H { 1691, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #1691 = X86SRL_D { 1690, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #1690 = X86SRL_B { 1689, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0, 0x0ULL }, // Inst #1689 = X86SRLI_W { 1688, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0, 0x0ULL }, // Inst #1688 = X86SRLI_H { 1687, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0, 0x0ULL }, // Inst #1687 = X86SRLI_D { 1686, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0, 0x0ULL }, // Inst #1686 = X86SRLI_B { 1685, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #1685 = X86SRA_W { 1684, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #1684 = X86SRA_H { 1683, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #1683 = X86SRA_D { 1682, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #1682 = X86SRA_B { 1681, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0, 0x0ULL }, // Inst #1681 = X86SRAI_W { 1680, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0, 0x0ULL }, // Inst #1680 = X86SRAI_H { 1679, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0, 0x0ULL }, // Inst #1679 = X86SRAI_D { 1678, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0, 0x0ULL }, // Inst #1678 = X86SRAI_B { 1677, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #1677 = X86SLL_W { 1676, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #1676 = X86SLL_H { 1675, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #1675 = X86SLL_D { 1674, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #1674 = X86SLL_B { 1673, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0, 0x0ULL }, // Inst #1673 = X86SLLI_W { 1672, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0, 0x0ULL }, // Inst #1672 = X86SLLI_H { 1671, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0, 0x0ULL }, // Inst #1671 = X86SLLI_D { 1670, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0, 0x0ULL }, // Inst #1670 = X86SLLI_B { 1669, 0, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 1, 0, 0x0ULL }, // Inst #1669 = X86SETTM { 1668, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 221, 0, 0x0ULL }, // Inst #1668 = X86SETTAG { 1667, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #1667 = X86SBC_W { 1666, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #1666 = X86SBC_H { 1665, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #1665 = X86SBC_D { 1664, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #1664 = X86SBC_B { 1663, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #1663 = X86ROTR_W { 1662, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #1662 = X86ROTR_H { 1661, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #1661 = X86ROTR_D { 1660, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #1660 = X86ROTR_B { 1659, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0, 0x0ULL }, // Inst #1659 = X86ROTRI_W { 1658, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0, 0x0ULL }, // Inst #1658 = X86ROTRI_H { 1657, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0, 0x0ULL }, // Inst #1657 = X86ROTRI_D { 1656, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0, 0x0ULL }, // Inst #1656 = X86ROTRI_B { 1655, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #1655 = X86ROTL_W { 1654, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #1654 = X86ROTL_H { 1653, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #1653 = X86ROTL_D { 1652, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #1652 = X86ROTL_B { 1651, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0, 0x0ULL }, // Inst #1651 = X86ROTLI_W { 1650, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0, 0x0ULL }, // Inst #1650 = X86ROTLI_H { 1649, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0, 0x0ULL }, // Inst #1649 = X86ROTLI_D { 1648, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0, 0x0ULL }, // Inst #1648 = X86ROTLI_B { 1647, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #1647 = X86RCR_W { 1646, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #1646 = X86RCR_H { 1645, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #1645 = X86RCR_D { 1644, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #1644 = X86RCR_B { 1643, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0, 0x0ULL }, // Inst #1643 = X86RCRI_W { 1642, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0, 0x0ULL }, // Inst #1642 = X86RCRI_H { 1641, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0, 0x0ULL }, // Inst #1641 = X86RCRI_D { 1640, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0, 0x0ULL }, // Inst #1640 = X86RCRI_B { 1639, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #1639 = X86RCL_W { 1638, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #1638 = X86RCL_H { 1637, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #1637 = X86RCL_D { 1636, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #1636 = X86RCL_B { 1635, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0, 0x0ULL }, // Inst #1635 = X86RCLI_W { 1634, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0, 0x0ULL }, // Inst #1634 = X86RCLI_H { 1633, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0, 0x0ULL }, // Inst #1633 = X86RCLI_D { 1632, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0, 0x0ULL }, // Inst #1632 = X86RCLI_B { 1631, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #1631 = X86OR_W { 1630, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #1630 = X86OR_H { 1629, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #1629 = X86OR_D { 1628, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #1628 = X86OR_B { 1627, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #1627 = X86MUL_WU { 1626, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #1626 = X86MUL_W { 1625, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #1625 = X86MUL_HU { 1624, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #1624 = X86MUL_H { 1623, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #1623 = X86MUL_DU { 1622, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #1622 = X86MUL_D { 1621, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #1621 = X86MUL_BU { 1620, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #1620 = X86MUL_B { 1619, 1, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 0, 0, 0x0ULL }, // Inst #1619 = X86MTTOP { 1618, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0, 0x0ULL }, // Inst #1618 = X86MTFLAG { 1617, 1, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 166, 0, 0x0ULL }, // Inst #1617 = X86MFTOP { 1616, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0, 0x0ULL }, // Inst #1616 = X86MFFLAG { 1615, 1, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 166, 0, 0x0ULL }, // Inst #1615 = X86INC_W { 1614, 1, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 166, 0, 0x0ULL }, // Inst #1614 = X86INC_H { 1613, 1, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 166, 0, 0x0ULL }, // Inst #1613 = X86INC_D { 1612, 1, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 166, 0, 0x0ULL }, // Inst #1612 = X86INC_B { 1611, 0, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 1, 0, 0x0ULL }, // Inst #1611 = X86INCTOP { 1610, 1, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 166, 0, 0x0ULL }, // Inst #1610 = X86DEC_W { 1609, 1, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 166, 0, 0x0ULL }, // Inst #1609 = X86DEC_H { 1608, 1, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 166, 0, 0x0ULL }, // Inst #1608 = X86DEC_D { 1607, 1, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 166, 0, 0x0ULL }, // Inst #1607 = X86DEC_B { 1606, 0, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 1, 0, 0x0ULL }, // Inst #1606 = X86DECTOP { 1605, 0, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 1, 0, 0x0ULL }, // Inst #1605 = X86CLRTM { 1604, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #1604 = X86AND_W { 1603, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #1603 = X86AND_H { 1602, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #1602 = X86AND_D { 1601, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #1601 = X86AND_B { 1600, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #1600 = X86ADD_WU { 1599, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #1599 = X86ADD_W { 1598, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #1598 = X86ADD_H { 1597, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #1597 = X86ADD_DU { 1596, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #1596 = X86ADD_D { 1595, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #1595 = X86ADD_B { 1594, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #1594 = X86ADC_W { 1593, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #1593 = X86ADC_H { 1592, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #1592 = X86ADC_D { 1591, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #1591 = X86ADC_B { 1590, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1590 = VXOR_V { 1589, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1589 = VXORI_B { 1588, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1588 = VSUB_W { 1587, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1587 = VSUB_Q { 1586, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1586 = VSUB_H { 1585, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1585 = VSUB_D { 1584, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1584 = VSUB_B { 1583, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1583 = VSUBWOD_W_HU { 1582, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1582 = VSUBWOD_W_H { 1581, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1581 = VSUBWOD_Q_DU { 1580, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1580 = VSUBWOD_Q_D { 1579, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1579 = VSUBWOD_H_BU { 1578, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1578 = VSUBWOD_H_B { 1577, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1577 = VSUBWOD_D_WU { 1576, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1576 = VSUBWOD_D_W { 1575, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1575 = VSUBWEV_W_HU { 1574, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1574 = VSUBWEV_W_H { 1573, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1573 = VSUBWEV_Q_DU { 1572, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1572 = VSUBWEV_Q_D { 1571, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1571 = VSUBWEV_H_BU { 1570, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1570 = VSUBWEV_H_B { 1569, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1569 = VSUBWEV_D_WU { 1568, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1568 = VSUBWEV_D_W { 1567, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1567 = VSUBI_WU { 1566, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1566 = VSUBI_HU { 1565, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1565 = VSUBI_DU { 1564, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1564 = VSUBI_BU { 1563, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 362, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #1563 = VSTX { 1562, 4, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 375, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #1562 = VSTELM_W { 1561, 4, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 375, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #1561 = VSTELM_H { 1560, 4, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 375, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #1560 = VSTELM_D { 1559, 4, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 375, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #1559 = VSTELM_B { 1558, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 359, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #1558 = VST { 1557, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1557 = VSSUB_WU { 1556, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1556 = VSSUB_W { 1555, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1555 = VSSUB_HU { 1554, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1554 = VSSUB_H { 1553, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1553 = VSSUB_DU { 1552, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1552 = VSSUB_D { 1551, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1551 = VSSUB_BU { 1550, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1550 = VSSUB_B { 1549, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1549 = VSSRLRN_W_D { 1548, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1548 = VSSRLRN_WU_D { 1547, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1547 = VSSRLRN_H_W { 1546, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1546 = VSSRLRN_HU_W { 1545, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1545 = VSSRLRN_B_H { 1544, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1544 = VSSRLRN_BU_H { 1543, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #1543 = VSSRLRNI_W_D { 1542, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #1542 = VSSRLRNI_WU_D { 1541, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #1541 = VSSRLRNI_H_W { 1540, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #1540 = VSSRLRNI_HU_W { 1539, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #1539 = VSSRLRNI_D_Q { 1538, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #1538 = VSSRLRNI_DU_Q { 1537, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #1537 = VSSRLRNI_B_H { 1536, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #1536 = VSSRLRNI_BU_H { 1535, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1535 = VSSRLN_W_D { 1534, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1534 = VSSRLN_WU_D { 1533, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1533 = VSSRLN_H_W { 1532, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1532 = VSSRLN_HU_W { 1531, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1531 = VSSRLN_B_H { 1530, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1530 = VSSRLN_BU_H { 1529, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #1529 = VSSRLNI_W_D { 1528, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #1528 = VSSRLNI_WU_D { 1527, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #1527 = VSSRLNI_H_W { 1526, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #1526 = VSSRLNI_HU_W { 1525, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #1525 = VSSRLNI_D_Q { 1524, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #1524 = VSSRLNI_DU_Q { 1523, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #1523 = VSSRLNI_B_H { 1522, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #1522 = VSSRLNI_BU_H { 1521, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1521 = VSSRARN_W_D { 1520, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1520 = VSSRARN_WU_D { 1519, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1519 = VSSRARN_H_W { 1518, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1518 = VSSRARN_HU_W { 1517, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1517 = VSSRARN_B_H { 1516, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1516 = VSSRARN_BU_H { 1515, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #1515 = VSSRARNI_W_D { 1514, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #1514 = VSSRARNI_WU_D { 1513, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #1513 = VSSRARNI_H_W { 1512, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #1512 = VSSRARNI_HU_W { 1511, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #1511 = VSSRARNI_D_Q { 1510, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #1510 = VSSRARNI_DU_Q { 1509, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #1509 = VSSRARNI_B_H { 1508, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #1508 = VSSRARNI_BU_H { 1507, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1507 = VSSRAN_W_D { 1506, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1506 = VSSRAN_WU_D { 1505, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1505 = VSSRAN_H_W { 1504, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1504 = VSSRAN_HU_W { 1503, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1503 = VSSRAN_B_H { 1502, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1502 = VSSRAN_BU_H { 1501, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #1501 = VSSRANI_W_D { 1500, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #1500 = VSSRANI_WU_D { 1499, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #1499 = VSSRANI_H_W { 1498, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #1498 = VSSRANI_HU_W { 1497, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #1497 = VSSRANI_D_Q { 1496, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #1496 = VSSRANI_DU_Q { 1495, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #1495 = VSSRANI_B_H { 1494, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #1494 = VSSRANI_BU_H { 1493, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1493 = VSRL_W { 1492, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1492 = VSRL_H { 1491, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1491 = VSRL_D { 1490, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1490 = VSRL_B { 1489, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1489 = VSRLR_W { 1488, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1488 = VSRLR_H { 1487, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1487 = VSRLR_D { 1486, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1486 = VSRLR_B { 1485, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1485 = VSRLRN_W_D { 1484, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1484 = VSRLRN_H_W { 1483, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1483 = VSRLRN_B_H { 1482, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #1482 = VSRLRNI_W_D { 1481, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #1481 = VSRLRNI_H_W { 1480, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #1480 = VSRLRNI_D_Q { 1479, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #1479 = VSRLRNI_B_H { 1478, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1478 = VSRLRI_W { 1477, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1477 = VSRLRI_H { 1476, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1476 = VSRLRI_D { 1475, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1475 = VSRLRI_B { 1474, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1474 = VSRLN_W_D { 1473, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1473 = VSRLN_H_W { 1472, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1472 = VSRLN_B_H { 1471, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #1471 = VSRLNI_W_D { 1470, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #1470 = VSRLNI_H_W { 1469, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #1469 = VSRLNI_D_Q { 1468, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #1468 = VSRLNI_B_H { 1467, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1467 = VSRLI_W { 1466, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1466 = VSRLI_H { 1465, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1465 = VSRLI_D { 1464, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1464 = VSRLI_B { 1463, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1463 = VSRA_W { 1462, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1462 = VSRA_H { 1461, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1461 = VSRA_D { 1460, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1460 = VSRA_B { 1459, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1459 = VSRAR_W { 1458, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1458 = VSRAR_H { 1457, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1457 = VSRAR_D { 1456, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1456 = VSRAR_B { 1455, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1455 = VSRARN_W_D { 1454, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1454 = VSRARN_H_W { 1453, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1453 = VSRARN_B_H { 1452, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #1452 = VSRARNI_W_D { 1451, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #1451 = VSRARNI_H_W { 1450, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #1450 = VSRARNI_D_Q { 1449, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #1449 = VSRARNI_B_H { 1448, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1448 = VSRARI_W { 1447, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1447 = VSRARI_H { 1446, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1446 = VSRARI_D { 1445, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1445 = VSRARI_B { 1444, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1444 = VSRAN_W_D { 1443, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1443 = VSRAN_H_W { 1442, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1442 = VSRAN_B_H { 1441, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #1441 = VSRANI_W_D { 1440, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #1440 = VSRANI_H_W { 1439, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #1439 = VSRANI_D_Q { 1438, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #1438 = VSRANI_B_H { 1437, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1437 = VSRAI_W { 1436, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1436 = VSRAI_H { 1435, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1435 = VSRAI_D { 1434, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1434 = VSRAI_B { 1433, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1433 = VSLT_WU { 1432, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1432 = VSLT_W { 1431, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1431 = VSLT_HU { 1430, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1430 = VSLT_H { 1429, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1429 = VSLT_DU { 1428, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1428 = VSLT_D { 1427, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1427 = VSLT_BU { 1426, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1426 = VSLT_B { 1425, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1425 = VSLTI_WU { 1424, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1424 = VSLTI_W { 1423, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1423 = VSLTI_HU { 1422, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1422 = VSLTI_H { 1421, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1421 = VSLTI_DU { 1420, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1420 = VSLTI_D { 1419, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1419 = VSLTI_BU { 1418, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1418 = VSLTI_B { 1417, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1417 = VSLL_W { 1416, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1416 = VSLL_H { 1415, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1415 = VSLL_D { 1414, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1414 = VSLL_B { 1413, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1413 = VSLLWIL_W_H { 1412, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1412 = VSLLWIL_WU_HU { 1411, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1411 = VSLLWIL_H_B { 1410, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1410 = VSLLWIL_HU_BU { 1409, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1409 = VSLLWIL_D_W { 1408, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1408 = VSLLWIL_DU_WU { 1407, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1407 = VSLLI_W { 1406, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1406 = VSLLI_H { 1405, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1405 = VSLLI_D { 1404, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1404 = VSLLI_B { 1403, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1403 = VSLE_WU { 1402, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1402 = VSLE_W { 1401, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1401 = VSLE_HU { 1400, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1400 = VSLE_H { 1399, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1399 = VSLE_DU { 1398, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1398 = VSLE_D { 1397, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1397 = VSLE_BU { 1396, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1396 = VSLE_B { 1395, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1395 = VSLEI_WU { 1394, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1394 = VSLEI_W { 1393, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1393 = VSLEI_HU { 1392, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1392 = VSLEI_H { 1391, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1391 = VSLEI_DU { 1390, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1390 = VSLEI_D { 1389, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1389 = VSLEI_BU { 1388, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1388 = VSLEI_B { 1387, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1387 = VSIGNCOV_W { 1386, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1386 = VSIGNCOV_H { 1385, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1385 = VSIGNCOV_D { 1384, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1384 = VSIGNCOV_B { 1383, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 351, 0, 0x0ULL }, // Inst #1383 = VSHUF_W { 1382, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 351, 0, 0x0ULL }, // Inst #1382 = VSHUF_H { 1381, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 351, 0, 0x0ULL }, // Inst #1381 = VSHUF_D { 1380, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 343, 0, 0x0ULL }, // Inst #1380 = VSHUF_B { 1379, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1379 = VSHUF4I_W { 1378, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1378 = VSHUF4I_H { 1377, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #1377 = VSHUF4I_D { 1376, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1376 = VSHUF4I_B { 1375, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 373, 0, 0x0ULL }, // Inst #1375 = VSETNEZ_V { 1374, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 373, 0, 0x0ULL }, // Inst #1374 = VSETEQZ_V { 1373, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 373, 0, 0x0ULL }, // Inst #1373 = VSETANYEQZ_W { 1372, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 373, 0, 0x0ULL }, // Inst #1372 = VSETANYEQZ_H { 1371, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 373, 0, 0x0ULL }, // Inst #1371 = VSETANYEQZ_D { 1370, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 373, 0, 0x0ULL }, // Inst #1370 = VSETANYEQZ_B { 1369, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 373, 0, 0x0ULL }, // Inst #1369 = VSETALLNEZ_W { 1368, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 373, 0, 0x0ULL }, // Inst #1368 = VSETALLNEZ_H { 1367, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 373, 0, 0x0ULL }, // Inst #1367 = VSETALLNEZ_D { 1366, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 373, 0, 0x0ULL }, // Inst #1366 = VSETALLNEZ_B { 1365, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1365 = VSEQ_W { 1364, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1364 = VSEQ_H { 1363, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1363 = VSEQ_D { 1362, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1362 = VSEQ_B { 1361, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1361 = VSEQI_W { 1360, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1360 = VSEQI_H { 1359, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1359 = VSEQI_D { 1358, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1358 = VSEQI_B { 1357, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1357 = VSAT_WU { 1356, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1356 = VSAT_W { 1355, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1355 = VSAT_HU { 1354, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1354 = VSAT_H { 1353, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1353 = VSAT_DU { 1352, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1352 = VSAT_D { 1351, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1351 = VSAT_BU { 1350, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1350 = VSAT_B { 1349, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1349 = VSADD_WU { 1348, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1348 = VSADD_W { 1347, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1347 = VSADD_HU { 1346, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1346 = VSADD_H { 1345, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1345 = VSADD_DU { 1344, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1344 = VSADD_D { 1343, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1343 = VSADD_BU { 1342, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1342 = VSADD_B { 1341, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1341 = VROTR_W { 1340, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1340 = VROTR_H { 1339, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1339 = VROTR_D { 1338, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1338 = VROTR_B { 1337, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1337 = VROTRI_W { 1336, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1336 = VROTRI_H { 1335, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1335 = VROTRI_D { 1334, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1334 = VROTRI_B { 1333, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 370, 0, 0x0ULL }, // Inst #1333 = VREPLVE_W { 1332, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 370, 0, 0x0ULL }, // Inst #1332 = VREPLVE_H { 1331, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 370, 0, 0x0ULL }, // Inst #1331 = VREPLVE_D { 1330, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 370, 0, 0x0ULL }, // Inst #1330 = VREPLVE_B { 1329, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1329 = VREPLVEI_W { 1328, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1328 = VREPLVEI_H { 1327, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1327 = VREPLVEI_D { 1326, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1326 = VREPLVEI_B { 1325, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 368, 0, 0x0ULL }, // Inst #1325 = VREPLGR2VR_W { 1324, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 368, 0, 0x0ULL }, // Inst #1324 = VREPLGR2VR_H { 1323, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 368, 0, 0x0ULL }, // Inst #1323 = VREPLGR2VR_D { 1322, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 368, 0, 0x0ULL }, // Inst #1322 = VREPLGR2VR_B { 1321, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 365, 0, 0x0ULL }, // Inst #1321 = VPICKVE2GR_WU { 1320, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 365, 0, 0x0ULL }, // Inst #1320 = VPICKVE2GR_W { 1319, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 365, 0, 0x0ULL }, // Inst #1319 = VPICKVE2GR_HU { 1318, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 365, 0, 0x0ULL }, // Inst #1318 = VPICKVE2GR_H { 1317, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 365, 0, 0x0ULL }, // Inst #1317 = VPICKVE2GR_DU { 1316, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 365, 0, 0x0ULL }, // Inst #1316 = VPICKVE2GR_D { 1315, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 365, 0, 0x0ULL }, // Inst #1315 = VPICKVE2GR_BU { 1314, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 365, 0, 0x0ULL }, // Inst #1314 = VPICKVE2GR_B { 1313, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1313 = VPICKOD_W { 1312, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1312 = VPICKOD_H { 1311, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1311 = VPICKOD_D { 1310, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1310 = VPICKOD_B { 1309, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1309 = VPICKEV_W { 1308, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1308 = VPICKEV_H { 1307, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1307 = VPICKEV_D { 1306, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1306 = VPICKEV_B { 1305, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #1305 = VPERMI_W { 1304, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1304 = VPCNT_W { 1303, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1303 = VPCNT_H { 1302, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1302 = VPCNT_D { 1301, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1301 = VPCNT_B { 1300, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1300 = VPACKOD_W { 1299, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1299 = VPACKOD_H { 1298, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1298 = VPACKOD_D { 1297, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1297 = VPACKOD_B { 1296, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1296 = VPACKEV_W { 1295, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1295 = VPACKEV_H { 1294, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1294 = VPACKEV_D { 1293, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1293 = VPACKEV_B { 1292, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1292 = VOR_V { 1291, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1291 = VORN_V { 1290, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1290 = VORI_B { 1289, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1289 = VNOR_V { 1288, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1288 = VNORI_B { 1287, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1287 = VNEG_W { 1286, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1286 = VNEG_H { 1285, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1285 = VNEG_D { 1284, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1284 = VNEG_B { 1283, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1283 = VMUL_W { 1282, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1282 = VMUL_H { 1281, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1281 = VMUL_D { 1280, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1280 = VMUL_B { 1279, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1279 = VMULWOD_W_HU_H { 1278, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1278 = VMULWOD_W_HU { 1277, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1277 = VMULWOD_W_H { 1276, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1276 = VMULWOD_Q_DU_D { 1275, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1275 = VMULWOD_Q_DU { 1274, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1274 = VMULWOD_Q_D { 1273, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1273 = VMULWOD_H_BU_B { 1272, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1272 = VMULWOD_H_BU { 1271, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1271 = VMULWOD_H_B { 1270, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1270 = VMULWOD_D_WU_W { 1269, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1269 = VMULWOD_D_WU { 1268, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1268 = VMULWOD_D_W { 1267, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1267 = VMULWEV_W_HU_H { 1266, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1266 = VMULWEV_W_HU { 1265, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1265 = VMULWEV_W_H { 1264, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1264 = VMULWEV_Q_DU_D { 1263, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1263 = VMULWEV_Q_DU { 1262, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1262 = VMULWEV_Q_D { 1261, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1261 = VMULWEV_H_BU_B { 1260, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1260 = VMULWEV_H_BU { 1259, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1259 = VMULWEV_H_B { 1258, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1258 = VMULWEV_D_WU_W { 1257, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1257 = VMULWEV_D_WU { 1256, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1256 = VMULWEV_D_W { 1255, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1255 = VMUH_WU { 1254, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1254 = VMUH_W { 1253, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1253 = VMUH_HU { 1252, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1252 = VMUH_H { 1251, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1251 = VMUH_DU { 1250, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1250 = VMUH_D { 1249, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1249 = VMUH_BU { 1248, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1248 = VMUH_B { 1247, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 351, 0, 0x0ULL }, // Inst #1247 = VMSUB_W { 1246, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 351, 0, 0x0ULL }, // Inst #1246 = VMSUB_H { 1245, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 351, 0, 0x0ULL }, // Inst #1245 = VMSUB_D { 1244, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 351, 0, 0x0ULL }, // Inst #1244 = VMSUB_B { 1243, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1243 = VMSKNZ_B { 1242, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1242 = VMSKLTZ_W { 1241, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1241 = VMSKLTZ_H { 1240, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1240 = VMSKLTZ_D { 1239, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1239 = VMSKLTZ_B { 1238, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1238 = VMSKGEZ_B { 1237, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1237 = VMOD_WU { 1236, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1236 = VMOD_W { 1235, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1235 = VMOD_HU { 1234, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1234 = VMOD_H { 1233, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1233 = VMOD_DU { 1232, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1232 = VMOD_D { 1231, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1231 = VMOD_BU { 1230, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1230 = VMOD_B { 1229, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1229 = VMIN_WU { 1228, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1228 = VMIN_W { 1227, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1227 = VMIN_HU { 1226, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1226 = VMIN_H { 1225, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1225 = VMIN_DU { 1224, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1224 = VMIN_D { 1223, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1223 = VMIN_BU { 1222, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1222 = VMIN_B { 1221, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1221 = VMINI_WU { 1220, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1220 = VMINI_W { 1219, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1219 = VMINI_HU { 1218, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1218 = VMINI_H { 1217, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1217 = VMINI_DU { 1216, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1216 = VMINI_D { 1215, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1215 = VMINI_BU { 1214, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1214 = VMINI_B { 1213, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1213 = VMAX_WU { 1212, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1212 = VMAX_W { 1211, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1211 = VMAX_HU { 1210, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1210 = VMAX_H { 1209, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1209 = VMAX_DU { 1208, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1208 = VMAX_D { 1207, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1207 = VMAX_BU { 1206, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1206 = VMAX_B { 1205, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1205 = VMAXI_WU { 1204, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1204 = VMAXI_W { 1203, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1203 = VMAXI_HU { 1202, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1202 = VMAXI_H { 1201, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1201 = VMAXI_DU { 1200, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1200 = VMAXI_D { 1199, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1199 = VMAXI_BU { 1198, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1198 = VMAXI_B { 1197, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 351, 0, 0x0ULL }, // Inst #1197 = VMADD_W { 1196, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 351, 0, 0x0ULL }, // Inst #1196 = VMADD_H { 1195, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 351, 0, 0x0ULL }, // Inst #1195 = VMADD_D { 1194, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 351, 0, 0x0ULL }, // Inst #1194 = VMADD_B { 1193, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 351, 0, 0x0ULL }, // Inst #1193 = VMADDWOD_W_HU_H { 1192, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 351, 0, 0x0ULL }, // Inst #1192 = VMADDWOD_W_HU { 1191, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 351, 0, 0x0ULL }, // Inst #1191 = VMADDWOD_W_H { 1190, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 351, 0, 0x0ULL }, // Inst #1190 = VMADDWOD_Q_DU_D { 1189, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 351, 0, 0x0ULL }, // Inst #1189 = VMADDWOD_Q_DU { 1188, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 351, 0, 0x0ULL }, // Inst #1188 = VMADDWOD_Q_D { 1187, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 351, 0, 0x0ULL }, // Inst #1187 = VMADDWOD_H_BU_B { 1186, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 351, 0, 0x0ULL }, // Inst #1186 = VMADDWOD_H_BU { 1185, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 351, 0, 0x0ULL }, // Inst #1185 = VMADDWOD_H_B { 1184, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 351, 0, 0x0ULL }, // Inst #1184 = VMADDWOD_D_WU_W { 1183, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 351, 0, 0x0ULL }, // Inst #1183 = VMADDWOD_D_WU { 1182, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 351, 0, 0x0ULL }, // Inst #1182 = VMADDWOD_D_W { 1181, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 351, 0, 0x0ULL }, // Inst #1181 = VMADDWEV_W_HU_H { 1180, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 351, 0, 0x0ULL }, // Inst #1180 = VMADDWEV_W_HU { 1179, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 351, 0, 0x0ULL }, // Inst #1179 = VMADDWEV_W_H { 1178, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 351, 0, 0x0ULL }, // Inst #1178 = VMADDWEV_Q_DU_D { 1177, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 351, 0, 0x0ULL }, // Inst #1177 = VMADDWEV_Q_DU { 1176, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 351, 0, 0x0ULL }, // Inst #1176 = VMADDWEV_Q_D { 1175, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 351, 0, 0x0ULL }, // Inst #1175 = VMADDWEV_H_BU_B { 1174, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 351, 0, 0x0ULL }, // Inst #1174 = VMADDWEV_H_BU { 1173, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 351, 0, 0x0ULL }, // Inst #1173 = VMADDWEV_H_B { 1172, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 351, 0, 0x0ULL }, // Inst #1172 = VMADDWEV_D_WU_W { 1171, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 351, 0, 0x0ULL }, // Inst #1171 = VMADDWEV_D_WU { 1170, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 351, 0, 0x0ULL }, // Inst #1170 = VMADDWEV_D_W { 1169, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 362, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #1169 = VLDX { 1168, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 359, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #1168 = VLDREPL_W { 1167, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 359, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #1167 = VLDREPL_H { 1166, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 359, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #1166 = VLDREPL_D { 1165, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 359, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #1165 = VLDREPL_B { 1164, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 206, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // Inst #1164 = VLDI { 1163, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 359, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #1163 = VLD { 1162, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 355, 0, 0x0ULL }, // Inst #1162 = VINSGR2VR_W { 1161, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 355, 0, 0x0ULL }, // Inst #1161 = VINSGR2VR_H { 1160, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 355, 0, 0x0ULL }, // Inst #1160 = VINSGR2VR_D { 1159, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 355, 0, 0x0ULL }, // Inst #1159 = VINSGR2VR_B { 1158, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1158 = VILVL_W { 1157, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1157 = VILVL_H { 1156, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1156 = VILVL_D { 1155, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1155 = VILVL_B { 1154, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1154 = VILVH_W { 1153, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1153 = VILVH_H { 1152, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1152 = VILVH_D { 1151, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1151 = VILVH_B { 1150, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1150 = VHSUBW_W_H { 1149, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1149 = VHSUBW_WU_HU { 1148, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1148 = VHSUBW_Q_D { 1147, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1147 = VHSUBW_QU_DU { 1146, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1146 = VHSUBW_H_B { 1145, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1145 = VHSUBW_HU_BU { 1144, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1144 = VHSUBW_D_W { 1143, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1143 = VHSUBW_DU_WU { 1142, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1142 = VHADDW_W_H { 1141, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1141 = VHADDW_WU_HU { 1140, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1140 = VHADDW_Q_D { 1139, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1139 = VHADDW_QU_DU { 1138, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1138 = VHADDW_H_B { 1137, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1137 = VHADDW_HU_BU { 1136, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1136 = VHADDW_D_W { 1135, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1135 = VHADDW_DU_WU { 1134, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1134 = VFTINT_W_S { 1133, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1133 = VFTINT_W_D { 1132, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1132 = VFTINT_WU_S { 1131, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1131 = VFTINT_L_D { 1130, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1130 = VFTINT_LU_D { 1129, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1129 = VFTINTRZ_W_S { 1128, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1128 = VFTINTRZ_W_D { 1127, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1127 = VFTINTRZ_WU_S { 1126, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1126 = VFTINTRZ_L_D { 1125, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1125 = VFTINTRZ_LU_D { 1124, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1124 = VFTINTRZL_L_S { 1123, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1123 = VFTINTRZH_L_S { 1122, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1122 = VFTINTRP_W_S { 1121, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1121 = VFTINTRP_W_D { 1120, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1120 = VFTINTRP_L_D { 1119, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1119 = VFTINTRPL_L_S { 1118, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1118 = VFTINTRPH_L_S { 1117, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1117 = VFTINTRNE_W_S { 1116, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1116 = VFTINTRNE_W_D { 1115, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1115 = VFTINTRNE_L_D { 1114, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1114 = VFTINTRNEL_L_S { 1113, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1113 = VFTINTRNEH_L_S { 1112, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1112 = VFTINTRM_W_S { 1111, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1111 = VFTINTRM_W_D { 1110, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1110 = VFTINTRM_L_D { 1109, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1109 = VFTINTRML_L_S { 1108, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1108 = VFTINTRMH_L_S { 1107, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1107 = VFTINTL_L_S { 1106, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1106 = VFTINTH_L_S { 1105, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1105 = VFSUB_S { 1104, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1104 = VFSUB_D { 1103, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1103 = VFSQRT_S { 1102, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1102 = VFSQRT_D { 1101, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 351, 0, 0x0ULL }, // Inst #1101 = VFRSTP_H { 1100, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 351, 0, 0x0ULL }, // Inst #1100 = VFRSTP_B { 1099, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #1099 = VFRSTPI_H { 1098, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #1098 = VFRSTPI_B { 1097, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1097 = VFRSQRT_S { 1096, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1096 = VFRSQRT_D { 1095, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1095 = VFRSQRTE_S { 1094, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1094 = VFRSQRTE_D { 1093, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1093 = VFRINT_S { 1092, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1092 = VFRINT_D { 1091, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1091 = VFRINTRZ_S { 1090, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1090 = VFRINTRZ_D { 1089, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1089 = VFRINTRP_S { 1088, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1088 = VFRINTRP_D { 1087, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1087 = VFRINTRNE_S { 1086, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1086 = VFRINTRNE_D { 1085, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1085 = VFRINTRM_S { 1084, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1084 = VFRINTRM_D { 1083, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1083 = VFRECIP_S { 1082, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1082 = VFRECIP_D { 1081, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1081 = VFRECIPE_S { 1080, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1080 = VFRECIPE_D { 1079, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 343, 0, 0x0ULL }, // Inst #1079 = VFNMSUB_S { 1078, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 343, 0, 0x0ULL }, // Inst #1078 = VFNMSUB_D { 1077, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 343, 0, 0x0ULL }, // Inst #1077 = VFNMADD_S { 1076, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 343, 0, 0x0ULL }, // Inst #1076 = VFNMADD_D { 1075, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1075 = VFMUL_S { 1074, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1074 = VFMUL_D { 1073, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 343, 0, 0x0ULL }, // Inst #1073 = VFMSUB_S { 1072, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 343, 0, 0x0ULL }, // Inst #1072 = VFMSUB_D { 1071, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1071 = VFMIN_S { 1070, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1070 = VFMIN_D { 1069, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1069 = VFMINA_S { 1068, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1068 = VFMINA_D { 1067, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1067 = VFMAX_S { 1066, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1066 = VFMAX_D { 1065, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1065 = VFMAXA_S { 1064, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1064 = VFMAXA_D { 1063, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 343, 0, 0x0ULL }, // Inst #1063 = VFMADD_S { 1062, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 343, 0, 0x0ULL }, // Inst #1062 = VFMADD_D { 1061, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1061 = VFLOGB_S { 1060, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1060 = VFLOGB_D { 1059, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1059 = VFFINT_S_WU { 1058, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1058 = VFFINT_S_W { 1057, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1057 = VFFINT_S_L { 1056, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1056 = VFFINT_D_LU { 1055, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1055 = VFFINT_D_L { 1054, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1054 = VFFINTL_D_W { 1053, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1053 = VFFINTH_D_W { 1052, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1052 = VFDIV_S { 1051, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1051 = VFDIV_D { 1050, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1050 = VFCVT_S_D { 1049, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1049 = VFCVT_H_S { 1048, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1048 = VFCVTL_S_H { 1047, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1047 = VFCVTL_D_S { 1046, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1046 = VFCVTH_S_H { 1045, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1045 = VFCVTH_D_S { 1044, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1044 = VFCMP_SUN_S { 1043, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1043 = VFCMP_SUN_D { 1042, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1042 = VFCMP_SUNE_S { 1041, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1041 = VFCMP_SUNE_D { 1040, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1040 = VFCMP_SULT_S { 1039, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1039 = VFCMP_SULT_D { 1038, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1038 = VFCMP_SULE_S { 1037, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1037 = VFCMP_SULE_D { 1036, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1036 = VFCMP_SUEQ_S { 1035, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1035 = VFCMP_SUEQ_D { 1034, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1034 = VFCMP_SOR_S { 1033, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1033 = VFCMP_SOR_D { 1032, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1032 = VFCMP_SNE_S { 1031, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1031 = VFCMP_SNE_D { 1030, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1030 = VFCMP_SLT_S { 1029, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1029 = VFCMP_SLT_D { 1028, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1028 = VFCMP_SLE_S { 1027, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1027 = VFCMP_SLE_D { 1026, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1026 = VFCMP_SEQ_S { 1025, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1025 = VFCMP_SEQ_D { 1024, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1024 = VFCMP_SAF_S { 1023, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1023 = VFCMP_SAF_D { 1022, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1022 = VFCMP_CUN_S { 1021, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1021 = VFCMP_CUN_D { 1020, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1020 = VFCMP_CUNE_S { 1019, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1019 = VFCMP_CUNE_D { 1018, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1018 = VFCMP_CULT_S { 1017, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1017 = VFCMP_CULT_D { 1016, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1016 = VFCMP_CULE_S { 1015, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1015 = VFCMP_CULE_D { 1014, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1014 = VFCMP_CUEQ_S { 1013, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1013 = VFCMP_CUEQ_D { 1012, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1012 = VFCMP_COR_S { 1011, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1011 = VFCMP_COR_D { 1010, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1010 = VFCMP_CNE_S { 1009, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1009 = VFCMP_CNE_D { 1008, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1008 = VFCMP_CLT_S { 1007, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1007 = VFCMP_CLT_D { 1006, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1006 = VFCMP_CLE_S { 1005, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1005 = VFCMP_CLE_D { 1004, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1004 = VFCMP_CEQ_S { 1003, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1003 = VFCMP_CEQ_D { 1002, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1002 = VFCMP_CAF_S { 1001, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1001 = VFCMP_CAF_D { 1000, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1000 = VFCLASS_S { 999, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #999 = VFCLASS_D { 998, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #998 = VFADD_S { 997, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #997 = VFADD_D { 996, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #996 = VEXTRINS_W { 995, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #995 = VEXTRINS_H { 994, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #994 = VEXTRINS_D { 993, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #993 = VEXTRINS_B { 992, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #992 = VEXTL_Q_D { 991, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #991 = VEXTL_QU_DU { 990, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #990 = VEXTH_W_H { 989, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #989 = VEXTH_WU_HU { 988, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #988 = VEXTH_Q_D { 987, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #987 = VEXTH_QU_DU { 986, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #986 = VEXTH_H_B { 985, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #985 = VEXTH_HU_BU { 984, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #984 = VEXTH_D_W { 983, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #983 = VEXTH_DU_WU { 982, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #982 = VEXT2XV_W_H { 981, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #981 = VEXT2XV_W_B { 980, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #980 = VEXT2XV_WU_HU { 979, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #979 = VEXT2XV_WU_BU { 978, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #978 = VEXT2XV_H_B { 977, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #977 = VEXT2XV_HU_BU { 976, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #976 = VEXT2XV_D_W { 975, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #975 = VEXT2XV_D_H { 974, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #974 = VEXT2XV_D_B { 973, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #973 = VEXT2XV_DU_WU { 972, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #972 = VEXT2XV_DU_HU { 971, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #971 = VEXT2XV_DU_BU { 970, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #970 = VDIV_WU { 969, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #969 = VDIV_W { 968, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #968 = VDIV_HU { 967, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #967 = VDIV_H { 966, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #966 = VDIV_DU { 965, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #965 = VDIV_D { 964, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #964 = VDIV_BU { 963, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #963 = VDIV_B { 962, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #962 = VCLZ_W { 961, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #961 = VCLZ_H { 960, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #960 = VCLZ_D { 959, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #959 = VCLZ_B { 958, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #958 = VCLO_W { 957, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #957 = VCLO_H { 956, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #956 = VCLO_D { 955, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #955 = VCLO_B { 954, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #954 = VBSRL_V { 953, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #953 = VBSLL_V { 952, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #952 = VBITSET_W { 951, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #951 = VBITSET_H { 950, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #950 = VBITSET_D { 949, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #949 = VBITSET_B { 948, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #948 = VBITSETI_W { 947, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #947 = VBITSETI_H { 946, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #946 = VBITSETI_D { 945, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #945 = VBITSETI_B { 944, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 343, 0, 0x0ULL }, // Inst #944 = VBITSEL_V { 943, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #943 = VBITSELI_B { 942, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #942 = VBITREV_W { 941, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #941 = VBITREV_H { 940, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #940 = VBITREV_D { 939, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #939 = VBITREV_B { 938, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #938 = VBITREVI_W { 937, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #937 = VBITREVI_H { 936, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #936 = VBITREVI_D { 935, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #935 = VBITREVI_B { 934, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #934 = VBITCLR_W { 933, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #933 = VBITCLR_H { 932, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #932 = VBITCLR_D { 931, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #931 = VBITCLR_B { 930, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #930 = VBITCLRI_W { 929, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #929 = VBITCLRI_H { 928, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #928 = VBITCLRI_D { 927, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #927 = VBITCLRI_B { 926, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #926 = VAVG_WU { 925, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #925 = VAVG_W { 924, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #924 = VAVG_HU { 923, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #923 = VAVG_H { 922, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #922 = VAVG_DU { 921, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #921 = VAVG_D { 920, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #920 = VAVG_BU { 919, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #919 = VAVG_B { 918, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #918 = VAVGR_WU { 917, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #917 = VAVGR_W { 916, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #916 = VAVGR_HU { 915, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #915 = VAVGR_H { 914, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #914 = VAVGR_DU { 913, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #913 = VAVGR_D { 912, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #912 = VAVGR_BU { 911, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #911 = VAVGR_B { 910, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #910 = VAND_V { 909, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #909 = VANDN_V { 908, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #908 = VANDI_B { 907, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #907 = VADD_W { 906, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #906 = VADD_Q { 905, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #905 = VADD_H { 904, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #904 = VADD_D { 903, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #903 = VADD_B { 902, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #902 = VADDWOD_W_HU_H { 901, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #901 = VADDWOD_W_HU { 900, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #900 = VADDWOD_W_H { 899, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #899 = VADDWOD_Q_DU_D { 898, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #898 = VADDWOD_Q_DU { 897, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #897 = VADDWOD_Q_D { 896, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #896 = VADDWOD_H_BU_B { 895, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #895 = VADDWOD_H_BU { 894, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #894 = VADDWOD_H_B { 893, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #893 = VADDWOD_D_WU_W { 892, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #892 = VADDWOD_D_WU { 891, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #891 = VADDWOD_D_W { 890, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #890 = VADDWEV_W_HU_H { 889, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #889 = VADDWEV_W_HU { 888, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #888 = VADDWEV_W_H { 887, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #887 = VADDWEV_Q_DU_D { 886, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #886 = VADDWEV_Q_DU { 885, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #885 = VADDWEV_Q_D { 884, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #884 = VADDWEV_H_BU_B { 883, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #883 = VADDWEV_H_BU { 882, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #882 = VADDWEV_H_B { 881, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #881 = VADDWEV_D_WU_W { 880, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #880 = VADDWEV_D_WU { 879, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #879 = VADDWEV_D_W { 878, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #878 = VADDI_WU { 877, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #877 = VADDI_HU { 876, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #876 = VADDI_DU { 875, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #875 = VADDI_BU { 874, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #874 = VADDA_W { 873, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #873 = VADDA_H { 872, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #872 = VADDA_D { 871, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #871 = VADDA_B { 870, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #870 = VABSD_WU { 869, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #869 = VABSD_W { 868, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #868 = VABSD_HU { 867, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #867 = VABSD_H { 866, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #866 = VABSD_DU { 865, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #865 = VABSD_D { 864, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #864 = VABSD_BU { 863, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #863 = VABSD_B { 862, 0, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #862 = TLBWR { 861, 0, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #861 = TLBSRCH { 860, 0, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #860 = TLBRD { 859, 0, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #859 = TLBFLUSH { 858, 0, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #858 = TLBFILL { 857, 0, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #857 = TLBCLR { 856, 1, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #856 = SYSCALL { 855, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0, 0x0ULL }, // Inst #855 = SUB_W { 854, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0, 0x0ULL }, // Inst #854 = SUB_D { 853, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 175, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #853 = ST_W { 852, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 175, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #852 = ST_H { 851, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 175, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #851 = ST_D { 850, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 175, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #850 = ST_B { 849, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #849 = STX_W { 848, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #848 = STX_H { 847, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #847 = STX_D { 846, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #846 = STX_B { 845, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 175, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #845 = STR_W { 844, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 175, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #844 = STR_D { 843, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 175, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #843 = STPTR_W { 842, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 175, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #842 = STPTR_D { 841, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 175, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #841 = STL_W { 840, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 175, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #840 = STL_D { 839, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #839 = STLE_W { 838, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #838 = STLE_H { 837, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #837 = STLE_D { 836, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #836 = STLE_B { 835, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #835 = STGT_W { 834, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #834 = STGT_H { 833, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #833 = STGT_D { 832, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #832 = STGT_B { 831, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0, 0x0ULL }, // Inst #831 = SRL_W { 830, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0, 0x0ULL }, // Inst #830 = SRL_D { 829, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 175, 0, 0x0ULL }, // Inst #829 = SRLI_W { 828, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 175, 0, 0x0ULL }, // Inst #828 = SRLI_D { 827, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0, 0x0ULL }, // Inst #827 = SRA_W { 826, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0, 0x0ULL }, // Inst #826 = SRA_D { 825, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 175, 0, 0x0ULL }, // Inst #825 = SRAI_W { 824, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 175, 0, 0x0ULL }, // Inst #824 = SRAI_D { 823, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 175, 0, 0x0ULL }, // Inst #823 = SLTUI { 822, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0, 0x0ULL }, // Inst #822 = SLTU { 821, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 175, 0, 0x0ULL }, // Inst #821 = SLTI { 820, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0, 0x0ULL }, // Inst #820 = SLT { 819, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0, 0x0ULL }, // Inst #819 = SLL_W { 818, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0, 0x0ULL }, // Inst #818 = SLL_D { 817, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 175, 0, 0x0ULL }, // Inst #817 = SLLI_W { 816, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 175, 0, 0x0ULL }, // Inst #816 = SLLI_D { 815, 1, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 332, 0, 0x0ULL }, // Inst #815 = SET_CFR_TRUE { 814, 1, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 332, 0, 0x0ULL }, // Inst #814 = SET_CFR_FALSE { 813, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #813 = SETX86LOOPNE { 812, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #812 = SETX86LOOPE { 811, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0, 0x0ULL }, // Inst #811 = SETX86J { 810, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0, 0x0ULL }, // Inst #810 = SETARMJ { 809, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 243, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #809 = SC_W { 808, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 328, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #808 = SC_Q { 807, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 243, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #807 = SC_D { 806, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 325, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #806 = SCREL_W { 805, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 325, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #805 = SCREL_D { 804, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0, 0x0ULL }, // Inst #804 = SBC_W { 803, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0, 0x0ULL }, // Inst #803 = SBC_H { 802, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0, 0x0ULL }, // Inst #802 = SBC_D { 801, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0, 0x0ULL }, // Inst #801 = SBC_B { 800, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0, 0x0ULL }, // Inst #800 = ROTR_W { 799, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0, 0x0ULL }, // Inst #799 = ROTR_H { 798, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0, 0x0ULL }, // Inst #798 = ROTR_D { 797, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0, 0x0ULL }, // Inst #797 = ROTR_B { 796, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 175, 0, 0x0ULL }, // Inst #796 = ROTRI_W { 795, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 175, 0, 0x0ULL }, // Inst #795 = ROTRI_H { 794, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 175, 0, 0x0ULL }, // Inst #794 = ROTRI_D { 793, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 175, 0, 0x0ULL }, // Inst #793 = ROTRI_B { 792, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #792 = REVH_D { 791, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #791 = REVH_2W { 790, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #790 = REVB_D { 789, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #789 = REVB_4H { 788, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #788 = REVB_2W { 787, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #787 = REVB_2H { 786, 2, 2, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #786 = RDTIME_D { 785, 2, 2, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #785 = RDTIMEL_W { 784, 2, 2, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #784 = RDTIMEH_W { 783, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0, 0x0ULL }, // Inst #783 = RCR_W { 782, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0, 0x0ULL }, // Inst #782 = RCR_H { 781, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0, 0x0ULL }, // Inst #781 = RCR_D { 780, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0, 0x0ULL }, // Inst #780 = RCR_B { 779, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 175, 0, 0x0ULL }, // Inst #779 = RCRI_W { 778, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 175, 0, 0x0ULL }, // Inst #778 = RCRI_H { 777, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 175, 0, 0x0ULL }, // Inst #777 = RCRI_D { 776, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 175, 0, 0x0ULL }, // Inst #776 = RCRI_B { 775, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 322, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #775 = PRELDX { 774, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 237, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #774 = PRELD { 773, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0, 0x0ULL }, // Inst #773 = PCALAU12I { 772, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0, 0x0ULL }, // Inst #772 = PCADDU18I { 771, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0, 0x0ULL }, // Inst #771 = PCADDU12I { 770, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0, 0x0ULL }, // Inst #770 = PCADDI { 769, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0, 0x0ULL }, // Inst #769 = ORN { 768, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 175, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // Inst #768 = ORI { 767, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0, 0x0ULL }, // Inst #767 = OR { 766, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0, 0x0ULL }, // Inst #766 = NOR { 765, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0, 0x0ULL }, // Inst #765 = MUL_W { 764, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0, 0x0ULL }, // Inst #764 = MUL_D { 763, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0, 0x0ULL }, // Inst #763 = MULW_D_WU { 762, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0, 0x0ULL }, // Inst #762 = MULW_D_W { 761, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0, 0x0ULL }, // Inst #761 = MULH_WU { 760, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0, 0x0ULL }, // Inst #760 = MULH_W { 759, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0, 0x0ULL }, // Inst #759 = MULH_DU { 758, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0, 0x0ULL }, // Inst #758 = MULH_D { 757, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 320, 0, 0x0ULL }, // Inst #757 = MOVSCR2GR { 756, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 318, 0, 0x0ULL }, // Inst #756 = MOVGR2SCR { 755, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 314, 0, 0x0ULL }, // Inst #755 = MOVGR2FR_W_64 { 754, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 316, 0, 0x0ULL }, // Inst #754 = MOVGR2FR_W { 753, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 314, 0, 0x0ULL }, // Inst #753 = MOVGR2FR_D { 752, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 311, 0, 0x0ULL }, // Inst #752 = MOVGR2FRH_W { 751, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 309, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #751 = MOVGR2FCSR { 750, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 307, 0, 0x0ULL }, // Inst #750 = MOVGR2CF { 749, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 303, 0, 0x0ULL }, // Inst #749 = MOVFRH2GR_S { 748, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 303, 0, 0x0ULL }, // Inst #748 = MOVFR2GR_S_64 { 747, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 305, 0, 0x0ULL }, // Inst #747 = MOVFR2GR_S { 746, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 303, 0, 0x0ULL }, // Inst #746 = MOVFR2GR_D { 745, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 301, 0, 0x0ULL }, // Inst #745 = MOVFR2CF_xS { 744, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 299, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #744 = MOVFCSR2GR { 743, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 297, 0, 0x0ULL }, // Inst #743 = MOVCF2GR { 742, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 295, 0, 0x0ULL }, // Inst #742 = MOVCF2FR_xS { 741, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #741 = MOD_WU { 740, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #740 = MOD_W { 739, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #739 = MOD_DU { 738, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #738 = MOD_D { 737, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0, 0x0ULL }, // Inst #737 = MASKNEZ { 736, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0, 0x0ULL }, // Inst #736 = MASKEQZ { 735, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 175, 0|(1ULL<<MCID::Rematerializable), 0x0ULL }, // Inst #735 = LU52I_D { 734, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 240, 0|(1ULL<<MCID::Rematerializable), 0x0ULL }, // Inst #734 = LU32I_D { 733, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0|(1ULL<<MCID::Rematerializable), 0x0ULL }, // Inst #733 = LU12I_W { 732, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 175, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #732 = LL_W { 731, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 175, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #731 = LL_D { 730, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #730 = LLACQ_W { 729, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #729 = LLACQ_D { 728, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 175, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #728 = LD_WU { 727, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 175, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #727 = LD_W { 726, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 175, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #726 = LD_HU { 725, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 175, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #725 = LD_H { 724, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 175, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #724 = LD_D { 723, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 175, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #723 = LD_BU { 722, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 175, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #722 = LD_B { 721, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #721 = LDX_WU { 720, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #720 = LDX_W { 719, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #719 = LDX_HU { 718, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #718 = LDX_H { 717, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #717 = LDX_D { 716, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #716 = LDX_BU { 715, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #715 = LDX_B { 714, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 175, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #714 = LDR_W { 713, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 175, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #713 = LDR_D { 712, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 175, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #712 = LDPTR_W { 711, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 175, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #711 = LDPTR_D { 710, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #710 = LDPTE { 709, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 175, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #709 = LDL_W { 708, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 175, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #708 = LDL_D { 707, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #707 = LDLE_W { 706, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #706 = LDLE_H { 705, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #705 = LDLE_D { 704, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #704 = LDLE_B { 703, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #703 = LDGT_W { 702, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #702 = LDGT_H { 701, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #701 = LDGT_D { 700, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #700 = LDGT_B { 699, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 175, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #699 = LDDIR { 698, 1, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 0, 0, 0x0ULL }, // Inst #698 = JISCR1 { 697, 1, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 0, 0, 0x0ULL }, // Inst #697 = JISCR0 { 696, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 175, 0, 0x0ULL }, // Inst #696 = JIRL { 695, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #695 = IOCSRWR_W { 694, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #694 = IOCSRWR_H { 693, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #693 = IOCSRWR_D { 692, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #692 = IOCSRWR_B { 691, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #691 = IOCSRRD_W { 690, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #690 = IOCSRRD_H { 689, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #689 = IOCSRRD_D { 688, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #688 = IOCSRRD_B { 687, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 175, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #687 = INVTLB { 686, 1, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #686 = IDLE { 685, 1, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #685 = IBAR { 684, 1, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #684 = HVCL { 683, 0, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #683 = GTLBFLUSH { 682, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 243, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #682 = GCSRXCHG { 681, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 240, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #681 = GCSRWR { 680, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #680 = GCSRRD { 679, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 249, 0, 0x0ULL }, // Inst #679 = FTINT_W_S { 678, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 265, 0, 0x0ULL }, // Inst #678 = FTINT_W_D { 677, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 263, 0, 0x0ULL }, // Inst #677 = FTINT_L_S { 676, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 247, 0, 0x0ULL }, // Inst #676 = FTINT_L_D { 675, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 249, 0, 0x0ULL }, // Inst #675 = FTINTRZ_W_S { 674, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 265, 0, 0x0ULL }, // Inst #674 = FTINTRZ_W_D { 673, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 263, 0, 0x0ULL }, // Inst #673 = FTINTRZ_L_S { 672, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 247, 0, 0x0ULL }, // Inst #672 = FTINTRZ_L_D { 671, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 249, 0, 0x0ULL }, // Inst #671 = FTINTRP_W_S { 670, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 265, 0, 0x0ULL }, // Inst #670 = FTINTRP_W_D { 669, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 263, 0, 0x0ULL }, // Inst #669 = FTINTRP_L_S { 668, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 247, 0, 0x0ULL }, // Inst #668 = FTINTRP_L_D { 667, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 249, 0, 0x0ULL }, // Inst #667 = FTINTRNE_W_S { 666, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 265, 0, 0x0ULL }, // Inst #666 = FTINTRNE_W_D { 665, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 263, 0, 0x0ULL }, // Inst #665 = FTINTRNE_L_S { 664, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 247, 0, 0x0ULL }, // Inst #664 = FTINTRNE_L_D { 663, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 249, 0, 0x0ULL }, // Inst #663 = FTINTRM_W_S { 662, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 265, 0, 0x0ULL }, // Inst #662 = FTINTRM_W_D { 661, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 263, 0, 0x0ULL }, // Inst #661 = FTINTRM_L_S { 660, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 247, 0, 0x0ULL }, // Inst #660 = FTINTRM_L_D { 659, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 254, 0, 0x0ULL }, // Inst #659 = FSUB_S { 658, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 251, 0, 0x0ULL }, // Inst #658 = FSUB_D { 657, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 276, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #657 = FST_S { 656, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 273, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #656 = FST_D { 655, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 270, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #655 = FSTX_S { 654, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 267, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #654 = FSTX_D { 653, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 270, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #653 = FSTLE_S { 652, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 267, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #652 = FSTLE_D { 651, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 270, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #651 = FSTGT_S { 650, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 267, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #650 = FSTGT_D { 649, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 249, 0, 0x0ULL }, // Inst #649 = FSQRT_S { 648, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 247, 0, 0x0ULL }, // Inst #648 = FSQRT_D { 647, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 291, 0, 0x0ULL }, // Inst #647 = FSEL_xS { 646, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 287, 0, 0x0ULL }, // Inst #646 = FSEL_xD { 645, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 254, 0, 0x0ULL }, // Inst #645 = FSCALEB_S { 644, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 251, 0, 0x0ULL }, // Inst #644 = FSCALEB_D { 643, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 249, 0, 0x0ULL }, // Inst #643 = FRSQRT_S { 642, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 247, 0, 0x0ULL }, // Inst #642 = FRSQRT_D { 641, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 249, 0, 0x0ULL }, // Inst #641 = FRSQRTE_S { 640, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 247, 0, 0x0ULL }, // Inst #640 = FRSQRTE_D { 639, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 249, 0, 0x0ULL }, // Inst #639 = FRINT_S { 638, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 247, 0, 0x0ULL }, // Inst #638 = FRINT_D { 637, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 249, 0, 0x0ULL }, // Inst #637 = FRECIP_S { 636, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 247, 0, 0x0ULL }, // Inst #636 = FRECIP_D { 635, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 249, 0, 0x0ULL }, // Inst #635 = FRECIPE_S { 634, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 247, 0, 0x0ULL }, // Inst #634 = FRECIPE_D { 633, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 283, 0, 0x0ULL }, // Inst #633 = FNMSUB_S { 632, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 279, 0, 0x0ULL }, // Inst #632 = FNMSUB_D { 631, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 283, 0, 0x0ULL }, // Inst #631 = FNMADD_S { 630, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 279, 0, 0x0ULL }, // Inst #630 = FNMADD_D { 629, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 249, 0, 0x0ULL }, // Inst #629 = FNEG_S { 628, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 247, 0, 0x0ULL }, // Inst #628 = FNEG_D { 627, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 254, 0, 0x0ULL }, // Inst #627 = FMUL_S { 626, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 251, 0, 0x0ULL }, // Inst #626 = FMUL_D { 625, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 283, 0, 0x0ULL }, // Inst #625 = FMSUB_S { 624, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 279, 0, 0x0ULL }, // Inst #624 = FMSUB_D { 623, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 249, 0, 0x0ULL }, // Inst #623 = FMOV_S { 622, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 247, 0, 0x0ULL }, // Inst #622 = FMOV_D { 621, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 254, 0, 0x0ULL }, // Inst #621 = FMIN_S { 620, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 251, 0, 0x0ULL }, // Inst #620 = FMIN_D { 619, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 254, 0, 0x0ULL }, // Inst #619 = FMINA_S { 618, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 251, 0, 0x0ULL }, // Inst #618 = FMINA_D { 617, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 254, 0, 0x0ULL }, // Inst #617 = FMAX_S { 616, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 251, 0, 0x0ULL }, // Inst #616 = FMAX_D { 615, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 254, 0, 0x0ULL }, // Inst #615 = FMAXA_S { 614, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 251, 0, 0x0ULL }, // Inst #614 = FMAXA_D { 613, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 283, 0, 0x0ULL }, // Inst #613 = FMADD_S { 612, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 279, 0, 0x0ULL }, // Inst #612 = FMADD_D { 611, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 249, 0, 0x0ULL }, // Inst #611 = FLOGB_S { 610, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 247, 0, 0x0ULL }, // Inst #610 = FLOGB_D { 609, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 276, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #609 = FLD_S { 608, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 273, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #608 = FLD_D { 607, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 270, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #607 = FLDX_S { 606, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 267, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #606 = FLDX_D { 605, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 270, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #605 = FLDLE_S { 604, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 267, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #604 = FLDLE_D { 603, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 270, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #603 = FLDGT_S { 602, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 267, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #602 = FLDGT_D { 601, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 249, 0, 0x0ULL }, // Inst #601 = FFINT_S_W { 600, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 265, 0, 0x0ULL }, // Inst #600 = FFINT_S_L { 599, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 263, 0, 0x0ULL }, // Inst #599 = FFINT_D_W { 598, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 247, 0, 0x0ULL }, // Inst #598 = FFINT_D_L { 597, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 254, 0, 0x0ULL }, // Inst #597 = FDIV_S { 596, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 251, 0, 0x0ULL }, // Inst #596 = FDIV_D { 595, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 249, 0, 0x0ULL }, // Inst #595 = FCVT_UD_D { 594, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 265, 0, 0x0ULL }, // Inst #594 = FCVT_S_D { 593, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 249, 0, 0x0ULL }, // Inst #593 = FCVT_LD_D { 592, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 263, 0, 0x0ULL }, // Inst #592 = FCVT_D_S { 591, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 254, 0, 0x0ULL }, // Inst #591 = FCVT_D_LD { 590, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 254, 0, 0x0ULL }, // Inst #590 = FCOPYSIGN_S { 589, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 251, 0, 0x0ULL }, // Inst #589 = FCOPYSIGN_D { 588, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 260, 0, 0x0ULL }, // Inst #588 = FCMP_SUN_S { 587, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 257, 0, 0x0ULL }, // Inst #587 = FCMP_SUN_D { 586, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 260, 0, 0x0ULL }, // Inst #586 = FCMP_SUNE_S { 585, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 257, 0, 0x0ULL }, // Inst #585 = FCMP_SUNE_D { 584, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 260, 0, 0x0ULL }, // Inst #584 = FCMP_SULT_S { 583, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 257, 0, 0x0ULL }, // Inst #583 = FCMP_SULT_D { 582, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 260, 0, 0x0ULL }, // Inst #582 = FCMP_SULE_S { 581, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 257, 0, 0x0ULL }, // Inst #581 = FCMP_SULE_D { 580, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 260, 0, 0x0ULL }, // Inst #580 = FCMP_SUEQ_S { 579, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 257, 0, 0x0ULL }, // Inst #579 = FCMP_SUEQ_D { 578, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 260, 0, 0x0ULL }, // Inst #578 = FCMP_SOR_S { 577, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 257, 0, 0x0ULL }, // Inst #577 = FCMP_SOR_D { 576, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 260, 0, 0x0ULL }, // Inst #576 = FCMP_SNE_S { 575, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 257, 0, 0x0ULL }, // Inst #575 = FCMP_SNE_D { 574, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 260, 0, 0x0ULL }, // Inst #574 = FCMP_SLT_S { 573, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 257, 0, 0x0ULL }, // Inst #573 = FCMP_SLT_D { 572, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 260, 0, 0x0ULL }, // Inst #572 = FCMP_SLE_S { 571, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 257, 0, 0x0ULL }, // Inst #571 = FCMP_SLE_D { 570, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 260, 0, 0x0ULL }, // Inst #570 = FCMP_SEQ_S { 569, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 257, 0, 0x0ULL }, // Inst #569 = FCMP_SEQ_D { 568, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 260, 0, 0x0ULL }, // Inst #568 = FCMP_SAF_S { 567, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 257, 0, 0x0ULL }, // Inst #567 = FCMP_SAF_D { 566, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 260, 0, 0x0ULL }, // Inst #566 = FCMP_CUN_S { 565, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 257, 0, 0x0ULL }, // Inst #565 = FCMP_CUN_D { 564, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 260, 0, 0x0ULL }, // Inst #564 = FCMP_CUNE_S { 563, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 257, 0, 0x0ULL }, // Inst #563 = FCMP_CUNE_D { 562, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 260, 0, 0x0ULL }, // Inst #562 = FCMP_CULT_S { 561, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 257, 0, 0x0ULL }, // Inst #561 = FCMP_CULT_D { 560, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 260, 0, 0x0ULL }, // Inst #560 = FCMP_CULE_S { 559, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 257, 0, 0x0ULL }, // Inst #559 = FCMP_CULE_D { 558, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 260, 0, 0x0ULL }, // Inst #558 = FCMP_CUEQ_S { 557, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 257, 0, 0x0ULL }, // Inst #557 = FCMP_CUEQ_D { 556, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 260, 0, 0x0ULL }, // Inst #556 = FCMP_COR_S { 555, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 257, 0, 0x0ULL }, // Inst #555 = FCMP_COR_D { 554, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 260, 0, 0x0ULL }, // Inst #554 = FCMP_CNE_S { 553, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 257, 0, 0x0ULL }, // Inst #553 = FCMP_CNE_D { 552, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 260, 0, 0x0ULL }, // Inst #552 = FCMP_CLT_S { 551, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 257, 0, 0x0ULL }, // Inst #551 = FCMP_CLT_D { 550, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 260, 0, 0x0ULL }, // Inst #550 = FCMP_CLE_S { 549, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 257, 0, 0x0ULL }, // Inst #549 = FCMP_CLE_D { 548, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 260, 0, 0x0ULL }, // Inst #548 = FCMP_CEQ_S { 547, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 257, 0, 0x0ULL }, // Inst #547 = FCMP_CEQ_D { 546, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 260, 0, 0x0ULL }, // Inst #546 = FCMP_CAF_S { 545, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 257, 0, 0x0ULL }, // Inst #545 = FCMP_CAF_D { 544, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 249, 0, 0x0ULL }, // Inst #544 = FCLASS_S { 543, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 247, 0, 0x0ULL }, // Inst #543 = FCLASS_D { 542, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 254, 0, 0x0ULL }, // Inst #542 = FADD_S { 541, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 251, 0, 0x0ULL }, // Inst #541 = FADD_D { 540, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 249, 0, 0x0ULL }, // Inst #540 = FABS_S { 539, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 247, 0, 0x0ULL }, // Inst #539 = FABS_D { 538, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #538 = EXT_W_H { 537, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #537 = EXT_W_B { 536, 0, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #536 = ERTN { 535, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #535 = DIV_WU { 534, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #534 = DIV_W { 533, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #533 = DIV_DU { 532, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #532 = DIV_D { 531, 1, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #531 = DBCL { 530, 1, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #530 = DBAR { 529, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #529 = CTZ_W { 528, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #528 = CTZ_D { 527, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #527 = CTO_W { 526, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #526 = CTO_D { 525, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 243, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #525 = CSRXCHG { 524, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 240, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #524 = CSRWR { 523, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #523 = CSRRD { 522, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0, 0x0ULL }, // Inst #522 = CRC_W_W_W { 521, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0, 0x0ULL }, // Inst #521 = CRC_W_H_W { 520, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0, 0x0ULL }, // Inst #520 = CRC_W_D_W { 519, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0, 0x0ULL }, // Inst #519 = CRC_W_B_W { 518, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0, 0x0ULL }, // Inst #518 = CRCC_W_W_W { 517, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0, 0x0ULL }, // Inst #517 = CRCC_W_H_W { 516, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0, 0x0ULL }, // Inst #516 = CRCC_W_D_W { 515, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0, 0x0ULL }, // Inst #515 = CRCC_W_B_W { 514, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #514 = CPUCFG { 513, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #513 = CLZ_W { 512, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #512 = CLZ_D { 511, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #511 = CLO_W { 510, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #510 = CLO_D { 509, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 237, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #509 = CACOP { 508, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 152, 0, 0x0ULL }, // Inst #508 = BYTEPICK_W { 507, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 152, 0, 0x0ULL }, // Inst #507 = BYTEPICK_D { 506, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 233, 0, 0x0ULL }, // Inst #506 = BSTRPICK_W { 505, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 233, 0, 0x0ULL }, // Inst #505 = BSTRPICK_D { 504, 5, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 228, 0, 0x0ULL }, // Inst #504 = BSTRINS_W { 503, 5, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 228, 0, 0x0ULL }, // Inst #503 = BSTRINS_D { 502, 1, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #502 = BREAK { 501, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #501 = BNEZ { 500, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 175, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #500 = BNE { 499, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 175, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #499 = BLTU { 498, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 175, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #498 = BLT { 497, 1, 0, 4, 0, 0, 1, LoongArchImpOpBase + 3, 0, 0|(1ULL<<MCID::Call), 0x0ULL }, // Inst #497 = BL { 496, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #496 = BITREV_W { 495, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #495 = BITREV_D { 494, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #494 = BITREV_8B { 493, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #493 = BITREV_4B { 492, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 175, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #492 = BGEU { 491, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 175, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #491 = BGE { 490, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #490 = BEQZ { 489, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 175, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #489 = BEQ { 488, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 226, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #488 = BCNEZ { 487, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 226, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #487 = BCEQZ { 486, 1, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #486 = B { 485, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #485 = ASRTLE_D { 484, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #484 = ASRTGT_D { 483, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 175, 0, 0x0ULL }, // Inst #483 = ARMXOR_W { 482, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 175, 0, 0x0ULL }, // Inst #482 = ARMSUB_W { 481, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 175, 0, 0x0ULL }, // Inst #481 = ARMSRL_W { 480, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 221, 0, 0x0ULL }, // Inst #480 = ARMSRLI_W { 479, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 175, 0, 0x0ULL }, // Inst #479 = ARMSRA_W { 478, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 221, 0, 0x0ULL }, // Inst #478 = ARMSRAI_W { 477, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 175, 0, 0x0ULL }, // Inst #477 = ARMSLL_W { 476, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 221, 0, 0x0ULL }, // Inst #476 = ARMSLLI_W { 475, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 175, 0, 0x0ULL }, // Inst #475 = ARMSBC_W { 474, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0, 0x0ULL }, // Inst #474 = ARMRRX_W { 473, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 175, 0, 0x0ULL }, // Inst #473 = ARMROTR_W { 472, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 221, 0, 0x0ULL }, // Inst #472 = ARMROTRI_W { 471, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 175, 0, 0x0ULL }, // Inst #471 = ARMOR_W { 470, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0, 0x0ULL }, // Inst #470 = ARMNOT_W { 469, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0, 0x0ULL }, // Inst #469 = ARMMTFLAG { 468, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0, 0x0ULL }, // Inst #468 = ARMMOV_W { 467, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0, 0x0ULL }, // Inst #467 = ARMMOV_D { 466, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 175, 0, 0x0ULL }, // Inst #466 = ARMMOVE { 465, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0, 0x0ULL }, // Inst #465 = ARMMFFLAG { 464, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 175, 0, 0x0ULL }, // Inst #464 = ARMAND_W { 463, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 175, 0, 0x0ULL }, // Inst #463 = ARMADD_W { 462, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 175, 0, 0x0ULL }, // Inst #462 = ARMADC_W { 461, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0, 0x0ULL }, // Inst #461 = ANDN { 460, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 175, 0, 0x0ULL }, // Inst #460 = ANDI { 459, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0, 0x0ULL }, // Inst #459 = AND { 458, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 218, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #458 = AMXOR__DB_W { 457, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 218, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #457 = AMXOR__DB_D { 456, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 218, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #456 = AMXOR_W { 455, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 218, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #455 = AMXOR_D { 454, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 218, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #454 = AMSWAP__DB_W { 453, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 218, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #453 = AMSWAP__DB_H { 452, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 218, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #452 = AMSWAP__DB_D { 451, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 218, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #451 = AMSWAP__DB_B { 450, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 218, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #450 = AMSWAP_W { 449, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 218, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #449 = AMSWAP_H { 448, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 218, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #448 = AMSWAP_D { 447, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 218, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #447 = AMSWAP_B { 446, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 218, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #446 = AMOR__DB_W { 445, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 218, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #445 = AMOR__DB_D { 444, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 218, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #444 = AMOR_W { 443, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 218, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #443 = AMOR_D { 442, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 218, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #442 = AMMIN__DB_WU { 441, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 218, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #441 = AMMIN__DB_W { 440, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 218, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #440 = AMMIN__DB_DU { 439, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 218, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #439 = AMMIN__DB_D { 438, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 218, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #438 = AMMIN_WU { 437, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 218, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #437 = AMMIN_W { 436, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 218, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #436 = AMMIN_DU { 435, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 218, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #435 = AMMIN_D { 434, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 218, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #434 = AMMAX__DB_WU { 433, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 218, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #433 = AMMAX__DB_W { 432, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 218, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #432 = AMMAX__DB_DU { 431, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 218, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #431 = AMMAX__DB_D { 430, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 218, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #430 = AMMAX_WU { 429, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 218, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #429 = AMMAX_W { 428, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 218, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #428 = AMMAX_DU { 427, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 218, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #427 = AMMAX_D { 426, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 218, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #426 = AMCAS__DB_W { 425, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 218, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #425 = AMCAS__DB_H { 424, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 218, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #424 = AMCAS__DB_D { 423, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 218, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #423 = AMCAS__DB_B { 422, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 218, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #422 = AMCAS_W { 421, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 218, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #421 = AMCAS_H { 420, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 218, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #420 = AMCAS_D { 419, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 218, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #419 = AMCAS_B { 418, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 218, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #418 = AMAND__DB_W { 417, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 218, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #417 = AMAND__DB_D { 416, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 218, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #416 = AMAND_W { 415, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 218, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #415 = AMAND_D { 414, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 218, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #414 = AMADD__DB_W { 413, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 218, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #413 = AMADD__DB_H { 412, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 218, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #412 = AMADD__DB_D { 411, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 218, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #411 = AMADD__DB_B { 410, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 218, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #410 = AMADD_W { 409, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 218, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #409 = AMADD_H { 408, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 218, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #408 = AMADD_D { 407, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 218, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #407 = AMADD_B { 406, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 152, 0, 0x0ULL }, // Inst #406 = ALSL_WU { 405, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 152, 0, 0x0ULL }, // Inst #405 = ALSL_W { 404, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 152, 0, 0x0ULL }, // Inst #404 = ALSL_D { 403, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0, 0x0ULL }, // Inst #403 = ADD_W { 402, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0, 0x0ULL }, // Inst #402 = ADD_D { 401, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 175, 0, 0x0ULL }, // Inst #401 = ADDU16I_D { 400, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 175, 0, 0x0ULL }, // Inst #400 = ADDU12I_W { 399, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 175, 0, 0x0ULL }, // Inst #399 = ADDU12I_D { 398, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 175, 0, 0x0ULL }, // Inst #398 = ADDI_W { 397, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 175, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // Inst #397 = ADDI_D { 396, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0, 0x0ULL }, // Inst #396 = ADC_W { 395, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0, 0x0ULL }, // Inst #395 = ADC_H { 394, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0, 0x0ULL }, // Inst #394 = ADC_D { 393, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0, 0x0ULL }, // Inst #393 = ADC_B { 392, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 216, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #392 = WRFCSR { 391, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #391 = RDFCSR { 390, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 214, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #390 = PseudoXVREPLI_W { 389, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 214, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #389 = PseudoXVREPLI_H { 388, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 214, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #388 = PseudoXVREPLI_D { 387, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 214, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #387 = PseudoXVREPLI_B { 386, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 210, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #386 = PseudoXVINSGR2VR_H { 385, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 210, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #385 = PseudoXVINSGR2VR_B { 384, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 208, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #384 = PseudoXVBZ_W { 383, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 208, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #383 = PseudoXVBZ_H { 382, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 208, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #382 = PseudoXVBZ_D { 381, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 208, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #381 = PseudoXVBZ_B { 380, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 208, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #380 = PseudoXVBZ { 379, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 208, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #379 = PseudoXVBNZ_W { 378, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 208, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #378 = PseudoXVBNZ_H { 377, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 208, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #377 = PseudoXVBNZ_D { 376, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 208, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #376 = PseudoXVBNZ_B { 375, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 208, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #375 = PseudoXVBNZ { 374, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 206, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #374 = PseudoVREPLI_W { 373, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 206, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #373 = PseudoVREPLI_H { 372, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 206, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #372 = PseudoVREPLI_D { 371, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 206, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #371 = PseudoVREPLI_B { 370, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 204, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #370 = PseudoVBZ_W { 369, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 204, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #369 = PseudoVBZ_H { 368, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 204, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #368 = PseudoVBZ_D { 367, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 204, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #367 = PseudoVBZ_B { 366, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 204, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #366 = PseudoVBZ { 365, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 204, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #365 = PseudoVBNZ_W { 364, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 204, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #364 = PseudoVBNZ_H { 363, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 204, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #363 = PseudoVBNZ_D { 362, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 204, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #362 = PseudoVBNZ_B { 361, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 204, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #361 = PseudoVBNZ { 360, 0, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #360 = PseudoUNIMP { 359, 1, 0, 4, 0, 1, 0, LoongArchImpOpBase + 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #359 = PseudoTAIL_MEDIUM { 358, 1, 0, 4, 0, 1, 0, LoongArchImpOpBase + 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #358 = PseudoTAIL_LARGE { 357, 1, 0, 4, 0, 1, 0, LoongArchImpOpBase + 2, 203, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #357 = PseudoTAILIndirect { 356, 2, 0, 4, 0, 1, 0, LoongArchImpOpBase + 2, 164, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #356 = PseudoTAIL36 { 355, 1, 0, 4, 0, 1, 0, LoongArchImpOpBase + 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #355 = PseudoTAIL { 354, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 178, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #354 = PseudoST_CFR { 353, 0, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #353 = PseudoRET { 352, 7, 2, 44, 0, 0, 0, LoongArchImpOpBase + 0, 196, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #352 = PseudoMaskedCmpXchg32 { 351, 6, 2, 36, 0, 0, 0, LoongArchImpOpBase + 0, 167, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #351 = PseudoMaskedAtomicSwap32 { 350, 7, 3, 48, 0, 0, 0, LoongArchImpOpBase + 0, 189, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #350 = PseudoMaskedAtomicLoadUMin32 { 349, 7, 3, 48, 0, 0, 0, LoongArchImpOpBase + 0, 189, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #349 = PseudoMaskedAtomicLoadUMax32 { 348, 6, 2, 36, 0, 0, 0, LoongArchImpOpBase + 0, 167, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #348 = PseudoMaskedAtomicLoadSub32 { 347, 6, 2, 36, 0, 0, 0, LoongArchImpOpBase + 0, 167, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #347 = PseudoMaskedAtomicLoadNand32 { 346, 8, 3, 56, 0, 0, 0, LoongArchImpOpBase + 0, 181, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #346 = PseudoMaskedAtomicLoadMin32 { 345, 8, 3, 56, 0, 0, 0, LoongArchImpOpBase + 0, 181, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #345 = PseudoMaskedAtomicLoadMax32 { 344, 6, 2, 36, 0, 0, 0, LoongArchImpOpBase + 0, 167, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #344 = PseudoMaskedAtomicLoadAdd32 { 343, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #343 = PseudoLI_W { 342, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #342 = PseudoLI_D { 341, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 178, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #341 = PseudoLD_CFR { 340, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #340 = PseudoLA_TLS_LE { 339, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 175, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #339 = PseudoLA_TLS_LD_LARGE { 338, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #338 = PseudoLA_TLS_LD { 337, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 175, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #337 = PseudoLA_TLS_IE_LARGE { 336, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #336 = PseudoLA_TLS_IE { 335, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 175, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #335 = PseudoLA_TLS_GD_LARGE { 334, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #334 = PseudoLA_TLS_GD { 333, 3, 1, 4, 0, 0, 2, LoongArchImpOpBase + 6, 175, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call), 0x0ULL }, // Inst #333 = PseudoLA_TLS_DESC_PC_LARGE { 332, 2, 1, 4, 0, 0, 1, LoongArchImpOpBase + 3, 164, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #332 = PseudoLA_TLS_DESC_PC { 331, 3, 1, 4, 0, 0, 1, LoongArchImpOpBase + 3, 175, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #331 = PseudoLA_TLS_DESC_ABS_LARGE { 330, 2, 1, 4, 0, 0, 1, LoongArchImpOpBase + 3, 164, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #330 = PseudoLA_TLS_DESC_ABS { 329, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 175, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #329 = PseudoLA_PCREL_LARGE { 328, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #328 = PseudoLA_PCREL { 327, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 175, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #327 = PseudoLA_GOT_LARGE { 326, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #326 = PseudoLA_GOT { 325, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 175, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #325 = PseudoLA_ABS_LARGE { 324, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #324 = PseudoLA_ABS { 323, 2, 0, 4, 0, 1, 0, LoongArchImpOpBase + 2, 164, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #323 = PseudoJIRL_TAIL { 322, 2, 0, 4, 0, 0, 1, LoongArchImpOpBase + 3, 164, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call), 0x0ULL }, // Inst #322 = PseudoJIRL_CALL { 321, 3, 1, 4, 0, 1, 1, LoongArchImpOpBase + 4, 175, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call), 0x0ULL }, // Inst #321 = PseudoDESC_CALL { 320, 2, 1, 12, 0, 0, 0, LoongArchImpOpBase + 0, 173, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #320 = PseudoCopyCFR { 319, 6, 2, 36, 0, 0, 0, LoongArchImpOpBase + 0, 167, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #319 = PseudoCmpXchg64 { 318, 6, 2, 36, 0, 0, 0, LoongArchImpOpBase + 0, 167, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #318 = PseudoCmpXchg32 { 317, 1, 0, 4, 0, 0, 1, LoongArchImpOpBase + 3, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call), 0x0ULL }, // Inst #317 = PseudoCALL_MEDIUM { 316, 1, 0, 4, 0, 0, 1, LoongArchImpOpBase + 3, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call), 0x0ULL }, // Inst #316 = PseudoCALL_LARGE { 315, 1, 0, 4, 0, 0, 1, LoongArchImpOpBase + 3, 166, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call), 0x0ULL }, // Inst #315 = PseudoCALLIndirect { 314, 1, 0, 4, 0, 0, 1, LoongArchImpOpBase + 3, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call), 0x0ULL }, // Inst #314 = PseudoCALL36 { 313, 1, 0, 4, 0, 0, 1, LoongArchImpOpBase + 3, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call), 0x0ULL }, // Inst #313 = PseudoCALL { 312, 1, 0, 4, 0, 1, 0, LoongArchImpOpBase + 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #312 = PseudoB_TAIL { 311, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #311 = PseudoBRIND { 310, 1, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #310 = PseudoBR { 309, 5, 2, 24, 0, 0, 0, LoongArchImpOpBase + 0, 156, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #309 = PseudoAtomicSwap32 { 308, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #308 = PseudoAtomicStoreW { 307, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #307 = PseudoAtomicStoreD { 306, 5, 2, 24, 0, 0, 0, LoongArchImpOpBase + 0, 156, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #306 = PseudoAtomicLoadXor32 { 305, 5, 2, 24, 0, 0, 0, LoongArchImpOpBase + 0, 156, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #305 = PseudoAtomicLoadSub32 { 304, 5, 2, 24, 0, 0, 0, LoongArchImpOpBase + 0, 156, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #304 = PseudoAtomicLoadOr32 { 303, 5, 2, 24, 0, 0, 0, LoongArchImpOpBase + 0, 156, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #303 = PseudoAtomicLoadNand64 { 302, 5, 2, 24, 0, 0, 0, LoongArchImpOpBase + 0, 156, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #302 = PseudoAtomicLoadNand32 { 301, 5, 2, 24, 0, 0, 0, LoongArchImpOpBase + 0, 156, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #301 = PseudoAtomicLoadAnd32 { 300, 5, 2, 24, 0, 0, 0, LoongArchImpOpBase + 0, 156, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #300 = PseudoAtomicLoadAdd32 { 299, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 152, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #299 = PseudoAddTPRel_W { 298, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 152, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #298 = PseudoAddTPRel_D { 297, 2, 0, 4, 0, 1, 1, LoongArchImpOpBase + 0, 21, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #297 = ADJCALLSTACKUP { 296, 2, 0, 4, 0, 1, 1, LoongArchImpOpBase + 0, 21, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #296 = ADJCALLSTACKDOWN { 295, 4, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 148, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #295 = G_UBFX { 294, 4, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 148, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #294 = G_SBFX { 293, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #293 = G_VECREDUCE_UMIN { 292, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #292 = G_VECREDUCE_UMAX { 291, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #291 = G_VECREDUCE_SMIN { 290, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #290 = G_VECREDUCE_SMAX { 289, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #289 = G_VECREDUCE_XOR { 288, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #288 = G_VECREDUCE_OR { 287, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #287 = G_VECREDUCE_AND { 286, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #286 = G_VECREDUCE_MUL { 285, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #285 = G_VECREDUCE_ADD { 284, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #284 = G_VECREDUCE_FMINIMUM { 283, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #283 = G_VECREDUCE_FMAXIMUM { 282, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #282 = G_VECREDUCE_FMIN { 281, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #281 = G_VECREDUCE_FMAX { 280, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #280 = G_VECREDUCE_FMUL { 279, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #279 = G_VECREDUCE_FADD { 278, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 131, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #278 = G_VECREDUCE_SEQ_FMUL { 277, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 131, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #277 = G_VECREDUCE_SEQ_FADD { 276, 1, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 1, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #276 = G_UBSANTRAP { 275, 0, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 1, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #275 = G_DEBUGTRAP { 274, 0, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 1, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #274 = G_TRAP { 273, 3, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 58, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #273 = G_BZERO { 272, 4, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 144, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #272 = G_MEMSET { 271, 4, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 144, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #271 = G_MEMMOVE { 270, 3, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 131, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #270 = G_MEMCPY_INLINE { 269, 4, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 144, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #269 = G_MEMCPY { 268, 2, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 142, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #268 = G_WRITE_REGISTER { 267, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #267 = G_READ_REGISTER { 266, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #266 = G_STRICT_FLDEXP { 265, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #265 = G_STRICT_FSQRT { 264, 4, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 46, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #264 = G_STRICT_FMA { 263, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #263 = G_STRICT_FREM { 262, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #262 = G_STRICT_FDIV { 261, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #261 = G_STRICT_FMUL { 260, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #260 = G_STRICT_FSUB { 259, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #259 = G_STRICT_FADD { 258, 1, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #258 = G_STACKRESTORE { 257, 1, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #257 = G_STACKSAVE { 256, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 69, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #256 = G_DYN_STACKALLOC { 255, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #255 = G_JUMP_TABLE { 254, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #254 = G_BLOCK_ADDR { 253, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #253 = G_ADDRSPACE_CAST { 252, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #252 = G_FNEARBYINT { 251, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #251 = G_FRINT { 250, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #250 = G_FFLOOR { 249, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #249 = G_FSQRT { 248, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #248 = G_FTANH { 247, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #247 = G_FSINH { 246, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #246 = G_FCOSH { 245, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #245 = G_FATAN { 244, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #244 = G_FASIN { 243, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #243 = G_FACOS { 242, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #242 = G_FTAN { 241, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #241 = G_FSIN { 240, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #240 = G_FCOS { 239, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #239 = G_FCEIL { 238, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #238 = G_BITREVERSE { 237, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #237 = G_BSWAP { 236, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #236 = G_CTPOP { 235, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #235 = G_CTLZ_ZERO_UNDEF { 234, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #234 = G_CTLZ { 233, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #233 = G_CTTZ_ZERO_UNDEF { 232, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #232 = G_CTTZ { 231, 4, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 138, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #231 = G_VECTOR_COMPRESS { 230, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #230 = G_SPLAT_VECTOR { 229, 4, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 134, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #229 = G_SHUFFLE_VECTOR { 228, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 131, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #228 = G_EXTRACT_VECTOR_ELT { 227, 4, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 127, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #227 = G_INSERT_VECTOR_ELT { 226, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 40, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #226 = G_EXTRACT_SUBVECTOR { 225, 4, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 63, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #225 = G_INSERT_SUBVECTOR { 224, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #224 = G_VSCALE { 223, 3, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 124, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #223 = G_BRJT { 222, 1, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #222 = G_BR { 221, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #221 = G_LLROUND { 220, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #220 = G_LROUND { 219, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #219 = G_ABS { 218, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #218 = G_UMAX { 217, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #217 = G_UMIN { 216, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #216 = G_SMAX { 215, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #215 = G_SMIN { 214, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #214 = G_PTRMASK { 213, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #213 = G_PTR_ADD { 212, 0, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 1, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #212 = G_RESET_FPMODE { 211, 1, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #211 = G_SET_FPMODE { 210, 1, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #210 = G_GET_FPMODE { 209, 0, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 1, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #209 = G_RESET_FPENV { 208, 1, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #208 = G_SET_FPENV { 207, 1, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #207 = G_GET_FPENV { 206, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #206 = G_FMAXIMUM { 205, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #205 = G_FMINIMUM { 204, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #204 = G_FMAXNUM_IEEE { 203, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #203 = G_FMINNUM_IEEE { 202, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #202 = G_FMAXNUM { 201, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #201 = G_FMINNUM { 200, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #200 = G_FCANONICALIZE { 199, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 98, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #199 = G_IS_FPCLASS { 198, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #198 = G_FCOPYSIGN { 197, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #197 = G_FABS { 196, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #196 = G_UITOFP { 195, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #195 = G_SITOFP { 194, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #194 = G_FPTOUI { 193, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #193 = G_FPTOSI { 192, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #192 = G_FPTRUNC { 191, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #191 = G_FPEXT { 190, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #190 = G_FNEG { 189, 3, 2, 0, 0, 0, 0, LoongArchImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #189 = G_FFREXP { 188, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #188 = G_FLDEXP { 187, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #187 = G_FLOG10 { 186, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #186 = G_FLOG2 { 185, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #185 = G_FLOG { 184, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #184 = G_FEXP10 { 183, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #183 = G_FEXP2 { 182, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #182 = G_FEXP { 181, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #181 = G_FPOWI { 180, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #180 = G_FPOW { 179, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #179 = G_FREM { 178, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #178 = G_FDIV { 177, 4, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 46, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #177 = G_FMAD { 176, 4, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 46, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #176 = G_FMA { 175, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #175 = G_FMUL { 174, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #174 = G_FSUB { 173, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #173 = G_FADD { 172, 4, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #172 = G_UDIVFIXSAT { 171, 4, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #171 = G_SDIVFIXSAT { 170, 4, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #170 = G_UDIVFIX { 169, 4, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #169 = G_SDIVFIX { 168, 4, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #168 = G_UMULFIXSAT { 167, 4, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #167 = G_SMULFIXSAT { 166, 4, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #166 = G_UMULFIX { 165, 4, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #165 = G_SMULFIX { 164, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #164 = G_SSHLSAT { 163, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #163 = G_USHLSAT { 162, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #162 = G_SSUBSAT { 161, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #161 = G_USUBSAT { 160, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #160 = G_SADDSAT { 159, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #159 = G_UADDSAT { 158, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #158 = G_SMULH { 157, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #157 = G_UMULH { 156, 4, 2, 0, 0, 0, 0, LoongArchImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #156 = G_SMULO { 155, 4, 2, 0, 0, 0, 0, LoongArchImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #155 = G_UMULO { 154, 5, 2, 0, 0, 0, 0, LoongArchImpOpBase + 0, 115, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #154 = G_SSUBE { 153, 4, 2, 0, 0, 0, 0, LoongArchImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #153 = G_SSUBO { 152, 5, 2, 0, 0, 0, 0, LoongArchImpOpBase + 0, 115, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #152 = G_SADDE { 151, 4, 2, 0, 0, 0, 0, LoongArchImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #151 = G_SADDO { 150, 5, 2, 0, 0, 0, 0, LoongArchImpOpBase + 0, 115, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #150 = G_USUBE { 149, 4, 2, 0, 0, 0, 0, LoongArchImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #149 = G_USUBO { 148, 5, 2, 0, 0, 0, 0, LoongArchImpOpBase + 0, 115, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #148 = G_UADDE { 147, 4, 2, 0, 0, 0, 0, LoongArchImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #147 = G_UADDO { 146, 4, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #146 = G_SELECT { 145, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 112, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #145 = G_UCMP { 144, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 112, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #144 = G_SCMP { 143, 4, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 108, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #143 = G_FCMP { 142, 4, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 108, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #142 = G_ICMP { 141, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #141 = G_ROTL { 140, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #140 = G_ROTR { 139, 4, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 104, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #139 = G_FSHR { 138, 4, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 104, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #138 = G_FSHL { 137, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #137 = G_ASHR { 136, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #136 = G_LSHR { 135, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #135 = G_SHL { 134, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #134 = G_ZEXT { 133, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 40, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #133 = G_SEXT_INREG { 132, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #132 = G_SEXT { 131, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 98, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #131 = G_VAARG { 130, 1, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #130 = G_VASTART { 129, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #129 = G_FCONSTANT { 128, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #128 = G_CONSTANT { 127, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #127 = G_TRUNC { 126, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #126 = G_ANYEXT { 125, 1, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #125 = G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS { 124, 1, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #124 = G_INTRINSIC_CONVERGENT { 123, 1, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #123 = G_INTRINSIC_W_SIDE_EFFECTS { 122, 1, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #122 = G_INTRINSIC { 121, 0, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 1, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #121 = G_INVOKE_REGION_START { 120, 1, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #120 = G_BRINDIRECT { 119, 2, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #119 = G_BRCOND { 118, 4, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 94, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #118 = G_PREFETCH { 117, 2, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 21, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #117 = G_FENCE { 116, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #116 = G_ATOMICRMW_UDEC_WRAP { 115, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #115 = G_ATOMICRMW_UINC_WRAP { 114, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #114 = G_ATOMICRMW_FMIN { 113, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #113 = G_ATOMICRMW_FMAX { 112, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #112 = G_ATOMICRMW_FSUB { 111, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #111 = G_ATOMICRMW_FADD { 110, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #110 = G_ATOMICRMW_UMIN { 109, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #109 = G_ATOMICRMW_UMAX { 108, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #108 = G_ATOMICRMW_MIN { 107, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #107 = G_ATOMICRMW_MAX { 106, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #106 = G_ATOMICRMW_XOR { 105, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #105 = G_ATOMICRMW_OR { 104, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #104 = G_ATOMICRMW_NAND { 103, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #103 = G_ATOMICRMW_AND { 102, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #102 = G_ATOMICRMW_SUB { 101, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #101 = G_ATOMICRMW_ADD { 100, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #100 = G_ATOMICRMW_XCHG { 99, 4, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #99 = G_ATOMIC_CMPXCHG { 98, 5, 2, 0, 0, 0, 0, LoongArchImpOpBase + 0, 82, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #98 = G_ATOMIC_CMPXCHG_WITH_SUCCESS { 97, 5, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 77, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #97 = G_INDEXED_STORE { 96, 2, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #96 = G_STORE { 95, 5, 2, 0, 0, 0, 0, LoongArchImpOpBase + 0, 72, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #95 = G_INDEXED_ZEXTLOAD { 94, 5, 2, 0, 0, 0, 0, LoongArchImpOpBase + 0, 72, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #94 = G_INDEXED_SEXTLOAD { 93, 5, 2, 0, 0, 0, 0, LoongArchImpOpBase + 0, 72, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #93 = G_INDEXED_LOAD { 92, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #92 = G_ZEXTLOAD { 91, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #91 = G_SEXTLOAD { 90, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #90 = G_LOAD { 89, 1, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #89 = G_READSTEADYCOUNTER { 88, 1, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #88 = G_READCYCLECOUNTER { 87, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #87 = G_INTRINSIC_ROUNDEVEN { 86, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #86 = G_INTRINSIC_LLRINT { 85, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #85 = G_INTRINSIC_LRINT { 84, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #84 = G_INTRINSIC_ROUND { 83, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #83 = G_INTRINSIC_TRUNC { 82, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 69, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #82 = G_INTRINSIC_FPTRUNC_ROUND { 81, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #81 = G_CONSTANT_FOLD_BARRIER { 80, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #80 = G_FREEZE { 79, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #79 = G_BITCAST { 78, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #78 = G_INTTOPTR { 77, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #77 = G_PTRTOINT { 76, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #76 = G_CONCAT_VECTORS { 75, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #75 = G_BUILD_VECTOR_TRUNC { 74, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #74 = G_BUILD_VECTOR { 73, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #73 = G_MERGE_VALUES { 72, 4, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 63, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #72 = G_INSERT { 71, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #71 = G_UNMERGE_VALUES { 70, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 58, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #70 = G_EXTRACT { 69, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #69 = G_CONSTANT_POOL { 68, 5, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 53, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #68 = G_PTRAUTH_GLOBAL_VALUE { 67, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #67 = G_GLOBAL_VALUE { 66, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #66 = G_FRAME_INDEX { 65, 1, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #65 = G_PHI { 64, 1, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #64 = G_IMPLICIT_DEF { 63, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #63 = G_XOR { 62, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #62 = G_OR { 61, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #61 = G_AND { 60, 4, 2, 0, 0, 0, 0, LoongArchImpOpBase + 0, 46, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #60 = G_UDIVREM { 59, 4, 2, 0, 0, 0, 0, LoongArchImpOpBase + 0, 46, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #59 = G_SDIVREM { 58, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #58 = G_UREM { 57, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #57 = G_SREM { 56, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #56 = G_UDIV { 55, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #55 = G_SDIV { 54, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #54 = G_MUL { 53, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #53 = G_SUB { 52, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #52 = G_ADD { 51, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 40, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #51 = G_ASSERT_ALIGN { 50, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 40, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #50 = G_ASSERT_ZEXT { 49, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 40, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #49 = G_ASSERT_SEXT { 48, 1, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #48 = CONVERGENCECTRL_GLUE { 47, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 13, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #47 = CONVERGENCECTRL_LOOP { 46, 1, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #46 = CONVERGENCECTRL_ANCHOR { 45, 1, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #45 = CONVERGENCECTRL_ENTRY { 44, 1, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL }, // Inst #44 = JUMP_TABLE_DEBUG_INFO { 43, 0, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #43 = MEMBARRIER { 42, 0, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #42 = FAKE_USE { 41, 0, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #41 = ICALL_BRANCH_FUNNEL { 40, 3, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 37, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #40 = PATCHABLE_TYPED_EVENT_CALL { 39, 2, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 35, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #39 = PATCHABLE_EVENT_CALL { 38, 0, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #38 = PATCHABLE_TAIL_CALL { 37, 0, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #37 = PATCHABLE_FUNCTION_EXIT { 36, 0, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #36 = PATCHABLE_RET { 35, 0, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #35 = PATCHABLE_FUNCTION_ENTER { 34, 0, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #34 = PATCHABLE_OP { 33, 1, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #33 = FAULTING_OP { 32, 2, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 33, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #32 = LOCAL_ESCAPE { 31, 0, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #31 = STATEPOINT { 30, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 30, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #30 = PREALLOCATED_ARG { 29, 1, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #29 = PREALLOCATED_SETUP { 28, 1, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 29, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x0ULL }, // Inst #28 = LOAD_STACK_GUARD { 27, 6, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 23, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #27 = PATCHPOINT { 26, 0, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #26 = FENTRY_CALL { 25, 2, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 21, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #25 = STACKMAP { 24, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 19, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL }, // Inst #24 = ARITH_FENCE { 23, 4, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 15, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #23 = PSEUDO_PROBE { 22, 1, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL }, // Inst #22 = LIFETIME_END { 21, 1, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL }, // Inst #21 = LIFETIME_START { 20, 0, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #20 = BUNDLE { 19, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 13, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // Inst #19 = COPY { 18, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 13, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // Inst #18 = REG_SEQUENCE { 17, 1, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL }, // Inst #17 = DBG_LABEL { 16, 0, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #16 = DBG_PHI { 15, 0, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #15 = DBG_INSTR_REF { 14, 0, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #14 = DBG_VALUE_LIST { 13, 0, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #13 = DBG_VALUE { 12, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // Inst #12 = COPY_TO_REGCLASS { 11, 4, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 9, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #11 = SUBREG_TO_REG { 10, 1, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // Inst #10 = IMPLICIT_DEF { 9, 4, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 5, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #9 = INSERT_SUBREG { 8, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 2, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #8 = EXTRACT_SUBREG { 7, 0, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #7 = KILL { 6, 1, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // Inst #6 = ANNOTATION_LABEL { 5, 1, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // Inst #5 = GC_LABEL { 4, 1, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // Inst #4 = EH_LABEL { 3, 1, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // Inst #3 = CFI_INSTRUCTION { 2, 0, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2 = INLINEASM_BR { 1, 0, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #1 = INLINEASM { 0, 1, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #0 = PHI }, { /* 0 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 1 */ /* 1 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, /* 2 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, /* 5 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, /* 9 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, /* 13 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 15 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, /* 19 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) }, /* 21 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, /* 23 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, /* 29 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, /* 30 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, /* 33 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, /* 35 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 37 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 40 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 }, /* 43 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, /* 46 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, /* 50 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, /* 51 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 53 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, /* 58 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 }, /* 61 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, /* 63 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 }, /* 67 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, /* 69 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, /* 72 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 77 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 82 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, /* 87 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, /* 91 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, /* 94 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, /* 98 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 101 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, /* 104 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, /* 108 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, /* 112 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, /* 115 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, /* 120 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 }, /* 124 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, /* 127 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, /* 131 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, /* 134 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 138 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, /* 142 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, /* 144 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 }, /* 148 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, /* 152 */ { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 156 */ { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 161 */ { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 164 */ { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 166 */ { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 167 */ { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 173 */ { LoongArch::CFRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::CFRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 175 */ { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 178 */ { LoongArch::CFRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 181 */ { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 189 */ { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 196 */ { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 203 */ { LoongArch::GPRTRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 204 */ { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::LSX128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 206 */ { LoongArch::LSX128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 208 */ { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::LASX256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 210 */ { LoongArch::LASX256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::LASX256RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 214 */ { LoongArch::LASX256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 216 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 218 */ { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 221 */ { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 224 */ { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 226 */ { LoongArch::CFRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 228 */ { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 233 */ { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 237 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 240 */ { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 243 */ { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 247 */ { LoongArch::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 249 */ { LoongArch::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 251 */ { LoongArch::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 254 */ { LoongArch::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 257 */ { LoongArch::CFRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 260 */ { LoongArch::CFRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 263 */ { LoongArch::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 265 */ { LoongArch::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 267 */ { LoongArch::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 270 */ { LoongArch::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 273 */ { LoongArch::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 276 */ { LoongArch::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 279 */ { LoongArch::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 283 */ { LoongArch::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 287 */ { LoongArch::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::CFRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 291 */ { LoongArch::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::CFRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 295 */ { LoongArch::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::CFRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 297 */ { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::CFRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 299 */ { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FCSRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 301 */ { LoongArch::CFRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 303 */ { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 305 */ { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 307 */ { LoongArch::CFRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 309 */ { LoongArch::FCSRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 311 */ { LoongArch::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 314 */ { LoongArch::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 316 */ { LoongArch::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 318 */ { LoongArch::SCRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 320 */ { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::SCRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 322 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 325 */ { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 328 */ { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 332 */ { LoongArch::CFRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 333 */ { LoongArch::LSX128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::LSX128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::LSX128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 336 */ { LoongArch::LSX128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::LSX128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 339 */ { LoongArch::LSX128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::LSX128RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { LoongArch::LSX128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 343 */ { LoongArch::LSX128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::LSX128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::LSX128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::LSX128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 347 */ { LoongArch::LSX128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::LSX128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 349 */ { LoongArch::LASX256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::LASX256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 351 */ { LoongArch::LSX128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::LSX128RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { LoongArch::LSX128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::LSX128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 355 */ { LoongArch::LSX128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::LSX128RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 359 */ { LoongArch::LSX128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 362 */ { LoongArch::LSX128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 365 */ { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::LSX128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 368 */ { LoongArch::LSX128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 370 */ { LoongArch::LSX128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::LSX128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 373 */ { LoongArch::CFRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::LSX128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 375 */ { LoongArch::LSX128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 379 */ { LoongArch::LASX256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::LASX256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::LASX256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 382 */ { LoongArch::LASX256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::LASX256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 385 */ { LoongArch::LASX256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::LASX256RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { LoongArch::LASX256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 389 */ { LoongArch::LASX256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::LASX256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::LASX256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::LASX256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 393 */ { LoongArch::LASX256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::LASX256RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { LoongArch::LASX256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::LASX256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 397 */ { LoongArch::LASX256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 400 */ { LoongArch::LASX256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 403 */ { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::LASX256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 406 */ { LoongArch::LASX256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 408 */ { LoongArch::LASX256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::LASX256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 411 */ { LoongArch::CFRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::LASX256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 413 */ { LoongArch::LASX256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }, { /* 0 */ /* 0 */ LoongArch::R3, LoongArch::R3, /* 2 */ LoongArch::R3, /* 3 */ LoongArch::R1, /* 4 */ LoongArch::R4, LoongArch::R4, /* 6 */ LoongArch::R1, LoongArch::R4, } }; #ifdef __GNUC__ #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Woverlength-strings" #endif extern const char LoongArchInstrNameData[] = { /* 0 */ "G_FLOG10\0" /* 9 */ "G_FEXP10\0" /* 18 */ "JISCR0\0" /* 25 */ "JISCR1\0" /* 32 */ "PseudoMaskedAtomicLoadSub32\0" /* 60 */ "PseudoAtomicLoadSub32\0" /* 82 */ "PseudoMaskedAtomicLoadAdd32\0" /* 110 */ "PseudoAtomicLoadAdd32\0" /* 132 */ "PseudoAtomicLoadAnd32\0" /* 154 */ "PseudoMaskedAtomicLoadNand32\0" /* 183 */ "PseudoAtomicLoadNand32\0" /* 206 */ "PseudoMaskedCmpXchg32\0" /* 228 */ "PseudoCmpXchg32\0" /* 244 */ "PseudoMaskedAtomicLoadUMin32\0" /* 273 */ "PseudoMaskedAtomicLoadMin32\0" /* 301 */ "PseudoMaskedAtomicSwap32\0" /* 326 */ "PseudoAtomicSwap32\0" /* 345 */ "PseudoAtomicLoadOr32\0" /* 366 */ "PseudoAtomicLoadXor32\0" /* 388 */ "PseudoMaskedAtomicLoadUMax32\0" /* 417 */ "PseudoMaskedAtomicLoadMax32\0" /* 445 */ "G_FLOG2\0" /* 453 */ "G_FEXP2\0" /* 461 */ "MOVFR2GR_S_64\0" /* 475 */ "MOVGR2FR_W_64\0" /* 489 */ "PseudoAtomicLoadNand64\0" /* 512 */ "PseudoCmpXchg64\0" /* 528 */ "PseudoTAIL36\0" /* 541 */ "PseudoCALL36\0" /* 554 */ "G_FMA\0" /* 560 */ "G_STRICT_FMA\0" /* 573 */ "BITREV_4B\0" /* 583 */ "BITREV_8B\0" /* 593 */ "INVTLB\0" /* 600 */ "G_FSUB\0" /* 607 */ "G_STRICT_FSUB\0" /* 621 */ "G_ATOMICRMW_FSUB\0" /* 638 */ "G_SUB\0" /* 644 */ "G_ATOMICRMW_SUB\0" /* 660 */ "XVREPLVE0_B\0" /* 672 */ "XVADDA_B\0" /* 681 */ "X86SRA_B\0" /* 690 */ "XVSRA_B\0" /* 698 */ "AMADD__DB_B\0" /* 710 */ "AMSWAP__DB_B\0" /* 723 */ "AMCAS__DB_B\0" /* 735 */ "X86SUB_B\0" /* 744 */ "XVMSUB_B\0" /* 753 */ "XVSSUB_B\0" /* 762 */ "XVSUB_B\0" /* 770 */ "X86SBC_B\0" /* 779 */ "X86ADC_B\0" /* 788 */ "X86DEC_B\0" /* 797 */ "X86INC_B\0" /* 806 */ "X86ADD_B\0" /* 815 */ "AMADD_B\0" /* 823 */ "XVMADD_B\0" /* 832 */ "XVSADD_B\0" /* 841 */ "XVADD_B\0" /* 849 */ "LD_B\0" /* 854 */ "X86AND_B\0" /* 863 */ "XVPACKOD_B\0" /* 874 */ "XVPICKOD_B\0" /* 885 */ "XVMOD_B\0" /* 893 */ "IOCSRRD_B\0" /* 903 */ "XVABSD_B\0" /* 912 */ "VEXT2XV_D_B\0" /* 924 */ "LDLE_B\0" /* 931 */ "XVSLE_B\0" /* 939 */ "STLE_B\0" /* 946 */ "XVREPLVE_B\0" /* 957 */ "XVSHUF_B\0" /* 966 */ "XVNEG_B\0" /* 974 */ "XVAVG_B\0" /* 982 */ "XVMUH_B\0" /* 990 */ "XVILVH_B\0" /* 999 */ "XVSUBWOD_H_B\0" /* 1012 */ "XVMADDWOD_H_B\0" /* 1026 */ "XVADDWOD_H_B\0" /* 1039 */ "XVMULWOD_H_B\0" /* 1052 */ "XVEXTH_H_B\0" /* 1063 */ "XVSLLWIL_H_B\0" /* 1076 */ "XVSUBWEV_H_B\0" /* 1089 */ "XVMADDWEV_H_B\0" /* 1103 */ "XVADDWEV_H_B\0" /* 1116 */ "XVMULWEV_H_B\0" /* 1129 */ "VEXT2XV_H_B\0" /* 1141 */ "XVHSUBW_H_B\0" /* 1153 */ "XVHADDW_H_B\0" /* 1165 */ "XVSHUF4I_B\0" /* 1176 */ "X86SRAI_B\0" /* 1186 */ "XVSRAI_B\0" /* 1195 */ "XVANDI_B\0" /* 1204 */ "XVSLEI_B\0" /* 1213 */ "XVREPL128VEI_B\0" /* 1228 */ "VREPLVEI_B\0" /* 1239 */ "X86RCLI_B\0" /* 1249 */ "XVBITSELI_B\0" /* 1261 */ "X86SLLI_B\0" /* 1271 */ "XVSLLI_B\0" /* 1280 */ "PseudoXVREPLI_B\0" /* 1296 */ "PseudoVREPLI_B\0" /* 1311 */ "X86SRLI_B\0" /* 1321 */ "XVSRLI_B\0" /* 1330 */ "X86ROTLI_B\0" /* 1341 */ "XVMINI_B\0" /* 1350 */ "XVFRSTPI_B\0" /* 1361 */ "XVSEQI_B\0" /* 1370 */ "XVSRARI_B\0" /* 1380 */ "X86RCRI_B\0" /* 1390 */ "XVBITCLRI_B\0" /* 1402 */ "XVSRLRI_B\0" /* 1412 */ "XVNORI_B\0" /* 1421 */ "XVORI_B\0" /* 1429 */ "XVXORI_B\0" /* 1438 */ "X86ROTRI_B\0" /* 1449 */ "XVROTRI_B\0" /* 1459 */ "XVBITSETI_B\0" /* 1471 */ "XVSLTI_B\0" /* 1480 */ "XVBITREVI_B\0" /* 1492 */ "XVMAXI_B\0" /* 1501 */ "X86RCL_B\0" /* 1510 */ "X86SLL_B\0" /* 1519 */ "XVSLL_B\0" /* 1527 */ "XVLDREPL_B\0" /* 1538 */ "X86SRL_B\0" /* 1547 */ "XVSRL_B\0" /* 1555 */ "X86ROTL_B\0" /* 1565 */ "X86MUL_B\0" /* 1574 */ "XVMUL_B\0" /* 1582 */ "XVILVL_B\0" /* 1591 */ "XVSTELM_B\0" /* 1601 */ "XVMIN_B\0" /* 1609 */ "XVCLO_B\0" /* 1617 */ "AMSWAP_B\0" /* 1626 */ "XVFRSTP_B\0" /* 1636 */ "XVSEQ_B\0" /* 1644 */ "XVSRAR_B\0" /* 1653 */ "X86RCR_B\0" /* 1662 */ "VPICKVE2GR_B\0" /* 1675 */ "XVAVGR_B\0" /* 1684 */ "XVBITCLR_B\0" /* 1695 */ "XVSRLR_B\0" /* 1704 */ "X86OR_B\0" /* 1712 */ "X86XOR_B\0" /* 1721 */ "X86ROTR_B\0" /* 1731 */ "XVROTR_B\0" /* 1740 */ "XVREPLGR2VR_B\0" /* 1754 */ "PseudoXVINSGR2VR_B\0" /* 1773 */ "IOCSRWR_B\0" /* 1783 */ "AMCAS_B\0" /* 1791 */ "XVEXTRINS_B\0" /* 1803 */ "XVSAT_B\0" /* 1811 */ "XVBITSET_B\0" /* 1822 */ "LDGT_B\0" /* 1829 */ "STGT_B\0" /* 1836 */ "XVSLT_B\0" /* 1844 */ "XVPCNT_B\0" /* 1853 */ "ST_B\0" /* 1858 */ "XVMADDWOD_H_BU_B\0" /* 1875 */ "XVADDWOD_H_BU_B\0" /* 1891 */ "XVMULWOD_H_BU_B\0" /* 1907 */ "XVMADDWEV_H_BU_B\0" /* 1924 */ "XVADDWEV_H_BU_B\0" /* 1940 */ "XVMULWEV_H_BU_B\0" /* 1956 */ "XVPACKEV_B\0" /* 1967 */ "XVPICKEV_B\0" /* 1978 */ "XVBITREV_B\0" /* 1989 */ "XVDIV_B\0" /* 1997 */ "XVSIGNCOV_B\0" /* 2009 */ "EXT_W_B\0" /* 2017 */ "VEXT2XV_W_B\0" /* 2029 */ "XVMAX_B\0" /* 2037 */ "LDX_B\0" /* 2043 */ "STX_B\0" /* 2049 */ "PseudoXVBZ_B\0" /* 2062 */ "PseudoVBZ_B\0" /* 2074 */ "XVMSKGEZ_B\0" /* 2085 */ "XVSETALLNEZ_B\0" /* 2099 */ "XVCLZ_B\0" /* 2107 */ "PseudoXVBNZ_B\0" /* 2121 */ "PseudoVBNZ_B\0" /* 2134 */ "XVMSKNZ_B\0" /* 2144 */ "XVSETANYEQZ_B\0" /* 2158 */ "XVMSKLTZ_B\0" /* 2169 */ "G_INTRINSIC\0" /* 2181 */ "G_FPTRUNC\0" /* 2191 */ "G_INTRINSIC_TRUNC\0" /* 2209 */ "G_TRUNC\0" /* 2217 */ "G_BUILD_VECTOR_TRUNC\0" /* 2238 */ "G_DYN_STACKALLOC\0" /* 2255 */ "PseudoLA_TLS_DESC_PC\0" /* 2276 */ "G_FMAD\0" /* 2283 */ "G_INDEXED_SEXTLOAD\0" /* 2302 */ "G_SEXTLOAD\0" /* 2313 */ "G_INDEXED_ZEXTLOAD\0" /* 2332 */ "G_ZEXTLOAD\0" /* 2343 */ "G_INDEXED_LOAD\0" /* 2358 */ "G_LOAD\0" /* 2365 */ "G_VECREDUCE_FADD\0" /* 2382 */ "G_FADD\0" /* 2389 */ "G_VECREDUCE_SEQ_FADD\0" /* 2410 */ "G_STRICT_FADD\0" /* 2424 */ "G_ATOMICRMW_FADD\0" /* 2441 */ "G_VECREDUCE_ADD\0" /* 2457 */ "G_ADD\0" /* 2463 */ "G_PTR_ADD\0" /* 2473 */ "G_ATOMICRMW_ADD\0" /* 2489 */ "PseudoLA_TLS_GD\0" /* 2505 */ "PRELD\0" /* 2511 */ "XVLD\0" /* 2516 */ "FCVT_D_LD\0" /* 2526 */ "PseudoLA_TLS_LD\0" /* 2542 */ "G_ATOMICRMW_NAND\0" /* 2559 */ "G_VECREDUCE_AND\0" /* 2575 */ "G_AND\0" /* 2581 */ "G_ATOMICRMW_AND\0" /* 2597 */ "LIFETIME_END\0" /* 2610 */ "PseudoBRIND\0" /* 2622 */ "G_BRCOND\0" /* 2631 */ "G_LLROUND\0" /* 2641 */ "G_LROUND\0" /* 2650 */ "G_INTRINSIC_ROUND\0" /* 2668 */ "G_INTRINSIC_FPTRUNC_ROUND\0" /* 2694 */ "LOAD_STACK_GUARD\0" /* 2711 */ "TLBRD\0" /* 2717 */ "GCSRRD\0" /* 2724 */ "XVREPLVE0_D\0" /* 2736 */ "XVINSVE0_D\0" /* 2747 */ "XVADDA_D\0" /* 2756 */ "XVFMINA_D\0" /* 2766 */ "X86SRA_D\0" /* 2775 */ "XVSRA_D\0" /* 2783 */ "XVFMAXA_D\0" /* 2793 */ "AMADD__DB_D\0" /* 2805 */ "AMAND__DB_D\0" /* 2817 */ "AMMIN__DB_D\0" /* 2829 */ "AMSWAP__DB_D\0" /* 2842 */ "AMOR__DB_D\0" /* 2853 */ "AMXOR__DB_D\0" /* 2865 */ "AMCAS__DB_D\0" /* 2877 */ "AMMAX__DB_D\0" /* 2889 */ "FSCALEB_D\0" /* 2899 */ "XVFLOGB_D\0" /* 2909 */ "X86SUB_D\0" /* 2918 */ "XVFSUB_D\0" /* 2927 */ "XVFMSUB_D\0" /* 2937 */ "XVFNMSUB_D\0" /* 2948 */ "XVMSUB_D\0" /* 2957 */ "XVSSUB_D\0" /* 2966 */ "XVSUB_D\0" /* 2974 */ "REVB_D\0" /* 2981 */ "X86SBC_D\0" /* 2990 */ "X86ADC_D\0" /* 2999 */ "X86DEC_D\0" /* 3008 */ "X86INC_D\0" /* 3017 */ "SC_D\0" /* 3022 */ "X86ADD_D\0" /* 3031 */ "XVFADD_D\0" /* 3040 */ "AMADD_D\0" /* 3048 */ "XVFMADD_D\0" /* 3058 */ "XVFNMADD_D\0" /* 3069 */ "XVMADD_D\0" /* 3078 */ "XVSADD_D\0" /* 3087 */ "XVADD_D\0" /* 3095 */ "FLD_D\0" /* 3101 */ "FCVT_LD_D\0" /* 3111 */ "X86AND_D\0" /* 3120 */ "AMAND_D\0" /* 3128 */ "XVPACKOD_D\0" /* 3139 */ "XVPICKOD_D\0" /* 3150 */ "XVMOD_D\0" /* 3158 */ "IOCSRRD_D\0" /* 3168 */ "XVABSD_D\0" /* 3177 */ "FCVT_UD_D\0" /* 3187 */ "XVFCMP_CLE_D\0" /* 3200 */ "FLDLE_D\0" /* 3208 */ "XVSLE_D\0" /* 3216 */ "XVFCMP_SLE_D\0" /* 3229 */ "ASRTLE_D\0" /* 3238 */ "FSTLE_D\0" /* 3246 */ "XVFCMP_CULE_D\0" /* 3260 */ "XVFCMP_SULE_D\0" /* 3274 */ "RDTIME_D\0" /* 3283 */ "XVFCMP_CNE_D\0" /* 3296 */ "XVFRINTRNE_D\0" /* 3309 */ "XVFCMP_SNE_D\0" /* 3322 */ "XVFCMP_CUNE_D\0" /* 3336 */ "XVFCMP_SUNE_D\0" /* 3350 */ "XVFRECIPE_D\0" /* 3362 */ "XVFRSQRTE_D\0" /* 3374 */ "XVPICKVE_D\0" /* 3385 */ "XVREPLVE_D\0" /* 3396 */ "XVFCMP_CAF_D\0" /* 3409 */ "XVFCMP_SAF_D\0" /* 3422 */ "XVSHUF_D\0" /* 3431 */ "FNEG_D\0" /* 3438 */ "XVNEG_D\0" /* 3446 */ "XVAVG_D\0" /* 3454 */ "MULH_D\0" /* 3461 */ "XVMUH_D\0" /* 3469 */ "REVH_D\0" /* 3476 */ "XVILVH_D\0" /* 3485 */ "ADDU12I_D\0" /* 3495 */ "LU32I_D\0" /* 3503 */ "LU52I_D\0" /* 3511 */ "XVSHUF4I_D\0" /* 3522 */ "ADDU16I_D\0" /* 3532 */ "X86SRAI_D\0" /* 3542 */ "XVSRAI_D\0" /* 3551 */ "ADDI_D\0" /* 3558 */ "XVSLEI_D\0" /* 3567 */ "XVREPL128VEI_D\0" /* 3582 */ "VREPLVEI_D\0" /* 3593 */ "X86RCLI_D\0" /* 3603 */ "XVHSELI_D\0" /* 3613 */ "X86SLLI_D\0" /* 3623 */ "XVSLLI_D\0" /* 3632 */ "PseudoXVREPLI_D\0" /* 3648 */ "PseudoVREPLI_D\0" /* 3663 */ "X86SRLI_D\0" /* 3673 */ "XVSRLI_D\0" /* 3682 */ "X86ROTLI_D\0" /* 3693 */ "PseudoLI_D\0" /* 3704 */ "XVPERMI_D\0" /* 3714 */ "XVMINI_D\0" /* 3723 */ "XVSEQI_D\0" /* 3732 */ "XVSRARI_D\0" /* 3742 */ "X86RCRI_D\0" /* 3752 */ "XVBITCLRI_D\0" /* 3764 */ "XVSRLRI_D\0" /* 3774 */ "X86ROTRI_D\0" /* 3785 */ "XVROTRI_D\0" /* 3795 */ "XVBITSETI_D\0" /* 3807 */ "XVSLTI_D\0" /* 3816 */ "XVBITREVI_D\0" /* 3828 */ "XVMAXI_D\0" /* 3837 */ "BYTEPICK_D\0" /* 3848 */ "BSTRPICK_D\0" /* 3859 */ "X86RCL_D\0" /* 3868 */ "LDL_D\0" /* 3874 */ "SCREL_D\0" /* 3882 */ "X86SLL_D\0" /* 3891 */ "XVSLL_D\0" /* 3899 */ "XVLDREPL_D\0" /* 3910 */ "X86SRL_D\0" /* 3919 */ "XVSRL_D\0" /* 3927 */ "ALSL_D\0" /* 3934 */ "X86ROTL_D\0" /* 3944 */ "STL_D\0" /* 3950 */ "X86MUL_D\0" /* 3959 */ "XVFMUL_D\0" /* 3968 */ "XVMUL_D\0" /* 3976 */ "XVILVL_D\0" /* 3985 */ "XVFTINTRNE_L_D\0" /* 4000 */ "XVFTINTRM_L_D\0" /* 4014 */ "XVFTINTRP_L_D\0" /* 4028 */ "XVFTINT_L_D\0" /* 4040 */ "XVFTINTRZ_L_D\0" /* 4054 */ "XVSTELM_D\0" /* 4064 */ "XVFRINTRM_D\0" /* 4076 */ "FCOPYSIGN_D\0" /* 4088 */ "XVFMIN_D\0" /* 4097 */ "AMMIN_D\0" /* 4105 */ "XVMIN_D\0" /* 4113 */ "XVFCMP_CUN_D\0" /* 4126 */ "XVFCMP_SUN_D\0" /* 4139 */ "XVCLO_D\0" /* 4147 */ "CTO_D\0" /* 4153 */ "AMSWAP_D\0" /* 4162 */ "XVFRECIP_D\0" /* 4173 */ "XVFRINTRP_D\0" /* 4185 */ "LLACQ_D\0" /* 4193 */ "XVFCMP_CEQ_D\0" /* 4206 */ "XVSEQ_D\0" /* 4214 */ "XVFCMP_SEQ_D\0" /* 4227 */ "XVFCMP_CUEQ_D\0" /* 4241 */ "XVFCMP_SUEQ_D\0" /* 4255 */ "XVSUBWOD_Q_D\0" /* 4268 */ "XVMADDWOD_Q_D\0" /* 4282 */ "XVADDWOD_Q_D\0" /* 4295 */ "XVMULWOD_Q_D\0" /* 4308 */ "XVEXTH_Q_D\0" /* 4319 */ "XVEXTL_Q_D\0" /* 4330 */ "XVSUBWEV_Q_D\0" /* 4343 */ "XVMADDWEV_Q_D\0" /* 4357 */ "XVADDWEV_Q_D\0" /* 4370 */ "XVMULWEV_Q_D\0" /* 4383 */ "XVHSUBW_Q_D\0" /* 4395 */ "XVHADDW_Q_D\0" /* 4407 */ "XVSRAR_D\0" /* 4416 */ "X86RCR_D\0" /* 4425 */ "LDR_D\0" /* 4431 */ "MOVGR2FR_D\0" /* 4442 */ "XVPICKVE2GR_D\0" /* 4456 */ "MOVFR2GR_D\0" /* 4467 */ "XVAVGR_D\0" /* 4476 */ "XVBITCLR_D\0" /* 4487 */ "XVSRLR_D\0" /* 4496 */ "X86OR_D\0" /* 4504 */ "XVFCMP_COR_D\0" /* 4517 */ "AMOR_D\0" /* 4524 */ "XVFCMP_SOR_D\0" /* 4537 */ "X86XOR_D\0" /* 4546 */ "AMXOR_D\0" /* 4554 */ "X86ROTR_D\0" /* 4564 */ "XVROTR_D\0" /* 4573 */ "LDPTR_D\0" /* 4581 */ "STPTR_D\0" /* 4589 */ "STR_D\0" /* 4595 */ "XVREPLGR2VR_D\0" /* 4609 */ "XVINSGR2VR_D\0" /* 4622 */ "IOCSRWR_D\0" /* 4632 */ "AMCAS_D\0" /* 4640 */ "FABS_D\0" /* 4647 */ "BSTRINS_D\0" /* 4657 */ "XVEXTRINS_D\0" /* 4669 */ "XVFCLASS_D\0" /* 4680 */ "XVFCVT_S_D\0" /* 4691 */ "XVSAT_D\0" /* 4699 */ "XVBITSET_D\0" /* 4710 */ "FLDGT_D\0" /* 4718 */ "ASRTGT_D\0" /* 4727 */ "FSTGT_D\0" /* 4735 */ "XVFCMP_CLT_D\0" /* 4748 */ "XVSLT_D\0" /* 4756 */ "XVFCMP_SLT_D\0" /* 4769 */ "XVFCMP_CULT_D\0" /* 4783 */ "XVFCMP_SULT_D\0" /* 4797 */ "XVPCNT_D\0" /* 4806 */ "XVFRINT_D\0" /* 4816 */ "XVFSQRT_D\0" /* 4826 */ "XVFRSQRT_D\0" /* 4837 */ "FST_D\0" /* 4843 */ "XVMADDWOD_Q_DU_D\0" /* 4860 */ "XVADDWOD_Q_DU_D\0" /* 4876 */ "XVMULWOD_Q_DU_D\0" /* 4892 */ "XVMADDWEV_Q_DU_D\0" /* 4909 */ "XVADDWEV_Q_DU_D\0" /* 4925 */ "XVMULWEV_Q_DU_D\0" /* 4941 */ "XVFTINT_LU_D\0" /* 4954 */ "XVFTINTRZ_LU_D\0" /* 4969 */ "XVSSRANI_WU_D\0" /* 4983 */ "XVSSRLNI_WU_D\0" /* 4997 */ "XVSSRARNI_WU_D\0" /* 5012 */ "XVSSRLRNI_WU_D\0" /* 5027 */ "XVSSRAN_WU_D\0" /* 5040 */ "XVSSRLN_WU_D\0" /* 5053 */ "XVSSRARN_WU_D\0" /* 5067 */ "XVSSRLRN_WU_D\0" /* 5081 */ "XVPACKEV_D\0" /* 5092 */ "XVPICKEV_D\0" /* 5103 */ "XVBITREV_D\0" /* 5114 */ "XVFDIV_D\0" /* 5123 */ "XVDIV_D\0" /* 5131 */ "XVSIGNCOV_D\0" /* 5143 */ "FMOV_D\0" /* 5150 */ "ARMMOV_D\0" /* 5159 */ "XVFTINTRNE_W_D\0" /* 5174 */ "XVSSRANI_W_D\0" /* 5187 */ "XVSRANI_W_D\0" /* 5199 */ "XVSSRLNI_W_D\0" /* 5212 */ "XVSRLNI_W_D\0" /* 5224 */ "XVSSRARNI_W_D\0" /* 5238 */ "XVSRARNI_W_D\0" /* 5251 */ "XVSSRLRNI_W_D\0" /* 5265 */ "XVSRLRNI_W_D\0" /* 5278 */ "XVFTINTRM_W_D\0" /* 5292 */ "XVSSRAN_W_D\0" /* 5304 */ "XVSRAN_W_D\0" /* 5315 */ "XVSSRLN_W_D\0" /* 5327 */ "XVSRLN_W_D\0" /* 5338 */ "XVSSRARN_W_D\0" /* 5351 */ "XVSRARN_W_D\0" /* 5363 */ "XVSSRLRN_W_D\0" /* 5376 */ "XVSRLRN_W_D\0" /* 5388 */ "XVFTINTRP_W_D\0" /* 5402 */ "XVFTINT_W_D\0" /* 5414 */ "XVFTINTRZ_W_D\0" /* 5428 */ "XVFMAX_D\0" /* 5437 */ "AMMAX_D\0" /* 5445 */ "XVMAX_D\0" /* 5453 */ "FLDX_D\0" /* 5460 */ "FSTX_D\0" /* 5467 */ "PseudoXVBZ_D\0" /* 5480 */ "PseudoVBZ_D\0" /* 5492 */ "XVSETALLNEZ_D\0" /* 5506 */ "XVCLZ_D\0" /* 5514 */ "PseudoXVBNZ_D\0" /* 5528 */ "PseudoVBNZ_D\0" /* 5541 */ "XVSETANYEQZ_D\0" /* 5555 */ "XVFRINTRZ_D\0" /* 5567 */ "CTZ_D\0" /* 5573 */ "XVMSKLTZ_D\0" /* 5584 */ "PseudoAddTPRel_D\0" /* 5601 */ "PseudoAtomicStoreD\0" /* 5620 */ "FSEL_xD\0" /* 5628 */ "PSEUDO_PROBE\0" /* 5641 */ "G_SSUBE\0" /* 5649 */ "G_USUBE\0" /* 5657 */ "G_FENCE\0" /* 5665 */ "ARITH_FENCE\0" /* 5677 */ "REG_SEQUENCE\0" /* 5690 */ "G_SADDE\0" /* 5698 */ "G_UADDE\0" /* 5706 */ "G_GET_FPMODE\0" /* 5719 */ "G_RESET_FPMODE\0" /* 5734 */ "G_SET_FPMODE\0" /* 5747 */ "G_FMINNUM_IEEE\0" /* 5762 */ "G_FMAXNUM_IEEE\0" /* 5777 */ "BGE\0" /* 5781 */ "PseudoLA_TLS_DESC_PC_LARGE\0" /* 5808 */ "PseudoLA_TLS_GD_LARGE\0" /* 5830 */ "PseudoLA_TLS_LD_LARGE\0" /* 5852 */ "PseudoLA_TLS_IE_LARGE\0" /* 5874 */ "PseudoLA_PCREL_LARGE\0" /* 5895 */ "PseudoTAIL_LARGE\0" /* 5912 */ "PseudoCALL_LARGE\0" /* 5929 */ "PseudoLA_ABS_LARGE\0" /* 5948 */ "PseudoLA_TLS_DESC_ABS_LARGE\0" /* 5976 */ "PseudoLA_GOT_LARGE\0" /* 5995 */ "PseudoLA_TLS_IE\0" /* 6011 */ "G_VSCALE\0" /* 6020 */ "G_JUMP_TABLE\0" /* 6033 */ "IDLE\0" /* 6038 */ "BUNDLE\0" /* 6045 */ "PseudoLA_TLS_LE\0" /* 6061 */ "BNE\0" /* 6065 */ "G_MEMCPY_INLINE\0" /* 6081 */ "SETX86LOOPNE\0" /* 6094 */ "LOCAL_ESCAPE\0" /* 6107 */ "SETX86LOOPE\0" /* 6119 */ "G_STACKRESTORE\0" /* 6134 */ "G_INDEXED_STORE\0" /* 6150 */ "G_STORE\0" /* 6158 */ "SET_CFR_FALSE\0" /* 6172 */ "G_BITREVERSE\0" /* 6185 */ "FAKE_USE\0" /* 6194 */ "LDPTE\0" /* 6200 */ "DBG_VALUE\0" /* 6210 */ "G_GLOBAL_VALUE\0" /* 6225 */ "G_PTRAUTH_GLOBAL_VALUE\0" /* 6248 */ "CONVERGENCECTRL_GLUE\0" /* 6269 */ "SET_CFR_TRUE\0" /* 6282 */ "G_STACKSAVE\0" /* 6294 */ "G_MEMMOVE\0" /* 6304 */ "ARMMOVE\0" /* 6312 */ "G_FREEZE\0" /* 6321 */ "G_FCANONICALIZE\0" /* 6337 */ "MOVGR2CF\0" /* 6346 */ "G_CTLZ_ZERO_UNDEF\0" /* 6364 */ "G_CTTZ_ZERO_UNDEF\0" /* 6382 */ "G_IMPLICIT_DEF\0" /* 6397 */ "DBG_INSTR_REF\0" /* 6411 */ "X86MFFLAG\0" /* 6421 */ "ARMMFFLAG\0" /* 6431 */ "X86MTFLAG\0" /* 6441 */ "ARMMTFLAG\0" /* 6451 */ "X86SETTAG\0" /* 6461 */ "G_FNEG\0" /* 6468 */ "EXTRACT_SUBREG\0" /* 6483 */ "INSERT_SUBREG\0" /* 6497 */ "G_SEXT_INREG\0" /* 6510 */ "SUBREG_TO_REG\0" /* 6524 */ "CPUCFG\0" /* 6531 */ "G_ATOMIC_CMPXCHG\0" /* 6548 */ "GCSRXCHG\0" /* 6557 */ "G_ATOMICRMW_XCHG\0" /* 6574 */ "G_FLOG\0" /* 6581 */ "G_VAARG\0" /* 6589 */ "PREALLOCATED_ARG\0" /* 6606 */ "REVB_2H\0" /* 6614 */ "REVB_4H\0" /* 6622 */ "TLBSRCH\0" /* 6630 */ "G_PREFETCH\0" /* 6641 */ "G_SMULH\0" /* 6649 */ "G_UMULH\0" /* 6657 */ "G_FTANH\0" /* 6665 */ "G_FSINH\0" /* 6673 */ "G_FCOSH\0" /* 6681 */ "GTLBFLUSH\0" /* 6691 */ "XVREPLVE0_H\0" /* 6703 */ "XVADDA_H\0" /* 6712 */ "X86SRA_H\0" /* 6721 */ "XVSRA_H\0" /* 6729 */ "AMADD__DB_H\0" /* 6741 */ "AMSWAP__DB_H\0" /* 6754 */ "AMCAS__DB_H\0" /* 6766 */ "X86SUB_H\0" /* 6775 */ "XVMSUB_H\0" /* 6784 */ "XVSSUB_H\0" /* 6793 */ "XVSUB_H\0" /* 6801 */ "XVSSRANI_B_H\0" /* 6814 */ "XVSRANI_B_H\0" /* 6826 */ "XVSSRLNI_B_H\0" /* 6839 */ "XVSRLNI_B_H\0" /* 6851 */ "XVSSRARNI_B_H\0" /* 6865 */ "XVSRARNI_B_H\0" /* 6878 */ "XVSSRLRNI_B_H\0" /* 6892 */ "XVSRLRNI_B_H\0" /* 6905 */ "XVSSRAN_B_H\0" /* 6917 */ "XVSRAN_B_H\0" /* 6928 */ "XVSSRLN_B_H\0" /* 6940 */ "XVSRLN_B_H\0" /* 6951 */ "XVSSRARN_B_H\0" /* 6964 */ "XVSRARN_B_H\0" /* 6976 */ "XVSSRLRN_B_H\0" /* 6989 */ "XVSRLRN_B_H\0" /* 7001 */ "X86SBC_H\0" /* 7010 */ "X86ADC_H\0" /* 7019 */ "X86DEC_H\0" /* 7028 */ "X86INC_H\0" /* 7037 */ "X86ADD_H\0" /* 7046 */ "AMADD_H\0" /* 7054 */ "XVMADD_H\0" /* 7063 */ "XVSADD_H\0" /* 7072 */ "XVADD_H\0" /* 7080 */ "LD_H\0" /* 7085 */ "X86AND_H\0" /* 7094 */ "XVPACKOD_H\0" /* 7105 */ "XVPICKOD_H\0" /* 7116 */ "XVMOD_H\0" /* 7124 */ "IOCSRRD_H\0" /* 7134 */ "XVABSD_H\0" /* 7143 */ "VEXT2XV_D_H\0" /* 7155 */ "LDLE_H\0" /* 7162 */ "XVSLE_H\0" /* 7170 */ "STLE_H\0" /* 7177 */ "XVREPLVE_H\0" /* 7188 */ "XVSHUF_H\0" /* 7197 */ "XVNEG_H\0" /* 7205 */ "XVAVG_H\0" /* 7213 */ "XVMUH_H\0" /* 7221 */ "XVILVH_H\0" /* 7230 */ "XVSHUF4I_H\0" /* 7241 */ "X86SRAI_H\0" /* 7251 */ "XVSRAI_H\0" /* 7260 */ "XVSLEI_H\0" /* 7269 */ "XVREPL128VEI_H\0" /* 7284 */ "VREPLVEI_H\0" /* 7295 */ "X86RCLI_H\0" /* 7305 */ "X86SLLI_H\0" /* 7315 */ "XVSLLI_H\0" /* 7324 */ "PseudoXVREPLI_H\0" /* 7340 */ "PseudoVREPLI_H\0" /* 7355 */ "X86SRLI_H\0" /* 7365 */ "XVSRLI_H\0" /* 7374 */ "X86ROTLI_H\0" /* 7385 */ "XVMINI_H\0" /* 7394 */ "XVFRSTPI_H\0" /* 7405 */ "XVSEQI_H\0" /* 7414 */ "XVSRARI_H\0" /* 7424 */ "X86RCRI_H\0" /* 7434 */ "XVBITCLRI_H\0" /* 7446 */ "XVSRLRI_H\0" /* 7456 */ "X86ROTRI_H\0" /* 7467 */ "XVROTRI_H\0" /* 7477 */ "XVBITSETI_H\0" /* 7489 */ "XVSLTI_H\0" /* 7498 */ "XVBITREVI_H\0" /* 7510 */ "XVMAXI_H\0" /* 7519 */ "X86RCL_H\0" /* 7528 */ "X86SLL_H\0" /* 7537 */ "XVSLL_H\0" /* 7545 */ "XVLDREPL_H\0" /* 7556 */ "X86SRL_H\0" /* 7565 */ "XVSRL_H\0" /* 7573 */ "X86ROTL_H\0" /* 7583 */ "X86MUL_H\0" /* 7592 */ "XVMUL_H\0" /* 7600 */ "XVILVL_H\0" /* 7609 */ "XVSTELM_H\0" /* 7619 */ "XVMIN_H\0" /* 7627 */ "XVCLO_H\0" /* 7635 */ "AMSWAP_H\0" /* 7644 */ "XVFRSTP_H\0" /* 7654 */ "XVSEQ_H\0" /* 7662 */ "XVSRAR_H\0" /* 7671 */ "X86RCR_H\0" /* 7680 */ "VPICKVE2GR_H\0" /* 7693 */ "XVAVGR_H\0" /* 7702 */ "XVBITCLR_H\0" /* 7713 */ "XVSRLR_H\0" /* 7722 */ "X86OR_H\0" /* 7730 */ "X86XOR_H\0" /* 7739 */ "X86ROTR_H\0" /* 7749 */ "XVROTR_H\0" /* 7758 */ "XVREPLGR2VR_H\0" /* 7772 */ "PseudoXVINSGR2VR_H\0" /* 7791 */ "IOCSRWR_H\0" /* 7801 */ "AMCAS_H\0" /* 7809 */ "XVEXTRINS_H\0" /* 7821 */ "XVFCVTH_S_H\0" /* 7833 */ "XVFCVTL_S_H\0" /* 7845 */ "XVSAT_H\0" /* 7853 */ "XVBITSET_H\0" /* 7864 */ "LDGT_H\0" /* 7871 */ "STGT_H\0" /* 7878 */ "XVSLT_H\0" /* 7886 */ "XVPCNT_H\0" /* 7895 */ "ST_H\0" /* 7900 */ "XVSSRANI_BU_H\0" /* 7914 */ "XVSSRLNI_BU_H\0" /* 7928 */ "XVSSRARNI_BU_H\0" /* 7943 */ "XVSSRLRNI_BU_H\0" /* 7958 */ "XVSSRAN_BU_H\0" /* 7971 */ "XVSSRLN_BU_H\0" /* 7984 */ "XVSSRARN_BU_H\0" /* 7998 */ "XVSSRLRN_BU_H\0" /* 8012 */ "XVMADDWOD_W_HU_H\0" /* 8029 */ "XVADDWOD_W_HU_H\0" /* 8045 */ "XVMULWOD_W_HU_H\0" /* 8061 */ "XVMADDWEV_W_HU_H\0" /* 8078 */ "XVADDWEV_W_HU_H\0" /* 8094 */ "XVMULWEV_W_HU_H\0" /* 8110 */ "XVPACKEV_H\0" /* 8121 */ "XVPICKEV_H\0" /* 8132 */ "XVBITREV_H\0" /* 8143 */ "XVDIV_H\0" /* 8151 */ "XVSIGNCOV_H\0" /* 8163 */ "XVSUBWOD_W_H\0" /* 8176 */ "XVMADDWOD_W_H\0" /* 8190 */ "XVADDWOD_W_H\0" /* 8203 */ "XVMULWOD_W_H\0" /* 8216 */ "XVEXTH_W_H\0" /* 8227 */ "XVSLLWIL_W_H\0" /* 8240 */ "EXT_W_H\0" /* 8248 */ "XVSUBWEV_W_H\0" /* 8261 */ "XVMADDWEV_W_H\0" /* 8275 */ "XVADDWEV_W_H\0" /* 8288 */ "XVMULWEV_W_H\0" /* 8301 */ "VEXT2XV_W_H\0" /* 8313 */ "XVHSUBW_W_H\0" /* 8325 */ "XVHADDW_W_H\0" /* 8337 */ "XVMAX_H\0" /* 8345 */ "LDX_H\0" /* 8351 */ "STX_H\0" /* 8357 */ "PseudoXVBZ_H\0" /* 8370 */ "PseudoVBZ_H\0" /* 8382 */ "XVSETALLNEZ_H\0" /* 8396 */ "XVCLZ_H\0" /* 8404 */ "PseudoXVBNZ_H\0" /* 8418 */ "PseudoVBNZ_H\0" /* 8431 */ "XVSETANYEQZ_H\0" /* 8445 */ "XVMSKLTZ_H\0" /* 8456 */ "PCALAU12I\0" /* 8466 */ "PCADDU12I\0" /* 8476 */ "PCADDU18I\0" /* 8486 */ "PCADDI\0" /* 8493 */ "XVLDI\0" /* 8499 */ "ANDI\0" /* 8504 */ "DBG_PHI\0" /* 8512 */ "XORI\0" /* 8517 */ "G_FPTOSI\0" /* 8526 */ "SLTI\0" /* 8531 */ "G_FPTOUI\0" /* 8540 */ "SLTUI\0" /* 8546 */ "G_FPOWI\0" /* 8554 */ "SETX86J\0" /* 8562 */ "SETARMJ\0" /* 8570 */ "BREAK\0" /* 8576 */ "G_PTRMASK\0" /* 8586 */ "BL\0" /* 8589 */ "DBCL\0" /* 8594 */ "HVCL\0" /* 8599 */ "GC_LABEL\0" /* 8608 */ "DBG_LABEL\0" /* 8618 */ "EH_LABEL\0" /* 8627 */ "ANNOTATION_LABEL\0" /* 8644 */ "ICALL_BRANCH_FUNNEL\0" /* 8664 */ "PseudoLA_PCREL\0" /* 8679 */ "G_FSHL\0" /* 8686 */ "G_SHL\0" /* 8692 */ "PseudoB_TAIL\0" /* 8705 */ "PseudoJIRL_TAIL\0" /* 8721 */ "PseudoTAIL\0" /* 8732 */ "G_FCEIL\0" /* 8740 */ "SYSCALL\0" /* 8748 */ "PseudoDESC_CALL\0" /* 8764 */ "PATCHABLE_TAIL_CALL\0" /* 8784 */ "PseudoJIRL_CALL\0" /* 8800 */ "PATCHABLE_TYPED_EVENT_CALL\0" /* 8827 */ "PATCHABLE_EVENT_CALL\0" /* 8848 */ "FENTRY_CALL\0" /* 8860 */ "PseudoCALL\0" /* 8871 */ "TLBFILL\0" /* 8879 */ "KILL\0" /* 8884 */ "G_CONSTANT_POOL\0" /* 8900 */ "JIRL\0" /* 8905 */ "G_ROTL\0" /* 8912 */ "G_VECREDUCE_FMUL\0" /* 8929 */ "G_FMUL\0" /* 8936 */ "G_VECREDUCE_SEQ_FMUL\0" /* 8957 */ "G_STRICT_FMUL\0" /* 8971 */ "G_VECREDUCE_MUL\0" /* 8987 */ "G_MUL\0" /* 8993 */ "XVFFINT_D_L\0" /* 9005 */ "XVFFINT_S_L\0" /* 9017 */ "G_FREM\0" /* 9024 */ "G_STRICT_FREM\0" /* 9038 */ "G_SREM\0" /* 9045 */ "G_UREM\0" /* 9052 */ "G_SDIVREM\0" /* 9062 */ "G_UDIVREM\0" /* 9072 */ "INLINEASM\0" /* 9082 */ "X86CLRTM\0" /* 9091 */ "X86SETTM\0" /* 9100 */ "PseudoTAIL_MEDIUM\0" /* 9118 */ "PseudoCALL_MEDIUM\0" /* 9136 */ "G_VECREDUCE_FMINIMUM\0" /* 9157 */ "G_FMINIMUM\0" /* 9168 */ "G_VECREDUCE_FMAXIMUM\0" /* 9189 */ "G_FMAXIMUM\0" /* 9200 */ "G_FMINNUM\0" /* 9210 */ "G_FMAXNUM\0" /* 9220 */ "G_FATAN\0" /* 9228 */ "G_FTAN\0" /* 9235 */ "ANDN\0" /* 9240 */ "G_INTRINSIC_ROUNDEVEN\0" /* 9262 */ "G_ASSERT_ALIGN\0" /* 9277 */ "G_FCOPYSIGN\0" /* 9289 */ "G_VECREDUCE_FMIN\0" /* 9306 */ "G_ATOMICRMW_FMIN\0" /* 9323 */ "G_VECREDUCE_SMIN\0" /* 9340 */ "G_SMIN\0" /* 9347 */ "G_VECREDUCE_UMIN\0" /* 9364 */ "G_UMIN\0" /* 9371 */ "G_ATOMICRMW_UMIN\0" /* 9388 */ "G_ATOMICRMW_MIN\0" /* 9404 */ "G_FASIN\0" /* 9412 */ "G_FSIN\0" /* 9419 */ "CFI_INSTRUCTION\0" /* 9435 */ "ORN\0" /* 9439 */ "ERTN\0" /* 9444 */ "ADJCALLSTACKDOWN\0" /* 9461 */ "G_SSUBO\0" /* 9469 */ "G_USUBO\0" /* 9477 */ "G_SADDO\0" /* 9485 */ "G_UADDO\0" /* 9493 */ "JUMP_TABLE_DEBUG_INFO\0" /* 9515 */ "G_SMULO\0" /* 9523 */ "G_UMULO\0" /* 9531 */ "G_BZERO\0" /* 9539 */ "STACKMAP\0" /* 9548 */ "G_DEBUGTRAP\0" /* 9560 */ "G_UBSANTRAP\0" /* 9572 */ "G_TRAP\0" /* 9579 */ "G_ATOMICRMW_UDEC_WRAP\0" /* 9601 */ "G_ATOMICRMW_UINC_WRAP\0" /* 9623 */ "G_BSWAP\0" /* 9631 */ "G_SITOFP\0" /* 9640 */ "G_UITOFP\0" /* 9649 */ "G_FCMP\0" /* 9656 */ "G_ICMP\0" /* 9663 */ "G_SCMP\0" /* 9670 */ "G_UCMP\0" /* 9677 */ "PseudoUNIMP\0" /* 9689 */ "CACOP\0" /* 9695 */ "CONVERGENCECTRL_LOOP\0" /* 9716 */ "G_CTPOP\0" /* 9724 */ "X86DECTOP\0" /* 9734 */ "X86INCTOP\0" /* 9744 */ "X86MFTOP\0" /* 9753 */ "X86MTTOP\0" /* 9762 */ "PATCHABLE_OP\0" /* 9775 */ "FAULTING_OP\0" /* 9787 */ "ADJCALLSTACKUP\0" /* 9802 */ "PREALLOCATED_SETUP\0" /* 9821 */ "G_FLDEXP\0" /* 9830 */ "G_STRICT_FLDEXP\0" /* 9846 */ "G_FEXP\0" /* 9853 */ "G_FFREXP\0" /* 9862 */ "BEQ\0" /* 9866 */ "XVREPLVE0_Q\0" /* 9878 */ "XVSUB_Q\0" /* 9886 */ "SC_Q\0" /* 9891 */ "XVADD_Q\0" /* 9899 */ "XVSSRANI_D_Q\0" /* 9912 */ "XVSRANI_D_Q\0" /* 9924 */ "XVSSRLNI_D_Q\0" /* 9937 */ "XVSRLNI_D_Q\0" /* 9949 */ "XVSSRARNI_D_Q\0" /* 9963 */ "XVSRARNI_D_Q\0" /* 9976 */ "XVSSRLRNI_D_Q\0" /* 9990 */ "XVSRLRNI_D_Q\0" /* 10003 */ "XVPERMI_Q\0" /* 10013 */ "XVSSRANI_DU_Q\0" /* 10027 */ "XVSSRLNI_DU_Q\0" /* 10041 */ "XVSSRARNI_DU_Q\0" /* 10056 */ "XVSSRLRNI_DU_Q\0" /* 10071 */ "DBAR\0" /* 10076 */ "IBAR\0" /* 10081 */ "G_BR\0" /* 10086 */ "INLINEASM_BR\0" /* 10099 */ "PseudoBR\0" /* 10108 */ "MOVGR2SCR\0" /* 10118 */ "G_BLOCK_ADDR\0" /* 10131 */ "MEMBARRIER\0" /* 10142 */ "G_CONSTANT_FOLD_BARRIER\0" /* 10166 */ "PATCHABLE_FUNCTION_ENTER\0" /* 10191 */ "G_READCYCLECOUNTER\0" /* 10210 */ "G_READSTEADYCOUNTER\0" /* 10230 */ "G_READ_REGISTER\0" /* 10246 */ "G_WRITE_REGISTER\0" /* 10263 */ "PseudoLD_CFR\0" /* 10276 */ "PseudoST_CFR\0" /* 10289 */ "PseudoCopyCFR\0" /* 10303 */ "MOVCF2GR\0" /* 10312 */ "MOVSCR2GR\0" /* 10322 */ "MOVFCSR2GR\0" /* 10333 */ "G_ASHR\0" /* 10340 */ "G_FSHR\0" /* 10347 */ "G_LSHR\0" /* 10354 */ "LDDIR\0" /* 10360 */ "TLBCLR\0" /* 10367 */ "CONVERGENCECTRL_ANCHOR\0" /* 10390 */ "NOR\0" /* 10394 */ "G_FFLOOR\0" /* 10403 */ "G_EXTRACT_SUBVECTOR\0" /* 10423 */ "G_INSERT_SUBVECTOR\0" /* 10442 */ "G_BUILD_VECTOR\0" /* 10457 */ "G_SHUFFLE_VECTOR\0" /* 10474 */ "G_SPLAT_VECTOR\0" /* 10489 */ "G_VECREDUCE_XOR\0" /* 10505 */ "G_XOR\0" /* 10511 */ "G_ATOMICRMW_XOR\0" /* 10527 */ "G_VECREDUCE_OR\0" /* 10542 */ "G_OR\0" /* 10547 */ "G_ATOMICRMW_OR\0" /* 10562 */ "MOVGR2FCSR\0" /* 10573 */ "RDFCSR\0" /* 10580 */ "WRFCSR\0" /* 10587 */ "G_ROTR\0" /* 10594 */ "G_INTTOPTR\0" /* 10605 */ "TLBWR\0" /* 10611 */ "GCSRWR\0" /* 10618 */ "G_FABS\0" /* 10625 */ "PseudoLA_ABS\0" /* 10638 */ "PseudoLA_TLS_DESC_ABS\0" /* 10660 */ "G_ABS\0" /* 10666 */ "G_UNMERGE_VALUES\0" /* 10683 */ "G_MERGE_VALUES\0" /* 10698 */ "G_FACOS\0" /* 10706 */ "G_FCOS\0" /* 10713 */ "G_CONCAT_VECTORS\0" /* 10730 */ "COPY_TO_REGCLASS\0" /* 10747 */ "G_IS_FPCLASS\0" /* 10760 */ "G_ATOMIC_CMPXCHG_WITH_SUCCESS\0" /* 10790 */ "G_VECTOR_COMPRESS\0" /* 10808 */ "G_INTRINSIC_W_SIDE_EFFECTS\0" /* 10835 */ "G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS\0" /* 10873 */ "XVFMINA_S\0" /* 10883 */ "XVFMAXA_S\0" /* 10893 */ "FSCALEB_S\0" /* 10903 */ "XVFLOGB_S\0" /* 10913 */ "XVFSUB_S\0" /* 10922 */ "XVFMSUB_S\0" /* 10932 */ "XVFNMSUB_S\0" /* 10943 */ "XVFADD_S\0" /* 10952 */ "XVFMADD_S\0" /* 10962 */ "XVFNMADD_S\0" /* 10973 */ "FLD_S\0" /* 10979 */ "XVFCVTH_D_S\0" /* 10991 */ "XVFCVTL_D_S\0" /* 11003 */ "FCVT_D_S\0" /* 11012 */ "XVFCMP_CLE_S\0" /* 11025 */ "FLDLE_S\0" /* 11033 */ "XVFCMP_SLE_S\0" /* 11046 */ "FSTLE_S\0" /* 11054 */ "XVFCMP_CULE_S\0" /* 11068 */ "XVFCMP_SULE_S\0" /* 11082 */ "XVFCMP_CNE_S\0" /* 11095 */ "XVFRINTRNE_S\0" /* 11108 */ "XVFCMP_SNE_S\0" /* 11121 */ "XVFCMP_CUNE_S\0" /* 11135 */ "XVFCMP_SUNE_S\0" /* 11149 */ "XVFRECIPE_S\0" /* 11161 */ "XVFRSQRTE_S\0" /* 11173 */ "XVFCMP_CAF_S\0" /* 11186 */ "XVFCMP_SAF_S\0" /* 11199 */ "FNEG_S\0" /* 11206 */ "XVFCVT_H_S\0" /* 11217 */ "XVFMUL_S\0" /* 11226 */ "FTINTRNE_L_S\0" /* 11239 */ "XVFTINTRNEH_L_S\0" /* 11255 */ "XVFTINTRMH_L_S\0" /* 11270 */ "XVFTINTRPH_L_S\0" /* 11285 */ "XVFTINTH_L_S\0" /* 11298 */ "XVFTINTRZH_L_S\0" /* 11313 */ "XVFTINTRNEL_L_S\0" /* 11329 */ "XVFTINTRML_L_S\0" /* 11344 */ "XVFTINTRPL_L_S\0" /* 11359 */ "XVFTINTL_L_S\0" /* 11372 */ "XVFTINTRZL_L_S\0" /* 11387 */ "FTINTRM_L_S\0" /* 11399 */ "FTINTRP_L_S\0" /* 11411 */ "FTINT_L_S\0" /* 11421 */ "FTINTRZ_L_S\0" /* 11433 */ "XVFRINTRM_S\0" /* 11445 */ "FCOPYSIGN_S\0" /* 11457 */ "XVFMIN_S\0" /* 11466 */ "XVFCMP_CUN_S\0" /* 11479 */ "XVFCMP_SUN_S\0" /* 11492 */ "XVFRECIP_S\0" /* 11503 */ "XVFRINTRP_S\0" /* 11515 */ "XVFCMP_CEQ_S\0" /* 11528 */ "XVFCMP_SEQ_S\0" /* 11541 */ "XVFCMP_CUEQ_S\0" /* 11555 */ "XVFCMP_SUEQ_S\0" /* 11569 */ "MOVFRH2GR_S\0" /* 11581 */ "MOVFR2GR_S\0" /* 11592 */ "XVFCMP_COR_S\0" /* 11605 */ "XVFCMP_SOR_S\0" /* 11618 */ "FABS_S\0" /* 11625 */ "XVFCLASS_S\0" /* 11636 */ "FLDGT_S\0" /* 11644 */ "FSTGT_S\0" /* 11652 */ "XVFCMP_CLT_S\0" /* 11665 */ "XVFCMP_SLT_S\0" /* 11678 */ "XVFCMP_CULT_S\0" /* 11692 */ "XVFCMP_SULT_S\0" /* 11706 */ "XVFRINT_S\0" /* 11716 */ "XVFSQRT_S\0" /* 11726 */ "XVFRSQRT_S\0" /* 11737 */ "FST_S\0" /* 11743 */ "XVFTINT_WU_S\0" /* 11756 */ "XVFTINTRZ_WU_S\0" /* 11771 */ "XVFDIV_S\0" /* 11780 */ "FMOV_S\0" /* 11787 */ "XVFTINTRNE_W_S\0" /* 11802 */ "XVFTINTRM_W_S\0" /* 11816 */ "XVFTINTRP_W_S\0" /* 11830 */ "XVFTINT_W_S\0" /* 11842 */ "XVFTINTRZ_W_S\0" /* 11856 */ "XVFMAX_S\0" /* 11865 */ "FLDX_S\0" /* 11872 */ "FSTX_S\0" /* 11879 */ "XVFRINTRZ_S\0" /* 11891 */ "MOVFR2CF_xS\0" /* 11903 */ "FSEL_xS\0" /* 11911 */ "MOVCF2FR_xS\0" /* 11923 */ "G_SSUBSAT\0" /* 11933 */ "G_USUBSAT\0" /* 11943 */ "G_SADDSAT\0" /* 11953 */ "G_UADDSAT\0" /* 11963 */ "G_SSHLSAT\0" /* 11973 */ "G_USHLSAT\0" /* 11983 */ "G_SMULFIXSAT\0" /* 11996 */ "G_UMULFIXSAT\0" /* 12009 */ "G_SDIVFIXSAT\0" /* 12022 */ "G_UDIVFIXSAT\0" /* 12035 */ "G_EXTRACT\0" /* 12045 */ "G_SELECT\0" /* 12054 */ "G_BRINDIRECT\0" /* 12067 */ "PATCHABLE_RET\0" /* 12081 */ "PseudoRET\0" /* 12091 */ "G_MEMSET\0" /* 12100 */ "PATCHABLE_FUNCTION_EXIT\0" /* 12124 */ "G_BRJT\0" /* 12131 */ "BLT\0" /* 12135 */ "G_EXTRACT_VECTOR_ELT\0" /* 12156 */ "G_INSERT_VECTOR_ELT\0" /* 12176 */ "SLT\0" /* 12180 */ "G_FCONSTANT\0" /* 12192 */ "G_CONSTANT\0" /* 12203 */ "G_INTRINSIC_CONVERGENT\0" /* 12226 */ "STATEPOINT\0" /* 12237 */ "PATCHPOINT\0" /* 12248 */ "G_PTRTOINT\0" /* 12259 */ "G_FRINT\0" /* 12267 */ "G_INTRINSIC_LLRINT\0" /* 12286 */ "G_INTRINSIC_LRINT\0" /* 12304 */ "G_FNEARBYINT\0" /* 12317 */ "PseudoLA_GOT\0" /* 12330 */ "G_VASTART\0" /* 12340 */ "LIFETIME_START\0" /* 12355 */ "G_INVOKE_REGION_START\0" /* 12377 */ "G_INSERT\0" /* 12386 */ "G_FSQRT\0" /* 12394 */ "G_STRICT_FSQRT\0" /* 12409 */ "G_BITCAST\0" /* 12419 */ "G_ADDRSPACE_CAST\0" /* 12436 */ "DBG_VALUE_LIST\0" /* 12451 */ "XVST\0" /* 12456 */ "G_FPEXT\0" /* 12464 */ "G_SEXT\0" /* 12471 */ "G_ASSERT_SEXT\0" /* 12485 */ "G_ANYEXT\0" /* 12494 */ "G_ZEXT\0" /* 12501 */ "G_ASSERT_ZEXT\0" /* 12515 */ "XVSSUB_BU\0" /* 12525 */ "XVSADD_BU\0" /* 12535 */ "LD_BU\0" /* 12541 */ "XVMOD_BU\0" /* 12550 */ "XVABSD_BU\0" /* 12560 */ "XVSLE_BU\0" /* 12569 */ "XVAVG_BU\0" /* 12578 */ "XVMUH_BU\0" /* 12587 */ "XVSUBWOD_H_BU\0" /* 12601 */ "XVMADDWOD_H_BU\0" /* 12616 */ "XVADDWOD_H_BU\0" /* 12630 */ "XVMULWOD_H_BU\0" /* 12644 */ "XVSUBWEV_H_BU\0" /* 12658 */ "XVMADDWEV_H_BU\0" /* 12673 */ "XVADDWEV_H_BU\0" /* 12687 */ "XVMULWEV_H_BU\0" /* 12701 */ "XVSUBI_BU\0" /* 12711 */ "XVADDI_BU\0" /* 12721 */ "XVSLEI_BU\0" /* 12731 */ "XVMINI_BU\0" /* 12741 */ "XVSLTI_BU\0" /* 12751 */ "XVMAXI_BU\0" /* 12761 */ "X86MUL_BU\0" /* 12771 */ "XVMIN_BU\0" /* 12780 */ "VPICKVE2GR_BU\0" /* 12794 */ "XVAVGR_BU\0" /* 12804 */ "XVSAT_BU\0" /* 12813 */ "XVSLT_BU\0" /* 12822 */ "VEXT2XV_DU_BU\0" /* 12836 */ "XVEXTH_HU_BU\0" /* 12849 */ "XVSLLWIL_HU_BU\0" /* 12864 */ "VEXT2XV_HU_BU\0" /* 12878 */ "XVHSUBW_HU_BU\0" /* 12892 */ "XVHADDW_HU_BU\0" /* 12906 */ "VEXT2XV_WU_BU\0" /* 12920 */ "XVDIV_BU\0" /* 12929 */ "XVMAX_BU\0" /* 12938 */ "LDX_BU\0" /* 12945 */ "AMMIN__DB_DU\0" /* 12958 */ "AMMAX__DB_DU\0" /* 12971 */ "X86SUB_DU\0" /* 12981 */ "XVSSUB_DU\0" /* 12991 */ "X86ADD_DU\0" /* 13001 */ "XVSADD_DU\0" /* 13011 */ "XVMOD_DU\0" /* 13020 */ "XVABSD_DU\0" /* 13030 */ "XVSLE_DU\0" /* 13039 */ "XVAVG_DU\0" /* 13048 */ "MULH_DU\0" /* 13056 */ "XVMUH_DU\0" /* 13065 */ "XVSUBI_DU\0" /* 13075 */ "XVADDI_DU\0" /* 13085 */ "XVSLEI_DU\0" /* 13095 */ "XVMINI_DU\0" /* 13105 */ "XVSLTI_DU\0" /* 13115 */ "XVMAXI_DU\0" /* 13125 */ "X86MUL_DU\0" /* 13135 */ "AMMIN_DU\0" /* 13144 */ "XVMIN_DU\0" /* 13153 */ "XVSUBWOD_Q_DU\0" /* 13167 */ "XVMADDWOD_Q_DU\0" /* 13182 */ "XVADDWOD_Q_DU\0" /* 13196 */ "XVMULWOD_Q_DU\0" /* 13210 */ "XVSUBWEV_Q_DU\0" /* 13224 */ "XVMADDWEV_Q_DU\0" /* 13239 */ "XVADDWEV_Q_DU\0" /* 13253 */ "XVMULWEV_Q_DU\0" /* 13267 */ "XVPICKVE2GR_DU\0" /* 13282 */ "XVAVGR_DU\0" /* 13292 */ "XVSAT_DU\0" /* 13301 */ "XVSLT_DU\0" /* 13310 */ "XVEXTH_QU_DU\0" /* 13323 */ "XVEXTL_QU_DU\0" /* 13336 */ "XVHSUBW_QU_DU\0" /* 13350 */ "XVHADDW_QU_DU\0" /* 13364 */ "XVDIV_DU\0" /* 13373 */ "AMMAX_DU\0" /* 13382 */ "XVMAX_DU\0" /* 13391 */ "BGEU\0" /* 13396 */ "XVSSUB_HU\0" /* 13406 */ "XVSADD_HU\0" /* 13416 */ "LD_HU\0" /* 13422 */ "XVMOD_HU\0" /* 13431 */ "XVABSD_HU\0" /* 13441 */ "XVSLE_HU\0" /* 13450 */ "XVAVG_HU\0" /* 13459 */ "XVMUH_HU\0" /* 13468 */ "XVSUBI_HU\0" /* 13478 */ "XVADDI_HU\0" /* 13488 */ "XVSLEI_HU\0" /* 13498 */ "XVMINI_HU\0" /* 13508 */ "XVSLTI_HU\0" /* 13518 */ "XVMAXI_HU\0" /* 13528 */ "X86MUL_HU\0" /* 13538 */ "XVMIN_HU\0" /* 13547 */ "VPICKVE2GR_HU\0" /* 13561 */ "XVAVGR_HU\0" /* 13571 */ "XVSAT_HU\0" /* 13580 */ "XVSLT_HU\0" /* 13589 */ "VEXT2XV_DU_HU\0" /* 13603 */ "XVEXTH_WU_HU\0" /* 13616 */ "XVSLLWIL_WU_HU\0" /* 13631 */ "VEXT2XV_WU_HU\0" /* 13645 */ "XVHSUBW_WU_HU\0" /* 13659 */ "XVHADDW_WU_HU\0" /* 13673 */ "XVDIV_HU\0" /* 13682 */ "XVSUBWOD_W_HU\0" /* 13696 */ "XVMADDWOD_W_HU\0" /* 13711 */ "XVADDWOD_W_HU\0" /* 13725 */ "XVMULWOD_W_HU\0" /* 13739 */ "XVSUBWEV_W_HU\0" /* 13753 */ "XVMADDWEV_W_HU\0" /* 13768 */ "XVADDWEV_W_HU\0" /* 13782 */ "XVMULWEV_W_HU\0" /* 13796 */ "XVMAX_HU\0" /* 13805 */ "LDX_HU\0" /* 13812 */ "XVFFINT_D_LU\0" /* 13825 */ "BLTU\0" /* 13830 */ "SLTU\0" /* 13835 */ "AMMIN__DB_WU\0" /* 13848 */ "AMMAX__DB_WU\0" /* 13861 */ "X86SUB_WU\0" /* 13871 */ "XVSSUB_WU\0" /* 13881 */ "X86ADD_WU\0" /* 13891 */ "XVSADD_WU\0" /* 13901 */ "LD_WU\0" /* 13907 */ "XVMOD_WU\0" /* 13916 */ "XVABSD_WU\0" /* 13926 */ "XVSUBWOD_D_WU\0" /* 13940 */ "XVMADDWOD_D_WU\0" /* 13955 */ "XVADDWOD_D_WU\0" /* 13969 */ "XVMULWOD_D_WU\0" /* 13983 */ "XVSUBWEV_D_WU\0" /* 13997 */ "XVMADDWEV_D_WU\0" /* 14012 */ "XVADDWEV_D_WU\0" /* 14026 */ "XVMULWEV_D_WU\0" /* 14040 */ "MULW_D_WU\0" /* 14050 */ "XVSLE_WU\0" /* 14059 */ "XVAVG_WU\0" /* 14068 */ "MULH_WU\0" /* 14076 */ "XVMUH_WU\0" /* 14085 */ "XVSUBI_WU\0" /* 14095 */ "XVADDI_WU\0" /* 14105 */ "XVSLEI_WU\0" /* 14115 */ "XVMINI_WU\0" /* 14125 */ "XVSLTI_WU\0" /* 14135 */ "XVMAXI_WU\0" /* 14145 */ "ALSL_WU\0" /* 14153 */ "X86MUL_WU\0" /* 14163 */ "AMMIN_WU\0" /* 14172 */ "XVMIN_WU\0" /* 14181 */ "XVPICKVE2GR_WU\0" /* 14196 */ "XVAVGR_WU\0" /* 14206 */ "XVFFINT_S_WU\0" /* 14219 */ "XVSAT_WU\0" /* 14228 */ "XVSLT_WU\0" /* 14237 */ "XVEXTH_DU_WU\0" /* 14250 */ "XVSLLWIL_DU_WU\0" /* 14265 */ "VEXT2XV_DU_WU\0" /* 14279 */ "XVHSUBW_DU_WU\0" /* 14293 */ "XVHADDW_DU_WU\0" /* 14307 */ "XVDIV_WU\0" /* 14316 */ "AMMAX_WU\0" /* 14325 */ "XVMAX_WU\0" /* 14334 */ "LDX_WU\0" /* 14341 */ "G_FDIV\0" /* 14348 */ "G_STRICT_FDIV\0" /* 14362 */ "G_SDIV\0" /* 14369 */ "G_UDIV\0" /* 14376 */ "G_GET_FPENV\0" /* 14388 */ "G_RESET_FPENV\0" /* 14402 */ "G_SET_FPENV\0" /* 14414 */ "XVAND_V\0" /* 14422 */ "XVBITSEL_V\0" /* 14433 */ "XVBSLL_V\0" /* 14442 */ "XVBSRL_V\0" /* 14451 */ "XVANDN_V\0" /* 14460 */ "XVORN_V\0" /* 14468 */ "XVNOR_V\0" /* 14476 */ "XVOR_V\0" /* 14483 */ "XVXOR_V\0" /* 14491 */ "XVSETNEZ_V\0" /* 14502 */ "XVSETEQZ_V\0" /* 14513 */ "REVB_2W\0" /* 14521 */ "REVH_2W\0" /* 14529 */ "G_FPOW\0" /* 14536 */ "XVREPLVE0_W\0" /* 14548 */ "XVINSVE0_W\0" /* 14559 */ "XVADDA_W\0" /* 14568 */ "X86SRA_W\0" /* 14577 */ "ARMSRA_W\0" /* 14586 */ "XVSRA_W\0" /* 14594 */ "AMADD__DB_W\0" /* 14606 */ "AMAND__DB_W\0" /* 14618 */ "AMMIN__DB_W\0" /* 14630 */ "AMSWAP__DB_W\0" /* 14643 */ "AMOR__DB_W\0" /* 14654 */ "AMXOR__DB_W\0" /* 14666 */ "AMCAS__DB_W\0" /* 14678 */ "AMMAX__DB_W\0" /* 14690 */ "X86SUB_W\0" /* 14699 */ "ARMSUB_W\0" /* 14708 */ "XVMSUB_W\0" /* 14717 */ "XVSSUB_W\0" /* 14726 */ "XVSUB_W\0" /* 14734 */ "CRCC_W_B_W\0" /* 14745 */ "CRC_W_B_W\0" /* 14755 */ "X86SBC_W\0" /* 14764 */ "ARMSBC_W\0" /* 14773 */ "X86ADC_W\0" /* 14782 */ "ARMADC_W\0" /* 14791 */ "X86DEC_W\0" /* 14800 */ "X86INC_W\0" /* 14809 */ "SC_W\0" /* 14814 */ "X86ADD_W\0" /* 14823 */ "AMADD_W\0" /* 14831 */ "ARMADD_W\0" /* 14840 */ "XVMADD_W\0" /* 14849 */ "XVSADD_W\0" /* 14858 */ "XVADD_W\0" /* 14866 */ "LD_W\0" /* 14871 */ "X86AND_W\0" /* 14880 */ "AMAND_W\0" /* 14888 */ "ARMAND_W\0" /* 14897 */ "XVPACKOD_W\0" /* 14908 */ "XVPICKOD_W\0" /* 14919 */ "XVMOD_W\0" /* 14927 */ "IOCSRRD_W\0" /* 14937 */ "XVABSD_W\0" /* 14946 */ "XVSUBWOD_D_W\0" /* 14959 */ "XVMADDWOD_D_W\0" /* 14973 */ "XVADDWOD_D_W\0" /* 14986 */ "XVMULWOD_D_W\0" /* 14999 */ "XVFFINTH_D_W\0" /* 15012 */ "XVEXTH_D_W\0" /* 15023 */ "XVSLLWIL_D_W\0" /* 15036 */ "XVFFINTL_D_W\0" /* 15049 */ "FFINT_D_W\0" /* 15059 */ "XVSUBWEV_D_W\0" /* 15072 */ "XVMADDWEV_D_W\0" /* 15086 */ "XVADDWEV_D_W\0" /* 15099 */ "XVMULWEV_D_W\0" /* 15112 */ "VEXT2XV_D_W\0" /* 15124 */ "XVHSUBW_D_W\0" /* 15136 */ "XVHADDW_D_W\0" /* 15148 */ "MULW_D_W\0" /* 15157 */ "CRCC_W_D_W\0" /* 15168 */ "CRC_W_D_W\0" /* 15178 */ "LDLE_W\0" /* 15185 */ "XVSLE_W\0" /* 15193 */ "STLE_W\0" /* 15200 */ "XVPICKVE_W\0" /* 15211 */ "XVREPLVE_W\0" /* 15222 */ "XVSHUF_W\0" /* 15231 */ "XVNEG_W\0" /* 15239 */ "XVAVG_W\0" /* 15247 */ "RDTIMEH_W\0" /* 15257 */ "MULH_W\0" /* 15264 */ "MOVGR2FRH_W\0" /* 15276 */ "XVMUH_W\0" /* 15284 */ "XVILVH_W\0" /* 15293 */ "XVSSRANI_H_W\0" /* 15306 */ "XVSRANI_H_W\0" /* 15318 */ "XVSSRLNI_H_W\0" /* 15331 */ "XVSRLNI_H_W\0" /* 15343 */ "XVSSRARNI_H_W\0" /* 15357 */ "XVSRARNI_H_W\0" /* 15370 */ "XVSSRLRNI_H_W\0" /* 15384 */ "XVSRLRNI_H_W\0" /* 15397 */ "XVSSRAN_H_W\0" /* 15409 */ "XVSRAN_H_W\0" /* 15420 */ "XVSSRLN_H_W\0" /* 15432 */ "XVSRLN_H_W\0" /* 15443 */ "XVSSRARN_H_W\0" /* 15456 */ "XVSRARN_H_W\0" /* 15468 */ "XVSSRLRN_H_W\0" /* 15481 */ "XVSRLRN_H_W\0" /* 15493 */ "CRCC_W_H_W\0" /* 15504 */ "CRC_W_H_W\0" /* 15514 */ "ADDU12I_W\0" /* 15524 */ "LU12I_W\0" /* 15532 */ "XVSHUF4I_W\0" /* 15543 */ "X86SRAI_W\0" /* 15553 */ "ARMSRAI_W\0" /* 15563 */ "XVSRAI_W\0" /* 15572 */ "ADDI_W\0" /* 15579 */ "XVSLEI_W\0" /* 15588 */ "XVREPL128VEI_W\0" /* 15603 */ "VREPLVEI_W\0" /* 15614 */ "X86RCLI_W\0" /* 15624 */ "X86SLLI_W\0" /* 15634 */ "ARMSLLI_W\0" /* 15644 */ "XVSLLI_W\0" /* 15653 */ "PseudoXVREPLI_W\0" /* 15669 */ "PseudoVREPLI_W\0" /* 15684 */ "X86SRLI_W\0" /* 15694 */ "ARMSRLI_W\0" /* 15704 */ "XVSRLI_W\0" /* 15713 */ "X86ROTLI_W\0" /* 15724 */ "PseudoLI_W\0" /* 15735 */ "XVPERMI_W\0" /* 15745 */ "XVMINI_W\0" /* 15754 */ "XVSEQI_W\0" /* 15763 */ "XVSRARI_W\0" /* 15773 */ "X86RCRI_W\0" /* 15783 */ "XVBITCLRI_W\0" /* 15795 */ "XVSRLRI_W\0" /* 15805 */ "X86ROTRI_W\0" /* 15816 */ "ARMROTRI_W\0" /* 15827 */ "XVROTRI_W\0" /* 15837 */ "XVBITSETI_W\0" /* 15849 */ "XVSLTI_W\0" /* 15858 */ "XVBITREVI_W\0" /* 15870 */ "XVMAXI_W\0" /* 15879 */ "BYTEPICK_W\0" /* 15890 */ "BSTRPICK_W\0" /* 15901 */ "X86RCL_W\0" /* 15910 */ "LDL_W\0" /* 15916 */ "RDTIMEL_W\0" /* 15926 */ "SCREL_W\0" /* 15934 */ "X86SLL_W\0" /* 15943 */ "ARMSLL_W\0" /* 15952 */ "XVSLL_W\0" /* 15960 */ "XVLDREPL_W\0" /* 15971 */ "X86SRL_W\0" /* 15980 */ "ARMSRL_W\0" /* 15989 */ "XVSRL_W\0" /* 15997 */ "ALSL_W\0" /* 16004 */ "X86ROTL_W\0" /* 16014 */ "STL_W\0" /* 16020 */ "X86MUL_W\0" /* 16029 */ "XVMUL_W\0" /* 16037 */ "XVILVL_W\0" /* 16046 */ "XVSTELM_W\0" /* 16056 */ "XVPERM_W\0" /* 16065 */ "AMMIN_W\0" /* 16073 */ "XVMIN_W\0" /* 16081 */ "XVCLO_W\0" /* 16089 */ "CTO_W\0" /* 16095 */ "AMSWAP_W\0" /* 16104 */ "LLACQ_W\0" /* 16112 */ "XVSEQ_W\0" /* 16120 */ "XVSRAR_W\0" /* 16129 */ "X86RCR_W\0" /* 16138 */ "LDR_W\0" /* 16144 */ "MOVGR2FR_W\0" /* 16155 */ "XVPICKVE2GR_W\0" /* 16169 */ "XVAVGR_W\0" /* 16178 */ "XVBITCLR_W\0" /* 16189 */ "XVSRLR_W\0" /* 16198 */ "X86OR_W\0" /* 16206 */ "AMOR_W\0" /* 16213 */ "ARMOR_W\0" /* 16221 */ "X86XOR_W\0" /* 16230 */ "AMXOR_W\0" /* 16238 */ "ARMXOR_W\0" /* 16247 */ "X86ROTR_W\0" /* 16257 */ "ARMROTR_W\0" /* 16267 */ "XVROTR_W\0" /* 16276 */ "LDPTR_W\0" /* 16284 */ "STPTR_W\0" /* 16292 */ "STR_W\0" /* 16298 */ "XVREPLGR2VR_W\0" /* 16312 */ "XVINSGR2VR_W\0" /* 16325 */ "IOCSRWR_W\0" /* 16335 */ "AMCAS_W\0" /* 16343 */ "BSTRINS_W\0" /* 16353 */ "XVEXTRINS_W\0" /* 16365 */ "XVFFINT_S_W\0" /* 16377 */ "XVSAT_W\0" /* 16385 */ "XVBITSET_W\0" /* 16396 */ "LDGT_W\0" /* 16403 */ "STGT_W\0" /* 16410 */ "XVSLT_W\0" /* 16418 */ "XVPCNT_W\0" /* 16427 */ "ARMNOT_W\0" /* 16436 */ "ST_W\0" /* 16441 */ "XVSSRANI_HU_W\0" /* 16455 */ "XVSSRLNI_HU_W\0" /* 16469 */ "XVSSRARNI_HU_W\0" /* 16484 */ "XVSSRLRNI_HU_W\0" /* 16499 */ "XVSSRAN_HU_W\0" /* 16512 */ "XVSSRLN_HU_W\0" /* 16525 */ "XVSSRARN_HU_W\0" /* 16539 */ "XVSSRLRN_HU_W\0" /* 16553 */ "XVMADDWOD_D_WU_W\0" /* 16570 */ "XVADDWOD_D_WU_W\0" /* 16586 */ "XVMULWOD_D_WU_W\0" /* 16602 */ "XVMADDWEV_D_WU_W\0" /* 16619 */ "XVADDWEV_D_WU_W\0" /* 16635 */ "XVMULWEV_D_WU_W\0" /* 16651 */ "XVPACKEV_W\0" /* 16662 */ "XVPICKEV_W\0" /* 16673 */ "XVBITREV_W\0" /* 16684 */ "XVDIV_W\0" /* 16692 */ "XVSIGNCOV_W\0" /* 16704 */ "ARMMOV_W\0" /* 16713 */ "CRCC_W_W_W\0" /* 16724 */ "CRC_W_W_W\0" /* 16734 */ "AMMAX_W\0" /* 16742 */ "XVMAX_W\0" /* 16750 */ "LDX_W\0" /* 16756 */ "ARMRRX_W\0" /* 16765 */ "STX_W\0" /* 16771 */ "PseudoXVBZ_W\0" /* 16784 */ "PseudoVBZ_W\0" /* 16796 */ "XVSETALLNEZ_W\0" /* 16810 */ "XVCLZ_W\0" /* 16818 */ "PseudoXVBNZ_W\0" /* 16832 */ "PseudoVBNZ_W\0" /* 16845 */ "XVSETANYEQZ_W\0" /* 16859 */ "CTZ_W\0" /* 16865 */ "XVMSKLTZ_W\0" /* 16876 */ "PseudoAddTPRel_W\0" /* 16893 */ "PseudoAtomicStoreW\0" /* 16912 */ "G_VECREDUCE_FMAX\0" /* 16929 */ "G_ATOMICRMW_FMAX\0" /* 16946 */ "G_VECREDUCE_SMAX\0" /* 16963 */ "G_SMAX\0" /* 16970 */ "G_VECREDUCE_UMAX\0" /* 16987 */ "G_UMAX\0" /* 16994 */ "G_ATOMICRMW_UMAX\0" /* 17011 */ "G_ATOMICRMW_MAX\0" /* 17027 */ "PRELDX\0" /* 17034 */ "XVLDX\0" /* 17040 */ "G_FRAME_INDEX\0" /* 17054 */ "G_SBFX\0" /* 17061 */ "G_UBFX\0" /* 17068 */ "G_SMULFIX\0" /* 17078 */ "G_UMULFIX\0" /* 17088 */ "G_SDIVFIX\0" /* 17098 */ "G_UDIVFIX\0" /* 17108 */ "XVSTX\0" /* 17114 */ "G_MEMCPY\0" /* 17123 */ "COPY\0" /* 17128 */ "CONVERGENCECTRL_ENTRY\0" /* 17150 */ "PseudoXVBZ\0" /* 17161 */ "PseudoVBZ\0" /* 17171 */ "BNEZ\0" /* 17176 */ "BCNEZ\0" /* 17182 */ "MASKNEZ\0" /* 17190 */ "G_CTLZ\0" /* 17197 */ "PseudoXVBNZ\0" /* 17209 */ "PseudoVBNZ\0" /* 17220 */ "BEQZ\0" /* 17225 */ "BCEQZ\0" /* 17231 */ "MASKEQZ\0" /* 17239 */ "G_CTTZ\0" /* 17246 */ "PseudoTAILIndirect\0" /* 17265 */ "PseudoCALLIndirect\0" }; #ifdef __GNUC__ #pragma GCC diagnostic pop #endif extern const unsigned LoongArchInstrNameIndices[] = { 8508U, 9072U, 10086U, 9419U, 8618U, 8599U, 8627U, 8879U, 6468U, 6483U, 6384U, 6510U, 10730U, 6200U, 12436U, 6397U, 8504U, 8608U, 5677U, 17123U, 6038U, 12340U, 2597U, 5628U, 5665U, 9539U, 8848U, 12237U, 2694U, 9802U, 6589U, 12226U, 6094U, 9775U, 9762U, 10166U, 12067U, 12100U, 8764U, 8827U, 8800U, 8644U, 6185U, 10131U, 9493U, 17128U, 10367U, 9695U, 6248U, 12471U, 12501U, 9262U, 2457U, 638U, 8987U, 14362U, 14369U, 9038U, 9045U, 9052U, 9062U, 2575U, 10542U, 10505U, 6382U, 8506U, 17040U, 6210U, 6225U, 8884U, 12035U, 10666U, 12377U, 10683U, 10442U, 2217U, 10713U, 12248U, 10594U, 12409U, 6312U, 10142U, 2668U, 2191U, 2650U, 12286U, 12267U, 9240U, 10191U, 10210U, 2358U, 2302U, 2332U, 2343U, 2283U, 2313U, 6150U, 6134U, 10760U, 6531U, 6557U, 2473U, 644U, 2581U, 2542U, 10547U, 10511U, 17011U, 9388U, 16994U, 9371U, 2424U, 621U, 16929U, 9306U, 9601U, 9579U, 5657U, 6630U, 2622U, 12054U, 12355U, 2169U, 10808U, 12203U, 10835U, 12485U, 2209U, 12192U, 12180U, 12330U, 6581U, 12464U, 6497U, 12494U, 8686U, 10347U, 10333U, 8679U, 10340U, 10587U, 8905U, 9656U, 9649U, 9663U, 9670U, 12045U, 9485U, 5698U, 9469U, 5649U, 9477U, 5690U, 9461U, 5641U, 9523U, 9515U, 6649U, 6641U, 11953U, 11943U, 11933U, 11923U, 11973U, 11963U, 17068U, 17078U, 11983U, 11996U, 17088U, 17098U, 12009U, 12022U, 2382U, 600U, 8929U, 554U, 2276U, 14341U, 9017U, 14529U, 8546U, 9846U, 453U, 9U, 6574U, 445U, 0U, 9821U, 9853U, 6461U, 12456U, 2181U, 8517U, 8531U, 9631U, 9640U, 10618U, 9277U, 10747U, 6321U, 9200U, 9210U, 5747U, 5762U, 9157U, 9189U, 14376U, 14402U, 14388U, 5706U, 5734U, 5719U, 2463U, 8576U, 9340U, 16963U, 9364U, 16987U, 10660U, 2641U, 2631U, 10081U, 12124U, 6011U, 10423U, 10403U, 12156U, 12135U, 10457U, 10474U, 10790U, 17239U, 6364U, 17190U, 6346U, 9716U, 9623U, 6172U, 8732U, 10706U, 9412U, 9228U, 10698U, 9404U, 9220U, 6673U, 6665U, 6657U, 12386U, 10394U, 12259U, 12304U, 12419U, 10118U, 6020U, 2238U, 6282U, 6119U, 2410U, 607U, 8957U, 14348U, 9024U, 560U, 12394U, 9830U, 10230U, 10246U, 17114U, 6065U, 6294U, 12091U, 9531U, 9572U, 9548U, 9560U, 2389U, 8936U, 2365U, 8912U, 16912U, 9289U, 9168U, 9136U, 2441U, 8971U, 2559U, 10527U, 10489U, 16946U, 9323U, 16970U, 9347U, 17054U, 17061U, 9444U, 9787U, 5584U, 16876U, 110U, 132U, 183U, 489U, 345U, 60U, 366U, 5601U, 16893U, 326U, 10099U, 2610U, 8692U, 8860U, 541U, 17265U, 5912U, 9118U, 228U, 512U, 10289U, 8748U, 8784U, 8705U, 10625U, 5929U, 12317U, 5976U, 8664U, 5874U, 10638U, 5948U, 2255U, 5781U, 2489U, 5808U, 5995U, 5852U, 2526U, 5830U, 6045U, 10263U, 3693U, 15724U, 82U, 417U, 273U, 154U, 32U, 388U, 244U, 301U, 206U, 12081U, 10276U, 8721U, 528U, 17246U, 5895U, 9100U, 9677U, 17209U, 2121U, 5528U, 8418U, 16832U, 17161U, 2062U, 5480U, 8370U, 16784U, 1296U, 3648U, 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12741U, 3807U, 13105U, 7489U, 13508U, 15849U, 14125U, 1836U, 12813U, 4748U, 13301U, 7878U, 13580U, 16410U, 14228U, 1186U, 3542U, 7251U, 15563U, 6814U, 9912U, 15306U, 5187U, 6917U, 15409U, 5304U, 1370U, 3732U, 7414U, 15763U, 6865U, 9963U, 15357U, 5238U, 6964U, 15456U, 5351U, 1644U, 4407U, 7662U, 16120U, 690U, 2775U, 6721U, 14586U, 1321U, 3673U, 7365U, 15704U, 6839U, 9937U, 15331U, 5212U, 6940U, 15432U, 5327U, 1402U, 3764U, 7446U, 15795U, 6892U, 9990U, 15384U, 5265U, 6989U, 15481U, 5376U, 1695U, 4487U, 7713U, 16189U, 1547U, 3919U, 7565U, 15989U, 7900U, 6801U, 10013U, 9899U, 16441U, 15293U, 4969U, 5174U, 7958U, 6905U, 16499U, 15397U, 5027U, 5292U, 7928U, 6851U, 10041U, 9949U, 16469U, 15343U, 4997U, 5224U, 7984U, 6951U, 16525U, 15443U, 5053U, 5338U, 7914U, 6826U, 10027U, 9924U, 16455U, 15318U, 4983U, 5199U, 7971U, 6928U, 16512U, 15420U, 5040U, 5315U, 7943U, 6878U, 10056U, 9976U, 16484U, 15370U, 5012U, 5251U, 7998U, 6976U, 16539U, 15468U, 5067U, 5363U, 753U, 12515U, 2957U, 12981U, 6784U, 13396U, 14717U, 13871U, 12451U, 1591U, 4054U, 7609U, 16046U, 17108U, 12701U, 13065U, 13468U, 14085U, 15059U, 13983U, 1076U, 12644U, 4330U, 13210U, 8248U, 13739U, 14946U, 13926U, 999U, 12587U, 4255U, 13153U, 8163U, 13682U, 762U, 2966U, 6793U, 9878U, 14726U, 1429U, 14483U, }; static inline void InitLoongArchMCInstrInfo(MCInstrInfo *II) { II->InitMCInstrInfo(LoongArchDescs.Insts, LoongArchInstrNameIndices, LoongArchInstrNameData, nullptr, nullptr, 2429); } } // end namespace llvm #endif // GET_INSTRINFO_MC_DESC #ifdef GET_INSTRINFO_HEADER #undef GET_INSTRINFO_HEADER namespace llvm { struct LoongArchGenInstrInfo : public TargetInstrInfo { explicit LoongArchGenInstrInfo(unsigned CFSetupOpcode = ~0u, unsigned CFDestroyOpcode = ~0u, unsigned CatchRetOpcode = ~0u, unsigned ReturnOpcode = ~0u); ~LoongArchGenInstrInfo() override = default; }; } // end namespace llvm #endif // GET_INSTRINFO_HEADER #ifdef GET_INSTRINFO_HELPER_DECLS #undef GET_INSTRINFO_HELPER_DECLS #endif // GET_INSTRINFO_HELPER_DECLS #ifdef GET_INSTRINFO_HELPERS #undef GET_INSTRINFO_HELPERS #endif // GET_INSTRINFO_HELPERS #ifdef GET_INSTRINFO_CTOR_DTOR #undef GET_INSTRINFO_CTOR_DTOR namespace llvm { extern const LoongArchInstrTable LoongArchDescs; extern const unsigned LoongArchInstrNameIndices[]; extern const char LoongArchInstrNameData[]; LoongArchGenInstrInfo::LoongArchGenInstrInfo(unsigned CFSetupOpcode, unsigned CFDestroyOpcode, unsigned CatchRetOpcode, unsigned ReturnOpcode) : TargetInstrInfo(CFSetupOpcode, CFDestroyOpcode, CatchRetOpcode, ReturnOpcode) { InitMCInstrInfo(LoongArchDescs.Insts, LoongArchInstrNameIndices, LoongArchInstrNameData, nullptr, nullptr, 2429); } } // end namespace llvm #endif // GET_INSTRINFO_CTOR_DTOR #ifdef GET_INSTRINFO_OPERAND_ENUM #undef GET_INSTRINFO_OPERAND_ENUM namespace llvm { namespace LoongArch { namespace OpName { enum { OPERAND_LAST }; } // end namespace OpName } // end namespace LoongArch } // end namespace llvm #endif //GET_INSTRINFO_OPERAND_ENUM #ifdef GET_INSTRINFO_NAMED_OPS #undef GET_INSTRINFO_NAMED_OPS namespace llvm { namespace LoongArch { LLVM_READONLY int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx) { return -1; } } // end namespace LoongArch } // end namespace llvm #endif //GET_INSTRINFO_NAMED_OPS #ifdef GET_INSTRINFO_OPERAND_TYPES_ENUM #undef GET_INSTRINFO_OPERAND_TYPES_ENUM namespace llvm { namespace LoongArch { namespace OpTypes { enum OperandType { bare_symbol = 0, f32imm = 1, f64imm = 2, grlenimm = 3, i1imm = 4, i8imm = 5, i16imm = 6, i32imm = 7, i64imm = 8, imm32 = 9, imm64 = 10, ptype0 = 11, ptype1 = 12, ptype2 = 13, ptype3 = 14, ptype4 = 15, ptype5 = 16, simm5 = 17, simm8 = 18, simm8_lsl1 = 19, simm8_lsl2 = 20, simm8_lsl3 = 21, simm9_lsl3 = 22, simm10 = 23, simm10_lsl2 = 24, simm11_lsl1 = 25, simm12 = 26, simm12_addlike = 27, simm12_lu52id = 28, simm13 = 29, simm14_lsl2 = 30, simm16 = 31, simm16_lsl2 = 32, simm16_lsl2_br = 33, simm16_lsl16 = 34, simm20 = 35, simm20_lu12iw = 36, simm20_lu32id = 37, simm20_pcaddi = 38, simm20_pcaddu18i = 39, simm20_pcalau12i = 40, simm21_lsl2 = 41, simm26_b = 42, simm26_symbol = 43, simm32_hi16_lo12 = 44, tprel_add_symbol = 45, type0 = 46, type1 = 47, type2 = 48, type3 = 49, type4 = 50, type5 = 51, uimm1 = 52, uimm2 = 53, uimm2_plus1 = 54, uimm3 = 55, uimm4 = 56, uimm5 = 57, uimm6 = 58, uimm7 = 59, uimm8 = 60, uimm12 = 61, uimm12_ori = 62, uimm14 = 63, uimm15 = 64, untyped_imm_0 = 65, GPRMemAtomic = 66, CFR = 67, FCSR = 68, FPR32 = 69, FPR64 = 70, GPR = 71, GPRT = 72, LASX256 = 73, LSX128 = 74, SCR = 75, OPERAND_TYPE_LIST_END }; } // end namespace OpTypes } // end namespace LoongArch } // end namespace llvm #endif // GET_INSTRINFO_OPERAND_TYPES_ENUM #ifdef GET_INSTRINFO_OPERAND_TYPE #undef GET_INSTRINFO_OPERAND_TYPE namespace llvm { namespace LoongArch { LLVM_READONLY static int getOperandType(uint16_t Opcode, uint16_t OpIdx) { static const uint16_t Offsets[] = { /* PHI */ 0, /* INLINEASM */ 1, /* INLINEASM_BR */ 1, /* CFI_INSTRUCTION */ 1, /* EH_LABEL */ 2, /* GC_LABEL */ 3, /* ANNOTATION_LABEL */ 4, /* KILL */ 5, /* EXTRACT_SUBREG */ 5, /* INSERT_SUBREG */ 8, /* IMPLICIT_DEF */ 12, /* SUBREG_TO_REG */ 13, /* COPY_TO_REGCLASS */ 17, /* DBG_VALUE */ 20, /* DBG_VALUE_LIST */ 20, /* DBG_INSTR_REF */ 20, /* DBG_PHI */ 20, /* DBG_LABEL */ 20, /* REG_SEQUENCE */ 21, /* COPY */ 23, /* BUNDLE */ 25, /* LIFETIME_START */ 25, /* LIFETIME_END */ 26, /* PSEUDO_PROBE */ 27, /* ARITH_FENCE */ 31, /* STACKMAP */ 33, /* FENTRY_CALL */ 35, /* PATCHPOINT */ 35, /* LOAD_STACK_GUARD */ 41, /* PREALLOCATED_SETUP */ 42, /* PREALLOCATED_ARG */ 43, /* STATEPOINT */ 46, /* LOCAL_ESCAPE */ 46, /* FAULTING_OP */ 48, /* PATCHABLE_OP */ 49, /* PATCHABLE_FUNCTION_ENTER */ 49, /* PATCHABLE_RET */ 49, /* PATCHABLE_FUNCTION_EXIT */ 49, /* PATCHABLE_TAIL_CALL */ 49, /* PATCHABLE_EVENT_CALL */ 49, /* PATCHABLE_TYPED_EVENT_CALL */ 51, /* ICALL_BRANCH_FUNNEL */ 54, /* FAKE_USE */ 54, /* MEMBARRIER */ 54, /* JUMP_TABLE_DEBUG_INFO */ 54, /* CONVERGENCECTRL_ENTRY */ 55, /* CONVERGENCECTRL_ANCHOR */ 56, /* CONVERGENCECTRL_LOOP */ 57, /* CONVERGENCECTRL_GLUE */ 59, /* G_ASSERT_SEXT */ 60, /* G_ASSERT_ZEXT */ 63, /* G_ASSERT_ALIGN */ 66, /* G_ADD */ 69, /* G_SUB */ 72, /* G_MUL */ 75, /* G_SDIV */ 78, /* G_UDIV */ 81, /* G_SREM */ 84, /* G_UREM */ 87, /* G_SDIVREM */ 90, /* G_UDIVREM */ 94, /* G_AND */ 98, /* G_OR */ 101, /* G_XOR */ 104, /* G_IMPLICIT_DEF */ 107, /* G_PHI */ 108, /* G_FRAME_INDEX */ 109, /* G_GLOBAL_VALUE */ 111, /* G_PTRAUTH_GLOBAL_VALUE */ 113, /* G_CONSTANT_POOL */ 118, /* G_EXTRACT */ 120, /* G_UNMERGE_VALUES */ 123, /* G_INSERT */ 125, /* G_MERGE_VALUES */ 129, /* G_BUILD_VECTOR */ 131, /* G_BUILD_VECTOR_TRUNC */ 133, /* G_CONCAT_VECTORS */ 135, /* G_PTRTOINT */ 137, /* G_INTTOPTR */ 139, /* G_BITCAST */ 141, /* G_FREEZE */ 143, /* G_CONSTANT_FOLD_BARRIER */ 145, /* G_INTRINSIC_FPTRUNC_ROUND */ 147, /* G_INTRINSIC_TRUNC */ 150, /* G_INTRINSIC_ROUND */ 152, /* G_INTRINSIC_LRINT */ 154, /* G_INTRINSIC_LLRINT */ 156, /* G_INTRINSIC_ROUNDEVEN */ 158, /* G_READCYCLECOUNTER */ 160, /* G_READSTEADYCOUNTER */ 161, /* G_LOAD */ 162, /* G_SEXTLOAD */ 164, /* G_ZEXTLOAD */ 166, /* G_INDEXED_LOAD */ 168, /* G_INDEXED_SEXTLOAD */ 173, /* G_INDEXED_ZEXTLOAD */ 178, /* G_STORE */ 183, /* G_INDEXED_STORE */ 185, /* G_ATOMIC_CMPXCHG_WITH_SUCCESS */ 190, /* G_ATOMIC_CMPXCHG */ 195, /* G_ATOMICRMW_XCHG */ 199, /* G_ATOMICRMW_ADD */ 202, /* G_ATOMICRMW_SUB */ 205, /* G_ATOMICRMW_AND */ 208, /* G_ATOMICRMW_NAND */ 211, /* G_ATOMICRMW_OR */ 214, /* G_ATOMICRMW_XOR */ 217, /* G_ATOMICRMW_MAX */ 220, /* G_ATOMICRMW_MIN */ 223, /* G_ATOMICRMW_UMAX */ 226, /* G_ATOMICRMW_UMIN */ 229, /* G_ATOMICRMW_FADD */ 232, /* G_ATOMICRMW_FSUB */ 235, /* G_ATOMICRMW_FMAX */ 238, /* G_ATOMICRMW_FMIN */ 241, /* G_ATOMICRMW_UINC_WRAP */ 244, /* G_ATOMICRMW_UDEC_WRAP */ 247, /* G_FENCE */ 250, /* G_PREFETCH */ 252, /* G_BRCOND */ 256, /* G_BRINDIRECT */ 258, /* G_INVOKE_REGION_START */ 259, /* G_INTRINSIC */ 259, /* G_INTRINSIC_W_SIDE_EFFECTS */ 260, /* G_INTRINSIC_CONVERGENT */ 261, /* G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS */ 262, /* G_ANYEXT */ 263, /* G_TRUNC */ 265, /* G_CONSTANT */ 267, /* G_FCONSTANT */ 269, /* G_VASTART */ 271, /* G_VAARG */ 272, /* G_SEXT */ 275, /* G_SEXT_INREG */ 277, /* G_ZEXT */ 280, /* G_SHL */ 282, /* G_LSHR */ 285, /* G_ASHR */ 288, /* G_FSHL */ 291, /* G_FSHR */ 295, /* G_ROTR */ 299, /* G_ROTL */ 302, /* G_ICMP */ 305, /* G_FCMP */ 309, /* G_SCMP */ 313, /* G_UCMP */ 316, /* G_SELECT */ 319, /* G_UADDO */ 323, /* G_UADDE */ 327, /* G_USUBO */ 332, /* G_USUBE */ 336, /* G_SADDO */ 341, /* G_SADDE */ 345, /* G_SSUBO */ 350, /* G_SSUBE */ 354, /* G_UMULO */ 359, /* G_SMULO */ 363, /* G_UMULH */ 367, /* G_SMULH */ 370, /* G_UADDSAT */ 373, /* G_SADDSAT */ 376, /* G_USUBSAT */ 379, /* G_SSUBSAT */ 382, /* G_USHLSAT */ 385, /* G_SSHLSAT */ 388, /* G_SMULFIX */ 391, /* G_UMULFIX */ 395, /* G_SMULFIXSAT */ 399, /* G_UMULFIXSAT */ 403, /* G_SDIVFIX */ 407, /* G_UDIVFIX */ 411, /* G_SDIVFIXSAT */ 415, /* G_UDIVFIXSAT */ 419, /* G_FADD */ 423, /* G_FSUB */ 426, /* G_FMUL */ 429, /* G_FMA */ 432, /* G_FMAD */ 436, /* G_FDIV */ 440, /* G_FREM */ 443, /* G_FPOW */ 446, /* G_FPOWI */ 449, /* G_FEXP */ 452, /* G_FEXP2 */ 454, /* G_FEXP10 */ 456, /* G_FLOG */ 458, /* G_FLOG2 */ 460, /* G_FLOG10 */ 462, /* G_FLDEXP */ 464, /* G_FFREXP */ 467, /* G_FNEG */ 470, /* G_FPEXT */ 472, /* G_FPTRUNC */ 474, /* G_FPTOSI */ 476, /* G_FPTOUI */ 478, /* G_SITOFP */ 480, /* G_UITOFP */ 482, /* G_FABS */ 484, /* G_FCOPYSIGN */ 486, /* G_IS_FPCLASS */ 489, /* G_FCANONICALIZE */ 492, /* G_FMINNUM */ 494, /* G_FMAXNUM */ 497, /* G_FMINNUM_IEEE */ 500, /* G_FMAXNUM_IEEE */ 503, /* G_FMINIMUM */ 506, /* G_FMAXIMUM */ 509, /* G_GET_FPENV */ 512, /* G_SET_FPENV */ 513, /* G_RESET_FPENV */ 514, /* G_GET_FPMODE */ 514, /* G_SET_FPMODE */ 515, /* G_RESET_FPMODE */ 516, /* G_PTR_ADD */ 516, /* G_PTRMASK */ 519, /* G_SMIN */ 522, /* G_SMAX */ 525, /* G_UMIN */ 528, /* G_UMAX */ 531, /* G_ABS */ 534, /* G_LROUND */ 536, /* G_LLROUND */ 538, /* G_BR */ 540, /* G_BRJT */ 541, /* G_VSCALE */ 544, /* G_INSERT_SUBVECTOR */ 546, /* G_EXTRACT_SUBVECTOR */ 550, /* G_INSERT_VECTOR_ELT */ 553, /* G_EXTRACT_VECTOR_ELT */ 557, /* G_SHUFFLE_VECTOR */ 560, /* G_SPLAT_VECTOR */ 564, /* G_VECTOR_COMPRESS */ 566, /* G_CTTZ */ 570, /* G_CTTZ_ZERO_UNDEF */ 572, /* G_CTLZ */ 574, /* G_CTLZ_ZERO_UNDEF */ 576, /* G_CTPOP */ 578, /* G_BSWAP */ 580, /* G_BITREVERSE */ 582, /* G_FCEIL */ 584, /* G_FCOS */ 586, /* G_FSIN */ 588, /* G_FTAN */ 590, /* G_FACOS */ 592, /* G_FASIN */ 594, /* G_FATAN */ 596, /* G_FCOSH */ 598, /* G_FSINH */ 600, /* G_FTANH */ 602, /* G_FSQRT */ 604, /* G_FFLOOR */ 606, /* G_FRINT */ 608, /* G_FNEARBYINT */ 610, /* G_ADDRSPACE_CAST */ 612, /* G_BLOCK_ADDR */ 614, /* G_JUMP_TABLE */ 616, /* G_DYN_STACKALLOC */ 618, /* G_STACKSAVE */ 621, /* G_STACKRESTORE */ 622, /* G_STRICT_FADD */ 623, /* G_STRICT_FSUB */ 626, /* G_STRICT_FMUL */ 629, /* G_STRICT_FDIV */ 632, /* G_STRICT_FREM */ 635, /* G_STRICT_FMA */ 638, /* G_STRICT_FSQRT */ 642, /* G_STRICT_FLDEXP */ 644, /* G_READ_REGISTER */ 647, /* G_WRITE_REGISTER */ 649, /* G_MEMCPY */ 651, /* G_MEMCPY_INLINE */ 655, /* G_MEMMOVE */ 658, /* G_MEMSET */ 662, /* G_BZERO */ 666, /* G_TRAP */ 669, /* G_DEBUGTRAP */ 669, /* G_UBSANTRAP */ 669, /* G_VECREDUCE_SEQ_FADD */ 670, /* G_VECREDUCE_SEQ_FMUL */ 673, /* G_VECREDUCE_FADD */ 676, /* G_VECREDUCE_FMUL */ 678, /* G_VECREDUCE_FMAX */ 680, /* G_VECREDUCE_FMIN */ 682, /* G_VECREDUCE_FMAXIMUM */ 684, /* G_VECREDUCE_FMINIMUM */ 686, /* G_VECREDUCE_ADD */ 688, /* G_VECREDUCE_MUL */ 690, /* G_VECREDUCE_AND */ 692, /* G_VECREDUCE_OR */ 694, /* G_VECREDUCE_XOR */ 696, /* G_VECREDUCE_SMAX */ 698, /* G_VECREDUCE_SMIN */ 700, /* G_VECREDUCE_UMAX */ 702, /* G_VECREDUCE_UMIN */ 704, /* G_SBFX */ 706, /* G_UBFX */ 710, /* ADJCALLSTACKDOWN */ 714, /* ADJCALLSTACKUP */ 716, /* PseudoAddTPRel_D */ 718, /* PseudoAddTPRel_W */ 722, /* PseudoAtomicLoadAdd32 */ 726, /* PseudoAtomicLoadAnd32 */ 731, /* PseudoAtomicLoadNand32 */ 736, /* PseudoAtomicLoadNand64 */ 741, /* PseudoAtomicLoadOr32 */ 746, /* PseudoAtomicLoadSub32 */ 751, /* PseudoAtomicLoadXor32 */ 756, /* PseudoAtomicStoreD */ 761, /* PseudoAtomicStoreW */ 764, /* PseudoAtomicSwap32 */ 767, /* PseudoBR */ 772, /* PseudoBRIND */ 773, /* PseudoB_TAIL */ 775, /* PseudoCALL */ 776, /* PseudoCALL36 */ 777, /* PseudoCALLIndirect */ 778, /* PseudoCALL_LARGE */ 779, /* PseudoCALL_MEDIUM */ 780, /* PseudoCmpXchg32 */ 781, /* PseudoCmpXchg64 */ 787, /* PseudoCopyCFR */ 793, /* PseudoDESC_CALL */ 795, /* PseudoJIRL_CALL */ 798, /* PseudoJIRL_TAIL */ 800, /* PseudoLA_ABS */ 802, /* PseudoLA_ABS_LARGE */ 804, /* PseudoLA_GOT */ 807, /* PseudoLA_GOT_LARGE */ 809, /* PseudoLA_PCREL */ 812, /* PseudoLA_PCREL_LARGE */ 814, /* PseudoLA_TLS_DESC_ABS */ 817, /* PseudoLA_TLS_DESC_ABS_LARGE */ 819, /* PseudoLA_TLS_DESC_PC */ 822, /* PseudoLA_TLS_DESC_PC_LARGE */ 824, /* PseudoLA_TLS_GD */ 827, /* PseudoLA_TLS_GD_LARGE */ 829, /* PseudoLA_TLS_IE */ 832, /* PseudoLA_TLS_IE_LARGE */ 834, /* PseudoLA_TLS_LD */ 837, /* PseudoLA_TLS_LD_LARGE */ 839, /* PseudoLA_TLS_LE */ 842, /* PseudoLD_CFR */ 844, /* PseudoLI_D */ 847, /* PseudoLI_W */ 849, /* PseudoMaskedAtomicLoadAdd32 */ 851, /* PseudoMaskedAtomicLoadMax32 */ 857, /* PseudoMaskedAtomicLoadMin32 */ 865, /* PseudoMaskedAtomicLoadNand32 */ 873, /* PseudoMaskedAtomicLoadSub32 */ 879, /* PseudoMaskedAtomicLoadUMax32 */ 885, /* PseudoMaskedAtomicLoadUMin32 */ 892, /* PseudoMaskedAtomicSwap32 */ 899, /* PseudoMaskedCmpXchg32 */ 905, /* PseudoRET */ 912, /* PseudoST_CFR */ 912, /* PseudoTAIL */ 915, /* PseudoTAIL36 */ 916, /* PseudoTAILIndirect */ 918, /* PseudoTAIL_LARGE */ 919, /* PseudoTAIL_MEDIUM */ 920, /* PseudoUNIMP */ 921, /* PseudoVBNZ */ 921, /* PseudoVBNZ_B */ 923, /* PseudoVBNZ_D */ 925, /* PseudoVBNZ_H */ 927, /* PseudoVBNZ_W */ 929, /* PseudoVBZ */ 931, /* PseudoVBZ_B */ 933, /* PseudoVBZ_D */ 935, /* PseudoVBZ_H */ 937, /* PseudoVBZ_W */ 939, /* PseudoVREPLI_B */ 941, /* PseudoVREPLI_D */ 943, /* PseudoVREPLI_H */ 945, /* PseudoVREPLI_W */ 947, /* PseudoXVBNZ */ 949, /* PseudoXVBNZ_B */ 951, /* PseudoXVBNZ_D */ 953, /* PseudoXVBNZ_H */ 955, /* PseudoXVBNZ_W */ 957, /* PseudoXVBZ */ 959, /* PseudoXVBZ_B */ 961, /* PseudoXVBZ_D */ 963, /* PseudoXVBZ_H */ 965, /* PseudoXVBZ_W */ 967, /* PseudoXVINSGR2VR_B */ 969, /* PseudoXVINSGR2VR_H */ 973, /* PseudoXVREPLI_B */ 977, /* PseudoXVREPLI_D */ 979, /* PseudoXVREPLI_H */ 981, /* PseudoXVREPLI_W */ 983, /* RDFCSR */ 985, /* WRFCSR */ 987, /* ADC_B */ 989, /* ADC_D */ 992, /* ADC_H */ 995, /* ADC_W */ 998, /* ADDI_D */ 1001, /* ADDI_W */ 1004, /* ADDU12I_D */ 1007, /* ADDU12I_W */ 1010, /* ADDU16I_D */ 1013, /* ADD_D */ 1016, /* ADD_W */ 1019, /* ALSL_D */ 1022, /* ALSL_W */ 1026, /* ALSL_WU */ 1030, /* AMADD_B */ 1034, /* AMADD_D */ 1037, /* AMADD_H */ 1040, /* AMADD_W */ 1043, /* AMADD__DB_B */ 1046, /* AMADD__DB_D */ 1049, /* AMADD__DB_H */ 1052, /* AMADD__DB_W */ 1055, /* AMAND_D */ 1058, /* AMAND_W */ 1061, /* AMAND__DB_D */ 1064, /* AMAND__DB_W */ 1067, /* AMCAS_B */ 1070, /* AMCAS_D */ 1073, /* AMCAS_H */ 1076, /* AMCAS_W */ 1079, /* AMCAS__DB_B */ 1082, /* AMCAS__DB_D */ 1085, /* AMCAS__DB_H */ 1088, /* AMCAS__DB_W */ 1091, /* AMMAX_D */ 1094, /* AMMAX_DU */ 1097, /* AMMAX_W */ 1100, /* AMMAX_WU */ 1103, /* AMMAX__DB_D */ 1106, /* AMMAX__DB_DU */ 1109, /* AMMAX__DB_W */ 1112, /* AMMAX__DB_WU */ 1115, /* AMMIN_D */ 1118, /* AMMIN_DU */ 1121, /* AMMIN_W */ 1124, /* AMMIN_WU */ 1127, /* AMMIN__DB_D */ 1130, /* AMMIN__DB_DU */ 1133, /* AMMIN__DB_W */ 1136, /* AMMIN__DB_WU */ 1139, /* AMOR_D */ 1142, /* AMOR_W */ 1145, /* AMOR__DB_D */ 1148, /* AMOR__DB_W */ 1151, /* AMSWAP_B */ 1154, /* AMSWAP_D */ 1157, /* AMSWAP_H */ 1160, /* AMSWAP_W */ 1163, /* AMSWAP__DB_B */ 1166, /* AMSWAP__DB_D */ 1169, /* AMSWAP__DB_H */ 1172, /* AMSWAP__DB_W */ 1175, /* AMXOR_D */ 1178, /* AMXOR_W */ 1181, /* AMXOR__DB_D */ 1184, /* AMXOR__DB_W */ 1187, /* AND */ 1190, /* ANDI */ 1193, /* ANDN */ 1196, /* ARMADC_W */ 1199, /* ARMADD_W */ 1202, /* ARMAND_W */ 1205, /* ARMMFFLAG */ 1208, /* ARMMOVE */ 1210, /* ARMMOV_D */ 1213, /* ARMMOV_W */ 1215, /* ARMMTFLAG */ 1217, /* ARMNOT_W */ 1219, /* ARMOR_W */ 1221, /* ARMROTRI_W */ 1224, /* ARMROTR_W */ 1227, /* ARMRRX_W */ 1230, /* ARMSBC_W */ 1232, /* ARMSLLI_W */ 1235, /* ARMSLL_W */ 1238, /* ARMSRAI_W */ 1241, /* ARMSRA_W */ 1244, /* ARMSRLI_W */ 1247, /* ARMSRL_W */ 1250, /* ARMSUB_W */ 1253, /* ARMXOR_W */ 1256, /* ASRTGT_D */ 1259, /* ASRTLE_D */ 1261, /* B */ 1263, /* BCEQZ */ 1264, /* BCNEZ */ 1266, /* BEQ */ 1268, /* BEQZ */ 1271, /* BGE */ 1273, /* BGEU */ 1276, /* BITREV_4B */ 1279, /* BITREV_8B */ 1281, /* BITREV_D */ 1283, /* BITREV_W */ 1285, /* BL */ 1287, /* BLT */ 1288, /* BLTU */ 1291, /* BNE */ 1294, /* BNEZ */ 1297, /* BREAK */ 1299, /* BSTRINS_D */ 1300, /* BSTRINS_W */ 1305, /* BSTRPICK_D */ 1310, /* BSTRPICK_W */ 1314, /* BYTEPICK_D */ 1318, /* BYTEPICK_W */ 1322, /* CACOP */ 1326, /* CLO_D */ 1329, /* CLO_W */ 1331, /* CLZ_D */ 1333, /* CLZ_W */ 1335, /* CPUCFG */ 1337, /* CRCC_W_B_W */ 1339, /* CRCC_W_D_W */ 1342, /* CRCC_W_H_W */ 1345, /* CRCC_W_W_W */ 1348, /* CRC_W_B_W */ 1351, /* CRC_W_D_W */ 1354, /* CRC_W_H_W */ 1357, /* CRC_W_W_W */ 1360, /* CSRRD */ 1363, /* CSRWR */ 1365, /* CSRXCHG */ 1368, /* CTO_D */ 1372, /* CTO_W */ 1374, /* CTZ_D */ 1376, /* CTZ_W */ 1378, /* DBAR */ 1380, /* DBCL */ 1381, /* DIV_D */ 1382, /* DIV_DU */ 1385, /* DIV_W */ 1388, /* DIV_WU */ 1391, /* ERTN */ 1394, /* EXT_W_B */ 1394, /* EXT_W_H */ 1396, /* FABS_D */ 1398, /* FABS_S */ 1400, /* FADD_D */ 1402, /* FADD_S */ 1405, /* FCLASS_D */ 1408, /* FCLASS_S */ 1410, /* FCMP_CAF_D */ 1412, /* FCMP_CAF_S */ 1415, /* FCMP_CEQ_D */ 1418, /* FCMP_CEQ_S */ 1421, /* FCMP_CLE_D */ 1424, /* FCMP_CLE_S */ 1427, /* FCMP_CLT_D */ 1430, /* FCMP_CLT_S */ 1433, /* FCMP_CNE_D */ 1436, /* FCMP_CNE_S */ 1439, /* FCMP_COR_D */ 1442, /* FCMP_COR_S */ 1445, /* FCMP_CUEQ_D */ 1448, /* FCMP_CUEQ_S */ 1451, /* FCMP_CULE_D */ 1454, /* FCMP_CULE_S */ 1457, /* FCMP_CULT_D */ 1460, /* FCMP_CULT_S */ 1463, /* FCMP_CUNE_D */ 1466, /* FCMP_CUNE_S */ 1469, /* FCMP_CUN_D */ 1472, /* FCMP_CUN_S */ 1475, /* FCMP_SAF_D */ 1478, /* FCMP_SAF_S */ 1481, /* FCMP_SEQ_D */ 1484, /* FCMP_SEQ_S */ 1487, /* FCMP_SLE_D */ 1490, /* FCMP_SLE_S */ 1493, /* FCMP_SLT_D */ 1496, /* FCMP_SLT_S */ 1499, /* FCMP_SNE_D */ 1502, /* FCMP_SNE_S */ 1505, /* FCMP_SOR_D */ 1508, /* FCMP_SOR_S */ 1511, /* FCMP_SUEQ_D */ 1514, /* FCMP_SUEQ_S */ 1517, /* FCMP_SULE_D */ 1520, /* FCMP_SULE_S */ 1523, /* FCMP_SULT_D */ 1526, /* FCMP_SULT_S */ 1529, /* FCMP_SUNE_D */ 1532, /* FCMP_SUNE_S */ 1535, /* FCMP_SUN_D */ 1538, /* FCMP_SUN_S */ 1541, /* FCOPYSIGN_D */ 1544, /* FCOPYSIGN_S */ 1547, /* FCVT_D_LD */ 1550, /* FCVT_D_S */ 1553, /* FCVT_LD_D */ 1555, /* FCVT_S_D */ 1557, /* FCVT_UD_D */ 1559, /* FDIV_D */ 1561, /* FDIV_S */ 1564, /* FFINT_D_L */ 1567, /* FFINT_D_W */ 1569, /* FFINT_S_L */ 1571, /* FFINT_S_W */ 1573, /* FLDGT_D */ 1575, /* FLDGT_S */ 1578, /* FLDLE_D */ 1581, /* FLDLE_S */ 1584, /* FLDX_D */ 1587, /* FLDX_S */ 1590, /* FLD_D */ 1593, /* FLD_S */ 1596, /* FLOGB_D */ 1599, /* FLOGB_S */ 1601, /* FMADD_D */ 1603, /* FMADD_S */ 1607, /* FMAXA_D */ 1611, /* FMAXA_S */ 1614, /* FMAX_D */ 1617, /* FMAX_S */ 1620, /* FMINA_D */ 1623, /* FMINA_S */ 1626, /* FMIN_D */ 1629, /* FMIN_S */ 1632, /* FMOV_D */ 1635, /* FMOV_S */ 1637, /* FMSUB_D */ 1639, /* FMSUB_S */ 1643, /* FMUL_D */ 1647, /* FMUL_S */ 1650, /* FNEG_D */ 1653, /* FNEG_S */ 1655, /* FNMADD_D */ 1657, /* FNMADD_S */ 1661, /* FNMSUB_D */ 1665, /* FNMSUB_S */ 1669, /* FRECIPE_D */ 1673, /* FRECIPE_S */ 1675, /* FRECIP_D */ 1677, /* FRECIP_S */ 1679, /* FRINT_D */ 1681, /* FRINT_S */ 1683, /* FRSQRTE_D */ 1685, /* FRSQRTE_S */ 1687, /* FRSQRT_D */ 1689, /* FRSQRT_S */ 1691, /* FSCALEB_D */ 1693, /* FSCALEB_S */ 1696, /* FSEL_xD */ 1699, /* FSEL_xS */ 1703, /* FSQRT_D */ 1707, /* FSQRT_S */ 1709, /* FSTGT_D */ 1711, /* FSTGT_S */ 1714, /* FSTLE_D */ 1717, /* FSTLE_S */ 1720, /* FSTX_D */ 1723, /* FSTX_S */ 1726, /* FST_D */ 1729, /* FST_S */ 1732, /* FSUB_D */ 1735, /* FSUB_S */ 1738, /* FTINTRM_L_D */ 1741, /* FTINTRM_L_S */ 1743, /* FTINTRM_W_D */ 1745, /* FTINTRM_W_S */ 1747, /* FTINTRNE_L_D */ 1749, /* FTINTRNE_L_S */ 1751, /* FTINTRNE_W_D */ 1753, /* FTINTRNE_W_S */ 1755, /* FTINTRP_L_D */ 1757, /* FTINTRP_L_S */ 1759, /* FTINTRP_W_D */ 1761, /* FTINTRP_W_S */ 1763, /* FTINTRZ_L_D */ 1765, /* FTINTRZ_L_S */ 1767, /* FTINTRZ_W_D */ 1769, /* FTINTRZ_W_S */ 1771, /* FTINT_L_D */ 1773, /* FTINT_L_S */ 1775, /* FTINT_W_D */ 1777, /* FTINT_W_S */ 1779, /* GCSRRD */ 1781, /* GCSRWR */ 1783, /* GCSRXCHG */ 1786, /* GTLBFLUSH */ 1790, /* HVCL */ 1790, /* IBAR */ 1791, /* IDLE */ 1792, /* INVTLB */ 1793, /* IOCSRRD_B */ 1796, /* IOCSRRD_D */ 1798, /* IOCSRRD_H */ 1800, /* IOCSRRD_W */ 1802, /* IOCSRWR_B */ 1804, /* IOCSRWR_D */ 1806, /* IOCSRWR_H */ 1808, /* IOCSRWR_W */ 1810, /* JIRL */ 1812, /* JISCR0 */ 1815, /* JISCR1 */ 1816, /* LDDIR */ 1817, /* LDGT_B */ 1820, /* LDGT_D */ 1823, /* LDGT_H */ 1826, /* LDGT_W */ 1829, /* LDLE_B */ 1832, /* LDLE_D */ 1835, /* LDLE_H */ 1838, /* LDLE_W */ 1841, /* LDL_D */ 1844, /* LDL_W */ 1847, /* LDPTE */ 1850, /* LDPTR_D */ 1852, /* LDPTR_W */ 1855, /* LDR_D */ 1858, /* LDR_W */ 1861, /* LDX_B */ 1864, /* LDX_BU */ 1867, /* LDX_D */ 1870, /* LDX_H */ 1873, /* LDX_HU */ 1876, /* LDX_W */ 1879, /* LDX_WU */ 1882, /* LD_B */ 1885, /* LD_BU */ 1888, /* LD_D */ 1891, /* LD_H */ 1894, /* LD_HU */ 1897, /* LD_W */ 1900, /* LD_WU */ 1903, /* LLACQ_D */ 1906, /* LLACQ_W */ 1908, /* LL_D */ 1910, /* LL_W */ 1913, /* LU12I_W */ 1916, /* LU32I_D */ 1918, /* LU52I_D */ 1921, /* MASKEQZ */ 1924, /* MASKNEZ */ 1927, /* MOD_D */ 1930, /* MOD_DU */ 1933, /* MOD_W */ 1936, /* MOD_WU */ 1939, /* MOVCF2FR_xS */ 1942, /* MOVCF2GR */ 1944, /* MOVFCSR2GR */ 1946, /* MOVFR2CF_xS */ 1948, /* MOVFR2GR_D */ 1950, /* MOVFR2GR_S */ 1952, /* MOVFR2GR_S_64 */ 1954, /* MOVFRH2GR_S */ 1956, /* MOVGR2CF */ 1958, /* MOVGR2FCSR */ 1960, /* MOVGR2FRH_W */ 1962, /* MOVGR2FR_D */ 1965, /* MOVGR2FR_W */ 1967, /* MOVGR2FR_W_64 */ 1969, /* MOVGR2SCR */ 1971, /* MOVSCR2GR */ 1973, /* MULH_D */ 1975, /* MULH_DU */ 1978, /* MULH_W */ 1981, /* MULH_WU */ 1984, /* MULW_D_W */ 1987, /* MULW_D_WU */ 1990, /* MUL_D */ 1993, /* MUL_W */ 1996, /* NOR */ 1999, /* OR */ 2002, /* ORI */ 2005, /* ORN */ 2008, /* PCADDI */ 2011, /* PCADDU12I */ 2013, /* PCADDU18I */ 2015, /* PCALAU12I */ 2017, /* PRELD */ 2019, /* PRELDX */ 2022, /* RCRI_B */ 2025, /* RCRI_D */ 2028, /* RCRI_H */ 2031, /* RCRI_W */ 2034, /* RCR_B */ 2037, /* RCR_D */ 2040, /* RCR_H */ 2043, /* RCR_W */ 2046, /* RDTIMEH_W */ 2049, /* RDTIMEL_W */ 2051, /* RDTIME_D */ 2053, /* REVB_2H */ 2055, /* REVB_2W */ 2057, /* REVB_4H */ 2059, /* REVB_D */ 2061, /* REVH_2W */ 2063, /* REVH_D */ 2065, /* ROTRI_B */ 2067, /* ROTRI_D */ 2070, /* ROTRI_H */ 2073, /* ROTRI_W */ 2076, /* ROTR_B */ 2079, /* ROTR_D */ 2082, /* ROTR_H */ 2085, /* ROTR_W */ 2088, /* SBC_B */ 2091, /* SBC_D */ 2094, /* SBC_H */ 2097, /* SBC_W */ 2100, /* SCREL_D */ 2103, /* SCREL_W */ 2106, /* SC_D */ 2109, /* SC_Q */ 2113, /* SC_W */ 2117, /* SETARMJ */ 2121, /* SETX86J */ 2123, /* SETX86LOOPE */ 2125, /* SETX86LOOPNE */ 2127, /* SET_CFR_FALSE */ 2129, /* SET_CFR_TRUE */ 2130, /* SLLI_D */ 2131, /* SLLI_W */ 2134, /* SLL_D */ 2137, /* SLL_W */ 2140, /* SLT */ 2143, /* SLTI */ 2146, /* SLTU */ 2149, /* SLTUI */ 2152, /* SRAI_D */ 2155, /* SRAI_W */ 2158, /* SRA_D */ 2161, /* SRA_W */ 2164, /* SRLI_D */ 2167, /* SRLI_W */ 2170, /* SRL_D */ 2173, /* SRL_W */ 2176, /* STGT_B */ 2179, /* STGT_D */ 2182, /* STGT_H */ 2185, /* STGT_W */ 2188, /* STLE_B */ 2191, /* STLE_D */ 2194, /* STLE_H */ 2197, /* STLE_W */ 2200, /* STL_D */ 2203, /* STL_W */ 2206, /* STPTR_D */ 2209, /* STPTR_W */ 2212, /* STR_D */ 2215, /* STR_W */ 2218, /* STX_B */ 2221, /* STX_D */ 2224, /* STX_H */ 2227, /* STX_W */ 2230, /* ST_B */ 2233, /* ST_D */ 2236, /* ST_H */ 2239, /* ST_W */ 2242, /* SUB_D */ 2245, /* SUB_W */ 2248, /* SYSCALL */ 2251, /* TLBCLR */ 2252, /* TLBFILL */ 2252, /* TLBFLUSH */ 2252, /* TLBRD */ 2252, /* TLBSRCH */ 2252, /* TLBWR */ 2252, /* VABSD_B */ 2252, /* VABSD_BU */ 2255, /* VABSD_D */ 2258, /* VABSD_DU */ 2261, /* VABSD_H */ 2264, /* VABSD_HU */ 2267, /* VABSD_W */ 2270, /* VABSD_WU */ 2273, /* VADDA_B */ 2276, /* VADDA_D */ 2279, /* VADDA_H */ 2282, /* VADDA_W */ 2285, /* VADDI_BU */ 2288, /* VADDI_DU */ 2291, /* VADDI_HU */ 2294, /* VADDI_WU */ 2297, /* VADDWEV_D_W */ 2300, /* VADDWEV_D_WU */ 2303, /* VADDWEV_D_WU_W */ 2306, /* VADDWEV_H_B */ 2309, /* VADDWEV_H_BU */ 2312, /* VADDWEV_H_BU_B */ 2315, /* VADDWEV_Q_D */ 2318, /* VADDWEV_Q_DU */ 2321, /* VADDWEV_Q_DU_D */ 2324, /* VADDWEV_W_H */ 2327, /* VADDWEV_W_HU */ 2330, /* VADDWEV_W_HU_H */ 2333, /* VADDWOD_D_W */ 2336, /* VADDWOD_D_WU */ 2339, /* VADDWOD_D_WU_W */ 2342, /* VADDWOD_H_B */ 2345, /* VADDWOD_H_BU */ 2348, /* VADDWOD_H_BU_B */ 2351, /* VADDWOD_Q_D */ 2354, /* VADDWOD_Q_DU */ 2357, /* VADDWOD_Q_DU_D */ 2360, /* VADDWOD_W_H */ 2363, /* VADDWOD_W_HU */ 2366, /* VADDWOD_W_HU_H */ 2369, /* VADD_B */ 2372, /* VADD_D */ 2375, /* VADD_H */ 2378, /* VADD_Q */ 2381, /* VADD_W */ 2384, /* VANDI_B */ 2387, /* VANDN_V */ 2390, /* VAND_V */ 2393, /* VAVGR_B */ 2396, /* VAVGR_BU */ 2399, /* VAVGR_D */ 2402, /* VAVGR_DU */ 2405, /* VAVGR_H */ 2408, /* VAVGR_HU */ 2411, /* VAVGR_W */ 2414, /* VAVGR_WU */ 2417, /* VAVG_B */ 2420, /* VAVG_BU */ 2423, /* VAVG_D */ 2426, /* VAVG_DU */ 2429, /* VAVG_H */ 2432, /* VAVG_HU */ 2435, /* VAVG_W */ 2438, /* VAVG_WU */ 2441, /* VBITCLRI_B */ 2444, /* VBITCLRI_D */ 2447, /* VBITCLRI_H */ 2450, /* VBITCLRI_W */ 2453, /* VBITCLR_B */ 2456, /* VBITCLR_D */ 2459, /* VBITCLR_H */ 2462, /* VBITCLR_W */ 2465, /* VBITREVI_B */ 2468, /* VBITREVI_D */ 2471, /* VBITREVI_H */ 2474, /* VBITREVI_W */ 2477, /* VBITREV_B */ 2480, /* VBITREV_D */ 2483, /* VBITREV_H */ 2486, /* VBITREV_W */ 2489, /* VBITSELI_B */ 2492, /* VBITSEL_V */ 2496, /* VBITSETI_B */ 2500, /* VBITSETI_D */ 2503, /* VBITSETI_H */ 2506, /* VBITSETI_W */ 2509, /* VBITSET_B */ 2512, /* VBITSET_D */ 2515, /* VBITSET_H */ 2518, /* VBITSET_W */ 2521, /* VBSLL_V */ 2524, /* VBSRL_V */ 2527, /* VCLO_B */ 2530, /* VCLO_D */ 2532, /* VCLO_H */ 2534, /* VCLO_W */ 2536, /* VCLZ_B */ 2538, /* VCLZ_D */ 2540, /* VCLZ_H */ 2542, /* VCLZ_W */ 2544, /* VDIV_B */ 2546, /* VDIV_BU */ 2549, /* VDIV_D */ 2552, /* VDIV_DU */ 2555, /* VDIV_H */ 2558, /* VDIV_HU */ 2561, /* VDIV_W */ 2564, /* VDIV_WU */ 2567, /* VEXT2XV_DU_BU */ 2570, /* VEXT2XV_DU_HU */ 2572, /* VEXT2XV_DU_WU */ 2574, /* VEXT2XV_D_B */ 2576, /* VEXT2XV_D_H */ 2578, /* VEXT2XV_D_W */ 2580, /* VEXT2XV_HU_BU */ 2582, /* VEXT2XV_H_B */ 2584, /* VEXT2XV_WU_BU */ 2586, /* VEXT2XV_WU_HU */ 2588, /* VEXT2XV_W_B */ 2590, /* VEXT2XV_W_H */ 2592, /* VEXTH_DU_WU */ 2594, /* VEXTH_D_W */ 2596, /* VEXTH_HU_BU */ 2598, /* VEXTH_H_B */ 2600, /* VEXTH_QU_DU */ 2602, /* VEXTH_Q_D */ 2604, /* VEXTH_WU_HU */ 2606, /* VEXTH_W_H */ 2608, /* VEXTL_QU_DU */ 2610, /* VEXTL_Q_D */ 2612, /* VEXTRINS_B */ 2614, /* VEXTRINS_D */ 2618, /* VEXTRINS_H */ 2622, /* VEXTRINS_W */ 2626, /* VFADD_D */ 2630, /* VFADD_S */ 2633, /* VFCLASS_D */ 2636, /* VFCLASS_S */ 2638, /* VFCMP_CAF_D */ 2640, /* VFCMP_CAF_S */ 2643, /* VFCMP_CEQ_D */ 2646, /* VFCMP_CEQ_S */ 2649, /* VFCMP_CLE_D */ 2652, /* VFCMP_CLE_S */ 2655, /* VFCMP_CLT_D */ 2658, /* VFCMP_CLT_S */ 2661, /* VFCMP_CNE_D */ 2664, /* VFCMP_CNE_S */ 2667, /* VFCMP_COR_D */ 2670, /* VFCMP_COR_S */ 2673, /* VFCMP_CUEQ_D */ 2676, /* VFCMP_CUEQ_S */ 2679, /* VFCMP_CULE_D */ 2682, /* VFCMP_CULE_S */ 2685, /* VFCMP_CULT_D */ 2688, /* VFCMP_CULT_S */ 2691, /* VFCMP_CUNE_D */ 2694, /* VFCMP_CUNE_S */ 2697, /* VFCMP_CUN_D */ 2700, /* VFCMP_CUN_S */ 2703, /* VFCMP_SAF_D */ 2706, /* VFCMP_SAF_S */ 2709, /* VFCMP_SEQ_D */ 2712, /* VFCMP_SEQ_S */ 2715, /* VFCMP_SLE_D */ 2718, /* VFCMP_SLE_S */ 2721, /* VFCMP_SLT_D */ 2724, /* VFCMP_SLT_S */ 2727, /* VFCMP_SNE_D */ 2730, /* VFCMP_SNE_S */ 2733, /* VFCMP_SOR_D */ 2736, /* VFCMP_SOR_S */ 2739, /* VFCMP_SUEQ_D */ 2742, /* VFCMP_SUEQ_S */ 2745, /* VFCMP_SULE_D */ 2748, /* VFCMP_SULE_S */ 2751, /* VFCMP_SULT_D */ 2754, /* VFCMP_SULT_S */ 2757, /* VFCMP_SUNE_D */ 2760, /* VFCMP_SUNE_S */ 2763, /* VFCMP_SUN_D */ 2766, /* VFCMP_SUN_S */ 2769, /* VFCVTH_D_S */ 2772, /* VFCVTH_S_H */ 2774, /* VFCVTL_D_S */ 2776, /* VFCVTL_S_H */ 2778, /* VFCVT_H_S */ 2780, /* VFCVT_S_D */ 2783, /* VFDIV_D */ 2786, /* VFDIV_S */ 2789, /* VFFINTH_D_W */ 2792, /* VFFINTL_D_W */ 2794, /* VFFINT_D_L */ 2796, /* VFFINT_D_LU */ 2798, /* VFFINT_S_L */ 2800, /* VFFINT_S_W */ 2803, /* VFFINT_S_WU */ 2805, /* VFLOGB_D */ 2807, /* VFLOGB_S */ 2809, /* VFMADD_D */ 2811, /* VFMADD_S */ 2815, /* VFMAXA_D */ 2819, /* VFMAXA_S */ 2822, /* VFMAX_D */ 2825, /* VFMAX_S */ 2828, /* VFMINA_D */ 2831, /* VFMINA_S */ 2834, /* VFMIN_D */ 2837, /* VFMIN_S */ 2840, /* VFMSUB_D */ 2843, /* VFMSUB_S */ 2847, /* VFMUL_D */ 2851, /* VFMUL_S */ 2854, /* VFNMADD_D */ 2857, /* VFNMADD_S */ 2861, /* VFNMSUB_D */ 2865, /* VFNMSUB_S */ 2869, /* VFRECIPE_D */ 2873, /* VFRECIPE_S */ 2875, /* VFRECIP_D */ 2877, /* VFRECIP_S */ 2879, /* VFRINTRM_D */ 2881, /* VFRINTRM_S */ 2883, /* VFRINTRNE_D */ 2885, /* VFRINTRNE_S */ 2887, /* VFRINTRP_D */ 2889, /* VFRINTRP_S */ 2891, /* VFRINTRZ_D */ 2893, /* VFRINTRZ_S */ 2895, /* VFRINT_D */ 2897, /* VFRINT_S */ 2899, /* VFRSQRTE_D */ 2901, /* VFRSQRTE_S */ 2903, /* VFRSQRT_D */ 2905, /* VFRSQRT_S */ 2907, /* VFRSTPI_B */ 2909, /* VFRSTPI_H */ 2913, /* VFRSTP_B */ 2917, /* VFRSTP_H */ 2921, /* VFSQRT_D */ 2925, /* VFSQRT_S */ 2927, /* VFSUB_D */ 2929, /* VFSUB_S */ 2932, /* VFTINTH_L_S */ 2935, /* VFTINTL_L_S */ 2937, /* VFTINTRMH_L_S */ 2939, /* VFTINTRML_L_S */ 2941, /* VFTINTRM_L_D */ 2943, /* VFTINTRM_W_D */ 2945, /* VFTINTRM_W_S */ 2948, /* VFTINTRNEH_L_S */ 2950, /* VFTINTRNEL_L_S */ 2952, /* VFTINTRNE_L_D */ 2954, /* VFTINTRNE_W_D */ 2956, /* VFTINTRNE_W_S */ 2959, /* VFTINTRPH_L_S */ 2961, /* VFTINTRPL_L_S */ 2963, /* VFTINTRP_L_D */ 2965, /* VFTINTRP_W_D */ 2967, /* VFTINTRP_W_S */ 2970, /* VFTINTRZH_L_S */ 2972, /* VFTINTRZL_L_S */ 2974, /* VFTINTRZ_LU_D */ 2976, /* VFTINTRZ_L_D */ 2978, /* VFTINTRZ_WU_S */ 2980, /* VFTINTRZ_W_D */ 2982, /* VFTINTRZ_W_S */ 2985, /* VFTINT_LU_D */ 2987, /* VFTINT_L_D */ 2989, /* VFTINT_WU_S */ 2991, /* VFTINT_W_D */ 2993, /* VFTINT_W_S */ 2996, /* VHADDW_DU_WU */ 2998, /* VHADDW_D_W */ 3001, /* VHADDW_HU_BU */ 3004, /* VHADDW_H_B */ 3007, /* VHADDW_QU_DU */ 3010, /* VHADDW_Q_D */ 3013, /* VHADDW_WU_HU */ 3016, /* VHADDW_W_H */ 3019, /* VHSUBW_DU_WU */ 3022, /* VHSUBW_D_W */ 3025, /* VHSUBW_HU_BU */ 3028, /* VHSUBW_H_B */ 3031, /* VHSUBW_QU_DU */ 3034, /* VHSUBW_Q_D */ 3037, /* VHSUBW_WU_HU */ 3040, /* VHSUBW_W_H */ 3043, /* VILVH_B */ 3046, /* VILVH_D */ 3049, /* VILVH_H */ 3052, /* VILVH_W */ 3055, /* VILVL_B */ 3058, /* VILVL_D */ 3061, /* VILVL_H */ 3064, /* VILVL_W */ 3067, /* VINSGR2VR_B */ 3070, /* VINSGR2VR_D */ 3074, /* VINSGR2VR_H */ 3078, /* VINSGR2VR_W */ 3082, /* VLD */ 3086, /* VLDI */ 3089, /* VLDREPL_B */ 3091, /* VLDREPL_D */ 3094, /* VLDREPL_H */ 3097, /* VLDREPL_W */ 3100, /* VLDX */ 3103, /* VMADDWEV_D_W */ 3106, /* VMADDWEV_D_WU */ 3110, /* VMADDWEV_D_WU_W */ 3114, /* VMADDWEV_H_B */ 3118, /* VMADDWEV_H_BU */ 3122, /* VMADDWEV_H_BU_B */ 3126, /* VMADDWEV_Q_D */ 3130, /* VMADDWEV_Q_DU */ 3134, /* VMADDWEV_Q_DU_D */ 3138, /* VMADDWEV_W_H */ 3142, /* VMADDWEV_W_HU */ 3146, /* VMADDWEV_W_HU_H */ 3150, /* VMADDWOD_D_W */ 3154, /* VMADDWOD_D_WU */ 3158, /* VMADDWOD_D_WU_W */ 3162, /* VMADDWOD_H_B */ 3166, /* VMADDWOD_H_BU */ 3170, /* VMADDWOD_H_BU_B */ 3174, /* VMADDWOD_Q_D */ 3178, /* VMADDWOD_Q_DU */ 3182, /* VMADDWOD_Q_DU_D */ 3186, /* VMADDWOD_W_H */ 3190, /* VMADDWOD_W_HU */ 3194, /* VMADDWOD_W_HU_H */ 3198, /* VMADD_B */ 3202, /* VMADD_D */ 3206, /* VMADD_H */ 3210, /* VMADD_W */ 3214, /* VMAXI_B */ 3218, /* VMAXI_BU */ 3221, /* VMAXI_D */ 3224, /* VMAXI_DU */ 3227, /* VMAXI_H */ 3230, /* VMAXI_HU */ 3233, /* VMAXI_W */ 3236, /* VMAXI_WU */ 3239, /* VMAX_B */ 3242, /* VMAX_BU */ 3245, /* VMAX_D */ 3248, /* VMAX_DU */ 3251, /* VMAX_H */ 3254, /* VMAX_HU */ 3257, /* VMAX_W */ 3260, /* VMAX_WU */ 3263, /* VMINI_B */ 3266, /* VMINI_BU */ 3269, /* VMINI_D */ 3272, /* VMINI_DU */ 3275, /* VMINI_H */ 3278, /* VMINI_HU */ 3281, /* VMINI_W */ 3284, /* VMINI_WU */ 3287, /* VMIN_B */ 3290, /* VMIN_BU */ 3293, /* VMIN_D */ 3296, /* VMIN_DU */ 3299, /* VMIN_H */ 3302, /* VMIN_HU */ 3305, /* VMIN_W */ 3308, /* VMIN_WU */ 3311, /* VMOD_B */ 3314, /* VMOD_BU */ 3317, /* VMOD_D */ 3320, /* VMOD_DU */ 3323, /* VMOD_H */ 3326, /* VMOD_HU */ 3329, /* VMOD_W */ 3332, /* VMOD_WU */ 3335, /* VMSKGEZ_B */ 3338, /* VMSKLTZ_B */ 3340, /* VMSKLTZ_D */ 3342, /* VMSKLTZ_H */ 3344, /* VMSKLTZ_W */ 3346, /* VMSKNZ_B */ 3348, /* VMSUB_B */ 3350, /* VMSUB_D */ 3354, /* VMSUB_H */ 3358, /* VMSUB_W */ 3362, /* VMUH_B */ 3366, /* VMUH_BU */ 3369, /* VMUH_D */ 3372, /* VMUH_DU */ 3375, /* VMUH_H */ 3378, /* VMUH_HU */ 3381, /* VMUH_W */ 3384, /* VMUH_WU */ 3387, /* VMULWEV_D_W */ 3390, /* VMULWEV_D_WU */ 3393, /* VMULWEV_D_WU_W */ 3396, /* VMULWEV_H_B */ 3399, /* VMULWEV_H_BU */ 3402, /* VMULWEV_H_BU_B */ 3405, /* VMULWEV_Q_D */ 3408, /* VMULWEV_Q_DU */ 3411, /* VMULWEV_Q_DU_D */ 3414, /* VMULWEV_W_H */ 3417, /* VMULWEV_W_HU */ 3420, /* VMULWEV_W_HU_H */ 3423, /* VMULWOD_D_W */ 3426, /* VMULWOD_D_WU */ 3429, /* VMULWOD_D_WU_W */ 3432, /* VMULWOD_H_B */ 3435, /* VMULWOD_H_BU */ 3438, /* VMULWOD_H_BU_B */ 3441, /* VMULWOD_Q_D */ 3444, /* VMULWOD_Q_DU */ 3447, /* VMULWOD_Q_DU_D */ 3450, /* VMULWOD_W_H */ 3453, /* VMULWOD_W_HU */ 3456, /* VMULWOD_W_HU_H */ 3459, /* VMUL_B */ 3462, /* VMUL_D */ 3465, /* VMUL_H */ 3468, /* VMUL_W */ 3471, /* VNEG_B */ 3474, /* VNEG_D */ 3476, /* VNEG_H */ 3478, /* VNEG_W */ 3480, /* VNORI_B */ 3482, /* VNOR_V */ 3485, /* VORI_B */ 3488, /* VORN_V */ 3491, /* VOR_V */ 3494, /* VPACKEV_B */ 3497, /* VPACKEV_D */ 3500, /* VPACKEV_H */ 3503, /* VPACKEV_W */ 3506, /* VPACKOD_B */ 3509, /* VPACKOD_D */ 3512, /* VPACKOD_H */ 3515, /* VPACKOD_W */ 3518, /* VPCNT_B */ 3521, /* VPCNT_D */ 3523, /* VPCNT_H */ 3525, /* VPCNT_W */ 3527, /* VPERMI_W */ 3529, /* VPICKEV_B */ 3533, /* VPICKEV_D */ 3536, /* VPICKEV_H */ 3539, /* VPICKEV_W */ 3542, /* VPICKOD_B */ 3545, /* VPICKOD_D */ 3548, /* VPICKOD_H */ 3551, /* VPICKOD_W */ 3554, /* VPICKVE2GR_B */ 3557, /* VPICKVE2GR_BU */ 3560, /* VPICKVE2GR_D */ 3563, /* VPICKVE2GR_DU */ 3566, /* VPICKVE2GR_H */ 3569, /* VPICKVE2GR_HU */ 3572, /* VPICKVE2GR_W */ 3575, /* VPICKVE2GR_WU */ 3578, /* VREPLGR2VR_B */ 3581, /* VREPLGR2VR_D */ 3583, /* VREPLGR2VR_H */ 3585, /* VREPLGR2VR_W */ 3587, /* VREPLVEI_B */ 3589, /* VREPLVEI_D */ 3592, /* VREPLVEI_H */ 3595, /* VREPLVEI_W */ 3598, /* VREPLVE_B */ 3601, /* VREPLVE_D */ 3604, /* VREPLVE_H */ 3607, /* VREPLVE_W */ 3610, /* VROTRI_B */ 3613, /* VROTRI_D */ 3616, /* VROTRI_H */ 3619, /* VROTRI_W */ 3622, /* VROTR_B */ 3625, /* VROTR_D */ 3628, /* VROTR_H */ 3631, /* VROTR_W */ 3634, /* VSADD_B */ 3637, /* VSADD_BU */ 3640, /* VSADD_D */ 3643, /* VSADD_DU */ 3646, /* VSADD_H */ 3649, /* VSADD_HU */ 3652, /* VSADD_W */ 3655, /* VSADD_WU */ 3658, /* VSAT_B */ 3661, /* VSAT_BU */ 3664, /* VSAT_D */ 3667, /* VSAT_DU */ 3670, /* VSAT_H */ 3673, /* VSAT_HU */ 3676, /* VSAT_W */ 3679, /* VSAT_WU */ 3682, /* VSEQI_B */ 3685, /* VSEQI_D */ 3688, /* VSEQI_H */ 3691, /* VSEQI_W */ 3694, /* VSEQ_B */ 3697, /* VSEQ_D */ 3700, /* VSEQ_H */ 3703, /* VSEQ_W */ 3706, /* VSETALLNEZ_B */ 3709, /* VSETALLNEZ_D */ 3711, /* VSETALLNEZ_H */ 3713, /* VSETALLNEZ_W */ 3715, /* VSETANYEQZ_B */ 3717, /* VSETANYEQZ_D */ 3719, /* VSETANYEQZ_H */ 3721, /* VSETANYEQZ_W */ 3723, /* VSETEQZ_V */ 3725, /* VSETNEZ_V */ 3727, /* VSHUF4I_B */ 3729, /* VSHUF4I_D */ 3732, /* VSHUF4I_H */ 3736, /* VSHUF4I_W */ 3739, /* VSHUF_B */ 3742, /* VSHUF_D */ 3746, /* VSHUF_H */ 3750, /* VSHUF_W */ 3754, /* VSIGNCOV_B */ 3758, /* VSIGNCOV_D */ 3761, /* VSIGNCOV_H */ 3764, /* VSIGNCOV_W */ 3767, /* VSLEI_B */ 3770, /* VSLEI_BU */ 3773, /* VSLEI_D */ 3776, /* VSLEI_DU */ 3779, /* VSLEI_H */ 3782, /* VSLEI_HU */ 3785, /* VSLEI_W */ 3788, /* VSLEI_WU */ 3791, /* VSLE_B */ 3794, /* VSLE_BU */ 3797, /* VSLE_D */ 3800, /* VSLE_DU */ 3803, /* VSLE_H */ 3806, /* VSLE_HU */ 3809, /* VSLE_W */ 3812, /* VSLE_WU */ 3815, /* VSLLI_B */ 3818, /* VSLLI_D */ 3821, /* VSLLI_H */ 3824, /* VSLLI_W */ 3827, /* VSLLWIL_DU_WU */ 3830, /* VSLLWIL_D_W */ 3833, /* VSLLWIL_HU_BU */ 3836, /* VSLLWIL_H_B */ 3839, /* VSLLWIL_WU_HU */ 3842, /* VSLLWIL_W_H */ 3845, /* VSLL_B */ 3848, /* VSLL_D */ 3851, /* VSLL_H */ 3854, /* VSLL_W */ 3857, /* VSLTI_B */ 3860, /* VSLTI_BU */ 3863, /* VSLTI_D */ 3866, /* VSLTI_DU */ 3869, /* VSLTI_H */ 3872, /* VSLTI_HU */ 3875, /* VSLTI_W */ 3878, /* VSLTI_WU */ 3881, /* VSLT_B */ 3884, /* VSLT_BU */ 3887, /* VSLT_D */ 3890, /* VSLT_DU */ 3893, /* VSLT_H */ 3896, /* VSLT_HU */ 3899, /* VSLT_W */ 3902, /* VSLT_WU */ 3905, /* VSRAI_B */ 3908, /* VSRAI_D */ 3911, /* VSRAI_H */ 3914, /* VSRAI_W */ 3917, /* VSRANI_B_H */ 3920, /* VSRANI_D_Q */ 3924, /* VSRANI_H_W */ 3928, /* VSRANI_W_D */ 3932, /* VSRAN_B_H */ 3936, /* VSRAN_H_W */ 3939, /* VSRAN_W_D */ 3942, /* VSRARI_B */ 3945, /* VSRARI_D */ 3948, /* VSRARI_H */ 3951, /* VSRARI_W */ 3954, /* VSRARNI_B_H */ 3957, /* VSRARNI_D_Q */ 3961, /* VSRARNI_H_W */ 3965, /* VSRARNI_W_D */ 3969, /* VSRARN_B_H */ 3973, /* VSRARN_H_W */ 3976, /* VSRARN_W_D */ 3979, /* VSRAR_B */ 3982, /* VSRAR_D */ 3985, /* VSRAR_H */ 3988, /* VSRAR_W */ 3991, /* VSRA_B */ 3994, /* VSRA_D */ 3997, /* VSRA_H */ 4000, /* VSRA_W */ 4003, /* VSRLI_B */ 4006, /* VSRLI_D */ 4009, /* VSRLI_H */ 4012, /* VSRLI_W */ 4015, /* VSRLNI_B_H */ 4018, /* VSRLNI_D_Q */ 4022, /* VSRLNI_H_W */ 4026, /* VSRLNI_W_D */ 4030, /* VSRLN_B_H */ 4034, /* VSRLN_H_W */ 4037, /* VSRLN_W_D */ 4040, /* VSRLRI_B */ 4043, /* VSRLRI_D */ 4046, /* VSRLRI_H */ 4049, /* VSRLRI_W */ 4052, /* VSRLRNI_B_H */ 4055, /* VSRLRNI_D_Q */ 4059, /* VSRLRNI_H_W */ 4063, /* VSRLRNI_W_D */ 4067, /* VSRLRN_B_H */ 4071, /* VSRLRN_H_W */ 4074, /* VSRLRN_W_D */ 4077, /* VSRLR_B */ 4080, /* VSRLR_D */ 4083, /* VSRLR_H */ 4086, /* VSRLR_W */ 4089, /* VSRL_B */ 4092, /* VSRL_D */ 4095, /* VSRL_H */ 4098, /* VSRL_W */ 4101, /* VSSRANI_BU_H */ 4104, /* VSSRANI_B_H */ 4108, /* VSSRANI_DU_Q */ 4112, /* VSSRANI_D_Q */ 4116, /* VSSRANI_HU_W */ 4120, /* VSSRANI_H_W */ 4124, /* VSSRANI_WU_D */ 4128, /* VSSRANI_W_D */ 4132, /* VSSRAN_BU_H */ 4136, /* VSSRAN_B_H */ 4139, /* VSSRAN_HU_W */ 4142, /* VSSRAN_H_W */ 4145, /* VSSRAN_WU_D */ 4148, /* VSSRAN_W_D */ 4151, /* VSSRARNI_BU_H */ 4154, /* VSSRARNI_B_H */ 4158, /* VSSRARNI_DU_Q */ 4162, /* VSSRARNI_D_Q */ 4166, /* VSSRARNI_HU_W */ 4170, /* VSSRARNI_H_W */ 4174, /* VSSRARNI_WU_D */ 4178, /* VSSRARNI_W_D */ 4182, /* VSSRARN_BU_H */ 4186, /* VSSRARN_B_H */ 4189, /* VSSRARN_HU_W */ 4192, /* VSSRARN_H_W */ 4195, /* VSSRARN_WU_D */ 4198, /* VSSRARN_W_D */ 4201, /* VSSRLNI_BU_H */ 4204, /* VSSRLNI_B_H */ 4208, /* VSSRLNI_DU_Q */ 4212, /* VSSRLNI_D_Q */ 4216, /* VSSRLNI_HU_W */ 4220, /* VSSRLNI_H_W */ 4224, /* VSSRLNI_WU_D */ 4228, /* VSSRLNI_W_D */ 4232, /* VSSRLN_BU_H */ 4236, /* VSSRLN_B_H */ 4239, /* VSSRLN_HU_W */ 4242, /* VSSRLN_H_W */ 4245, /* VSSRLN_WU_D */ 4248, /* VSSRLN_W_D */ 4251, /* VSSRLRNI_BU_H */ 4254, /* VSSRLRNI_B_H */ 4258, /* VSSRLRNI_DU_Q */ 4262, /* VSSRLRNI_D_Q */ 4266, /* VSSRLRNI_HU_W */ 4270, /* VSSRLRNI_H_W */ 4274, /* VSSRLRNI_WU_D */ 4278, /* VSSRLRNI_W_D */ 4282, /* VSSRLRN_BU_H */ 4286, /* VSSRLRN_B_H */ 4289, /* VSSRLRN_HU_W */ 4292, /* VSSRLRN_H_W */ 4295, /* VSSRLRN_WU_D */ 4298, /* VSSRLRN_W_D */ 4301, /* VSSUB_B */ 4304, /* VSSUB_BU */ 4307, /* VSSUB_D */ 4310, /* VSSUB_DU */ 4313, /* VSSUB_H */ 4316, /* VSSUB_HU */ 4319, /* VSSUB_W */ 4322, /* VSSUB_WU */ 4325, /* VST */ 4328, /* VSTELM_B */ 4331, /* VSTELM_D */ 4335, /* VSTELM_H */ 4339, /* VSTELM_W */ 4343, /* VSTX */ 4347, /* VSUBI_BU */ 4350, /* VSUBI_DU */ 4353, /* VSUBI_HU */ 4356, /* VSUBI_WU */ 4359, /* VSUBWEV_D_W */ 4362, /* VSUBWEV_D_WU */ 4365, /* VSUBWEV_H_B */ 4368, /* VSUBWEV_H_BU */ 4371, /* VSUBWEV_Q_D */ 4374, /* VSUBWEV_Q_DU */ 4377, /* VSUBWEV_W_H */ 4380, /* VSUBWEV_W_HU */ 4383, /* VSUBWOD_D_W */ 4386, /* VSUBWOD_D_WU */ 4389, /* VSUBWOD_H_B */ 4392, /* VSUBWOD_H_BU */ 4395, /* VSUBWOD_Q_D */ 4398, /* VSUBWOD_Q_DU */ 4401, /* VSUBWOD_W_H */ 4404, /* VSUBWOD_W_HU */ 4407, /* VSUB_B */ 4410, /* VSUB_D */ 4413, /* VSUB_H */ 4416, /* VSUB_Q */ 4419, /* VSUB_W */ 4422, /* VXORI_B */ 4425, /* VXOR_V */ 4428, /* X86ADC_B */ 4431, /* X86ADC_D */ 4433, /* X86ADC_H */ 4435, /* X86ADC_W */ 4437, /* X86ADD_B */ 4439, /* X86ADD_D */ 4441, /* X86ADD_DU */ 4443, /* X86ADD_H */ 4445, /* X86ADD_W */ 4447, /* X86ADD_WU */ 4449, /* X86AND_B */ 4451, /* X86AND_D */ 4453, /* X86AND_H */ 4455, /* X86AND_W */ 4457, /* X86CLRTM */ 4459, /* X86DECTOP */ 4459, /* X86DEC_B */ 4459, /* X86DEC_D */ 4460, /* X86DEC_H */ 4461, /* X86DEC_W */ 4462, /* X86INCTOP */ 4463, /* X86INC_B */ 4463, /* X86INC_D */ 4464, /* X86INC_H */ 4465, /* X86INC_W */ 4466, /* X86MFFLAG */ 4467, /* X86MFTOP */ 4469, /* X86MTFLAG */ 4470, /* X86MTTOP */ 4472, /* X86MUL_B */ 4473, /* X86MUL_BU */ 4475, /* X86MUL_D */ 4477, /* X86MUL_DU */ 4479, /* X86MUL_H */ 4481, /* X86MUL_HU */ 4483, /* X86MUL_W */ 4485, /* X86MUL_WU */ 4487, /* X86OR_B */ 4489, /* X86OR_D */ 4491, /* X86OR_H */ 4493, /* X86OR_W */ 4495, /* X86RCLI_B */ 4497, /* X86RCLI_D */ 4499, /* X86RCLI_H */ 4501, /* X86RCLI_W */ 4503, /* X86RCL_B */ 4505, /* X86RCL_D */ 4507, /* X86RCL_H */ 4509, /* X86RCL_W */ 4511, /* X86RCRI_B */ 4513, /* X86RCRI_D */ 4515, /* X86RCRI_H */ 4517, /* X86RCRI_W */ 4519, /* X86RCR_B */ 4521, /* X86RCR_D */ 4523, /* X86RCR_H */ 4525, /* X86RCR_W */ 4527, /* X86ROTLI_B */ 4529, /* X86ROTLI_D */ 4531, /* X86ROTLI_H */ 4533, /* X86ROTLI_W */ 4535, /* X86ROTL_B */ 4537, /* X86ROTL_D */ 4539, /* X86ROTL_H */ 4541, /* X86ROTL_W */ 4543, /* X86ROTRI_B */ 4545, /* X86ROTRI_D */ 4547, /* X86ROTRI_H */ 4549, /* X86ROTRI_W */ 4551, /* X86ROTR_B */ 4553, /* X86ROTR_D */ 4555, /* X86ROTR_H */ 4557, /* X86ROTR_W */ 4559, /* X86SBC_B */ 4561, /* X86SBC_D */ 4563, /* X86SBC_H */ 4565, /* X86SBC_W */ 4567, /* X86SETTAG */ 4569, /* X86SETTM */ 4572, /* X86SLLI_B */ 4572, /* X86SLLI_D */ 4574, /* X86SLLI_H */ 4576, /* X86SLLI_W */ 4578, /* X86SLL_B */ 4580, /* X86SLL_D */ 4582, /* X86SLL_H */ 4584, /* X86SLL_W */ 4586, /* X86SRAI_B */ 4588, /* X86SRAI_D */ 4590, /* X86SRAI_H */ 4592, /* X86SRAI_W */ 4594, /* X86SRA_B */ 4596, /* X86SRA_D */ 4598, /* X86SRA_H */ 4600, /* X86SRA_W */ 4602, /* X86SRLI_B */ 4604, /* X86SRLI_D */ 4606, /* X86SRLI_H */ 4608, /* X86SRLI_W */ 4610, /* X86SRL_B */ 4612, /* X86SRL_D */ 4614, /* X86SRL_H */ 4616, /* X86SRL_W */ 4618, /* X86SUB_B */ 4620, /* X86SUB_D */ 4622, /* X86SUB_DU */ 4624, /* X86SUB_H */ 4626, /* X86SUB_W */ 4628, /* X86SUB_WU */ 4630, /* X86XOR_B */ 4632, /* X86XOR_D */ 4634, /* X86XOR_H */ 4636, /* X86XOR_W */ 4638, /* XOR */ 4640, /* XORI */ 4643, /* XVABSD_B */ 4646, /* XVABSD_BU */ 4649, /* XVABSD_D */ 4652, /* XVABSD_DU */ 4655, /* XVABSD_H */ 4658, /* XVABSD_HU */ 4661, /* XVABSD_W */ 4664, /* XVABSD_WU */ 4667, /* XVADDA_B */ 4670, /* XVADDA_D */ 4673, /* XVADDA_H */ 4676, /* XVADDA_W */ 4679, /* XVADDI_BU */ 4682, /* XVADDI_DU */ 4685, /* XVADDI_HU */ 4688, /* XVADDI_WU */ 4691, /* XVADDWEV_D_W */ 4694, /* XVADDWEV_D_WU */ 4697, /* XVADDWEV_D_WU_W */ 4700, /* XVADDWEV_H_B */ 4703, /* XVADDWEV_H_BU */ 4706, /* XVADDWEV_H_BU_B */ 4709, /* XVADDWEV_Q_D */ 4712, /* XVADDWEV_Q_DU */ 4715, /* XVADDWEV_Q_DU_D */ 4718, /* XVADDWEV_W_H */ 4721, /* XVADDWEV_W_HU */ 4724, /* XVADDWEV_W_HU_H */ 4727, /* XVADDWOD_D_W */ 4730, /* XVADDWOD_D_WU */ 4733, /* XVADDWOD_D_WU_W */ 4736, /* XVADDWOD_H_B */ 4739, /* XVADDWOD_H_BU */ 4742, /* XVADDWOD_H_BU_B */ 4745, /* XVADDWOD_Q_D */ 4748, /* XVADDWOD_Q_DU */ 4751, /* XVADDWOD_Q_DU_D */ 4754, /* XVADDWOD_W_H */ 4757, /* XVADDWOD_W_HU */ 4760, /* XVADDWOD_W_HU_H */ 4763, /* XVADD_B */ 4766, /* XVADD_D */ 4769, /* XVADD_H */ 4772, /* XVADD_Q */ 4775, /* XVADD_W */ 4778, /* XVANDI_B */ 4781, /* XVANDN_V */ 4784, /* XVAND_V */ 4787, /* XVAVGR_B */ 4790, /* XVAVGR_BU */ 4793, /* XVAVGR_D */ 4796, /* XVAVGR_DU */ 4799, /* XVAVGR_H */ 4802, /* XVAVGR_HU */ 4805, /* XVAVGR_W */ 4808, /* XVAVGR_WU */ 4811, /* XVAVG_B */ 4814, /* XVAVG_BU */ 4817, /* XVAVG_D */ 4820, /* XVAVG_DU */ 4823, /* XVAVG_H */ 4826, /* XVAVG_HU */ 4829, /* XVAVG_W */ 4832, /* XVAVG_WU */ 4835, /* XVBITCLRI_B */ 4838, /* XVBITCLRI_D */ 4841, /* XVBITCLRI_H */ 4844, /* XVBITCLRI_W */ 4847, /* XVBITCLR_B */ 4850, /* XVBITCLR_D */ 4853, /* XVBITCLR_H */ 4856, /* XVBITCLR_W */ 4859, /* XVBITREVI_B */ 4862, /* XVBITREVI_D */ 4865, /* XVBITREVI_H */ 4868, /* XVBITREVI_W */ 4871, /* XVBITREV_B */ 4874, /* XVBITREV_D */ 4877, /* XVBITREV_H */ 4880, /* XVBITREV_W */ 4883, /* XVBITSELI_B */ 4886, /* XVBITSEL_V */ 4890, /* XVBITSETI_B */ 4894, /* XVBITSETI_D */ 4897, /* XVBITSETI_H */ 4900, /* XVBITSETI_W */ 4903, /* XVBITSET_B */ 4906, /* XVBITSET_D */ 4909, /* XVBITSET_H */ 4912, /* XVBITSET_W */ 4915, /* XVBSLL_V */ 4918, /* XVBSRL_V */ 4921, /* XVCLO_B */ 4924, /* XVCLO_D */ 4926, /* XVCLO_H */ 4928, /* XVCLO_W */ 4930, /* XVCLZ_B */ 4932, /* XVCLZ_D */ 4934, /* XVCLZ_H */ 4936, /* XVCLZ_W */ 4938, /* XVDIV_B */ 4940, /* XVDIV_BU */ 4943, /* XVDIV_D */ 4946, /* XVDIV_DU */ 4949, /* XVDIV_H */ 4952, /* XVDIV_HU */ 4955, /* XVDIV_W */ 4958, /* XVDIV_WU */ 4961, /* XVEXTH_DU_WU */ 4964, /* XVEXTH_D_W */ 4966, /* XVEXTH_HU_BU */ 4968, /* XVEXTH_H_B */ 4970, /* XVEXTH_QU_DU */ 4972, /* XVEXTH_Q_D */ 4974, /* XVEXTH_WU_HU */ 4976, /* XVEXTH_W_H */ 4978, /* XVEXTL_QU_DU */ 4980, /* XVEXTL_Q_D */ 4982, /* XVEXTRINS_B */ 4984, /* XVEXTRINS_D */ 4988, /* XVEXTRINS_H */ 4992, /* XVEXTRINS_W */ 4996, /* XVFADD_D */ 5000, /* XVFADD_S */ 5003, /* XVFCLASS_D */ 5006, /* XVFCLASS_S */ 5008, /* XVFCMP_CAF_D */ 5010, /* XVFCMP_CAF_S */ 5013, /* XVFCMP_CEQ_D */ 5016, /* XVFCMP_CEQ_S */ 5019, /* XVFCMP_CLE_D */ 5022, /* XVFCMP_CLE_S */ 5025, /* XVFCMP_CLT_D */ 5028, /* XVFCMP_CLT_S */ 5031, /* XVFCMP_CNE_D */ 5034, /* XVFCMP_CNE_S */ 5037, /* XVFCMP_COR_D */ 5040, /* XVFCMP_COR_S */ 5043, /* XVFCMP_CUEQ_D */ 5046, /* XVFCMP_CUEQ_S */ 5049, /* XVFCMP_CULE_D */ 5052, /* XVFCMP_CULE_S */ 5055, /* XVFCMP_CULT_D */ 5058, /* XVFCMP_CULT_S */ 5061, /* XVFCMP_CUNE_D */ 5064, /* XVFCMP_CUNE_S */ 5067, /* XVFCMP_CUN_D */ 5070, /* XVFCMP_CUN_S */ 5073, /* XVFCMP_SAF_D */ 5076, /* XVFCMP_SAF_S */ 5079, /* XVFCMP_SEQ_D */ 5082, /* XVFCMP_SEQ_S */ 5085, /* XVFCMP_SLE_D */ 5088, /* XVFCMP_SLE_S */ 5091, /* XVFCMP_SLT_D */ 5094, /* XVFCMP_SLT_S */ 5097, /* XVFCMP_SNE_D */ 5100, /* XVFCMP_SNE_S */ 5103, /* XVFCMP_SOR_D */ 5106, /* XVFCMP_SOR_S */ 5109, /* XVFCMP_SUEQ_D */ 5112, /* XVFCMP_SUEQ_S */ 5115, /* XVFCMP_SULE_D */ 5118, /* XVFCMP_SULE_S */ 5121, /* XVFCMP_SULT_D */ 5124, /* XVFCMP_SULT_S */ 5127, /* XVFCMP_SUNE_D */ 5130, /* XVFCMP_SUNE_S */ 5133, /* XVFCMP_SUN_D */ 5136, /* XVFCMP_SUN_S */ 5139, /* XVFCVTH_D_S */ 5142, /* XVFCVTH_S_H */ 5144, /* XVFCVTL_D_S */ 5146, /* XVFCVTL_S_H */ 5148, /* XVFCVT_H_S */ 5150, /* XVFCVT_S_D */ 5153, /* XVFDIV_D */ 5156, /* XVFDIV_S */ 5159, /* XVFFINTH_D_W */ 5162, /* XVFFINTL_D_W */ 5164, /* XVFFINT_D_L */ 5166, /* XVFFINT_D_LU */ 5168, /* XVFFINT_S_L */ 5170, /* XVFFINT_S_W */ 5173, /* XVFFINT_S_WU */ 5175, /* XVFLOGB_D */ 5177, /* XVFLOGB_S */ 5179, /* XVFMADD_D */ 5181, /* XVFMADD_S */ 5185, /* XVFMAXA_D */ 5189, /* XVFMAXA_S */ 5192, /* XVFMAX_D */ 5195, /* XVFMAX_S */ 5198, /* XVFMINA_D */ 5201, /* XVFMINA_S */ 5204, /* XVFMIN_D */ 5207, /* XVFMIN_S */ 5210, /* XVFMSUB_D */ 5213, /* XVFMSUB_S */ 5217, /* XVFMUL_D */ 5221, /* XVFMUL_S */ 5224, /* XVFNMADD_D */ 5227, /* XVFNMADD_S */ 5231, /* XVFNMSUB_D */ 5235, /* XVFNMSUB_S */ 5239, /* XVFRECIPE_D */ 5243, /* XVFRECIPE_S */ 5245, /* XVFRECIP_D */ 5247, /* XVFRECIP_S */ 5249, /* XVFRINTRM_D */ 5251, /* XVFRINTRM_S */ 5253, /* XVFRINTRNE_D */ 5255, /* XVFRINTRNE_S */ 5257, /* XVFRINTRP_D */ 5259, /* XVFRINTRP_S */ 5261, /* XVFRINTRZ_D */ 5263, /* XVFRINTRZ_S */ 5265, /* XVFRINT_D */ 5267, /* XVFRINT_S */ 5269, /* XVFRSQRTE_D */ 5271, /* XVFRSQRTE_S */ 5273, /* XVFRSQRT_D */ 5275, /* XVFRSQRT_S */ 5277, /* XVFRSTPI_B */ 5279, /* XVFRSTPI_H */ 5283, /* XVFRSTP_B */ 5287, /* XVFRSTP_H */ 5291, /* XVFSQRT_D */ 5295, /* XVFSQRT_S */ 5297, /* XVFSUB_D */ 5299, /* XVFSUB_S */ 5302, /* XVFTINTH_L_S */ 5305, /* XVFTINTL_L_S */ 5307, /* XVFTINTRMH_L_S */ 5309, /* XVFTINTRML_L_S */ 5311, /* XVFTINTRM_L_D */ 5313, /* XVFTINTRM_W_D */ 5315, /* XVFTINTRM_W_S */ 5318, /* XVFTINTRNEH_L_S */ 5320, /* XVFTINTRNEL_L_S */ 5322, /* XVFTINTRNE_L_D */ 5324, /* XVFTINTRNE_W_D */ 5326, /* XVFTINTRNE_W_S */ 5329, /* XVFTINTRPH_L_S */ 5331, /* XVFTINTRPL_L_S */ 5333, /* XVFTINTRP_L_D */ 5335, /* XVFTINTRP_W_D */ 5337, /* XVFTINTRP_W_S */ 5340, /* XVFTINTRZH_L_S */ 5342, /* XVFTINTRZL_L_S */ 5344, /* XVFTINTRZ_LU_D */ 5346, /* XVFTINTRZ_L_D */ 5348, /* XVFTINTRZ_WU_S */ 5350, /* XVFTINTRZ_W_D */ 5352, /* XVFTINTRZ_W_S */ 5355, /* XVFTINT_LU_D */ 5357, /* XVFTINT_L_D */ 5359, /* XVFTINT_WU_S */ 5361, /* XVFTINT_W_D */ 5363, /* XVFTINT_W_S */ 5366, /* XVHADDW_DU_WU */ 5368, /* XVHADDW_D_W */ 5371, /* XVHADDW_HU_BU */ 5374, /* XVHADDW_H_B */ 5377, /* XVHADDW_QU_DU */ 5380, /* XVHADDW_Q_D */ 5383, /* XVHADDW_WU_HU */ 5386, /* XVHADDW_W_H */ 5389, /* XVHSELI_D */ 5392, /* XVHSUBW_DU_WU */ 5395, /* XVHSUBW_D_W */ 5398, /* XVHSUBW_HU_BU */ 5401, /* XVHSUBW_H_B */ 5404, /* XVHSUBW_QU_DU */ 5407, /* XVHSUBW_Q_D */ 5410, /* XVHSUBW_WU_HU */ 5413, /* XVHSUBW_W_H */ 5416, /* XVILVH_B */ 5419, /* XVILVH_D */ 5422, /* XVILVH_H */ 5425, /* XVILVH_W */ 5428, /* XVILVL_B */ 5431, /* XVILVL_D */ 5434, /* XVILVL_H */ 5437, /* XVILVL_W */ 5440, /* XVINSGR2VR_D */ 5443, /* XVINSGR2VR_W */ 5447, /* XVINSVE0_D */ 5451, /* XVINSVE0_W */ 5455, /* XVLD */ 5459, /* XVLDI */ 5462, /* XVLDREPL_B */ 5464, /* XVLDREPL_D */ 5467, /* XVLDREPL_H */ 5470, /* XVLDREPL_W */ 5473, /* XVLDX */ 5476, /* XVMADDWEV_D_W */ 5479, /* XVMADDWEV_D_WU */ 5483, /* XVMADDWEV_D_WU_W */ 5487, /* XVMADDWEV_H_B */ 5491, /* XVMADDWEV_H_BU */ 5495, /* XVMADDWEV_H_BU_B */ 5499, /* XVMADDWEV_Q_D */ 5503, /* XVMADDWEV_Q_DU */ 5507, /* XVMADDWEV_Q_DU_D */ 5511, /* XVMADDWEV_W_H */ 5515, /* XVMADDWEV_W_HU */ 5519, /* XVMADDWEV_W_HU_H */ 5523, /* XVMADDWOD_D_W */ 5527, /* XVMADDWOD_D_WU */ 5531, /* XVMADDWOD_D_WU_W */ 5535, /* XVMADDWOD_H_B */ 5539, /* XVMADDWOD_H_BU */ 5543, /* XVMADDWOD_H_BU_B */ 5547, /* XVMADDWOD_Q_D */ 5551, /* XVMADDWOD_Q_DU */ 5555, /* XVMADDWOD_Q_DU_D */ 5559, /* XVMADDWOD_W_H */ 5563, /* XVMADDWOD_W_HU */ 5567, /* XVMADDWOD_W_HU_H */ 5571, /* XVMADD_B */ 5575, /* XVMADD_D */ 5579, /* XVMADD_H */ 5583, /* XVMADD_W */ 5587, /* XVMAXI_B */ 5591, /* XVMAXI_BU */ 5594, /* XVMAXI_D */ 5597, /* XVMAXI_DU */ 5600, /* XVMAXI_H */ 5603, /* XVMAXI_HU */ 5606, /* XVMAXI_W */ 5609, /* XVMAXI_WU */ 5612, /* XVMAX_B */ 5615, /* XVMAX_BU */ 5618, /* XVMAX_D */ 5621, /* XVMAX_DU */ 5624, /* XVMAX_H */ 5627, /* XVMAX_HU */ 5630, /* XVMAX_W */ 5633, /* XVMAX_WU */ 5636, /* XVMINI_B */ 5639, /* XVMINI_BU */ 5642, /* XVMINI_D */ 5645, /* XVMINI_DU */ 5648, /* XVMINI_H */ 5651, /* XVMINI_HU */ 5654, /* XVMINI_W */ 5657, /* XVMINI_WU */ 5660, /* XVMIN_B */ 5663, /* XVMIN_BU */ 5666, /* XVMIN_D */ 5669, /* XVMIN_DU */ 5672, /* XVMIN_H */ 5675, /* XVMIN_HU */ 5678, /* XVMIN_W */ 5681, /* XVMIN_WU */ 5684, /* XVMOD_B */ 5687, /* XVMOD_BU */ 5690, /* XVMOD_D */ 5693, /* XVMOD_DU */ 5696, /* XVMOD_H */ 5699, /* XVMOD_HU */ 5702, /* XVMOD_W */ 5705, /* XVMOD_WU */ 5708, /* XVMSKGEZ_B */ 5711, /* XVMSKLTZ_B */ 5713, /* XVMSKLTZ_D */ 5715, /* XVMSKLTZ_H */ 5717, /* XVMSKLTZ_W */ 5719, /* XVMSKNZ_B */ 5721, /* XVMSUB_B */ 5723, /* XVMSUB_D */ 5727, /* XVMSUB_H */ 5731, /* XVMSUB_W */ 5735, /* XVMUH_B */ 5739, /* XVMUH_BU */ 5742, /* XVMUH_D */ 5745, /* XVMUH_DU */ 5748, /* XVMUH_H */ 5751, /* XVMUH_HU */ 5754, /* XVMUH_W */ 5757, /* XVMUH_WU */ 5760, /* XVMULWEV_D_W */ 5763, /* XVMULWEV_D_WU */ 5766, /* XVMULWEV_D_WU_W */ 5769, /* XVMULWEV_H_B */ 5772, /* XVMULWEV_H_BU */ 5775, /* XVMULWEV_H_BU_B */ 5778, /* XVMULWEV_Q_D */ 5781, /* XVMULWEV_Q_DU */ 5784, /* XVMULWEV_Q_DU_D */ 5787, /* XVMULWEV_W_H */ 5790, /* XVMULWEV_W_HU */ 5793, /* XVMULWEV_W_HU_H */ 5796, /* XVMULWOD_D_W */ 5799, /* XVMULWOD_D_WU */ 5802, /* XVMULWOD_D_WU_W */ 5805, /* XVMULWOD_H_B */ 5808, /* XVMULWOD_H_BU */ 5811, /* XVMULWOD_H_BU_B */ 5814, /* XVMULWOD_Q_D */ 5817, /* XVMULWOD_Q_DU */ 5820, /* XVMULWOD_Q_DU_D */ 5823, /* XVMULWOD_W_H */ 5826, /* XVMULWOD_W_HU */ 5829, /* XVMULWOD_W_HU_H */ 5832, /* XVMUL_B */ 5835, /* XVMUL_D */ 5838, /* XVMUL_H */ 5841, /* XVMUL_W */ 5844, /* XVNEG_B */ 5847, /* XVNEG_D */ 5849, /* XVNEG_H */ 5851, /* XVNEG_W */ 5853, /* XVNORI_B */ 5855, /* XVNOR_V */ 5858, /* XVORI_B */ 5861, /* XVORN_V */ 5864, /* XVOR_V */ 5867, /* XVPACKEV_B */ 5870, /* XVPACKEV_D */ 5873, /* XVPACKEV_H */ 5876, /* XVPACKEV_W */ 5879, /* XVPACKOD_B */ 5882, /* XVPACKOD_D */ 5885, /* XVPACKOD_H */ 5888, /* XVPACKOD_W */ 5891, /* XVPCNT_B */ 5894, /* XVPCNT_D */ 5896, /* XVPCNT_H */ 5898, /* XVPCNT_W */ 5900, /* XVPERMI_D */ 5902, /* XVPERMI_Q */ 5905, /* XVPERMI_W */ 5909, /* XVPERM_W */ 5913, /* XVPICKEV_B */ 5916, /* XVPICKEV_D */ 5919, /* XVPICKEV_H */ 5922, /* XVPICKEV_W */ 5925, /* XVPICKOD_B */ 5928, /* XVPICKOD_D */ 5931, /* XVPICKOD_H */ 5934, /* XVPICKOD_W */ 5937, /* XVPICKVE2GR_D */ 5940, /* XVPICKVE2GR_DU */ 5943, /* XVPICKVE2GR_W */ 5946, /* XVPICKVE2GR_WU */ 5949, /* XVPICKVE_D */ 5952, /* XVPICKVE_W */ 5955, /* XVREPL128VEI_B */ 5958, /* XVREPL128VEI_D */ 5961, /* XVREPL128VEI_H */ 5964, /* XVREPL128VEI_W */ 5967, /* XVREPLGR2VR_B */ 5970, /* XVREPLGR2VR_D */ 5972, /* XVREPLGR2VR_H */ 5974, /* XVREPLGR2VR_W */ 5976, /* XVREPLVE0_B */ 5978, /* XVREPLVE0_D */ 5980, /* XVREPLVE0_H */ 5982, /* XVREPLVE0_Q */ 5984, /* XVREPLVE0_W */ 5986, /* XVREPLVE_B */ 5988, /* XVREPLVE_D */ 5991, /* XVREPLVE_H */ 5994, /* XVREPLVE_W */ 5997, /* XVROTRI_B */ 6000, /* XVROTRI_D */ 6003, /* XVROTRI_H */ 6006, /* XVROTRI_W */ 6009, /* XVROTR_B */ 6012, /* XVROTR_D */ 6015, /* XVROTR_H */ 6018, /* XVROTR_W */ 6021, /* XVSADD_B */ 6024, /* XVSADD_BU */ 6027, /* XVSADD_D */ 6030, /* XVSADD_DU */ 6033, /* XVSADD_H */ 6036, /* XVSADD_HU */ 6039, /* XVSADD_W */ 6042, /* XVSADD_WU */ 6045, /* XVSAT_B */ 6048, /* XVSAT_BU */ 6051, /* XVSAT_D */ 6054, /* XVSAT_DU */ 6057, /* XVSAT_H */ 6060, /* XVSAT_HU */ 6063, /* XVSAT_W */ 6066, /* XVSAT_WU */ 6069, /* XVSEQI_B */ 6072, /* XVSEQI_D */ 6075, /* XVSEQI_H */ 6078, /* XVSEQI_W */ 6081, /* XVSEQ_B */ 6084, /* XVSEQ_D */ 6087, /* XVSEQ_H */ 6090, /* XVSEQ_W */ 6093, /* XVSETALLNEZ_B */ 6096, /* XVSETALLNEZ_D */ 6098, /* XVSETALLNEZ_H */ 6100, /* XVSETALLNEZ_W */ 6102, /* XVSETANYEQZ_B */ 6104, /* XVSETANYEQZ_D */ 6106, /* XVSETANYEQZ_H */ 6108, /* XVSETANYEQZ_W */ 6110, /* XVSETEQZ_V */ 6112, /* XVSETNEZ_V */ 6114, /* XVSHUF4I_B */ 6116, /* XVSHUF4I_D */ 6119, /* XVSHUF4I_H */ 6123, /* XVSHUF4I_W */ 6126, /* XVSHUF_B */ 6129, /* XVSHUF_D */ 6133, /* XVSHUF_H */ 6137, /* XVSHUF_W */ 6141, /* XVSIGNCOV_B */ 6145, /* XVSIGNCOV_D */ 6148, /* XVSIGNCOV_H */ 6151, /* XVSIGNCOV_W */ 6154, /* XVSLEI_B */ 6157, /* XVSLEI_BU */ 6160, /* XVSLEI_D */ 6163, /* XVSLEI_DU */ 6166, /* XVSLEI_H */ 6169, /* XVSLEI_HU */ 6172, /* XVSLEI_W */ 6175, /* XVSLEI_WU */ 6178, /* XVSLE_B */ 6181, /* XVSLE_BU */ 6184, /* XVSLE_D */ 6187, /* XVSLE_DU */ 6190, /* XVSLE_H */ 6193, /* XVSLE_HU */ 6196, /* XVSLE_W */ 6199, /* XVSLE_WU */ 6202, /* XVSLLI_B */ 6205, /* XVSLLI_D */ 6208, /* XVSLLI_H */ 6211, /* XVSLLI_W */ 6214, /* XVSLLWIL_DU_WU */ 6217, /* XVSLLWIL_D_W */ 6220, /* XVSLLWIL_HU_BU */ 6223, /* XVSLLWIL_H_B */ 6226, /* XVSLLWIL_WU_HU */ 6229, /* XVSLLWIL_W_H */ 6232, /* XVSLL_B */ 6235, /* XVSLL_D */ 6238, /* XVSLL_H */ 6241, /* XVSLL_W */ 6244, /* XVSLTI_B */ 6247, /* XVSLTI_BU */ 6250, /* XVSLTI_D */ 6253, /* XVSLTI_DU */ 6256, /* XVSLTI_H */ 6259, /* XVSLTI_HU */ 6262, /* XVSLTI_W */ 6265, /* XVSLTI_WU */ 6268, /* XVSLT_B */ 6271, /* XVSLT_BU */ 6274, /* XVSLT_D */ 6277, /* XVSLT_DU */ 6280, /* XVSLT_H */ 6283, /* XVSLT_HU */ 6286, /* XVSLT_W */ 6289, /* XVSLT_WU */ 6292, /* XVSRAI_B */ 6295, /* XVSRAI_D */ 6298, /* XVSRAI_H */ 6301, /* XVSRAI_W */ 6304, /* XVSRANI_B_H */ 6307, /* XVSRANI_D_Q */ 6311, /* XVSRANI_H_W */ 6315, /* XVSRANI_W_D */ 6319, /* XVSRAN_B_H */ 6323, /* XVSRAN_H_W */ 6326, /* XVSRAN_W_D */ 6329, /* XVSRARI_B */ 6332, /* XVSRARI_D */ 6335, /* XVSRARI_H */ 6338, /* XVSRARI_W */ 6341, /* XVSRARNI_B_H */ 6344, /* XVSRARNI_D_Q */ 6348, /* XVSRARNI_H_W */ 6352, /* XVSRARNI_W_D */ 6356, /* XVSRARN_B_H */ 6360, /* XVSRARN_H_W */ 6363, /* XVSRARN_W_D */ 6366, /* XVSRAR_B */ 6369, /* XVSRAR_D */ 6372, /* XVSRAR_H */ 6375, /* XVSRAR_W */ 6378, /* XVSRA_B */ 6381, /* XVSRA_D */ 6384, /* XVSRA_H */ 6387, /* XVSRA_W */ 6390, /* XVSRLI_B */ 6393, /* XVSRLI_D */ 6396, /* XVSRLI_H */ 6399, /* XVSRLI_W */ 6402, /* XVSRLNI_B_H */ 6405, /* XVSRLNI_D_Q */ 6409, /* XVSRLNI_H_W */ 6413, /* XVSRLNI_W_D */ 6417, /* XVSRLN_B_H */ 6421, /* XVSRLN_H_W */ 6424, /* XVSRLN_W_D */ 6427, /* XVSRLRI_B */ 6430, /* XVSRLRI_D */ 6433, /* XVSRLRI_H */ 6436, /* XVSRLRI_W */ 6439, /* XVSRLRNI_B_H */ 6442, /* XVSRLRNI_D_Q */ 6446, /* XVSRLRNI_H_W */ 6450, /* XVSRLRNI_W_D */ 6454, /* XVSRLRN_B_H */ 6458, /* XVSRLRN_H_W */ 6461, /* XVSRLRN_W_D */ 6464, /* XVSRLR_B */ 6467, /* XVSRLR_D */ 6470, /* XVSRLR_H */ 6473, /* XVSRLR_W */ 6476, /* XVSRL_B */ 6479, /* XVSRL_D */ 6482, /* XVSRL_H */ 6485, /* XVSRL_W */ 6488, /* XVSSRANI_BU_H */ 6491, /* XVSSRANI_B_H */ 6495, /* XVSSRANI_DU_Q */ 6499, /* XVSSRANI_D_Q */ 6503, /* XVSSRANI_HU_W */ 6507, /* XVSSRANI_H_W */ 6511, /* XVSSRANI_WU_D */ 6515, /* XVSSRANI_W_D */ 6519, /* XVSSRAN_BU_H */ 6523, /* XVSSRAN_B_H */ 6526, /* XVSSRAN_HU_W */ 6529, /* XVSSRAN_H_W */ 6532, /* XVSSRAN_WU_D */ 6535, /* XVSSRAN_W_D */ 6538, /* XVSSRARNI_BU_H */ 6541, /* XVSSRARNI_B_H */ 6545, /* XVSSRARNI_DU_Q */ 6549, /* XVSSRARNI_D_Q */ 6553, /* XVSSRARNI_HU_W */ 6557, /* XVSSRARNI_H_W */ 6561, /* XVSSRARNI_WU_D */ 6565, /* XVSSRARNI_W_D */ 6569, /* XVSSRARN_BU_H */ 6573, /* XVSSRARN_B_H */ 6576, /* XVSSRARN_HU_W */ 6579, /* XVSSRARN_H_W */ 6582, /* XVSSRARN_WU_D */ 6585, /* XVSSRARN_W_D */ 6588, /* XVSSRLNI_BU_H */ 6591, /* XVSSRLNI_B_H */ 6595, /* XVSSRLNI_DU_Q */ 6599, /* XVSSRLNI_D_Q */ 6603, /* XVSSRLNI_HU_W */ 6607, /* XVSSRLNI_H_W */ 6611, /* XVSSRLNI_WU_D */ 6615, /* XVSSRLNI_W_D */ 6619, /* XVSSRLN_BU_H */ 6623, /* XVSSRLN_B_H */ 6626, /* XVSSRLN_HU_W */ 6629, /* XVSSRLN_H_W */ 6632, /* XVSSRLN_WU_D */ 6635, /* XVSSRLN_W_D */ 6638, /* XVSSRLRNI_BU_H */ 6641, /* XVSSRLRNI_B_H */ 6645, /* XVSSRLRNI_DU_Q */ 6649, /* XVSSRLRNI_D_Q */ 6653, /* XVSSRLRNI_HU_W */ 6657, /* XVSSRLRNI_H_W */ 6661, /* XVSSRLRNI_WU_D */ 6665, /* XVSSRLRNI_W_D */ 6669, /* XVSSRLRN_BU_H */ 6673, /* XVSSRLRN_B_H */ 6676, /* XVSSRLRN_HU_W */ 6679, /* XVSSRLRN_H_W */ 6682, /* XVSSRLRN_WU_D */ 6685, /* XVSSRLRN_W_D */ 6688, /* XVSSUB_B */ 6691, /* XVSSUB_BU */ 6694, /* XVSSUB_D */ 6697, /* XVSSUB_DU */ 6700, /* XVSSUB_H */ 6703, /* XVSSUB_HU */ 6706, /* XVSSUB_W */ 6709, /* XVSSUB_WU */ 6712, /* XVST */ 6715, /* XVSTELM_B */ 6718, /* XVSTELM_D */ 6722, /* XVSTELM_H */ 6726, /* XVSTELM_W */ 6730, /* XVSTX */ 6734, /* XVSUBI_BU */ 6737, /* XVSUBI_DU */ 6740, /* XVSUBI_HU */ 6743, /* XVSUBI_WU */ 6746, /* XVSUBWEV_D_W */ 6749, /* XVSUBWEV_D_WU */ 6752, /* XVSUBWEV_H_B */ 6755, /* XVSUBWEV_H_BU */ 6758, /* XVSUBWEV_Q_D */ 6761, /* XVSUBWEV_Q_DU */ 6764, /* XVSUBWEV_W_H */ 6767, /* XVSUBWEV_W_HU */ 6770, /* XVSUBWOD_D_W */ 6773, /* XVSUBWOD_D_WU */ 6776, /* XVSUBWOD_H_B */ 6779, /* XVSUBWOD_H_BU */ 6782, /* XVSUBWOD_Q_D */ 6785, /* XVSUBWOD_Q_DU */ 6788, /* XVSUBWOD_W_H */ 6791, /* XVSUBWOD_W_HU */ 6794, /* XVSUB_B */ 6797, /* XVSUB_D */ 6800, /* XVSUB_H */ 6803, /* XVSUB_Q */ 6806, /* XVSUB_W */ 6809, /* XVXORI_B */ 6812, /* XVXOR_V */ 6815, }; using namespace OpTypes; static const int8_t OpcodeOperandTypes[] = { /* PHI */ -1, /* INLINEASM */ /* INLINEASM_BR */ /* CFI_INSTRUCTION */ i32imm, /* EH_LABEL */ i32imm, /* GC_LABEL */ i32imm, /* ANNOTATION_LABEL */ i32imm, /* KILL */ /* EXTRACT_SUBREG */ -1, -1, i32imm, /* INSERT_SUBREG */ -1, -1, -1, i32imm, /* IMPLICIT_DEF */ -1, /* SUBREG_TO_REG */ -1, -1, -1, i32imm, /* COPY_TO_REGCLASS */ -1, -1, i32imm, /* DBG_VALUE */ /* DBG_VALUE_LIST */ /* DBG_INSTR_REF */ /* DBG_PHI */ /* DBG_LABEL */ -1, /* REG_SEQUENCE */ -1, -1, /* COPY */ -1, -1, /* BUNDLE */ /* LIFETIME_START */ i32imm, /* LIFETIME_END */ i32imm, /* PSEUDO_PROBE */ i64imm, i64imm, i8imm, i32imm, /* ARITH_FENCE */ -1, -1, /* STACKMAP */ i64imm, i32imm, /* FENTRY_CALL */ /* PATCHPOINT */ -1, i64imm, i32imm, -1, i32imm, i32imm, /* LOAD_STACK_GUARD */ -1, /* PREALLOCATED_SETUP */ i32imm, /* PREALLOCATED_ARG */ -1, i32imm, i32imm, /* STATEPOINT */ /* LOCAL_ESCAPE */ -1, i32imm, /* FAULTING_OP */ -1, /* PATCHABLE_OP */ /* PATCHABLE_FUNCTION_ENTER */ /* PATCHABLE_RET */ /* PATCHABLE_FUNCTION_EXIT */ /* PATCHABLE_TAIL_CALL */ /* PATCHABLE_EVENT_CALL */ -1, -1, /* PATCHABLE_TYPED_EVENT_CALL */ -1, -1, -1, /* ICALL_BRANCH_FUNNEL */ /* FAKE_USE */ /* MEMBARRIER */ /* JUMP_TABLE_DEBUG_INFO */ i64imm, /* CONVERGENCECTRL_ENTRY */ -1, /* CONVERGENCECTRL_ANCHOR */ -1, /* CONVERGENCECTRL_LOOP */ -1, -1, /* CONVERGENCECTRL_GLUE */ -1, /* G_ASSERT_SEXT */ type0, type0, untyped_imm_0, /* G_ASSERT_ZEXT */ type0, type0, untyped_imm_0, /* G_ASSERT_ALIGN */ type0, type0, untyped_imm_0, /* G_ADD */ type0, type0, type0, /* G_SUB */ type0, type0, type0, /* G_MUL */ type0, type0, type0, /* G_SDIV */ type0, type0, type0, /* G_UDIV */ type0, type0, type0, /* G_SREM */ type0, type0, type0, /* G_UREM */ type0, type0, type0, /* G_SDIVREM */ type0, type0, type0, type0, /* G_UDIVREM */ type0, type0, type0, type0, /* G_AND */ type0, type0, type0, /* G_OR */ type0, type0, type0, /* G_XOR */ type0, type0, type0, /* G_IMPLICIT_DEF */ type0, /* G_PHI */ type0, /* G_FRAME_INDEX */ type0, -1, /* G_GLOBAL_VALUE */ type0, -1, /* G_PTRAUTH_GLOBAL_VALUE */ type0, -1, i32imm, type1, i64imm, /* G_CONSTANT_POOL */ type0, -1, /* G_EXTRACT */ type0, type1, untyped_imm_0, /* G_UNMERGE_VALUES */ type0, type1, /* G_INSERT */ type0, type0, type1, untyped_imm_0, /* G_MERGE_VALUES */ type0, type1, /* G_BUILD_VECTOR */ type0, type1, /* G_BUILD_VECTOR_TRUNC */ type0, type1, /* G_CONCAT_VECTORS */ type0, type1, /* G_PTRTOINT */ type0, type1, /* G_INTTOPTR */ type0, type1, /* G_BITCAST */ type0, type1, /* G_FREEZE */ type0, type0, /* G_CONSTANT_FOLD_BARRIER */ type0, type0, /* G_INTRINSIC_FPTRUNC_ROUND */ type0, type1, i32imm, /* G_INTRINSIC_TRUNC */ type0, type0, /* G_INTRINSIC_ROUND */ type0, type0, /* G_INTRINSIC_LRINT */ type0, type1, /* G_INTRINSIC_LLRINT */ type0, type1, /* G_INTRINSIC_ROUNDEVEN */ type0, type0, /* G_READCYCLECOUNTER */ type0, /* G_READSTEADYCOUNTER */ type0, /* G_LOAD */ type0, ptype1, /* G_SEXTLOAD */ type0, ptype1, /* G_ZEXTLOAD */ type0, ptype1, /* G_INDEXED_LOAD */ type0, ptype1, ptype1, type2, -1, /* G_INDEXED_SEXTLOAD */ type0, ptype1, ptype1, type2, -1, /* G_INDEXED_ZEXTLOAD */ type0, ptype1, ptype1, type2, -1, /* G_STORE */ type0, ptype1, /* G_INDEXED_STORE */ ptype0, type1, ptype0, ptype2, -1, /* G_ATOMIC_CMPXCHG_WITH_SUCCESS */ type0, type1, type2, type0, type0, /* G_ATOMIC_CMPXCHG */ type0, ptype1, type0, type0, /* G_ATOMICRMW_XCHG */ type0, ptype1, type0, /* G_ATOMICRMW_ADD */ type0, ptype1, type0, /* G_ATOMICRMW_SUB */ type0, ptype1, type0, /* G_ATOMICRMW_AND */ type0, ptype1, type0, /* G_ATOMICRMW_NAND */ type0, ptype1, type0, /* G_ATOMICRMW_OR */ type0, ptype1, type0, /* G_ATOMICRMW_XOR */ type0, ptype1, type0, /* G_ATOMICRMW_MAX */ type0, ptype1, type0, /* G_ATOMICRMW_MIN */ type0, ptype1, type0, /* G_ATOMICRMW_UMAX */ type0, ptype1, type0, /* G_ATOMICRMW_UMIN */ type0, ptype1, type0, /* G_ATOMICRMW_FADD */ type0, ptype1, type0, /* G_ATOMICRMW_FSUB */ type0, ptype1, type0, /* G_ATOMICRMW_FMAX */ type0, ptype1, type0, /* G_ATOMICRMW_FMIN */ type0, ptype1, type0, /* G_ATOMICRMW_UINC_WRAP */ type0, ptype1, type0, /* G_ATOMICRMW_UDEC_WRAP */ type0, ptype1, type0, /* G_FENCE */ i32imm, i32imm, /* G_PREFETCH */ ptype0, i32imm, i32imm, i32imm, /* G_BRCOND */ type0, -1, /* G_BRINDIRECT */ type0, /* G_INVOKE_REGION_START */ /* G_INTRINSIC */ -1, /* G_INTRINSIC_W_SIDE_EFFECTS */ -1, /* G_INTRINSIC_CONVERGENT */ -1, /* G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS */ -1, /* G_ANYEXT */ type0, type1, /* G_TRUNC */ type0, type1, /* G_CONSTANT */ type0, -1, /* G_FCONSTANT */ type0, -1, /* G_VASTART */ type0, /* G_VAARG */ type0, type1, -1, /* G_SEXT */ type0, type1, /* G_SEXT_INREG */ type0, type0, untyped_imm_0, /* G_ZEXT */ type0, type1, /* G_SHL */ type0, type0, type1, /* G_LSHR */ type0, type0, type1, /* G_ASHR */ type0, type0, type1, /* G_FSHL */ type0, type0, type0, type1, /* G_FSHR */ type0, type0, type0, type1, /* G_ROTR */ type0, type0, type1, /* G_ROTL */ type0, type0, type1, /* G_ICMP */ type0, -1, type1, type1, /* G_FCMP */ type0, -1, type1, type1, /* G_SCMP */ type0, type1, type1, /* G_UCMP */ type0, type1, type1, /* G_SELECT */ type0, type1, type0, type0, /* G_UADDO */ type0, type1, type0, type0, /* G_UADDE */ type0, type1, type0, type0, type1, /* G_USUBO */ type0, type1, type0, type0, /* G_USUBE */ type0, type1, type0, type0, type1, /* G_SADDO */ type0, type1, type0, type0, /* G_SADDE */ type0, type1, type0, type0, type1, /* G_SSUBO */ type0, type1, type0, type0, /* G_SSUBE */ type0, type1, type0, type0, type1, /* G_UMULO */ type0, type1, type0, type0, /* G_SMULO */ type0, type1, type0, type0, /* G_UMULH */ type0, type0, type0, /* G_SMULH */ type0, type0, type0, /* G_UADDSAT */ type0, type0, type0, /* G_SADDSAT */ type0, type0, type0, /* G_USUBSAT */ type0, type0, type0, /* G_SSUBSAT */ type0, type0, type0, /* G_USHLSAT */ type0, type0, type1, /* G_SSHLSAT */ type0, type0, type1, /* G_SMULFIX */ type0, type0, type0, untyped_imm_0, /* G_UMULFIX */ type0, type0, type0, untyped_imm_0, /* G_SMULFIXSAT */ type0, type0, type0, untyped_imm_0, /* G_UMULFIXSAT */ type0, type0, type0, untyped_imm_0, /* G_SDIVFIX */ type0, type0, type0, untyped_imm_0, /* G_UDIVFIX */ type0, type0, type0, untyped_imm_0, /* G_SDIVFIXSAT */ type0, type0, type0, untyped_imm_0, /* G_UDIVFIXSAT */ type0, type0, type0, untyped_imm_0, /* G_FADD */ type0, type0, type0, /* G_FSUB */ type0, type0, type0, /* G_FMUL */ type0, type0, type0, /* G_FMA */ type0, type0, type0, type0, /* G_FMAD */ type0, type0, type0, type0, /* G_FDIV */ type0, type0, type0, /* G_FREM */ type0, type0, type0, /* G_FPOW */ type0, type0, type0, /* G_FPOWI */ type0, type0, type1, /* G_FEXP */ type0, type0, /* G_FEXP2 */ type0, type0, /* G_FEXP10 */ type0, type0, /* G_FLOG */ type0, type0, /* G_FLOG2 */ type0, type0, /* G_FLOG10 */ type0, type0, /* G_FLDEXP */ type0, type0, type1, /* G_FFREXP */ type0, type1, type0, /* G_FNEG */ type0, type0, /* G_FPEXT */ type0, type1, /* G_FPTRUNC */ type0, type1, /* G_FPTOSI */ type0, type1, /* G_FPTOUI */ type0, type1, /* G_SITOFP */ type0, type1, /* G_UITOFP */ type0, type1, /* G_FABS */ type0, type0, /* G_FCOPYSIGN */ type0, type0, type1, /* G_IS_FPCLASS */ type0, type1, -1, /* G_FCANONICALIZE */ type0, type0, /* G_FMINNUM */ type0, type0, type0, /* G_FMAXNUM */ type0, type0, type0, /* G_FMINNUM_IEEE */ type0, type0, type0, /* G_FMAXNUM_IEEE */ type0, type0, type0, /* G_FMINIMUM */ type0, type0, type0, /* G_FMAXIMUM */ type0, type0, type0, /* G_GET_FPENV */ type0, /* G_SET_FPENV */ type0, /* G_RESET_FPENV */ /* G_GET_FPMODE */ type0, /* G_SET_FPMODE */ type0, /* G_RESET_FPMODE */ /* G_PTR_ADD */ ptype0, ptype0, type1, /* G_PTRMASK */ ptype0, ptype0, type1, /* G_SMIN */ type0, type0, type0, /* G_SMAX */ type0, type0, type0, /* G_UMIN */ type0, type0, type0, /* G_UMAX */ type0, type0, type0, /* G_ABS */ type0, type0, /* G_LROUND */ type0, type1, /* G_LLROUND */ type0, type1, /* G_BR */ -1, /* G_BRJT */ ptype0, -1, type1, /* G_VSCALE */ type0, -1, /* G_INSERT_SUBVECTOR */ type0, type0, type1, untyped_imm_0, /* G_EXTRACT_SUBVECTOR */ type0, type0, untyped_imm_0, /* G_INSERT_VECTOR_ELT */ type0, type0, type1, type2, /* G_EXTRACT_VECTOR_ELT */ type0, type1, type2, /* G_SHUFFLE_VECTOR */ type0, type1, type1, -1, /* G_SPLAT_VECTOR */ type0, type1, /* G_VECTOR_COMPRESS */ type0, type0, type1, type0, /* G_CTTZ */ type0, type1, /* G_CTTZ_ZERO_UNDEF */ type0, type1, /* G_CTLZ */ type0, type1, /* G_CTLZ_ZERO_UNDEF */ type0, type1, /* G_CTPOP */ type0, type1, /* G_BSWAP */ type0, type0, /* G_BITREVERSE */ type0, type0, /* G_FCEIL */ type0, type0, /* G_FCOS */ type0, type0, /* G_FSIN */ type0, type0, /* G_FTAN */ type0, type0, /* G_FACOS */ type0, type0, /* G_FASIN */ type0, type0, /* G_FATAN */ type0, type0, /* G_FCOSH */ type0, type0, /* G_FSINH */ type0, type0, /* G_FTANH */ type0, type0, /* G_FSQRT */ type0, type0, /* G_FFLOOR */ type0, type0, /* G_FRINT */ type0, type0, /* G_FNEARBYINT */ type0, type0, /* G_ADDRSPACE_CAST */ type0, type1, /* G_BLOCK_ADDR */ type0, -1, /* G_JUMP_TABLE */ type0, -1, /* G_DYN_STACKALLOC */ ptype0, type1, i32imm, /* G_STACKSAVE */ ptype0, /* G_STACKRESTORE */ ptype0, /* G_STRICT_FADD */ type0, type0, type0, /* G_STRICT_FSUB */ type0, type0, type0, /* G_STRICT_FMUL */ type0, type0, type0, /* G_STRICT_FDIV */ type0, type0, type0, /* G_STRICT_FREM */ type0, type0, type0, /* G_STRICT_FMA */ type0, type0, type0, type0, /* G_STRICT_FSQRT */ type0, type0, /* G_STRICT_FLDEXP */ type0, type0, type1, /* G_READ_REGISTER */ type0, -1, /* G_WRITE_REGISTER */ -1, type0, /* G_MEMCPY */ ptype0, ptype1, type2, untyped_imm_0, /* G_MEMCPY_INLINE */ ptype0, ptype1, type2, /* G_MEMMOVE */ ptype0, ptype1, type2, untyped_imm_0, /* G_MEMSET */ ptype0, type1, type2, untyped_imm_0, /* G_BZERO */ ptype0, type1, untyped_imm_0, /* G_TRAP */ /* G_DEBUGTRAP */ /* G_UBSANTRAP */ i8imm, /* G_VECREDUCE_SEQ_FADD */ type0, type1, type2, /* G_VECREDUCE_SEQ_FMUL */ type0, type1, type2, /* G_VECREDUCE_FADD */ type0, type1, /* G_VECREDUCE_FMUL */ type0, type1, /* G_VECREDUCE_FMAX */ type0, type1, /* G_VECREDUCE_FMIN */ type0, type1, /* G_VECREDUCE_FMAXIMUM */ type0, type1, /* G_VECREDUCE_FMINIMUM */ type0, type1, /* G_VECREDUCE_ADD */ type0, type1, /* G_VECREDUCE_MUL */ type0, type1, /* G_VECREDUCE_AND */ type0, type1, /* G_VECREDUCE_OR */ type0, type1, /* G_VECREDUCE_XOR */ type0, type1, /* G_VECREDUCE_SMAX */ type0, type1, /* G_VECREDUCE_SMIN */ type0, type1, /* G_VECREDUCE_UMAX */ type0, type1, /* G_VECREDUCE_UMIN */ type0, type1, /* G_SBFX */ type0, type0, type1, type1, /* G_UBFX */ type0, type0, type1, type1, /* ADJCALLSTACKDOWN */ i32imm, i32imm, /* ADJCALLSTACKUP */ i32imm, i32imm, /* PseudoAddTPRel_D */ GPR, GPR, GPR, tprel_add_symbol, /* PseudoAddTPRel_W */ GPR, GPR, GPR, tprel_add_symbol, /* PseudoAtomicLoadAdd32 */ GPR, GPR, GPR, GPR, grlenimm, /* PseudoAtomicLoadAnd32 */ GPR, GPR, GPR, GPR, grlenimm, /* PseudoAtomicLoadNand32 */ GPR, GPR, GPR, GPR, grlenimm, /* PseudoAtomicLoadNand64 */ GPR, GPR, GPR, GPR, grlenimm, /* PseudoAtomicLoadOr32 */ GPR, GPR, GPR, GPR, grlenimm, /* PseudoAtomicLoadSub32 */ GPR, GPR, GPR, GPR, grlenimm, /* PseudoAtomicLoadXor32 */ GPR, GPR, GPR, GPR, grlenimm, /* PseudoAtomicStoreD */ GPR, GPR, GPR, /* PseudoAtomicStoreW */ GPR, GPR, GPR, /* PseudoAtomicSwap32 */ GPR, GPR, GPR, GPR, grlenimm, /* PseudoBR */ simm26_b, /* PseudoBRIND */ GPR, simm16_lsl2, /* PseudoB_TAIL */ simm26_b, /* PseudoCALL */ bare_symbol, /* PseudoCALL36 */ bare_symbol, /* PseudoCALLIndirect */ GPR, /* PseudoCALL_LARGE */ bare_symbol, /* PseudoCALL_MEDIUM */ bare_symbol, /* PseudoCmpXchg32 */ GPR, GPR, GPR, GPR, GPR, grlenimm, /* PseudoCmpXchg64 */ GPR, GPR, GPR, GPR, GPR, grlenimm, /* PseudoCopyCFR */ CFR, CFR, /* PseudoDESC_CALL */ GPR, GPR, simm16_lsl2, /* PseudoJIRL_CALL */ GPR, simm16_lsl2, /* PseudoJIRL_TAIL */ GPR, simm16_lsl2, /* PseudoLA_ABS */ GPR, bare_symbol, /* PseudoLA_ABS_LARGE */ GPR, GPR, bare_symbol, /* PseudoLA_GOT */ GPR, bare_symbol, /* PseudoLA_GOT_LARGE */ GPR, GPR, bare_symbol, /* PseudoLA_PCREL */ GPR, bare_symbol, /* PseudoLA_PCREL_LARGE */ GPR, GPR, bare_symbol, /* PseudoLA_TLS_DESC_ABS */ GPR, bare_symbol, /* PseudoLA_TLS_DESC_ABS_LARGE */ GPR, GPR, bare_symbol, /* PseudoLA_TLS_DESC_PC */ GPR, bare_symbol, /* PseudoLA_TLS_DESC_PC_LARGE */ GPR, GPR, bare_symbol, /* PseudoLA_TLS_GD */ GPR, bare_symbol, /* PseudoLA_TLS_GD_LARGE */ GPR, GPR, bare_symbol, /* PseudoLA_TLS_IE */ GPR, bare_symbol, /* PseudoLA_TLS_IE_LARGE */ GPR, GPR, bare_symbol, /* PseudoLA_TLS_LD */ GPR, bare_symbol, /* PseudoLA_TLS_LD_LARGE */ GPR, GPR, bare_symbol, /* PseudoLA_TLS_LE */ GPR, bare_symbol, /* PseudoLD_CFR */ CFR, GPR, grlenimm, /* PseudoLI_D */ GPR, imm64, /* PseudoLI_W */ GPR, imm32, /* PseudoMaskedAtomicLoadAdd32 */ GPR, GPR, GPR, GPR, GPR, grlenimm, /* PseudoMaskedAtomicLoadMax32 */ GPR, GPR, GPR, GPR, GPR, GPR, grlenimm, grlenimm, /* PseudoMaskedAtomicLoadMin32 */ GPR, GPR, GPR, GPR, GPR, GPR, grlenimm, grlenimm, /* PseudoMaskedAtomicLoadNand32 */ GPR, GPR, GPR, GPR, GPR, grlenimm, /* PseudoMaskedAtomicLoadSub32 */ GPR, GPR, GPR, GPR, GPR, grlenimm, /* PseudoMaskedAtomicLoadUMax32 */ GPR, GPR, GPR, GPR, GPR, GPR, grlenimm, /* PseudoMaskedAtomicLoadUMin32 */ GPR, GPR, GPR, GPR, GPR, GPR, grlenimm, /* PseudoMaskedAtomicSwap32 */ GPR, GPR, GPR, GPR, GPR, grlenimm, /* PseudoMaskedCmpXchg32 */ GPR, GPR, GPR, GPR, GPR, GPR, grlenimm, /* PseudoRET */ /* PseudoST_CFR */ CFR, GPR, grlenimm, /* PseudoTAIL */ bare_symbol, /* PseudoTAIL36 */ GPR, bare_symbol, /* PseudoTAILIndirect */ GPRT, /* PseudoTAIL_LARGE */ bare_symbol, /* PseudoTAIL_MEDIUM */ bare_symbol, /* PseudoUNIMP */ /* PseudoVBNZ */ GPR, LSX128, /* PseudoVBNZ_B */ GPR, LSX128, /* PseudoVBNZ_D */ GPR, LSX128, /* PseudoVBNZ_H */ GPR, LSX128, /* PseudoVBNZ_W */ GPR, LSX128, /* PseudoVBZ */ GPR, LSX128, /* PseudoVBZ_B */ GPR, LSX128, /* PseudoVBZ_D */ GPR, LSX128, /* PseudoVBZ_H */ GPR, LSX128, /* PseudoVBZ_W */ GPR, LSX128, /* PseudoVREPLI_B */ LSX128, simm10, /* PseudoVREPLI_D */ LSX128, simm10, /* PseudoVREPLI_H */ LSX128, simm10, /* PseudoVREPLI_W */ LSX128, simm10, /* PseudoXVBNZ */ GPR, LASX256, /* PseudoXVBNZ_B */ GPR, LASX256, /* PseudoXVBNZ_D */ GPR, LASX256, /* PseudoXVBNZ_H */ GPR, LASX256, /* PseudoXVBNZ_W */ GPR, LASX256, /* PseudoXVBZ */ GPR, LASX256, /* PseudoXVBZ_B */ GPR, LASX256, /* PseudoXVBZ_D */ GPR, LASX256, /* PseudoXVBZ_H */ GPR, LASX256, /* PseudoXVBZ_W */ GPR, LASX256, /* PseudoXVINSGR2VR_B */ LASX256, LASX256, GPR, uimm5, /* PseudoXVINSGR2VR_H */ LASX256, LASX256, GPR, uimm4, /* PseudoXVREPLI_B */ LASX256, simm10, /* PseudoXVREPLI_D */ LASX256, simm10, /* PseudoXVREPLI_H */ LASX256, simm10, /* PseudoXVREPLI_W */ LASX256, simm10, /* RDFCSR */ GPR, uimm2, /* WRFCSR */ uimm2, GPR, /* ADC_B */ GPR, GPR, GPR, /* ADC_D */ GPR, GPR, GPR, /* ADC_H */ GPR, GPR, GPR, /* ADC_W */ GPR, GPR, GPR, /* ADDI_D */ GPR, GPR, simm12_addlike, /* ADDI_W */ GPR, GPR, simm12_addlike, /* ADDU12I_D */ GPR, GPR, simm5, /* ADDU12I_W */ GPR, GPR, simm5, /* ADDU16I_D */ GPR, GPR, simm16, /* ADD_D */ GPR, GPR, GPR, /* ADD_W */ GPR, GPR, GPR, /* ALSL_D */ GPR, GPR, GPR, uimm2_plus1, /* ALSL_W */ GPR, GPR, GPR, uimm2_plus1, /* ALSL_WU */ GPR, GPR, GPR, uimm2_plus1, /* AMADD_B */ GPR, GPR, GPRMemAtomic, /* AMADD_D */ GPR, GPR, GPRMemAtomic, /* AMADD_H */ GPR, GPR, GPRMemAtomic, /* AMADD_W */ GPR, GPR, GPRMemAtomic, /* AMADD__DB_B */ GPR, GPR, GPRMemAtomic, /* AMADD__DB_D */ GPR, GPR, GPRMemAtomic, /* AMADD__DB_H */ GPR, GPR, GPRMemAtomic, /* AMADD__DB_W */ GPR, GPR, GPRMemAtomic, /* AMAND_D */ GPR, GPR, GPRMemAtomic, /* AMAND_W */ GPR, GPR, GPRMemAtomic, /* AMAND__DB_D */ GPR, GPR, GPRMemAtomic, /* AMAND__DB_W */ GPR, GPR, GPRMemAtomic, /* AMCAS_B */ GPR, GPR, GPRMemAtomic, /* AMCAS_D */ GPR, GPR, GPRMemAtomic, /* AMCAS_H */ GPR, GPR, GPRMemAtomic, /* AMCAS_W */ GPR, GPR, GPRMemAtomic, /* AMCAS__DB_B */ GPR, GPR, GPRMemAtomic, /* AMCAS__DB_D */ GPR, GPR, GPRMemAtomic, /* AMCAS__DB_H */ GPR, GPR, GPRMemAtomic, /* AMCAS__DB_W */ GPR, GPR, GPRMemAtomic, /* AMMAX_D */ GPR, GPR, GPRMemAtomic, /* AMMAX_DU */ GPR, GPR, GPRMemAtomic, /* AMMAX_W */ GPR, GPR, GPRMemAtomic, /* AMMAX_WU */ GPR, GPR, GPRMemAtomic, /* AMMAX__DB_D */ GPR, GPR, GPRMemAtomic, /* AMMAX__DB_DU */ GPR, GPR, GPRMemAtomic, /* AMMAX__DB_W */ GPR, GPR, GPRMemAtomic, /* AMMAX__DB_WU */ GPR, GPR, GPRMemAtomic, /* AMMIN_D */ GPR, GPR, GPRMemAtomic, /* AMMIN_DU */ GPR, GPR, GPRMemAtomic, /* AMMIN_W */ GPR, GPR, GPRMemAtomic, /* AMMIN_WU */ GPR, GPR, GPRMemAtomic, /* AMMIN__DB_D */ GPR, GPR, GPRMemAtomic, /* AMMIN__DB_DU */ GPR, GPR, GPRMemAtomic, /* AMMIN__DB_W */ GPR, GPR, GPRMemAtomic, /* AMMIN__DB_WU */ GPR, GPR, GPRMemAtomic, /* AMOR_D */ GPR, GPR, GPRMemAtomic, /* AMOR_W */ GPR, GPR, GPRMemAtomic, /* AMOR__DB_D */ GPR, GPR, GPRMemAtomic, /* AMOR__DB_W */ GPR, GPR, GPRMemAtomic, /* AMSWAP_B */ GPR, GPR, GPRMemAtomic, /* AMSWAP_D */ GPR, GPR, GPRMemAtomic, /* AMSWAP_H */ GPR, GPR, GPRMemAtomic, /* AMSWAP_W */ GPR, GPR, GPRMemAtomic, /* AMSWAP__DB_B */ GPR, GPR, GPRMemAtomic, /* AMSWAP__DB_D */ GPR, GPR, GPRMemAtomic, /* AMSWAP__DB_H */ GPR, GPR, GPRMemAtomic, /* AMSWAP__DB_W */ GPR, GPR, GPRMemAtomic, /* AMXOR_D */ GPR, GPR, GPRMemAtomic, /* AMXOR_W */ GPR, GPR, GPRMemAtomic, /* AMXOR__DB_D */ GPR, GPR, GPRMemAtomic, /* AMXOR__DB_W */ GPR, GPR, GPRMemAtomic, /* AND */ GPR, GPR, GPR, /* ANDI */ GPR, GPR, uimm12, /* ANDN */ GPR, GPR, GPR, /* ARMADC_W */ GPR, GPR, uimm4, /* ARMADD_W */ GPR, GPR, uimm4, /* ARMAND_W */ GPR, GPR, uimm4, /* ARMMFFLAG */ GPR, uimm8, /* ARMMOVE */ GPR, GPR, uimm4, /* ARMMOV_D */ GPR, uimm4, /* ARMMOV_W */ GPR, uimm4, /* ARMMTFLAG */ GPR, uimm8, /* ARMNOT_W */ GPR, uimm4, /* ARMOR_W */ GPR, GPR, uimm4, /* ARMROTRI_W */ GPR, uimm5, uimm4, /* ARMROTR_W */ GPR, GPR, uimm4, /* ARMRRX_W */ GPR, uimm4, /* ARMSBC_W */ GPR, GPR, uimm4, /* ARMSLLI_W */ GPR, uimm5, uimm4, /* ARMSLL_W */ GPR, GPR, uimm4, /* ARMSRAI_W */ GPR, uimm5, uimm4, /* ARMSRA_W */ GPR, GPR, uimm4, /* ARMSRLI_W */ GPR, uimm5, uimm4, /* ARMSRL_W */ GPR, GPR, uimm4, /* ARMSUB_W */ GPR, GPR, uimm4, /* ARMXOR_W */ GPR, GPR, uimm4, /* ASRTGT_D */ GPR, GPR, /* ASRTLE_D */ GPR, GPR, /* B */ simm26_b, /* BCEQZ */ CFR, simm21_lsl2, /* BCNEZ */ CFR, simm21_lsl2, /* BEQ */ GPR, GPR, simm16_lsl2_br, /* BEQZ */ GPR, simm21_lsl2, /* BGE */ GPR, GPR, simm16_lsl2_br, /* BGEU */ GPR, GPR, simm16_lsl2_br, /* BITREV_4B */ GPR, GPR, /* BITREV_8B */ GPR, GPR, /* BITREV_D */ GPR, GPR, /* BITREV_W */ GPR, GPR, /* BL */ simm26_symbol, /* BLT */ GPR, GPR, simm16_lsl2_br, /* BLTU */ GPR, GPR, simm16_lsl2_br, /* BNE */ GPR, GPR, simm16_lsl2_br, /* BNEZ */ GPR, simm21_lsl2, /* BREAK */ uimm15, /* BSTRINS_D */ GPR, GPR, GPR, uimm6, uimm6, /* BSTRINS_W */ GPR, GPR, GPR, uimm5, uimm5, /* BSTRPICK_D */ GPR, GPR, uimm6, uimm6, /* BSTRPICK_W */ GPR, GPR, uimm5, uimm5, /* BYTEPICK_D */ GPR, GPR, GPR, uimm3, /* BYTEPICK_W */ GPR, GPR, GPR, uimm2, /* CACOP */ uimm5, GPR, simm12, /* CLO_D */ GPR, GPR, /* CLO_W */ GPR, GPR, /* CLZ_D */ GPR, GPR, /* CLZ_W */ GPR, GPR, /* CPUCFG */ GPR, GPR, /* CRCC_W_B_W */ GPR, GPR, GPR, /* CRCC_W_D_W */ GPR, GPR, GPR, /* CRCC_W_H_W */ GPR, GPR, GPR, /* CRCC_W_W_W */ GPR, GPR, GPR, /* CRC_W_B_W */ GPR, GPR, GPR, /* CRC_W_D_W */ GPR, GPR, GPR, /* CRC_W_H_W */ GPR, GPR, GPR, /* CRC_W_W_W */ GPR, GPR, GPR, /* CSRRD */ GPR, uimm14, /* CSRWR */ GPR, GPR, uimm14, /* CSRXCHG */ GPR, GPR, GPR, uimm14, /* CTO_D */ GPR, GPR, /* CTO_W */ GPR, GPR, /* CTZ_D */ GPR, GPR, /* CTZ_W */ GPR, GPR, /* DBAR */ uimm15, /* DBCL */ uimm15, /* DIV_D */ GPR, GPR, GPR, /* DIV_DU */ GPR, GPR, GPR, /* DIV_W */ GPR, GPR, GPR, /* DIV_WU */ GPR, GPR, GPR, /* ERTN */ /* EXT_W_B */ GPR, GPR, /* EXT_W_H */ GPR, GPR, /* FABS_D */ FPR64, FPR64, /* FABS_S */ FPR32, FPR32, /* FADD_D */ FPR64, FPR64, FPR64, /* FADD_S */ FPR32, FPR32, FPR32, /* FCLASS_D */ FPR64, FPR64, /* FCLASS_S */ FPR32, FPR32, /* FCMP_CAF_D */ CFR, FPR64, FPR64, /* FCMP_CAF_S */ CFR, FPR32, FPR32, /* FCMP_CEQ_D */ CFR, FPR64, FPR64, /* FCMP_CEQ_S */ CFR, FPR32, FPR32, /* FCMP_CLE_D */ CFR, FPR64, FPR64, /* FCMP_CLE_S */ CFR, FPR32, FPR32, /* FCMP_CLT_D */ CFR, FPR64, FPR64, /* FCMP_CLT_S */ CFR, FPR32, FPR32, /* FCMP_CNE_D */ CFR, FPR64, FPR64, /* FCMP_CNE_S */ CFR, FPR32, FPR32, /* FCMP_COR_D */ CFR, FPR64, FPR64, /* FCMP_COR_S */ CFR, FPR32, FPR32, /* FCMP_CUEQ_D */ CFR, FPR64, FPR64, /* FCMP_CUEQ_S */ CFR, FPR32, FPR32, /* FCMP_CULE_D */ CFR, FPR64, FPR64, /* FCMP_CULE_S */ CFR, FPR32, FPR32, /* FCMP_CULT_D */ CFR, FPR64, FPR64, /* FCMP_CULT_S */ CFR, FPR32, FPR32, /* FCMP_CUNE_D */ CFR, FPR64, FPR64, /* FCMP_CUNE_S */ CFR, FPR32, FPR32, /* FCMP_CUN_D */ CFR, FPR64, FPR64, /* FCMP_CUN_S */ CFR, FPR32, FPR32, /* FCMP_SAF_D */ CFR, FPR64, FPR64, /* FCMP_SAF_S */ CFR, FPR32, FPR32, /* FCMP_SEQ_D */ CFR, FPR64, FPR64, /* FCMP_SEQ_S */ CFR, FPR32, FPR32, /* FCMP_SLE_D */ CFR, FPR64, FPR64, /* FCMP_SLE_S */ CFR, FPR32, FPR32, /* FCMP_SLT_D */ CFR, FPR64, FPR64, /* FCMP_SLT_S */ CFR, FPR32, FPR32, /* FCMP_SNE_D */ CFR, FPR64, FPR64, /* FCMP_SNE_S */ CFR, FPR32, FPR32, /* FCMP_SOR_D */ CFR, FPR64, FPR64, /* FCMP_SOR_S */ CFR, FPR32, FPR32, /* FCMP_SUEQ_D */ CFR, FPR64, FPR64, /* FCMP_SUEQ_S */ CFR, FPR32, FPR32, /* FCMP_SULE_D */ CFR, FPR64, FPR64, /* FCMP_SULE_S */ CFR, FPR32, FPR32, /* FCMP_SULT_D */ CFR, FPR64, FPR64, /* FCMP_SULT_S */ CFR, FPR32, FPR32, /* FCMP_SUNE_D */ CFR, FPR64, FPR64, /* FCMP_SUNE_S */ CFR, FPR32, FPR32, /* FCMP_SUN_D */ CFR, FPR64, FPR64, /* FCMP_SUN_S */ CFR, FPR32, FPR32, /* FCOPYSIGN_D */ FPR64, FPR64, FPR64, /* FCOPYSIGN_S */ FPR32, FPR32, FPR32, /* FCVT_D_LD */ FPR32, FPR32, FPR32, /* FCVT_D_S */ FPR64, FPR32, /* FCVT_LD_D */ FPR32, FPR32, /* FCVT_S_D */ FPR32, FPR64, /* FCVT_UD_D */ FPR32, FPR32, /* FDIV_D */ FPR64, FPR64, FPR64, /* FDIV_S */ FPR32, FPR32, FPR32, /* FFINT_D_L */ FPR64, FPR64, /* FFINT_D_W */ FPR64, FPR32, /* FFINT_S_L */ FPR32, FPR64, /* FFINT_S_W */ FPR32, FPR32, /* FLDGT_D */ FPR64, GPR, GPR, /* FLDGT_S */ FPR32, GPR, GPR, /* FLDLE_D */ FPR64, GPR, GPR, /* FLDLE_S */ FPR32, GPR, GPR, /* FLDX_D */ FPR64, GPR, GPR, /* FLDX_S */ FPR32, GPR, GPR, /* FLD_D */ FPR64, GPR, simm12, /* FLD_S */ FPR32, GPR, simm12, /* FLOGB_D */ FPR64, FPR64, /* FLOGB_S */ FPR32, FPR32, /* FMADD_D */ FPR64, FPR64, FPR64, FPR64, /* FMADD_S */ FPR32, FPR32, FPR32, FPR32, /* FMAXA_D */ FPR64, FPR64, FPR64, /* FMAXA_S */ FPR32, FPR32, FPR32, /* FMAX_D */ FPR64, FPR64, FPR64, /* FMAX_S */ FPR32, FPR32, FPR32, /* FMINA_D */ FPR64, FPR64, FPR64, /* FMINA_S */ FPR32, FPR32, FPR32, /* FMIN_D */ FPR64, FPR64, FPR64, /* FMIN_S */ FPR32, FPR32, FPR32, /* FMOV_D */ FPR64, FPR64, /* FMOV_S */ FPR32, FPR32, /* FMSUB_D */ FPR64, FPR64, FPR64, FPR64, /* FMSUB_S */ FPR32, FPR32, FPR32, FPR32, /* FMUL_D */ FPR64, FPR64, FPR64, /* FMUL_S */ FPR32, FPR32, FPR32, /* FNEG_D */ FPR64, FPR64, /* FNEG_S */ FPR32, FPR32, /* FNMADD_D */ FPR64, FPR64, FPR64, FPR64, /* FNMADD_S */ FPR32, FPR32, FPR32, FPR32, /* FNMSUB_D */ FPR64, FPR64, FPR64, FPR64, /* FNMSUB_S */ FPR32, FPR32, FPR32, FPR32, /* FRECIPE_D */ FPR64, FPR64, /* FRECIPE_S */ FPR32, FPR32, /* FRECIP_D */ FPR64, FPR64, /* FRECIP_S */ FPR32, FPR32, /* FRINT_D */ FPR64, FPR64, /* FRINT_S */ FPR32, FPR32, /* FRSQRTE_D */ FPR64, FPR64, /* FRSQRTE_S */ FPR32, FPR32, /* FRSQRT_D */ FPR64, FPR64, /* FRSQRT_S */ FPR32, FPR32, /* FSCALEB_D */ FPR64, FPR64, FPR64, /* FSCALEB_S */ FPR32, FPR32, FPR32, /* FSEL_xD */ FPR64, FPR64, FPR64, CFR, /* FSEL_xS */ FPR32, FPR32, FPR32, CFR, /* FSQRT_D */ FPR64, FPR64, /* FSQRT_S */ FPR32, FPR32, /* FSTGT_D */ FPR64, GPR, GPR, /* FSTGT_S */ FPR32, GPR, GPR, /* FSTLE_D */ FPR64, GPR, GPR, /* FSTLE_S */ FPR32, GPR, GPR, /* FSTX_D */ FPR64, GPR, GPR, /* FSTX_S */ FPR32, GPR, GPR, /* FST_D */ FPR64, GPR, simm12, /* FST_S */ FPR32, GPR, simm12, /* FSUB_D */ FPR64, FPR64, FPR64, /* FSUB_S */ FPR32, FPR32, FPR32, /* FTINTRM_L_D */ FPR64, FPR64, /* FTINTRM_L_S */ FPR64, FPR32, /* FTINTRM_W_D */ FPR32, FPR64, /* FTINTRM_W_S */ FPR32, FPR32, /* FTINTRNE_L_D */ FPR64, FPR64, /* FTINTRNE_L_S */ FPR64, FPR32, /* FTINTRNE_W_D */ FPR32, FPR64, /* FTINTRNE_W_S */ FPR32, FPR32, /* FTINTRP_L_D */ FPR64, FPR64, /* FTINTRP_L_S */ FPR64, FPR32, /* FTINTRP_W_D */ FPR32, FPR64, /* FTINTRP_W_S */ FPR32, FPR32, /* FTINTRZ_L_D */ FPR64, FPR64, /* FTINTRZ_L_S */ FPR64, FPR32, /* FTINTRZ_W_D */ FPR32, FPR64, /* FTINTRZ_W_S */ FPR32, FPR32, /* FTINT_L_D */ FPR64, FPR64, /* FTINT_L_S */ FPR64, FPR32, /* FTINT_W_D */ FPR32, FPR64, /* FTINT_W_S */ FPR32, FPR32, /* GCSRRD */ GPR, uimm14, /* GCSRWR */ GPR, GPR, uimm14, /* GCSRXCHG */ GPR, GPR, GPR, uimm14, /* GTLBFLUSH */ /* HVCL */ uimm15, /* IBAR */ uimm15, /* IDLE */ uimm15, /* INVTLB */ GPR, GPR, uimm5, /* IOCSRRD_B */ GPR, GPR, /* IOCSRRD_D */ GPR, GPR, /* IOCSRRD_H */ GPR, GPR, /* IOCSRRD_W */ GPR, GPR, /* IOCSRWR_B */ GPR, GPR, /* IOCSRWR_D */ GPR, GPR, /* IOCSRWR_H */ GPR, GPR, /* IOCSRWR_W */ GPR, GPR, /* JIRL */ GPR, GPR, simm16_lsl2, /* JISCR0 */ simm21_lsl2, /* JISCR1 */ simm21_lsl2, /* LDDIR */ GPR, GPR, uimm8, /* LDGT_B */ GPR, GPR, GPR, /* LDGT_D */ GPR, GPR, GPR, /* LDGT_H */ GPR, GPR, GPR, /* LDGT_W */ GPR, GPR, GPR, /* LDLE_B */ GPR, GPR, GPR, /* LDLE_D */ GPR, GPR, GPR, /* LDLE_H */ GPR, GPR, GPR, /* LDLE_W */ GPR, GPR, GPR, /* LDL_D */ GPR, GPR, simm12_addlike, /* LDL_W */ GPR, GPR, simm12_addlike, /* LDPTE */ GPR, uimm8, /* LDPTR_D */ GPR, GPR, simm14_lsl2, /* LDPTR_W */ GPR, GPR, simm14_lsl2, /* LDR_D */ GPR, GPR, simm12_addlike, /* LDR_W */ GPR, GPR, simm12_addlike, /* LDX_B */ GPR, GPR, GPR, /* LDX_BU */ GPR, GPR, GPR, /* LDX_D */ GPR, GPR, GPR, /* LDX_H */ GPR, GPR, GPR, /* LDX_HU */ GPR, GPR, GPR, /* LDX_W */ GPR, GPR, GPR, /* LDX_WU */ GPR, GPR, GPR, /* LD_B */ GPR, GPR, simm12_addlike, /* LD_BU */ GPR, GPR, simm12_addlike, /* LD_D */ GPR, GPR, simm12_addlike, /* LD_H */ GPR, GPR, simm12_addlike, /* LD_HU */ GPR, GPR, simm12_addlike, /* LD_W */ GPR, GPR, simm12_addlike, /* LD_WU */ GPR, GPR, simm12_addlike, /* LLACQ_D */ GPR, GPR, /* LLACQ_W */ GPR, GPR, /* LL_D */ GPR, GPR, simm14_lsl2, /* LL_W */ GPR, GPR, simm14_lsl2, /* LU12I_W */ GPR, simm20_lu12iw, /* LU32I_D */ GPR, GPR, simm20_lu32id, /* LU52I_D */ GPR, GPR, simm12_lu52id, /* MASKEQZ */ GPR, GPR, GPR, /* MASKNEZ */ GPR, GPR, GPR, /* MOD_D */ GPR, GPR, GPR, /* MOD_DU */ GPR, GPR, GPR, /* MOD_W */ GPR, GPR, GPR, /* MOD_WU */ GPR, GPR, GPR, /* MOVCF2FR_xS */ FPR32, CFR, /* MOVCF2GR */ GPR, CFR, /* MOVFCSR2GR */ GPR, FCSR, /* MOVFR2CF_xS */ CFR, FPR32, /* MOVFR2GR_D */ GPR, FPR64, /* MOVFR2GR_S */ GPR, FPR32, /* MOVFR2GR_S_64 */ GPR, FPR64, /* MOVFRH2GR_S */ GPR, FPR64, /* MOVGR2CF */ CFR, GPR, /* MOVGR2FCSR */ FCSR, GPR, /* MOVGR2FRH_W */ FPR64, FPR64, GPR, /* MOVGR2FR_D */ FPR64, GPR, /* MOVGR2FR_W */ FPR32, GPR, /* MOVGR2FR_W_64 */ FPR64, GPR, /* MOVGR2SCR */ SCR, GPR, /* MOVSCR2GR */ GPR, SCR, /* MULH_D */ GPR, GPR, GPR, /* MULH_DU */ GPR, GPR, GPR, /* MULH_W */ GPR, GPR, GPR, /* MULH_WU */ GPR, GPR, GPR, /* MULW_D_W */ GPR, GPR, GPR, /* MULW_D_WU */ GPR, GPR, GPR, /* MUL_D */ GPR, GPR, GPR, /* MUL_W */ GPR, GPR, GPR, /* NOR */ GPR, GPR, GPR, /* OR */ GPR, GPR, GPR, /* ORI */ GPR, GPR, uimm12_ori, /* ORN */ GPR, GPR, GPR, /* PCADDI */ GPR, simm20_pcaddi, /* PCADDU12I */ GPR, simm20, /* PCADDU18I */ GPR, simm20_pcaddu18i, /* PCALAU12I */ GPR, simm20_pcalau12i, /* PRELD */ uimm5, GPR, simm12, /* PRELDX */ uimm5, GPR, GPR, /* RCRI_B */ GPR, GPR, uimm3, /* RCRI_D */ GPR, GPR, uimm6, /* RCRI_H */ GPR, GPR, uimm4, /* RCRI_W */ GPR, GPR, uimm5, /* RCR_B */ GPR, GPR, GPR, /* RCR_D */ GPR, GPR, GPR, /* RCR_H */ GPR, GPR, GPR, /* RCR_W */ GPR, GPR, GPR, /* RDTIMEH_W */ GPR, GPR, /* RDTIMEL_W */ GPR, GPR, /* RDTIME_D */ GPR, GPR, /* REVB_2H */ GPR, GPR, /* REVB_2W */ GPR, GPR, /* REVB_4H */ GPR, GPR, /* REVB_D */ GPR, GPR, /* REVH_2W */ GPR, GPR, /* REVH_D */ GPR, GPR, /* ROTRI_B */ GPR, GPR, uimm3, /* ROTRI_D */ GPR, GPR, uimm6, /* ROTRI_H */ GPR, GPR, uimm4, /* ROTRI_W */ GPR, GPR, uimm5, /* ROTR_B */ GPR, GPR, GPR, /* ROTR_D */ GPR, GPR, GPR, /* ROTR_H */ GPR, GPR, GPR, /* ROTR_W */ GPR, GPR, GPR, /* SBC_B */ GPR, GPR, GPR, /* SBC_D */ GPR, GPR, GPR, /* SBC_H */ GPR, GPR, GPR, /* SBC_W */ GPR, GPR, GPR, /* SCREL_D */ GPR, GPR, GPR, /* SCREL_W */ GPR, GPR, GPR, /* SC_D */ GPR, GPR, GPR, simm14_lsl2, /* SC_Q */ GPR, GPR, GPR, GPR, /* SC_W */ GPR, GPR, GPR, simm14_lsl2, /* SETARMJ */ GPR, uimm4, /* SETX86J */ GPR, uimm4, /* SETX86LOOPE */ GPR, GPR, /* SETX86LOOPNE */ GPR, GPR, /* SET_CFR_FALSE */ CFR, /* SET_CFR_TRUE */ CFR, /* SLLI_D */ GPR, GPR, uimm6, /* SLLI_W */ GPR, GPR, uimm5, /* SLL_D */ GPR, GPR, GPR, /* SLL_W */ GPR, GPR, GPR, /* SLT */ GPR, GPR, GPR, /* SLTI */ GPR, GPR, simm12, /* SLTU */ GPR, GPR, GPR, /* SLTUI */ GPR, GPR, simm12, /* SRAI_D */ GPR, GPR, uimm6, /* SRAI_W */ GPR, GPR, uimm5, /* SRA_D */ GPR, GPR, GPR, /* SRA_W */ GPR, GPR, GPR, /* SRLI_D */ GPR, GPR, uimm6, /* SRLI_W */ GPR, GPR, uimm5, /* SRL_D */ GPR, GPR, GPR, /* SRL_W */ GPR, GPR, GPR, /* STGT_B */ GPR, GPR, GPR, /* STGT_D */ GPR, GPR, GPR, /* STGT_H */ GPR, GPR, GPR, /* STGT_W */ GPR, GPR, GPR, /* STLE_B */ GPR, GPR, GPR, /* STLE_D */ GPR, GPR, GPR, /* STLE_H */ GPR, GPR, GPR, /* STLE_W */ GPR, GPR, GPR, /* STL_D */ GPR, GPR, simm12_addlike, /* STL_W */ GPR, GPR, simm12_addlike, /* STPTR_D */ GPR, GPR, simm14_lsl2, /* STPTR_W */ GPR, GPR, simm14_lsl2, /* STR_D */ GPR, GPR, simm12_addlike, /* STR_W */ GPR, GPR, simm12_addlike, /* STX_B */ GPR, GPR, GPR, /* STX_D */ GPR, GPR, GPR, /* STX_H */ GPR, GPR, GPR, /* STX_W */ GPR, GPR, GPR, /* ST_B */ GPR, GPR, simm12_addlike, /* ST_D */ GPR, GPR, simm12_addlike, /* ST_H */ GPR, GPR, simm12_addlike, /* ST_W */ GPR, GPR, simm12_addlike, /* SUB_D */ GPR, GPR, GPR, /* SUB_W */ GPR, GPR, GPR, /* SYSCALL */ uimm15, /* TLBCLR */ /* TLBFILL */ /* TLBFLUSH */ /* TLBRD */ /* TLBSRCH */ /* TLBWR */ /* VABSD_B */ LSX128, LSX128, LSX128, /* VABSD_BU */ LSX128, LSX128, LSX128, /* VABSD_D */ LSX128, LSX128, LSX128, /* VABSD_DU */ LSX128, LSX128, LSX128, /* VABSD_H */ LSX128, LSX128, LSX128, /* VABSD_HU */ LSX128, LSX128, LSX128, /* VABSD_W */ LSX128, LSX128, LSX128, /* VABSD_WU */ LSX128, LSX128, LSX128, /* VADDA_B */ LSX128, LSX128, LSX128, /* VADDA_D */ LSX128, LSX128, LSX128, /* VADDA_H */ LSX128, LSX128, LSX128, /* VADDA_W */ LSX128, LSX128, LSX128, /* VADDI_BU */ LSX128, LSX128, uimm5, /* VADDI_DU */ LSX128, LSX128, uimm5, /* VADDI_HU */ LSX128, LSX128, uimm5, /* VADDI_WU */ LSX128, LSX128, uimm5, /* VADDWEV_D_W */ LSX128, LSX128, LSX128, /* VADDWEV_D_WU */ LSX128, LSX128, LSX128, /* VADDWEV_D_WU_W */ LSX128, LSX128, LSX128, /* VADDWEV_H_B */ LSX128, LSX128, LSX128, /* VADDWEV_H_BU */ LSX128, LSX128, LSX128, /* VADDWEV_H_BU_B */ LSX128, LSX128, LSX128, /* VADDWEV_Q_D */ LSX128, LSX128, LSX128, /* VADDWEV_Q_DU */ LSX128, LSX128, LSX128, /* VADDWEV_Q_DU_D */ LSX128, LSX128, LSX128, /* VADDWEV_W_H */ LSX128, LSX128, LSX128, /* VADDWEV_W_HU */ LSX128, LSX128, LSX128, /* VADDWEV_W_HU_H */ LSX128, LSX128, LSX128, /* VADDWOD_D_W */ LSX128, LSX128, LSX128, /* VADDWOD_D_WU */ LSX128, LSX128, LSX128, /* VADDWOD_D_WU_W */ LSX128, LSX128, LSX128, /* VADDWOD_H_B */ LSX128, LSX128, LSX128, /* VADDWOD_H_BU */ LSX128, LSX128, LSX128, /* VADDWOD_H_BU_B */ LSX128, LSX128, LSX128, /* VADDWOD_Q_D */ LSX128, LSX128, LSX128, /* VADDWOD_Q_DU */ LSX128, LSX128, LSX128, /* VADDWOD_Q_DU_D */ LSX128, LSX128, LSX128, /* VADDWOD_W_H */ LSX128, LSX128, LSX128, /* VADDWOD_W_HU */ LSX128, LSX128, LSX128, /* VADDWOD_W_HU_H */ LSX128, LSX128, LSX128, /* VADD_B */ LSX128, LSX128, LSX128, /* VADD_D */ LSX128, LSX128, LSX128, /* VADD_H */ LSX128, LSX128, LSX128, /* VADD_Q */ LSX128, LSX128, LSX128, /* VADD_W */ LSX128, LSX128, LSX128, /* VANDI_B */ LSX128, LSX128, uimm8, /* VANDN_V */ LSX128, LSX128, LSX128, /* VAND_V */ LSX128, LSX128, LSX128, /* VAVGR_B */ LSX128, LSX128, LSX128, /* VAVGR_BU */ LSX128, LSX128, LSX128, /* VAVGR_D */ LSX128, LSX128, LSX128, /* VAVGR_DU */ LSX128, LSX128, LSX128, /* VAVGR_H */ LSX128, LSX128, LSX128, /* VAVGR_HU */ LSX128, LSX128, LSX128, /* VAVGR_W */ LSX128, LSX128, LSX128, /* VAVGR_WU */ LSX128, LSX128, LSX128, /* VAVG_B */ LSX128, LSX128, LSX128, /* VAVG_BU */ LSX128, LSX128, LSX128, /* VAVG_D */ LSX128, LSX128, LSX128, /* VAVG_DU */ LSX128, LSX128, LSX128, /* VAVG_H */ LSX128, LSX128, LSX128, /* VAVG_HU */ LSX128, LSX128, LSX128, /* VAVG_W */ LSX128, LSX128, LSX128, /* VAVG_WU */ LSX128, LSX128, LSX128, /* VBITCLRI_B */ LSX128, LSX128, uimm3, /* VBITCLRI_D */ LSX128, LSX128, uimm6, /* VBITCLRI_H */ LSX128, LSX128, uimm4, /* VBITCLRI_W */ LSX128, LSX128, uimm5, /* VBITCLR_B */ LSX128, LSX128, LSX128, /* VBITCLR_D */ LSX128, LSX128, LSX128, /* VBITCLR_H */ LSX128, LSX128, LSX128, /* VBITCLR_W */ LSX128, LSX128, LSX128, /* VBITREVI_B */ LSX128, LSX128, uimm3, /* VBITREVI_D */ LSX128, LSX128, uimm6, /* VBITREVI_H */ LSX128, LSX128, uimm4, /* VBITREVI_W */ LSX128, LSX128, uimm5, /* VBITREV_B */ LSX128, LSX128, LSX128, /* VBITREV_D */ LSX128, LSX128, LSX128, /* VBITREV_H */ LSX128, LSX128, LSX128, /* VBITREV_W */ LSX128, LSX128, LSX128, /* VBITSELI_B */ LSX128, LSX128, LSX128, uimm8, /* VBITSEL_V */ LSX128, LSX128, LSX128, LSX128, /* VBITSETI_B */ LSX128, LSX128, uimm3, /* VBITSETI_D */ LSX128, LSX128, uimm6, /* VBITSETI_H */ LSX128, LSX128, uimm4, /* VBITSETI_W */ LSX128, LSX128, uimm5, /* VBITSET_B */ LSX128, LSX128, LSX128, /* VBITSET_D */ LSX128, LSX128, LSX128, /* VBITSET_H */ LSX128, LSX128, LSX128, /* VBITSET_W */ LSX128, LSX128, LSX128, /* VBSLL_V */ LSX128, LSX128, uimm5, /* VBSRL_V */ LSX128, LSX128, uimm5, /* VCLO_B */ LSX128, LSX128, /* VCLO_D */ LSX128, LSX128, /* VCLO_H */ LSX128, LSX128, /* VCLO_W */ LSX128, LSX128, /* VCLZ_B */ LSX128, LSX128, /* VCLZ_D */ LSX128, LSX128, /* VCLZ_H */ LSX128, LSX128, /* VCLZ_W */ LSX128, LSX128, /* VDIV_B */ LSX128, LSX128, LSX128, /* VDIV_BU */ LSX128, LSX128, LSX128, /* VDIV_D */ LSX128, LSX128, LSX128, /* VDIV_DU */ LSX128, LSX128, LSX128, /* VDIV_H */ LSX128, LSX128, LSX128, /* VDIV_HU */ LSX128, LSX128, LSX128, /* VDIV_W */ LSX128, LSX128, LSX128, /* VDIV_WU */ LSX128, LSX128, LSX128, /* VEXT2XV_DU_BU */ LASX256, LASX256, /* VEXT2XV_DU_HU */ LASX256, LASX256, /* VEXT2XV_DU_WU */ LASX256, LASX256, /* VEXT2XV_D_B */ LASX256, LASX256, /* VEXT2XV_D_H */ LASX256, LASX256, /* VEXT2XV_D_W */ LASX256, LASX256, /* VEXT2XV_HU_BU */ LASX256, LASX256, /* VEXT2XV_H_B */ LASX256, LASX256, /* VEXT2XV_WU_BU */ LASX256, LASX256, /* VEXT2XV_WU_HU */ LASX256, LASX256, /* VEXT2XV_W_B */ LASX256, LASX256, /* VEXT2XV_W_H */ LASX256, LASX256, /* VEXTH_DU_WU */ LSX128, LSX128, /* VEXTH_D_W */ LSX128, LSX128, /* VEXTH_HU_BU */ LSX128, LSX128, /* VEXTH_H_B */ LSX128, LSX128, /* VEXTH_QU_DU */ LSX128, LSX128, /* VEXTH_Q_D */ LSX128, LSX128, /* VEXTH_WU_HU */ LSX128, LSX128, /* VEXTH_W_H */ LSX128, LSX128, /* VEXTL_QU_DU */ LSX128, LSX128, /* VEXTL_Q_D */ LSX128, LSX128, /* VEXTRINS_B */ LSX128, LSX128, LSX128, uimm8, /* VEXTRINS_D */ LSX128, LSX128, LSX128, uimm8, /* VEXTRINS_H */ LSX128, LSX128, LSX128, uimm8, /* VEXTRINS_W */ LSX128, LSX128, LSX128, uimm8, /* VFADD_D */ LSX128, LSX128, LSX128, /* VFADD_S */ LSX128, LSX128, LSX128, /* VFCLASS_D */ LSX128, LSX128, /* VFCLASS_S */ LSX128, LSX128, /* VFCMP_CAF_D */ LSX128, LSX128, LSX128, /* VFCMP_CAF_S */ LSX128, LSX128, LSX128, /* VFCMP_CEQ_D */ LSX128, LSX128, LSX128, /* VFCMP_CEQ_S */ LSX128, LSX128, LSX128, /* VFCMP_CLE_D */ LSX128, LSX128, LSX128, /* VFCMP_CLE_S */ LSX128, LSX128, LSX128, /* VFCMP_CLT_D */ LSX128, LSX128, LSX128, /* VFCMP_CLT_S */ LSX128, LSX128, LSX128, /* VFCMP_CNE_D */ LSX128, LSX128, LSX128, /* VFCMP_CNE_S */ LSX128, LSX128, LSX128, /* VFCMP_COR_D */ LSX128, LSX128, LSX128, /* VFCMP_COR_S */ LSX128, LSX128, LSX128, /* VFCMP_CUEQ_D */ LSX128, LSX128, LSX128, /* VFCMP_CUEQ_S */ LSX128, LSX128, LSX128, /* VFCMP_CULE_D */ LSX128, LSX128, LSX128, /* VFCMP_CULE_S */ LSX128, LSX128, LSX128, /* VFCMP_CULT_D */ LSX128, LSX128, LSX128, /* VFCMP_CULT_S */ LSX128, LSX128, LSX128, /* VFCMP_CUNE_D */ LSX128, LSX128, LSX128, /* VFCMP_CUNE_S */ LSX128, LSX128, LSX128, /* VFCMP_CUN_D */ LSX128, LSX128, LSX128, /* VFCMP_CUN_S */ LSX128, LSX128, LSX128, /* VFCMP_SAF_D */ LSX128, LSX128, LSX128, /* VFCMP_SAF_S */ LSX128, LSX128, LSX128, /* VFCMP_SEQ_D */ LSX128, LSX128, LSX128, /* VFCMP_SEQ_S */ LSX128, LSX128, LSX128, /* VFCMP_SLE_D */ LSX128, LSX128, LSX128, /* VFCMP_SLE_S */ LSX128, LSX128, LSX128, /* VFCMP_SLT_D */ LSX128, LSX128, LSX128, /* VFCMP_SLT_S */ LSX128, LSX128, LSX128, /* VFCMP_SNE_D */ LSX128, LSX128, LSX128, /* VFCMP_SNE_S */ LSX128, LSX128, LSX128, /* VFCMP_SOR_D */ LSX128, LSX128, LSX128, /* VFCMP_SOR_S */ LSX128, LSX128, LSX128, /* VFCMP_SUEQ_D */ LSX128, LSX128, LSX128, /* VFCMP_SUEQ_S */ LSX128, LSX128, LSX128, /* VFCMP_SULE_D */ LSX128, LSX128, LSX128, /* VFCMP_SULE_S */ LSX128, LSX128, LSX128, /* VFCMP_SULT_D */ LSX128, LSX128, LSX128, /* VFCMP_SULT_S */ LSX128, LSX128, LSX128, /* VFCMP_SUNE_D */ LSX128, LSX128, LSX128, /* VFCMP_SUNE_S */ LSX128, LSX128, LSX128, /* VFCMP_SUN_D */ LSX128, LSX128, LSX128, /* VFCMP_SUN_S */ LSX128, LSX128, LSX128, /* VFCVTH_D_S */ LSX128, LSX128, /* VFCVTH_S_H */ LSX128, LSX128, /* VFCVTL_D_S */ LSX128, LSX128, /* VFCVTL_S_H */ LSX128, LSX128, /* VFCVT_H_S */ LSX128, LSX128, LSX128, /* VFCVT_S_D */ LSX128, LSX128, LSX128, /* VFDIV_D */ LSX128, LSX128, LSX128, /* VFDIV_S */ LSX128, LSX128, LSX128, /* VFFINTH_D_W */ LSX128, LSX128, /* VFFINTL_D_W */ LSX128, LSX128, /* VFFINT_D_L */ LSX128, LSX128, /* VFFINT_D_LU */ LSX128, LSX128, /* VFFINT_S_L */ LSX128, LSX128, LSX128, /* VFFINT_S_W */ LSX128, LSX128, /* VFFINT_S_WU */ LSX128, LSX128, /* VFLOGB_D */ LSX128, LSX128, /* VFLOGB_S */ LSX128, LSX128, /* VFMADD_D */ LSX128, LSX128, LSX128, LSX128, /* VFMADD_S */ LSX128, LSX128, LSX128, LSX128, /* VFMAXA_D */ LSX128, LSX128, LSX128, /* VFMAXA_S */ LSX128, LSX128, LSX128, /* VFMAX_D */ LSX128, LSX128, LSX128, /* VFMAX_S */ LSX128, LSX128, LSX128, /* VFMINA_D */ LSX128, LSX128, LSX128, /* VFMINA_S */ LSX128, LSX128, LSX128, /* VFMIN_D */ LSX128, LSX128, LSX128, /* VFMIN_S */ LSX128, LSX128, LSX128, /* VFMSUB_D */ LSX128, LSX128, LSX128, LSX128, /* VFMSUB_S */ LSX128, LSX128, LSX128, LSX128, /* VFMUL_D */ LSX128, LSX128, LSX128, /* VFMUL_S */ LSX128, LSX128, LSX128, /* VFNMADD_D */ LSX128, LSX128, LSX128, LSX128, /* VFNMADD_S */ LSX128, LSX128, LSX128, LSX128, /* VFNMSUB_D */ LSX128, LSX128, LSX128, LSX128, /* VFNMSUB_S */ LSX128, LSX128, LSX128, LSX128, /* VFRECIPE_D */ LSX128, LSX128, /* VFRECIPE_S */ LSX128, LSX128, /* VFRECIP_D */ LSX128, LSX128, /* VFRECIP_S */ LSX128, LSX128, /* VFRINTRM_D */ LSX128, LSX128, /* VFRINTRM_S */ LSX128, LSX128, /* VFRINTRNE_D */ LSX128, LSX128, /* VFRINTRNE_S */ LSX128, LSX128, /* VFRINTRP_D */ LSX128, LSX128, /* VFRINTRP_S */ LSX128, LSX128, /* VFRINTRZ_D */ LSX128, LSX128, /* VFRINTRZ_S */ LSX128, LSX128, /* VFRINT_D */ LSX128, LSX128, /* VFRINT_S */ LSX128, LSX128, /* VFRSQRTE_D */ LSX128, LSX128, /* VFRSQRTE_S */ LSX128, LSX128, /* VFRSQRT_D */ LSX128, LSX128, /* VFRSQRT_S */ LSX128, LSX128, /* VFRSTPI_B */ LSX128, LSX128, LSX128, uimm5, /* VFRSTPI_H */ LSX128, LSX128, LSX128, uimm5, /* VFRSTP_B */ LSX128, LSX128, LSX128, LSX128, /* VFRSTP_H */ LSX128, LSX128, LSX128, LSX128, /* VFSQRT_D */ LSX128, LSX128, /* VFSQRT_S */ LSX128, LSX128, /* VFSUB_D */ LSX128, LSX128, LSX128, /* VFSUB_S */ LSX128, LSX128, LSX128, /* VFTINTH_L_S */ LSX128, LSX128, /* VFTINTL_L_S */ LSX128, LSX128, /* VFTINTRMH_L_S */ LSX128, LSX128, /* VFTINTRML_L_S */ LSX128, LSX128, /* VFTINTRM_L_D */ LSX128, LSX128, /* VFTINTRM_W_D */ LSX128, LSX128, LSX128, /* VFTINTRM_W_S */ LSX128, LSX128, /* VFTINTRNEH_L_S */ LSX128, LSX128, /* VFTINTRNEL_L_S */ LSX128, LSX128, /* VFTINTRNE_L_D */ LSX128, LSX128, /* VFTINTRNE_W_D */ LSX128, LSX128, LSX128, /* VFTINTRNE_W_S */ LSX128, LSX128, /* VFTINTRPH_L_S */ LSX128, LSX128, /* VFTINTRPL_L_S */ LSX128, LSX128, /* VFTINTRP_L_D */ LSX128, LSX128, /* VFTINTRP_W_D */ LSX128, LSX128, LSX128, /* VFTINTRP_W_S */ LSX128, LSX128, /* VFTINTRZH_L_S */ LSX128, LSX128, /* VFTINTRZL_L_S */ LSX128, LSX128, /* VFTINTRZ_LU_D */ LSX128, LSX128, /* VFTINTRZ_L_D */ LSX128, LSX128, /* VFTINTRZ_WU_S */ LSX128, LSX128, /* VFTINTRZ_W_D */ LSX128, LSX128, LSX128, /* VFTINTRZ_W_S */ LSX128, LSX128, /* VFTINT_LU_D */ LSX128, LSX128, /* VFTINT_L_D */ LSX128, LSX128, /* VFTINT_WU_S */ LSX128, LSX128, /* VFTINT_W_D */ LSX128, LSX128, LSX128, /* VFTINT_W_S */ LSX128, LSX128, /* VHADDW_DU_WU */ LSX128, LSX128, LSX128, /* VHADDW_D_W */ LSX128, LSX128, LSX128, /* VHADDW_HU_BU */ LSX128, LSX128, LSX128, /* VHADDW_H_B */ LSX128, LSX128, LSX128, /* VHADDW_QU_DU */ LSX128, LSX128, LSX128, /* VHADDW_Q_D */ LSX128, LSX128, LSX128, /* VHADDW_WU_HU */ LSX128, LSX128, LSX128, /* VHADDW_W_H */ LSX128, LSX128, LSX128, /* VHSUBW_DU_WU */ LSX128, LSX128, LSX128, /* VHSUBW_D_W */ LSX128, LSX128, LSX128, /* VHSUBW_HU_BU */ LSX128, LSX128, LSX128, /* VHSUBW_H_B */ LSX128, LSX128, LSX128, /* VHSUBW_QU_DU */ LSX128, LSX128, LSX128, /* VHSUBW_Q_D */ LSX128, LSX128, LSX128, /* VHSUBW_WU_HU */ LSX128, LSX128, LSX128, /* VHSUBW_W_H */ LSX128, LSX128, LSX128, /* VILVH_B */ LSX128, LSX128, LSX128, /* VILVH_D */ LSX128, LSX128, LSX128, /* VILVH_H */ LSX128, LSX128, LSX128, /* VILVH_W */ LSX128, LSX128, LSX128, /* VILVL_B */ LSX128, LSX128, LSX128, /* VILVL_D */ LSX128, LSX128, LSX128, /* VILVL_H */ LSX128, LSX128, LSX128, /* VILVL_W */ LSX128, LSX128, LSX128, /* VINSGR2VR_B */ LSX128, LSX128, GPR, uimm4, /* VINSGR2VR_D */ LSX128, LSX128, GPR, uimm1, /* VINSGR2VR_H */ LSX128, LSX128, GPR, uimm3, /* VINSGR2VR_W */ LSX128, LSX128, GPR, uimm2, /* VLD */ LSX128, GPR, simm12, /* VLDI */ LSX128, simm13, /* VLDREPL_B */ LSX128, GPR, simm12, /* VLDREPL_D */ LSX128, GPR, simm9_lsl3, /* VLDREPL_H */ LSX128, GPR, simm11_lsl1, /* VLDREPL_W */ LSX128, GPR, simm10_lsl2, /* VLDX */ LSX128, GPR, GPR, /* VMADDWEV_D_W */ LSX128, LSX128, LSX128, LSX128, /* VMADDWEV_D_WU */ LSX128, LSX128, LSX128, LSX128, /* VMADDWEV_D_WU_W */ LSX128, LSX128, LSX128, LSX128, /* VMADDWEV_H_B */ LSX128, LSX128, LSX128, LSX128, /* VMADDWEV_H_BU */ LSX128, LSX128, LSX128, LSX128, /* VMADDWEV_H_BU_B */ LSX128, LSX128, LSX128, LSX128, /* VMADDWEV_Q_D */ LSX128, LSX128, LSX128, LSX128, /* VMADDWEV_Q_DU */ LSX128, LSX128, LSX128, LSX128, /* VMADDWEV_Q_DU_D */ LSX128, LSX128, LSX128, LSX128, /* VMADDWEV_W_H */ LSX128, LSX128, LSX128, LSX128, /* VMADDWEV_W_HU */ LSX128, LSX128, LSX128, LSX128, /* VMADDWEV_W_HU_H */ LSX128, LSX128, LSX128, LSX128, /* VMADDWOD_D_W */ LSX128, LSX128, LSX128, LSX128, /* VMADDWOD_D_WU */ LSX128, LSX128, LSX128, LSX128, /* VMADDWOD_D_WU_W */ LSX128, LSX128, LSX128, LSX128, /* VMADDWOD_H_B */ LSX128, LSX128, LSX128, LSX128, /* VMADDWOD_H_BU */ LSX128, LSX128, LSX128, LSX128, /* VMADDWOD_H_BU_B */ LSX128, LSX128, LSX128, LSX128, /* VMADDWOD_Q_D */ LSX128, LSX128, LSX128, LSX128, /* VMADDWOD_Q_DU */ LSX128, LSX128, LSX128, LSX128, /* VMADDWOD_Q_DU_D */ LSX128, LSX128, LSX128, LSX128, /* VMADDWOD_W_H */ LSX128, LSX128, LSX128, LSX128, /* VMADDWOD_W_HU */ LSX128, LSX128, LSX128, LSX128, /* VMADDWOD_W_HU_H */ LSX128, LSX128, LSX128, LSX128, /* VMADD_B */ LSX128, LSX128, LSX128, LSX128, /* VMADD_D */ LSX128, LSX128, LSX128, LSX128, /* VMADD_H */ LSX128, LSX128, LSX128, LSX128, /* VMADD_W */ LSX128, LSX128, LSX128, LSX128, /* VMAXI_B */ LSX128, LSX128, simm5, /* VMAXI_BU */ LSX128, LSX128, uimm5, /* VMAXI_D */ LSX128, LSX128, simm5, /* VMAXI_DU */ LSX128, LSX128, uimm5, /* VMAXI_H */ LSX128, LSX128, simm5, /* VMAXI_HU */ LSX128, LSX128, uimm5, /* VMAXI_W */ LSX128, LSX128, simm5, /* VMAXI_WU */ LSX128, LSX128, uimm5, /* VMAX_B */ LSX128, LSX128, LSX128, /* VMAX_BU */ LSX128, LSX128, LSX128, /* VMAX_D */ LSX128, LSX128, LSX128, /* VMAX_DU */ LSX128, LSX128, LSX128, /* VMAX_H */ LSX128, LSX128, LSX128, /* VMAX_HU */ LSX128, LSX128, LSX128, /* VMAX_W */ LSX128, LSX128, LSX128, /* VMAX_WU */ LSX128, LSX128, LSX128, /* VMINI_B */ LSX128, LSX128, simm5, /* VMINI_BU */ LSX128, LSX128, uimm5, /* VMINI_D */ LSX128, LSX128, simm5, /* VMINI_DU */ LSX128, LSX128, uimm5, /* VMINI_H */ LSX128, LSX128, simm5, /* VMINI_HU */ LSX128, LSX128, uimm5, /* VMINI_W */ LSX128, LSX128, simm5, /* VMINI_WU */ LSX128, LSX128, uimm5, /* VMIN_B */ LSX128, LSX128, LSX128, /* VMIN_BU */ LSX128, LSX128, LSX128, /* VMIN_D */ LSX128, LSX128, LSX128, /* VMIN_DU */ LSX128, LSX128, LSX128, /* VMIN_H */ LSX128, LSX128, LSX128, /* VMIN_HU */ LSX128, LSX128, LSX128, /* VMIN_W */ LSX128, LSX128, LSX128, /* VMIN_WU */ LSX128, LSX128, LSX128, /* VMOD_B */ LSX128, LSX128, LSX128, /* VMOD_BU */ LSX128, LSX128, LSX128, /* VMOD_D */ LSX128, LSX128, LSX128, /* VMOD_DU */ LSX128, LSX128, LSX128, /* VMOD_H */ LSX128, LSX128, LSX128, /* VMOD_HU */ LSX128, LSX128, LSX128, /* VMOD_W */ LSX128, LSX128, LSX128, /* VMOD_WU */ LSX128, LSX128, LSX128, /* VMSKGEZ_B */ LSX128, LSX128, /* VMSKLTZ_B */ LSX128, LSX128, /* VMSKLTZ_D */ LSX128, LSX128, /* VMSKLTZ_H */ LSX128, LSX128, /* VMSKLTZ_W */ LSX128, LSX128, /* VMSKNZ_B */ LSX128, LSX128, /* VMSUB_B */ LSX128, LSX128, LSX128, LSX128, /* VMSUB_D */ LSX128, LSX128, LSX128, LSX128, /* VMSUB_H */ LSX128, LSX128, LSX128, LSX128, /* VMSUB_W */ LSX128, LSX128, LSX128, LSX128, /* VMUH_B */ LSX128, LSX128, LSX128, /* VMUH_BU */ LSX128, LSX128, LSX128, /* VMUH_D */ LSX128, LSX128, LSX128, /* VMUH_DU */ LSX128, LSX128, LSX128, /* VMUH_H */ LSX128, LSX128, LSX128, /* VMUH_HU */ LSX128, LSX128, LSX128, /* VMUH_W */ LSX128, LSX128, LSX128, /* VMUH_WU */ LSX128, LSX128, LSX128, /* VMULWEV_D_W */ LSX128, LSX128, LSX128, /* VMULWEV_D_WU */ LSX128, LSX128, LSX128, /* VMULWEV_D_WU_W */ LSX128, LSX128, LSX128, /* VMULWEV_H_B */ LSX128, LSX128, LSX128, /* VMULWEV_H_BU */ LSX128, LSX128, LSX128, /* VMULWEV_H_BU_B */ LSX128, LSX128, LSX128, /* VMULWEV_Q_D */ LSX128, LSX128, LSX128, /* VMULWEV_Q_DU */ LSX128, LSX128, LSX128, /* VMULWEV_Q_DU_D */ LSX128, LSX128, LSX128, /* VMULWEV_W_H */ LSX128, LSX128, LSX128, /* VMULWEV_W_HU */ LSX128, LSX128, LSX128, /* VMULWEV_W_HU_H */ LSX128, LSX128, LSX128, /* VMULWOD_D_W */ LSX128, LSX128, LSX128, /* VMULWOD_D_WU */ LSX128, LSX128, LSX128, /* VMULWOD_D_WU_W */ LSX128, LSX128, LSX128, /* VMULWOD_H_B */ LSX128, LSX128, LSX128, /* VMULWOD_H_BU */ LSX128, LSX128, LSX128, /* VMULWOD_H_BU_B */ LSX128, LSX128, LSX128, /* VMULWOD_Q_D */ LSX128, LSX128, LSX128, /* VMULWOD_Q_DU */ LSX128, LSX128, LSX128, /* VMULWOD_Q_DU_D */ LSX128, LSX128, LSX128, /* VMULWOD_W_H */ LSX128, LSX128, LSX128, /* VMULWOD_W_HU */ LSX128, LSX128, LSX128, /* VMULWOD_W_HU_H */ LSX128, LSX128, LSX128, /* VMUL_B */ LSX128, LSX128, LSX128, /* VMUL_D */ LSX128, LSX128, LSX128, /* VMUL_H */ LSX128, LSX128, LSX128, /* VMUL_W */ LSX128, LSX128, LSX128, /* VNEG_B */ LSX128, LSX128, /* VNEG_D */ LSX128, LSX128, /* VNEG_H */ LSX128, LSX128, /* VNEG_W */ LSX128, LSX128, /* VNORI_B */ LSX128, LSX128, uimm8, /* VNOR_V */ LSX128, LSX128, LSX128, /* VORI_B */ LSX128, LSX128, uimm8, /* VORN_V */ LSX128, LSX128, LSX128, /* VOR_V */ LSX128, LSX128, LSX128, /* VPACKEV_B */ LSX128, LSX128, LSX128, /* VPACKEV_D */ LSX128, LSX128, LSX128, /* VPACKEV_H */ LSX128, LSX128, LSX128, /* VPACKEV_W */ LSX128, LSX128, LSX128, /* VPACKOD_B */ LSX128, LSX128, LSX128, /* VPACKOD_D */ LSX128, LSX128, LSX128, /* VPACKOD_H */ LSX128, LSX128, LSX128, /* VPACKOD_W */ LSX128, LSX128, LSX128, /* VPCNT_B */ LSX128, LSX128, /* VPCNT_D */ LSX128, LSX128, /* VPCNT_H */ LSX128, LSX128, /* VPCNT_W */ LSX128, LSX128, /* VPERMI_W */ LSX128, LSX128, LSX128, uimm8, /* VPICKEV_B */ LSX128, LSX128, LSX128, /* VPICKEV_D */ LSX128, LSX128, LSX128, /* VPICKEV_H */ LSX128, LSX128, LSX128, /* VPICKEV_W */ LSX128, LSX128, LSX128, /* VPICKOD_B */ LSX128, LSX128, LSX128, /* VPICKOD_D */ LSX128, LSX128, LSX128, /* VPICKOD_H */ LSX128, LSX128, LSX128, /* VPICKOD_W */ LSX128, LSX128, LSX128, /* VPICKVE2GR_B */ GPR, LSX128, uimm4, /* VPICKVE2GR_BU */ GPR, LSX128, uimm4, /* VPICKVE2GR_D */ GPR, LSX128, uimm1, /* VPICKVE2GR_DU */ GPR, LSX128, uimm1, /* VPICKVE2GR_H */ GPR, LSX128, uimm3, /* VPICKVE2GR_HU */ GPR, LSX128, uimm3, /* VPICKVE2GR_W */ GPR, LSX128, uimm2, /* VPICKVE2GR_WU */ GPR, LSX128, uimm2, /* VREPLGR2VR_B */ LSX128, GPR, /* VREPLGR2VR_D */ LSX128, GPR, /* VREPLGR2VR_H */ LSX128, GPR, /* VREPLGR2VR_W */ LSX128, GPR, /* VREPLVEI_B */ LSX128, LSX128, uimm4, /* VREPLVEI_D */ LSX128, LSX128, uimm1, /* VREPLVEI_H */ LSX128, LSX128, uimm3, /* VREPLVEI_W */ LSX128, LSX128, uimm2, /* VREPLVE_B */ LSX128, LSX128, GPR, /* VREPLVE_D */ LSX128, LSX128, GPR, /* VREPLVE_H */ LSX128, LSX128, GPR, /* VREPLVE_W */ LSX128, LSX128, GPR, /* VROTRI_B */ LSX128, LSX128, uimm3, /* VROTRI_D */ LSX128, LSX128, uimm6, /* VROTRI_H */ LSX128, LSX128, uimm4, /* VROTRI_W */ LSX128, LSX128, uimm5, /* VROTR_B */ LSX128, LSX128, LSX128, /* VROTR_D */ LSX128, LSX128, LSX128, /* VROTR_H */ LSX128, LSX128, LSX128, /* VROTR_W */ LSX128, LSX128, LSX128, /* VSADD_B */ LSX128, LSX128, LSX128, /* VSADD_BU */ LSX128, LSX128, LSX128, /* VSADD_D */ LSX128, LSX128, LSX128, /* VSADD_DU */ LSX128, LSX128, LSX128, /* VSADD_H */ LSX128, LSX128, LSX128, /* VSADD_HU */ LSX128, LSX128, LSX128, /* VSADD_W */ LSX128, LSX128, LSX128, /* VSADD_WU */ LSX128, LSX128, LSX128, /* VSAT_B */ LSX128, LSX128, uimm3, /* VSAT_BU */ LSX128, LSX128, uimm3, /* VSAT_D */ LSX128, LSX128, uimm6, /* VSAT_DU */ LSX128, LSX128, uimm6, /* VSAT_H */ LSX128, LSX128, uimm4, /* VSAT_HU */ LSX128, LSX128, uimm4, /* VSAT_W */ LSX128, LSX128, uimm5, /* VSAT_WU */ LSX128, LSX128, uimm5, /* VSEQI_B */ LSX128, LSX128, simm5, /* VSEQI_D */ LSX128, LSX128, simm5, /* VSEQI_H */ LSX128, LSX128, simm5, /* VSEQI_W */ LSX128, LSX128, simm5, /* VSEQ_B */ LSX128, LSX128, LSX128, /* VSEQ_D */ LSX128, LSX128, LSX128, /* VSEQ_H */ LSX128, LSX128, LSX128, /* VSEQ_W */ LSX128, LSX128, LSX128, /* VSETALLNEZ_B */ CFR, LSX128, /* VSETALLNEZ_D */ CFR, LSX128, /* VSETALLNEZ_H */ CFR, LSX128, /* VSETALLNEZ_W */ CFR, LSX128, /* VSETANYEQZ_B */ CFR, LSX128, /* VSETANYEQZ_D */ CFR, LSX128, /* VSETANYEQZ_H */ CFR, LSX128, /* VSETANYEQZ_W */ CFR, LSX128, /* VSETEQZ_V */ CFR, LSX128, /* VSETNEZ_V */ CFR, LSX128, /* VSHUF4I_B */ LSX128, LSX128, uimm8, /* VSHUF4I_D */ LSX128, LSX128, LSX128, uimm8, /* VSHUF4I_H */ LSX128, LSX128, uimm8, /* VSHUF4I_W */ LSX128, LSX128, uimm8, /* VSHUF_B */ LSX128, LSX128, LSX128, LSX128, /* VSHUF_D */ LSX128, LSX128, LSX128, LSX128, /* VSHUF_H */ LSX128, LSX128, LSX128, LSX128, /* VSHUF_W */ LSX128, LSX128, LSX128, LSX128, /* VSIGNCOV_B */ LSX128, LSX128, LSX128, /* VSIGNCOV_D */ LSX128, LSX128, LSX128, /* VSIGNCOV_H */ LSX128, LSX128, LSX128, /* VSIGNCOV_W */ LSX128, LSX128, LSX128, /* VSLEI_B */ LSX128, LSX128, simm5, /* VSLEI_BU */ LSX128, LSX128, uimm5, /* VSLEI_D */ LSX128, LSX128, simm5, /* VSLEI_DU */ LSX128, LSX128, uimm5, /* VSLEI_H */ LSX128, LSX128, simm5, /* VSLEI_HU */ LSX128, LSX128, uimm5, /* VSLEI_W */ LSX128, LSX128, simm5, /* VSLEI_WU */ LSX128, LSX128, uimm5, /* VSLE_B */ LSX128, LSX128, LSX128, /* VSLE_BU */ LSX128, LSX128, LSX128, /* VSLE_D */ LSX128, LSX128, LSX128, /* VSLE_DU */ LSX128, LSX128, LSX128, /* VSLE_H */ LSX128, LSX128, LSX128, /* VSLE_HU */ LSX128, LSX128, LSX128, /* VSLE_W */ LSX128, LSX128, LSX128, /* VSLE_WU */ LSX128, LSX128, LSX128, /* VSLLI_B */ LSX128, LSX128, uimm3, /* VSLLI_D */ LSX128, LSX128, uimm6, /* VSLLI_H */ LSX128, LSX128, uimm4, /* VSLLI_W */ LSX128, LSX128, uimm5, /* VSLLWIL_DU_WU */ LSX128, LSX128, uimm5, /* VSLLWIL_D_W */ LSX128, LSX128, uimm5, /* VSLLWIL_HU_BU */ LSX128, LSX128, uimm3, /* VSLLWIL_H_B */ LSX128, LSX128, uimm3, /* VSLLWIL_WU_HU */ LSX128, LSX128, uimm4, /* VSLLWIL_W_H */ LSX128, LSX128, uimm4, /* VSLL_B */ LSX128, LSX128, LSX128, /* VSLL_D */ LSX128, LSX128, LSX128, /* VSLL_H */ LSX128, LSX128, LSX128, /* VSLL_W */ LSX128, LSX128, LSX128, /* VSLTI_B */ LSX128, LSX128, simm5, /* VSLTI_BU */ LSX128, LSX128, uimm5, /* VSLTI_D */ LSX128, LSX128, simm5, /* VSLTI_DU */ LSX128, LSX128, uimm5, /* VSLTI_H */ LSX128, LSX128, simm5, /* VSLTI_HU */ LSX128, LSX128, uimm5, /* VSLTI_W */ LSX128, LSX128, simm5, /* VSLTI_WU */ LSX128, LSX128, uimm5, /* VSLT_B */ LSX128, LSX128, LSX128, /* VSLT_BU */ LSX128, LSX128, LSX128, /* VSLT_D */ LSX128, LSX128, LSX128, /* VSLT_DU */ LSX128, LSX128, LSX128, /* VSLT_H */ LSX128, LSX128, LSX128, /* VSLT_HU */ LSX128, LSX128, LSX128, /* VSLT_W */ LSX128, LSX128, LSX128, /* VSLT_WU */ LSX128, LSX128, LSX128, /* VSRAI_B */ LSX128, LSX128, uimm3, /* VSRAI_D */ LSX128, LSX128, uimm6, /* VSRAI_H */ LSX128, LSX128, uimm4, /* VSRAI_W */ LSX128, LSX128, uimm5, /* VSRANI_B_H */ LSX128, LSX128, LSX128, uimm4, /* VSRANI_D_Q */ LSX128, LSX128, LSX128, uimm7, /* VSRANI_H_W */ LSX128, LSX128, LSX128, uimm5, /* VSRANI_W_D */ LSX128, LSX128, LSX128, uimm6, /* VSRAN_B_H */ LSX128, LSX128, LSX128, /* VSRAN_H_W */ LSX128, LSX128, LSX128, /* VSRAN_W_D */ LSX128, LSX128, LSX128, /* VSRARI_B */ LSX128, LSX128, uimm3, /* VSRARI_D */ LSX128, LSX128, uimm6, /* VSRARI_H */ LSX128, LSX128, uimm4, /* VSRARI_W */ LSX128, LSX128, uimm5, /* VSRARNI_B_H */ LSX128, LSX128, LSX128, uimm4, /* VSRARNI_D_Q */ LSX128, LSX128, LSX128, uimm7, /* VSRARNI_H_W */ LSX128, LSX128, LSX128, uimm5, /* VSRARNI_W_D */ LSX128, LSX128, LSX128, uimm6, /* VSRARN_B_H */ LSX128, LSX128, LSX128, /* VSRARN_H_W */ LSX128, LSX128, LSX128, /* VSRARN_W_D */ LSX128, LSX128, LSX128, /* VSRAR_B */ LSX128, LSX128, LSX128, /* VSRAR_D */ LSX128, LSX128, LSX128, /* VSRAR_H */ LSX128, LSX128, LSX128, /* VSRAR_W */ LSX128, LSX128, LSX128, /* VSRA_B */ LSX128, LSX128, LSX128, /* VSRA_D */ LSX128, LSX128, LSX128, /* VSRA_H */ LSX128, LSX128, LSX128, /* VSRA_W */ LSX128, LSX128, LSX128, /* VSRLI_B */ LSX128, LSX128, uimm3, /* VSRLI_D */ LSX128, LSX128, uimm6, /* VSRLI_H */ LSX128, LSX128, uimm4, /* VSRLI_W */ LSX128, LSX128, uimm5, /* VSRLNI_B_H */ LSX128, LSX128, LSX128, uimm4, /* VSRLNI_D_Q */ LSX128, LSX128, LSX128, uimm7, /* VSRLNI_H_W */ LSX128, LSX128, LSX128, uimm5, /* VSRLNI_W_D */ LSX128, LSX128, LSX128, uimm6, /* VSRLN_B_H */ LSX128, LSX128, LSX128, /* VSRLN_H_W */ LSX128, LSX128, LSX128, /* VSRLN_W_D */ LSX128, LSX128, LSX128, /* VSRLRI_B */ LSX128, LSX128, uimm3, /* VSRLRI_D */ LSX128, LSX128, uimm6, /* VSRLRI_H */ LSX128, LSX128, uimm4, /* VSRLRI_W */ LSX128, LSX128, uimm5, /* VSRLRNI_B_H */ LSX128, LSX128, LSX128, uimm4, /* VSRLRNI_D_Q */ LSX128, LSX128, LSX128, uimm7, /* VSRLRNI_H_W */ LSX128, LSX128, LSX128, uimm5, /* VSRLRNI_W_D */ LSX128, LSX128, LSX128, uimm6, /* VSRLRN_B_H */ LSX128, LSX128, LSX128, /* VSRLRN_H_W */ LSX128, LSX128, LSX128, /* VSRLRN_W_D */ LSX128, LSX128, LSX128, /* VSRLR_B */ LSX128, LSX128, LSX128, /* VSRLR_D */ LSX128, LSX128, LSX128, /* VSRLR_H */ LSX128, LSX128, LSX128, /* VSRLR_W */ LSX128, LSX128, LSX128, /* VSRL_B */ LSX128, LSX128, LSX128, /* VSRL_D */ LSX128, LSX128, LSX128, /* VSRL_H */ LSX128, LSX128, LSX128, /* VSRL_W */ LSX128, LSX128, LSX128, /* VSSRANI_BU_H */ LSX128, LSX128, LSX128, uimm4, /* VSSRANI_B_H */ LSX128, LSX128, LSX128, uimm4, /* VSSRANI_DU_Q */ LSX128, LSX128, LSX128, uimm7, /* VSSRANI_D_Q */ LSX128, LSX128, LSX128, uimm7, /* VSSRANI_HU_W */ LSX128, LSX128, LSX128, uimm5, /* VSSRANI_H_W */ LSX128, LSX128, LSX128, uimm5, /* VSSRANI_WU_D */ LSX128, LSX128, LSX128, uimm6, /* VSSRANI_W_D */ LSX128, LSX128, LSX128, uimm6, /* VSSRAN_BU_H */ LSX128, LSX128, LSX128, /* VSSRAN_B_H */ LSX128, LSX128, LSX128, /* VSSRAN_HU_W */ LSX128, LSX128, LSX128, /* VSSRAN_H_W */ LSX128, LSX128, LSX128, /* VSSRAN_WU_D */ LSX128, LSX128, LSX128, /* VSSRAN_W_D */ LSX128, LSX128, LSX128, /* VSSRARNI_BU_H */ LSX128, LSX128, LSX128, uimm4, /* VSSRARNI_B_H */ LSX128, LSX128, LSX128, uimm4, /* VSSRARNI_DU_Q */ LSX128, LSX128, LSX128, uimm7, /* VSSRARNI_D_Q */ LSX128, LSX128, LSX128, uimm7, /* VSSRARNI_HU_W */ LSX128, LSX128, LSX128, uimm5, /* VSSRARNI_H_W */ LSX128, LSX128, LSX128, uimm5, /* VSSRARNI_WU_D */ LSX128, LSX128, LSX128, uimm6, /* VSSRARNI_W_D */ LSX128, LSX128, LSX128, uimm6, /* VSSRARN_BU_H */ LSX128, LSX128, LSX128, /* VSSRARN_B_H */ LSX128, LSX128, LSX128, /* VSSRARN_HU_W */ LSX128, LSX128, LSX128, /* VSSRARN_H_W */ LSX128, LSX128, LSX128, /* VSSRARN_WU_D */ LSX128, LSX128, LSX128, /* VSSRARN_W_D */ LSX128, LSX128, LSX128, /* VSSRLNI_BU_H */ LSX128, LSX128, LSX128, uimm4, /* VSSRLNI_B_H */ LSX128, LSX128, LSX128, uimm4, /* VSSRLNI_DU_Q */ LSX128, LSX128, LSX128, uimm7, /* VSSRLNI_D_Q */ LSX128, LSX128, LSX128, uimm7, /* VSSRLNI_HU_W */ LSX128, LSX128, LSX128, uimm5, /* VSSRLNI_H_W */ LSX128, LSX128, LSX128, uimm5, /* VSSRLNI_WU_D */ LSX128, LSX128, LSX128, uimm6, /* VSSRLNI_W_D */ LSX128, LSX128, LSX128, uimm6, /* VSSRLN_BU_H */ LSX128, LSX128, LSX128, /* VSSRLN_B_H */ LSX128, LSX128, LSX128, /* VSSRLN_HU_W */ LSX128, LSX128, LSX128, /* VSSRLN_H_W */ LSX128, LSX128, LSX128, /* VSSRLN_WU_D */ LSX128, LSX128, LSX128, /* VSSRLN_W_D */ LSX128, LSX128, LSX128, /* VSSRLRNI_BU_H */ LSX128, LSX128, LSX128, uimm4, /* VSSRLRNI_B_H */ LSX128, LSX128, LSX128, uimm4, /* VSSRLRNI_DU_Q */ LSX128, LSX128, LSX128, uimm7, /* VSSRLRNI_D_Q */ LSX128, LSX128, LSX128, uimm7, /* VSSRLRNI_HU_W */ LSX128, LSX128, LSX128, uimm5, /* VSSRLRNI_H_W */ LSX128, LSX128, LSX128, uimm5, /* VSSRLRNI_WU_D */ LSX128, LSX128, LSX128, uimm6, /* VSSRLRNI_W_D */ LSX128, LSX128, LSX128, uimm6, /* VSSRLRN_BU_H */ LSX128, LSX128, LSX128, /* VSSRLRN_B_H */ LSX128, LSX128, LSX128, /* VSSRLRN_HU_W */ LSX128, LSX128, LSX128, /* VSSRLRN_H_W */ LSX128, LSX128, LSX128, /* VSSRLRN_WU_D */ LSX128, LSX128, LSX128, /* VSSRLRN_W_D */ LSX128, LSX128, LSX128, /* VSSUB_B */ LSX128, LSX128, LSX128, /* VSSUB_BU */ LSX128, LSX128, LSX128, /* VSSUB_D */ LSX128, LSX128, LSX128, /* VSSUB_DU */ LSX128, LSX128, LSX128, /* VSSUB_H */ LSX128, LSX128, LSX128, /* VSSUB_HU */ LSX128, LSX128, LSX128, /* VSSUB_W */ LSX128, LSX128, LSX128, /* VSSUB_WU */ LSX128, LSX128, LSX128, /* VST */ LSX128, GPR, simm12, /* VSTELM_B */ LSX128, GPR, simm8, uimm4, /* VSTELM_D */ LSX128, GPR, simm8_lsl3, uimm1, /* VSTELM_H */ LSX128, GPR, simm8_lsl1, uimm3, /* VSTELM_W */ LSX128, GPR, simm8_lsl2, uimm2, /* VSTX */ LSX128, GPR, GPR, /* VSUBI_BU */ LSX128, LSX128, uimm5, /* VSUBI_DU */ LSX128, LSX128, uimm5, /* VSUBI_HU */ LSX128, LSX128, uimm5, /* VSUBI_WU */ LSX128, LSX128, uimm5, /* VSUBWEV_D_W */ LSX128, LSX128, LSX128, /* VSUBWEV_D_WU */ LSX128, LSX128, LSX128, /* VSUBWEV_H_B */ LSX128, LSX128, LSX128, /* VSUBWEV_H_BU */ LSX128, LSX128, LSX128, /* VSUBWEV_Q_D */ LSX128, LSX128, LSX128, /* VSUBWEV_Q_DU */ LSX128, LSX128, LSX128, /* VSUBWEV_W_H */ LSX128, LSX128, LSX128, /* VSUBWEV_W_HU */ LSX128, LSX128, LSX128, /* VSUBWOD_D_W */ LSX128, LSX128, LSX128, /* VSUBWOD_D_WU */ LSX128, LSX128, LSX128, /* VSUBWOD_H_B */ LSX128, LSX128, LSX128, /* VSUBWOD_H_BU */ LSX128, LSX128, LSX128, /* VSUBWOD_Q_D */ LSX128, LSX128, LSX128, /* VSUBWOD_Q_DU */ LSX128, LSX128, LSX128, /* VSUBWOD_W_H */ LSX128, LSX128, LSX128, /* VSUBWOD_W_HU */ LSX128, LSX128, LSX128, /* VSUB_B */ LSX128, LSX128, LSX128, /* VSUB_D */ LSX128, LSX128, LSX128, /* VSUB_H */ LSX128, LSX128, LSX128, /* VSUB_Q */ LSX128, LSX128, LSX128, /* VSUB_W */ LSX128, LSX128, LSX128, /* VXORI_B */ LSX128, LSX128, uimm8, /* VXOR_V */ LSX128, LSX128, LSX128, /* X86ADC_B */ GPR, GPR, /* X86ADC_D */ GPR, GPR, /* X86ADC_H */ GPR, GPR, /* X86ADC_W */ GPR, GPR, /* X86ADD_B */ GPR, GPR, /* X86ADD_D */ GPR, GPR, /* X86ADD_DU */ GPR, GPR, /* X86ADD_H */ GPR, GPR, /* X86ADD_W */ GPR, GPR, /* X86ADD_WU */ GPR, GPR, /* X86AND_B */ GPR, GPR, /* X86AND_D */ GPR, GPR, /* X86AND_H */ GPR, GPR, /* X86AND_W */ GPR, GPR, /* X86CLRTM */ /* X86DECTOP */ /* X86DEC_B */ GPR, /* X86DEC_D */ GPR, /* X86DEC_H */ GPR, /* X86DEC_W */ GPR, /* X86INCTOP */ /* X86INC_B */ GPR, /* X86INC_D */ GPR, /* X86INC_H */ GPR, /* X86INC_W */ GPR, /* X86MFFLAG */ GPR, uimm8, /* X86MFTOP */ GPR, /* X86MTFLAG */ GPR, uimm8, /* X86MTTOP */ uimm3, /* X86MUL_B */ GPR, GPR, /* X86MUL_BU */ GPR, GPR, /* X86MUL_D */ GPR, GPR, /* X86MUL_DU */ GPR, GPR, /* X86MUL_H */ GPR, GPR, /* X86MUL_HU */ GPR, GPR, /* X86MUL_W */ GPR, GPR, /* X86MUL_WU */ GPR, GPR, /* X86OR_B */ GPR, GPR, /* X86OR_D */ GPR, GPR, /* X86OR_H */ GPR, GPR, /* X86OR_W */ GPR, GPR, /* X86RCLI_B */ GPR, uimm3, /* X86RCLI_D */ GPR, uimm6, /* X86RCLI_H */ GPR, uimm4, /* X86RCLI_W */ GPR, uimm5, /* X86RCL_B */ GPR, GPR, /* X86RCL_D */ GPR, GPR, /* X86RCL_H */ GPR, GPR, /* X86RCL_W */ GPR, GPR, /* X86RCRI_B */ GPR, uimm3, /* X86RCRI_D */ GPR, uimm6, /* X86RCRI_H */ GPR, uimm4, /* X86RCRI_W */ GPR, uimm5, /* X86RCR_B */ GPR, GPR, /* X86RCR_D */ GPR, GPR, /* X86RCR_H */ GPR, GPR, /* X86RCR_W */ GPR, GPR, /* X86ROTLI_B */ GPR, uimm3, /* X86ROTLI_D */ GPR, uimm6, /* X86ROTLI_H */ GPR, uimm4, /* X86ROTLI_W */ GPR, uimm5, /* X86ROTL_B */ GPR, GPR, /* X86ROTL_D */ GPR, GPR, /* X86ROTL_H */ GPR, GPR, /* X86ROTL_W */ GPR, GPR, /* X86ROTRI_B */ GPR, uimm3, /* X86ROTRI_D */ GPR, uimm6, /* X86ROTRI_H */ GPR, uimm4, /* X86ROTRI_W */ GPR, uimm5, /* X86ROTR_B */ GPR, GPR, /* X86ROTR_D */ GPR, GPR, /* X86ROTR_H */ GPR, GPR, /* X86ROTR_W */ GPR, GPR, /* X86SBC_B */ GPR, GPR, /* X86SBC_D */ GPR, GPR, /* X86SBC_H */ GPR, GPR, /* X86SBC_W */ GPR, GPR, /* X86SETTAG */ GPR, uimm5, uimm8, /* X86SETTM */ /* X86SLLI_B */ GPR, uimm3, /* X86SLLI_D */ GPR, uimm6, /* X86SLLI_H */ GPR, uimm4, /* X86SLLI_W */ GPR, uimm5, /* X86SLL_B */ GPR, GPR, /* X86SLL_D */ GPR, GPR, /* X86SLL_H */ GPR, GPR, /* X86SLL_W */ GPR, GPR, /* X86SRAI_B */ GPR, uimm3, /* X86SRAI_D */ GPR, uimm6, /* X86SRAI_H */ GPR, uimm4, /* X86SRAI_W */ GPR, uimm5, /* X86SRA_B */ GPR, GPR, /* X86SRA_D */ GPR, GPR, /* X86SRA_H */ GPR, GPR, /* X86SRA_W */ GPR, GPR, /* X86SRLI_B */ GPR, uimm3, /* X86SRLI_D */ GPR, uimm6, /* X86SRLI_H */ GPR, uimm4, /* X86SRLI_W */ GPR, uimm5, /* X86SRL_B */ GPR, GPR, /* X86SRL_D */ GPR, GPR, /* X86SRL_H */ GPR, GPR, /* X86SRL_W */ GPR, GPR, /* X86SUB_B */ GPR, GPR, /* X86SUB_D */ GPR, GPR, /* X86SUB_DU */ GPR, GPR, /* X86SUB_H */ GPR, GPR, /* X86SUB_W */ GPR, GPR, /* X86SUB_WU */ GPR, GPR, /* X86XOR_B */ GPR, GPR, /* X86XOR_D */ GPR, GPR, /* X86XOR_H */ GPR, GPR, /* X86XOR_W */ GPR, GPR, /* XOR */ GPR, GPR, GPR, /* XORI */ GPR, GPR, uimm12, /* XVABSD_B */ LASX256, LASX256, LASX256, /* XVABSD_BU */ LASX256, LASX256, LASX256, /* XVABSD_D */ LASX256, LASX256, LASX256, /* XVABSD_DU */ LASX256, LASX256, LASX256, /* XVABSD_H */ LASX256, LASX256, LASX256, /* XVABSD_HU */ LASX256, LASX256, LASX256, /* XVABSD_W */ LASX256, LASX256, LASX256, /* XVABSD_WU */ LASX256, LASX256, LASX256, /* XVADDA_B */ LASX256, LASX256, LASX256, /* XVADDA_D */ LASX256, LASX256, LASX256, /* XVADDA_H */ LASX256, LASX256, LASX256, /* XVADDA_W */ LASX256, LASX256, LASX256, /* XVADDI_BU */ LASX256, LASX256, uimm5, /* XVADDI_DU */ LASX256, LASX256, uimm5, /* XVADDI_HU */ LASX256, LASX256, uimm5, /* XVADDI_WU */ LASX256, LASX256, uimm5, /* XVADDWEV_D_W */ LASX256, LASX256, LASX256, /* XVADDWEV_D_WU */ LASX256, LASX256, LASX256, /* XVADDWEV_D_WU_W */ LASX256, LASX256, LASX256, /* XVADDWEV_H_B */ LASX256, LASX256, LASX256, /* XVADDWEV_H_BU */ LASX256, LASX256, LASX256, /* XVADDWEV_H_BU_B */ LASX256, LASX256, LASX256, /* XVADDWEV_Q_D */ LASX256, LASX256, LASX256, /* XVADDWEV_Q_DU */ LASX256, LASX256, LASX256, /* XVADDWEV_Q_DU_D */ LASX256, LASX256, LASX256, /* XVADDWEV_W_H */ LASX256, LASX256, LASX256, /* XVADDWEV_W_HU */ LASX256, LASX256, LASX256, /* XVADDWEV_W_HU_H */ LASX256, LASX256, LASX256, /* XVADDWOD_D_W */ LASX256, LASX256, LASX256, /* XVADDWOD_D_WU */ LASX256, LASX256, LASX256, /* XVADDWOD_D_WU_W */ LASX256, LASX256, LASX256, /* XVADDWOD_H_B */ LASX256, LASX256, LASX256, /* XVADDWOD_H_BU */ LASX256, LASX256, LASX256, /* XVADDWOD_H_BU_B */ LASX256, LASX256, LASX256, /* XVADDWOD_Q_D */ LASX256, LASX256, LASX256, /* XVADDWOD_Q_DU */ LASX256, LASX256, LASX256, /* XVADDWOD_Q_DU_D */ LASX256, LASX256, LASX256, /* XVADDWOD_W_H */ LASX256, LASX256, LASX256, /* XVADDWOD_W_HU */ LASX256, LASX256, LASX256, /* XVADDWOD_W_HU_H */ LASX256, LASX256, LASX256, /* XVADD_B */ LASX256, LASX256, LASX256, /* XVADD_D */ LASX256, LASX256, LASX256, /* XVADD_H */ LASX256, LASX256, LASX256, /* XVADD_Q */ LASX256, LASX256, LASX256, /* XVADD_W */ LASX256, LASX256, LASX256, /* XVANDI_B */ LASX256, LASX256, uimm8, /* XVANDN_V */ LASX256, LASX256, LASX256, /* XVAND_V */ LASX256, LASX256, LASX256, /* XVAVGR_B */ LASX256, LASX256, LASX256, /* XVAVGR_BU */ LASX256, LASX256, LASX256, /* XVAVGR_D */ LASX256, LASX256, LASX256, /* XVAVGR_DU */ LASX256, LASX256, LASX256, /* XVAVGR_H */ LASX256, LASX256, LASX256, /* XVAVGR_HU */ LASX256, LASX256, LASX256, /* XVAVGR_W */ LASX256, LASX256, LASX256, /* XVAVGR_WU */ LASX256, LASX256, LASX256, /* XVAVG_B */ LASX256, LASX256, LASX256, /* XVAVG_BU */ LASX256, LASX256, LASX256, /* XVAVG_D */ LASX256, LASX256, LASX256, /* XVAVG_DU */ LASX256, LASX256, LASX256, /* XVAVG_H */ LASX256, LASX256, LASX256, /* XVAVG_HU */ LASX256, LASX256, LASX256, /* XVAVG_W */ LASX256, LASX256, LASX256, /* XVAVG_WU */ LASX256, LASX256, LASX256, /* XVBITCLRI_B */ LASX256, LASX256, uimm3, /* XVBITCLRI_D */ LASX256, LASX256, uimm6, /* XVBITCLRI_H */ LASX256, LASX256, uimm4, /* XVBITCLRI_W */ LASX256, LASX256, uimm5, /* XVBITCLR_B */ LASX256, LASX256, LASX256, /* XVBITCLR_D */ LASX256, LASX256, LASX256, /* XVBITCLR_H */ LASX256, LASX256, LASX256, /* XVBITCLR_W */ LASX256, LASX256, LASX256, /* XVBITREVI_B */ LASX256, LASX256, uimm3, /* XVBITREVI_D */ LASX256, LASX256, uimm6, /* XVBITREVI_H */ LASX256, LASX256, uimm4, /* XVBITREVI_W */ LASX256, LASX256, uimm5, /* XVBITREV_B */ LASX256, LASX256, LASX256, /* XVBITREV_D */ LASX256, LASX256, LASX256, /* XVBITREV_H */ LASX256, LASX256, LASX256, /* XVBITREV_W */ LASX256, LASX256, LASX256, /* XVBITSELI_B */ LASX256, LASX256, LASX256, uimm8, /* XVBITSEL_V */ LASX256, LASX256, LASX256, LASX256, /* XVBITSETI_B */ LASX256, LASX256, uimm3, /* XVBITSETI_D */ LASX256, LASX256, uimm6, /* XVBITSETI_H */ LASX256, LASX256, uimm4, /* XVBITSETI_W */ LASX256, LASX256, uimm5, /* XVBITSET_B */ LASX256, LASX256, LASX256, /* XVBITSET_D */ LASX256, LASX256, LASX256, /* XVBITSET_H */ LASX256, LASX256, LASX256, /* XVBITSET_W */ LASX256, LASX256, LASX256, /* XVBSLL_V */ LASX256, LASX256, uimm5, /* XVBSRL_V */ LASX256, LASX256, uimm5, /* XVCLO_B */ LASX256, LASX256, /* XVCLO_D */ LASX256, LASX256, /* XVCLO_H */ LASX256, LASX256, /* XVCLO_W */ LASX256, LASX256, /* XVCLZ_B */ LASX256, LASX256, /* XVCLZ_D */ LASX256, LASX256, /* XVCLZ_H */ LASX256, LASX256, /* XVCLZ_W */ LASX256, LASX256, /* XVDIV_B */ LASX256, LASX256, LASX256, /* XVDIV_BU */ LASX256, LASX256, LASX256, /* XVDIV_D */ LASX256, LASX256, LASX256, /* XVDIV_DU */ LASX256, LASX256, LASX256, /* XVDIV_H */ LASX256, LASX256, LASX256, /* XVDIV_HU */ LASX256, LASX256, LASX256, /* XVDIV_W */ LASX256, LASX256, LASX256, /* XVDIV_WU */ LASX256, LASX256, LASX256, /* XVEXTH_DU_WU */ LASX256, LASX256, /* XVEXTH_D_W */ LASX256, LASX256, /* XVEXTH_HU_BU */ LASX256, LASX256, /* XVEXTH_H_B */ LASX256, LASX256, /* XVEXTH_QU_DU */ LASX256, LASX256, /* XVEXTH_Q_D */ LASX256, LASX256, /* XVEXTH_WU_HU */ LASX256, LASX256, /* XVEXTH_W_H */ LASX256, LASX256, /* XVEXTL_QU_DU */ LASX256, LASX256, /* XVEXTL_Q_D */ LASX256, LASX256, /* XVEXTRINS_B */ LASX256, LASX256, LASX256, uimm8, /* XVEXTRINS_D */ LASX256, LASX256, LASX256, uimm8, /* XVEXTRINS_H */ LASX256, LASX256, LASX256, uimm8, /* XVEXTRINS_W */ LASX256, LASX256, LASX256, uimm8, /* XVFADD_D */ LASX256, LASX256, LASX256, /* XVFADD_S */ LASX256, LASX256, LASX256, /* XVFCLASS_D */ LASX256, LASX256, /* XVFCLASS_S */ LASX256, LASX256, /* XVFCMP_CAF_D */ LASX256, LASX256, LASX256, /* XVFCMP_CAF_S */ LASX256, LASX256, LASX256, /* XVFCMP_CEQ_D */ LASX256, LASX256, LASX256, /* XVFCMP_CEQ_S */ LASX256, LASX256, LASX256, /* XVFCMP_CLE_D */ LASX256, LASX256, LASX256, /* XVFCMP_CLE_S */ LASX256, LASX256, LASX256, /* XVFCMP_CLT_D */ LASX256, LASX256, LASX256, /* XVFCMP_CLT_S */ LASX256, LASX256, LASX256, /* XVFCMP_CNE_D */ LASX256, LASX256, LASX256, /* XVFCMP_CNE_S */ LASX256, LASX256, LASX256, /* XVFCMP_COR_D */ LASX256, LASX256, LASX256, /* XVFCMP_COR_S */ LASX256, LASX256, LASX256, /* XVFCMP_CUEQ_D */ LASX256, LASX256, LASX256, /* XVFCMP_CUEQ_S */ LASX256, LASX256, LASX256, /* XVFCMP_CULE_D */ LASX256, LASX256, LASX256, /* XVFCMP_CULE_S */ LASX256, LASX256, LASX256, /* XVFCMP_CULT_D */ LASX256, LASX256, LASX256, /* XVFCMP_CULT_S */ LASX256, LASX256, LASX256, /* XVFCMP_CUNE_D */ LASX256, LASX256, LASX256, /* XVFCMP_CUNE_S */ LASX256, LASX256, LASX256, /* XVFCMP_CUN_D */ LASX256, LASX256, LASX256, /* XVFCMP_CUN_S */ LASX256, LASX256, LASX256, /* XVFCMP_SAF_D */ LASX256, LASX256, LASX256, /* XVFCMP_SAF_S */ LASX256, LASX256, LASX256, /* XVFCMP_SEQ_D */ LASX256, LASX256, LASX256, /* XVFCMP_SEQ_S */ LASX256, LASX256, LASX256, /* XVFCMP_SLE_D */ LASX256, LASX256, LASX256, /* XVFCMP_SLE_S */ LASX256, LASX256, LASX256, /* XVFCMP_SLT_D */ LASX256, LASX256, LASX256, /* XVFCMP_SLT_S */ LASX256, LASX256, LASX256, /* XVFCMP_SNE_D */ LASX256, LASX256, LASX256, /* XVFCMP_SNE_S */ LASX256, LASX256, LASX256, /* XVFCMP_SOR_D */ LASX256, LASX256, LASX256, /* XVFCMP_SOR_S */ LASX256, LASX256, LASX256, /* XVFCMP_SUEQ_D */ LASX256, LASX256, LASX256, /* XVFCMP_SUEQ_S */ LASX256, LASX256, LASX256, /* XVFCMP_SULE_D */ LASX256, LASX256, LASX256, /* XVFCMP_SULE_S */ LASX256, LASX256, LASX256, /* XVFCMP_SULT_D */ LASX256, LASX256, LASX256, /* XVFCMP_SULT_S */ LASX256, LASX256, LASX256, /* XVFCMP_SUNE_D */ LASX256, LASX256, LASX256, /* XVFCMP_SUNE_S */ LASX256, LASX256, LASX256, /* XVFCMP_SUN_D */ LASX256, LASX256, LASX256, /* XVFCMP_SUN_S */ LASX256, LASX256, LASX256, /* XVFCVTH_D_S */ LASX256, LASX256, /* XVFCVTH_S_H */ LASX256, LASX256, /* XVFCVTL_D_S */ LASX256, LASX256, /* XVFCVTL_S_H */ LASX256, LASX256, /* XVFCVT_H_S */ LASX256, LASX256, LASX256, /* XVFCVT_S_D */ LASX256, LASX256, LASX256, /* XVFDIV_D */ LASX256, LASX256, LASX256, /* XVFDIV_S */ LASX256, LASX256, LASX256, /* XVFFINTH_D_W */ LASX256, LASX256, /* XVFFINTL_D_W */ LASX256, LASX256, /* XVFFINT_D_L */ LASX256, LASX256, /* XVFFINT_D_LU */ LASX256, LASX256, /* XVFFINT_S_L */ LASX256, LASX256, LASX256, /* XVFFINT_S_W */ LASX256, LASX256, /* XVFFINT_S_WU */ LASX256, LASX256, /* XVFLOGB_D */ LASX256, LASX256, /* XVFLOGB_S */ LASX256, LASX256, /* XVFMADD_D */ LASX256, LASX256, LASX256, LASX256, /* XVFMADD_S */ LASX256, LASX256, LASX256, LASX256, /* XVFMAXA_D */ LASX256, LASX256, LASX256, /* XVFMAXA_S */ LASX256, LASX256, LASX256, /* XVFMAX_D */ LASX256, LASX256, LASX256, /* XVFMAX_S */ LASX256, LASX256, LASX256, /* XVFMINA_D */ LASX256, LASX256, LASX256, /* XVFMINA_S */ LASX256, LASX256, LASX256, /* XVFMIN_D */ LASX256, LASX256, LASX256, /* XVFMIN_S */ LASX256, LASX256, LASX256, /* XVFMSUB_D */ LASX256, LASX256, LASX256, LASX256, /* XVFMSUB_S */ LASX256, LASX256, LASX256, LASX256, /* XVFMUL_D */ LASX256, LASX256, LASX256, /* XVFMUL_S */ LASX256, LASX256, LASX256, /* XVFNMADD_D */ LASX256, LASX256, LASX256, LASX256, /* XVFNMADD_S */ LASX256, LASX256, LASX256, LASX256, /* XVFNMSUB_D */ LASX256, LASX256, LASX256, LASX256, /* XVFNMSUB_S */ LASX256, LASX256, LASX256, LASX256, /* XVFRECIPE_D */ LASX256, LASX256, /* XVFRECIPE_S */ LASX256, LASX256, /* XVFRECIP_D */ LASX256, LASX256, /* XVFRECIP_S */ LASX256, LASX256, /* XVFRINTRM_D */ LASX256, LASX256, /* XVFRINTRM_S */ LASX256, LASX256, /* XVFRINTRNE_D */ LASX256, LASX256, /* XVFRINTRNE_S */ LASX256, LASX256, /* XVFRINTRP_D */ LASX256, LASX256, /* XVFRINTRP_S */ LASX256, LASX256, /* XVFRINTRZ_D */ LASX256, LASX256, /* XVFRINTRZ_S */ LASX256, LASX256, /* XVFRINT_D */ LASX256, LASX256, /* XVFRINT_S */ LASX256, LASX256, /* XVFRSQRTE_D */ LASX256, LASX256, /* XVFRSQRTE_S */ LASX256, LASX256, /* XVFRSQRT_D */ LASX256, LASX256, /* XVFRSQRT_S */ LASX256, LASX256, /* XVFRSTPI_B */ LASX256, LASX256, LASX256, uimm5, /* XVFRSTPI_H */ LASX256, LASX256, LASX256, uimm5, /* XVFRSTP_B */ LASX256, LASX256, LASX256, LASX256, /* XVFRSTP_H */ LASX256, LASX256, LASX256, LASX256, /* XVFSQRT_D */ LASX256, LASX256, /* XVFSQRT_S */ LASX256, LASX256, /* XVFSUB_D */ LASX256, LASX256, LASX256, /* XVFSUB_S */ LASX256, LASX256, LASX256, /* XVFTINTH_L_S */ LASX256, LASX256, /* XVFTINTL_L_S */ LASX256, LASX256, /* XVFTINTRMH_L_S */ LASX256, LASX256, /* XVFTINTRML_L_S */ LASX256, LASX256, /* XVFTINTRM_L_D */ LASX256, LASX256, /* XVFTINTRM_W_D */ LASX256, LASX256, LASX256, /* XVFTINTRM_W_S */ LASX256, LASX256, /* XVFTINTRNEH_L_S */ LASX256, LASX256, /* XVFTINTRNEL_L_S */ LASX256, LASX256, /* XVFTINTRNE_L_D */ LASX256, LASX256, /* XVFTINTRNE_W_D */ LASX256, LASX256, LASX256, /* XVFTINTRNE_W_S */ LASX256, LASX256, /* XVFTINTRPH_L_S */ LASX256, LASX256, /* XVFTINTRPL_L_S */ LASX256, LASX256, /* XVFTINTRP_L_D */ LASX256, LASX256, /* XVFTINTRP_W_D */ LASX256, LASX256, LASX256, /* XVFTINTRP_W_S */ LASX256, LASX256, /* XVFTINTRZH_L_S */ LASX256, LASX256, /* XVFTINTRZL_L_S */ LASX256, LASX256, /* XVFTINTRZ_LU_D */ LASX256, LASX256, /* XVFTINTRZ_L_D */ LASX256, LASX256, /* XVFTINTRZ_WU_S */ LASX256, LASX256, /* XVFTINTRZ_W_D */ LASX256, LASX256, LASX256, /* XVFTINTRZ_W_S */ LASX256, LASX256, /* XVFTINT_LU_D */ LASX256, LASX256, /* XVFTINT_L_D */ LASX256, LASX256, /* XVFTINT_WU_S */ LASX256, LASX256, /* XVFTINT_W_D */ LASX256, LASX256, LASX256, /* XVFTINT_W_S */ LASX256, LASX256, /* XVHADDW_DU_WU */ LASX256, LASX256, LASX256, /* XVHADDW_D_W */ LASX256, LASX256, LASX256, /* XVHADDW_HU_BU */ LASX256, LASX256, LASX256, /* XVHADDW_H_B */ LASX256, LASX256, LASX256, /* XVHADDW_QU_DU */ LASX256, LASX256, LASX256, /* XVHADDW_Q_D */ LASX256, LASX256, LASX256, /* XVHADDW_WU_HU */ LASX256, LASX256, LASX256, /* XVHADDW_W_H */ LASX256, LASX256, LASX256, /* XVHSELI_D */ LASX256, LASX256, uimm5, /* XVHSUBW_DU_WU */ LASX256, LASX256, LASX256, /* XVHSUBW_D_W */ LASX256, LASX256, LASX256, /* XVHSUBW_HU_BU */ LASX256, LASX256, LASX256, /* XVHSUBW_H_B */ LASX256, LASX256, LASX256, /* XVHSUBW_QU_DU */ LASX256, LASX256, LASX256, /* XVHSUBW_Q_D */ LASX256, LASX256, LASX256, /* XVHSUBW_WU_HU */ LASX256, LASX256, LASX256, /* XVHSUBW_W_H */ LASX256, LASX256, LASX256, /* XVILVH_B */ LASX256, LASX256, LASX256, /* XVILVH_D */ LASX256, LASX256, LASX256, /* XVILVH_H */ LASX256, LASX256, LASX256, /* XVILVH_W */ LASX256, LASX256, LASX256, /* XVILVL_B */ LASX256, LASX256, LASX256, /* XVILVL_D */ LASX256, LASX256, LASX256, /* XVILVL_H */ LASX256, LASX256, LASX256, /* XVILVL_W */ LASX256, LASX256, LASX256, /* XVINSGR2VR_D */ LASX256, LASX256, GPR, uimm2, /* XVINSGR2VR_W */ LASX256, LASX256, GPR, uimm3, /* XVINSVE0_D */ LASX256, LASX256, LASX256, uimm2, /* XVINSVE0_W */ LASX256, LASX256, LASX256, uimm3, /* XVLD */ LASX256, GPR, simm12, /* XVLDI */ LASX256, simm13, /* XVLDREPL_B */ LASX256, GPR, simm12, /* XVLDREPL_D */ LASX256, GPR, simm9_lsl3, /* XVLDREPL_H */ LASX256, GPR, simm11_lsl1, /* XVLDREPL_W */ LASX256, GPR, simm10_lsl2, /* XVLDX */ LASX256, GPR, GPR, /* XVMADDWEV_D_W */ LASX256, LASX256, LASX256, LASX256, /* XVMADDWEV_D_WU */ LASX256, LASX256, LASX256, LASX256, /* XVMADDWEV_D_WU_W */ LASX256, LASX256, LASX256, LASX256, /* XVMADDWEV_H_B */ LASX256, LASX256, LASX256, LASX256, /* XVMADDWEV_H_BU */ LASX256, LASX256, LASX256, LASX256, /* XVMADDWEV_H_BU_B */ LASX256, LASX256, LASX256, LASX256, /* XVMADDWEV_Q_D */ LASX256, LASX256, LASX256, LASX256, /* XVMADDWEV_Q_DU */ LASX256, LASX256, LASX256, LASX256, /* XVMADDWEV_Q_DU_D */ LASX256, LASX256, LASX256, LASX256, /* XVMADDWEV_W_H */ LASX256, LASX256, LASX256, LASX256, /* XVMADDWEV_W_HU */ LASX256, LASX256, LASX256, LASX256, /* XVMADDWEV_W_HU_H */ LASX256, LASX256, LASX256, LASX256, /* XVMADDWOD_D_W */ LASX256, LASX256, LASX256, LASX256, /* XVMADDWOD_D_WU */ LASX256, LASX256, LASX256, LASX256, /* XVMADDWOD_D_WU_W */ LASX256, LASX256, LASX256, LASX256, /* XVMADDWOD_H_B */ LASX256, LASX256, LASX256, LASX256, /* XVMADDWOD_H_BU */ LASX256, LASX256, LASX256, LASX256, /* XVMADDWOD_H_BU_B */ LASX256, LASX256, LASX256, LASX256, /* XVMADDWOD_Q_D */ LASX256, LASX256, LASX256, LASX256, /* XVMADDWOD_Q_DU */ LASX256, LASX256, LASX256, LASX256, /* XVMADDWOD_Q_DU_D */ LASX256, LASX256, LASX256, LASX256, /* XVMADDWOD_W_H */ LASX256, LASX256, LASX256, LASX256, /* XVMADDWOD_W_HU */ LASX256, LASX256, LASX256, LASX256, /* XVMADDWOD_W_HU_H */ LASX256, LASX256, LASX256, LASX256, /* XVMADD_B */ LASX256, LASX256, LASX256, LASX256, /* XVMADD_D */ LASX256, LASX256, LASX256, LASX256, /* XVMADD_H */ LASX256, LASX256, LASX256, LASX256, /* XVMADD_W */ LASX256, LASX256, LASX256, LASX256, /* XVMAXI_B */ LASX256, LASX256, simm5, /* XVMAXI_BU */ LASX256, LASX256, uimm5, /* XVMAXI_D */ LASX256, LASX256, simm5, /* XVMAXI_DU */ LASX256, LASX256, uimm5, /* XVMAXI_H */ LASX256, LASX256, simm5, /* XVMAXI_HU */ LASX256, LASX256, uimm5, /* XVMAXI_W */ LASX256, LASX256, simm5, /* XVMAXI_WU */ LASX256, LASX256, uimm5, /* XVMAX_B */ LASX256, LASX256, LASX256, /* XVMAX_BU */ LASX256, LASX256, LASX256, /* XVMAX_D */ LASX256, LASX256, LASX256, /* XVMAX_DU */ LASX256, LASX256, LASX256, /* XVMAX_H */ LASX256, LASX256, LASX256, /* XVMAX_HU */ LASX256, LASX256, LASX256, /* XVMAX_W */ LASX256, LASX256, LASX256, /* XVMAX_WU */ LASX256, LASX256, LASX256, /* XVMINI_B */ LASX256, LASX256, simm5, /* XVMINI_BU */ LASX256, LASX256, uimm5, /* XVMINI_D */ LASX256, LASX256, simm5, /* XVMINI_DU */ LASX256, LASX256, uimm5, /* XVMINI_H */ LASX256, LASX256, simm5, /* XVMINI_HU */ LASX256, LASX256, uimm5, /* XVMINI_W */ LASX256, LASX256, simm5, /* XVMINI_WU */ LASX256, LASX256, uimm5, /* XVMIN_B */ LASX256, LASX256, LASX256, /* XVMIN_BU */ LASX256, LASX256, LASX256, /* XVMIN_D */ LASX256, LASX256, LASX256, /* XVMIN_DU */ LASX256, LASX256, LASX256, /* XVMIN_H */ LASX256, LASX256, LASX256, /* XVMIN_HU */ LASX256, LASX256, LASX256, /* XVMIN_W */ LASX256, LASX256, LASX256, /* XVMIN_WU */ LASX256, LASX256, LASX256, /* XVMOD_B */ LASX256, LASX256, LASX256, /* XVMOD_BU */ LASX256, LASX256, LASX256, /* XVMOD_D */ LASX256, LASX256, LASX256, /* XVMOD_DU */ LASX256, LASX256, LASX256, /* XVMOD_H */ LASX256, LASX256, LASX256, /* XVMOD_HU */ LASX256, LASX256, LASX256, /* XVMOD_W */ LASX256, LASX256, LASX256, /* XVMOD_WU */ LASX256, LASX256, LASX256, /* XVMSKGEZ_B */ LASX256, LASX256, /* XVMSKLTZ_B */ LASX256, LASX256, /* XVMSKLTZ_D */ LASX256, LASX256, /* XVMSKLTZ_H */ LASX256, LASX256, /* XVMSKLTZ_W */ LASX256, LASX256, /* XVMSKNZ_B */ LASX256, LASX256, /* XVMSUB_B */ LASX256, LASX256, LASX256, LASX256, /* XVMSUB_D */ LASX256, LASX256, LASX256, LASX256, /* XVMSUB_H */ LASX256, LASX256, LASX256, LASX256, /* XVMSUB_W */ LASX256, LASX256, LASX256, LASX256, /* XVMUH_B */ LASX256, LASX256, LASX256, /* XVMUH_BU */ LASX256, LASX256, LASX256, /* XVMUH_D */ LASX256, LASX256, LASX256, /* XVMUH_DU */ LASX256, LASX256, LASX256, /* XVMUH_H */ LASX256, LASX256, LASX256, /* XVMUH_HU */ LASX256, LASX256, LASX256, /* XVMUH_W */ LASX256, LASX256, LASX256, /* XVMUH_WU */ LASX256, LASX256, LASX256, /* XVMULWEV_D_W */ LASX256, LASX256, LASX256, /* XVMULWEV_D_WU */ LASX256, LASX256, LASX256, /* XVMULWEV_D_WU_W */ LASX256, LASX256, LASX256, /* XVMULWEV_H_B */ LASX256, LASX256, LASX256, /* XVMULWEV_H_BU */ LASX256, LASX256, LASX256, /* XVMULWEV_H_BU_B */ LASX256, LASX256, LASX256, /* XVMULWEV_Q_D */ LASX256, LASX256, LASX256, /* XVMULWEV_Q_DU */ LASX256, LASX256, LASX256, /* XVMULWEV_Q_DU_D */ LASX256, LASX256, LASX256, /* XVMULWEV_W_H */ LASX256, LASX256, LASX256, /* XVMULWEV_W_HU */ LASX256, LASX256, LASX256, /* XVMULWEV_W_HU_H */ LASX256, LASX256, LASX256, /* XVMULWOD_D_W */ LASX256, LASX256, LASX256, /* XVMULWOD_D_WU */ LASX256, LASX256, LASX256, /* XVMULWOD_D_WU_W */ LASX256, LASX256, LASX256, /* XVMULWOD_H_B */ LASX256, LASX256, LASX256, /* XVMULWOD_H_BU */ LASX256, LASX256, LASX256, /* XVMULWOD_H_BU_B */ LASX256, LASX256, LASX256, /* XVMULWOD_Q_D */ LASX256, LASX256, LASX256, /* XVMULWOD_Q_DU */ LASX256, LASX256, LASX256, /* XVMULWOD_Q_DU_D */ LASX256, LASX256, LASX256, /* XVMULWOD_W_H */ LASX256, LASX256, LASX256, /* XVMULWOD_W_HU */ LASX256, LASX256, LASX256, /* XVMULWOD_W_HU_H */ LASX256, LASX256, LASX256, /* XVMUL_B */ LASX256, LASX256, LASX256, /* XVMUL_D */ LASX256, LASX256, LASX256, /* XVMUL_H */ LASX256, LASX256, LASX256, /* XVMUL_W */ LASX256, LASX256, LASX256, /* XVNEG_B */ LASX256, LASX256, /* XVNEG_D */ LASX256, LASX256, /* XVNEG_H */ LASX256, LASX256, /* XVNEG_W */ LASX256, LASX256, /* XVNORI_B */ LASX256, LASX256, uimm8, /* XVNOR_V */ LASX256, LASX256, LASX256, /* XVORI_B */ LASX256, LASX256, uimm8, /* XVORN_V */ LASX256, LASX256, LASX256, /* XVOR_V */ LASX256, LASX256, LASX256, /* XVPACKEV_B */ LASX256, LASX256, LASX256, /* XVPACKEV_D */ LASX256, LASX256, LASX256, /* XVPACKEV_H */ LASX256, LASX256, LASX256, /* XVPACKEV_W */ LASX256, LASX256, LASX256, /* XVPACKOD_B */ LASX256, LASX256, LASX256, /* XVPACKOD_D */ LASX256, LASX256, LASX256, /* XVPACKOD_H */ LASX256, LASX256, LASX256, /* XVPACKOD_W */ LASX256, LASX256, LASX256, /* XVPCNT_B */ LASX256, LASX256, /* XVPCNT_D */ LASX256, LASX256, /* XVPCNT_H */ LASX256, LASX256, /* XVPCNT_W */ LASX256, LASX256, /* XVPERMI_D */ LASX256, LASX256, uimm8, /* XVPERMI_Q */ LASX256, LASX256, LASX256, uimm8, /* XVPERMI_W */ LASX256, LASX256, LASX256, uimm8, /* XVPERM_W */ LASX256, LASX256, LASX256, /* XVPICKEV_B */ LASX256, LASX256, LASX256, /* XVPICKEV_D */ LASX256, LASX256, LASX256, /* XVPICKEV_H */ LASX256, LASX256, LASX256, /* XVPICKEV_W */ LASX256, LASX256, LASX256, /* XVPICKOD_B */ LASX256, LASX256, LASX256, /* XVPICKOD_D */ LASX256, LASX256, LASX256, /* XVPICKOD_H */ LASX256, LASX256, LASX256, /* XVPICKOD_W */ LASX256, LASX256, LASX256, /* XVPICKVE2GR_D */ GPR, LASX256, uimm2, /* XVPICKVE2GR_DU */ GPR, LASX256, uimm2, /* XVPICKVE2GR_W */ GPR, LASX256, uimm3, /* XVPICKVE2GR_WU */ GPR, LASX256, uimm3, /* XVPICKVE_D */ LASX256, LASX256, uimm2, /* XVPICKVE_W */ LASX256, LASX256, uimm3, /* XVREPL128VEI_B */ LASX256, LASX256, uimm4, /* XVREPL128VEI_D */ LASX256, LASX256, uimm1, /* XVREPL128VEI_H */ LASX256, LASX256, uimm3, /* XVREPL128VEI_W */ LASX256, LASX256, uimm2, /* XVREPLGR2VR_B */ LASX256, GPR, /* XVREPLGR2VR_D */ LASX256, GPR, /* XVREPLGR2VR_H */ LASX256, GPR, /* XVREPLGR2VR_W */ LASX256, GPR, /* XVREPLVE0_B */ LASX256, LASX256, /* XVREPLVE0_D */ LASX256, LASX256, /* XVREPLVE0_H */ LASX256, LASX256, /* XVREPLVE0_Q */ LASX256, LASX256, /* XVREPLVE0_W */ LASX256, LASX256, /* XVREPLVE_B */ LASX256, LASX256, GPR, /* XVREPLVE_D */ LASX256, LASX256, GPR, /* XVREPLVE_H */ LASX256, LASX256, GPR, /* XVREPLVE_W */ LASX256, LASX256, GPR, /* XVROTRI_B */ LASX256, LASX256, uimm3, /* XVROTRI_D */ LASX256, LASX256, uimm6, /* XVROTRI_H */ LASX256, LASX256, uimm4, /* XVROTRI_W */ LASX256, LASX256, uimm5, /* XVROTR_B */ LASX256, LASX256, LASX256, /* XVROTR_D */ LASX256, LASX256, LASX256, /* XVROTR_H */ LASX256, LASX256, LASX256, /* XVROTR_W */ LASX256, LASX256, LASX256, /* XVSADD_B */ LASX256, LASX256, LASX256, /* XVSADD_BU */ LASX256, LASX256, LASX256, /* XVSADD_D */ LASX256, LASX256, LASX256, /* XVSADD_DU */ LASX256, LASX256, LASX256, /* XVSADD_H */ LASX256, LASX256, LASX256, /* XVSADD_HU */ LASX256, LASX256, LASX256, /* XVSADD_W */ LASX256, LASX256, LASX256, /* XVSADD_WU */ LASX256, LASX256, LASX256, /* XVSAT_B */ LASX256, LASX256, uimm3, /* XVSAT_BU */ LASX256, LASX256, uimm3, /* XVSAT_D */ LASX256, LASX256, uimm6, /* XVSAT_DU */ LASX256, LASX256, uimm6, /* XVSAT_H */ LASX256, LASX256, uimm4, /* XVSAT_HU */ LASX256, LASX256, uimm4, /* XVSAT_W */ LASX256, LASX256, uimm5, /* XVSAT_WU */ LASX256, LASX256, uimm5, /* XVSEQI_B */ LASX256, LASX256, simm5, /* XVSEQI_D */ LASX256, LASX256, simm5, /* XVSEQI_H */ LASX256, LASX256, simm5, /* XVSEQI_W */ LASX256, LASX256, simm5, /* XVSEQ_B */ LASX256, LASX256, LASX256, /* XVSEQ_D */ LASX256, LASX256, LASX256, /* XVSEQ_H */ LASX256, LASX256, LASX256, /* XVSEQ_W */ LASX256, LASX256, LASX256, /* XVSETALLNEZ_B */ CFR, LASX256, /* XVSETALLNEZ_D */ CFR, LASX256, /* XVSETALLNEZ_H */ CFR, LASX256, /* XVSETALLNEZ_W */ CFR, LASX256, /* XVSETANYEQZ_B */ CFR, LASX256, /* XVSETANYEQZ_D */ CFR, LASX256, /* XVSETANYEQZ_H */ CFR, LASX256, /* XVSETANYEQZ_W */ CFR, LASX256, /* XVSETEQZ_V */ CFR, LASX256, /* XVSETNEZ_V */ CFR, LASX256, /* XVSHUF4I_B */ LASX256, LASX256, uimm8, /* XVSHUF4I_D */ LASX256, LASX256, LASX256, uimm8, /* XVSHUF4I_H */ LASX256, LASX256, uimm8, /* XVSHUF4I_W */ LASX256, LASX256, uimm8, /* XVSHUF_B */ LASX256, LASX256, LASX256, LASX256, /* XVSHUF_D */ LASX256, LASX256, LASX256, LASX256, /* XVSHUF_H */ LASX256, LASX256, LASX256, LASX256, /* XVSHUF_W */ LASX256, LASX256, LASX256, LASX256, /* XVSIGNCOV_B */ LASX256, LASX256, LASX256, /* XVSIGNCOV_D */ LASX256, LASX256, LASX256, /* XVSIGNCOV_H */ LASX256, LASX256, LASX256, /* XVSIGNCOV_W */ LASX256, LASX256, LASX256, /* XVSLEI_B */ LASX256, LASX256, simm5, /* XVSLEI_BU */ LASX256, LASX256, uimm5, /* XVSLEI_D */ LASX256, LASX256, simm5, /* XVSLEI_DU */ LASX256, LASX256, uimm5, /* XVSLEI_H */ LASX256, LASX256, simm5, /* XVSLEI_HU */ LASX256, LASX256, uimm5, /* XVSLEI_W */ LASX256, LASX256, simm5, /* XVSLEI_WU */ LASX256, LASX256, uimm5, /* XVSLE_B */ LASX256, LASX256, LASX256, /* XVSLE_BU */ LASX256, LASX256, LASX256, /* XVSLE_D */ LASX256, LASX256, LASX256, /* XVSLE_DU */ LASX256, LASX256, LASX256, /* XVSLE_H */ LASX256, LASX256, LASX256, /* XVSLE_HU */ LASX256, LASX256, LASX256, /* XVSLE_W */ LASX256, LASX256, LASX256, /* XVSLE_WU */ LASX256, LASX256, LASX256, /* XVSLLI_B */ LASX256, LASX256, uimm3, /* XVSLLI_D */ LASX256, LASX256, uimm6, /* XVSLLI_H */ LASX256, LASX256, uimm4, /* XVSLLI_W */ LASX256, LASX256, uimm5, /* XVSLLWIL_DU_WU */ LASX256, LASX256, uimm5, /* XVSLLWIL_D_W */ LASX256, LASX256, uimm5, /* XVSLLWIL_HU_BU */ LASX256, LASX256, uimm3, /* XVSLLWIL_H_B */ LASX256, LASX256, uimm3, /* XVSLLWIL_WU_HU */ LASX256, LASX256, uimm4, /* XVSLLWIL_W_H */ LASX256, LASX256, uimm4, /* XVSLL_B */ LASX256, LASX256, LASX256, /* XVSLL_D */ LASX256, LASX256, LASX256, /* XVSLL_H */ LASX256, LASX256, LASX256, /* XVSLL_W */ LASX256, LASX256, LASX256, /* XVSLTI_B */ LASX256, LASX256, simm5, /* XVSLTI_BU */ LASX256, LASX256, uimm5, /* XVSLTI_D */ LASX256, LASX256, simm5, /* XVSLTI_DU */ LASX256, LASX256, uimm5, /* XVSLTI_H */ LASX256, LASX256, simm5, /* XVSLTI_HU */ LASX256, LASX256, uimm5, /* XVSLTI_W */ LASX256, LASX256, simm5, /* XVSLTI_WU */ LASX256, LASX256, uimm5, /* XVSLT_B */ LASX256, LASX256, LASX256, /* XVSLT_BU */ LASX256, LASX256, LASX256, /* XVSLT_D */ LASX256, LASX256, LASX256, /* XVSLT_DU */ LASX256, LASX256, LASX256, /* XVSLT_H */ LASX256, LASX256, LASX256, /* XVSLT_HU */ LASX256, LASX256, LASX256, /* XVSLT_W */ LASX256, LASX256, LASX256, /* XVSLT_WU */ LASX256, LASX256, LASX256, /* XVSRAI_B */ LASX256, LASX256, uimm3, /* XVSRAI_D */ LASX256, LASX256, uimm6, /* XVSRAI_H */ LASX256, LASX256, uimm4, /* XVSRAI_W */ LASX256, LASX256, uimm5, /* XVSRANI_B_H */ LASX256, LASX256, LASX256, uimm4, /* XVSRANI_D_Q */ LASX256, LASX256, LASX256, uimm7, /* XVSRANI_H_W */ LASX256, LASX256, LASX256, uimm5, /* XVSRANI_W_D */ LASX256, LASX256, LASX256, uimm6, /* XVSRAN_B_H */ LASX256, LASX256, LASX256, /* XVSRAN_H_W */ LASX256, LASX256, LASX256, /* XVSRAN_W_D */ LASX256, LASX256, LASX256, /* XVSRARI_B */ LASX256, LASX256, uimm3, /* XVSRARI_D */ LASX256, LASX256, uimm6, /* XVSRARI_H */ LASX256, LASX256, uimm4, /* XVSRARI_W */ LASX256, LASX256, uimm5, /* XVSRARNI_B_H */ LASX256, LASX256, LASX256, uimm4, /* XVSRARNI_D_Q */ LASX256, LASX256, LASX256, uimm7, /* XVSRARNI_H_W */ LASX256, LASX256, LASX256, uimm5, /* XVSRARNI_W_D */ LASX256, LASX256, LASX256, uimm6, /* XVSRARN_B_H */ LASX256, LASX256, LASX256, /* XVSRARN_H_W */ LASX256, LASX256, LASX256, /* XVSRARN_W_D */ LASX256, LASX256, LASX256, /* XVSRAR_B */ LASX256, LASX256, LASX256, /* XVSRAR_D */ LASX256, LASX256, LASX256, /* XVSRAR_H */ LASX256, LASX256, LASX256, /* XVSRAR_W */ LASX256, LASX256, LASX256, /* XVSRA_B */ LASX256, LASX256, LASX256, /* XVSRA_D */ LASX256, LASX256, LASX256, /* XVSRA_H */ LASX256, LASX256, LASX256, /* XVSRA_W */ LASX256, LASX256, LASX256, /* XVSRLI_B */ LASX256, LASX256, uimm3, /* XVSRLI_D */ LASX256, LASX256, uimm6, /* XVSRLI_H */ LASX256, LASX256, uimm4, /* XVSRLI_W */ LASX256, LASX256, uimm5, /* XVSRLNI_B_H */ LASX256, LASX256, LASX256, uimm4, /* XVSRLNI_D_Q */ LASX256, LASX256, LASX256, uimm7, /* XVSRLNI_H_W */ LASX256, LASX256, LASX256, uimm5, /* XVSRLNI_W_D */ LASX256, LASX256, LASX256, uimm6, /* XVSRLN_B_H */ LASX256, LASX256, LASX256, /* XVSRLN_H_W */ LASX256, LASX256, LASX256, /* XVSRLN_W_D */ LASX256, LASX256, LASX256, /* XVSRLRI_B */ LASX256, LASX256, uimm3, /* XVSRLRI_D */ LASX256, LASX256, uimm6, /* XVSRLRI_H */ LASX256, LASX256, uimm4, /* XVSRLRI_W */ LASX256, LASX256, uimm5, /* XVSRLRNI_B_H */ LASX256, LASX256, LASX256, uimm4, /* XVSRLRNI_D_Q */ LASX256, LASX256, LASX256, uimm7, /* XVSRLRNI_H_W */ LASX256, LASX256, LASX256, uimm5, /* XVSRLRNI_W_D */ LASX256, LASX256, LASX256, uimm6, /* XVSRLRN_B_H */ LASX256, LASX256, LASX256, /* XVSRLRN_H_W */ LASX256, LASX256, LASX256, /* XVSRLRN_W_D */ LASX256, LASX256, LASX256, /* XVSRLR_B */ LASX256, LASX256, LASX256, /* XVSRLR_D */ LASX256, LASX256, LASX256, /* XVSRLR_H */ LASX256, LASX256, LASX256, /* XVSRLR_W */ LASX256, LASX256, LASX256, /* XVSRL_B */ LASX256, LASX256, LASX256, /* XVSRL_D */ LASX256, LASX256, LASX256, /* XVSRL_H */ LASX256, LASX256, LASX256, /* XVSRL_W */ LASX256, LASX256, LASX256, /* XVSSRANI_BU_H */ LASX256, LASX256, LASX256, uimm4, /* XVSSRANI_B_H */ LASX256, LASX256, LASX256, uimm4, /* XVSSRANI_DU_Q */ LASX256, LASX256, LASX256, uimm7, /* XVSSRANI_D_Q */ LASX256, LASX256, LASX256, uimm7, /* XVSSRANI_HU_W */ LASX256, LASX256, LASX256, uimm5, /* XVSSRANI_H_W */ LASX256, LASX256, LASX256, uimm5, /* XVSSRANI_WU_D */ LASX256, LASX256, LASX256, uimm6, /* XVSSRANI_W_D */ LASX256, LASX256, LASX256, uimm6, /* XVSSRAN_BU_H */ LASX256, LASX256, LASX256, /* XVSSRAN_B_H */ LASX256, LASX256, LASX256, /* XVSSRAN_HU_W */ LASX256, LASX256, LASX256, /* XVSSRAN_H_W */ LASX256, LASX256, LASX256, /* XVSSRAN_WU_D */ LASX256, LASX256, LASX256, /* XVSSRAN_W_D */ LASX256, LASX256, LASX256, /* XVSSRARNI_BU_H */ LASX256, LASX256, LASX256, uimm4, /* XVSSRARNI_B_H */ LASX256, LASX256, LASX256, uimm4, /* XVSSRARNI_DU_Q */ LASX256, LASX256, LASX256, uimm7, /* XVSSRARNI_D_Q */ LASX256, LASX256, LASX256, uimm7, /* XVSSRARNI_HU_W */ LASX256, LASX256, LASX256, uimm5, /* XVSSRARNI_H_W */ LASX256, LASX256, LASX256, uimm5, /* XVSSRARNI_WU_D */ LASX256, LASX256, LASX256, uimm6, /* XVSSRARNI_W_D */ LASX256, LASX256, LASX256, uimm6, /* XVSSRARN_BU_H */ LASX256, LASX256, LASX256, /* XVSSRARN_B_H */ LASX256, LASX256, LASX256, /* XVSSRARN_HU_W */ LASX256, LASX256, LASX256, /* XVSSRARN_H_W */ LASX256, LASX256, LASX256, /* XVSSRARN_WU_D */ LASX256, LASX256, LASX256, /* XVSSRARN_W_D */ LASX256, LASX256, LASX256, /* XVSSRLNI_BU_H */ LASX256, LASX256, LASX256, uimm4, /* XVSSRLNI_B_H */ LASX256, LASX256, LASX256, uimm4, /* XVSSRLNI_DU_Q */ LASX256, LASX256, LASX256, uimm7, /* XVSSRLNI_D_Q */ LASX256, LASX256, LASX256, uimm7, /* XVSSRLNI_HU_W */ LASX256, LASX256, LASX256, uimm5, /* XVSSRLNI_H_W */ LASX256, LASX256, LASX256, uimm5, /* XVSSRLNI_WU_D */ LASX256, LASX256, LASX256, uimm6, /* XVSSRLNI_W_D */ LASX256, LASX256, LASX256, uimm6, /* XVSSRLN_BU_H */ LASX256, LASX256, LASX256, /* XVSSRLN_B_H */ LASX256, LASX256, LASX256, /* XVSSRLN_HU_W */ LASX256, LASX256, LASX256, /* XVSSRLN_H_W */ LASX256, LASX256, LASX256, /* XVSSRLN_WU_D */ LASX256, LASX256, LASX256, /* XVSSRLN_W_D */ LASX256, LASX256, LASX256, /* XVSSRLRNI_BU_H */ LASX256, LASX256, LASX256, uimm4, /* XVSSRLRNI_B_H */ LASX256, LASX256, LASX256, uimm4, /* XVSSRLRNI_DU_Q */ LASX256, LASX256, LASX256, uimm7, /* XVSSRLRNI_D_Q */ LASX256, LASX256, LASX256, uimm7, /* XVSSRLRNI_HU_W */ LASX256, LASX256, LASX256, uimm5, /* XVSSRLRNI_H_W */ LASX256, LASX256, LASX256, uimm5, /* XVSSRLRNI_WU_D */ LASX256, LASX256, LASX256, uimm6, /* XVSSRLRNI_W_D */ LASX256, LASX256, LASX256, uimm6, /* XVSSRLRN_BU_H */ LASX256, LASX256, LASX256, /* XVSSRLRN_B_H */ LASX256, LASX256, LASX256, /* XVSSRLRN_HU_W */ LASX256, LASX256, LASX256, /* XVSSRLRN_H_W */ LASX256, LASX256, LASX256, /* XVSSRLRN_WU_D */ LASX256, LASX256, LASX256, /* XVSSRLRN_W_D */ LASX256, LASX256, LASX256, /* XVSSUB_B */ LASX256, LASX256, LASX256, /* XVSSUB_BU */ LASX256, LASX256, LASX256, /* XVSSUB_D */ LASX256, LASX256, LASX256, /* XVSSUB_DU */ LASX256, LASX256, LASX256, /* XVSSUB_H */ LASX256, LASX256, LASX256, /* XVSSUB_HU */ LASX256, LASX256, LASX256, /* XVSSUB_W */ LASX256, LASX256, LASX256, /* XVSSUB_WU */ LASX256, LASX256, LASX256, /* XVST */ LASX256, GPR, simm12, /* XVSTELM_B */ LASX256, GPR, simm8, uimm5, /* XVSTELM_D */ LASX256, GPR, simm8_lsl3, uimm2, /* XVSTELM_H */ LASX256, GPR, simm8_lsl1, uimm4, /* XVSTELM_W */ LASX256, GPR, simm8_lsl2, uimm3, /* XVSTX */ LASX256, GPR, GPR, /* XVSUBI_BU */ LASX256, LASX256, uimm5, /* XVSUBI_DU */ LASX256, LASX256, uimm5, /* XVSUBI_HU */ LASX256, LASX256, uimm5, /* XVSUBI_WU */ LASX256, LASX256, uimm5, /* XVSUBWEV_D_W */ LASX256, LASX256, LASX256, /* XVSUBWEV_D_WU */ LASX256, LASX256, LASX256, /* XVSUBWEV_H_B */ LASX256, LASX256, LASX256, /* XVSUBWEV_H_BU */ LASX256, LASX256, LASX256, /* XVSUBWEV_Q_D */ LASX256, LASX256, LASX256, /* XVSUBWEV_Q_DU */ LASX256, LASX256, LASX256, /* XVSUBWEV_W_H */ LASX256, LASX256, LASX256, /* XVSUBWEV_W_HU */ LASX256, LASX256, LASX256, /* XVSUBWOD_D_W */ LASX256, LASX256, LASX256, /* XVSUBWOD_D_WU */ LASX256, LASX256, LASX256, /* XVSUBWOD_H_B */ LASX256, LASX256, LASX256, /* XVSUBWOD_H_BU */ LASX256, LASX256, LASX256, /* XVSUBWOD_Q_D */ LASX256, LASX256, LASX256, /* XVSUBWOD_Q_DU */ LASX256, LASX256, LASX256, /* XVSUBWOD_W_H */ LASX256, LASX256, LASX256, /* XVSUBWOD_W_HU */ LASX256, LASX256, LASX256, /* XVSUB_B */ LASX256, LASX256, LASX256, /* XVSUB_D */ LASX256, LASX256, LASX256, /* XVSUB_H */ LASX256, LASX256, LASX256, /* XVSUB_Q */ LASX256, LASX256, LASX256, /* XVSUB_W */ LASX256, LASX256, LASX256, /* XVXORI_B */ LASX256, LASX256, uimm8, /* XVXOR_V */ LASX256, LASX256, LASX256, }; return OpcodeOperandTypes[Offsets[Opcode] + OpIdx]; } } // end namespace LoongArch } // end namespace llvm #endif // GET_INSTRINFO_OPERAND_TYPE #ifdef GET_INSTRINFO_MEM_OPERAND_SIZE #undef GET_INSTRINFO_MEM_OPERAND_SIZE namespace llvm { namespace LoongArch { LLVM_READONLY static int getMemOperandSize(int OpType) { switch (OpType) { default: return 0; } } } // end namespace LoongArch } // end namespace llvm #endif // GET_INSTRINFO_MEM_OPERAND_SIZE #ifdef GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP #undef GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP namespace llvm { namespace LoongArch { LLVM_READONLY static unsigned getLogicalOperandSize(uint16_t Opcode, uint16_t LogicalOpIdx) { return LogicalOpIdx; } LLVM_READONLY static inline unsigned getLogicalOperandIdx(uint16_t Opcode, uint16_t LogicalOpIdx) { auto S = 0U; for (auto i = 0U; i < LogicalOpIdx; ++i) S += getLogicalOperandSize(Opcode, i); return S; } } // end namespace LoongArch } // end namespace llvm #endif // GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP #ifdef GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP #undef GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP namespace llvm { namespace LoongArch { LLVM_READONLY static int getLogicalOperandType(uint16_t Opcode, uint16_t LogicalOpIdx) { return -1; } } // end namespace LoongArch } // end namespace llvm #endif // GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP #ifdef GET_INSTRINFO_MC_HELPER_DECLS #undef GET_INSTRINFO_MC_HELPER_DECLS namespace llvm { class MCInst; class FeatureBitset; namespace LoongArch_MC { void verifyInstructionPredicates(unsigned Opcode, const FeatureBitset &Features); } // end namespace LoongArch_MC } // end namespace llvm #endif // GET_INSTRINFO_MC_HELPER_DECLS #ifdef GET_INSTRINFO_MC_HELPERS #undef GET_INSTRINFO_MC_HELPERS namespace llvm { namespace LoongArch_MC { } // end namespace LoongArch_MC } // end namespace llvm #endif // GET_GENISTRINFO_MC_HELPERS #if (defined(ENABLE_INSTR_PREDICATE_VERIFIER) && !defined(NDEBUG)) ||\ defined(GET_AVAILABLE_OPCODE_CHECKER) #define GET_COMPUTE_FEATURES #endif #ifdef GET_COMPUTE_FEATURES #undef GET_COMPUTE_FEATURES namespace llvm { namespace LoongArch_MC { // Bits for subtarget features that participate in instruction matching. enum SubtargetFeatureBits : uint8_t { Feature_IsLA64Bit = 4, Feature_IsLA32Bit = 3, Feature_HasLaGlobalWithPcrelBit = 1, Feature_HasLaGlobalWithAbsBit = 0, Feature_HasLaLocalWithAbsBit = 2, }; inline FeatureBitset computeAvailableFeatures(const FeatureBitset &FB) { FeatureBitset Features; if (FB[LoongArch::Feature64Bit]) Features.set(Feature_IsLA64Bit); if (!FB[LoongArch::Feature64Bit]) Features.set(Feature_IsLA32Bit); if (FB[LoongArch::LaGlobalWithPcrel]) Features.set(Feature_HasLaGlobalWithPcrelBit); if (FB[LoongArch::LaGlobalWithAbs]) Features.set(Feature_HasLaGlobalWithAbsBit); if (FB[LoongArch::LaLocalWithAbs]) Features.set(Feature_HasLaLocalWithAbsBit); return Features; } inline FeatureBitset computeRequiredFeatures(unsigned Opcode) { enum : uint8_t { CEFBS_None, CEFBS_IsLA32, CEFBS_IsLA64, CEFBS_IsLA32_HasLaGlobalWithAbs, CEFBS_IsLA64_HasLaGlobalWithAbs, }; static constexpr FeatureBitset FeatureBitsets[] = { {}, // CEFBS_None {Feature_IsLA32Bit, }, {Feature_IsLA64Bit, }, {Feature_IsLA32Bit, Feature_HasLaGlobalWithAbsBit, }, {Feature_IsLA64Bit, Feature_HasLaGlobalWithAbsBit, }, }; static constexpr uint8_t RequiredFeaturesRefs[] = { CEFBS_None, // PHI = 0 CEFBS_None, // INLINEASM = 1 CEFBS_None, // INLINEASM_BR = 2 CEFBS_None, // CFI_INSTRUCTION = 3 CEFBS_None, // EH_LABEL = 4 CEFBS_None, // GC_LABEL = 5 CEFBS_None, // ANNOTATION_LABEL = 6 CEFBS_None, // KILL = 7 CEFBS_None, // EXTRACT_SUBREG = 8 CEFBS_None, // INSERT_SUBREG = 9 CEFBS_None, // IMPLICIT_DEF = 10 CEFBS_None, // SUBREG_TO_REG = 11 CEFBS_None, // COPY_TO_REGCLASS = 12 CEFBS_None, // DBG_VALUE = 13 CEFBS_None, // DBG_VALUE_LIST = 14 CEFBS_None, // DBG_INSTR_REF = 15 CEFBS_None, // DBG_PHI = 16 CEFBS_None, // DBG_LABEL = 17 CEFBS_None, // REG_SEQUENCE = 18 CEFBS_None, // COPY = 19 CEFBS_None, // BUNDLE = 20 CEFBS_None, // LIFETIME_START = 21 CEFBS_None, // LIFETIME_END = 22 CEFBS_None, // PSEUDO_PROBE = 23 CEFBS_None, // ARITH_FENCE = 24 CEFBS_None, // STACKMAP = 25 CEFBS_None, // FENTRY_CALL = 26 CEFBS_None, // PATCHPOINT = 27 CEFBS_None, // LOAD_STACK_GUARD = 28 CEFBS_None, // PREALLOCATED_SETUP = 29 CEFBS_None, // PREALLOCATED_ARG = 30 CEFBS_None, // STATEPOINT = 31 CEFBS_None, // LOCAL_ESCAPE = 32 CEFBS_None, // FAULTING_OP = 33 CEFBS_None, // PATCHABLE_OP = 34 CEFBS_None, // PATCHABLE_FUNCTION_ENTER = 35 CEFBS_None, // PATCHABLE_RET = 36 CEFBS_None, // PATCHABLE_FUNCTION_EXIT = 37 CEFBS_None, // PATCHABLE_TAIL_CALL = 38 CEFBS_None, // PATCHABLE_EVENT_CALL = 39 CEFBS_None, // PATCHABLE_TYPED_EVENT_CALL = 40 CEFBS_None, // ICALL_BRANCH_FUNNEL = 41 CEFBS_None, // FAKE_USE = 42 CEFBS_None, // MEMBARRIER = 43 CEFBS_None, // JUMP_TABLE_DEBUG_INFO = 44 CEFBS_None, // CONVERGENCECTRL_ENTRY = 45 CEFBS_None, // CONVERGENCECTRL_ANCHOR = 46 CEFBS_None, // CONVERGENCECTRL_LOOP = 47 CEFBS_None, // CONVERGENCECTRL_GLUE = 48 CEFBS_None, // G_ASSERT_SEXT = 49 CEFBS_None, // G_ASSERT_ZEXT = 50 CEFBS_None, // G_ASSERT_ALIGN = 51 CEFBS_None, // G_ADD = 52 CEFBS_None, // G_SUB = 53 CEFBS_None, // G_MUL = 54 CEFBS_None, // G_SDIV = 55 CEFBS_None, // G_UDIV = 56 CEFBS_None, // G_SREM = 57 CEFBS_None, // G_UREM = 58 CEFBS_None, // G_SDIVREM = 59 CEFBS_None, // G_UDIVREM = 60 CEFBS_None, // G_AND = 61 CEFBS_None, // G_OR = 62 CEFBS_None, // G_XOR = 63 CEFBS_None, // G_IMPLICIT_DEF = 64 CEFBS_None, // G_PHI = 65 CEFBS_None, // G_FRAME_INDEX = 66 CEFBS_None, // G_GLOBAL_VALUE = 67 CEFBS_None, // G_PTRAUTH_GLOBAL_VALUE = 68 CEFBS_None, // G_CONSTANT_POOL = 69 CEFBS_None, // G_EXTRACT = 70 CEFBS_None, // G_UNMERGE_VALUES = 71 CEFBS_None, // G_INSERT = 72 CEFBS_None, // G_MERGE_VALUES = 73 CEFBS_None, // G_BUILD_VECTOR = 74 CEFBS_None, // G_BUILD_VECTOR_TRUNC = 75 CEFBS_None, // G_CONCAT_VECTORS = 76 CEFBS_None, // G_PTRTOINT = 77 CEFBS_None, // G_INTTOPTR = 78 CEFBS_None, // G_BITCAST = 79 CEFBS_None, // G_FREEZE = 80 CEFBS_None, // G_CONSTANT_FOLD_BARRIER = 81 CEFBS_None, // G_INTRINSIC_FPTRUNC_ROUND = 82 CEFBS_None, // G_INTRINSIC_TRUNC = 83 CEFBS_None, // G_INTRINSIC_ROUND = 84 CEFBS_None, // G_INTRINSIC_LRINT = 85 CEFBS_None, // G_INTRINSIC_LLRINT = 86 CEFBS_None, // G_INTRINSIC_ROUNDEVEN = 87 CEFBS_None, // G_READCYCLECOUNTER = 88 CEFBS_None, // G_READSTEADYCOUNTER = 89 CEFBS_None, // G_LOAD = 90 CEFBS_None, // G_SEXTLOAD = 91 CEFBS_None, // G_ZEXTLOAD = 92 CEFBS_None, // G_INDEXED_LOAD = 93 CEFBS_None, // G_INDEXED_SEXTLOAD = 94 CEFBS_None, // G_INDEXED_ZEXTLOAD = 95 CEFBS_None, // G_STORE = 96 CEFBS_None, // G_INDEXED_STORE = 97 CEFBS_None, // G_ATOMIC_CMPXCHG_WITH_SUCCESS = 98 CEFBS_None, // G_ATOMIC_CMPXCHG = 99 CEFBS_None, // G_ATOMICRMW_XCHG = 100 CEFBS_None, // G_ATOMICRMW_ADD = 101 CEFBS_None, // G_ATOMICRMW_SUB = 102 CEFBS_None, // G_ATOMICRMW_AND = 103 CEFBS_None, // G_ATOMICRMW_NAND = 104 CEFBS_None, // G_ATOMICRMW_OR = 105 CEFBS_None, // G_ATOMICRMW_XOR = 106 CEFBS_None, // G_ATOMICRMW_MAX = 107 CEFBS_None, // G_ATOMICRMW_MIN = 108 CEFBS_None, // G_ATOMICRMW_UMAX = 109 CEFBS_None, // G_ATOMICRMW_UMIN = 110 CEFBS_None, // G_ATOMICRMW_FADD = 111 CEFBS_None, // G_ATOMICRMW_FSUB = 112 CEFBS_None, // G_ATOMICRMW_FMAX = 113 CEFBS_None, // G_ATOMICRMW_FMIN = 114 CEFBS_None, // G_ATOMICRMW_UINC_WRAP = 115 CEFBS_None, // G_ATOMICRMW_UDEC_WRAP = 116 CEFBS_None, // G_FENCE = 117 CEFBS_None, // G_PREFETCH = 118 CEFBS_None, // G_BRCOND = 119 CEFBS_None, // G_BRINDIRECT = 120 CEFBS_None, // G_INVOKE_REGION_START = 121 CEFBS_None, // G_INTRINSIC = 122 CEFBS_None, // G_INTRINSIC_W_SIDE_EFFECTS = 123 CEFBS_None, // G_INTRINSIC_CONVERGENT = 124 CEFBS_None, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS = 125 CEFBS_None, // G_ANYEXT = 126 CEFBS_None, // G_TRUNC = 127 CEFBS_None, // G_CONSTANT = 128 CEFBS_None, // G_FCONSTANT = 129 CEFBS_None, // G_VASTART = 130 CEFBS_None, // G_VAARG = 131 CEFBS_None, // G_SEXT = 132 CEFBS_None, // G_SEXT_INREG = 133 CEFBS_None, // G_ZEXT = 134 CEFBS_None, // G_SHL = 135 CEFBS_None, // G_LSHR = 136 CEFBS_None, // G_ASHR = 137 CEFBS_None, // G_FSHL = 138 CEFBS_None, // G_FSHR = 139 CEFBS_None, // G_ROTR = 140 CEFBS_None, // G_ROTL = 141 CEFBS_None, // G_ICMP = 142 CEFBS_None, // G_FCMP = 143 CEFBS_None, // G_SCMP = 144 CEFBS_None, // G_UCMP = 145 CEFBS_None, // G_SELECT = 146 CEFBS_None, // G_UADDO = 147 CEFBS_None, // G_UADDE = 148 CEFBS_None, // G_USUBO = 149 CEFBS_None, // G_USUBE = 150 CEFBS_None, // G_SADDO = 151 CEFBS_None, // G_SADDE = 152 CEFBS_None, // G_SSUBO = 153 CEFBS_None, // G_SSUBE = 154 CEFBS_None, // G_UMULO = 155 CEFBS_None, // G_SMULO = 156 CEFBS_None, // G_UMULH = 157 CEFBS_None, // G_SMULH = 158 CEFBS_None, // G_UADDSAT = 159 CEFBS_None, // G_SADDSAT = 160 CEFBS_None, // G_USUBSAT = 161 CEFBS_None, // G_SSUBSAT = 162 CEFBS_None, // G_USHLSAT = 163 CEFBS_None, // G_SSHLSAT = 164 CEFBS_None, // G_SMULFIX = 165 CEFBS_None, // G_UMULFIX = 166 CEFBS_None, // G_SMULFIXSAT = 167 CEFBS_None, // G_UMULFIXSAT = 168 CEFBS_None, // G_SDIVFIX = 169 CEFBS_None, // G_UDIVFIX = 170 CEFBS_None, // G_SDIVFIXSAT = 171 CEFBS_None, // G_UDIVFIXSAT = 172 CEFBS_None, // G_FADD = 173 CEFBS_None, // G_FSUB = 174 CEFBS_None, // G_FMUL = 175 CEFBS_None, // G_FMA = 176 CEFBS_None, // G_FMAD = 177 CEFBS_None, // G_FDIV = 178 CEFBS_None, // G_FREM = 179 CEFBS_None, // G_FPOW = 180 CEFBS_None, // G_FPOWI = 181 CEFBS_None, // G_FEXP = 182 CEFBS_None, // G_FEXP2 = 183 CEFBS_None, // G_FEXP10 = 184 CEFBS_None, // G_FLOG = 185 CEFBS_None, // G_FLOG2 = 186 CEFBS_None, // G_FLOG10 = 187 CEFBS_None, // G_FLDEXP = 188 CEFBS_None, // G_FFREXP = 189 CEFBS_None, // G_FNEG = 190 CEFBS_None, // G_FPEXT = 191 CEFBS_None, // G_FPTRUNC = 192 CEFBS_None, // G_FPTOSI = 193 CEFBS_None, // G_FPTOUI = 194 CEFBS_None, // G_SITOFP = 195 CEFBS_None, // G_UITOFP = 196 CEFBS_None, // G_FABS = 197 CEFBS_None, // G_FCOPYSIGN = 198 CEFBS_None, // G_IS_FPCLASS = 199 CEFBS_None, // G_FCANONICALIZE = 200 CEFBS_None, // G_FMINNUM = 201 CEFBS_None, // G_FMAXNUM = 202 CEFBS_None, // G_FMINNUM_IEEE = 203 CEFBS_None, // G_FMAXNUM_IEEE = 204 CEFBS_None, // G_FMINIMUM = 205 CEFBS_None, // G_FMAXIMUM = 206 CEFBS_None, // G_GET_FPENV = 207 CEFBS_None, // G_SET_FPENV = 208 CEFBS_None, // G_RESET_FPENV = 209 CEFBS_None, // G_GET_FPMODE = 210 CEFBS_None, // G_SET_FPMODE = 211 CEFBS_None, // G_RESET_FPMODE = 212 CEFBS_None, // G_PTR_ADD = 213 CEFBS_None, // G_PTRMASK = 214 CEFBS_None, // G_SMIN = 215 CEFBS_None, // G_SMAX = 216 CEFBS_None, // G_UMIN = 217 CEFBS_None, // G_UMAX = 218 CEFBS_None, // G_ABS = 219 CEFBS_None, // G_LROUND = 220 CEFBS_None, // G_LLROUND = 221 CEFBS_None, // G_BR = 222 CEFBS_None, // G_BRJT = 223 CEFBS_None, // G_VSCALE = 224 CEFBS_None, // G_INSERT_SUBVECTOR = 225 CEFBS_None, // G_EXTRACT_SUBVECTOR = 226 CEFBS_None, // G_INSERT_VECTOR_ELT = 227 CEFBS_None, // G_EXTRACT_VECTOR_ELT = 228 CEFBS_None, // G_SHUFFLE_VECTOR = 229 CEFBS_None, // G_SPLAT_VECTOR = 230 CEFBS_None, // G_VECTOR_COMPRESS = 231 CEFBS_None, // G_CTTZ = 232 CEFBS_None, // G_CTTZ_ZERO_UNDEF = 233 CEFBS_None, // G_CTLZ = 234 CEFBS_None, // G_CTLZ_ZERO_UNDEF = 235 CEFBS_None, // G_CTPOP = 236 CEFBS_None, // G_BSWAP = 237 CEFBS_None, // G_BITREVERSE = 238 CEFBS_None, // G_FCEIL = 239 CEFBS_None, // G_FCOS = 240 CEFBS_None, // G_FSIN = 241 CEFBS_None, // G_FTAN = 242 CEFBS_None, // G_FACOS = 243 CEFBS_None, // G_FASIN = 244 CEFBS_None, // G_FATAN = 245 CEFBS_None, // G_FCOSH = 246 CEFBS_None, // G_FSINH = 247 CEFBS_None, // G_FTANH = 248 CEFBS_None, // G_FSQRT = 249 CEFBS_None, // G_FFLOOR = 250 CEFBS_None, // G_FRINT = 251 CEFBS_None, // G_FNEARBYINT = 252 CEFBS_None, // G_ADDRSPACE_CAST = 253 CEFBS_None, // G_BLOCK_ADDR = 254 CEFBS_None, // G_JUMP_TABLE = 255 CEFBS_None, // G_DYN_STACKALLOC = 256 CEFBS_None, // G_STACKSAVE = 257 CEFBS_None, // G_STACKRESTORE = 258 CEFBS_None, // G_STRICT_FADD = 259 CEFBS_None, // G_STRICT_FSUB = 260 CEFBS_None, // G_STRICT_FMUL = 261 CEFBS_None, // G_STRICT_FDIV = 262 CEFBS_None, // G_STRICT_FREM = 263 CEFBS_None, // G_STRICT_FMA = 264 CEFBS_None, // G_STRICT_FSQRT = 265 CEFBS_None, // G_STRICT_FLDEXP = 266 CEFBS_None, // G_READ_REGISTER = 267 CEFBS_None, // G_WRITE_REGISTER = 268 CEFBS_None, // G_MEMCPY = 269 CEFBS_None, // G_MEMCPY_INLINE = 270 CEFBS_None, // G_MEMMOVE = 271 CEFBS_None, // G_MEMSET = 272 CEFBS_None, // G_BZERO = 273 CEFBS_None, // G_TRAP = 274 CEFBS_None, // G_DEBUGTRAP = 275 CEFBS_None, // G_UBSANTRAP = 276 CEFBS_None, // G_VECREDUCE_SEQ_FADD = 277 CEFBS_None, // G_VECREDUCE_SEQ_FMUL = 278 CEFBS_None, // G_VECREDUCE_FADD = 279 CEFBS_None, // G_VECREDUCE_FMUL = 280 CEFBS_None, // G_VECREDUCE_FMAX = 281 CEFBS_None, // G_VECREDUCE_FMIN = 282 CEFBS_None, // G_VECREDUCE_FMAXIMUM = 283 CEFBS_None, // G_VECREDUCE_FMINIMUM = 284 CEFBS_None, // G_VECREDUCE_ADD = 285 CEFBS_None, // G_VECREDUCE_MUL = 286 CEFBS_None, // G_VECREDUCE_AND = 287 CEFBS_None, // G_VECREDUCE_OR = 288 CEFBS_None, // G_VECREDUCE_XOR = 289 CEFBS_None, // G_VECREDUCE_SMAX = 290 CEFBS_None, // G_VECREDUCE_SMIN = 291 CEFBS_None, // G_VECREDUCE_UMAX = 292 CEFBS_None, // G_VECREDUCE_UMIN = 293 CEFBS_None, // G_SBFX = 294 CEFBS_None, // G_UBFX = 295 CEFBS_None, // ADJCALLSTACKDOWN = 296 CEFBS_None, // ADJCALLSTACKUP = 297 CEFBS_IsLA64, // PseudoAddTPRel_D = 298 CEFBS_IsLA32, // PseudoAddTPRel_W = 299 CEFBS_None, // PseudoAtomicLoadAdd32 = 300 CEFBS_None, // PseudoAtomicLoadAnd32 = 301 CEFBS_None, // PseudoAtomicLoadNand32 = 302 CEFBS_None, // PseudoAtomicLoadNand64 = 303 CEFBS_None, // PseudoAtomicLoadOr32 = 304 CEFBS_None, // PseudoAtomicLoadSub32 = 305 CEFBS_None, // PseudoAtomicLoadXor32 = 306 CEFBS_IsLA64, // PseudoAtomicStoreD = 307 CEFBS_None, // PseudoAtomicStoreW = 308 CEFBS_None, // PseudoAtomicSwap32 = 309 CEFBS_None, // PseudoBR = 310 CEFBS_None, // PseudoBRIND = 311 CEFBS_None, // PseudoB_TAIL = 312 CEFBS_None, // PseudoCALL = 313 CEFBS_IsLA64, // PseudoCALL36 = 314 CEFBS_None, // PseudoCALLIndirect = 315 CEFBS_None, // PseudoCALL_LARGE = 316 CEFBS_None, // PseudoCALL_MEDIUM = 317 CEFBS_None, // PseudoCmpXchg32 = 318 CEFBS_None, // PseudoCmpXchg64 = 319 CEFBS_None, // PseudoCopyCFR = 320 CEFBS_None, // PseudoDESC_CALL = 321 CEFBS_None, // PseudoJIRL_CALL = 322 CEFBS_None, // PseudoJIRL_TAIL = 323 CEFBS_None, // PseudoLA_ABS = 324 CEFBS_None, // PseudoLA_ABS_LARGE = 325 CEFBS_None, // PseudoLA_GOT = 326 CEFBS_IsLA64, // PseudoLA_GOT_LARGE = 327 CEFBS_None, // PseudoLA_PCREL = 328 CEFBS_IsLA64, // PseudoLA_PCREL_LARGE = 329 CEFBS_IsLA32_HasLaGlobalWithAbs, // PseudoLA_TLS_DESC_ABS = 330 CEFBS_IsLA64_HasLaGlobalWithAbs, // PseudoLA_TLS_DESC_ABS_LARGE = 331 CEFBS_None, // PseudoLA_TLS_DESC_PC = 332 CEFBS_IsLA64, // PseudoLA_TLS_DESC_PC_LARGE = 333 CEFBS_None, // PseudoLA_TLS_GD = 334 CEFBS_IsLA64, // PseudoLA_TLS_GD_LARGE = 335 CEFBS_None, // PseudoLA_TLS_IE = 336 CEFBS_IsLA64, // PseudoLA_TLS_IE_LARGE = 337 CEFBS_None, // PseudoLA_TLS_LD = 338 CEFBS_IsLA64, // PseudoLA_TLS_LD_LARGE = 339 CEFBS_None, // PseudoLA_TLS_LE = 340 CEFBS_None, // PseudoLD_CFR = 341 CEFBS_IsLA64, // PseudoLI_D = 342 CEFBS_None, // PseudoLI_W = 343 CEFBS_None, // PseudoMaskedAtomicLoadAdd32 = 344 CEFBS_None, // PseudoMaskedAtomicLoadMax32 = 345 CEFBS_None, // PseudoMaskedAtomicLoadMin32 = 346 CEFBS_None, // PseudoMaskedAtomicLoadNand32 = 347 CEFBS_None, // PseudoMaskedAtomicLoadSub32 = 348 CEFBS_None, // PseudoMaskedAtomicLoadUMax32 = 349 CEFBS_None, // PseudoMaskedAtomicLoadUMin32 = 350 CEFBS_None, // PseudoMaskedAtomicSwap32 = 351 CEFBS_None, // PseudoMaskedCmpXchg32 = 352 CEFBS_None, // PseudoRET = 353 CEFBS_None, // PseudoST_CFR = 354 CEFBS_None, // PseudoTAIL = 355 CEFBS_IsLA64, // PseudoTAIL36 = 356 CEFBS_None, // PseudoTAILIndirect = 357 CEFBS_None, // PseudoTAIL_LARGE = 358 CEFBS_None, // PseudoTAIL_MEDIUM = 359 CEFBS_None, // PseudoUNIMP = 360 CEFBS_None, // PseudoVBNZ = 361 CEFBS_None, // PseudoVBNZ_B = 362 CEFBS_None, // PseudoVBNZ_D = 363 CEFBS_None, // PseudoVBNZ_H = 364 CEFBS_None, // PseudoVBNZ_W = 365 CEFBS_None, // PseudoVBZ = 366 CEFBS_None, // PseudoVBZ_B = 367 CEFBS_None, // PseudoVBZ_D = 368 CEFBS_None, // PseudoVBZ_H = 369 CEFBS_None, // PseudoVBZ_W = 370 CEFBS_None, // PseudoVREPLI_B = 371 CEFBS_None, // PseudoVREPLI_D = 372 CEFBS_None, // PseudoVREPLI_H = 373 CEFBS_None, // PseudoVREPLI_W = 374 CEFBS_None, // PseudoXVBNZ = 375 CEFBS_None, // PseudoXVBNZ_B = 376 CEFBS_None, // PseudoXVBNZ_D = 377 CEFBS_None, // PseudoXVBNZ_H = 378 CEFBS_None, // PseudoXVBNZ_W = 379 CEFBS_None, // PseudoXVBZ = 380 CEFBS_None, // PseudoXVBZ_B = 381 CEFBS_None, // PseudoXVBZ_D = 382 CEFBS_None, // PseudoXVBZ_H = 383 CEFBS_None, // PseudoXVBZ_W = 384 CEFBS_None, // PseudoXVINSGR2VR_B = 385 CEFBS_None, // PseudoXVINSGR2VR_H = 386 CEFBS_None, // PseudoXVREPLI_B = 387 CEFBS_None, // PseudoXVREPLI_D = 388 CEFBS_None, // PseudoXVREPLI_H = 389 CEFBS_None, // PseudoXVREPLI_W = 390 CEFBS_None, // RDFCSR = 391 CEFBS_None, // WRFCSR = 392 CEFBS_None, // ADC_B = 393 CEFBS_IsLA64, // ADC_D = 394 CEFBS_None, // ADC_H = 395 CEFBS_None, // ADC_W = 396 CEFBS_IsLA64, // ADDI_D = 397 CEFBS_None, // ADDI_W = 398 CEFBS_IsLA64, // ADDU12I_D = 399 CEFBS_None, // ADDU12I_W = 400 CEFBS_IsLA64, // ADDU16I_D = 401 CEFBS_IsLA64, // ADD_D = 402 CEFBS_None, // ADD_W = 403 CEFBS_IsLA64, // ALSL_D = 404 CEFBS_None, // ALSL_W = 405 CEFBS_IsLA64, // ALSL_WU = 406 CEFBS_IsLA64, // AMADD_B = 407 CEFBS_IsLA64, // AMADD_D = 408 CEFBS_IsLA64, // AMADD_H = 409 CEFBS_IsLA64, // AMADD_W = 410 CEFBS_IsLA64, // AMADD__DB_B = 411 CEFBS_IsLA64, // AMADD__DB_D = 412 CEFBS_IsLA64, // AMADD__DB_H = 413 CEFBS_IsLA64, // AMADD__DB_W = 414 CEFBS_IsLA64, // AMAND_D = 415 CEFBS_IsLA64, // AMAND_W = 416 CEFBS_IsLA64, // AMAND__DB_D = 417 CEFBS_IsLA64, // AMAND__DB_W = 418 CEFBS_IsLA64, // AMCAS_B = 419 CEFBS_IsLA64, // AMCAS_D = 420 CEFBS_IsLA64, // AMCAS_H = 421 CEFBS_IsLA64, // AMCAS_W = 422 CEFBS_IsLA64, // AMCAS__DB_B = 423 CEFBS_IsLA64, // AMCAS__DB_D = 424 CEFBS_IsLA64, // AMCAS__DB_H = 425 CEFBS_IsLA64, // AMCAS__DB_W = 426 CEFBS_IsLA64, // AMMAX_D = 427 CEFBS_IsLA64, // AMMAX_DU = 428 CEFBS_IsLA64, // AMMAX_W = 429 CEFBS_IsLA64, // AMMAX_WU = 430 CEFBS_IsLA64, // AMMAX__DB_D = 431 CEFBS_IsLA64, // AMMAX__DB_DU = 432 CEFBS_IsLA64, // AMMAX__DB_W = 433 CEFBS_IsLA64, // AMMAX__DB_WU = 434 CEFBS_IsLA64, // AMMIN_D = 435 CEFBS_IsLA64, // AMMIN_DU = 436 CEFBS_IsLA64, // AMMIN_W = 437 CEFBS_IsLA64, // AMMIN_WU = 438 CEFBS_IsLA64, // AMMIN__DB_D = 439 CEFBS_IsLA64, // AMMIN__DB_DU = 440 CEFBS_IsLA64, // AMMIN__DB_W = 441 CEFBS_IsLA64, // AMMIN__DB_WU = 442 CEFBS_IsLA64, // AMOR_D = 443 CEFBS_IsLA64, // AMOR_W = 444 CEFBS_IsLA64, // AMOR__DB_D = 445 CEFBS_IsLA64, // AMOR__DB_W = 446 CEFBS_IsLA64, // AMSWAP_B = 447 CEFBS_IsLA64, // AMSWAP_D = 448 CEFBS_IsLA64, // AMSWAP_H = 449 CEFBS_IsLA64, // AMSWAP_W = 450 CEFBS_IsLA64, // AMSWAP__DB_B = 451 CEFBS_IsLA64, // AMSWAP__DB_D = 452 CEFBS_IsLA64, // AMSWAP__DB_H = 453 CEFBS_IsLA64, // AMSWAP__DB_W = 454 CEFBS_IsLA64, // AMXOR_D = 455 CEFBS_IsLA64, // AMXOR_W = 456 CEFBS_IsLA64, // AMXOR__DB_D = 457 CEFBS_IsLA64, // AMXOR__DB_W = 458 CEFBS_None, // AND = 459 CEFBS_None, // ANDI = 460 CEFBS_None, // ANDN = 461 CEFBS_None, // ARMADC_W = 462 CEFBS_None, // ARMADD_W = 463 CEFBS_None, // ARMAND_W = 464 CEFBS_None, // ARMMFFLAG = 465 CEFBS_None, // ARMMOVE = 466 CEFBS_IsLA64, // ARMMOV_D = 467 CEFBS_None, // ARMMOV_W = 468 CEFBS_None, // ARMMTFLAG = 469 CEFBS_None, // ARMNOT_W = 470 CEFBS_None, // ARMOR_W = 471 CEFBS_None, // ARMROTRI_W = 472 CEFBS_None, // ARMROTR_W = 473 CEFBS_None, // ARMRRX_W = 474 CEFBS_None, // ARMSBC_W = 475 CEFBS_None, // ARMSLLI_W = 476 CEFBS_None, // ARMSLL_W = 477 CEFBS_None, // ARMSRAI_W = 478 CEFBS_None, // ARMSRA_W = 479 CEFBS_None, // ARMSRLI_W = 480 CEFBS_None, // ARMSRL_W = 481 CEFBS_None, // ARMSUB_W = 482 CEFBS_None, // ARMXOR_W = 483 CEFBS_IsLA64, // ASRTGT_D = 484 CEFBS_IsLA64, // ASRTLE_D = 485 CEFBS_None, // B = 486 CEFBS_None, // BCEQZ = 487 CEFBS_None, // BCNEZ = 488 CEFBS_None, // BEQ = 489 CEFBS_None, // BEQZ = 490 CEFBS_None, // BGE = 491 CEFBS_None, // BGEU = 492 CEFBS_None, // BITREV_4B = 493 CEFBS_IsLA64, // BITREV_8B = 494 CEFBS_IsLA64, // BITREV_D = 495 CEFBS_None, // BITREV_W = 496 CEFBS_None, // BL = 497 CEFBS_None, // BLT = 498 CEFBS_None, // BLTU = 499 CEFBS_None, // BNE = 500 CEFBS_None, // BNEZ = 501 CEFBS_None, // BREAK = 502 CEFBS_IsLA64, // BSTRINS_D = 503 CEFBS_None, // BSTRINS_W = 504 CEFBS_IsLA64, // BSTRPICK_D = 505 CEFBS_None, // BSTRPICK_W = 506 CEFBS_IsLA64, // BYTEPICK_D = 507 CEFBS_None, // BYTEPICK_W = 508 CEFBS_None, // CACOP = 509 CEFBS_IsLA64, // CLO_D = 510 CEFBS_None, // CLO_W = 511 CEFBS_IsLA64, // CLZ_D = 512 CEFBS_None, // CLZ_W = 513 CEFBS_None, // CPUCFG = 514 CEFBS_IsLA64, // CRCC_W_B_W = 515 CEFBS_IsLA64, // CRCC_W_D_W = 516 CEFBS_IsLA64, // CRCC_W_H_W = 517 CEFBS_IsLA64, // CRCC_W_W_W = 518 CEFBS_IsLA64, // CRC_W_B_W = 519 CEFBS_IsLA64, // CRC_W_D_W = 520 CEFBS_IsLA64, // CRC_W_H_W = 521 CEFBS_IsLA64, // CRC_W_W_W = 522 CEFBS_None, // CSRRD = 523 CEFBS_None, // CSRWR = 524 CEFBS_None, // CSRXCHG = 525 CEFBS_IsLA64, // CTO_D = 526 CEFBS_None, // CTO_W = 527 CEFBS_IsLA64, // CTZ_D = 528 CEFBS_None, // CTZ_W = 529 CEFBS_None, // DBAR = 530 CEFBS_None, // DBCL = 531 CEFBS_IsLA64, // DIV_D = 532 CEFBS_IsLA64, // DIV_DU = 533 CEFBS_None, // DIV_W = 534 CEFBS_None, // DIV_WU = 535 CEFBS_None, // ERTN = 536 CEFBS_None, // EXT_W_B = 537 CEFBS_None, // EXT_W_H = 538 CEFBS_None, // FABS_D = 539 CEFBS_None, // FABS_S = 540 CEFBS_None, // FADD_D = 541 CEFBS_None, // FADD_S = 542 CEFBS_None, // FCLASS_D = 543 CEFBS_None, // FCLASS_S = 544 CEFBS_None, // FCMP_CAF_D = 545 CEFBS_None, // FCMP_CAF_S = 546 CEFBS_None, // FCMP_CEQ_D = 547 CEFBS_None, // FCMP_CEQ_S = 548 CEFBS_None, // FCMP_CLE_D = 549 CEFBS_None, // FCMP_CLE_S = 550 CEFBS_None, // FCMP_CLT_D = 551 CEFBS_None, // FCMP_CLT_S = 552 CEFBS_None, // FCMP_CNE_D = 553 CEFBS_None, // FCMP_CNE_S = 554 CEFBS_None, // FCMP_COR_D = 555 CEFBS_None, // FCMP_COR_S = 556 CEFBS_None, // FCMP_CUEQ_D = 557 CEFBS_None, // FCMP_CUEQ_S = 558 CEFBS_None, // FCMP_CULE_D = 559 CEFBS_None, // FCMP_CULE_S = 560 CEFBS_None, // FCMP_CULT_D = 561 CEFBS_None, // FCMP_CULT_S = 562 CEFBS_None, // FCMP_CUNE_D = 563 CEFBS_None, // FCMP_CUNE_S = 564 CEFBS_None, // FCMP_CUN_D = 565 CEFBS_None, // FCMP_CUN_S = 566 CEFBS_None, // FCMP_SAF_D = 567 CEFBS_None, // FCMP_SAF_S = 568 CEFBS_None, // FCMP_SEQ_D = 569 CEFBS_None, // FCMP_SEQ_S = 570 CEFBS_None, // FCMP_SLE_D = 571 CEFBS_None, // FCMP_SLE_S = 572 CEFBS_None, // FCMP_SLT_D = 573 CEFBS_None, // FCMP_SLT_S = 574 CEFBS_None, // FCMP_SNE_D = 575 CEFBS_None, // FCMP_SNE_S = 576 CEFBS_None, // FCMP_SOR_D = 577 CEFBS_None, // FCMP_SOR_S = 578 CEFBS_None, // FCMP_SUEQ_D = 579 CEFBS_None, // FCMP_SUEQ_S = 580 CEFBS_None, // FCMP_SULE_D = 581 CEFBS_None, // FCMP_SULE_S = 582 CEFBS_None, // FCMP_SULT_D = 583 CEFBS_None, // FCMP_SULT_S = 584 CEFBS_None, // FCMP_SUNE_D = 585 CEFBS_None, // FCMP_SUNE_S = 586 CEFBS_None, // FCMP_SUN_D = 587 CEFBS_None, // FCMP_SUN_S = 588 CEFBS_None, // FCOPYSIGN_D = 589 CEFBS_None, // FCOPYSIGN_S = 590 CEFBS_None, // FCVT_D_LD = 591 CEFBS_None, // FCVT_D_S = 592 CEFBS_None, // FCVT_LD_D = 593 CEFBS_None, // FCVT_S_D = 594 CEFBS_None, // FCVT_UD_D = 595 CEFBS_None, // FDIV_D = 596 CEFBS_None, // FDIV_S = 597 CEFBS_None, // FFINT_D_L = 598 CEFBS_None, // FFINT_D_W = 599 CEFBS_None, // FFINT_S_L = 600 CEFBS_None, // FFINT_S_W = 601 CEFBS_None, // FLDGT_D = 602 CEFBS_None, // FLDGT_S = 603 CEFBS_None, // FLDLE_D = 604 CEFBS_None, // FLDLE_S = 605 CEFBS_None, // FLDX_D = 606 CEFBS_None, // FLDX_S = 607 CEFBS_None, // FLD_D = 608 CEFBS_None, // FLD_S = 609 CEFBS_None, // FLOGB_D = 610 CEFBS_None, // FLOGB_S = 611 CEFBS_None, // FMADD_D = 612 CEFBS_None, // FMADD_S = 613 CEFBS_None, // FMAXA_D = 614 CEFBS_None, // FMAXA_S = 615 CEFBS_None, // FMAX_D = 616 CEFBS_None, // FMAX_S = 617 CEFBS_None, // FMINA_D = 618 CEFBS_None, // FMINA_S = 619 CEFBS_None, // FMIN_D = 620 CEFBS_None, // FMIN_S = 621 CEFBS_None, // FMOV_D = 622 CEFBS_None, // FMOV_S = 623 CEFBS_None, // FMSUB_D = 624 CEFBS_None, // FMSUB_S = 625 CEFBS_None, // FMUL_D = 626 CEFBS_None, // FMUL_S = 627 CEFBS_None, // FNEG_D = 628 CEFBS_None, // FNEG_S = 629 CEFBS_None, // FNMADD_D = 630 CEFBS_None, // FNMADD_S = 631 CEFBS_None, // FNMSUB_D = 632 CEFBS_None, // FNMSUB_S = 633 CEFBS_None, // FRECIPE_D = 634 CEFBS_None, // FRECIPE_S = 635 CEFBS_None, // FRECIP_D = 636 CEFBS_None, // FRECIP_S = 637 CEFBS_None, // FRINT_D = 638 CEFBS_None, // FRINT_S = 639 CEFBS_None, // FRSQRTE_D = 640 CEFBS_None, // FRSQRTE_S = 641 CEFBS_None, // FRSQRT_D = 642 CEFBS_None, // FRSQRT_S = 643 CEFBS_None, // FSCALEB_D = 644 CEFBS_None, // FSCALEB_S = 645 CEFBS_None, // FSEL_xD = 646 CEFBS_None, // FSEL_xS = 647 CEFBS_None, // FSQRT_D = 648 CEFBS_None, // FSQRT_S = 649 CEFBS_None, // FSTGT_D = 650 CEFBS_None, // FSTGT_S = 651 CEFBS_None, // FSTLE_D = 652 CEFBS_None, // FSTLE_S = 653 CEFBS_None, // FSTX_D = 654 CEFBS_None, // FSTX_S = 655 CEFBS_None, // FST_D = 656 CEFBS_None, // FST_S = 657 CEFBS_None, // FSUB_D = 658 CEFBS_None, // FSUB_S = 659 CEFBS_None, // FTINTRM_L_D = 660 CEFBS_None, // FTINTRM_L_S = 661 CEFBS_None, // FTINTRM_W_D = 662 CEFBS_None, // FTINTRM_W_S = 663 CEFBS_None, // FTINTRNE_L_D = 664 CEFBS_None, // FTINTRNE_L_S = 665 CEFBS_None, // FTINTRNE_W_D = 666 CEFBS_None, // FTINTRNE_W_S = 667 CEFBS_None, // FTINTRP_L_D = 668 CEFBS_None, // FTINTRP_L_S = 669 CEFBS_None, // FTINTRP_W_D = 670 CEFBS_None, // FTINTRP_W_S = 671 CEFBS_None, // FTINTRZ_L_D = 672 CEFBS_None, // FTINTRZ_L_S = 673 CEFBS_None, // FTINTRZ_W_D = 674 CEFBS_None, // FTINTRZ_W_S = 675 CEFBS_None, // FTINT_L_D = 676 CEFBS_None, // FTINT_L_S = 677 CEFBS_None, // FTINT_W_D = 678 CEFBS_None, // FTINT_W_S = 679 CEFBS_None, // GCSRRD = 680 CEFBS_None, // GCSRWR = 681 CEFBS_None, // GCSRXCHG = 682 CEFBS_None, // GTLBFLUSH = 683 CEFBS_None, // HVCL = 684 CEFBS_None, // IBAR = 685 CEFBS_None, // IDLE = 686 CEFBS_None, // INVTLB = 687 CEFBS_None, // IOCSRRD_B = 688 CEFBS_IsLA64, // IOCSRRD_D = 689 CEFBS_None, // IOCSRRD_H = 690 CEFBS_None, // IOCSRRD_W = 691 CEFBS_None, // IOCSRWR_B = 692 CEFBS_IsLA64, // IOCSRWR_D = 693 CEFBS_None, // IOCSRWR_H = 694 CEFBS_None, // IOCSRWR_W = 695 CEFBS_None, // JIRL = 696 CEFBS_None, // JISCR0 = 697 CEFBS_None, // JISCR1 = 698 CEFBS_None, // LDDIR = 699 CEFBS_IsLA64, // LDGT_B = 700 CEFBS_IsLA64, // LDGT_D = 701 CEFBS_IsLA64, // LDGT_H = 702 CEFBS_IsLA64, // LDGT_W = 703 CEFBS_IsLA64, // LDLE_B = 704 CEFBS_IsLA64, // LDLE_D = 705 CEFBS_IsLA64, // LDLE_H = 706 CEFBS_IsLA64, // LDLE_W = 707 CEFBS_IsLA64, // LDL_D = 708 CEFBS_None, // LDL_W = 709 CEFBS_None, // LDPTE = 710 CEFBS_IsLA64, // LDPTR_D = 711 CEFBS_IsLA64, // LDPTR_W = 712 CEFBS_IsLA64, // LDR_D = 713 CEFBS_None, // LDR_W = 714 CEFBS_IsLA64, // LDX_B = 715 CEFBS_IsLA64, // LDX_BU = 716 CEFBS_IsLA64, // LDX_D = 717 CEFBS_IsLA64, // LDX_H = 718 CEFBS_IsLA64, // LDX_HU = 719 CEFBS_IsLA64, // LDX_W = 720 CEFBS_IsLA64, // LDX_WU = 721 CEFBS_None, // LD_B = 722 CEFBS_None, // LD_BU = 723 CEFBS_IsLA64, // LD_D = 724 CEFBS_None, // LD_H = 725 CEFBS_None, // LD_HU = 726 CEFBS_None, // LD_W = 727 CEFBS_IsLA64, // LD_WU = 728 CEFBS_IsLA64, // LLACQ_D = 729 CEFBS_None, // LLACQ_W = 730 CEFBS_IsLA64, // LL_D = 731 CEFBS_None, // LL_W = 732 CEFBS_None, // LU12I_W = 733 CEFBS_IsLA64, // LU32I_D = 734 CEFBS_IsLA64, // LU52I_D = 735 CEFBS_None, // MASKEQZ = 736 CEFBS_None, // MASKNEZ = 737 CEFBS_IsLA64, // MOD_D = 738 CEFBS_IsLA64, // MOD_DU = 739 CEFBS_None, // MOD_W = 740 CEFBS_None, // MOD_WU = 741 CEFBS_None, // MOVCF2FR_xS = 742 CEFBS_None, // MOVCF2GR = 743 CEFBS_None, // MOVFCSR2GR = 744 CEFBS_None, // MOVFR2CF_xS = 745 CEFBS_IsLA64, // MOVFR2GR_D = 746 CEFBS_None, // MOVFR2GR_S = 747 CEFBS_None, // MOVFR2GR_S_64 = 748 CEFBS_None, // MOVFRH2GR_S = 749 CEFBS_None, // MOVGR2CF = 750 CEFBS_None, // MOVGR2FCSR = 751 CEFBS_None, // MOVGR2FRH_W = 752 CEFBS_IsLA64, // MOVGR2FR_D = 753 CEFBS_None, // MOVGR2FR_W = 754 CEFBS_IsLA32, // MOVGR2FR_W_64 = 755 CEFBS_None, // MOVGR2SCR = 756 CEFBS_None, // MOVSCR2GR = 757 CEFBS_IsLA64, // MULH_D = 758 CEFBS_IsLA64, // MULH_DU = 759 CEFBS_None, // MULH_W = 760 CEFBS_None, // MULH_WU = 761 CEFBS_IsLA64, // MULW_D_W = 762 CEFBS_IsLA64, // MULW_D_WU = 763 CEFBS_IsLA64, // MUL_D = 764 CEFBS_None, // MUL_W = 765 CEFBS_None, // NOR = 766 CEFBS_None, // OR = 767 CEFBS_None, // ORI = 768 CEFBS_None, // ORN = 769 CEFBS_None, // PCADDI = 770 CEFBS_None, // PCADDU12I = 771 CEFBS_IsLA64, // PCADDU18I = 772 CEFBS_None, // PCALAU12I = 773 CEFBS_None, // PRELD = 774 CEFBS_IsLA64, // PRELDX = 775 CEFBS_None, // RCRI_B = 776 CEFBS_IsLA64, // RCRI_D = 777 CEFBS_None, // RCRI_H = 778 CEFBS_None, // RCRI_W = 779 CEFBS_None, // RCR_B = 780 CEFBS_IsLA64, // RCR_D = 781 CEFBS_None, // RCR_H = 782 CEFBS_None, // RCR_W = 783 CEFBS_None, // RDTIMEH_W = 784 CEFBS_None, // RDTIMEL_W = 785 CEFBS_IsLA64, // RDTIME_D = 786 CEFBS_None, // REVB_2H = 787 CEFBS_IsLA64, // REVB_2W = 788 CEFBS_IsLA64, // REVB_4H = 789 CEFBS_IsLA64, // REVB_D = 790 CEFBS_IsLA64, // REVH_2W = 791 CEFBS_IsLA64, // REVH_D = 792 CEFBS_None, // ROTRI_B = 793 CEFBS_IsLA64, // ROTRI_D = 794 CEFBS_None, // ROTRI_H = 795 CEFBS_None, // ROTRI_W = 796 CEFBS_None, // ROTR_B = 797 CEFBS_IsLA64, // ROTR_D = 798 CEFBS_None, // ROTR_H = 799 CEFBS_None, // ROTR_W = 800 CEFBS_None, // SBC_B = 801 CEFBS_IsLA64, // SBC_D = 802 CEFBS_None, // SBC_H = 803 CEFBS_None, // SBC_W = 804 CEFBS_IsLA64, // SCREL_D = 805 CEFBS_None, // SCREL_W = 806 CEFBS_IsLA64, // SC_D = 807 CEFBS_IsLA64, // SC_Q = 808 CEFBS_None, // SC_W = 809 CEFBS_None, // SETARMJ = 810 CEFBS_None, // SETX86J = 811 CEFBS_None, // SETX86LOOPE = 812 CEFBS_None, // SETX86LOOPNE = 813 CEFBS_None, // SET_CFR_FALSE = 814 CEFBS_None, // SET_CFR_TRUE = 815 CEFBS_IsLA64, // SLLI_D = 816 CEFBS_None, // SLLI_W = 817 CEFBS_IsLA64, // SLL_D = 818 CEFBS_None, // SLL_W = 819 CEFBS_None, // SLT = 820 CEFBS_None, // SLTI = 821 CEFBS_None, // SLTU = 822 CEFBS_None, // SLTUI = 823 CEFBS_IsLA64, // SRAI_D = 824 CEFBS_None, // SRAI_W = 825 CEFBS_IsLA64, // SRA_D = 826 CEFBS_None, // SRA_W = 827 CEFBS_IsLA64, // SRLI_D = 828 CEFBS_None, // SRLI_W = 829 CEFBS_IsLA64, // SRL_D = 830 CEFBS_None, // SRL_W = 831 CEFBS_IsLA64, // STGT_B = 832 CEFBS_IsLA64, // STGT_D = 833 CEFBS_IsLA64, // STGT_H = 834 CEFBS_IsLA64, // STGT_W = 835 CEFBS_IsLA64, // STLE_B = 836 CEFBS_IsLA64, // STLE_D = 837 CEFBS_IsLA64, // STLE_H = 838 CEFBS_IsLA64, // STLE_W = 839 CEFBS_IsLA64, // STL_D = 840 CEFBS_None, // STL_W = 841 CEFBS_IsLA64, // STPTR_D = 842 CEFBS_IsLA64, // STPTR_W = 843 CEFBS_IsLA64, // STR_D = 844 CEFBS_None, // STR_W = 845 CEFBS_IsLA64, // STX_B = 846 CEFBS_IsLA64, // STX_D = 847 CEFBS_IsLA64, // STX_H = 848 CEFBS_IsLA64, // STX_W = 849 CEFBS_None, // ST_B = 850 CEFBS_IsLA64, // ST_D = 851 CEFBS_None, // ST_H = 852 CEFBS_None, // ST_W = 853 CEFBS_IsLA64, // SUB_D = 854 CEFBS_None, // SUB_W = 855 CEFBS_None, // SYSCALL = 856 CEFBS_None, // TLBCLR = 857 CEFBS_None, // TLBFILL = 858 CEFBS_None, // TLBFLUSH = 859 CEFBS_None, // TLBRD = 860 CEFBS_None, // TLBSRCH = 861 CEFBS_None, // TLBWR = 862 CEFBS_None, // VABSD_B = 863 CEFBS_None, // VABSD_BU = 864 CEFBS_None, // VABSD_D = 865 CEFBS_None, // VABSD_DU = 866 CEFBS_None, // VABSD_H = 867 CEFBS_None, // VABSD_HU = 868 CEFBS_None, // VABSD_W = 869 CEFBS_None, // VABSD_WU = 870 CEFBS_None, // VADDA_B = 871 CEFBS_None, // VADDA_D = 872 CEFBS_None, // VADDA_H = 873 CEFBS_None, // VADDA_W = 874 CEFBS_None, // VADDI_BU = 875 CEFBS_None, // VADDI_DU = 876 CEFBS_None, // VADDI_HU = 877 CEFBS_None, // VADDI_WU = 878 CEFBS_None, // VADDWEV_D_W = 879 CEFBS_None, // VADDWEV_D_WU = 880 CEFBS_None, // VADDWEV_D_WU_W = 881 CEFBS_None, // VADDWEV_H_B = 882 CEFBS_None, // VADDWEV_H_BU = 883 CEFBS_None, // VADDWEV_H_BU_B = 884 CEFBS_None, // VADDWEV_Q_D = 885 CEFBS_None, // VADDWEV_Q_DU = 886 CEFBS_None, // VADDWEV_Q_DU_D = 887 CEFBS_None, // VADDWEV_W_H = 888 CEFBS_None, // VADDWEV_W_HU = 889 CEFBS_None, // VADDWEV_W_HU_H = 890 CEFBS_None, // VADDWOD_D_W = 891 CEFBS_None, // VADDWOD_D_WU = 892 CEFBS_None, // VADDWOD_D_WU_W = 893 CEFBS_None, // VADDWOD_H_B = 894 CEFBS_None, // VADDWOD_H_BU = 895 CEFBS_None, // VADDWOD_H_BU_B = 896 CEFBS_None, // VADDWOD_Q_D = 897 CEFBS_None, // VADDWOD_Q_DU = 898 CEFBS_None, // VADDWOD_Q_DU_D = 899 CEFBS_None, // VADDWOD_W_H = 900 CEFBS_None, // VADDWOD_W_HU = 901 CEFBS_None, // VADDWOD_W_HU_H = 902 CEFBS_None, // VADD_B = 903 CEFBS_None, // VADD_D = 904 CEFBS_None, // VADD_H = 905 CEFBS_None, // VADD_Q = 906 CEFBS_None, // VADD_W = 907 CEFBS_None, // VANDI_B = 908 CEFBS_None, // VANDN_V = 909 CEFBS_None, // VAND_V = 910 CEFBS_None, // VAVGR_B = 911 CEFBS_None, // VAVGR_BU = 912 CEFBS_None, // VAVGR_D = 913 CEFBS_None, // VAVGR_DU = 914 CEFBS_None, // VAVGR_H = 915 CEFBS_None, // VAVGR_HU = 916 CEFBS_None, // VAVGR_W = 917 CEFBS_None, // VAVGR_WU = 918 CEFBS_None, // VAVG_B = 919 CEFBS_None, // VAVG_BU = 920 CEFBS_None, // VAVG_D = 921 CEFBS_None, // VAVG_DU = 922 CEFBS_None, // VAVG_H = 923 CEFBS_None, // VAVG_HU = 924 CEFBS_None, // VAVG_W = 925 CEFBS_None, // VAVG_WU = 926 CEFBS_None, // VBITCLRI_B = 927 CEFBS_None, // VBITCLRI_D = 928 CEFBS_None, // VBITCLRI_H = 929 CEFBS_None, // VBITCLRI_W = 930 CEFBS_None, // VBITCLR_B = 931 CEFBS_None, // VBITCLR_D = 932 CEFBS_None, // VBITCLR_H = 933 CEFBS_None, // VBITCLR_W = 934 CEFBS_None, // VBITREVI_B = 935 CEFBS_None, // VBITREVI_D = 936 CEFBS_None, // VBITREVI_H = 937 CEFBS_None, // VBITREVI_W = 938 CEFBS_None, // VBITREV_B = 939 CEFBS_None, // VBITREV_D = 940 CEFBS_None, // VBITREV_H = 941 CEFBS_None, // VBITREV_W = 942 CEFBS_None, // VBITSELI_B = 943 CEFBS_None, // VBITSEL_V = 944 CEFBS_None, // VBITSETI_B = 945 CEFBS_None, // VBITSETI_D = 946 CEFBS_None, // VBITSETI_H = 947 CEFBS_None, // VBITSETI_W = 948 CEFBS_None, // VBITSET_B = 949 CEFBS_None, // VBITSET_D = 950 CEFBS_None, // VBITSET_H = 951 CEFBS_None, // VBITSET_W = 952 CEFBS_None, // VBSLL_V = 953 CEFBS_None, // VBSRL_V = 954 CEFBS_None, // VCLO_B = 955 CEFBS_None, // VCLO_D = 956 CEFBS_None, // VCLO_H = 957 CEFBS_None, // VCLO_W = 958 CEFBS_None, // VCLZ_B = 959 CEFBS_None, // VCLZ_D = 960 CEFBS_None, // VCLZ_H = 961 CEFBS_None, // VCLZ_W = 962 CEFBS_None, // VDIV_B = 963 CEFBS_None, // VDIV_BU = 964 CEFBS_None, // VDIV_D = 965 CEFBS_None, // VDIV_DU = 966 CEFBS_None, // VDIV_H = 967 CEFBS_None, // VDIV_HU = 968 CEFBS_None, // VDIV_W = 969 CEFBS_None, // VDIV_WU = 970 CEFBS_None, // VEXT2XV_DU_BU = 971 CEFBS_None, // VEXT2XV_DU_HU = 972 CEFBS_None, // VEXT2XV_DU_WU = 973 CEFBS_None, // VEXT2XV_D_B = 974 CEFBS_None, // VEXT2XV_D_H = 975 CEFBS_None, // VEXT2XV_D_W = 976 CEFBS_None, // VEXT2XV_HU_BU = 977 CEFBS_None, // VEXT2XV_H_B = 978 CEFBS_None, // VEXT2XV_WU_BU = 979 CEFBS_None, // VEXT2XV_WU_HU = 980 CEFBS_None, // VEXT2XV_W_B = 981 CEFBS_None, // VEXT2XV_W_H = 982 CEFBS_None, // VEXTH_DU_WU = 983 CEFBS_None, // VEXTH_D_W = 984 CEFBS_None, // VEXTH_HU_BU = 985 CEFBS_None, // VEXTH_H_B = 986 CEFBS_None, // VEXTH_QU_DU = 987 CEFBS_None, // VEXTH_Q_D = 988 CEFBS_None, // VEXTH_WU_HU = 989 CEFBS_None, // VEXTH_W_H = 990 CEFBS_None, // VEXTL_QU_DU = 991 CEFBS_None, // VEXTL_Q_D = 992 CEFBS_None, // VEXTRINS_B = 993 CEFBS_None, // VEXTRINS_D = 994 CEFBS_None, // VEXTRINS_H = 995 CEFBS_None, // VEXTRINS_W = 996 CEFBS_None, // VFADD_D = 997 CEFBS_None, // VFADD_S = 998 CEFBS_None, // VFCLASS_D = 999 CEFBS_None, // VFCLASS_S = 1000 CEFBS_None, // VFCMP_CAF_D = 1001 CEFBS_None, // VFCMP_CAF_S = 1002 CEFBS_None, // VFCMP_CEQ_D = 1003 CEFBS_None, // VFCMP_CEQ_S = 1004 CEFBS_None, // VFCMP_CLE_D = 1005 CEFBS_None, // VFCMP_CLE_S = 1006 CEFBS_None, // VFCMP_CLT_D = 1007 CEFBS_None, // VFCMP_CLT_S = 1008 CEFBS_None, // VFCMP_CNE_D = 1009 CEFBS_None, // VFCMP_CNE_S = 1010 CEFBS_None, // VFCMP_COR_D = 1011 CEFBS_None, // VFCMP_COR_S = 1012 CEFBS_None, // VFCMP_CUEQ_D = 1013 CEFBS_None, // VFCMP_CUEQ_S = 1014 CEFBS_None, // VFCMP_CULE_D = 1015 CEFBS_None, // VFCMP_CULE_S = 1016 CEFBS_None, // VFCMP_CULT_D = 1017 CEFBS_None, // VFCMP_CULT_S = 1018 CEFBS_None, // VFCMP_CUNE_D = 1019 CEFBS_None, // VFCMP_CUNE_S = 1020 CEFBS_None, // VFCMP_CUN_D = 1021 CEFBS_None, // VFCMP_CUN_S = 1022 CEFBS_None, // VFCMP_SAF_D = 1023 CEFBS_None, // VFCMP_SAF_S = 1024 CEFBS_None, // VFCMP_SEQ_D = 1025 CEFBS_None, // VFCMP_SEQ_S = 1026 CEFBS_None, // VFCMP_SLE_D = 1027 CEFBS_None, // VFCMP_SLE_S = 1028 CEFBS_None, // VFCMP_SLT_D = 1029 CEFBS_None, // VFCMP_SLT_S = 1030 CEFBS_None, // VFCMP_SNE_D = 1031 CEFBS_None, // VFCMP_SNE_S = 1032 CEFBS_None, // VFCMP_SOR_D = 1033 CEFBS_None, // VFCMP_SOR_S = 1034 CEFBS_None, // VFCMP_SUEQ_D = 1035 CEFBS_None, // VFCMP_SUEQ_S = 1036 CEFBS_None, // VFCMP_SULE_D = 1037 CEFBS_None, // VFCMP_SULE_S = 1038 CEFBS_None, // VFCMP_SULT_D = 1039 CEFBS_None, // VFCMP_SULT_S = 1040 CEFBS_None, // VFCMP_SUNE_D = 1041 CEFBS_None, // VFCMP_SUNE_S = 1042 CEFBS_None, // VFCMP_SUN_D = 1043 CEFBS_None, // VFCMP_SUN_S = 1044 CEFBS_None, // VFCVTH_D_S = 1045 CEFBS_None, // VFCVTH_S_H = 1046 CEFBS_None, // VFCVTL_D_S = 1047 CEFBS_None, // VFCVTL_S_H = 1048 CEFBS_None, // VFCVT_H_S = 1049 CEFBS_None, // VFCVT_S_D = 1050 CEFBS_None, // VFDIV_D = 1051 CEFBS_None, // VFDIV_S = 1052 CEFBS_None, // VFFINTH_D_W = 1053 CEFBS_None, // VFFINTL_D_W = 1054 CEFBS_None, // VFFINT_D_L = 1055 CEFBS_None, // VFFINT_D_LU = 1056 CEFBS_None, // VFFINT_S_L = 1057 CEFBS_None, // VFFINT_S_W = 1058 CEFBS_None, // VFFINT_S_WU = 1059 CEFBS_None, // VFLOGB_D = 1060 CEFBS_None, // VFLOGB_S = 1061 CEFBS_None, // VFMADD_D = 1062 CEFBS_None, // VFMADD_S = 1063 CEFBS_None, // VFMAXA_D = 1064 CEFBS_None, // VFMAXA_S = 1065 CEFBS_None, // VFMAX_D = 1066 CEFBS_None, // VFMAX_S = 1067 CEFBS_None, // VFMINA_D = 1068 CEFBS_None, // VFMINA_S = 1069 CEFBS_None, // VFMIN_D = 1070 CEFBS_None, // VFMIN_S = 1071 CEFBS_None, // VFMSUB_D = 1072 CEFBS_None, // VFMSUB_S = 1073 CEFBS_None, // VFMUL_D = 1074 CEFBS_None, // VFMUL_S = 1075 CEFBS_None, // VFNMADD_D = 1076 CEFBS_None, // VFNMADD_S = 1077 CEFBS_None, // VFNMSUB_D = 1078 CEFBS_None, // VFNMSUB_S = 1079 CEFBS_None, // VFRECIPE_D = 1080 CEFBS_None, // VFRECIPE_S = 1081 CEFBS_None, // VFRECIP_D = 1082 CEFBS_None, // VFRECIP_S = 1083 CEFBS_None, // VFRINTRM_D = 1084 CEFBS_None, // VFRINTRM_S = 1085 CEFBS_None, // VFRINTRNE_D = 1086 CEFBS_None, // VFRINTRNE_S = 1087 CEFBS_None, // VFRINTRP_D = 1088 CEFBS_None, // VFRINTRP_S = 1089 CEFBS_None, // VFRINTRZ_D = 1090 CEFBS_None, // VFRINTRZ_S = 1091 CEFBS_None, // VFRINT_D = 1092 CEFBS_None, // VFRINT_S = 1093 CEFBS_None, // VFRSQRTE_D = 1094 CEFBS_None, // VFRSQRTE_S = 1095 CEFBS_None, // VFRSQRT_D = 1096 CEFBS_None, // VFRSQRT_S = 1097 CEFBS_None, // VFRSTPI_B = 1098 CEFBS_None, // VFRSTPI_H = 1099 CEFBS_None, // VFRSTP_B = 1100 CEFBS_None, // VFRSTP_H = 1101 CEFBS_None, // VFSQRT_D = 1102 CEFBS_None, // VFSQRT_S = 1103 CEFBS_None, // VFSUB_D = 1104 CEFBS_None, // VFSUB_S = 1105 CEFBS_None, // VFTINTH_L_S = 1106 CEFBS_None, // VFTINTL_L_S = 1107 CEFBS_None, // VFTINTRMH_L_S = 1108 CEFBS_None, // VFTINTRML_L_S = 1109 CEFBS_None, // VFTINTRM_L_D = 1110 CEFBS_None, // VFTINTRM_W_D = 1111 CEFBS_None, // VFTINTRM_W_S = 1112 CEFBS_None, // VFTINTRNEH_L_S = 1113 CEFBS_None, // VFTINTRNEL_L_S = 1114 CEFBS_None, // VFTINTRNE_L_D = 1115 CEFBS_None, // VFTINTRNE_W_D = 1116 CEFBS_None, // VFTINTRNE_W_S = 1117 CEFBS_None, // VFTINTRPH_L_S = 1118 CEFBS_None, // VFTINTRPL_L_S = 1119 CEFBS_None, // VFTINTRP_L_D = 1120 CEFBS_None, // VFTINTRP_W_D = 1121 CEFBS_None, // VFTINTRP_W_S = 1122 CEFBS_None, // VFTINTRZH_L_S = 1123 CEFBS_None, // VFTINTRZL_L_S = 1124 CEFBS_None, // VFTINTRZ_LU_D = 1125 CEFBS_None, // VFTINTRZ_L_D = 1126 CEFBS_None, // VFTINTRZ_WU_S = 1127 CEFBS_None, // VFTINTRZ_W_D = 1128 CEFBS_None, // VFTINTRZ_W_S = 1129 CEFBS_None, // VFTINT_LU_D = 1130 CEFBS_None, // VFTINT_L_D = 1131 CEFBS_None, // VFTINT_WU_S = 1132 CEFBS_None, // VFTINT_W_D = 1133 CEFBS_None, // VFTINT_W_S = 1134 CEFBS_None, // VHADDW_DU_WU = 1135 CEFBS_None, // VHADDW_D_W = 1136 CEFBS_None, // VHADDW_HU_BU = 1137 CEFBS_None, // VHADDW_H_B = 1138 CEFBS_None, // VHADDW_QU_DU = 1139 CEFBS_None, // VHADDW_Q_D = 1140 CEFBS_None, // VHADDW_WU_HU = 1141 CEFBS_None, // VHADDW_W_H = 1142 CEFBS_None, // VHSUBW_DU_WU = 1143 CEFBS_None, // VHSUBW_D_W = 1144 CEFBS_None, // VHSUBW_HU_BU = 1145 CEFBS_None, // VHSUBW_H_B = 1146 CEFBS_None, // VHSUBW_QU_DU = 1147 CEFBS_None, // VHSUBW_Q_D = 1148 CEFBS_None, // VHSUBW_WU_HU = 1149 CEFBS_None, // VHSUBW_W_H = 1150 CEFBS_None, // VILVH_B = 1151 CEFBS_None, // VILVH_D = 1152 CEFBS_None, // VILVH_H = 1153 CEFBS_None, // VILVH_W = 1154 CEFBS_None, // VILVL_B = 1155 CEFBS_None, // VILVL_D = 1156 CEFBS_None, // VILVL_H = 1157 CEFBS_None, // VILVL_W = 1158 CEFBS_None, // VINSGR2VR_B = 1159 CEFBS_None, // VINSGR2VR_D = 1160 CEFBS_None, // VINSGR2VR_H = 1161 CEFBS_None, // VINSGR2VR_W = 1162 CEFBS_None, // VLD = 1163 CEFBS_None, // VLDI = 1164 CEFBS_None, // VLDREPL_B = 1165 CEFBS_None, // VLDREPL_D = 1166 CEFBS_None, // VLDREPL_H = 1167 CEFBS_None, // VLDREPL_W = 1168 CEFBS_None, // VLDX = 1169 CEFBS_None, // VMADDWEV_D_W = 1170 CEFBS_None, // VMADDWEV_D_WU = 1171 CEFBS_None, // VMADDWEV_D_WU_W = 1172 CEFBS_None, // VMADDWEV_H_B = 1173 CEFBS_None, // VMADDWEV_H_BU = 1174 CEFBS_None, // VMADDWEV_H_BU_B = 1175 CEFBS_None, // VMADDWEV_Q_D = 1176 CEFBS_None, // VMADDWEV_Q_DU = 1177 CEFBS_None, // VMADDWEV_Q_DU_D = 1178 CEFBS_None, // VMADDWEV_W_H = 1179 CEFBS_None, // VMADDWEV_W_HU = 1180 CEFBS_None, // VMADDWEV_W_HU_H = 1181 CEFBS_None, // VMADDWOD_D_W = 1182 CEFBS_None, // VMADDWOD_D_WU = 1183 CEFBS_None, // VMADDWOD_D_WU_W = 1184 CEFBS_None, // VMADDWOD_H_B = 1185 CEFBS_None, // VMADDWOD_H_BU = 1186 CEFBS_None, // VMADDWOD_H_BU_B = 1187 CEFBS_None, // VMADDWOD_Q_D = 1188 CEFBS_None, // VMADDWOD_Q_DU = 1189 CEFBS_None, // VMADDWOD_Q_DU_D = 1190 CEFBS_None, // VMADDWOD_W_H = 1191 CEFBS_None, // VMADDWOD_W_HU = 1192 CEFBS_None, // VMADDWOD_W_HU_H = 1193 CEFBS_None, // VMADD_B = 1194 CEFBS_None, // VMADD_D = 1195 CEFBS_None, // VMADD_H = 1196 CEFBS_None, // VMADD_W = 1197 CEFBS_None, // VMAXI_B = 1198 CEFBS_None, // VMAXI_BU = 1199 CEFBS_None, // VMAXI_D = 1200 CEFBS_None, // VMAXI_DU = 1201 CEFBS_None, // VMAXI_H = 1202 CEFBS_None, // VMAXI_HU = 1203 CEFBS_None, // VMAXI_W = 1204 CEFBS_None, // VMAXI_WU = 1205 CEFBS_None, // VMAX_B = 1206 CEFBS_None, // VMAX_BU = 1207 CEFBS_None, // VMAX_D = 1208 CEFBS_None, // VMAX_DU = 1209 CEFBS_None, // VMAX_H = 1210 CEFBS_None, // VMAX_HU = 1211 CEFBS_None, // VMAX_W = 1212 CEFBS_None, // VMAX_WU = 1213 CEFBS_None, // VMINI_B = 1214 CEFBS_None, // VMINI_BU = 1215 CEFBS_None, // VMINI_D = 1216 CEFBS_None, // VMINI_DU = 1217 CEFBS_None, // VMINI_H = 1218 CEFBS_None, // VMINI_HU = 1219 CEFBS_None, // VMINI_W = 1220 CEFBS_None, // VMINI_WU = 1221 CEFBS_None, // VMIN_B = 1222 CEFBS_None, // VMIN_BU = 1223 CEFBS_None, // VMIN_D = 1224 CEFBS_None, // VMIN_DU = 1225 CEFBS_None, // VMIN_H = 1226 CEFBS_None, // VMIN_HU = 1227 CEFBS_None, // VMIN_W = 1228 CEFBS_None, // VMIN_WU = 1229 CEFBS_None, // VMOD_B = 1230 CEFBS_None, // VMOD_BU = 1231 CEFBS_None, // VMOD_D = 1232 CEFBS_None, // VMOD_DU = 1233 CEFBS_None, // VMOD_H = 1234 CEFBS_None, // VMOD_HU = 1235 CEFBS_None, // VMOD_W = 1236 CEFBS_None, // VMOD_WU = 1237 CEFBS_None, // VMSKGEZ_B = 1238 CEFBS_None, // VMSKLTZ_B = 1239 CEFBS_None, // VMSKLTZ_D = 1240 CEFBS_None, // VMSKLTZ_H = 1241 CEFBS_None, // VMSKLTZ_W = 1242 CEFBS_None, // VMSKNZ_B = 1243 CEFBS_None, // VMSUB_B = 1244 CEFBS_None, // VMSUB_D = 1245 CEFBS_None, // VMSUB_H = 1246 CEFBS_None, // VMSUB_W = 1247 CEFBS_None, // VMUH_B = 1248 CEFBS_None, // VMUH_BU = 1249 CEFBS_None, // VMUH_D = 1250 CEFBS_None, // VMUH_DU = 1251 CEFBS_None, // VMUH_H = 1252 CEFBS_None, // VMUH_HU = 1253 CEFBS_None, // VMUH_W = 1254 CEFBS_None, // VMUH_WU = 1255 CEFBS_None, // VMULWEV_D_W = 1256 CEFBS_None, // VMULWEV_D_WU = 1257 CEFBS_None, // VMULWEV_D_WU_W = 1258 CEFBS_None, // VMULWEV_H_B = 1259 CEFBS_None, // VMULWEV_H_BU = 1260 CEFBS_None, // VMULWEV_H_BU_B = 1261 CEFBS_None, // VMULWEV_Q_D = 1262 CEFBS_None, // VMULWEV_Q_DU = 1263 CEFBS_None, // VMULWEV_Q_DU_D = 1264 CEFBS_None, // VMULWEV_W_H = 1265 CEFBS_None, // VMULWEV_W_HU = 1266 CEFBS_None, // VMULWEV_W_HU_H = 1267 CEFBS_None, // VMULWOD_D_W = 1268 CEFBS_None, // VMULWOD_D_WU = 1269 CEFBS_None, // VMULWOD_D_WU_W = 1270 CEFBS_None, // VMULWOD_H_B = 1271 CEFBS_None, // VMULWOD_H_BU = 1272 CEFBS_None, // VMULWOD_H_BU_B = 1273 CEFBS_None, // VMULWOD_Q_D = 1274 CEFBS_None, // VMULWOD_Q_DU = 1275 CEFBS_None, // VMULWOD_Q_DU_D = 1276 CEFBS_None, // VMULWOD_W_H = 1277 CEFBS_None, // VMULWOD_W_HU = 1278 CEFBS_None, // VMULWOD_W_HU_H = 1279 CEFBS_None, // VMUL_B = 1280 CEFBS_None, // VMUL_D = 1281 CEFBS_None, // VMUL_H = 1282 CEFBS_None, // VMUL_W = 1283 CEFBS_None, // VNEG_B = 1284 CEFBS_None, // VNEG_D = 1285 CEFBS_None, // VNEG_H = 1286 CEFBS_None, // VNEG_W = 1287 CEFBS_None, // VNORI_B = 1288 CEFBS_None, // VNOR_V = 1289 CEFBS_None, // VORI_B = 1290 CEFBS_None, // VORN_V = 1291 CEFBS_None, // VOR_V = 1292 CEFBS_None, // VPACKEV_B = 1293 CEFBS_None, // VPACKEV_D = 1294 CEFBS_None, // VPACKEV_H = 1295 CEFBS_None, // VPACKEV_W = 1296 CEFBS_None, // VPACKOD_B = 1297 CEFBS_None, // VPACKOD_D = 1298 CEFBS_None, // VPACKOD_H = 1299 CEFBS_None, // VPACKOD_W = 1300 CEFBS_None, // VPCNT_B = 1301 CEFBS_None, // VPCNT_D = 1302 CEFBS_None, // VPCNT_H = 1303 CEFBS_None, // VPCNT_W = 1304 CEFBS_None, // VPERMI_W = 1305 CEFBS_None, // VPICKEV_B = 1306 CEFBS_None, // VPICKEV_D = 1307 CEFBS_None, // VPICKEV_H = 1308 CEFBS_None, // VPICKEV_W = 1309 CEFBS_None, // VPICKOD_B = 1310 CEFBS_None, // VPICKOD_D = 1311 CEFBS_None, // VPICKOD_H = 1312 CEFBS_None, // VPICKOD_W = 1313 CEFBS_None, // VPICKVE2GR_B = 1314 CEFBS_None, // VPICKVE2GR_BU = 1315 CEFBS_None, // VPICKVE2GR_D = 1316 CEFBS_None, // VPICKVE2GR_DU = 1317 CEFBS_None, // VPICKVE2GR_H = 1318 CEFBS_None, // VPICKVE2GR_HU = 1319 CEFBS_None, // VPICKVE2GR_W = 1320 CEFBS_None, // VPICKVE2GR_WU = 1321 CEFBS_None, // VREPLGR2VR_B = 1322 CEFBS_None, // VREPLGR2VR_D = 1323 CEFBS_None, // VREPLGR2VR_H = 1324 CEFBS_None, // VREPLGR2VR_W = 1325 CEFBS_None, // VREPLVEI_B = 1326 CEFBS_None, // VREPLVEI_D = 1327 CEFBS_None, // VREPLVEI_H = 1328 CEFBS_None, // VREPLVEI_W = 1329 CEFBS_None, // VREPLVE_B = 1330 CEFBS_None, // VREPLVE_D = 1331 CEFBS_None, // VREPLVE_H = 1332 CEFBS_None, // VREPLVE_W = 1333 CEFBS_None, // VROTRI_B = 1334 CEFBS_None, // VROTRI_D = 1335 CEFBS_None, // VROTRI_H = 1336 CEFBS_None, // VROTRI_W = 1337 CEFBS_None, // VROTR_B = 1338 CEFBS_None, // VROTR_D = 1339 CEFBS_None, // VROTR_H = 1340 CEFBS_None, // VROTR_W = 1341 CEFBS_None, // VSADD_B = 1342 CEFBS_None, // VSADD_BU = 1343 CEFBS_None, // VSADD_D = 1344 CEFBS_None, // VSADD_DU = 1345 CEFBS_None, // VSADD_H = 1346 CEFBS_None, // VSADD_HU = 1347 CEFBS_None, // VSADD_W = 1348 CEFBS_None, // VSADD_WU = 1349 CEFBS_None, // VSAT_B = 1350 CEFBS_None, // VSAT_BU = 1351 CEFBS_None, // VSAT_D = 1352 CEFBS_None, // VSAT_DU = 1353 CEFBS_None, // VSAT_H = 1354 CEFBS_None, // VSAT_HU = 1355 CEFBS_None, // VSAT_W = 1356 CEFBS_None, // VSAT_WU = 1357 CEFBS_None, // VSEQI_B = 1358 CEFBS_None, // VSEQI_D = 1359 CEFBS_None, // VSEQI_H = 1360 CEFBS_None, // VSEQI_W = 1361 CEFBS_None, // VSEQ_B = 1362 CEFBS_None, // VSEQ_D = 1363 CEFBS_None, // VSEQ_H = 1364 CEFBS_None, // VSEQ_W = 1365 CEFBS_None, // VSETALLNEZ_B = 1366 CEFBS_None, // VSETALLNEZ_D = 1367 CEFBS_None, // VSETALLNEZ_H = 1368 CEFBS_None, // VSETALLNEZ_W = 1369 CEFBS_None, // VSETANYEQZ_B = 1370 CEFBS_None, // VSETANYEQZ_D = 1371 CEFBS_None, // VSETANYEQZ_H = 1372 CEFBS_None, // VSETANYEQZ_W = 1373 CEFBS_None, // VSETEQZ_V = 1374 CEFBS_None, // VSETNEZ_V = 1375 CEFBS_None, // VSHUF4I_B = 1376 CEFBS_None, // VSHUF4I_D = 1377 CEFBS_None, // VSHUF4I_H = 1378 CEFBS_None, // VSHUF4I_W = 1379 CEFBS_None, // VSHUF_B = 1380 CEFBS_None, // VSHUF_D = 1381 CEFBS_None, // VSHUF_H = 1382 CEFBS_None, // VSHUF_W = 1383 CEFBS_None, // VSIGNCOV_B = 1384 CEFBS_None, // VSIGNCOV_D = 1385 CEFBS_None, // VSIGNCOV_H = 1386 CEFBS_None, // VSIGNCOV_W = 1387 CEFBS_None, // VSLEI_B = 1388 CEFBS_None, // VSLEI_BU = 1389 CEFBS_None, // VSLEI_D = 1390 CEFBS_None, // VSLEI_DU = 1391 CEFBS_None, // VSLEI_H = 1392 CEFBS_None, // VSLEI_HU = 1393 CEFBS_None, // VSLEI_W = 1394 CEFBS_None, // VSLEI_WU = 1395 CEFBS_None, // VSLE_B = 1396 CEFBS_None, // VSLE_BU = 1397 CEFBS_None, // VSLE_D = 1398 CEFBS_None, // VSLE_DU = 1399 CEFBS_None, // VSLE_H = 1400 CEFBS_None, // VSLE_HU = 1401 CEFBS_None, // VSLE_W = 1402 CEFBS_None, // VSLE_WU = 1403 CEFBS_None, // VSLLI_B = 1404 CEFBS_None, // VSLLI_D = 1405 CEFBS_None, // VSLLI_H = 1406 CEFBS_None, // VSLLI_W = 1407 CEFBS_None, // VSLLWIL_DU_WU = 1408 CEFBS_None, // VSLLWIL_D_W = 1409 CEFBS_None, // VSLLWIL_HU_BU = 1410 CEFBS_None, // VSLLWIL_H_B = 1411 CEFBS_None, // VSLLWIL_WU_HU = 1412 CEFBS_None, // VSLLWIL_W_H = 1413 CEFBS_None, // VSLL_B = 1414 CEFBS_None, // VSLL_D = 1415 CEFBS_None, // VSLL_H = 1416 CEFBS_None, // VSLL_W = 1417 CEFBS_None, // VSLTI_B = 1418 CEFBS_None, // VSLTI_BU = 1419 CEFBS_None, // VSLTI_D = 1420 CEFBS_None, // VSLTI_DU = 1421 CEFBS_None, // VSLTI_H = 1422 CEFBS_None, // VSLTI_HU = 1423 CEFBS_None, // VSLTI_W = 1424 CEFBS_None, // VSLTI_WU = 1425 CEFBS_None, // VSLT_B = 1426 CEFBS_None, // VSLT_BU = 1427 CEFBS_None, // VSLT_D = 1428 CEFBS_None, // VSLT_DU = 1429 CEFBS_None, // VSLT_H = 1430 CEFBS_None, // VSLT_HU = 1431 CEFBS_None, // VSLT_W = 1432 CEFBS_None, // VSLT_WU = 1433 CEFBS_None, // VSRAI_B = 1434 CEFBS_None, // VSRAI_D = 1435 CEFBS_None, // VSRAI_H = 1436 CEFBS_None, // VSRAI_W = 1437 CEFBS_None, // VSRANI_B_H = 1438 CEFBS_None, // VSRANI_D_Q = 1439 CEFBS_None, // VSRANI_H_W = 1440 CEFBS_None, // VSRANI_W_D = 1441 CEFBS_None, // VSRAN_B_H = 1442 CEFBS_None, // VSRAN_H_W = 1443 CEFBS_None, // VSRAN_W_D = 1444 CEFBS_None, // VSRARI_B = 1445 CEFBS_None, // VSRARI_D = 1446 CEFBS_None, // VSRARI_H = 1447 CEFBS_None, // VSRARI_W = 1448 CEFBS_None, // VSRARNI_B_H = 1449 CEFBS_None, // VSRARNI_D_Q = 1450 CEFBS_None, // VSRARNI_H_W = 1451 CEFBS_None, // VSRARNI_W_D = 1452 CEFBS_None, // VSRARN_B_H = 1453 CEFBS_None, // VSRARN_H_W = 1454 CEFBS_None, // VSRARN_W_D = 1455 CEFBS_None, // VSRAR_B = 1456 CEFBS_None, // VSRAR_D = 1457 CEFBS_None, // VSRAR_H = 1458 CEFBS_None, // VSRAR_W = 1459 CEFBS_None, // VSRA_B = 1460 CEFBS_None, // VSRA_D = 1461 CEFBS_None, // VSRA_H = 1462 CEFBS_None, // VSRA_W = 1463 CEFBS_None, // VSRLI_B = 1464 CEFBS_None, // VSRLI_D = 1465 CEFBS_None, // VSRLI_H = 1466 CEFBS_None, // VSRLI_W = 1467 CEFBS_None, // VSRLNI_B_H = 1468 CEFBS_None, // VSRLNI_D_Q = 1469 CEFBS_None, // VSRLNI_H_W = 1470 CEFBS_None, // VSRLNI_W_D = 1471 CEFBS_None, // VSRLN_B_H = 1472 CEFBS_None, // VSRLN_H_W = 1473 CEFBS_None, // VSRLN_W_D = 1474 CEFBS_None, // VSRLRI_B = 1475 CEFBS_None, // VSRLRI_D = 1476 CEFBS_None, // VSRLRI_H = 1477 CEFBS_None, // VSRLRI_W = 1478 CEFBS_None, // VSRLRNI_B_H = 1479 CEFBS_None, // VSRLRNI_D_Q = 1480 CEFBS_None, // VSRLRNI_H_W = 1481 CEFBS_None, // VSRLRNI_W_D = 1482 CEFBS_None, // VSRLRN_B_H = 1483 CEFBS_None, // VSRLRN_H_W = 1484 CEFBS_None, // VSRLRN_W_D = 1485 CEFBS_None, // VSRLR_B = 1486 CEFBS_None, // VSRLR_D = 1487 CEFBS_None, // VSRLR_H = 1488 CEFBS_None, // VSRLR_W = 1489 CEFBS_None, // VSRL_B = 1490 CEFBS_None, // VSRL_D = 1491 CEFBS_None, // VSRL_H = 1492 CEFBS_None, // VSRL_W = 1493 CEFBS_None, // VSSRANI_BU_H = 1494 CEFBS_None, // VSSRANI_B_H = 1495 CEFBS_None, // VSSRANI_DU_Q = 1496 CEFBS_None, // VSSRANI_D_Q = 1497 CEFBS_None, // VSSRANI_HU_W = 1498 CEFBS_None, // VSSRANI_H_W = 1499 CEFBS_None, // VSSRANI_WU_D = 1500 CEFBS_None, // VSSRANI_W_D = 1501 CEFBS_None, // VSSRAN_BU_H = 1502 CEFBS_None, // VSSRAN_B_H = 1503 CEFBS_None, // VSSRAN_HU_W = 1504 CEFBS_None, // VSSRAN_H_W = 1505 CEFBS_None, // VSSRAN_WU_D = 1506 CEFBS_None, // VSSRAN_W_D = 1507 CEFBS_None, // VSSRARNI_BU_H = 1508 CEFBS_None, // VSSRARNI_B_H = 1509 CEFBS_None, // VSSRARNI_DU_Q = 1510 CEFBS_None, // VSSRARNI_D_Q = 1511 CEFBS_None, // VSSRARNI_HU_W = 1512 CEFBS_None, // VSSRARNI_H_W = 1513 CEFBS_None, // VSSRARNI_WU_D = 1514 CEFBS_None, // VSSRARNI_W_D = 1515 CEFBS_None, // VSSRARN_BU_H = 1516 CEFBS_None, // VSSRARN_B_H = 1517 CEFBS_None, // VSSRARN_HU_W = 1518 CEFBS_None, // VSSRARN_H_W = 1519 CEFBS_None, // VSSRARN_WU_D = 1520 CEFBS_None, // VSSRARN_W_D = 1521 CEFBS_None, // VSSRLNI_BU_H = 1522 CEFBS_None, // VSSRLNI_B_H = 1523 CEFBS_None, // VSSRLNI_DU_Q = 1524 CEFBS_None, // VSSRLNI_D_Q = 1525 CEFBS_None, // VSSRLNI_HU_W = 1526 CEFBS_None, // VSSRLNI_H_W = 1527 CEFBS_None, // VSSRLNI_WU_D = 1528 CEFBS_None, // VSSRLNI_W_D = 1529 CEFBS_None, // VSSRLN_BU_H = 1530 CEFBS_None, // VSSRLN_B_H = 1531 CEFBS_None, // VSSRLN_HU_W = 1532 CEFBS_None, // VSSRLN_H_W = 1533 CEFBS_None, // VSSRLN_WU_D = 1534 CEFBS_None, // VSSRLN_W_D = 1535 CEFBS_None, // VSSRLRNI_BU_H = 1536 CEFBS_None, // VSSRLRNI_B_H = 1537 CEFBS_None, // VSSRLRNI_DU_Q = 1538 CEFBS_None, // VSSRLRNI_D_Q = 1539 CEFBS_None, // VSSRLRNI_HU_W = 1540 CEFBS_None, // VSSRLRNI_H_W = 1541 CEFBS_None, // VSSRLRNI_WU_D = 1542 CEFBS_None, // VSSRLRNI_W_D = 1543 CEFBS_None, // VSSRLRN_BU_H = 1544 CEFBS_None, // VSSRLRN_B_H = 1545 CEFBS_None, // VSSRLRN_HU_W = 1546 CEFBS_None, // VSSRLRN_H_W = 1547 CEFBS_None, // VSSRLRN_WU_D = 1548 CEFBS_None, // VSSRLRN_W_D = 1549 CEFBS_None, // VSSUB_B = 1550 CEFBS_None, // VSSUB_BU = 1551 CEFBS_None, // VSSUB_D = 1552 CEFBS_None, // VSSUB_DU = 1553 CEFBS_None, // VSSUB_H = 1554 CEFBS_None, // VSSUB_HU = 1555 CEFBS_None, // VSSUB_W = 1556 CEFBS_None, // VSSUB_WU = 1557 CEFBS_None, // VST = 1558 CEFBS_None, // VSTELM_B = 1559 CEFBS_None, // VSTELM_D = 1560 CEFBS_None, // VSTELM_H = 1561 CEFBS_None, // VSTELM_W = 1562 CEFBS_None, // VSTX = 1563 CEFBS_None, // VSUBI_BU = 1564 CEFBS_None, // VSUBI_DU = 1565 CEFBS_None, // VSUBI_HU = 1566 CEFBS_None, // VSUBI_WU = 1567 CEFBS_None, // VSUBWEV_D_W = 1568 CEFBS_None, // VSUBWEV_D_WU = 1569 CEFBS_None, // VSUBWEV_H_B = 1570 CEFBS_None, // VSUBWEV_H_BU = 1571 CEFBS_None, // VSUBWEV_Q_D = 1572 CEFBS_None, // VSUBWEV_Q_DU = 1573 CEFBS_None, // VSUBWEV_W_H = 1574 CEFBS_None, // VSUBWEV_W_HU = 1575 CEFBS_None, // VSUBWOD_D_W = 1576 CEFBS_None, // VSUBWOD_D_WU = 1577 CEFBS_None, // VSUBWOD_H_B = 1578 CEFBS_None, // VSUBWOD_H_BU = 1579 CEFBS_None, // VSUBWOD_Q_D = 1580 CEFBS_None, // VSUBWOD_Q_DU = 1581 CEFBS_None, // VSUBWOD_W_H = 1582 CEFBS_None, // VSUBWOD_W_HU = 1583 CEFBS_None, // VSUB_B = 1584 CEFBS_None, // VSUB_D = 1585 CEFBS_None, // VSUB_H = 1586 CEFBS_None, // VSUB_Q = 1587 CEFBS_None, // VSUB_W = 1588 CEFBS_None, // VXORI_B = 1589 CEFBS_None, // VXOR_V = 1590 CEFBS_None, // X86ADC_B = 1591 CEFBS_IsLA64, // X86ADC_D = 1592 CEFBS_None, // X86ADC_H = 1593 CEFBS_None, // X86ADC_W = 1594 CEFBS_None, // X86ADD_B = 1595 CEFBS_IsLA64, // X86ADD_D = 1596 CEFBS_IsLA64, // X86ADD_DU = 1597 CEFBS_None, // X86ADD_H = 1598 CEFBS_None, // X86ADD_W = 1599 CEFBS_IsLA64, // X86ADD_WU = 1600 CEFBS_None, // X86AND_B = 1601 CEFBS_IsLA64, // X86AND_D = 1602 CEFBS_None, // X86AND_H = 1603 CEFBS_None, // X86AND_W = 1604 CEFBS_None, // X86CLRTM = 1605 CEFBS_None, // X86DECTOP = 1606 CEFBS_None, // X86DEC_B = 1607 CEFBS_IsLA64, // X86DEC_D = 1608 CEFBS_None, // X86DEC_H = 1609 CEFBS_None, // X86DEC_W = 1610 CEFBS_None, // X86INCTOP = 1611 CEFBS_None, // X86INC_B = 1612 CEFBS_IsLA64, // X86INC_D = 1613 CEFBS_None, // X86INC_H = 1614 CEFBS_None, // X86INC_W = 1615 CEFBS_None, // X86MFFLAG = 1616 CEFBS_None, // X86MFTOP = 1617 CEFBS_None, // X86MTFLAG = 1618 CEFBS_None, // X86MTTOP = 1619 CEFBS_None, // X86MUL_B = 1620 CEFBS_None, // X86MUL_BU = 1621 CEFBS_IsLA64, // X86MUL_D = 1622 CEFBS_IsLA64, // X86MUL_DU = 1623 CEFBS_None, // X86MUL_H = 1624 CEFBS_None, // X86MUL_HU = 1625 CEFBS_None, // X86MUL_W = 1626 CEFBS_IsLA64, // X86MUL_WU = 1627 CEFBS_None, // X86OR_B = 1628 CEFBS_IsLA64, // X86OR_D = 1629 CEFBS_None, // X86OR_H = 1630 CEFBS_None, // X86OR_W = 1631 CEFBS_None, // X86RCLI_B = 1632 CEFBS_IsLA64, // X86RCLI_D = 1633 CEFBS_None, // X86RCLI_H = 1634 CEFBS_None, // X86RCLI_W = 1635 CEFBS_None, // X86RCL_B = 1636 CEFBS_IsLA64, // X86RCL_D = 1637 CEFBS_None, // X86RCL_H = 1638 CEFBS_None, // X86RCL_W = 1639 CEFBS_None, // X86RCRI_B = 1640 CEFBS_IsLA64, // X86RCRI_D = 1641 CEFBS_None, // X86RCRI_H = 1642 CEFBS_None, // X86RCRI_W = 1643 CEFBS_None, // X86RCR_B = 1644 CEFBS_IsLA64, // X86RCR_D = 1645 CEFBS_None, // X86RCR_H = 1646 CEFBS_None, // X86RCR_W = 1647 CEFBS_None, // X86ROTLI_B = 1648 CEFBS_IsLA64, // X86ROTLI_D = 1649 CEFBS_None, // X86ROTLI_H = 1650 CEFBS_None, // X86ROTLI_W = 1651 CEFBS_None, // X86ROTL_B = 1652 CEFBS_IsLA64, // X86ROTL_D = 1653 CEFBS_None, // X86ROTL_H = 1654 CEFBS_None, // X86ROTL_W = 1655 CEFBS_None, // X86ROTRI_B = 1656 CEFBS_IsLA64, // X86ROTRI_D = 1657 CEFBS_None, // X86ROTRI_H = 1658 CEFBS_None, // X86ROTRI_W = 1659 CEFBS_None, // X86ROTR_B = 1660 CEFBS_IsLA64, // X86ROTR_D = 1661 CEFBS_None, // X86ROTR_H = 1662 CEFBS_None, // X86ROTR_W = 1663 CEFBS_None, // X86SBC_B = 1664 CEFBS_IsLA64, // X86SBC_D = 1665 CEFBS_None, // X86SBC_H = 1666 CEFBS_None, // X86SBC_W = 1667 CEFBS_None, // X86SETTAG = 1668 CEFBS_None, // X86SETTM = 1669 CEFBS_None, // X86SLLI_B = 1670 CEFBS_IsLA64, // X86SLLI_D = 1671 CEFBS_None, // X86SLLI_H = 1672 CEFBS_None, // X86SLLI_W = 1673 CEFBS_None, // X86SLL_B = 1674 CEFBS_IsLA64, // X86SLL_D = 1675 CEFBS_None, // X86SLL_H = 1676 CEFBS_None, // X86SLL_W = 1677 CEFBS_None, // X86SRAI_B = 1678 CEFBS_IsLA64, // X86SRAI_D = 1679 CEFBS_None, // X86SRAI_H = 1680 CEFBS_None, // X86SRAI_W = 1681 CEFBS_None, // X86SRA_B = 1682 CEFBS_IsLA64, // X86SRA_D = 1683 CEFBS_None, // X86SRA_H = 1684 CEFBS_None, // X86SRA_W = 1685 CEFBS_None, // X86SRLI_B = 1686 CEFBS_IsLA64, // X86SRLI_D = 1687 CEFBS_None, // X86SRLI_H = 1688 CEFBS_None, // X86SRLI_W = 1689 CEFBS_None, // X86SRL_B = 1690 CEFBS_IsLA64, // X86SRL_D = 1691 CEFBS_None, // X86SRL_H = 1692 CEFBS_None, // X86SRL_W = 1693 CEFBS_None, // X86SUB_B = 1694 CEFBS_IsLA64, // X86SUB_D = 1695 CEFBS_IsLA64, // X86SUB_DU = 1696 CEFBS_None, // X86SUB_H = 1697 CEFBS_None, // X86SUB_W = 1698 CEFBS_IsLA64, // X86SUB_WU = 1699 CEFBS_None, // X86XOR_B = 1700 CEFBS_IsLA64, // X86XOR_D = 1701 CEFBS_None, // X86XOR_H = 1702 CEFBS_None, // X86XOR_W = 1703 CEFBS_None, // XOR = 1704 CEFBS_None, // XORI = 1705 CEFBS_None, // XVABSD_B = 1706 CEFBS_None, // XVABSD_BU = 1707 CEFBS_None, // XVABSD_D = 1708 CEFBS_None, // XVABSD_DU = 1709 CEFBS_None, // XVABSD_H = 1710 CEFBS_None, // XVABSD_HU = 1711 CEFBS_None, // XVABSD_W = 1712 CEFBS_None, // XVABSD_WU = 1713 CEFBS_None, // XVADDA_B = 1714 CEFBS_None, // XVADDA_D = 1715 CEFBS_None, // XVADDA_H = 1716 CEFBS_None, // XVADDA_W = 1717 CEFBS_None, // XVADDI_BU = 1718 CEFBS_None, // XVADDI_DU = 1719 CEFBS_None, // XVADDI_HU = 1720 CEFBS_None, // XVADDI_WU = 1721 CEFBS_None, // XVADDWEV_D_W = 1722 CEFBS_None, // XVADDWEV_D_WU = 1723 CEFBS_None, // XVADDWEV_D_WU_W = 1724 CEFBS_None, // XVADDWEV_H_B = 1725 CEFBS_None, // XVADDWEV_H_BU = 1726 CEFBS_None, // XVADDWEV_H_BU_B = 1727 CEFBS_None, // XVADDWEV_Q_D = 1728 CEFBS_None, // XVADDWEV_Q_DU = 1729 CEFBS_None, // XVADDWEV_Q_DU_D = 1730 CEFBS_None, // XVADDWEV_W_H = 1731 CEFBS_None, // XVADDWEV_W_HU = 1732 CEFBS_None, // XVADDWEV_W_HU_H = 1733 CEFBS_None, // XVADDWOD_D_W = 1734 CEFBS_None, // XVADDWOD_D_WU = 1735 CEFBS_None, // XVADDWOD_D_WU_W = 1736 CEFBS_None, // XVADDWOD_H_B = 1737 CEFBS_None, // XVADDWOD_H_BU = 1738 CEFBS_None, // XVADDWOD_H_BU_B = 1739 CEFBS_None, // XVADDWOD_Q_D = 1740 CEFBS_None, // XVADDWOD_Q_DU = 1741 CEFBS_None, // XVADDWOD_Q_DU_D = 1742 CEFBS_None, // XVADDWOD_W_H = 1743 CEFBS_None, // XVADDWOD_W_HU = 1744 CEFBS_None, // XVADDWOD_W_HU_H = 1745 CEFBS_None, // XVADD_B = 1746 CEFBS_None, // XVADD_D = 1747 CEFBS_None, // XVADD_H = 1748 CEFBS_None, // XVADD_Q = 1749 CEFBS_None, // XVADD_W = 1750 CEFBS_None, // XVANDI_B = 1751 CEFBS_None, // XVANDN_V = 1752 CEFBS_None, // XVAND_V = 1753 CEFBS_None, // XVAVGR_B = 1754 CEFBS_None, // XVAVGR_BU = 1755 CEFBS_None, // XVAVGR_D = 1756 CEFBS_None, // XVAVGR_DU = 1757 CEFBS_None, // XVAVGR_H = 1758 CEFBS_None, // XVAVGR_HU = 1759 CEFBS_None, // XVAVGR_W = 1760 CEFBS_None, // XVAVGR_WU = 1761 CEFBS_None, // XVAVG_B = 1762 CEFBS_None, // XVAVG_BU = 1763 CEFBS_None, // XVAVG_D = 1764 CEFBS_None, // XVAVG_DU = 1765 CEFBS_None, // XVAVG_H = 1766 CEFBS_None, // XVAVG_HU = 1767 CEFBS_None, // XVAVG_W = 1768 CEFBS_None, // XVAVG_WU = 1769 CEFBS_None, // XVBITCLRI_B = 1770 CEFBS_None, // XVBITCLRI_D = 1771 CEFBS_None, // XVBITCLRI_H = 1772 CEFBS_None, // XVBITCLRI_W = 1773 CEFBS_None, // XVBITCLR_B = 1774 CEFBS_None, // XVBITCLR_D = 1775 CEFBS_None, // XVBITCLR_H = 1776 CEFBS_None, // XVBITCLR_W = 1777 CEFBS_None, // XVBITREVI_B = 1778 CEFBS_None, // XVBITREVI_D = 1779 CEFBS_None, // XVBITREVI_H = 1780 CEFBS_None, // XVBITREVI_W = 1781 CEFBS_None, // XVBITREV_B = 1782 CEFBS_None, // XVBITREV_D = 1783 CEFBS_None, // XVBITREV_H = 1784 CEFBS_None, // XVBITREV_W = 1785 CEFBS_None, // XVBITSELI_B = 1786 CEFBS_None, // XVBITSEL_V = 1787 CEFBS_None, // XVBITSETI_B = 1788 CEFBS_None, // XVBITSETI_D = 1789 CEFBS_None, // XVBITSETI_H = 1790 CEFBS_None, // XVBITSETI_W = 1791 CEFBS_None, // XVBITSET_B = 1792 CEFBS_None, // XVBITSET_D = 1793 CEFBS_None, // XVBITSET_H = 1794 CEFBS_None, // XVBITSET_W = 1795 CEFBS_None, // XVBSLL_V = 1796 CEFBS_None, // XVBSRL_V = 1797 CEFBS_None, // XVCLO_B = 1798 CEFBS_None, // XVCLO_D = 1799 CEFBS_None, // XVCLO_H = 1800 CEFBS_None, // XVCLO_W = 1801 CEFBS_None, // XVCLZ_B = 1802 CEFBS_None, // XVCLZ_D = 1803 CEFBS_None, // XVCLZ_H = 1804 CEFBS_None, // XVCLZ_W = 1805 CEFBS_None, // XVDIV_B = 1806 CEFBS_None, // XVDIV_BU = 1807 CEFBS_None, // XVDIV_D = 1808 CEFBS_None, // XVDIV_DU = 1809 CEFBS_None, // XVDIV_H = 1810 CEFBS_None, // XVDIV_HU = 1811 CEFBS_None, // XVDIV_W = 1812 CEFBS_None, // XVDIV_WU = 1813 CEFBS_None, // XVEXTH_DU_WU = 1814 CEFBS_None, // XVEXTH_D_W = 1815 CEFBS_None, // XVEXTH_HU_BU = 1816 CEFBS_None, // XVEXTH_H_B = 1817 CEFBS_None, // XVEXTH_QU_DU = 1818 CEFBS_None, // XVEXTH_Q_D = 1819 CEFBS_None, // XVEXTH_WU_HU = 1820 CEFBS_None, // XVEXTH_W_H = 1821 CEFBS_None, // XVEXTL_QU_DU = 1822 CEFBS_None, // XVEXTL_Q_D = 1823 CEFBS_None, // XVEXTRINS_B = 1824 CEFBS_None, // XVEXTRINS_D = 1825 CEFBS_None, // XVEXTRINS_H = 1826 CEFBS_None, // XVEXTRINS_W = 1827 CEFBS_None, // XVFADD_D = 1828 CEFBS_None, // XVFADD_S = 1829 CEFBS_None, // XVFCLASS_D = 1830 CEFBS_None, // XVFCLASS_S = 1831 CEFBS_None, // XVFCMP_CAF_D = 1832 CEFBS_None, // XVFCMP_CAF_S = 1833 CEFBS_None, // XVFCMP_CEQ_D = 1834 CEFBS_None, // XVFCMP_CEQ_S = 1835 CEFBS_None, // XVFCMP_CLE_D = 1836 CEFBS_None, // XVFCMP_CLE_S = 1837 CEFBS_None, // XVFCMP_CLT_D = 1838 CEFBS_None, // XVFCMP_CLT_S = 1839 CEFBS_None, // XVFCMP_CNE_D = 1840 CEFBS_None, // XVFCMP_CNE_S = 1841 CEFBS_None, // XVFCMP_COR_D = 1842 CEFBS_None, // XVFCMP_COR_S = 1843 CEFBS_None, // XVFCMP_CUEQ_D = 1844 CEFBS_None, // XVFCMP_CUEQ_S = 1845 CEFBS_None, // XVFCMP_CULE_D = 1846 CEFBS_None, // XVFCMP_CULE_S = 1847 CEFBS_None, // XVFCMP_CULT_D = 1848 CEFBS_None, // XVFCMP_CULT_S = 1849 CEFBS_None, // XVFCMP_CUNE_D = 1850 CEFBS_None, // XVFCMP_CUNE_S = 1851 CEFBS_None, // XVFCMP_CUN_D = 1852 CEFBS_None, // XVFCMP_CUN_S = 1853 CEFBS_None, // XVFCMP_SAF_D = 1854 CEFBS_None, // XVFCMP_SAF_S = 1855 CEFBS_None, // XVFCMP_SEQ_D = 1856 CEFBS_None, // XVFCMP_SEQ_S = 1857 CEFBS_None, // XVFCMP_SLE_D = 1858 CEFBS_None, // XVFCMP_SLE_S = 1859 CEFBS_None, // XVFCMP_SLT_D = 1860 CEFBS_None, // XVFCMP_SLT_S = 1861 CEFBS_None, // XVFCMP_SNE_D = 1862 CEFBS_None, // XVFCMP_SNE_S = 1863 CEFBS_None, // XVFCMP_SOR_D = 1864 CEFBS_None, // XVFCMP_SOR_S = 1865 CEFBS_None, // XVFCMP_SUEQ_D = 1866 CEFBS_None, // XVFCMP_SUEQ_S = 1867 CEFBS_None, // XVFCMP_SULE_D = 1868 CEFBS_None, // XVFCMP_SULE_S = 1869 CEFBS_None, // XVFCMP_SULT_D = 1870 CEFBS_None, // XVFCMP_SULT_S = 1871 CEFBS_None, // XVFCMP_SUNE_D = 1872 CEFBS_None, // XVFCMP_SUNE_S = 1873 CEFBS_None, // XVFCMP_SUN_D = 1874 CEFBS_None, // XVFCMP_SUN_S = 1875 CEFBS_None, // XVFCVTH_D_S = 1876 CEFBS_None, // XVFCVTH_S_H = 1877 CEFBS_None, // XVFCVTL_D_S = 1878 CEFBS_None, // XVFCVTL_S_H = 1879 CEFBS_None, // XVFCVT_H_S = 1880 CEFBS_None, // XVFCVT_S_D = 1881 CEFBS_None, // XVFDIV_D = 1882 CEFBS_None, // XVFDIV_S = 1883 CEFBS_None, // XVFFINTH_D_W = 1884 CEFBS_None, // XVFFINTL_D_W = 1885 CEFBS_None, // XVFFINT_D_L = 1886 CEFBS_None, // XVFFINT_D_LU = 1887 CEFBS_None, // XVFFINT_S_L = 1888 CEFBS_None, // XVFFINT_S_W = 1889 CEFBS_None, // XVFFINT_S_WU = 1890 CEFBS_None, // XVFLOGB_D = 1891 CEFBS_None, // XVFLOGB_S = 1892 CEFBS_None, // XVFMADD_D = 1893 CEFBS_None, // XVFMADD_S = 1894 CEFBS_None, // XVFMAXA_D = 1895 CEFBS_None, // XVFMAXA_S = 1896 CEFBS_None, // XVFMAX_D = 1897 CEFBS_None, // XVFMAX_S = 1898 CEFBS_None, // XVFMINA_D = 1899 CEFBS_None, // XVFMINA_S = 1900 CEFBS_None, // XVFMIN_D = 1901 CEFBS_None, // XVFMIN_S = 1902 CEFBS_None, // XVFMSUB_D = 1903 CEFBS_None, // XVFMSUB_S = 1904 CEFBS_None, // XVFMUL_D = 1905 CEFBS_None, // XVFMUL_S = 1906 CEFBS_None, // XVFNMADD_D = 1907 CEFBS_None, // XVFNMADD_S = 1908 CEFBS_None, // XVFNMSUB_D = 1909 CEFBS_None, // XVFNMSUB_S = 1910 CEFBS_None, // XVFRECIPE_D = 1911 CEFBS_None, // XVFRECIPE_S = 1912 CEFBS_None, // XVFRECIP_D = 1913 CEFBS_None, // XVFRECIP_S = 1914 CEFBS_None, // XVFRINTRM_D = 1915 CEFBS_None, // XVFRINTRM_S = 1916 CEFBS_None, // XVFRINTRNE_D = 1917 CEFBS_None, // XVFRINTRNE_S = 1918 CEFBS_None, // XVFRINTRP_D = 1919 CEFBS_None, // XVFRINTRP_S = 1920 CEFBS_None, // XVFRINTRZ_D = 1921 CEFBS_None, // XVFRINTRZ_S = 1922 CEFBS_None, // XVFRINT_D = 1923 CEFBS_None, // XVFRINT_S = 1924 CEFBS_None, // XVFRSQRTE_D = 1925 CEFBS_None, // XVFRSQRTE_S = 1926 CEFBS_None, // XVFRSQRT_D = 1927 CEFBS_None, // XVFRSQRT_S = 1928 CEFBS_None, // XVFRSTPI_B = 1929 CEFBS_None, // XVFRSTPI_H = 1930 CEFBS_None, // XVFRSTP_B = 1931 CEFBS_None, // XVFRSTP_H = 1932 CEFBS_None, // XVFSQRT_D = 1933 CEFBS_None, // XVFSQRT_S = 1934 CEFBS_None, // XVFSUB_D = 1935 CEFBS_None, // XVFSUB_S = 1936 CEFBS_None, // XVFTINTH_L_S = 1937 CEFBS_None, // XVFTINTL_L_S = 1938 CEFBS_None, // XVFTINTRMH_L_S = 1939 CEFBS_None, // XVFTINTRML_L_S = 1940 CEFBS_None, // XVFTINTRM_L_D = 1941 CEFBS_None, // XVFTINTRM_W_D = 1942 CEFBS_None, // XVFTINTRM_W_S = 1943 CEFBS_None, // XVFTINTRNEH_L_S = 1944 CEFBS_None, // XVFTINTRNEL_L_S = 1945 CEFBS_None, // XVFTINTRNE_L_D = 1946 CEFBS_None, // XVFTINTRNE_W_D = 1947 CEFBS_None, // XVFTINTRNE_W_S = 1948 CEFBS_None, // XVFTINTRPH_L_S = 1949 CEFBS_None, // XVFTINTRPL_L_S = 1950 CEFBS_None, // XVFTINTRP_L_D = 1951 CEFBS_None, // XVFTINTRP_W_D = 1952 CEFBS_None, // XVFTINTRP_W_S = 1953 CEFBS_None, // XVFTINTRZH_L_S = 1954 CEFBS_None, // XVFTINTRZL_L_S = 1955 CEFBS_None, // XVFTINTRZ_LU_D = 1956 CEFBS_None, // XVFTINTRZ_L_D = 1957 CEFBS_None, // XVFTINTRZ_WU_S = 1958 CEFBS_None, // XVFTINTRZ_W_D = 1959 CEFBS_None, // XVFTINTRZ_W_S = 1960 CEFBS_None, // XVFTINT_LU_D = 1961 CEFBS_None, // XVFTINT_L_D = 1962 CEFBS_None, // XVFTINT_WU_S = 1963 CEFBS_None, // XVFTINT_W_D = 1964 CEFBS_None, // XVFTINT_W_S = 1965 CEFBS_None, // XVHADDW_DU_WU = 1966 CEFBS_None, // XVHADDW_D_W = 1967 CEFBS_None, // XVHADDW_HU_BU = 1968 CEFBS_None, // XVHADDW_H_B = 1969 CEFBS_None, // XVHADDW_QU_DU = 1970 CEFBS_None, // XVHADDW_Q_D = 1971 CEFBS_None, // XVHADDW_WU_HU = 1972 CEFBS_None, // XVHADDW_W_H = 1973 CEFBS_None, // XVHSELI_D = 1974 CEFBS_None, // XVHSUBW_DU_WU = 1975 CEFBS_None, // XVHSUBW_D_W = 1976 CEFBS_None, // XVHSUBW_HU_BU = 1977 CEFBS_None, // XVHSUBW_H_B = 1978 CEFBS_None, // XVHSUBW_QU_DU = 1979 CEFBS_None, // XVHSUBW_Q_D = 1980 CEFBS_None, // XVHSUBW_WU_HU = 1981 CEFBS_None, // XVHSUBW_W_H = 1982 CEFBS_None, // XVILVH_B = 1983 CEFBS_None, // XVILVH_D = 1984 CEFBS_None, // XVILVH_H = 1985 CEFBS_None, // XVILVH_W = 1986 CEFBS_None, // XVILVL_B = 1987 CEFBS_None, // XVILVL_D = 1988 CEFBS_None, // XVILVL_H = 1989 CEFBS_None, // XVILVL_W = 1990 CEFBS_None, // XVINSGR2VR_D = 1991 CEFBS_None, // XVINSGR2VR_W = 1992 CEFBS_None, // XVINSVE0_D = 1993 CEFBS_None, // XVINSVE0_W = 1994 CEFBS_None, // XVLD = 1995 CEFBS_None, // XVLDI = 1996 CEFBS_None, // XVLDREPL_B = 1997 CEFBS_None, // XVLDREPL_D = 1998 CEFBS_None, // XVLDREPL_H = 1999 CEFBS_None, // XVLDREPL_W = 2000 CEFBS_None, // XVLDX = 2001 CEFBS_None, // XVMADDWEV_D_W = 2002 CEFBS_None, // XVMADDWEV_D_WU = 2003 CEFBS_None, // XVMADDWEV_D_WU_W = 2004 CEFBS_None, // XVMADDWEV_H_B = 2005 CEFBS_None, // XVMADDWEV_H_BU = 2006 CEFBS_None, // XVMADDWEV_H_BU_B = 2007 CEFBS_None, // XVMADDWEV_Q_D = 2008 CEFBS_None, // XVMADDWEV_Q_DU = 2009 CEFBS_None, // XVMADDWEV_Q_DU_D = 2010 CEFBS_None, // XVMADDWEV_W_H = 2011 CEFBS_None, // XVMADDWEV_W_HU = 2012 CEFBS_None, // XVMADDWEV_W_HU_H = 2013 CEFBS_None, // XVMADDWOD_D_W = 2014 CEFBS_None, // XVMADDWOD_D_WU = 2015 CEFBS_None, // XVMADDWOD_D_WU_W = 2016 CEFBS_None, // XVMADDWOD_H_B = 2017 CEFBS_None, // XVMADDWOD_H_BU = 2018 CEFBS_None, // XVMADDWOD_H_BU_B = 2019 CEFBS_None, // XVMADDWOD_Q_D = 2020 CEFBS_None, // XVMADDWOD_Q_DU = 2021 CEFBS_None, // XVMADDWOD_Q_DU_D = 2022 CEFBS_None, // XVMADDWOD_W_H = 2023 CEFBS_None, // XVMADDWOD_W_HU = 2024 CEFBS_None, // XVMADDWOD_W_HU_H = 2025 CEFBS_None, // XVMADD_B = 2026 CEFBS_None, // XVMADD_D = 2027 CEFBS_None, // XVMADD_H = 2028 CEFBS_None, // XVMADD_W = 2029 CEFBS_None, // XVMAXI_B = 2030 CEFBS_None, // XVMAXI_BU = 2031 CEFBS_None, // XVMAXI_D = 2032 CEFBS_None, // XVMAXI_DU = 2033 CEFBS_None, // XVMAXI_H = 2034 CEFBS_None, // XVMAXI_HU = 2035 CEFBS_None, // XVMAXI_W = 2036 CEFBS_None, // XVMAXI_WU = 2037 CEFBS_None, // XVMAX_B = 2038 CEFBS_None, // XVMAX_BU = 2039 CEFBS_None, // XVMAX_D = 2040 CEFBS_None, // XVMAX_DU = 2041 CEFBS_None, // XVMAX_H = 2042 CEFBS_None, // XVMAX_HU = 2043 CEFBS_None, // XVMAX_W = 2044 CEFBS_None, // XVMAX_WU = 2045 CEFBS_None, // XVMINI_B = 2046 CEFBS_None, // XVMINI_BU = 2047 CEFBS_None, // XVMINI_D = 2048 CEFBS_None, // XVMINI_DU = 2049 CEFBS_None, // XVMINI_H = 2050 CEFBS_None, // XVMINI_HU = 2051 CEFBS_None, // XVMINI_W = 2052 CEFBS_None, // XVMINI_WU = 2053 CEFBS_None, // XVMIN_B = 2054 CEFBS_None, // XVMIN_BU = 2055 CEFBS_None, // XVMIN_D = 2056 CEFBS_None, // XVMIN_DU = 2057 CEFBS_None, // XVMIN_H = 2058 CEFBS_None, // XVMIN_HU = 2059 CEFBS_None, // XVMIN_W = 2060 CEFBS_None, // XVMIN_WU = 2061 CEFBS_None, // XVMOD_B = 2062 CEFBS_None, // XVMOD_BU = 2063 CEFBS_None, // XVMOD_D = 2064 CEFBS_None, // XVMOD_DU = 2065 CEFBS_None, // XVMOD_H = 2066 CEFBS_None, // XVMOD_HU = 2067 CEFBS_None, // XVMOD_W = 2068 CEFBS_None, // XVMOD_WU = 2069 CEFBS_None, // XVMSKGEZ_B = 2070 CEFBS_None, // XVMSKLTZ_B = 2071 CEFBS_None, // XVMSKLTZ_D = 2072 CEFBS_None, // XVMSKLTZ_H = 2073 CEFBS_None, // XVMSKLTZ_W = 2074 CEFBS_None, // XVMSKNZ_B = 2075 CEFBS_None, // XVMSUB_B = 2076 CEFBS_None, // XVMSUB_D = 2077 CEFBS_None, // XVMSUB_H = 2078 CEFBS_None, // XVMSUB_W = 2079 CEFBS_None, // XVMUH_B = 2080 CEFBS_None, // XVMUH_BU = 2081 CEFBS_None, // XVMUH_D = 2082 CEFBS_None, // XVMUH_DU = 2083 CEFBS_None, // XVMUH_H = 2084 CEFBS_None, // XVMUH_HU = 2085 CEFBS_None, // XVMUH_W = 2086 CEFBS_None, // XVMUH_WU = 2087 CEFBS_None, // XVMULWEV_D_W = 2088 CEFBS_None, // XVMULWEV_D_WU = 2089 CEFBS_None, // XVMULWEV_D_WU_W = 2090 CEFBS_None, // XVMULWEV_H_B = 2091 CEFBS_None, // XVMULWEV_H_BU = 2092 CEFBS_None, // XVMULWEV_H_BU_B = 2093 CEFBS_None, // XVMULWEV_Q_D = 2094 CEFBS_None, // XVMULWEV_Q_DU = 2095 CEFBS_None, // XVMULWEV_Q_DU_D = 2096 CEFBS_None, // XVMULWEV_W_H = 2097 CEFBS_None, // XVMULWEV_W_HU = 2098 CEFBS_None, // XVMULWEV_W_HU_H = 2099 CEFBS_None, // XVMULWOD_D_W = 2100 CEFBS_None, // XVMULWOD_D_WU = 2101 CEFBS_None, // XVMULWOD_D_WU_W = 2102 CEFBS_None, // XVMULWOD_H_B = 2103 CEFBS_None, // XVMULWOD_H_BU = 2104 CEFBS_None, // XVMULWOD_H_BU_B = 2105 CEFBS_None, // XVMULWOD_Q_D = 2106 CEFBS_None, // XVMULWOD_Q_DU = 2107 CEFBS_None, // XVMULWOD_Q_DU_D = 2108 CEFBS_None, // XVMULWOD_W_H = 2109 CEFBS_None, // XVMULWOD_W_HU = 2110 CEFBS_None, // XVMULWOD_W_HU_H = 2111 CEFBS_None, // XVMUL_B = 2112 CEFBS_None, // XVMUL_D = 2113 CEFBS_None, // XVMUL_H = 2114 CEFBS_None, // XVMUL_W = 2115 CEFBS_None, // XVNEG_B = 2116 CEFBS_None, // XVNEG_D = 2117 CEFBS_None, // XVNEG_H = 2118 CEFBS_None, // XVNEG_W = 2119 CEFBS_None, // XVNORI_B = 2120 CEFBS_None, // XVNOR_V = 2121 CEFBS_None, // XVORI_B = 2122 CEFBS_None, // XVORN_V = 2123 CEFBS_None, // XVOR_V = 2124 CEFBS_None, // XVPACKEV_B = 2125 CEFBS_None, // XVPACKEV_D = 2126 CEFBS_None, // XVPACKEV_H = 2127 CEFBS_None, // XVPACKEV_W = 2128 CEFBS_None, // XVPACKOD_B = 2129 CEFBS_None, // XVPACKOD_D = 2130 CEFBS_None, // XVPACKOD_H = 2131 CEFBS_None, // XVPACKOD_W = 2132 CEFBS_None, // XVPCNT_B = 2133 CEFBS_None, // XVPCNT_D = 2134 CEFBS_None, // XVPCNT_H = 2135 CEFBS_None, // XVPCNT_W = 2136 CEFBS_None, // XVPERMI_D = 2137 CEFBS_None, // XVPERMI_Q = 2138 CEFBS_None, // XVPERMI_W = 2139 CEFBS_None, // XVPERM_W = 2140 CEFBS_None, // XVPICKEV_B = 2141 CEFBS_None, // XVPICKEV_D = 2142 CEFBS_None, // XVPICKEV_H = 2143 CEFBS_None, // XVPICKEV_W = 2144 CEFBS_None, // XVPICKOD_B = 2145 CEFBS_None, // XVPICKOD_D = 2146 CEFBS_None, // XVPICKOD_H = 2147 CEFBS_None, // XVPICKOD_W = 2148 CEFBS_None, // XVPICKVE2GR_D = 2149 CEFBS_None, // XVPICKVE2GR_DU = 2150 CEFBS_None, // XVPICKVE2GR_W = 2151 CEFBS_None, // XVPICKVE2GR_WU = 2152 CEFBS_None, // XVPICKVE_D = 2153 CEFBS_None, // XVPICKVE_W = 2154 CEFBS_None, // XVREPL128VEI_B = 2155 CEFBS_None, // XVREPL128VEI_D = 2156 CEFBS_None, // XVREPL128VEI_H = 2157 CEFBS_None, // XVREPL128VEI_W = 2158 CEFBS_None, // XVREPLGR2VR_B = 2159 CEFBS_None, // XVREPLGR2VR_D = 2160 CEFBS_None, // XVREPLGR2VR_H = 2161 CEFBS_None, // XVREPLGR2VR_W = 2162 CEFBS_None, // XVREPLVE0_B = 2163 CEFBS_None, // XVREPLVE0_D = 2164 CEFBS_None, // XVREPLVE0_H = 2165 CEFBS_None, // XVREPLVE0_Q = 2166 CEFBS_None, // XVREPLVE0_W = 2167 CEFBS_None, // XVREPLVE_B = 2168 CEFBS_None, // XVREPLVE_D = 2169 CEFBS_None, // XVREPLVE_H = 2170 CEFBS_None, // XVREPLVE_W = 2171 CEFBS_None, // XVROTRI_B = 2172 CEFBS_None, // XVROTRI_D = 2173 CEFBS_None, // XVROTRI_H = 2174 CEFBS_None, // XVROTRI_W = 2175 CEFBS_None, // XVROTR_B = 2176 CEFBS_None, // XVROTR_D = 2177 CEFBS_None, // XVROTR_H = 2178 CEFBS_None, // XVROTR_W = 2179 CEFBS_None, // XVSADD_B = 2180 CEFBS_None, // XVSADD_BU = 2181 CEFBS_None, // XVSADD_D = 2182 CEFBS_None, // XVSADD_DU = 2183 CEFBS_None, // XVSADD_H = 2184 CEFBS_None, // XVSADD_HU = 2185 CEFBS_None, // XVSADD_W = 2186 CEFBS_None, // XVSADD_WU = 2187 CEFBS_None, // XVSAT_B = 2188 CEFBS_None, // XVSAT_BU = 2189 CEFBS_None, // XVSAT_D = 2190 CEFBS_None, // XVSAT_DU = 2191 CEFBS_None, // XVSAT_H = 2192 CEFBS_None, // XVSAT_HU = 2193 CEFBS_None, // XVSAT_W = 2194 CEFBS_None, // XVSAT_WU = 2195 CEFBS_None, // XVSEQI_B = 2196 CEFBS_None, // XVSEQI_D = 2197 CEFBS_None, // XVSEQI_H = 2198 CEFBS_None, // XVSEQI_W = 2199 CEFBS_None, // XVSEQ_B = 2200 CEFBS_None, // XVSEQ_D = 2201 CEFBS_None, // XVSEQ_H = 2202 CEFBS_None, // XVSEQ_W = 2203 CEFBS_None, // XVSETALLNEZ_B = 2204 CEFBS_None, // XVSETALLNEZ_D = 2205 CEFBS_None, // XVSETALLNEZ_H = 2206 CEFBS_None, // XVSETALLNEZ_W = 2207 CEFBS_None, // XVSETANYEQZ_B = 2208 CEFBS_None, // XVSETANYEQZ_D = 2209 CEFBS_None, // XVSETANYEQZ_H = 2210 CEFBS_None, // XVSETANYEQZ_W = 2211 CEFBS_None, // XVSETEQZ_V = 2212 CEFBS_None, // XVSETNEZ_V = 2213 CEFBS_None, // XVSHUF4I_B = 2214 CEFBS_None, // XVSHUF4I_D = 2215 CEFBS_None, // XVSHUF4I_H = 2216 CEFBS_None, // XVSHUF4I_W = 2217 CEFBS_None, // XVSHUF_B = 2218 CEFBS_None, // XVSHUF_D = 2219 CEFBS_None, // XVSHUF_H = 2220 CEFBS_None, // XVSHUF_W = 2221 CEFBS_None, // XVSIGNCOV_B = 2222 CEFBS_None, // XVSIGNCOV_D = 2223 CEFBS_None, // XVSIGNCOV_H = 2224 CEFBS_None, // XVSIGNCOV_W = 2225 CEFBS_None, // XVSLEI_B = 2226 CEFBS_None, // XVSLEI_BU = 2227 CEFBS_None, // XVSLEI_D = 2228 CEFBS_None, // XVSLEI_DU = 2229 CEFBS_None, // XVSLEI_H = 2230 CEFBS_None, // XVSLEI_HU = 2231 CEFBS_None, // XVSLEI_W = 2232 CEFBS_None, // XVSLEI_WU = 2233 CEFBS_None, // XVSLE_B = 2234 CEFBS_None, // XVSLE_BU = 2235 CEFBS_None, // XVSLE_D = 2236 CEFBS_None, // XVSLE_DU = 2237 CEFBS_None, // XVSLE_H = 2238 CEFBS_None, // XVSLE_HU = 2239 CEFBS_None, // XVSLE_W = 2240 CEFBS_None, // XVSLE_WU = 2241 CEFBS_None, // XVSLLI_B = 2242 CEFBS_None, // XVSLLI_D = 2243 CEFBS_None, // XVSLLI_H = 2244 CEFBS_None, // XVSLLI_W = 2245 CEFBS_None, // XVSLLWIL_DU_WU = 2246 CEFBS_None, // XVSLLWIL_D_W = 2247 CEFBS_None, // XVSLLWIL_HU_BU = 2248 CEFBS_None, // XVSLLWIL_H_B = 2249 CEFBS_None, // XVSLLWIL_WU_HU = 2250 CEFBS_None, // XVSLLWIL_W_H = 2251 CEFBS_None, // XVSLL_B = 2252 CEFBS_None, // XVSLL_D = 2253 CEFBS_None, // XVSLL_H = 2254 CEFBS_None, // XVSLL_W = 2255 CEFBS_None, // XVSLTI_B = 2256 CEFBS_None, // XVSLTI_BU = 2257 CEFBS_None, // XVSLTI_D = 2258 CEFBS_None, // XVSLTI_DU = 2259 CEFBS_None, // XVSLTI_H = 2260 CEFBS_None, // XVSLTI_HU = 2261 CEFBS_None, // XVSLTI_W = 2262 CEFBS_None, // XVSLTI_WU = 2263 CEFBS_None, // XVSLT_B = 2264 CEFBS_None, // XVSLT_BU = 2265 CEFBS_None, // XVSLT_D = 2266 CEFBS_None, // XVSLT_DU = 2267 CEFBS_None, // XVSLT_H = 2268 CEFBS_None, // XVSLT_HU = 2269 CEFBS_None, // XVSLT_W = 2270 CEFBS_None, // XVSLT_WU = 2271 CEFBS_None, // XVSRAI_B = 2272 CEFBS_None, // XVSRAI_D = 2273 CEFBS_None, // XVSRAI_H = 2274 CEFBS_None, // XVSRAI_W = 2275 CEFBS_None, // XVSRANI_B_H = 2276 CEFBS_None, // XVSRANI_D_Q = 2277 CEFBS_None, // XVSRANI_H_W = 2278 CEFBS_None, // XVSRANI_W_D = 2279 CEFBS_None, // XVSRAN_B_H = 2280 CEFBS_None, // XVSRAN_H_W = 2281 CEFBS_None, // XVSRAN_W_D = 2282 CEFBS_None, // XVSRARI_B = 2283 CEFBS_None, // XVSRARI_D = 2284 CEFBS_None, // XVSRARI_H = 2285 CEFBS_None, // XVSRARI_W = 2286 CEFBS_None, // XVSRARNI_B_H = 2287 CEFBS_None, // XVSRARNI_D_Q = 2288 CEFBS_None, // XVSRARNI_H_W = 2289 CEFBS_None, // XVSRARNI_W_D = 2290 CEFBS_None, // XVSRARN_B_H = 2291 CEFBS_None, // XVSRARN_H_W = 2292 CEFBS_None, // XVSRARN_W_D = 2293 CEFBS_None, // XVSRAR_B = 2294 CEFBS_None, // XVSRAR_D = 2295 CEFBS_None, // XVSRAR_H = 2296 CEFBS_None, // XVSRAR_W = 2297 CEFBS_None, // XVSRA_B = 2298 CEFBS_None, // XVSRA_D = 2299 CEFBS_None, // XVSRA_H = 2300 CEFBS_None, // XVSRA_W = 2301 CEFBS_None, // XVSRLI_B = 2302 CEFBS_None, // XVSRLI_D = 2303 CEFBS_None, // XVSRLI_H = 2304 CEFBS_None, // XVSRLI_W = 2305 CEFBS_None, // XVSRLNI_B_H = 2306 CEFBS_None, // XVSRLNI_D_Q = 2307 CEFBS_None, // XVSRLNI_H_W = 2308 CEFBS_None, // XVSRLNI_W_D = 2309 CEFBS_None, // XVSRLN_B_H = 2310 CEFBS_None, // XVSRLN_H_W = 2311 CEFBS_None, // XVSRLN_W_D = 2312 CEFBS_None, // XVSRLRI_B = 2313 CEFBS_None, // XVSRLRI_D = 2314 CEFBS_None, // XVSRLRI_H = 2315 CEFBS_None, // XVSRLRI_W = 2316 CEFBS_None, // XVSRLRNI_B_H = 2317 CEFBS_None, // XVSRLRNI_D_Q = 2318 CEFBS_None, // XVSRLRNI_H_W = 2319 CEFBS_None, // XVSRLRNI_W_D = 2320 CEFBS_None, // XVSRLRN_B_H = 2321 CEFBS_None, // XVSRLRN_H_W = 2322 CEFBS_None, // XVSRLRN_W_D = 2323 CEFBS_None, // XVSRLR_B = 2324 CEFBS_None, // XVSRLR_D = 2325 CEFBS_None, // XVSRLR_H = 2326 CEFBS_None, // XVSRLR_W = 2327 CEFBS_None, // XVSRL_B = 2328 CEFBS_None, // XVSRL_D = 2329 CEFBS_None, // XVSRL_H = 2330 CEFBS_None, // XVSRL_W = 2331 CEFBS_None, // XVSSRANI_BU_H = 2332 CEFBS_None, // XVSSRANI_B_H = 2333 CEFBS_None, // XVSSRANI_DU_Q = 2334 CEFBS_None, // XVSSRANI_D_Q = 2335 CEFBS_None, // XVSSRANI_HU_W = 2336 CEFBS_None, // XVSSRANI_H_W = 2337 CEFBS_None, // XVSSRANI_WU_D = 2338 CEFBS_None, // XVSSRANI_W_D = 2339 CEFBS_None, // XVSSRAN_BU_H = 2340 CEFBS_None, // XVSSRAN_B_H = 2341 CEFBS_None, // XVSSRAN_HU_W = 2342 CEFBS_None, // XVSSRAN_H_W = 2343 CEFBS_None, // XVSSRAN_WU_D = 2344 CEFBS_None, // XVSSRAN_W_D = 2345 CEFBS_None, // XVSSRARNI_BU_H = 2346 CEFBS_None, // XVSSRARNI_B_H = 2347 CEFBS_None, // XVSSRARNI_DU_Q = 2348 CEFBS_None, // XVSSRARNI_D_Q = 2349 CEFBS_None, // XVSSRARNI_HU_W = 2350 CEFBS_None, // XVSSRARNI_H_W = 2351 CEFBS_None, // XVSSRARNI_WU_D = 2352 CEFBS_None, // XVSSRARNI_W_D = 2353 CEFBS_None, // XVSSRARN_BU_H = 2354 CEFBS_None, // XVSSRARN_B_H = 2355 CEFBS_None, // XVSSRARN_HU_W = 2356 CEFBS_None, // XVSSRARN_H_W = 2357 CEFBS_None, // XVSSRARN_WU_D = 2358 CEFBS_None, // XVSSRARN_W_D = 2359 CEFBS_None, // XVSSRLNI_BU_H = 2360 CEFBS_None, // XVSSRLNI_B_H = 2361 CEFBS_None, // XVSSRLNI_DU_Q = 2362 CEFBS_None, // XVSSRLNI_D_Q = 2363 CEFBS_None, // XVSSRLNI_HU_W = 2364 CEFBS_None, // XVSSRLNI_H_W = 2365 CEFBS_None, // XVSSRLNI_WU_D = 2366 CEFBS_None, // XVSSRLNI_W_D = 2367 CEFBS_None, // XVSSRLN_BU_H = 2368 CEFBS_None, // XVSSRLN_B_H = 2369 CEFBS_None, // XVSSRLN_HU_W = 2370 CEFBS_None, // XVSSRLN_H_W = 2371 CEFBS_None, // XVSSRLN_WU_D = 2372 CEFBS_None, // XVSSRLN_W_D = 2373 CEFBS_None, // XVSSRLRNI_BU_H = 2374 CEFBS_None, // XVSSRLRNI_B_H = 2375 CEFBS_None, // XVSSRLRNI_DU_Q = 2376 CEFBS_None, // XVSSRLRNI_D_Q = 2377 CEFBS_None, // XVSSRLRNI_HU_W = 2378 CEFBS_None, // XVSSRLRNI_H_W = 2379 CEFBS_None, // XVSSRLRNI_WU_D = 2380 CEFBS_None, // XVSSRLRNI_W_D = 2381 CEFBS_None, // XVSSRLRN_BU_H = 2382 CEFBS_None, // XVSSRLRN_B_H = 2383 CEFBS_None, // XVSSRLRN_HU_W = 2384 CEFBS_None, // XVSSRLRN_H_W = 2385 CEFBS_None, // XVSSRLRN_WU_D = 2386 CEFBS_None, // XVSSRLRN_W_D = 2387 CEFBS_None, // XVSSUB_B = 2388 CEFBS_None, // XVSSUB_BU = 2389 CEFBS_None, // XVSSUB_D = 2390 CEFBS_None, // XVSSUB_DU = 2391 CEFBS_None, // XVSSUB_H = 2392 CEFBS_None, // XVSSUB_HU = 2393 CEFBS_None, // XVSSUB_W = 2394 CEFBS_None, // XVSSUB_WU = 2395 CEFBS_None, // XVST = 2396 CEFBS_None, // XVSTELM_B = 2397 CEFBS_None, // XVSTELM_D = 2398 CEFBS_None, // XVSTELM_H = 2399 CEFBS_None, // XVSTELM_W = 2400 CEFBS_None, // XVSTX = 2401 CEFBS_None, // XVSUBI_BU = 2402 CEFBS_None, // XVSUBI_DU = 2403 CEFBS_None, // XVSUBI_HU = 2404 CEFBS_None, // XVSUBI_WU = 2405 CEFBS_None, // XVSUBWEV_D_W = 2406 CEFBS_None, // XVSUBWEV_D_WU = 2407 CEFBS_None, // XVSUBWEV_H_B = 2408 CEFBS_None, // XVSUBWEV_H_BU = 2409 CEFBS_None, // XVSUBWEV_Q_D = 2410 CEFBS_None, // XVSUBWEV_Q_DU = 2411 CEFBS_None, // XVSUBWEV_W_H = 2412 CEFBS_None, // XVSUBWEV_W_HU = 2413 CEFBS_None, // XVSUBWOD_D_W = 2414 CEFBS_None, // XVSUBWOD_D_WU = 2415 CEFBS_None, // XVSUBWOD_H_B = 2416 CEFBS_None, // XVSUBWOD_H_BU = 2417 CEFBS_None, // XVSUBWOD_Q_D = 2418 CEFBS_None, // XVSUBWOD_Q_DU = 2419 CEFBS_None, // XVSUBWOD_W_H = 2420 CEFBS_None, // XVSUBWOD_W_HU = 2421 CEFBS_None, // XVSUB_B = 2422 CEFBS_None, // XVSUB_D = 2423 CEFBS_None, // XVSUB_H = 2424 CEFBS_None, // XVSUB_Q = 2425 CEFBS_None, // XVSUB_W = 2426 CEFBS_None, // XVXORI_B = 2427 CEFBS_None, // XVXOR_V = 2428 }; assert(Opcode < 2429); return FeatureBitsets[RequiredFeaturesRefs[Opcode]]; } } // end namespace LoongArch_MC } // end namespace llvm #endif // GET_COMPUTE_FEATURES #ifdef GET_AVAILABLE_OPCODE_CHECKER #undef GET_AVAILABLE_OPCODE_CHECKER namespace llvm { namespace LoongArch_MC { bool isOpcodeAvailable(unsigned Opcode, const FeatureBitset &Features) { FeatureBitset AvailableFeatures = computeAvailableFeatures(Features); FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode); FeatureBitset MissingFeatures = (AvailableFeatures & RequiredFeatures) ^ RequiredFeatures; return !MissingFeatures.any(); } } // end namespace LoongArch_MC } // end namespace llvm #endif // GET_AVAILABLE_OPCODE_CHECKER #ifdef ENABLE_INSTR_PREDICATE_VERIFIER #undef ENABLE_INSTR_PREDICATE_VERIFIER #include <sstream> namespace llvm { namespace LoongArch_MC { #ifndef NDEBUG static const char *SubtargetFeatureNames[] = { "Feature_HasLaGlobalWithAbs", "Feature_HasLaGlobalWithPcrel", "Feature_HasLaLocalWithAbs", "Feature_IsLA32", "Feature_IsLA64", nullptr }; #endif // NDEBUG void verifyInstructionPredicates( unsigned Opcode, const FeatureBitset &Features) { #ifndef NDEBUG FeatureBitset AvailableFeatures = computeAvailableFeatures(Features); FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode); FeatureBitset MissingFeatures = (AvailableFeatures & RequiredFeatures) ^ RequiredFeatures; if (MissingFeatures.any()) { std::ostringstream Msg; Msg << "Attempting to emit " << &LoongArchInstrNameData[LoongArchInstrNameIndices[Opcode]] << " instruction but the "; for (unsigned i = 0, e = MissingFeatures.size(); i != e; ++i) if (MissingFeatures.test(i)) Msg << SubtargetFeatureNames[i] << " "; Msg << "predicate(s) are not met"; report_fatal_error(Msg.str().c_str()); } #endif // NDEBUG } } // end namespace LoongArch_MC } // end namespace llvm #endif // ENABLE_INSTR_PREDICATE_VERIFIER
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