llvm/lib/Target/LoongArch/LoongArchGenMCCodeEmitter.inc

/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
|*                                                                            *|
|* Machine Code Emitter                                                       *|
|*                                                                            *|
|* Automatically generated file, do not edit!                                 *|
|*                                                                            *|
\*===----------------------------------------------------------------------===*/

uint64_t LoongArchMCCodeEmitter::getBinaryCodeForInstr(const MCInst &MI,
    SmallVectorImpl<MCFixup> &Fixups,
    const MCSubtargetInfo &STI) const { … }

#ifdef GET_OPERAND_BIT_OFFSET
#undef GET_OPERAND_BIT_OFFSET

uint32_t LoongArchMCCodeEmitter::getOperandBitOffset(const MCInst &MI,
    unsigned OpNum,
    const MCSubtargetInfo &STI) const {
  switch (MI.getOpcode()) {
    case LoongArch::ERTN:
    case LoongArch::GTLBFLUSH:
    case LoongArch::TLBCLR:
    case LoongArch::TLBFILL:
    case LoongArch::TLBFLUSH:
    case LoongArch::TLBRD:
    case LoongArch::TLBSRCH:
    case LoongArch::TLBWR:
    case LoongArch::X86CLRTM:
    case LoongArch::X86DECTOP:
    case LoongArch::X86INCTOP:
    case LoongArch::X86SETTM: {
      break;
    }
    case LoongArch::SET_CFR_FALSE:
    case LoongArch::SET_CFR_TRUE: {
      switch (OpNum) {
      case 0:
        // op: cd
        return 0;
      }
      break;
    }
    case LoongArch::BREAK:
    case LoongArch::DBAR:
    case LoongArch::DBCL:
    case LoongArch::HVCL:
    case LoongArch::IBAR:
    case LoongArch::IDLE:
    case LoongArch::SYSCALL: {
      switch (OpNum) {
      case 0:
        // op: imm15
        return 0;
      }
      break;
    }
    case LoongArch::JISCR0:
    case LoongArch::JISCR1: {
      switch (OpNum) {
      case 0:
        // op: imm21
        return 0;
      }
      break;
    }
    case LoongArch::B:
    case LoongArch::BL: {
      switch (OpNum) {
      case 0:
        // op: imm26
        return 0;
      }
      break;
    }
    case LoongArch::X86MTTOP: {
      switch (OpNum) {
      case 0:
        // op: ptr
        return 5;
      }
      break;
    }
    case LoongArch::X86MFTOP: {
      switch (OpNum) {
      case 0:
        // op: rd
        return 0;
      }
      break;
    }
    case LoongArch::X86DEC_B:
    case LoongArch::X86DEC_D:
    case LoongArch::X86DEC_H:
    case LoongArch::X86DEC_W:
    case LoongArch::X86INC_B:
    case LoongArch::X86INC_D:
    case LoongArch::X86INC_H:
    case LoongArch::X86INC_W: {
      switch (OpNum) {
      case 0:
        // op: rj
        return 5;
      }
      break;
    }
    case LoongArch::INVTLB: {
      switch (OpNum) {
      case 0:
        // op: rk
        return 10;
      case 1:
        // op: rj
        return 5;
      case 2:
        // op: op
        return 0;
      }
      break;
    }
    case LoongArch::CSRRD:
    case LoongArch::GCSRRD: {
      switch (OpNum) {
      case 1:
        // op: csr_num
        return 10;
      case 0:
        // op: rd
        return 0;
      }
      break;
    }
    case LoongArch::FABS_D:
    case LoongArch::FABS_S:
    case LoongArch::FCLASS_D:
    case LoongArch::FCLASS_S:
    case LoongArch::FCVT_D_S:
    case LoongArch::FCVT_LD_D:
    case LoongArch::FCVT_S_D:
    case LoongArch::FCVT_UD_D:
    case LoongArch::FFINT_D_L:
    case LoongArch::FFINT_D_W:
    case LoongArch::FFINT_S_L:
    case LoongArch::FFINT_S_W:
    case LoongArch::FLOGB_D:
    case LoongArch::FLOGB_S:
    case LoongArch::FNEG_D:
    case LoongArch::FNEG_S:
    case LoongArch::FRECIPE_D:
    case LoongArch::FRECIPE_S:
    case LoongArch::FRECIP_D:
    case LoongArch::FRECIP_S:
    case LoongArch::FRINT_D:
    case LoongArch::FRINT_S:
    case LoongArch::FRSQRTE_D:
    case LoongArch::FRSQRTE_S:
    case LoongArch::FRSQRT_D:
    case LoongArch::FRSQRT_S:
    case LoongArch::FSQRT_D:
    case LoongArch::FSQRT_S:
    case LoongArch::FTINTRM_L_D:
    case LoongArch::FTINTRM_L_S:
    case LoongArch::FTINTRM_W_D:
    case LoongArch::FTINTRM_W_S:
    case LoongArch::FTINTRNE_L_D:
    case LoongArch::FTINTRNE_L_S:
    case LoongArch::FTINTRNE_W_D:
    case LoongArch::FTINTRNE_W_S:
    case LoongArch::FTINTRP_L_D:
    case LoongArch::FTINTRP_L_S:
    case LoongArch::FTINTRP_W_D:
    case LoongArch::FTINTRP_W_S:
    case LoongArch::FTINTRZ_L_D:
    case LoongArch::FTINTRZ_L_S:
    case LoongArch::FTINTRZ_W_D:
    case LoongArch::FTINTRZ_W_S:
    case LoongArch::FTINT_L_D:
    case LoongArch::FTINT_L_S:
    case LoongArch::FTINT_W_D:
    case LoongArch::FTINT_W_S: {
      switch (OpNum) {
      case 1:
        // op: fj
        return 5;
      case 0:
        // op: fd
        return 0;
      }
      break;
    }
    case LoongArch::VLDI: {
      switch (OpNum) {
      case 1:
        // op: imm13
        return 5;
      case 0:
        // op: vd
        return 0;
      }
      break;
    }
    case LoongArch::XVLDI: {
      switch (OpNum) {
      case 1:
        // op: imm13
        return 5;
      case 0:
        // op: xd
        return 0;
      }
      break;
    }
    case LoongArch::LU12I_W:
    case LoongArch::PCADDI:
    case LoongArch::PCADDU12I:
    case LoongArch::PCADDU18I:
    case LoongArch::PCALAU12I: {
      switch (OpNum) {
      case 1:
        // op: imm20
        return 5;
      case 0:
        // op: rd
        return 0;
      }
      break;
    }
    case LoongArch::BCEQZ:
    case LoongArch::BCNEZ: {
      switch (OpNum) {
      case 1:
        // op: imm21
        return 0;
      case 0:
        // op: cj
        return 5;
      }
      break;
    }
    case LoongArch::BEQZ:
    case LoongArch::BNEZ: {
      switch (OpNum) {
      case 1:
        // op: imm21
        return 0;
      case 0:
        // op: rj
        return 5;
      }
      break;
    }
    case LoongArch::X86RCLI_B:
    case LoongArch::X86RCRI_B:
    case LoongArch::X86ROTLI_B:
    case LoongArch::X86ROTRI_B:
    case LoongArch::X86SLLI_B:
    case LoongArch::X86SRAI_B:
    case LoongArch::X86SRLI_B: {
      switch (OpNum) {
      case 1:
        // op: imm3
        return 10;
      case 0:
        // op: rj
        return 5;
      }
      break;
    }
    case LoongArch::SETARMJ:
    case LoongArch::SETX86J: {
      switch (OpNum) {
      case 1:
        // op: imm4
        return 10;
      case 0:
        // op: rd
        return 0;
      }
      break;
    }
    case LoongArch::ARMMOV_D:
    case LoongArch::ARMMOV_W:
    case LoongArch::ARMNOT_W:
    case LoongArch::ARMRRX_W:
    case LoongArch::X86RCLI_H:
    case LoongArch::X86RCRI_H:
    case LoongArch::X86ROTLI_H:
    case LoongArch::X86ROTRI_H:
    case LoongArch::X86SLLI_H:
    case LoongArch::X86SRAI_H:
    case LoongArch::X86SRLI_H: {
      switch (OpNum) {
      case 1:
        // op: imm4
        return 10;
      case 0:
        // op: rj
        return 5;
      }
      break;
    }
    case LoongArch::ARMROTRI_W:
    case LoongArch::ARMSLLI_W:
    case LoongArch::ARMSRAI_W:
    case LoongArch::ARMSRLI_W: {
      switch (OpNum) {
      case 1:
        // op: imm5
        return 10;
      case 0:
        // op: rj
        return 5;
      case 2:
        // op: imm4
        return 0;
      }
      break;
    }
    case LoongArch::X86RCLI_W:
    case LoongArch::X86RCRI_W:
    case LoongArch::X86ROTLI_W:
    case LoongArch::X86ROTRI_W:
    case LoongArch::X86SLLI_W:
    case LoongArch::X86SRAI_W:
    case LoongArch::X86SRLI_W: {
      switch (OpNum) {
      case 1:
        // op: imm5
        return 10;
      case 0:
        // op: rj
        return 5;
      }
      break;
    }
    case LoongArch::X86RCLI_D:
    case LoongArch::X86RCRI_D:
    case LoongArch::X86ROTLI_D:
    case LoongArch::X86ROTRI_D:
    case LoongArch::X86SLLI_D:
    case LoongArch::X86SRAI_D:
    case LoongArch::X86SRLI_D: {
      switch (OpNum) {
      case 1:
        // op: imm6
        return 10;
      case 0:
        // op: rj
        return 5;
      }
      break;
    }
    case LoongArch::ARMMFFLAG:
    case LoongArch::ARMMTFLAG:
    case LoongArch::X86MFFLAG:
    case LoongArch::X86MTFLAG: {
      switch (OpNum) {
      case 1:
        // op: imm8
        return 10;
      case 0:
        // op: rd
        return 0;
      }
      break;
    }
    case LoongArch::BITREV_4B:
    case LoongArch::BITREV_8B:
    case LoongArch::BITREV_D:
    case LoongArch::BITREV_W:
    case LoongArch::CLO_D:
    case LoongArch::CLO_W:
    case LoongArch::CLZ_D:
    case LoongArch::CLZ_W:
    case LoongArch::CPUCFG:
    case LoongArch::CTO_D:
    case LoongArch::CTO_W:
    case LoongArch::CTZ_D:
    case LoongArch::CTZ_W:
    case LoongArch::EXT_W_B:
    case LoongArch::EXT_W_H:
    case LoongArch::IOCSRRD_B:
    case LoongArch::IOCSRRD_D:
    case LoongArch::IOCSRRD_H:
    case LoongArch::IOCSRRD_W:
    case LoongArch::IOCSRWR_B:
    case LoongArch::IOCSRWR_D:
    case LoongArch::IOCSRWR_H:
    case LoongArch::IOCSRWR_W:
    case LoongArch::LLACQ_D:
    case LoongArch::LLACQ_W:
    case LoongArch::RDTIMEH_W:
    case LoongArch::RDTIMEL_W:
    case LoongArch::RDTIME_D:
    case LoongArch::REVB_2H:
    case LoongArch::REVB_2W:
    case LoongArch::REVB_4H:
    case LoongArch::REVB_D:
    case LoongArch::REVH_2W:
    case LoongArch::REVH_D:
    case LoongArch::SETX86LOOPE:
    case LoongArch::SETX86LOOPNE: {
      switch (OpNum) {
      case 1:
        // op: rj
        return 5;
      case 0:
        // op: rd
        return 0;
      }
      break;
    }
    case LoongArch::MOVGR2SCR: {
      switch (OpNum) {
      case 1:
        // op: rj
        return 5;
      case 0:
        // op: sd
        return 0;
      }
      break;
    }
    case LoongArch::VREPLGR2VR_B:
    case LoongArch::VREPLGR2VR_D:
    case LoongArch::VREPLGR2VR_H:
    case LoongArch::VREPLGR2VR_W: {
      switch (OpNum) {
      case 1:
        // op: rj
        return 5;
      case 0:
        // op: vd
        return 0;
      }
      break;
    }
    case LoongArch::XVREPLGR2VR_B:
    case LoongArch::XVREPLGR2VR_D:
    case LoongArch::XVREPLGR2VR_H:
    case LoongArch::XVREPLGR2VR_W: {
      switch (OpNum) {
      case 1:
        // op: rj
        return 5;
      case 0:
        // op: xd
        return 0;
      }
      break;
    }
    case LoongArch::ASRTGT_D:
    case LoongArch::ASRTLE_D:
    case LoongArch::X86ADC_B:
    case LoongArch::X86ADC_D:
    case LoongArch::X86ADC_H:
    case LoongArch::X86ADC_W:
    case LoongArch::X86ADD_B:
    case LoongArch::X86ADD_D:
    case LoongArch::X86ADD_DU:
    case LoongArch::X86ADD_H:
    case LoongArch::X86ADD_W:
    case LoongArch::X86ADD_WU:
    case LoongArch::X86AND_B:
    case LoongArch::X86AND_D:
    case LoongArch::X86AND_H:
    case LoongArch::X86AND_W:
    case LoongArch::X86MUL_B:
    case LoongArch::X86MUL_BU:
    case LoongArch::X86MUL_D:
    case LoongArch::X86MUL_DU:
    case LoongArch::X86MUL_H:
    case LoongArch::X86MUL_HU:
    case LoongArch::X86MUL_W:
    case LoongArch::X86MUL_WU:
    case LoongArch::X86OR_B:
    case LoongArch::X86OR_D:
    case LoongArch::X86OR_H:
    case LoongArch::X86OR_W:
    case LoongArch::X86RCL_B:
    case LoongArch::X86RCL_D:
    case LoongArch::X86RCL_H:
    case LoongArch::X86RCL_W:
    case LoongArch::X86RCR_B:
    case LoongArch::X86RCR_D:
    case LoongArch::X86RCR_H:
    case LoongArch::X86RCR_W:
    case LoongArch::X86ROTL_B:
    case LoongArch::X86ROTL_D:
    case LoongArch::X86ROTL_H:
    case LoongArch::X86ROTL_W:
    case LoongArch::X86ROTR_B:
    case LoongArch::X86ROTR_D:
    case LoongArch::X86ROTR_H:
    case LoongArch::X86ROTR_W:
    case LoongArch::X86SBC_B:
    case LoongArch::X86SBC_D:
    case LoongArch::X86SBC_H:
    case LoongArch::X86SBC_W:
    case LoongArch::X86SLL_B:
    case LoongArch::X86SLL_D:
    case LoongArch::X86SLL_H:
    case LoongArch::X86SLL_W:
    case LoongArch::X86SRA_B:
    case LoongArch::X86SRA_D:
    case LoongArch::X86SRA_H:
    case LoongArch::X86SRA_W:
    case LoongArch::X86SRL_B:
    case LoongArch::X86SRL_D:
    case LoongArch::X86SRL_H:
    case LoongArch::X86SRL_W:
    case LoongArch::X86SUB_B:
    case LoongArch::X86SUB_D:
    case LoongArch::X86SUB_DU:
    case LoongArch::X86SUB_H:
    case LoongArch::X86SUB_W:
    case LoongArch::X86SUB_WU:
    case LoongArch::X86XOR_B:
    case LoongArch::X86XOR_D:
    case LoongArch::X86XOR_H:
    case LoongArch::X86XOR_W: {
      switch (OpNum) {
      case 1:
        // op: rk
        return 10;
      case 0:
        // op: rj
        return 5;
      }
      break;
    }
    case LoongArch::AMADD_B:
    case LoongArch::AMADD_D:
    case LoongArch::AMADD_H:
    case LoongArch::AMADD_W:
    case LoongArch::AMADD__DB_B:
    case LoongArch::AMADD__DB_D:
    case LoongArch::AMADD__DB_H:
    case LoongArch::AMADD__DB_W:
    case LoongArch::AMAND_D:
    case LoongArch::AMAND_W:
    case LoongArch::AMAND__DB_D:
    case LoongArch::AMAND__DB_W:
    case LoongArch::AMCAS_B:
    case LoongArch::AMCAS_D:
    case LoongArch::AMCAS_H:
    case LoongArch::AMCAS_W:
    case LoongArch::AMCAS__DB_B:
    case LoongArch::AMCAS__DB_D:
    case LoongArch::AMCAS__DB_H:
    case LoongArch::AMCAS__DB_W:
    case LoongArch::AMMAX_D:
    case LoongArch::AMMAX_DU:
    case LoongArch::AMMAX_W:
    case LoongArch::AMMAX_WU:
    case LoongArch::AMMAX__DB_D:
    case LoongArch::AMMAX__DB_DU:
    case LoongArch::AMMAX__DB_W:
    case LoongArch::AMMAX__DB_WU:
    case LoongArch::AMMIN_D:
    case LoongArch::AMMIN_DU:
    case LoongArch::AMMIN_W:
    case LoongArch::AMMIN_WU:
    case LoongArch::AMMIN__DB_D:
    case LoongArch::AMMIN__DB_DU:
    case LoongArch::AMMIN__DB_W:
    case LoongArch::AMMIN__DB_WU:
    case LoongArch::AMOR_D:
    case LoongArch::AMOR_W:
    case LoongArch::AMOR__DB_D:
    case LoongArch::AMOR__DB_W:
    case LoongArch::AMSWAP_B:
    case LoongArch::AMSWAP_D:
    case LoongArch::AMSWAP_H:
    case LoongArch::AMSWAP_W:
    case LoongArch::AMSWAP__DB_B:
    case LoongArch::AMSWAP__DB_D:
    case LoongArch::AMSWAP__DB_H:
    case LoongArch::AMSWAP__DB_W:
    case LoongArch::AMXOR_D:
    case LoongArch::AMXOR_W:
    case LoongArch::AMXOR__DB_D:
    case LoongArch::AMXOR__DB_W: {
      switch (OpNum) {
      case 1:
        // op: rk
        return 10;
      case 2:
        // op: rj
        return 5;
      case 0:
        // op: rd
        return 0;
      }
      break;
    }
    case LoongArch::LDPTE: {
      switch (OpNum) {
      case 1:
        // op: seq
        return 10;
      case 0:
        // op: rj
        return 5;
      }
      break;
    }
    case LoongArch::MOVSCR2GR: {
      switch (OpNum) {
      case 1:
        // op: sj
        return 5;
      case 0:
        // op: rd
        return 0;
      }
      break;
    }
    case LoongArch::FMOV_D:
    case LoongArch::FMOV_S:
    case LoongArch::MOVCF2FR_xS:
    case LoongArch::MOVCF2GR:
    case LoongArch::MOVFCSR2GR:
    case LoongArch::MOVFR2CF_xS:
    case LoongArch::MOVFR2GR_D:
    case LoongArch::MOVFR2GR_S:
    case LoongArch::MOVFR2GR_S_64:
    case LoongArch::MOVFRH2GR_S:
    case LoongArch::MOVGR2CF:
    case LoongArch::MOVGR2FCSR:
    case LoongArch::MOVGR2FR_D:
    case LoongArch::MOVGR2FR_W:
    case LoongArch::MOVGR2FR_W_64: {
      switch (OpNum) {
      case 1:
        // op: src
        return 5;
      case 0:
        // op: dst
        return 0;
      }
      break;
    }
    case LoongArch::VSETALLNEZ_B:
    case LoongArch::VSETALLNEZ_D:
    case LoongArch::VSETALLNEZ_H:
    case LoongArch::VSETALLNEZ_W:
    case LoongArch::VSETANYEQZ_B:
    case LoongArch::VSETANYEQZ_D:
    case LoongArch::VSETANYEQZ_H:
    case LoongArch::VSETANYEQZ_W:
    case LoongArch::VSETEQZ_V:
    case LoongArch::VSETNEZ_V: {
      switch (OpNum) {
      case 1:
        // op: vj
        return 5;
      case 0:
        // op: cd
        return 0;
      }
      break;
    }
    case LoongArch::VCLO_B:
    case LoongArch::VCLO_D:
    case LoongArch::VCLO_H:
    case LoongArch::VCLO_W:
    case LoongArch::VCLZ_B:
    case LoongArch::VCLZ_D:
    case LoongArch::VCLZ_H:
    case LoongArch::VCLZ_W:
    case LoongArch::VEXTH_DU_WU:
    case LoongArch::VEXTH_D_W:
    case LoongArch::VEXTH_HU_BU:
    case LoongArch::VEXTH_H_B:
    case LoongArch::VEXTH_QU_DU:
    case LoongArch::VEXTH_Q_D:
    case LoongArch::VEXTH_WU_HU:
    case LoongArch::VEXTH_W_H:
    case LoongArch::VEXTL_QU_DU:
    case LoongArch::VEXTL_Q_D:
    case LoongArch::VFCLASS_D:
    case LoongArch::VFCLASS_S:
    case LoongArch::VFCVTH_D_S:
    case LoongArch::VFCVTH_S_H:
    case LoongArch::VFCVTL_D_S:
    case LoongArch::VFCVTL_S_H:
    case LoongArch::VFFINTH_D_W:
    case LoongArch::VFFINTL_D_W:
    case LoongArch::VFFINT_D_L:
    case LoongArch::VFFINT_D_LU:
    case LoongArch::VFFINT_S_W:
    case LoongArch::VFFINT_S_WU:
    case LoongArch::VFLOGB_D:
    case LoongArch::VFLOGB_S:
    case LoongArch::VFRECIPE_D:
    case LoongArch::VFRECIPE_S:
    case LoongArch::VFRECIP_D:
    case LoongArch::VFRECIP_S:
    case LoongArch::VFRINTRM_D:
    case LoongArch::VFRINTRM_S:
    case LoongArch::VFRINTRNE_D:
    case LoongArch::VFRINTRNE_S:
    case LoongArch::VFRINTRP_D:
    case LoongArch::VFRINTRP_S:
    case LoongArch::VFRINTRZ_D:
    case LoongArch::VFRINTRZ_S:
    case LoongArch::VFRINT_D:
    case LoongArch::VFRINT_S:
    case LoongArch::VFRSQRTE_D:
    case LoongArch::VFRSQRTE_S:
    case LoongArch::VFRSQRT_D:
    case LoongArch::VFRSQRT_S:
    case LoongArch::VFSQRT_D:
    case LoongArch::VFSQRT_S:
    case LoongArch::VFTINTH_L_S:
    case LoongArch::VFTINTL_L_S:
    case LoongArch::VFTINTRMH_L_S:
    case LoongArch::VFTINTRML_L_S:
    case LoongArch::VFTINTRM_L_D:
    case LoongArch::VFTINTRM_W_S:
    case LoongArch::VFTINTRNEH_L_S:
    case LoongArch::VFTINTRNEL_L_S:
    case LoongArch::VFTINTRNE_L_D:
    case LoongArch::VFTINTRNE_W_S:
    case LoongArch::VFTINTRPH_L_S:
    case LoongArch::VFTINTRPL_L_S:
    case LoongArch::VFTINTRP_L_D:
    case LoongArch::VFTINTRP_W_S:
    case LoongArch::VFTINTRZH_L_S:
    case LoongArch::VFTINTRZL_L_S:
    case LoongArch::VFTINTRZ_LU_D:
    case LoongArch::VFTINTRZ_L_D:
    case LoongArch::VFTINTRZ_WU_S:
    case LoongArch::VFTINTRZ_W_S:
    case LoongArch::VFTINT_LU_D:
    case LoongArch::VFTINT_L_D:
    case LoongArch::VFTINT_WU_S:
    case LoongArch::VFTINT_W_S:
    case LoongArch::VMSKGEZ_B:
    case LoongArch::VMSKLTZ_B:
    case LoongArch::VMSKLTZ_D:
    case LoongArch::VMSKLTZ_H:
    case LoongArch::VMSKLTZ_W:
    case LoongArch::VMSKNZ_B:
    case LoongArch::VNEG_B:
    case LoongArch::VNEG_D:
    case LoongArch::VNEG_H:
    case LoongArch::VNEG_W:
    case LoongArch::VPCNT_B:
    case LoongArch::VPCNT_D:
    case LoongArch::VPCNT_H:
    case LoongArch::VPCNT_W: {
      switch (OpNum) {
      case 1:
        // op: vj
        return 5;
      case 0:
        // op: vd
        return 0;
      }
      break;
    }
    case LoongArch::XVSETALLNEZ_B:
    case LoongArch::XVSETALLNEZ_D:
    case LoongArch::XVSETALLNEZ_H:
    case LoongArch::XVSETALLNEZ_W:
    case LoongArch::XVSETANYEQZ_B:
    case LoongArch::XVSETANYEQZ_D:
    case LoongArch::XVSETANYEQZ_H:
    case LoongArch::XVSETANYEQZ_W:
    case LoongArch::XVSETEQZ_V:
    case LoongArch::XVSETNEZ_V: {
      switch (OpNum) {
      case 1:
        // op: xj
        return 5;
      case 0:
        // op: cd
        return 0;
      }
      break;
    }
    case LoongArch::VEXT2XV_DU_BU:
    case LoongArch::VEXT2XV_DU_HU:
    case LoongArch::VEXT2XV_DU_WU:
    case LoongArch::VEXT2XV_D_B:
    case LoongArch::VEXT2XV_D_H:
    case LoongArch::VEXT2XV_D_W:
    case LoongArch::VEXT2XV_HU_BU:
    case LoongArch::VEXT2XV_H_B:
    case LoongArch::VEXT2XV_WU_BU:
    case LoongArch::VEXT2XV_WU_HU:
    case LoongArch::VEXT2XV_W_B:
    case LoongArch::VEXT2XV_W_H:
    case LoongArch::XVCLO_B:
    case LoongArch::XVCLO_D:
    case LoongArch::XVCLO_H:
    case LoongArch::XVCLO_W:
    case LoongArch::XVCLZ_B:
    case LoongArch::XVCLZ_D:
    case LoongArch::XVCLZ_H:
    case LoongArch::XVCLZ_W:
    case LoongArch::XVEXTH_DU_WU:
    case LoongArch::XVEXTH_D_W:
    case LoongArch::XVEXTH_HU_BU:
    case LoongArch::XVEXTH_H_B:
    case LoongArch::XVEXTH_QU_DU:
    case LoongArch::XVEXTH_Q_D:
    case LoongArch::XVEXTH_WU_HU:
    case LoongArch::XVEXTH_W_H:
    case LoongArch::XVEXTL_QU_DU:
    case LoongArch::XVEXTL_Q_D:
    case LoongArch::XVFCLASS_D:
    case LoongArch::XVFCLASS_S:
    case LoongArch::XVFCVTH_D_S:
    case LoongArch::XVFCVTH_S_H:
    case LoongArch::XVFCVTL_D_S:
    case LoongArch::XVFCVTL_S_H:
    case LoongArch::XVFFINTH_D_W:
    case LoongArch::XVFFINTL_D_W:
    case LoongArch::XVFFINT_D_L:
    case LoongArch::XVFFINT_D_LU:
    case LoongArch::XVFFINT_S_W:
    case LoongArch::XVFFINT_S_WU:
    case LoongArch::XVFLOGB_D:
    case LoongArch::XVFLOGB_S:
    case LoongArch::XVFRECIPE_D:
    case LoongArch::XVFRECIPE_S:
    case LoongArch::XVFRECIP_D:
    case LoongArch::XVFRECIP_S:
    case LoongArch::XVFRINTRM_D:
    case LoongArch::XVFRINTRM_S:
    case LoongArch::XVFRINTRNE_D:
    case LoongArch::XVFRINTRNE_S:
    case LoongArch::XVFRINTRP_D:
    case LoongArch::XVFRINTRP_S:
    case LoongArch::XVFRINTRZ_D:
    case LoongArch::XVFRINTRZ_S:
    case LoongArch::XVFRINT_D:
    case LoongArch::XVFRINT_S:
    case LoongArch::XVFRSQRTE_D:
    case LoongArch::XVFRSQRTE_S:
    case LoongArch::XVFRSQRT_D:
    case LoongArch::XVFRSQRT_S:
    case LoongArch::XVFSQRT_D:
    case LoongArch::XVFSQRT_S:
    case LoongArch::XVFTINTH_L_S:
    case LoongArch::XVFTINTL_L_S:
    case LoongArch::XVFTINTRMH_L_S:
    case LoongArch::XVFTINTRML_L_S:
    case LoongArch::XVFTINTRM_L_D:
    case LoongArch::XVFTINTRM_W_S:
    case LoongArch::XVFTINTRNEH_L_S:
    case LoongArch::XVFTINTRNEL_L_S:
    case LoongArch::XVFTINTRNE_L_D:
    case LoongArch::XVFTINTRNE_W_S:
    case LoongArch::XVFTINTRPH_L_S:
    case LoongArch::XVFTINTRPL_L_S:
    case LoongArch::XVFTINTRP_L_D:
    case LoongArch::XVFTINTRP_W_S:
    case LoongArch::XVFTINTRZH_L_S:
    case LoongArch::XVFTINTRZL_L_S:
    case LoongArch::XVFTINTRZ_LU_D:
    case LoongArch::XVFTINTRZ_L_D:
    case LoongArch::XVFTINTRZ_WU_S:
    case LoongArch::XVFTINTRZ_W_S:
    case LoongArch::XVFTINT_LU_D:
    case LoongArch::XVFTINT_L_D:
    case LoongArch::XVFTINT_WU_S:
    case LoongArch::XVFTINT_W_S:
    case LoongArch::XVMSKGEZ_B:
    case LoongArch::XVMSKLTZ_B:
    case LoongArch::XVMSKLTZ_D:
    case LoongArch::XVMSKLTZ_H:
    case LoongArch::XVMSKLTZ_W:
    case LoongArch::XVMSKNZ_B:
    case LoongArch::XVNEG_B:
    case LoongArch::XVNEG_D:
    case LoongArch::XVNEG_H:
    case LoongArch::XVNEG_W:
    case LoongArch::XVPCNT_B:
    case LoongArch::XVPCNT_D:
    case LoongArch::XVPCNT_H:
    case LoongArch::XVPCNT_W:
    case LoongArch::XVREPLVE0_B:
    case LoongArch::XVREPLVE0_D:
    case LoongArch::XVREPLVE0_H:
    case LoongArch::XVREPLVE0_Q:
    case LoongArch::XVREPLVE0_W: {
      switch (OpNum) {
      case 1:
        // op: xj
        return 5;
      case 0:
        // op: xd
        return 0;
      }
      break;
    }
    case LoongArch::CSRWR:
    case LoongArch::GCSRWR: {
      switch (OpNum) {
      case 2:
        // op: csr_num
        return 10;
      case 1:
        // op: rd
        return 0;
      }
      break;
    }
    case LoongArch::FCMP_CAF_D:
    case LoongArch::FCMP_CAF_S:
    case LoongArch::FCMP_CEQ_D:
    case LoongArch::FCMP_CEQ_S:
    case LoongArch::FCMP_CLE_D:
    case LoongArch::FCMP_CLE_S:
    case LoongArch::FCMP_CLT_D:
    case LoongArch::FCMP_CLT_S:
    case LoongArch::FCMP_CNE_D:
    case LoongArch::FCMP_CNE_S:
    case LoongArch::FCMP_COR_D:
    case LoongArch::FCMP_COR_S:
    case LoongArch::FCMP_CUEQ_D:
    case LoongArch::FCMP_CUEQ_S:
    case LoongArch::FCMP_CULE_D:
    case LoongArch::FCMP_CULE_S:
    case LoongArch::FCMP_CULT_D:
    case LoongArch::FCMP_CULT_S:
    case LoongArch::FCMP_CUNE_D:
    case LoongArch::FCMP_CUNE_S:
    case LoongArch::FCMP_CUN_D:
    case LoongArch::FCMP_CUN_S:
    case LoongArch::FCMP_SAF_D:
    case LoongArch::FCMP_SAF_S:
    case LoongArch::FCMP_SEQ_D:
    case LoongArch::FCMP_SEQ_S:
    case LoongArch::FCMP_SLE_D:
    case LoongArch::FCMP_SLE_S:
    case LoongArch::FCMP_SLT_D:
    case LoongArch::FCMP_SLT_S:
    case LoongArch::FCMP_SNE_D:
    case LoongArch::FCMP_SNE_S:
    case LoongArch::FCMP_SOR_D:
    case LoongArch::FCMP_SOR_S:
    case LoongArch::FCMP_SUEQ_D:
    case LoongArch::FCMP_SUEQ_S:
    case LoongArch::FCMP_SULE_D:
    case LoongArch::FCMP_SULE_S:
    case LoongArch::FCMP_SULT_D:
    case LoongArch::FCMP_SULT_S:
    case LoongArch::FCMP_SUNE_D:
    case LoongArch::FCMP_SUNE_S:
    case LoongArch::FCMP_SUN_D:
    case LoongArch::FCMP_SUN_S: {
      switch (OpNum) {
      case 2:
        // op: fk
        return 10;
      case 1:
        // op: fj
        return 5;
      case 0:
        // op: cd
        return 0;
      }
      break;
    }
    case LoongArch::FADD_D:
    case LoongArch::FADD_S:
    case LoongArch::FCOPYSIGN_D:
    case LoongArch::FCOPYSIGN_S:
    case LoongArch::FCVT_D_LD:
    case LoongArch::FDIV_D:
    case LoongArch::FDIV_S:
    case LoongArch::FMAXA_D:
    case LoongArch::FMAXA_S:
    case LoongArch::FMAX_D:
    case LoongArch::FMAX_S:
    case LoongArch::FMINA_D:
    case LoongArch::FMINA_S:
    case LoongArch::FMIN_D:
    case LoongArch::FMIN_S:
    case LoongArch::FMUL_D:
    case LoongArch::FMUL_S:
    case LoongArch::FSCALEB_D:
    case LoongArch::FSCALEB_S:
    case LoongArch::FSUB_D:
    case LoongArch::FSUB_S: {
      switch (OpNum) {
      case 2:
        // op: fk
        return 10;
      case 1:
        // op: fj
        return 5;
      case 0:
        // op: fd
        return 0;
      }
      break;
    }
    case LoongArch::VPICKVE2GR_D:
    case LoongArch::VPICKVE2GR_DU: {
      switch (OpNum) {
      case 2:
        // op: imm1
        return 10;
      case 1:
        // op: vj
        return 5;
      case 0:
        // op: rd
        return 0;
      }
      break;
    }
    case LoongArch::VREPLVEI_D: {
      switch (OpNum) {
      case 2:
        // op: imm1
        return 10;
      case 1:
        // op: vj
        return 5;
      case 0:
        // op: vd
        return 0;
      }
      break;
    }
    case LoongArch::XVREPL128VEI_D: {
      switch (OpNum) {
      case 2:
        // op: imm1
        return 10;
      case 1:
        // op: xj
        return 5;
      case 0:
        // op: xd
        return 0;
      }
      break;
    }
    case LoongArch::VLDREPL_W: {
      switch (OpNum) {
      case 2:
        // op: imm10
        return 10;
      case 1:
        // op: rj
        return 5;
      case 0:
        // op: vd
        return 0;
      }
      break;
    }
    case LoongArch::XVLDREPL_W: {
      switch (OpNum) {
      case 2:
        // op: imm10
        return 10;
      case 1:
        // op: rj
        return 5;
      case 0:
        // op: xd
        return 0;
      }
      break;
    }
    case LoongArch::VLDREPL_H: {
      switch (OpNum) {
      case 2:
        // op: imm11
        return 10;
      case 1:
        // op: rj
        return 5;
      case 0:
        // op: vd
        return 0;
      }
      break;
    }
    case LoongArch::XVLDREPL_H: {
      switch (OpNum) {
      case 2:
        // op: imm11
        return 10;
      case 1:
        // op: rj
        return 5;
      case 0:
        // op: xd
        return 0;
      }
      break;
    }
    case LoongArch::FLD_D:
    case LoongArch::FLD_S:
    case LoongArch::FST_D:
    case LoongArch::FST_S: {
      switch (OpNum) {
      case 2:
        // op: imm12
        return 10;
      case 1:
        // op: rj
        return 5;
      case 0:
        // op: fd
        return 0;
      }
      break;
    }
    case LoongArch::PRELD: {
      switch (OpNum) {
      case 2:
        // op: imm12
        return 10;
      case 1:
        // op: rj
        return 5;
      case 0:
        // op: imm5
        return 0;
      }
      break;
    }
    case LoongArch::CACOP: {
      switch (OpNum) {
      case 2:
        // op: imm12
        return 10;
      case 1:
        // op: rj
        return 5;
      case 0:
        // op: op
        return 0;
      }
      break;
    }
    case LoongArch::ADDI_D:
    case LoongArch::ADDI_W:
    case LoongArch::ANDI:
    case LoongArch::LDL_D:
    case LoongArch::LDL_W:
    case LoongArch::LDR_D:
    case LoongArch::LDR_W:
    case LoongArch::LD_B:
    case LoongArch::LD_BU:
    case LoongArch::LD_D:
    case LoongArch::LD_H:
    case LoongArch::LD_HU:
    case LoongArch::LD_W:
    case LoongArch::LD_WU:
    case LoongArch::LU52I_D:
    case LoongArch::ORI:
    case LoongArch::SLTI:
    case LoongArch::SLTUI:
    case LoongArch::STL_D:
    case LoongArch::STL_W:
    case LoongArch::STR_D:
    case LoongArch::STR_W:
    case LoongArch::ST_B:
    case LoongArch::ST_D:
    case LoongArch::ST_H:
    case LoongArch::ST_W:
    case LoongArch::XORI: {
      switch (OpNum) {
      case 2:
        // op: imm12
        return 10;
      case 1:
        // op: rj
        return 5;
      case 0:
        // op: rd
        return 0;
      }
      break;
    }
    case LoongArch::VLD:
    case LoongArch::VLDREPL_B:
    case LoongArch::VST: {
      switch (OpNum) {
      case 2:
        // op: imm12
        return 10;
      case 1:
        // op: rj
        return 5;
      case 0:
        // op: vd
        return 0;
      }
      break;
    }
    case LoongArch::XVLD:
    case LoongArch::XVLDREPL_B:
    case LoongArch::XVST: {
      switch (OpNum) {
      case 2:
        // op: imm12
        return 10;
      case 1:
        // op: rj
        return 5;
      case 0:
        // op: xd
        return 0;
      }
      break;
    }
    case LoongArch::LDPTR_D:
    case LoongArch::LDPTR_W:
    case LoongArch::LL_D:
    case LoongArch::LL_W:
    case LoongArch::STPTR_D:
    case LoongArch::STPTR_W: {
      switch (OpNum) {
      case 2:
        // op: imm14
        return 10;
      case 1:
        // op: rj
        return 5;
      case 0:
        // op: rd
        return 0;
      }
      break;
    }
    case LoongArch::BEQ:
    case LoongArch::BGE:
    case LoongArch::BGEU:
    case LoongArch::BLT:
    case LoongArch::BLTU:
    case LoongArch::BNE: {
      switch (OpNum) {
      case 2:
        // op: imm16
        return 10;
      case 0:
        // op: rj
        return 5;
      case 1:
        // op: rd
        return 0;
      }
      break;
    }
    case LoongArch::ADDU16I_D:
    case LoongArch::JIRL: {
      switch (OpNum) {
      case 2:
        // op: imm16
        return 10;
      case 1:
        // op: rj
        return 5;
      case 0:
        // op: rd
        return 0;
      }
      break;
    }
    case LoongArch::VPICKVE2GR_W:
    case LoongArch::VPICKVE2GR_WU: {
      switch (OpNum) {
      case 2:
        // op: imm2
        return 10;
      case 1:
        // op: vj
        return 5;
      case 0:
        // op: rd
        return 0;
      }
      break;
    }
    case LoongArch::VREPLVEI_W: {
      switch (OpNum) {
      case 2:
        // op: imm2
        return 10;
      case 1:
        // op: vj
        return 5;
      case 0:
        // op: vd
        return 0;
      }
      break;
    }
    case LoongArch::XVPICKVE2GR_D:
    case LoongArch::XVPICKVE2GR_DU: {
      switch (OpNum) {
      case 2:
        // op: imm2
        return 10;
      case 1:
        // op: xj
        return 5;
      case 0:
        // op: rd
        return 0;
      }
      break;
    }
    case LoongArch::XVPICKVE_D:
    case LoongArch::XVREPL128VEI_W: {
      switch (OpNum) {
      case 2:
        // op: imm2
        return 10;
      case 1:
        // op: xj
        return 5;
      case 0:
        // op: xd
        return 0;
      }
      break;
    }
    case LoongArch::LU32I_D: {
      switch (OpNum) {
      case 2:
        // op: imm20
        return 5;
      case 1:
        // op: rd
        return 0;
      }
      break;
    }
    case LoongArch::RCRI_B:
    case LoongArch::ROTRI_B: {
      switch (OpNum) {
      case 2:
        // op: imm3
        return 10;
      case 1:
        // op: rj
        return 5;
      case 0:
        // op: rd
        return 0;
      }
      break;
    }
    case LoongArch::VPICKVE2GR_H:
    case LoongArch::VPICKVE2GR_HU: {
      switch (OpNum) {
      case 2:
        // op: imm3
        return 10;
      case 1:
        // op: vj
        return 5;
      case 0:
        // op: rd
        return 0;
      }
      break;
    }
    case LoongArch::VBITCLRI_B:
    case LoongArch::VBITREVI_B:
    case LoongArch::VBITSETI_B:
    case LoongArch::VREPLVEI_H:
    case LoongArch::VROTRI_B:
    case LoongArch::VSAT_B:
    case LoongArch::VSAT_BU:
    case LoongArch::VSLLI_B:
    case LoongArch::VSLLWIL_HU_BU:
    case LoongArch::VSLLWIL_H_B:
    case LoongArch::VSRAI_B:
    case LoongArch::VSRARI_B:
    case LoongArch::VSRLI_B:
    case LoongArch::VSRLRI_B: {
      switch (OpNum) {
      case 2:
        // op: imm3
        return 10;
      case 1:
        // op: vj
        return 5;
      case 0:
        // op: vd
        return 0;
      }
      break;
    }
    case LoongArch::XVPICKVE2GR_W:
    case LoongArch::XVPICKVE2GR_WU: {
      switch (OpNum) {
      case 2:
        // op: imm3
        return 10;
      case 1:
        // op: xj
        return 5;
      case 0:
        // op: rd
        return 0;
      }
      break;
    }
    case LoongArch::XVBITCLRI_B:
    case LoongArch::XVBITREVI_B:
    case LoongArch::XVBITSETI_B:
    case LoongArch::XVPICKVE_W:
    case LoongArch::XVREPL128VEI_H:
    case LoongArch::XVROTRI_B:
    case LoongArch::XVSAT_B:
    case LoongArch::XVSAT_BU:
    case LoongArch::XVSLLI_B:
    case LoongArch::XVSLLWIL_HU_BU:
    case LoongArch::XVSLLWIL_H_B:
    case LoongArch::XVSRAI_B:
    case LoongArch::XVSRARI_B:
    case LoongArch::XVSRLI_B:
    case LoongArch::XVSRLRI_B: {
      switch (OpNum) {
      case 2:
        // op: imm3
        return 10;
      case 1:
        // op: xj
        return 5;
      case 0:
        // op: xd
        return 0;
      }
      break;
    }
    case LoongArch::ARMADC_W:
    case LoongArch::ARMADD_W:
    case LoongArch::ARMAND_W:
    case LoongArch::ARMOR_W:
    case LoongArch::ARMROTR_W:
    case LoongArch::ARMSBC_W:
    case LoongArch::ARMSLL_W:
    case LoongArch::ARMSRA_W:
    case LoongArch::ARMSRL_W:
    case LoongArch::ARMSUB_W:
    case LoongArch::ARMXOR_W: {
      switch (OpNum) {
      case 2:
        // op: imm4
        return 0;
      case 1:
        // op: rk
        return 10;
      case 0:
        // op: rj
        return 5;
      }
      break;
    }
    case LoongArch::ARMMOVE:
    case LoongArch::RCRI_H:
    case LoongArch::ROTRI_H: {
      switch (OpNum) {
      case 2:
        // op: imm4
        return 10;
      case 1:
        // op: rj
        return 5;
      case 0:
        // op: rd
        return 0;
      }
      break;
    }
    case LoongArch::VPICKVE2GR_B:
    case LoongArch::VPICKVE2GR_BU: {
      switch (OpNum) {
      case 2:
        // op: imm4
        return 10;
      case 1:
        // op: vj
        return 5;
      case 0:
        // op: rd
        return 0;
      }
      break;
    }
    case LoongArch::VBITCLRI_H:
    case LoongArch::VBITREVI_H:
    case LoongArch::VBITSETI_H:
    case LoongArch::VREPLVEI_B:
    case LoongArch::VROTRI_H:
    case LoongArch::VSAT_H:
    case LoongArch::VSAT_HU:
    case LoongArch::VSLLI_H:
    case LoongArch::VSLLWIL_WU_HU:
    case LoongArch::VSLLWIL_W_H:
    case LoongArch::VSRAI_H:
    case LoongArch::VSRARI_H:
    case LoongArch::VSRLI_H:
    case LoongArch::VSRLRI_H: {
      switch (OpNum) {
      case 2:
        // op: imm4
        return 10;
      case 1:
        // op: vj
        return 5;
      case 0:
        // op: vd
        return 0;
      }
      break;
    }
    case LoongArch::XVBITCLRI_H:
    case LoongArch::XVBITREVI_H:
    case LoongArch::XVBITSETI_H:
    case LoongArch::XVREPL128VEI_B:
    case LoongArch::XVROTRI_H:
    case LoongArch::XVSAT_H:
    case LoongArch::XVSAT_HU:
    case LoongArch::XVSLLI_H:
    case LoongArch::XVSLLWIL_WU_HU:
    case LoongArch::XVSLLWIL_W_H:
    case LoongArch::XVSRAI_H:
    case LoongArch::XVSRARI_H:
    case LoongArch::XVSRLI_H:
    case LoongArch::XVSRLRI_H: {
      switch (OpNum) {
      case 2:
        // op: imm4
        return 10;
      case 1:
        // op: xj
        return 5;
      case 0:
        // op: xd
        return 0;
      }
      break;
    }
    case LoongArch::ADDU12I_D:
    case LoongArch::ADDU12I_W:
    case LoongArch::RCRI_W:
    case LoongArch::ROTRI_W:
    case LoongArch::SLLI_W:
    case LoongArch::SRAI_W:
    case LoongArch::SRLI_W: {
      switch (OpNum) {
      case 2:
        // op: imm5
        return 10;
      case 1:
        // op: rj
        return 5;
      case 0:
        // op: rd
        return 0;
      }
      break;
    }
    case LoongArch::VADDI_BU:
    case LoongArch::VADDI_DU:
    case LoongArch::VADDI_HU:
    case LoongArch::VADDI_WU:
    case LoongArch::VBITCLRI_W:
    case LoongArch::VBITREVI_W:
    case LoongArch::VBITSETI_W:
    case LoongArch::VBSLL_V:
    case LoongArch::VBSRL_V:
    case LoongArch::VMAXI_B:
    case LoongArch::VMAXI_BU:
    case LoongArch::VMAXI_D:
    case LoongArch::VMAXI_DU:
    case LoongArch::VMAXI_H:
    case LoongArch::VMAXI_HU:
    case LoongArch::VMAXI_W:
    case LoongArch::VMAXI_WU:
    case LoongArch::VMINI_B:
    case LoongArch::VMINI_BU:
    case LoongArch::VMINI_D:
    case LoongArch::VMINI_DU:
    case LoongArch::VMINI_H:
    case LoongArch::VMINI_HU:
    case LoongArch::VMINI_W:
    case LoongArch::VMINI_WU:
    case LoongArch::VROTRI_W:
    case LoongArch::VSAT_W:
    case LoongArch::VSAT_WU:
    case LoongArch::VSEQI_B:
    case LoongArch::VSEQI_D:
    case LoongArch::VSEQI_H:
    case LoongArch::VSEQI_W:
    case LoongArch::VSLEI_B:
    case LoongArch::VSLEI_BU:
    case LoongArch::VSLEI_D:
    case LoongArch::VSLEI_DU:
    case LoongArch::VSLEI_H:
    case LoongArch::VSLEI_HU:
    case LoongArch::VSLEI_W:
    case LoongArch::VSLEI_WU:
    case LoongArch::VSLLI_W:
    case LoongArch::VSLLWIL_DU_WU:
    case LoongArch::VSLLWIL_D_W:
    case LoongArch::VSLTI_B:
    case LoongArch::VSLTI_BU:
    case LoongArch::VSLTI_D:
    case LoongArch::VSLTI_DU:
    case LoongArch::VSLTI_H:
    case LoongArch::VSLTI_HU:
    case LoongArch::VSLTI_W:
    case LoongArch::VSLTI_WU:
    case LoongArch::VSRAI_W:
    case LoongArch::VSRARI_W:
    case LoongArch::VSRLI_W:
    case LoongArch::VSRLRI_W:
    case LoongArch::VSUBI_BU:
    case LoongArch::VSUBI_DU:
    case LoongArch::VSUBI_HU:
    case LoongArch::VSUBI_WU: {
      switch (OpNum) {
      case 2:
        // op: imm5
        return 10;
      case 1:
        // op: vj
        return 5;
      case 0:
        // op: vd
        return 0;
      }
      break;
    }
    case LoongArch::XVADDI_BU:
    case LoongArch::XVADDI_DU:
    case LoongArch::XVADDI_HU:
    case LoongArch::XVADDI_WU:
    case LoongArch::XVBITCLRI_W:
    case LoongArch::XVBITREVI_W:
    case LoongArch::XVBITSETI_W:
    case LoongArch::XVBSLL_V:
    case LoongArch::XVBSRL_V:
    case LoongArch::XVHSELI_D:
    case LoongArch::XVMAXI_B:
    case LoongArch::XVMAXI_BU:
    case LoongArch::XVMAXI_D:
    case LoongArch::XVMAXI_DU:
    case LoongArch::XVMAXI_H:
    case LoongArch::XVMAXI_HU:
    case LoongArch::XVMAXI_W:
    case LoongArch::XVMAXI_WU:
    case LoongArch::XVMINI_B:
    case LoongArch::XVMINI_BU:
    case LoongArch::XVMINI_D:
    case LoongArch::XVMINI_DU:
    case LoongArch::XVMINI_H:
    case LoongArch::XVMINI_HU:
    case LoongArch::XVMINI_W:
    case LoongArch::XVMINI_WU:
    case LoongArch::XVROTRI_W:
    case LoongArch::XVSAT_W:
    case LoongArch::XVSAT_WU:
    case LoongArch::XVSEQI_B:
    case LoongArch::XVSEQI_D:
    case LoongArch::XVSEQI_H:
    case LoongArch::XVSEQI_W:
    case LoongArch::XVSLEI_B:
    case LoongArch::XVSLEI_BU:
    case LoongArch::XVSLEI_D:
    case LoongArch::XVSLEI_DU:
    case LoongArch::XVSLEI_H:
    case LoongArch::XVSLEI_HU:
    case LoongArch::XVSLEI_W:
    case LoongArch::XVSLEI_WU:
    case LoongArch::XVSLLI_W:
    case LoongArch::XVSLLWIL_DU_WU:
    case LoongArch::XVSLLWIL_D_W:
    case LoongArch::XVSLTI_B:
    case LoongArch::XVSLTI_BU:
    case LoongArch::XVSLTI_D:
    case LoongArch::XVSLTI_DU:
    case LoongArch::XVSLTI_H:
    case LoongArch::XVSLTI_HU:
    case LoongArch::XVSLTI_W:
    case LoongArch::XVSLTI_WU:
    case LoongArch::XVSRAI_W:
    case LoongArch::XVSRARI_W:
    case LoongArch::XVSRLI_W:
    case LoongArch::XVSRLRI_W:
    case LoongArch::XVSUBI_BU:
    case LoongArch::XVSUBI_DU:
    case LoongArch::XVSUBI_HU:
    case LoongArch::XVSUBI_WU: {
      switch (OpNum) {
      case 2:
        // op: imm5
        return 10;
      case 1:
        // op: xj
        return 5;
      case 0:
        // op: xd
        return 0;
      }
      break;
    }
    case LoongArch::RCRI_D:
    case LoongArch::ROTRI_D:
    case LoongArch::SLLI_D:
    case LoongArch::SRAI_D:
    case LoongArch::SRLI_D: {
      switch (OpNum) {
      case 2:
        // op: imm6
        return 10;
      case 1:
        // op: rj
        return 5;
      case 0:
        // op: rd
        return 0;
      }
      break;
    }
    case LoongArch::VBITCLRI_D:
    case LoongArch::VBITREVI_D:
    case LoongArch::VBITSETI_D:
    case LoongArch::VROTRI_D:
    case LoongArch::VSAT_D:
    case LoongArch::VSAT_DU:
    case LoongArch::VSLLI_D:
    case LoongArch::VSRAI_D:
    case LoongArch::VSRARI_D:
    case LoongArch::VSRLI_D:
    case LoongArch::VSRLRI_D: {
      switch (OpNum) {
      case 2:
        // op: imm6
        return 10;
      case 1:
        // op: vj
        return 5;
      case 0:
        // op: vd
        return 0;
      }
      break;
    }
    case LoongArch::XVBITCLRI_D:
    case LoongArch::XVBITREVI_D:
    case LoongArch::XVBITSETI_D:
    case LoongArch::XVROTRI_D:
    case LoongArch::XVSAT_D:
    case LoongArch::XVSAT_DU:
    case LoongArch::XVSLLI_D:
    case LoongArch::XVSRAI_D:
    case LoongArch::XVSRARI_D:
    case LoongArch::XVSRLI_D:
    case LoongArch::XVSRLRI_D: {
      switch (OpNum) {
      case 2:
        // op: imm6
        return 10;
      case 1:
        // op: xj
        return 5;
      case 0:
        // op: xd
        return 0;
      }
      break;
    }
    case LoongArch::X86SETTAG: {
      switch (OpNum) {
      case 2:
        // op: imm8
        return 10;
      case 1:
        // op: imm5
        return 5;
      case 0:
        // op: rd
        return 0;
      }
      break;
    }
    case LoongArch::LDDIR: {
      switch (OpNum) {
      case 2:
        // op: imm8
        return 10;
      case 1:
        // op: rj
        return 5;
      case 0:
        // op: rd
        return 0;
      }
      break;
    }
    case LoongArch::VANDI_B:
    case LoongArch::VNORI_B:
    case LoongArch::VORI_B:
    case LoongArch::VSHUF4I_B:
    case LoongArch::VSHUF4I_H:
    case LoongArch::VSHUF4I_W:
    case LoongArch::VXORI_B: {
      switch (OpNum) {
      case 2:
        // op: imm8
        return 10;
      case 1:
        // op: vj
        return 5;
      case 0:
        // op: vd
        return 0;
      }
      break;
    }
    case LoongArch::XVANDI_B:
    case LoongArch::XVNORI_B:
    case LoongArch::XVORI_B:
    case LoongArch::XVPERMI_D:
    case LoongArch::XVSHUF4I_B:
    case LoongArch::XVSHUF4I_H:
    case LoongArch::XVSHUF4I_W:
    case LoongArch::XVXORI_B: {
      switch (OpNum) {
      case 2:
        // op: imm8
        return 10;
      case 1:
        // op: xj
        return 5;
      case 0:
        // op: xd
        return 0;
      }
      break;
    }
    case LoongArch::VLDREPL_D: {
      switch (OpNum) {
      case 2:
        // op: imm9
        return 10;
      case 1:
        // op: rj
        return 5;
      case 0:
        // op: vd
        return 0;
      }
      break;
    }
    case LoongArch::XVLDREPL_D: {
      switch (OpNum) {
      case 2:
        // op: imm9
        return 10;
      case 1:
        // op: rj
        return 5;
      case 0:
        // op: xd
        return 0;
      }
      break;
    }
    case LoongArch::BSTRPICK_D: {
      switch (OpNum) {
      case 2:
        // op: msbd
        return 16;
      case 3:
        // op: lsbd
        return 10;
      case 1:
        // op: rj
        return 5;
      case 0:
        // op: rd
        return 0;
      }
      break;
    }
    case LoongArch::BSTRPICK_W: {
      switch (OpNum) {
      case 2:
        // op: msbw
        return 16;
      case 3:
        // op: lsbw
        return 10;
      case 1:
        // op: rj
        return 5;
      case 0:
        // op: rd
        return 0;
      }
      break;
    }
    case LoongArch::SCREL_D:
    case LoongArch::SCREL_W: {
      switch (OpNum) {
      case 2:
        // op: rj
        return 5;
      case 1:
        // op: rd
        return 0;
      }
      break;
    }
    case LoongArch::FLDGT_D:
    case LoongArch::FLDGT_S:
    case LoongArch::FLDLE_D:
    case LoongArch::FLDLE_S:
    case LoongArch::FLDX_D:
    case LoongArch::FLDX_S:
    case LoongArch::FSTGT_D:
    case LoongArch::FSTGT_S:
    case LoongArch::FSTLE_D:
    case LoongArch::FSTLE_S:
    case LoongArch::FSTX_D:
    case LoongArch::FSTX_S: {
      switch (OpNum) {
      case 2:
        // op: rk
        return 10;
      case 1:
        // op: rj
        return 5;
      case 0:
        // op: fd
        return 0;
      }
      break;
    }
    case LoongArch::PRELDX: {
      switch (OpNum) {
      case 2:
        // op: rk
        return 10;
      case 1:
        // op: rj
        return 5;
      case 0:
        // op: imm5
        return 0;
      }
      break;
    }
    case LoongArch::ADC_B:
    case LoongArch::ADC_D:
    case LoongArch::ADC_H:
    case LoongArch::ADC_W:
    case LoongArch::ADD_D:
    case LoongArch::ADD_W:
    case LoongArch::AND:
    case LoongArch::ANDN:
    case LoongArch::CRCC_W_B_W:
    case LoongArch::CRCC_W_D_W:
    case LoongArch::CRCC_W_H_W:
    case LoongArch::CRCC_W_W_W:
    case LoongArch::CRC_W_B_W:
    case LoongArch::CRC_W_D_W:
    case LoongArch::CRC_W_H_W:
    case LoongArch::CRC_W_W_W:
    case LoongArch::DIV_D:
    case LoongArch::DIV_DU:
    case LoongArch::DIV_W:
    case LoongArch::DIV_WU:
    case LoongArch::LDGT_B:
    case LoongArch::LDGT_D:
    case LoongArch::LDGT_H:
    case LoongArch::LDGT_W:
    case LoongArch::LDLE_B:
    case LoongArch::LDLE_D:
    case LoongArch::LDLE_H:
    case LoongArch::LDLE_W:
    case LoongArch::LDX_B:
    case LoongArch::LDX_BU:
    case LoongArch::LDX_D:
    case LoongArch::LDX_H:
    case LoongArch::LDX_HU:
    case LoongArch::LDX_W:
    case LoongArch::LDX_WU:
    case LoongArch::MASKEQZ:
    case LoongArch::MASKNEZ:
    case LoongArch::MOD_D:
    case LoongArch::MOD_DU:
    case LoongArch::MOD_W:
    case LoongArch::MOD_WU:
    case LoongArch::MULH_D:
    case LoongArch::MULH_DU:
    case LoongArch::MULH_W:
    case LoongArch::MULH_WU:
    case LoongArch::MULW_D_W:
    case LoongArch::MULW_D_WU:
    case LoongArch::MUL_D:
    case LoongArch::MUL_W:
    case LoongArch::NOR:
    case LoongArch::OR:
    case LoongArch::ORN:
    case LoongArch::RCR_B:
    case LoongArch::RCR_D:
    case LoongArch::RCR_H:
    case LoongArch::RCR_W:
    case LoongArch::ROTR_B:
    case LoongArch::ROTR_D:
    case LoongArch::ROTR_H:
    case LoongArch::ROTR_W:
    case LoongArch::SBC_B:
    case LoongArch::SBC_D:
    case LoongArch::SBC_H:
    case LoongArch::SBC_W:
    case LoongArch::SLL_D:
    case LoongArch::SLL_W:
    case LoongArch::SLT:
    case LoongArch::SLTU:
    case LoongArch::SRA_D:
    case LoongArch::SRA_W:
    case LoongArch::SRL_D:
    case LoongArch::SRL_W:
    case LoongArch::STGT_B:
    case LoongArch::STGT_D:
    case LoongArch::STGT_H:
    case LoongArch::STGT_W:
    case LoongArch::STLE_B:
    case LoongArch::STLE_D:
    case LoongArch::STLE_H:
    case LoongArch::STLE_W:
    case LoongArch::STX_B:
    case LoongArch::STX_D:
    case LoongArch::STX_H:
    case LoongArch::STX_W:
    case LoongArch::SUB_D:
    case LoongArch::SUB_W:
    case LoongArch::XOR: {
      switch (OpNum) {
      case 2:
        // op: rk
        return 10;
      case 1:
        // op: rj
        return 5;
      case 0:
        // op: rd
        return 0;
      }
      break;
    }
    case LoongArch::VLDX:
    case LoongArch::VSTX: {
      switch (OpNum) {
      case 2:
        // op: rk
        return 10;
      case 1:
        // op: rj
        return 5;
      case 0:
        // op: vd
        return 0;
      }
      break;
    }
    case LoongArch::XVLDX:
    case LoongArch::XVSTX: {
      switch (OpNum) {
      case 2:
        // op: rk
        return 10;
      case 1:
        // op: rj
        return 5;
      case 0:
        // op: xd
        return 0;
      }
      break;
    }
    case LoongArch::VREPLVE_B:
    case LoongArch::VREPLVE_D:
    case LoongArch::VREPLVE_H:
    case LoongArch::VREPLVE_W: {
      switch (OpNum) {
      case 2:
        // op: rk
        return 10;
      case 1:
        // op: vj
        return 5;
      case 0:
        // op: vd
        return 0;
      }
      break;
    }
    case LoongArch::XVREPLVE_B:
    case LoongArch::XVREPLVE_D:
    case LoongArch::XVREPLVE_H:
    case LoongArch::XVREPLVE_W: {
      switch (OpNum) {
      case 2:
        // op: rk
        return 10;
      case 1:
        // op: xj
        return 5;
      case 0:
        // op: xd
        return 0;
      }
      break;
    }
    case LoongArch::SC_Q: {
      switch (OpNum) {
      case 2:
        // op: rk
        return 10;
      case 3:
        // op: rj
        return 5;
      case 1:
        // op: rd
        return 0;
      }
      break;
    }
    case LoongArch::MOVGR2FRH_W: {
      switch (OpNum) {
      case 2:
        // op: src
        return 5;
      case 1:
        // op: dst
        return 0;
      }
      break;
    }
    case LoongArch::VABSD_B:
    case LoongArch::VABSD_BU:
    case LoongArch::VABSD_D:
    case LoongArch::VABSD_DU:
    case LoongArch::VABSD_H:
    case LoongArch::VABSD_HU:
    case LoongArch::VABSD_W:
    case LoongArch::VABSD_WU:
    case LoongArch::VADDA_B:
    case LoongArch::VADDA_D:
    case LoongArch::VADDA_H:
    case LoongArch::VADDA_W:
    case LoongArch::VADDWEV_D_W:
    case LoongArch::VADDWEV_D_WU:
    case LoongArch::VADDWEV_D_WU_W:
    case LoongArch::VADDWEV_H_B:
    case LoongArch::VADDWEV_H_BU:
    case LoongArch::VADDWEV_H_BU_B:
    case LoongArch::VADDWEV_Q_D:
    case LoongArch::VADDWEV_Q_DU:
    case LoongArch::VADDWEV_Q_DU_D:
    case LoongArch::VADDWEV_W_H:
    case LoongArch::VADDWEV_W_HU:
    case LoongArch::VADDWEV_W_HU_H:
    case LoongArch::VADDWOD_D_W:
    case LoongArch::VADDWOD_D_WU:
    case LoongArch::VADDWOD_D_WU_W:
    case LoongArch::VADDWOD_H_B:
    case LoongArch::VADDWOD_H_BU:
    case LoongArch::VADDWOD_H_BU_B:
    case LoongArch::VADDWOD_Q_D:
    case LoongArch::VADDWOD_Q_DU:
    case LoongArch::VADDWOD_Q_DU_D:
    case LoongArch::VADDWOD_W_H:
    case LoongArch::VADDWOD_W_HU:
    case LoongArch::VADDWOD_W_HU_H:
    case LoongArch::VADD_B:
    case LoongArch::VADD_D:
    case LoongArch::VADD_H:
    case LoongArch::VADD_Q:
    case LoongArch::VADD_W:
    case LoongArch::VANDN_V:
    case LoongArch::VAND_V:
    case LoongArch::VAVGR_B:
    case LoongArch::VAVGR_BU:
    case LoongArch::VAVGR_D:
    case LoongArch::VAVGR_DU:
    case LoongArch::VAVGR_H:
    case LoongArch::VAVGR_HU:
    case LoongArch::VAVGR_W:
    case LoongArch::VAVGR_WU:
    case LoongArch::VAVG_B:
    case LoongArch::VAVG_BU:
    case LoongArch::VAVG_D:
    case LoongArch::VAVG_DU:
    case LoongArch::VAVG_H:
    case LoongArch::VAVG_HU:
    case LoongArch::VAVG_W:
    case LoongArch::VAVG_WU:
    case LoongArch::VBITCLR_B:
    case LoongArch::VBITCLR_D:
    case LoongArch::VBITCLR_H:
    case LoongArch::VBITCLR_W:
    case LoongArch::VBITREV_B:
    case LoongArch::VBITREV_D:
    case LoongArch::VBITREV_H:
    case LoongArch::VBITREV_W:
    case LoongArch::VBITSET_B:
    case LoongArch::VBITSET_D:
    case LoongArch::VBITSET_H:
    case LoongArch::VBITSET_W:
    case LoongArch::VDIV_B:
    case LoongArch::VDIV_BU:
    case LoongArch::VDIV_D:
    case LoongArch::VDIV_DU:
    case LoongArch::VDIV_H:
    case LoongArch::VDIV_HU:
    case LoongArch::VDIV_W:
    case LoongArch::VDIV_WU:
    case LoongArch::VFADD_D:
    case LoongArch::VFADD_S:
    case LoongArch::VFCMP_CAF_D:
    case LoongArch::VFCMP_CAF_S:
    case LoongArch::VFCMP_CEQ_D:
    case LoongArch::VFCMP_CEQ_S:
    case LoongArch::VFCMP_CLE_D:
    case LoongArch::VFCMP_CLE_S:
    case LoongArch::VFCMP_CLT_D:
    case LoongArch::VFCMP_CLT_S:
    case LoongArch::VFCMP_CNE_D:
    case LoongArch::VFCMP_CNE_S:
    case LoongArch::VFCMP_COR_D:
    case LoongArch::VFCMP_COR_S:
    case LoongArch::VFCMP_CUEQ_D:
    case LoongArch::VFCMP_CUEQ_S:
    case LoongArch::VFCMP_CULE_D:
    case LoongArch::VFCMP_CULE_S:
    case LoongArch::VFCMP_CULT_D:
    case LoongArch::VFCMP_CULT_S:
    case LoongArch::VFCMP_CUNE_D:
    case LoongArch::VFCMP_CUNE_S:
    case LoongArch::VFCMP_CUN_D:
    case LoongArch::VFCMP_CUN_S:
    case LoongArch::VFCMP_SAF_D:
    case LoongArch::VFCMP_SAF_S:
    case LoongArch::VFCMP_SEQ_D:
    case LoongArch::VFCMP_SEQ_S:
    case LoongArch::VFCMP_SLE_D:
    case LoongArch::VFCMP_SLE_S:
    case LoongArch::VFCMP_SLT_D:
    case LoongArch::VFCMP_SLT_S:
    case LoongArch::VFCMP_SNE_D:
    case LoongArch::VFCMP_SNE_S:
    case LoongArch::VFCMP_SOR_D:
    case LoongArch::VFCMP_SOR_S:
    case LoongArch::VFCMP_SUEQ_D:
    case LoongArch::VFCMP_SUEQ_S:
    case LoongArch::VFCMP_SULE_D:
    case LoongArch::VFCMP_SULE_S:
    case LoongArch::VFCMP_SULT_D:
    case LoongArch::VFCMP_SULT_S:
    case LoongArch::VFCMP_SUNE_D:
    case LoongArch::VFCMP_SUNE_S:
    case LoongArch::VFCMP_SUN_D:
    case LoongArch::VFCMP_SUN_S:
    case LoongArch::VFCVT_H_S:
    case LoongArch::VFCVT_S_D:
    case LoongArch::VFDIV_D:
    case LoongArch::VFDIV_S:
    case LoongArch::VFFINT_S_L:
    case LoongArch::VFMAXA_D:
    case LoongArch::VFMAXA_S:
    case LoongArch::VFMAX_D:
    case LoongArch::VFMAX_S:
    case LoongArch::VFMINA_D:
    case LoongArch::VFMINA_S:
    case LoongArch::VFMIN_D:
    case LoongArch::VFMIN_S:
    case LoongArch::VFMUL_D:
    case LoongArch::VFMUL_S:
    case LoongArch::VFSUB_D:
    case LoongArch::VFSUB_S:
    case LoongArch::VFTINTRM_W_D:
    case LoongArch::VFTINTRNE_W_D:
    case LoongArch::VFTINTRP_W_D:
    case LoongArch::VFTINTRZ_W_D:
    case LoongArch::VFTINT_W_D:
    case LoongArch::VHADDW_DU_WU:
    case LoongArch::VHADDW_D_W:
    case LoongArch::VHADDW_HU_BU:
    case LoongArch::VHADDW_H_B:
    case LoongArch::VHADDW_QU_DU:
    case LoongArch::VHADDW_Q_D:
    case LoongArch::VHADDW_WU_HU:
    case LoongArch::VHADDW_W_H:
    case LoongArch::VHSUBW_DU_WU:
    case LoongArch::VHSUBW_D_W:
    case LoongArch::VHSUBW_HU_BU:
    case LoongArch::VHSUBW_H_B:
    case LoongArch::VHSUBW_QU_DU:
    case LoongArch::VHSUBW_Q_D:
    case LoongArch::VHSUBW_WU_HU:
    case LoongArch::VHSUBW_W_H:
    case LoongArch::VILVH_B:
    case LoongArch::VILVH_D:
    case LoongArch::VILVH_H:
    case LoongArch::VILVH_W:
    case LoongArch::VILVL_B:
    case LoongArch::VILVL_D:
    case LoongArch::VILVL_H:
    case LoongArch::VILVL_W:
    case LoongArch::VMAX_B:
    case LoongArch::VMAX_BU:
    case LoongArch::VMAX_D:
    case LoongArch::VMAX_DU:
    case LoongArch::VMAX_H:
    case LoongArch::VMAX_HU:
    case LoongArch::VMAX_W:
    case LoongArch::VMAX_WU:
    case LoongArch::VMIN_B:
    case LoongArch::VMIN_BU:
    case LoongArch::VMIN_D:
    case LoongArch::VMIN_DU:
    case LoongArch::VMIN_H:
    case LoongArch::VMIN_HU:
    case LoongArch::VMIN_W:
    case LoongArch::VMIN_WU:
    case LoongArch::VMOD_B:
    case LoongArch::VMOD_BU:
    case LoongArch::VMOD_D:
    case LoongArch::VMOD_DU:
    case LoongArch::VMOD_H:
    case LoongArch::VMOD_HU:
    case LoongArch::VMOD_W:
    case LoongArch::VMOD_WU:
    case LoongArch::VMUH_B:
    case LoongArch::VMUH_BU:
    case LoongArch::VMUH_D:
    case LoongArch::VMUH_DU:
    case LoongArch::VMUH_H:
    case LoongArch::VMUH_HU:
    case LoongArch::VMUH_W:
    case LoongArch::VMUH_WU:
    case LoongArch::VMULWEV_D_W:
    case LoongArch::VMULWEV_D_WU:
    case LoongArch::VMULWEV_D_WU_W:
    case LoongArch::VMULWEV_H_B:
    case LoongArch::VMULWEV_H_BU:
    case LoongArch::VMULWEV_H_BU_B:
    case LoongArch::VMULWEV_Q_D:
    case LoongArch::VMULWEV_Q_DU:
    case LoongArch::VMULWEV_Q_DU_D:
    case LoongArch::VMULWEV_W_H:
    case LoongArch::VMULWEV_W_HU:
    case LoongArch::VMULWEV_W_HU_H:
    case LoongArch::VMULWOD_D_W:
    case LoongArch::VMULWOD_D_WU:
    case LoongArch::VMULWOD_D_WU_W:
    case LoongArch::VMULWOD_H_B:
    case LoongArch::VMULWOD_H_BU:
    case LoongArch::VMULWOD_H_BU_B:
    case LoongArch::VMULWOD_Q_D:
    case LoongArch::VMULWOD_Q_DU:
    case LoongArch::VMULWOD_Q_DU_D:
    case LoongArch::VMULWOD_W_H:
    case LoongArch::VMULWOD_W_HU:
    case LoongArch::VMULWOD_W_HU_H:
    case LoongArch::VMUL_B:
    case LoongArch::VMUL_D:
    case LoongArch::VMUL_H:
    case LoongArch::VMUL_W:
    case LoongArch::VNOR_V:
    case LoongArch::VORN_V:
    case LoongArch::VOR_V:
    case LoongArch::VPACKEV_B:
    case LoongArch::VPACKEV_D:
    case LoongArch::VPACKEV_H:
    case LoongArch::VPACKEV_W:
    case LoongArch::VPACKOD_B:
    case LoongArch::VPACKOD_D:
    case LoongArch::VPACKOD_H:
    case LoongArch::VPACKOD_W:
    case LoongArch::VPICKEV_B:
    case LoongArch::VPICKEV_D:
    case LoongArch::VPICKEV_H:
    case LoongArch::VPICKEV_W:
    case LoongArch::VPICKOD_B:
    case LoongArch::VPICKOD_D:
    case LoongArch::VPICKOD_H:
    case LoongArch::VPICKOD_W:
    case LoongArch::VROTR_B:
    case LoongArch::VROTR_D:
    case LoongArch::VROTR_H:
    case LoongArch::VROTR_W:
    case LoongArch::VSADD_B:
    case LoongArch::VSADD_BU:
    case LoongArch::VSADD_D:
    case LoongArch::VSADD_DU:
    case LoongArch::VSADD_H:
    case LoongArch::VSADD_HU:
    case LoongArch::VSADD_W:
    case LoongArch::VSADD_WU:
    case LoongArch::VSEQ_B:
    case LoongArch::VSEQ_D:
    case LoongArch::VSEQ_H:
    case LoongArch::VSEQ_W:
    case LoongArch::VSIGNCOV_B:
    case LoongArch::VSIGNCOV_D:
    case LoongArch::VSIGNCOV_H:
    case LoongArch::VSIGNCOV_W:
    case LoongArch::VSLE_B:
    case LoongArch::VSLE_BU:
    case LoongArch::VSLE_D:
    case LoongArch::VSLE_DU:
    case LoongArch::VSLE_H:
    case LoongArch::VSLE_HU:
    case LoongArch::VSLE_W:
    case LoongArch::VSLE_WU:
    case LoongArch::VSLL_B:
    case LoongArch::VSLL_D:
    case LoongArch::VSLL_H:
    case LoongArch::VSLL_W:
    case LoongArch::VSLT_B:
    case LoongArch::VSLT_BU:
    case LoongArch::VSLT_D:
    case LoongArch::VSLT_DU:
    case LoongArch::VSLT_H:
    case LoongArch::VSLT_HU:
    case LoongArch::VSLT_W:
    case LoongArch::VSLT_WU:
    case LoongArch::VSRAN_B_H:
    case LoongArch::VSRAN_H_W:
    case LoongArch::VSRAN_W_D:
    case LoongArch::VSRARN_B_H:
    case LoongArch::VSRARN_H_W:
    case LoongArch::VSRARN_W_D:
    case LoongArch::VSRAR_B:
    case LoongArch::VSRAR_D:
    case LoongArch::VSRAR_H:
    case LoongArch::VSRAR_W:
    case LoongArch::VSRA_B:
    case LoongArch::VSRA_D:
    case LoongArch::VSRA_H:
    case LoongArch::VSRA_W:
    case LoongArch::VSRLN_B_H:
    case LoongArch::VSRLN_H_W:
    case LoongArch::VSRLN_W_D:
    case LoongArch::VSRLRN_B_H:
    case LoongArch::VSRLRN_H_W:
    case LoongArch::VSRLRN_W_D:
    case LoongArch::VSRLR_B:
    case LoongArch::VSRLR_D:
    case LoongArch::VSRLR_H:
    case LoongArch::VSRLR_W:
    case LoongArch::VSRL_B:
    case LoongArch::VSRL_D:
    case LoongArch::VSRL_H:
    case LoongArch::VSRL_W:
    case LoongArch::VSSRAN_BU_H:
    case LoongArch::VSSRAN_B_H:
    case LoongArch::VSSRAN_HU_W:
    case LoongArch::VSSRAN_H_W:
    case LoongArch::VSSRAN_WU_D:
    case LoongArch::VSSRAN_W_D:
    case LoongArch::VSSRARN_BU_H:
    case LoongArch::VSSRARN_B_H:
    case LoongArch::VSSRARN_HU_W:
    case LoongArch::VSSRARN_H_W:
    case LoongArch::VSSRARN_WU_D:
    case LoongArch::VSSRARN_W_D:
    case LoongArch::VSSRLN_BU_H:
    case LoongArch::VSSRLN_B_H:
    case LoongArch::VSSRLN_HU_W:
    case LoongArch::VSSRLN_H_W:
    case LoongArch::VSSRLN_WU_D:
    case LoongArch::VSSRLN_W_D:
    case LoongArch::VSSRLRN_BU_H:
    case LoongArch::VSSRLRN_B_H:
    case LoongArch::VSSRLRN_HU_W:
    case LoongArch::VSSRLRN_H_W:
    case LoongArch::VSSRLRN_WU_D:
    case LoongArch::VSSRLRN_W_D:
    case LoongArch::VSSUB_B:
    case LoongArch::VSSUB_BU:
    case LoongArch::VSSUB_D:
    case LoongArch::VSSUB_DU:
    case LoongArch::VSSUB_H:
    case LoongArch::VSSUB_HU:
    case LoongArch::VSSUB_W:
    case LoongArch::VSSUB_WU:
    case LoongArch::VSUBWEV_D_W:
    case LoongArch::VSUBWEV_D_WU:
    case LoongArch::VSUBWEV_H_B:
    case LoongArch::VSUBWEV_H_BU:
    case LoongArch::VSUBWEV_Q_D:
    case LoongArch::VSUBWEV_Q_DU:
    case LoongArch::VSUBWEV_W_H:
    case LoongArch::VSUBWEV_W_HU:
    case LoongArch::VSUBWOD_D_W:
    case LoongArch::VSUBWOD_D_WU:
    case LoongArch::VSUBWOD_H_B:
    case LoongArch::VSUBWOD_H_BU:
    case LoongArch::VSUBWOD_Q_D:
    case LoongArch::VSUBWOD_Q_DU:
    case LoongArch::VSUBWOD_W_H:
    case LoongArch::VSUBWOD_W_HU:
    case LoongArch::VSUB_B:
    case LoongArch::VSUB_D:
    case LoongArch::VSUB_H:
    case LoongArch::VSUB_Q:
    case LoongArch::VSUB_W:
    case LoongArch::VXOR_V: {
      switch (OpNum) {
      case 2:
        // op: vk
        return 10;
      case 1:
        // op: vj
        return 5;
      case 0:
        // op: vd
        return 0;
      }
      break;
    }
    case LoongArch::XVABSD_B:
    case LoongArch::XVABSD_BU:
    case LoongArch::XVABSD_D:
    case LoongArch::XVABSD_DU:
    case LoongArch::XVABSD_H:
    case LoongArch::XVABSD_HU:
    case LoongArch::XVABSD_W:
    case LoongArch::XVABSD_WU:
    case LoongArch::XVADDA_B:
    case LoongArch::XVADDA_D:
    case LoongArch::XVADDA_H:
    case LoongArch::XVADDA_W:
    case LoongArch::XVADDWEV_D_W:
    case LoongArch::XVADDWEV_D_WU:
    case LoongArch::XVADDWEV_D_WU_W:
    case LoongArch::XVADDWEV_H_B:
    case LoongArch::XVADDWEV_H_BU:
    case LoongArch::XVADDWEV_H_BU_B:
    case LoongArch::XVADDWEV_Q_D:
    case LoongArch::XVADDWEV_Q_DU:
    case LoongArch::XVADDWEV_Q_DU_D:
    case LoongArch::XVADDWEV_W_H:
    case LoongArch::XVADDWEV_W_HU:
    case LoongArch::XVADDWEV_W_HU_H:
    case LoongArch::XVADDWOD_D_W:
    case LoongArch::XVADDWOD_D_WU:
    case LoongArch::XVADDWOD_D_WU_W:
    case LoongArch::XVADDWOD_H_B:
    case LoongArch::XVADDWOD_H_BU:
    case LoongArch::XVADDWOD_H_BU_B:
    case LoongArch::XVADDWOD_Q_D:
    case LoongArch::XVADDWOD_Q_DU:
    case LoongArch::XVADDWOD_Q_DU_D:
    case LoongArch::XVADDWOD_W_H:
    case LoongArch::XVADDWOD_W_HU:
    case LoongArch::XVADDWOD_W_HU_H:
    case LoongArch::XVADD_B:
    case LoongArch::XVADD_D:
    case LoongArch::XVADD_H:
    case LoongArch::XVADD_Q:
    case LoongArch::XVADD_W:
    case LoongArch::XVANDN_V:
    case LoongArch::XVAND_V:
    case LoongArch::XVAVGR_B:
    case LoongArch::XVAVGR_BU:
    case LoongArch::XVAVGR_D:
    case LoongArch::XVAVGR_DU:
    case LoongArch::XVAVGR_H:
    case LoongArch::XVAVGR_HU:
    case LoongArch::XVAVGR_W:
    case LoongArch::XVAVGR_WU:
    case LoongArch::XVAVG_B:
    case LoongArch::XVAVG_BU:
    case LoongArch::XVAVG_D:
    case LoongArch::XVAVG_DU:
    case LoongArch::XVAVG_H:
    case LoongArch::XVAVG_HU:
    case LoongArch::XVAVG_W:
    case LoongArch::XVAVG_WU:
    case LoongArch::XVBITCLR_B:
    case LoongArch::XVBITCLR_D:
    case LoongArch::XVBITCLR_H:
    case LoongArch::XVBITCLR_W:
    case LoongArch::XVBITREV_B:
    case LoongArch::XVBITREV_D:
    case LoongArch::XVBITREV_H:
    case LoongArch::XVBITREV_W:
    case LoongArch::XVBITSET_B:
    case LoongArch::XVBITSET_D:
    case LoongArch::XVBITSET_H:
    case LoongArch::XVBITSET_W:
    case LoongArch::XVDIV_B:
    case LoongArch::XVDIV_BU:
    case LoongArch::XVDIV_D:
    case LoongArch::XVDIV_DU:
    case LoongArch::XVDIV_H:
    case LoongArch::XVDIV_HU:
    case LoongArch::XVDIV_W:
    case LoongArch::XVDIV_WU:
    case LoongArch::XVFADD_D:
    case LoongArch::XVFADD_S:
    case LoongArch::XVFCMP_CAF_D:
    case LoongArch::XVFCMP_CAF_S:
    case LoongArch::XVFCMP_CEQ_D:
    case LoongArch::XVFCMP_CEQ_S:
    case LoongArch::XVFCMP_CLE_D:
    case LoongArch::XVFCMP_CLE_S:
    case LoongArch::XVFCMP_CLT_D:
    case LoongArch::XVFCMP_CLT_S:
    case LoongArch::XVFCMP_CNE_D:
    case LoongArch::XVFCMP_CNE_S:
    case LoongArch::XVFCMP_COR_D:
    case LoongArch::XVFCMP_COR_S:
    case LoongArch::XVFCMP_CUEQ_D:
    case LoongArch::XVFCMP_CUEQ_S:
    case LoongArch::XVFCMP_CULE_D:
    case LoongArch::XVFCMP_CULE_S:
    case LoongArch::XVFCMP_CULT_D:
    case LoongArch::XVFCMP_CULT_S:
    case LoongArch::XVFCMP_CUNE_D:
    case LoongArch::XVFCMP_CUNE_S:
    case LoongArch::XVFCMP_CUN_D:
    case LoongArch::XVFCMP_CUN_S:
    case LoongArch::XVFCMP_SAF_D:
    case LoongArch::XVFCMP_SAF_S:
    case LoongArch::XVFCMP_SEQ_D:
    case LoongArch::XVFCMP_SEQ_S:
    case LoongArch::XVFCMP_SLE_D:
    case LoongArch::XVFCMP_SLE_S:
    case LoongArch::XVFCMP_SLT_D:
    case LoongArch::XVFCMP_SLT_S:
    case LoongArch::XVFCMP_SNE_D:
    case LoongArch::XVFCMP_SNE_S:
    case LoongArch::XVFCMP_SOR_D:
    case LoongArch::XVFCMP_SOR_S:
    case LoongArch::XVFCMP_SUEQ_D:
    case LoongArch::XVFCMP_SUEQ_S:
    case LoongArch::XVFCMP_SULE_D:
    case LoongArch::XVFCMP_SULE_S:
    case LoongArch::XVFCMP_SULT_D:
    case LoongArch::XVFCMP_SULT_S:
    case LoongArch::XVFCMP_SUNE_D:
    case LoongArch::XVFCMP_SUNE_S:
    case LoongArch::XVFCMP_SUN_D:
    case LoongArch::XVFCMP_SUN_S:
    case LoongArch::XVFCVT_H_S:
    case LoongArch::XVFCVT_S_D:
    case LoongArch::XVFDIV_D:
    case LoongArch::XVFDIV_S:
    case LoongArch::XVFFINT_S_L:
    case LoongArch::XVFMAXA_D:
    case LoongArch::XVFMAXA_S:
    case LoongArch::XVFMAX_D:
    case LoongArch::XVFMAX_S:
    case LoongArch::XVFMINA_D:
    case LoongArch::XVFMINA_S:
    case LoongArch::XVFMIN_D:
    case LoongArch::XVFMIN_S:
    case LoongArch::XVFMUL_D:
    case LoongArch::XVFMUL_S:
    case LoongArch::XVFSUB_D:
    case LoongArch::XVFSUB_S:
    case LoongArch::XVFTINTRM_W_D:
    case LoongArch::XVFTINTRNE_W_D:
    case LoongArch::XVFTINTRP_W_D:
    case LoongArch::XVFTINTRZ_W_D:
    case LoongArch::XVFTINT_W_D:
    case LoongArch::XVHADDW_DU_WU:
    case LoongArch::XVHADDW_D_W:
    case LoongArch::XVHADDW_HU_BU:
    case LoongArch::XVHADDW_H_B:
    case LoongArch::XVHADDW_QU_DU:
    case LoongArch::XVHADDW_Q_D:
    case LoongArch::XVHADDW_WU_HU:
    case LoongArch::XVHADDW_W_H:
    case LoongArch::XVHSUBW_DU_WU:
    case LoongArch::XVHSUBW_D_W:
    case LoongArch::XVHSUBW_HU_BU:
    case LoongArch::XVHSUBW_H_B:
    case LoongArch::XVHSUBW_QU_DU:
    case LoongArch::XVHSUBW_Q_D:
    case LoongArch::XVHSUBW_WU_HU:
    case LoongArch::XVHSUBW_W_H:
    case LoongArch::XVILVH_B:
    case LoongArch::XVILVH_D:
    case LoongArch::XVILVH_H:
    case LoongArch::XVILVH_W:
    case LoongArch::XVILVL_B:
    case LoongArch::XVILVL_D:
    case LoongArch::XVILVL_H:
    case LoongArch::XVILVL_W:
    case LoongArch::XVMAX_B:
    case LoongArch::XVMAX_BU:
    case LoongArch::XVMAX_D:
    case LoongArch::XVMAX_DU:
    case LoongArch::XVMAX_H:
    case LoongArch::XVMAX_HU:
    case LoongArch::XVMAX_W:
    case LoongArch::XVMAX_WU:
    case LoongArch::XVMIN_B:
    case LoongArch::XVMIN_BU:
    case LoongArch::XVMIN_D:
    case LoongArch::XVMIN_DU:
    case LoongArch::XVMIN_H:
    case LoongArch::XVMIN_HU:
    case LoongArch::XVMIN_W:
    case LoongArch::XVMIN_WU:
    case LoongArch::XVMOD_B:
    case LoongArch::XVMOD_BU:
    case LoongArch::XVMOD_D:
    case LoongArch::XVMOD_DU:
    case LoongArch::XVMOD_H:
    case LoongArch::XVMOD_HU:
    case LoongArch::XVMOD_W:
    case LoongArch::XVMOD_WU:
    case LoongArch::XVMUH_B:
    case LoongArch::XVMUH_BU:
    case LoongArch::XVMUH_D:
    case LoongArch::XVMUH_DU:
    case LoongArch::XVMUH_H:
    case LoongArch::XVMUH_HU:
    case LoongArch::XVMUH_W:
    case LoongArch::XVMUH_WU:
    case LoongArch::XVMULWEV_D_W:
    case LoongArch::XVMULWEV_D_WU:
    case LoongArch::XVMULWEV_D_WU_W:
    case LoongArch::XVMULWEV_H_B:
    case LoongArch::XVMULWEV_H_BU:
    case LoongArch::XVMULWEV_H_BU_B:
    case LoongArch::XVMULWEV_Q_D:
    case LoongArch::XVMULWEV_Q_DU:
    case LoongArch::XVMULWEV_Q_DU_D:
    case LoongArch::XVMULWEV_W_H:
    case LoongArch::XVMULWEV_W_HU:
    case LoongArch::XVMULWEV_W_HU_H:
    case LoongArch::XVMULWOD_D_W:
    case LoongArch::XVMULWOD_D_WU:
    case LoongArch::XVMULWOD_D_WU_W:
    case LoongArch::XVMULWOD_H_B:
    case LoongArch::XVMULWOD_H_BU:
    case LoongArch::XVMULWOD_H_BU_B:
    case LoongArch::XVMULWOD_Q_D:
    case LoongArch::XVMULWOD_Q_DU:
    case LoongArch::XVMULWOD_Q_DU_D:
    case LoongArch::XVMULWOD_W_H:
    case LoongArch::XVMULWOD_W_HU:
    case LoongArch::XVMULWOD_W_HU_H:
    case LoongArch::XVMUL_B:
    case LoongArch::XVMUL_D:
    case LoongArch::XVMUL_H:
    case LoongArch::XVMUL_W:
    case LoongArch::XVNOR_V:
    case LoongArch::XVORN_V:
    case LoongArch::XVOR_V:
    case LoongArch::XVPACKEV_B:
    case LoongArch::XVPACKEV_D:
    case LoongArch::XVPACKEV_H:
    case LoongArch::XVPACKEV_W:
    case LoongArch::XVPACKOD_B:
    case LoongArch::XVPACKOD_D:
    case LoongArch::XVPACKOD_H:
    case LoongArch::XVPACKOD_W:
    case LoongArch::XVPERM_W:
    case LoongArch::XVPICKEV_B:
    case LoongArch::XVPICKEV_D:
    case LoongArch::XVPICKEV_H:
    case LoongArch::XVPICKEV_W:
    case LoongArch::XVPICKOD_B:
    case LoongArch::XVPICKOD_D:
    case LoongArch::XVPICKOD_H:
    case LoongArch::XVPICKOD_W:
    case LoongArch::XVROTR_B:
    case LoongArch::XVROTR_D:
    case LoongArch::XVROTR_H:
    case LoongArch::XVROTR_W:
    case LoongArch::XVSADD_B:
    case LoongArch::XVSADD_BU:
    case LoongArch::XVSADD_D:
    case LoongArch::XVSADD_DU:
    case LoongArch::XVSADD_H:
    case LoongArch::XVSADD_HU:
    case LoongArch::XVSADD_W:
    case LoongArch::XVSADD_WU:
    case LoongArch::XVSEQ_B:
    case LoongArch::XVSEQ_D:
    case LoongArch::XVSEQ_H:
    case LoongArch::XVSEQ_W:
    case LoongArch::XVSIGNCOV_B:
    case LoongArch::XVSIGNCOV_D:
    case LoongArch::XVSIGNCOV_H:
    case LoongArch::XVSIGNCOV_W:
    case LoongArch::XVSLE_B:
    case LoongArch::XVSLE_BU:
    case LoongArch::XVSLE_D:
    case LoongArch::XVSLE_DU:
    case LoongArch::XVSLE_H:
    case LoongArch::XVSLE_HU:
    case LoongArch::XVSLE_W:
    case LoongArch::XVSLE_WU:
    case LoongArch::XVSLL_B:
    case LoongArch::XVSLL_D:
    case LoongArch::XVSLL_H:
    case LoongArch::XVSLL_W:
    case LoongArch::XVSLT_B:
    case LoongArch::XVSLT_BU:
    case LoongArch::XVSLT_D:
    case LoongArch::XVSLT_DU:
    case LoongArch::XVSLT_H:
    case LoongArch::XVSLT_HU:
    case LoongArch::XVSLT_W:
    case LoongArch::XVSLT_WU:
    case LoongArch::XVSRAN_B_H:
    case LoongArch::XVSRAN_H_W:
    case LoongArch::XVSRAN_W_D:
    case LoongArch::XVSRARN_B_H:
    case LoongArch::XVSRARN_H_W:
    case LoongArch::XVSRARN_W_D:
    case LoongArch::XVSRAR_B:
    case LoongArch::XVSRAR_D:
    case LoongArch::XVSRAR_H:
    case LoongArch::XVSRAR_W:
    case LoongArch::XVSRA_B:
    case LoongArch::XVSRA_D:
    case LoongArch::XVSRA_H:
    case LoongArch::XVSRA_W:
    case LoongArch::XVSRLN_B_H:
    case LoongArch::XVSRLN_H_W:
    case LoongArch::XVSRLN_W_D:
    case LoongArch::XVSRLRN_B_H:
    case LoongArch::XVSRLRN_H_W:
    case LoongArch::XVSRLRN_W_D:
    case LoongArch::XVSRLR_B:
    case LoongArch::XVSRLR_D:
    case LoongArch::XVSRLR_H:
    case LoongArch::XVSRLR_W:
    case LoongArch::XVSRL_B:
    case LoongArch::XVSRL_D:
    case LoongArch::XVSRL_H:
    case LoongArch::XVSRL_W:
    case LoongArch::XVSSRAN_BU_H:
    case LoongArch::XVSSRAN_B_H:
    case LoongArch::XVSSRAN_HU_W:
    case LoongArch::XVSSRAN_H_W:
    case LoongArch::XVSSRAN_WU_D:
    case LoongArch::XVSSRAN_W_D:
    case LoongArch::XVSSRARN_BU_H:
    case LoongArch::XVSSRARN_B_H:
    case LoongArch::XVSSRARN_HU_W:
    case LoongArch::XVSSRARN_H_W:
    case LoongArch::XVSSRARN_WU_D:
    case LoongArch::XVSSRARN_W_D:
    case LoongArch::XVSSRLN_BU_H:
    case LoongArch::XVSSRLN_B_H:
    case LoongArch::XVSSRLN_HU_W:
    case LoongArch::XVSSRLN_H_W:
    case LoongArch::XVSSRLN_WU_D:
    case LoongArch::XVSSRLN_W_D:
    case LoongArch::XVSSRLRN_BU_H:
    case LoongArch::XVSSRLRN_B_H:
    case LoongArch::XVSSRLRN_HU_W:
    case LoongArch::XVSSRLRN_H_W:
    case LoongArch::XVSSRLRN_WU_D:
    case LoongArch::XVSSRLRN_W_D:
    case LoongArch::XVSSUB_B:
    case LoongArch::XVSSUB_BU:
    case LoongArch::XVSSUB_D:
    case LoongArch::XVSSUB_DU:
    case LoongArch::XVSSUB_H:
    case LoongArch::XVSSUB_HU:
    case LoongArch::XVSSUB_W:
    case LoongArch::XVSSUB_WU:
    case LoongArch::XVSUBWEV_D_W:
    case LoongArch::XVSUBWEV_D_WU:
    case LoongArch::XVSUBWEV_H_B:
    case LoongArch::XVSUBWEV_H_BU:
    case LoongArch::XVSUBWEV_Q_D:
    case LoongArch::XVSUBWEV_Q_DU:
    case LoongArch::XVSUBWEV_W_H:
    case LoongArch::XVSUBWEV_W_HU:
    case LoongArch::XVSUBWOD_D_W:
    case LoongArch::XVSUBWOD_D_WU:
    case LoongArch::XVSUBWOD_H_B:
    case LoongArch::XVSUBWOD_H_BU:
    case LoongArch::XVSUBWOD_Q_D:
    case LoongArch::XVSUBWOD_Q_DU:
    case LoongArch::XVSUBWOD_W_H:
    case LoongArch::XVSUBWOD_W_HU:
    case LoongArch::XVSUB_B:
    case LoongArch::XVSUB_D:
    case LoongArch::XVSUB_H:
    case LoongArch::XVSUB_Q:
    case LoongArch::XVSUB_W:
    case LoongArch::XVXOR_V: {
      switch (OpNum) {
      case 2:
        // op: xk
        return 10;
      case 1:
        // op: xj
        return 5;
      case 0:
        // op: xd
        return 0;
      }
      break;
    }
    case LoongArch::FSEL_xD:
    case LoongArch::FSEL_xS: {
      switch (OpNum) {
      case 3:
        // op: ca
        return 15;
      case 2:
        // op: fk
        return 10;
      case 1:
        // op: fj
        return 5;
      case 0:
        // op: fd
        return 0;
      }
      break;
    }
    case LoongArch::CSRXCHG:
    case LoongArch::GCSRXCHG: {
      switch (OpNum) {
      case 3:
        // op: csr_num
        return 10;
      case 2:
        // op: rj
        return 5;
      case 1:
        // op: rd
        return 0;
      }
      break;
    }
    case LoongArch::FMADD_D:
    case LoongArch::FMADD_S:
    case LoongArch::FMSUB_D:
    case LoongArch::FMSUB_S:
    case LoongArch::FNMADD_D:
    case LoongArch::FNMADD_S:
    case LoongArch::FNMSUB_D:
    case LoongArch::FNMSUB_S: {
      switch (OpNum) {
      case 3:
        // op: fa
        return 15;
      case 2:
        // op: fk
        return 10;
      case 1:
        // op: fj
        return 5;
      case 0:
        // op: fd
        return 0;
      }
      break;
    }
    case LoongArch::VINSGR2VR_D: {
      switch (OpNum) {
      case 3:
        // op: imm1
        return 10;
      case 2:
        // op: rj
        return 5;
      case 1:
        // op: vd
        return 0;
      }
      break;
    }
    case LoongArch::VSTELM_D: {
      switch (OpNum) {
      case 3:
        // op: imm1
        return 18;
      case 2:
        // op: imm8
        return 10;
      case 1:
        // op: rj
        return 5;
      case 0:
        // op: vd
        return 0;
      }
      break;
    }
    case LoongArch::SC_D:
    case LoongArch::SC_W: {
      switch (OpNum) {
      case 3:
        // op: imm14
        return 10;
      case 2:
        // op: rj
        return 5;
      case 1:
        // op: rd
        return 0;
      }
      break;
    }
    case LoongArch::VINSGR2VR_W: {
      switch (OpNum) {
      case 3:
        // op: imm2
        return 10;
      case 2:
        // op: rj
        return 5;
      case 1:
        // op: vd
        return 0;
      }
      break;
    }
    case LoongArch::XVINSGR2VR_D: {
      switch (OpNum) {
      case 3:
        // op: imm2
        return 10;
      case 2:
        // op: rj
        return 5;
      case 1:
        // op: xd
        return 0;
      }
      break;
    }
    case LoongArch::XVINSVE0_D: {
      switch (OpNum) {
      case 3:
        // op: imm2
        return 10;
      case 2:
        // op: xj
        return 5;
      case 1:
        // op: xd
        return 0;
      }
      break;
    }
    case LoongArch::ALSL_D:
    case LoongArch::ALSL_W:
    case LoongArch::ALSL_WU:
    case LoongArch::BYTEPICK_W: {
      switch (OpNum) {
      case 3:
        // op: imm2
        return 15;
      case 2:
        // op: rk
        return 10;
      case 1:
        // op: rj
        return 5;
      case 0:
        // op: rd
        return 0;
      }
      break;
    }
    case LoongArch::VSTELM_W: {
      switch (OpNum) {
      case 3:
        // op: imm2
        return 18;
      case 2:
        // op: imm8
        return 10;
      case 1:
        // op: rj
        return 5;
      case 0:
        // op: vd
        return 0;
      }
      break;
    }
    case LoongArch::XVSTELM_D: {
      switch (OpNum) {
      case 3:
        // op: imm2
        return 18;
      case 2:
        // op: imm8
        return 10;
      case 1:
        // op: rj
        return 5;
      case 0:
        // op: xd
        return 0;
      }
      break;
    }
    case LoongArch::VINSGR2VR_H: {
      switch (OpNum) {
      case 3:
        // op: imm3
        return 10;
      case 2:
        // op: rj
        return 5;
      case 1:
        // op: vd
        return 0;
      }
      break;
    }
    case LoongArch::XVINSGR2VR_W: {
      switch (OpNum) {
      case 3:
        // op: imm3
        return 10;
      case 2:
        // op: rj
        return 5;
      case 1:
        // op: xd
        return 0;
      }
      break;
    }
    case LoongArch::XVINSVE0_W: {
      switch (OpNum) {
      case 3:
        // op: imm3
        return 10;
      case 2:
        // op: xj
        return 5;
      case 1:
        // op: xd
        return 0;
      }
      break;
    }
    case LoongArch::BYTEPICK_D: {
      switch (OpNum) {
      case 3:
        // op: imm3
        return 15;
      case 2:
        // op: rk
        return 10;
      case 1:
        // op: rj
        return 5;
      case 0:
        // op: rd
        return 0;
      }
      break;
    }
    case LoongArch::VSTELM_H: {
      switch (OpNum) {
      case 3:
        // op: imm3
        return 18;
      case 2:
        // op: imm8
        return 10;
      case 1:
        // op: rj
        return 5;
      case 0:
        // op: vd
        return 0;
      }
      break;
    }
    case LoongArch::XVSTELM_W: {
      switch (OpNum) {
      case 3:
        // op: imm3
        return 18;
      case 2:
        // op: imm8
        return 10;
      case 1:
        // op: rj
        return 5;
      case 0:
        // op: xd
        return 0;
      }
      break;
    }
    case LoongArch::VINSGR2VR_B: {
      switch (OpNum) {
      case 3:
        // op: imm4
        return 10;
      case 2:
        // op: rj
        return 5;
      case 1:
        // op: vd
        return 0;
      }
      break;
    }
    case LoongArch::VSRANI_B_H:
    case LoongArch::VSRARNI_B_H:
    case LoongArch::VSRLNI_B_H:
    case LoongArch::VSRLRNI_B_H:
    case LoongArch::VSSRANI_BU_H:
    case LoongArch::VSSRANI_B_H:
    case LoongArch::VSSRARNI_BU_H:
    case LoongArch::VSSRARNI_B_H:
    case LoongArch::VSSRLNI_BU_H:
    case LoongArch::VSSRLNI_B_H:
    case LoongArch::VSSRLRNI_BU_H:
    case LoongArch::VSSRLRNI_B_H: {
      switch (OpNum) {
      case 3:
        // op: imm4
        return 10;
      case 2:
        // op: vj
        return 5;
      case 1:
        // op: vd
        return 0;
      }
      break;
    }
    case LoongArch::XVSRANI_B_H:
    case LoongArch::XVSRARNI_B_H:
    case LoongArch::XVSRLNI_B_H:
    case LoongArch::XVSRLRNI_B_H:
    case LoongArch::XVSSRANI_BU_H:
    case LoongArch::XVSSRANI_B_H:
    case LoongArch::XVSSRARNI_BU_H:
    case LoongArch::XVSSRARNI_B_H:
    case LoongArch::XVSSRLNI_BU_H:
    case LoongArch::XVSSRLNI_B_H:
    case LoongArch::XVSSRLRNI_BU_H:
    case LoongArch::XVSSRLRNI_B_H: {
      switch (OpNum) {
      case 3:
        // op: imm4
        return 10;
      case 2:
        // op: xj
        return 5;
      case 1:
        // op: xd
        return 0;
      }
      break;
    }
    case LoongArch::VSTELM_B: {
      switch (OpNum) {
      case 3:
        // op: imm4
        return 18;
      case 2:
        // op: imm8
        return 10;
      case 1:
        // op: rj
        return 5;
      case 0:
        // op: vd
        return 0;
      }
      break;
    }
    case LoongArch::XVSTELM_H: {
      switch (OpNum) {
      case 3:
        // op: imm4
        return 18;
      case 2:
        // op: imm8
        return 10;
      case 1:
        // op: rj
        return 5;
      case 0:
        // op: xd
        return 0;
      }
      break;
    }
    case LoongArch::VFRSTPI_B:
    case LoongArch::VFRSTPI_H:
    case LoongArch::VSRANI_H_W:
    case LoongArch::VSRARNI_H_W:
    case LoongArch::VSRLNI_H_W:
    case LoongArch::VSRLRNI_H_W:
    case LoongArch::VSSRANI_HU_W:
    case LoongArch::VSSRANI_H_W:
    case LoongArch::VSSRARNI_HU_W:
    case LoongArch::VSSRARNI_H_W:
    case LoongArch::VSSRLNI_HU_W:
    case LoongArch::VSSRLNI_H_W:
    case LoongArch::VSSRLRNI_HU_W:
    case LoongArch::VSSRLRNI_H_W: {
      switch (OpNum) {
      case 3:
        // op: imm5
        return 10;
      case 2:
        // op: vj
        return 5;
      case 1:
        // op: vd
        return 0;
      }
      break;
    }
    case LoongArch::XVFRSTPI_B:
    case LoongArch::XVFRSTPI_H:
    case LoongArch::XVSRANI_H_W:
    case LoongArch::XVSRARNI_H_W:
    case LoongArch::XVSRLNI_H_W:
    case LoongArch::XVSRLRNI_H_W:
    case LoongArch::XVSSRANI_HU_W:
    case LoongArch::XVSSRANI_H_W:
    case LoongArch::XVSSRARNI_HU_W:
    case LoongArch::XVSSRARNI_H_W:
    case LoongArch::XVSSRLNI_HU_W:
    case LoongArch::XVSSRLNI_H_W:
    case LoongArch::XVSSRLRNI_HU_W:
    case LoongArch::XVSSRLRNI_H_W: {
      switch (OpNum) {
      case 3:
        // op: imm5
        return 10;
      case 2:
        // op: xj
        return 5;
      case 1:
        // op: xd
        return 0;
      }
      break;
    }
    case LoongArch::XVSTELM_B: {
      switch (OpNum) {
      case 3:
        // op: imm5
        return 18;
      case 2:
        // op: imm8
        return 10;
      case 1:
        // op: rj
        return 5;
      case 0:
        // op: xd
        return 0;
      }
      break;
    }
    case LoongArch::VSRANI_W_D:
    case LoongArch::VSRARNI_W_D:
    case LoongArch::VSRLNI_W_D:
    case LoongArch::VSRLRNI_W_D:
    case LoongArch::VSSRANI_WU_D:
    case LoongArch::VSSRANI_W_D:
    case LoongArch::VSSRARNI_WU_D:
    case LoongArch::VSSRARNI_W_D:
    case LoongArch::VSSRLNI_WU_D:
    case LoongArch::VSSRLNI_W_D:
    case LoongArch::VSSRLRNI_WU_D:
    case LoongArch::VSSRLRNI_W_D: {
      switch (OpNum) {
      case 3:
        // op: imm6
        return 10;
      case 2:
        // op: vj
        return 5;
      case 1:
        // op: vd
        return 0;
      }
      break;
    }
    case LoongArch::XVSRANI_W_D:
    case LoongArch::XVSRARNI_W_D:
    case LoongArch::XVSRLNI_W_D:
    case LoongArch::XVSRLRNI_W_D:
    case LoongArch::XVSSRANI_WU_D:
    case LoongArch::XVSSRANI_W_D:
    case LoongArch::XVSSRARNI_WU_D:
    case LoongArch::XVSSRARNI_W_D:
    case LoongArch::XVSSRLNI_WU_D:
    case LoongArch::XVSSRLNI_W_D:
    case LoongArch::XVSSRLRNI_WU_D:
    case LoongArch::XVSSRLRNI_W_D: {
      switch (OpNum) {
      case 3:
        // op: imm6
        return 10;
      case 2:
        // op: xj
        return 5;
      case 1:
        // op: xd
        return 0;
      }
      break;
    }
    case LoongArch::VSRANI_D_Q:
    case LoongArch::VSRARNI_D_Q:
    case LoongArch::VSRLNI_D_Q:
    case LoongArch::VSRLRNI_D_Q:
    case LoongArch::VSSRANI_DU_Q:
    case LoongArch::VSSRANI_D_Q:
    case LoongArch::VSSRARNI_DU_Q:
    case LoongArch::VSSRARNI_D_Q:
    case LoongArch::VSSRLNI_DU_Q:
    case LoongArch::VSSRLNI_D_Q:
    case LoongArch::VSSRLRNI_DU_Q:
    case LoongArch::VSSRLRNI_D_Q: {
      switch (OpNum) {
      case 3:
        // op: imm7
        return 10;
      case 2:
        // op: vj
        return 5;
      case 1:
        // op: vd
        return 0;
      }
      break;
    }
    case LoongArch::XVSRANI_D_Q:
    case LoongArch::XVSRARNI_D_Q:
    case LoongArch::XVSRLNI_D_Q:
    case LoongArch::XVSRLRNI_D_Q:
    case LoongArch::XVSSRANI_DU_Q:
    case LoongArch::XVSSRANI_D_Q:
    case LoongArch::XVSSRARNI_DU_Q:
    case LoongArch::XVSSRARNI_D_Q:
    case LoongArch::XVSSRLNI_DU_Q:
    case LoongArch::XVSSRLNI_D_Q:
    case LoongArch::XVSSRLRNI_DU_Q:
    case LoongArch::XVSSRLRNI_D_Q: {
      switch (OpNum) {
      case 3:
        // op: imm7
        return 10;
      case 2:
        // op: xj
        return 5;
      case 1:
        // op: xd
        return 0;
      }
      break;
    }
    case LoongArch::VBITSELI_B:
    case LoongArch::VEXTRINS_B:
    case LoongArch::VEXTRINS_D:
    case LoongArch::VEXTRINS_H:
    case LoongArch::VEXTRINS_W:
    case LoongArch::VPERMI_W:
    case LoongArch::VSHUF4I_D: {
      switch (OpNum) {
      case 3:
        // op: imm8
        return 10;
      case 2:
        // op: vj
        return 5;
      case 1:
        // op: vd
        return 0;
      }
      break;
    }
    case LoongArch::XVBITSELI_B:
    case LoongArch::XVEXTRINS_B:
    case LoongArch::XVEXTRINS_D:
    case LoongArch::XVEXTRINS_H:
    case LoongArch::XVEXTRINS_W:
    case LoongArch::XVPERMI_Q:
    case LoongArch::XVPERMI_W:
    case LoongArch::XVSHUF4I_D: {
      switch (OpNum) {
      case 3:
        // op: imm8
        return 10;
      case 2:
        // op: xj
        return 5;
      case 1:
        // op: xd
        return 0;
      }
      break;
    }
    case LoongArch::BSTRINS_D: {
      switch (OpNum) {
      case 3:
        // op: msbd
        return 16;
      case 4:
        // op: lsbd
        return 10;
      case 2:
        // op: rj
        return 5;
      case 1:
        // op: rd
        return 0;
      }
      break;
    }
    case LoongArch::BSTRINS_W: {
      switch (OpNum) {
      case 3:
        // op: msbw
        return 16;
      case 4:
        // op: lsbw
        return 10;
      case 2:
        // op: rj
        return 5;
      case 1:
        // op: rd
        return 0;
      }
      break;
    }
    case LoongArch::VBITSEL_V:
    case LoongArch::VFMADD_D:
    case LoongArch::VFMADD_S:
    case LoongArch::VFMSUB_D:
    case LoongArch::VFMSUB_S:
    case LoongArch::VFNMADD_D:
    case LoongArch::VFNMADD_S:
    case LoongArch::VFNMSUB_D:
    case LoongArch::VFNMSUB_S:
    case LoongArch::VSHUF_B: {
      switch (OpNum) {
      case 3:
        // op: va
        return 15;
      case 2:
        // op: vk
        return 10;
      case 1:
        // op: vj
        return 5;
      case 0:
        // op: vd
        return 0;
      }
      break;
    }
    case LoongArch::VFRSTP_B:
    case LoongArch::VFRSTP_H:
    case LoongArch::VMADDWEV_D_W:
    case LoongArch::VMADDWEV_D_WU:
    case LoongArch::VMADDWEV_D_WU_W:
    case LoongArch::VMADDWEV_H_B:
    case LoongArch::VMADDWEV_H_BU:
    case LoongArch::VMADDWEV_H_BU_B:
    case LoongArch::VMADDWEV_Q_D:
    case LoongArch::VMADDWEV_Q_DU:
    case LoongArch::VMADDWEV_Q_DU_D:
    case LoongArch::VMADDWEV_W_H:
    case LoongArch::VMADDWEV_W_HU:
    case LoongArch::VMADDWEV_W_HU_H:
    case LoongArch::VMADDWOD_D_W:
    case LoongArch::VMADDWOD_D_WU:
    case LoongArch::VMADDWOD_D_WU_W:
    case LoongArch::VMADDWOD_H_B:
    case LoongArch::VMADDWOD_H_BU:
    case LoongArch::VMADDWOD_H_BU_B:
    case LoongArch::VMADDWOD_Q_D:
    case LoongArch::VMADDWOD_Q_DU:
    case LoongArch::VMADDWOD_Q_DU_D:
    case LoongArch::VMADDWOD_W_H:
    case LoongArch::VMADDWOD_W_HU:
    case LoongArch::VMADDWOD_W_HU_H:
    case LoongArch::VMADD_B:
    case LoongArch::VMADD_D:
    case LoongArch::VMADD_H:
    case LoongArch::VMADD_W:
    case LoongArch::VMSUB_B:
    case LoongArch::VMSUB_D:
    case LoongArch::VMSUB_H:
    case LoongArch::VMSUB_W:
    case LoongArch::VSHUF_D:
    case LoongArch::VSHUF_H:
    case LoongArch::VSHUF_W: {
      switch (OpNum) {
      case 3:
        // op: vk
        return 10;
      case 2:
        // op: vj
        return 5;
      case 1:
        // op: vd
        return 0;
      }
      break;
    }
    case LoongArch::XVBITSEL_V:
    case LoongArch::XVFMADD_D:
    case LoongArch::XVFMADD_S:
    case LoongArch::XVFMSUB_D:
    case LoongArch::XVFMSUB_S:
    case LoongArch::XVFNMADD_D:
    case LoongArch::XVFNMADD_S:
    case LoongArch::XVFNMSUB_D:
    case LoongArch::XVFNMSUB_S:
    case LoongArch::XVSHUF_B: {
      switch (OpNum) {
      case 3:
        // op: xa
        return 15;
      case 2:
        // op: xk
        return 10;
      case 1:
        // op: xj
        return 5;
      case 0:
        // op: xd
        return 0;
      }
      break;
    }
    case LoongArch::XVFRSTP_B:
    case LoongArch::XVFRSTP_H:
    case LoongArch::XVMADDWEV_D_W:
    case LoongArch::XVMADDWEV_D_WU:
    case LoongArch::XVMADDWEV_D_WU_W:
    case LoongArch::XVMADDWEV_H_B:
    case LoongArch::XVMADDWEV_H_BU:
    case LoongArch::XVMADDWEV_H_BU_B:
    case LoongArch::XVMADDWEV_Q_D:
    case LoongArch::XVMADDWEV_Q_DU:
    case LoongArch::XVMADDWEV_Q_DU_D:
    case LoongArch::XVMADDWEV_W_H:
    case LoongArch::XVMADDWEV_W_HU:
    case LoongArch::XVMADDWEV_W_HU_H:
    case LoongArch::XVMADDWOD_D_W:
    case LoongArch::XVMADDWOD_D_WU:
    case LoongArch::XVMADDWOD_D_WU_W:
    case LoongArch::XVMADDWOD_H_B:
    case LoongArch::XVMADDWOD_H_BU:
    case LoongArch::XVMADDWOD_H_BU_B:
    case LoongArch::XVMADDWOD_Q_D:
    case LoongArch::XVMADDWOD_Q_DU:
    case LoongArch::XVMADDWOD_Q_DU_D:
    case LoongArch::XVMADDWOD_W_H:
    case LoongArch::XVMADDWOD_W_HU:
    case LoongArch::XVMADDWOD_W_HU_H:
    case LoongArch::XVMADD_B:
    case LoongArch::XVMADD_D:
    case LoongArch::XVMADD_H:
    case LoongArch::XVMADD_W:
    case LoongArch::XVMSUB_B:
    case LoongArch::XVMSUB_D:
    case LoongArch::XVMSUB_H:
    case LoongArch::XVMSUB_W:
    case LoongArch::XVSHUF_D:
    case LoongArch::XVSHUF_H:
    case LoongArch::XVSHUF_W: {
      switch (OpNum) {
      case 3:
        // op: xk
        return 10;
      case 2:
        // op: xj
        return 5;
      case 1:
        // op: xd
        return 0;
      }
      break;
    }
  }
  std::string msg;
  raw_string_ostream Msg(msg);
  Msg << "Not supported instr[opcode]: " << MI << "[" << OpNum << "]";
  report_fatal_error(Msg.str().c_str());
}

#endif // GET_OPERAND_BIT_OFFSET