llvm/lib/Target/MSP430/MSP430GenInstrInfo.inc

/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
|*                                                                            *|
|* Target Instruction Enum Values and Descriptors                             *|
|*                                                                            *|
|* Automatically generated file, do not edit!                                 *|
|*                                                                            *|
\*===----------------------------------------------------------------------===*/

#ifdef GET_INSTRINFO_ENUM
#undef GET_INSTRINFO_ENUM
namespace llvm {

namespace MSP430 {
  enum { … };

} // end namespace MSP430
} // end namespace llvm
#endif // GET_INSTRINFO_ENUM

#ifdef GET_INSTRINFO_SCHED_ENUM
#undef GET_INSTRINFO_SCHED_ENUM
namespace llvm {

namespace MSP430 {
namespace Sched {
  enum {
    NoInstrModel	= 0,
    SCHED_LIST_END = 1
  };
} // end namespace Sched
} // end namespace MSP430
} // end namespace llvm
#endif // GET_INSTRINFO_SCHED_ENUM

#if defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
namespace llvm {

struct MSP430InstrTable {
  MCInstrDesc Insts[639];
  static_assert(alignof(MCInstrDesc) >= alignof(MCOperandInfo), "Unwanted padding between Insts and OperandInfo");
  MCOperandInfo OperandInfo[267];
  static_assert(alignof(MCOperandInfo) >= alignof(MCPhysReg), "Unwanted padding between OperandInfo and ImplicitOps");
  MCPhysReg ImplicitOps[17];
};

} // end namespace llvm
#endif // defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)

#ifdef GET_INSTRINFO_MC_DESC
#undef GET_INSTRINFO_MC_DESC
namespace llvm {

static_assert(sizeof(MCOperandInfo) % sizeof(MCPhysReg) == 0);
static constexpr unsigned MSP430ImpOpBase = sizeof MSP430InstrTable::OperandInfo / (sizeof(MCPhysReg));

extern const MSP430InstrTable MSP430Descs = {
  {
    { 638,	2,	1,	2,	0,	0,	0,	MSP430ImpOpBase + 0,	249,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #638 = ZEXT16r
    { 637,	3,	1,	2,	0,	0,	1,	MSP430ImpOpBase + 0,	208,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #637 = XOR8rr
    { 636,	4,	2,	2,	0,	0,	1,	MSP430ImpOpBase + 0,	204,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #636 = XOR8rp
    { 635,	3,	1,	2,	0,	0,	1,	MSP430ImpOpBase + 0,	201,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #635 = XOR8rn
    { 634,	4,	1,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	197,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #634 = XOR8rm
    { 633,	3,	1,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	194,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #633 = XOR8ri
    { 632,	3,	1,	2,	0,	0,	1,	MSP430ImpOpBase + 0,	191,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #632 = XOR8rc
    { 631,	3,	0,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	188,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #631 = XOR8mr
    { 630,	3,	0,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	162,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #630 = XOR8mp
    { 629,	3,	0,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	162,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #629 = XOR8mn
    { 628,	4,	0,	6,	0,	0,	1,	MSP430ImpOpBase + 0,	158,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #628 = XOR8mm
    { 627,	3,	0,	6,	0,	0,	1,	MSP430ImpOpBase + 0,	155,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #627 = XOR8mi
    { 626,	3,	0,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	152,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #626 = XOR8mc
    { 625,	3,	1,	2,	0,	0,	1,	MSP430ImpOpBase + 0,	185,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #625 = XOR16rr
    { 624,	4,	2,	2,	0,	0,	1,	MSP430ImpOpBase + 0,	181,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #624 = XOR16rp
    { 623,	3,	1,	2,	0,	0,	1,	MSP430ImpOpBase + 0,	178,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #623 = XOR16rn
    { 622,	4,	1,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	174,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #622 = XOR16rm
    { 621,	3,	1,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	171,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #621 = XOR16ri
    { 620,	3,	1,	2,	0,	0,	1,	MSP430ImpOpBase + 0,	168,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #620 = XOR16rc
    { 619,	3,	0,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	165,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #619 = XOR16mr
    { 618,	3,	0,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	162,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #618 = XOR16mp
    { 617,	3,	0,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	162,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #617 = XOR16mn
    { 616,	4,	0,	6,	0,	0,	1,	MSP430ImpOpBase + 0,	158,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #616 = XOR16mm
    { 615,	3,	0,	6,	0,	0,	1,	MSP430ImpOpBase + 0,	155,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #615 = XOR16mi
    { 614,	3,	0,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	152,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #614 = XOR16mc
    { 613,	3,	1,	0,	0,	0,	1,	MSP430ImpOpBase + 0,	264,	0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #613 = Srl8
    { 612,	3,	1,	0,	0,	0,	1,	MSP430ImpOpBase + 0,	261,	0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #612 = Srl16
    { 611,	3,	1,	0,	0,	0,	1,	MSP430ImpOpBase + 0,	264,	0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #611 = Sra8
    { 610,	3,	1,	0,	0,	0,	1,	MSP430ImpOpBase + 0,	261,	0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #610 = Sra16
    { 609,	3,	1,	0,	0,	0,	1,	MSP430ImpOpBase + 0,	264,	0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #609 = Shl8
    { 608,	3,	1,	0,	0,	0,	1,	MSP430ImpOpBase + 0,	261,	0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #608 = Shl16
    { 607,	4,	1,	0,	0,	1,	0,	MSP430ImpOpBase + 0,	257,	0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #607 = Select8
    { 606,	4,	1,	0,	0,	1,	0,	MSP430ImpOpBase + 0,	253,	0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #606 = Select16
    { 605,	2,	1,	2,	0,	0,	0,	MSP430ImpOpBase + 0,	249,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #605 = SWPB16r
    { 604,	1,	0,	2,	0,	0,	0,	MSP430ImpOpBase + 0,	239,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #604 = SWPB16p
    { 603,	1,	0,	2,	0,	0,	0,	MSP430ImpOpBase + 0,	239,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #603 = SWPB16n
    { 602,	2,	0,	4,	0,	0,	0,	MSP430ImpOpBase + 0,	236,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #602 = SWPB16m
    { 601,	3,	1,	2,	0,	1,	1,	MSP430ImpOpBase + 1,	208,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #601 = SUBC8rr
    { 600,	4,	2,	2,	0,	1,	1,	MSP430ImpOpBase + 1,	204,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #600 = SUBC8rp
    { 599,	3,	1,	2,	0,	1,	1,	MSP430ImpOpBase + 1,	201,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #599 = SUBC8rn
    { 598,	4,	1,	4,	0,	1,	1,	MSP430ImpOpBase + 1,	197,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #598 = SUBC8rm
    { 597,	3,	1,	4,	0,	1,	1,	MSP430ImpOpBase + 1,	194,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #597 = SUBC8ri
    { 596,	3,	1,	2,	0,	1,	1,	MSP430ImpOpBase + 1,	191,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #596 = SUBC8rc
    { 595,	3,	0,	4,	0,	1,	1,	MSP430ImpOpBase + 1,	188,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #595 = SUBC8mr
    { 594,	3,	0,	4,	0,	1,	1,	MSP430ImpOpBase + 1,	162,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #594 = SUBC8mp
    { 593,	3,	0,	4,	0,	1,	1,	MSP430ImpOpBase + 1,	162,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #593 = SUBC8mn
    { 592,	4,	0,	6,	0,	1,	1,	MSP430ImpOpBase + 1,	158,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #592 = SUBC8mm
    { 591,	3,	0,	6,	0,	1,	1,	MSP430ImpOpBase + 1,	155,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #591 = SUBC8mi
    { 590,	3,	0,	4,	0,	1,	1,	MSP430ImpOpBase + 1,	152,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #590 = SUBC8mc
    { 589,	3,	1,	2,	0,	1,	1,	MSP430ImpOpBase + 1,	185,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #589 = SUBC16rr
    { 588,	4,	2,	2,	0,	1,	1,	MSP430ImpOpBase + 1,	181,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #588 = SUBC16rp
    { 587,	3,	1,	2,	0,	1,	1,	MSP430ImpOpBase + 1,	178,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #587 = SUBC16rn
    { 586,	4,	1,	4,	0,	1,	1,	MSP430ImpOpBase + 1,	174,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #586 = SUBC16rm
    { 585,	3,	1,	4,	0,	1,	1,	MSP430ImpOpBase + 1,	171,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #585 = SUBC16ri
    { 584,	3,	1,	2,	0,	1,	1,	MSP430ImpOpBase + 1,	168,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #584 = SUBC16rc
    { 583,	3,	0,	4,	0,	1,	1,	MSP430ImpOpBase + 1,	165,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #583 = SUBC16mr
    { 582,	3,	0,	4,	0,	1,	1,	MSP430ImpOpBase + 1,	162,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #582 = SUBC16mp
    { 581,	3,	0,	4,	0,	1,	1,	MSP430ImpOpBase + 1,	162,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #581 = SUBC16mn
    { 580,	4,	0,	6,	0,	1,	1,	MSP430ImpOpBase + 1,	158,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #580 = SUBC16mm
    { 579,	3,	0,	6,	0,	1,	1,	MSP430ImpOpBase + 1,	155,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #579 = SUBC16mi
    { 578,	3,	0,	4,	0,	1,	1,	MSP430ImpOpBase + 1,	152,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #578 = SUBC16mc
    { 577,	3,	1,	2,	0,	0,	1,	MSP430ImpOpBase + 0,	208,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #577 = SUB8rr
    { 576,	4,	2,	2,	0,	0,	1,	MSP430ImpOpBase + 0,	204,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #576 = SUB8rp
    { 575,	3,	1,	2,	0,	0,	1,	MSP430ImpOpBase + 0,	201,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #575 = SUB8rn
    { 574,	4,	1,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	197,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #574 = SUB8rm
    { 573,	3,	1,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	194,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #573 = SUB8ri
    { 572,	3,	1,	2,	0,	0,	1,	MSP430ImpOpBase + 0,	191,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #572 = SUB8rc
    { 571,	3,	0,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	188,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #571 = SUB8mr
    { 570,	3,	0,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	162,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #570 = SUB8mp
    { 569,	3,	0,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	162,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #569 = SUB8mn
    { 568,	4,	0,	6,	0,	0,	1,	MSP430ImpOpBase + 0,	158,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #568 = SUB8mm
    { 567,	3,	0,	6,	0,	0,	1,	MSP430ImpOpBase + 0,	155,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #567 = SUB8mi
    { 566,	3,	0,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	152,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #566 = SUB8mc
    { 565,	3,	1,	2,	0,	0,	1,	MSP430ImpOpBase + 0,	185,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #565 = SUB16rr
    { 564,	4,	2,	2,	0,	0,	1,	MSP430ImpOpBase + 0,	181,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #564 = SUB16rp
    { 563,	3,	1,	2,	0,	0,	1,	MSP430ImpOpBase + 0,	178,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #563 = SUB16rn
    { 562,	4,	1,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	174,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #562 = SUB16rm
    { 561,	3,	1,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	171,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #561 = SUB16ri
    { 560,	3,	1,	2,	0,	0,	1,	MSP430ImpOpBase + 0,	168,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #560 = SUB16rc
    { 559,	3,	0,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	165,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #559 = SUB16mr
    { 558,	3,	0,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	162,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #558 = SUB16mp
    { 557,	3,	0,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	162,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #557 = SUB16mn
    { 556,	4,	0,	6,	0,	0,	1,	MSP430ImpOpBase + 0,	158,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #556 = SUB16mm
    { 555,	3,	0,	6,	0,	0,	1,	MSP430ImpOpBase + 0,	155,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #555 = SUB16mi
    { 554,	3,	0,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	152,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #554 = SUB16mc
    { 553,	2,	1,	2,	0,	0,	1,	MSP430ImpOpBase + 0,	249,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #553 = SEXT16r
    { 552,	1,	0,	2,	0,	0,	1,	MSP430ImpOpBase + 0,	239,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #552 = SEXT16p
    { 551,	1,	0,	2,	0,	0,	1,	MSP430ImpOpBase + 0,	239,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #551 = SEXT16n
    { 550,	2,	0,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	236,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #550 = SEXT16m
    { 549,	2,	1,	0,	0,	0,	1,	MSP430ImpOpBase + 0,	234,	0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #549 = Rrcl8
    { 548,	2,	1,	0,	0,	0,	1,	MSP430ImpOpBase + 0,	223,	0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #548 = Rrcl16
    { 547,	2,	1,	2,	0,	1,	1,	MSP430ImpOpBase + 1,	251,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #547 = RRC8r
    { 546,	1,	0,	2,	0,	1,	1,	MSP430ImpOpBase + 1,	239,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #546 = RRC8p
    { 545,	1,	0,	2,	0,	1,	1,	MSP430ImpOpBase + 1,	239,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #545 = RRC8n
    { 544,	2,	0,	4,	0,	1,	1,	MSP430ImpOpBase + 1,	236,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #544 = RRC8m
    { 543,	2,	1,	2,	0,	1,	1,	MSP430ImpOpBase + 1,	249,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #543 = RRC16r
    { 542,	1,	0,	2,	0,	1,	1,	MSP430ImpOpBase + 1,	239,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #542 = RRC16p
    { 541,	1,	0,	2,	0,	1,	1,	MSP430ImpOpBase + 1,	239,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #541 = RRC16n
    { 540,	2,	0,	4,	0,	1,	1,	MSP430ImpOpBase + 1,	236,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #540 = RRC16m
    { 539,	2,	1,	2,	0,	0,	1,	MSP430ImpOpBase + 0,	251,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #539 = RRA8r
    { 538,	1,	0,	2,	0,	0,	1,	MSP430ImpOpBase + 0,	239,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #538 = RRA8p
    { 537,	1,	0,	2,	0,	0,	1,	MSP430ImpOpBase + 0,	239,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #537 = RRA8n
    { 536,	2,	0,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	236,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #536 = RRA8m
    { 535,	2,	1,	2,	0,	0,	1,	MSP430ImpOpBase + 0,	249,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #535 = RRA16r
    { 534,	1,	0,	2,	0,	0,	1,	MSP430ImpOpBase + 0,	239,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #534 = RRA16p
    { 533,	1,	0,	2,	0,	0,	1,	MSP430ImpOpBase + 0,	239,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #533 = RRA16n
    { 532,	2,	0,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	236,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #532 = RRA16m
    { 531,	0,	0,	2,	0,	0,	0,	MSP430ImpOpBase + 0,	1,	0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #531 = RETI
    { 530,	0,	0,	2,	0,	0,	0,	MSP430ImpOpBase + 0,	1,	0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #530 = RET
    { 529,	1,	0,	2,	0,	1,	1,	MSP430ImpOpBase + 15,	248,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #529 = PUSH8r
    { 528,	1,	0,	2,	0,	1,	1,	MSP430ImpOpBase + 15,	238,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #528 = PUSH16r
    { 527,	1,	0,	4,	0,	1,	1,	MSP430ImpOpBase + 15,	1,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #527 = PUSH16i
    { 526,	1,	0,	2,	0,	1,	1,	MSP430ImpOpBase + 15,	0,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #526 = PUSH16c
    { 525,	1,	1,	2,	0,	1,	1,	MSP430ImpOpBase + 15,	238,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #525 = POP16r
    { 524,	2,	1,	2,	0,	0,	0,	MSP430ImpOpBase + 0,	246,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #524 = MOVZX16rr8
    { 523,	3,	1,	4,	0,	0,	0,	MSP430ImpOpBase + 0,	218,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #523 = MOVZX16rm8
    { 522,	2,	1,	2,	0,	0,	0,	MSP430ImpOpBase + 0,	234,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #522 = MOV8rr
    { 521,	3,	2,	2,	0,	0,	0,	MSP430ImpOpBase + 0,	243,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #521 = MOV8rp
    { 520,	2,	1,	2,	0,	0,	0,	MSP430ImpOpBase + 0,	232,	0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #520 = MOV8rn
    { 519,	3,	1,	4,	0,	0,	0,	MSP430ImpOpBase + 0,	229,	0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #519 = MOV8rm
    { 518,	2,	1,	4,	0,	0,	0,	MSP430ImpOpBase + 0,	227,	0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #518 = MOV8ri
    { 517,	2,	1,	2,	0,	0,	0,	MSP430ImpOpBase + 0,	225,	0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #517 = MOV8rc
    { 516,	3,	0,	4,	0,	0,	0,	MSP430ImpOpBase + 0,	188,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #516 = MOV8mr
    { 515,	3,	0,	4,	0,	0,	0,	MSP430ImpOpBase + 0,	162,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #515 = MOV8mn
    { 514,	4,	0,	6,	0,	0,	0,	MSP430ImpOpBase + 0,	158,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #514 = MOV8mm
    { 513,	3,	0,	6,	0,	0,	0,	MSP430ImpOpBase + 0,	155,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #513 = MOV8mi
    { 512,	3,	0,	4,	0,	0,	0,	MSP430ImpOpBase + 0,	152,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #512 = MOV8mc
    { 511,	2,	1,	2,	0,	0,	0,	MSP430ImpOpBase + 0,	223,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #511 = MOV16rr
    { 510,	3,	2,	2,	0,	0,	0,	MSP430ImpOpBase + 0,	240,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #510 = MOV16rp
    { 509,	2,	1,	2,	0,	0,	0,	MSP430ImpOpBase + 0,	221,	0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #509 = MOV16rn
    { 508,	3,	1,	4,	0,	0,	0,	MSP430ImpOpBase + 0,	218,	0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #508 = MOV16rm
    { 507,	2,	1,	4,	0,	0,	0,	MSP430ImpOpBase + 0,	216,	0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #507 = MOV16ri
    { 506,	2,	1,	2,	0,	0,	0,	MSP430ImpOpBase + 0,	214,	0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #506 = MOV16rc
    { 505,	3,	0,	4,	0,	0,	0,	MSP430ImpOpBase + 0,	165,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #505 = MOV16mr
    { 504,	3,	0,	4,	0,	0,	0,	MSP430ImpOpBase + 0,	162,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #504 = MOV16mn
    { 503,	4,	0,	6,	0,	0,	0,	MSP430ImpOpBase + 0,	158,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #503 = MOV16mm
    { 502,	3,	0,	6,	0,	0,	0,	MSP430ImpOpBase + 0,	155,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #502 = MOV16mi
    { 501,	3,	0,	4,	0,	0,	0,	MSP430ImpOpBase + 0,	152,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #501 = MOV16mc
    { 500,	1,	0,	2,	0,	0,	0,	MSP430ImpOpBase + 0,	0,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #500 = JMP
    { 499,	2,	0,	2,	0,	1,	0,	MSP430ImpOpBase + 0,	13,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #499 = JCC
    { 498,	3,	1,	2,	0,	1,	1,	MSP430ImpOpBase + 1,	208,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #498 = DADD8rr
    { 497,	4,	2,	2,	0,	1,	1,	MSP430ImpOpBase + 1,	204,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #497 = DADD8rp
    { 496,	3,	1,	2,	0,	1,	1,	MSP430ImpOpBase + 1,	201,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #496 = DADD8rn
    { 495,	4,	1,	4,	0,	1,	1,	MSP430ImpOpBase + 1,	197,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #495 = DADD8rm
    { 494,	3,	1,	4,	0,	1,	1,	MSP430ImpOpBase + 1,	194,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #494 = DADD8ri
    { 493,	3,	1,	2,	0,	1,	1,	MSP430ImpOpBase + 1,	191,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #493 = DADD8rc
    { 492,	3,	0,	4,	0,	1,	1,	MSP430ImpOpBase + 1,	188,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #492 = DADD8mr
    { 491,	3,	0,	4,	0,	1,	1,	MSP430ImpOpBase + 1,	162,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #491 = DADD8mp
    { 490,	3,	0,	4,	0,	1,	1,	MSP430ImpOpBase + 1,	162,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #490 = DADD8mn
    { 489,	4,	0,	6,	0,	1,	1,	MSP430ImpOpBase + 1,	158,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #489 = DADD8mm
    { 488,	3,	0,	6,	0,	1,	1,	MSP430ImpOpBase + 1,	155,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #488 = DADD8mi
    { 487,	3,	0,	4,	0,	1,	1,	MSP430ImpOpBase + 1,	152,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #487 = DADD8mc
    { 486,	3,	1,	2,	0,	1,	1,	MSP430ImpOpBase + 1,	185,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #486 = DADD16rr
    { 485,	4,	2,	2,	0,	1,	1,	MSP430ImpOpBase + 1,	181,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #485 = DADD16rp
    { 484,	3,	1,	2,	0,	1,	1,	MSP430ImpOpBase + 1,	178,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #484 = DADD16rn
    { 483,	4,	1,	4,	0,	1,	1,	MSP430ImpOpBase + 1,	174,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #483 = DADD16rm
    { 482,	3,	1,	4,	0,	1,	1,	MSP430ImpOpBase + 1,	171,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #482 = DADD16ri
    { 481,	3,	1,	2,	0,	1,	1,	MSP430ImpOpBase + 1,	168,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #481 = DADD16rc
    { 480,	3,	0,	4,	0,	1,	1,	MSP430ImpOpBase + 1,	165,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #480 = DADD16mr
    { 479,	3,	0,	4,	0,	1,	1,	MSP430ImpOpBase + 1,	162,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #479 = DADD16mp
    { 478,	3,	0,	4,	0,	1,	1,	MSP430ImpOpBase + 1,	162,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #478 = DADD16mn
    { 477,	4,	0,	6,	0,	1,	1,	MSP430ImpOpBase + 1,	158,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #477 = DADD16mm
    { 476,	3,	0,	6,	0,	1,	1,	MSP430ImpOpBase + 1,	155,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #476 = DADD16mi
    { 475,	3,	0,	4,	0,	1,	1,	MSP430ImpOpBase + 1,	152,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #475 = DADD16mc
    { 474,	2,	0,	2,	0,	0,	1,	MSP430ImpOpBase + 0,	234,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #474 = CMP8rr
    { 473,	2,	0,	2,	0,	0,	1,	MSP430ImpOpBase + 0,	232,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #473 = CMP8rp
    { 472,	2,	0,	2,	0,	0,	1,	MSP430ImpOpBase + 0,	232,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #472 = CMP8rn
    { 471,	3,	0,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	229,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #471 = CMP8rm
    { 470,	2,	0,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	227,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #470 = CMP8ri
    { 469,	2,	0,	2,	0,	0,	1,	MSP430ImpOpBase + 0,	225,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #469 = CMP8rc
    { 468,	3,	0,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	188,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #468 = CMP8mr
    { 467,	3,	0,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	162,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #467 = CMP8mp
    { 466,	3,	0,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	162,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #466 = CMP8mn
    { 465,	4,	0,	6,	0,	0,	1,	MSP430ImpOpBase + 0,	158,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #465 = CMP8mm
    { 464,	3,	0,	6,	0,	0,	1,	MSP430ImpOpBase + 0,	155,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #464 = CMP8mi
    { 463,	3,	0,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	152,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #463 = CMP8mc
    { 462,	2,	0,	2,	0,	0,	1,	MSP430ImpOpBase + 0,	223,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #462 = CMP16rr
    { 461,	2,	0,	2,	0,	0,	1,	MSP430ImpOpBase + 0,	221,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #461 = CMP16rp
    { 460,	2,	0,	2,	0,	0,	1,	MSP430ImpOpBase + 0,	221,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #460 = CMP16rn
    { 459,	3,	0,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	218,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #459 = CMP16rm
    { 458,	2,	0,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	216,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #458 = CMP16ri
    { 457,	2,	0,	2,	0,	0,	1,	MSP430ImpOpBase + 0,	214,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #457 = CMP16rc
    { 456,	3,	0,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	165,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #456 = CMP16mr
    { 455,	3,	0,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	162,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #455 = CMP16mp
    { 454,	3,	0,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	162,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #454 = CMP16mn
    { 453,	4,	0,	6,	0,	0,	1,	MSP430ImpOpBase + 0,	158,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #453 = CMP16mm
    { 452,	3,	0,	6,	0,	0,	1,	MSP430ImpOpBase + 0,	155,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #452 = CMP16mi
    { 451,	3,	0,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	152,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #451 = CMP16mc
    { 450,	1,	0,	2,	0,	1,	6,	MSP430ImpOpBase + 8,	238,	0|(1ULL<<MCID::Call)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #450 = CALLr
    { 449,	1,	0,	2,	0,	1,	6,	MSP430ImpOpBase + 8,	239,	0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #449 = CALLp
    { 448,	1,	0,	2,	0,	1,	6,	MSP430ImpOpBase + 8,	239,	0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #448 = CALLn
    { 447,	2,	0,	4,	0,	1,	6,	MSP430ImpOpBase + 8,	236,	0|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #447 = CALLm
    { 446,	1,	0,	4,	0,	1,	6,	MSP430ImpOpBase + 8,	1,	0|(1ULL<<MCID::Call)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #446 = CALLi
    { 445,	1,	0,	2,	0,	0,	0,	MSP430ImpOpBase + 0,	238,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #445 = Br
    { 444,	2,	0,	4,	0,	0,	0,	MSP430ImpOpBase + 0,	236,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #444 = Bm
    { 443,	1,	0,	4,	0,	0,	0,	MSP430ImpOpBase + 0,	1,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #443 = Bi
    { 442,	2,	0,	2,	0,	0,	1,	MSP430ImpOpBase + 0,	234,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #442 = BIT8rr
    { 441,	2,	0,	2,	0,	0,	1,	MSP430ImpOpBase + 0,	232,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #441 = BIT8rp
    { 440,	2,	0,	2,	0,	0,	1,	MSP430ImpOpBase + 0,	232,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #440 = BIT8rn
    { 439,	3,	0,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	229,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #439 = BIT8rm
    { 438,	2,	0,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	227,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #438 = BIT8ri
    { 437,	2,	0,	2,	0,	0,	1,	MSP430ImpOpBase + 0,	225,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #437 = BIT8rc
    { 436,	3,	0,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	188,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #436 = BIT8mr
    { 435,	3,	0,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	162,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #435 = BIT8mp
    { 434,	3,	0,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	162,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #434 = BIT8mn
    { 433,	4,	0,	6,	0,	0,	1,	MSP430ImpOpBase + 0,	158,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #433 = BIT8mm
    { 432,	3,	0,	6,	0,	0,	1,	MSP430ImpOpBase + 0,	155,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #432 = BIT8mi
    { 431,	3,	0,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	152,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #431 = BIT8mc
    { 430,	2,	0,	2,	0,	0,	1,	MSP430ImpOpBase + 0,	223,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #430 = BIT16rr
    { 429,	2,	0,	2,	0,	0,	1,	MSP430ImpOpBase + 0,	221,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #429 = BIT16rp
    { 428,	2,	0,	2,	0,	0,	1,	MSP430ImpOpBase + 0,	221,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #428 = BIT16rn
    { 427,	3,	0,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	218,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #427 = BIT16rm
    { 426,	2,	0,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	216,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #426 = BIT16ri
    { 425,	2,	0,	2,	0,	0,	1,	MSP430ImpOpBase + 0,	214,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #425 = BIT16rc
    { 424,	3,	0,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	165,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #424 = BIT16mr
    { 423,	3,	0,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	162,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #423 = BIT16mp
    { 422,	3,	0,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	162,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #422 = BIT16mn
    { 421,	4,	0,	6,	0,	0,	1,	MSP430ImpOpBase + 0,	158,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #421 = BIT16mm
    { 420,	3,	0,	6,	0,	0,	1,	MSP430ImpOpBase + 0,	155,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #420 = BIT16mi
    { 419,	3,	0,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	152,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #419 = BIT16mc
    { 418,	3,	1,	2,	0,	0,	1,	MSP430ImpOpBase + 0,	208,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #418 = BIS8rr
    { 417,	4,	2,	2,	0,	0,	1,	MSP430ImpOpBase + 0,	204,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #417 = BIS8rp
    { 416,	3,	1,	2,	0,	0,	1,	MSP430ImpOpBase + 0,	201,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #416 = BIS8rn
    { 415,	4,	1,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	197,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #415 = BIS8rm
    { 414,	3,	1,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	194,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #414 = BIS8ri
    { 413,	3,	1,	2,	0,	0,	1,	MSP430ImpOpBase + 0,	191,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #413 = BIS8rc
    { 412,	3,	0,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	188,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #412 = BIS8mr
    { 411,	3,	0,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	162,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #411 = BIS8mp
    { 410,	3,	0,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	162,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #410 = BIS8mn
    { 409,	4,	0,	6,	0,	0,	1,	MSP430ImpOpBase + 0,	158,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #409 = BIS8mm
    { 408,	3,	0,	6,	0,	0,	1,	MSP430ImpOpBase + 0,	155,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #408 = BIS8mi
    { 407,	3,	0,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	152,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #407 = BIS8mc
    { 406,	3,	1,	2,	0,	0,	1,	MSP430ImpOpBase + 0,	185,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #406 = BIS16rr
    { 405,	4,	2,	2,	0,	0,	1,	MSP430ImpOpBase + 0,	181,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #405 = BIS16rp
    { 404,	3,	1,	2,	0,	0,	1,	MSP430ImpOpBase + 0,	178,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #404 = BIS16rn
    { 403,	4,	1,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	174,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #403 = BIS16rm
    { 402,	3,	1,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	171,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #402 = BIS16ri
    { 401,	3,	1,	2,	0,	0,	1,	MSP430ImpOpBase + 0,	168,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #401 = BIS16rc
    { 400,	3,	0,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	165,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #400 = BIS16mr
    { 399,	3,	0,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	162,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #399 = BIS16mp
    { 398,	3,	0,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	162,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #398 = BIS16mn
    { 397,	4,	0,	6,	0,	0,	1,	MSP430ImpOpBase + 0,	158,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #397 = BIS16mm
    { 396,	3,	0,	6,	0,	0,	1,	MSP430ImpOpBase + 0,	155,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #396 = BIS16mi
    { 395,	3,	0,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	152,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #395 = BIS16mc
    { 394,	3,	1,	2,	0,	0,	1,	MSP430ImpOpBase + 0,	208,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #394 = BIC8rr
    { 393,	4,	2,	2,	0,	0,	1,	MSP430ImpOpBase + 0,	204,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #393 = BIC8rp
    { 392,	3,	1,	2,	0,	0,	1,	MSP430ImpOpBase + 0,	201,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #392 = BIC8rn
    { 391,	4,	1,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	197,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #391 = BIC8rm
    { 390,	3,	1,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	194,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #390 = BIC8ri
    { 389,	3,	1,	2,	0,	0,	1,	MSP430ImpOpBase + 0,	191,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #389 = BIC8rc
    { 388,	3,	0,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	188,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #388 = BIC8mr
    { 387,	3,	0,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	162,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #387 = BIC8mp
    { 386,	3,	0,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	162,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #386 = BIC8mn
    { 385,	4,	0,	6,	0,	0,	1,	MSP430ImpOpBase + 0,	158,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #385 = BIC8mm
    { 384,	3,	0,	6,	0,	0,	1,	MSP430ImpOpBase + 0,	155,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #384 = BIC8mi
    { 383,	3,	0,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	152,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #383 = BIC8mc
    { 382,	3,	1,	2,	0,	0,	1,	MSP430ImpOpBase + 0,	185,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #382 = BIC16rr
    { 381,	4,	2,	2,	0,	0,	1,	MSP430ImpOpBase + 0,	181,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #381 = BIC16rp
    { 380,	3,	1,	2,	0,	0,	1,	MSP430ImpOpBase + 0,	178,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #380 = BIC16rn
    { 379,	4,	1,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	174,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #379 = BIC16rm
    { 378,	3,	1,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	171,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #378 = BIC16ri
    { 377,	3,	1,	2,	0,	0,	1,	MSP430ImpOpBase + 0,	168,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #377 = BIC16rc
    { 376,	3,	0,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	165,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #376 = BIC16mr
    { 375,	3,	0,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	162,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #375 = BIC16mp
    { 374,	3,	0,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	162,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #374 = BIC16mn
    { 373,	4,	0,	6,	0,	0,	1,	MSP430ImpOpBase + 0,	158,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #373 = BIC16mm
    { 372,	3,	0,	6,	0,	0,	1,	MSP430ImpOpBase + 0,	155,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #372 = BIC16mi
    { 371,	3,	0,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	152,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #371 = BIC16mc
    { 370,	3,	1,	2,	0,	0,	1,	MSP430ImpOpBase + 0,	208,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #370 = AND8rr
    { 369,	4,	2,	2,	0,	0,	1,	MSP430ImpOpBase + 0,	204,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #369 = AND8rp
    { 368,	3,	1,	2,	0,	0,	1,	MSP430ImpOpBase + 0,	201,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #368 = AND8rn
    { 367,	4,	1,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	197,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #367 = AND8rm
    { 366,	3,	1,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	194,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #366 = AND8ri
    { 365,	3,	1,	2,	0,	0,	1,	MSP430ImpOpBase + 0,	191,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #365 = AND8rc
    { 364,	3,	0,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	188,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #364 = AND8mr
    { 363,	3,	0,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	162,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #363 = AND8mp
    { 362,	3,	0,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	162,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #362 = AND8mn
    { 361,	4,	0,	6,	0,	0,	1,	MSP430ImpOpBase + 0,	158,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #361 = AND8mm
    { 360,	3,	0,	6,	0,	0,	1,	MSP430ImpOpBase + 0,	155,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #360 = AND8mi
    { 359,	3,	0,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	152,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #359 = AND8mc
    { 358,	3,	1,	2,	0,	0,	1,	MSP430ImpOpBase + 0,	185,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #358 = AND16rr
    { 357,	4,	2,	2,	0,	0,	1,	MSP430ImpOpBase + 0,	181,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #357 = AND16rp
    { 356,	3,	1,	2,	0,	0,	1,	MSP430ImpOpBase + 0,	178,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #356 = AND16rn
    { 355,	4,	1,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	174,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #355 = AND16rm
    { 354,	3,	1,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	171,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #354 = AND16ri
    { 353,	3,	1,	2,	0,	0,	1,	MSP430ImpOpBase + 0,	168,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #353 = AND16rc
    { 352,	3,	0,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	165,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #352 = AND16mr
    { 351,	3,	0,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	162,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #351 = AND16mp
    { 350,	3,	0,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	162,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #350 = AND16mn
    { 349,	4,	0,	6,	0,	0,	1,	MSP430ImpOpBase + 0,	158,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #349 = AND16mm
    { 348,	3,	0,	6,	0,	0,	1,	MSP430ImpOpBase + 0,	155,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #348 = AND16mi
    { 347,	3,	0,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	152,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #347 = AND16mc
    { 346,	2,	0,	0,	0,	1,	2,	MSP430ImpOpBase + 5,	21,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #346 = ADJCALLSTACKUP
    { 345,	2,	0,	0,	0,	1,	2,	MSP430ImpOpBase + 5,	21,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #345 = ADJCALLSTACKDOWN
    { 344,	3,	1,	0,	0,	1,	1,	MSP430ImpOpBase + 3,	211,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #344 = ADDframe
    { 343,	3,	1,	2,	0,	1,	1,	MSP430ImpOpBase + 1,	208,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #343 = ADDC8rr
    { 342,	4,	2,	2,	0,	1,	1,	MSP430ImpOpBase + 1,	204,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #342 = ADDC8rp
    { 341,	3,	1,	2,	0,	1,	1,	MSP430ImpOpBase + 1,	201,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #341 = ADDC8rn
    { 340,	4,	1,	4,	0,	1,	1,	MSP430ImpOpBase + 1,	197,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #340 = ADDC8rm
    { 339,	3,	1,	4,	0,	1,	1,	MSP430ImpOpBase + 1,	194,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #339 = ADDC8ri
    { 338,	3,	1,	2,	0,	1,	1,	MSP430ImpOpBase + 1,	191,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #338 = ADDC8rc
    { 337,	3,	0,	4,	0,	1,	1,	MSP430ImpOpBase + 1,	188,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #337 = ADDC8mr
    { 336,	3,	0,	4,	0,	1,	1,	MSP430ImpOpBase + 1,	162,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #336 = ADDC8mp
    { 335,	3,	0,	4,	0,	1,	1,	MSP430ImpOpBase + 1,	162,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #335 = ADDC8mn
    { 334,	4,	0,	6,	0,	1,	1,	MSP430ImpOpBase + 1,	158,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #334 = ADDC8mm
    { 333,	3,	0,	6,	0,	1,	1,	MSP430ImpOpBase + 1,	155,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #333 = ADDC8mi
    { 332,	3,	0,	4,	0,	1,	1,	MSP430ImpOpBase + 1,	152,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #332 = ADDC8mc
    { 331,	3,	1,	2,	0,	1,	1,	MSP430ImpOpBase + 1,	185,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #331 = ADDC16rr
    { 330,	4,	2,	2,	0,	1,	1,	MSP430ImpOpBase + 1,	181,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #330 = ADDC16rp
    { 329,	3,	1,	2,	0,	1,	1,	MSP430ImpOpBase + 1,	178,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #329 = ADDC16rn
    { 328,	4,	1,	4,	0,	1,	1,	MSP430ImpOpBase + 1,	174,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #328 = ADDC16rm
    { 327,	3,	1,	4,	0,	1,	1,	MSP430ImpOpBase + 1,	171,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #327 = ADDC16ri
    { 326,	3,	1,	2,	0,	1,	1,	MSP430ImpOpBase + 1,	168,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #326 = ADDC16rc
    { 325,	3,	0,	4,	0,	1,	1,	MSP430ImpOpBase + 1,	165,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #325 = ADDC16mr
    { 324,	3,	0,	4,	0,	1,	1,	MSP430ImpOpBase + 1,	162,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #324 = ADDC16mp
    { 323,	3,	0,	4,	0,	1,	1,	MSP430ImpOpBase + 1,	162,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #323 = ADDC16mn
    { 322,	4,	0,	6,	0,	1,	1,	MSP430ImpOpBase + 1,	158,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #322 = ADDC16mm
    { 321,	3,	0,	6,	0,	1,	1,	MSP430ImpOpBase + 1,	155,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #321 = ADDC16mi
    { 320,	3,	0,	4,	0,	1,	1,	MSP430ImpOpBase + 1,	152,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #320 = ADDC16mc
    { 319,	3,	1,	2,	0,	0,	1,	MSP430ImpOpBase + 0,	208,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #319 = ADD8rr
    { 318,	4,	2,	2,	0,	0,	1,	MSP430ImpOpBase + 0,	204,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #318 = ADD8rp
    { 317,	3,	1,	2,	0,	0,	1,	MSP430ImpOpBase + 0,	201,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #317 = ADD8rn
    { 316,	4,	1,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	197,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #316 = ADD8rm
    { 315,	3,	1,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	194,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #315 = ADD8ri
    { 314,	3,	1,	2,	0,	0,	1,	MSP430ImpOpBase + 0,	191,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #314 = ADD8rc
    { 313,	3,	0,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	188,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #313 = ADD8mr
    { 312,	3,	0,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	162,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #312 = ADD8mp
    { 311,	3,	0,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	162,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #311 = ADD8mn
    { 310,	4,	0,	6,	0,	0,	1,	MSP430ImpOpBase + 0,	158,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #310 = ADD8mm
    { 309,	3,	0,	6,	0,	0,	1,	MSP430ImpOpBase + 0,	155,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #309 = ADD8mi
    { 308,	3,	0,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	152,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #308 = ADD8mc
    { 307,	3,	1,	2,	0,	0,	1,	MSP430ImpOpBase + 0,	185,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #307 = ADD16rr
    { 306,	4,	2,	2,	0,	0,	1,	MSP430ImpOpBase + 0,	181,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #306 = ADD16rp
    { 305,	3,	1,	2,	0,	0,	1,	MSP430ImpOpBase + 0,	178,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #305 = ADD16rn
    { 304,	4,	1,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	174,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #304 = ADD16rm
    { 303,	3,	1,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	171,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #303 = ADD16ri
    { 302,	3,	1,	2,	0,	0,	1,	MSP430ImpOpBase + 0,	168,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #302 = ADD16rc
    { 301,	3,	0,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	165,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #301 = ADD16mr
    { 300,	3,	0,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	162,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #300 = ADD16mp
    { 299,	3,	0,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	162,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #299 = ADD16mn
    { 298,	4,	0,	6,	0,	0,	1,	MSP430ImpOpBase + 0,	158,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #298 = ADD16mm
    { 297,	3,	0,	6,	0,	0,	1,	MSP430ImpOpBase + 0,	155,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #297 = ADD16mi
    { 296,	3,	0,	4,	0,	0,	1,	MSP430ImpOpBase + 0,	152,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #296 = ADD16mc
    { 295,	4,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	148,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #295 = G_UBFX
    { 294,	4,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	148,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #294 = G_SBFX
    { 293,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #293 = G_VECREDUCE_UMIN
    { 292,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #292 = G_VECREDUCE_UMAX
    { 291,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #291 = G_VECREDUCE_SMIN
    { 290,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #290 = G_VECREDUCE_SMAX
    { 289,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #289 = G_VECREDUCE_XOR
    { 288,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #288 = G_VECREDUCE_OR
    { 287,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #287 = G_VECREDUCE_AND
    { 286,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #286 = G_VECREDUCE_MUL
    { 285,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #285 = G_VECREDUCE_ADD
    { 284,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #284 = G_VECREDUCE_FMINIMUM
    { 283,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #283 = G_VECREDUCE_FMAXIMUM
    { 282,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #282 = G_VECREDUCE_FMIN
    { 281,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #281 = G_VECREDUCE_FMAX
    { 280,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #280 = G_VECREDUCE_FMUL
    { 279,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #279 = G_VECREDUCE_FADD
    { 278,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	131,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #278 = G_VECREDUCE_SEQ_FMUL
    { 277,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	131,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #277 = G_VECREDUCE_SEQ_FADD
    { 276,	1,	0,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	1,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #276 = G_UBSANTRAP
    { 275,	0,	0,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	1,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #275 = G_DEBUGTRAP
    { 274,	0,	0,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	1,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #274 = G_TRAP
    { 273,	3,	0,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	58,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #273 = G_BZERO
    { 272,	4,	0,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	144,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #272 = G_MEMSET
    { 271,	4,	0,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	144,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #271 = G_MEMMOVE
    { 270,	3,	0,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	131,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #270 = G_MEMCPY_INLINE
    { 269,	4,	0,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	144,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #269 = G_MEMCPY
    { 268,	2,	0,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	142,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL },  // Inst #268 = G_WRITE_REGISTER
    { 267,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	51,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL },  // Inst #267 = G_READ_REGISTER
    { 266,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	101,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #266 = G_STRICT_FLDEXP
    { 265,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #265 = G_STRICT_FSQRT
    { 264,	4,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	46,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #264 = G_STRICT_FMA
    { 263,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #263 = G_STRICT_FREM
    { 262,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #262 = G_STRICT_FDIV
    { 261,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #261 = G_STRICT_FMUL
    { 260,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #260 = G_STRICT_FSUB
    { 259,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #259 = G_STRICT_FADD
    { 258,	1,	0,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	50,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #258 = G_STACKRESTORE
    { 257,	1,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	50,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #257 = G_STACKSAVE
    { 256,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	69,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #256 = G_DYN_STACKALLOC
    { 255,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	51,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #255 = G_JUMP_TABLE
    { 254,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	51,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #254 = G_BLOCK_ADDR
    { 253,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #253 = G_ADDRSPACE_CAST
    { 252,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #252 = G_FNEARBYINT
    { 251,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #251 = G_FRINT
    { 250,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #250 = G_FFLOOR
    { 249,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #249 = G_FSQRT
    { 248,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #248 = G_FTANH
    { 247,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #247 = G_FSINH
    { 246,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #246 = G_FCOSH
    { 245,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #245 = G_FATAN
    { 244,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #244 = G_FASIN
    { 243,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #243 = G_FACOS
    { 242,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #242 = G_FTAN
    { 241,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #241 = G_FSIN
    { 240,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #240 = G_FCOS
    { 239,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #239 = G_FCEIL
    { 238,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #238 = G_BITREVERSE
    { 237,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #237 = G_BSWAP
    { 236,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #236 = G_CTPOP
    { 235,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #235 = G_CTLZ_ZERO_UNDEF
    { 234,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #234 = G_CTLZ
    { 233,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #233 = G_CTTZ_ZERO_UNDEF
    { 232,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #232 = G_CTTZ
    { 231,	4,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	138,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #231 = G_VECTOR_COMPRESS
    { 230,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #230 = G_SPLAT_VECTOR
    { 229,	4,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	134,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #229 = G_SHUFFLE_VECTOR
    { 228,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	131,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #228 = G_EXTRACT_VECTOR_ELT
    { 227,	4,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	127,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #227 = G_INSERT_VECTOR_ELT
    { 226,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	40,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #226 = G_EXTRACT_SUBVECTOR
    { 225,	4,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	63,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #225 = G_INSERT_SUBVECTOR
    { 224,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	51,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #224 = G_VSCALE
    { 223,	3,	0,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	124,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #223 = G_BRJT
    { 222,	1,	0,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #222 = G_BR
    { 221,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #221 = G_LLROUND
    { 220,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #220 = G_LROUND
    { 219,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #219 = G_ABS
    { 218,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #218 = G_UMAX
    { 217,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #217 = G_UMIN
    { 216,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #216 = G_SMAX
    { 215,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #215 = G_SMIN
    { 214,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	101,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #214 = G_PTRMASK
    { 213,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	101,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #213 = G_PTR_ADD
    { 212,	0,	0,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	1,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #212 = G_RESET_FPMODE
    { 211,	1,	0,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	50,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #211 = G_SET_FPMODE
    { 210,	1,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	50,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #210 = G_GET_FPMODE
    { 209,	0,	0,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	1,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #209 = G_RESET_FPENV
    { 208,	1,	0,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	50,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #208 = G_SET_FPENV
    { 207,	1,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	50,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #207 = G_GET_FPENV
    { 206,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #206 = G_FMAXIMUM
    { 205,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #205 = G_FMINIMUM
    { 204,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #204 = G_FMAXNUM_IEEE
    { 203,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #203 = G_FMINNUM_IEEE
    { 202,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #202 = G_FMAXNUM
    { 201,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #201 = G_FMINNUM
    { 200,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #200 = G_FCANONICALIZE
    { 199,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	98,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #199 = G_IS_FPCLASS
    { 198,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	101,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #198 = G_FCOPYSIGN
    { 197,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #197 = G_FABS
    { 196,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #196 = G_UITOFP
    { 195,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #195 = G_SITOFP
    { 194,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #194 = G_FPTOUI
    { 193,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #193 = G_FPTOSI
    { 192,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #192 = G_FPTRUNC
    { 191,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #191 = G_FPEXT
    { 190,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #190 = G_FNEG
    { 189,	3,	2,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #189 = G_FFREXP
    { 188,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	101,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #188 = G_FLDEXP
    { 187,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #187 = G_FLOG10
    { 186,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #186 = G_FLOG2
    { 185,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #185 = G_FLOG
    { 184,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #184 = G_FEXP10
    { 183,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #183 = G_FEXP2
    { 182,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #182 = G_FEXP
    { 181,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	101,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #181 = G_FPOWI
    { 180,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #180 = G_FPOW
    { 179,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #179 = G_FREM
    { 178,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #178 = G_FDIV
    { 177,	4,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	46,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #177 = G_FMAD
    { 176,	4,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	46,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #176 = G_FMA
    { 175,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #175 = G_FMUL
    { 174,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #174 = G_FSUB
    { 173,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #173 = G_FADD
    { 172,	4,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	120,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #172 = G_UDIVFIXSAT
    { 171,	4,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	120,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #171 = G_SDIVFIXSAT
    { 170,	4,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	120,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #170 = G_UDIVFIX
    { 169,	4,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	120,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #169 = G_SDIVFIX
    { 168,	4,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	120,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #168 = G_UMULFIXSAT
    { 167,	4,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	120,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #167 = G_SMULFIXSAT
    { 166,	4,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	120,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #166 = G_UMULFIX
    { 165,	4,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	120,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #165 = G_SMULFIX
    { 164,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	101,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #164 = G_SSHLSAT
    { 163,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	101,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #163 = G_USHLSAT
    { 162,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #162 = G_SSUBSAT
    { 161,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #161 = G_USUBSAT
    { 160,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #160 = G_SADDSAT
    { 159,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #159 = G_UADDSAT
    { 158,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #158 = G_SMULH
    { 157,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #157 = G_UMULH
    { 156,	4,	2,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	87,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #156 = G_SMULO
    { 155,	4,	2,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	87,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #155 = G_UMULO
    { 154,	5,	2,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	115,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #154 = G_SSUBE
    { 153,	4,	2,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	87,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #153 = G_SSUBO
    { 152,	5,	2,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	115,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #152 = G_SADDE
    { 151,	4,	2,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	87,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #151 = G_SADDO
    { 150,	5,	2,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	115,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #150 = G_USUBE
    { 149,	4,	2,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	87,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #149 = G_USUBO
    { 148,	5,	2,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	115,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #148 = G_UADDE
    { 147,	4,	2,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	87,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #147 = G_UADDO
    { 146,	4,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	87,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #146 = G_SELECT
    { 145,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	112,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #145 = G_UCMP
    { 144,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	112,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #144 = G_SCMP
    { 143,	4,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	108,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #143 = G_FCMP
    { 142,	4,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	108,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #142 = G_ICMP
    { 141,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	101,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #141 = G_ROTL
    { 140,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	101,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #140 = G_ROTR
    { 139,	4,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	104,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #139 = G_FSHR
    { 138,	4,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	104,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #138 = G_FSHL
    { 137,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	101,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #137 = G_ASHR
    { 136,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	101,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #136 = G_LSHR
    { 135,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	101,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #135 = G_SHL
    { 134,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #134 = G_ZEXT
    { 133,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	40,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #133 = G_SEXT_INREG
    { 132,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #132 = G_SEXT
    { 131,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	98,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #131 = G_VAARG
    { 130,	1,	0,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	50,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #130 = G_VASTART
    { 129,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	51,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #129 = G_FCONSTANT
    { 128,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	51,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #128 = G_CONSTANT
    { 127,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #127 = G_TRUNC
    { 126,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #126 = G_ANYEXT
    { 125,	1,	0,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL },  // Inst #125 = G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
    { 124,	1,	0,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL },  // Inst #124 = G_INTRINSIC_CONVERGENT
    { 123,	1,	0,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #123 = G_INTRINSIC_W_SIDE_EFFECTS
    { 122,	1,	0,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #122 = G_INTRINSIC
    { 121,	0,	0,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	1,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #121 = G_INVOKE_REGION_START
    { 120,	1,	0,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	50,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #120 = G_BRINDIRECT
    { 119,	2,	0,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	51,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #119 = G_BRCOND
    { 118,	4,	0,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	94,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #118 = G_PREFETCH
    { 117,	2,	0,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	21,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #117 = G_FENCE
    { 116,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #116 = G_ATOMICRMW_UDEC_WRAP
    { 115,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #115 = G_ATOMICRMW_UINC_WRAP
    { 114,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #114 = G_ATOMICRMW_FMIN
    { 113,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #113 = G_ATOMICRMW_FMAX
    { 112,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #112 = G_ATOMICRMW_FSUB
    { 111,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #111 = G_ATOMICRMW_FADD
    { 110,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #110 = G_ATOMICRMW_UMIN
    { 109,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #109 = G_ATOMICRMW_UMAX
    { 108,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #108 = G_ATOMICRMW_MIN
    { 107,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #107 = G_ATOMICRMW_MAX
    { 106,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #106 = G_ATOMICRMW_XOR
    { 105,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #105 = G_ATOMICRMW_OR
    { 104,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #104 = G_ATOMICRMW_NAND
    { 103,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #103 = G_ATOMICRMW_AND
    { 102,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #102 = G_ATOMICRMW_SUB
    { 101,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #101 = G_ATOMICRMW_ADD
    { 100,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #100 = G_ATOMICRMW_XCHG
    { 99,	4,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	87,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #99 = G_ATOMIC_CMPXCHG
    { 98,	5,	2,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	82,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #98 = G_ATOMIC_CMPXCHG_WITH_SUCCESS
    { 97,	5,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	77,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #97 = G_INDEXED_STORE
    { 96,	2,	0,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #96 = G_STORE
    { 95,	5,	2,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	72,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #95 = G_INDEXED_ZEXTLOAD
    { 94,	5,	2,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	72,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #94 = G_INDEXED_SEXTLOAD
    { 93,	5,	2,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	72,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #93 = G_INDEXED_LOAD
    { 92,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #92 = G_ZEXTLOAD
    { 91,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #91 = G_SEXTLOAD
    { 90,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #90 = G_LOAD
    { 89,	1,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	50,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #89 = G_READSTEADYCOUNTER
    { 88,	1,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	50,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #88 = G_READCYCLECOUNTER
    { 87,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #87 = G_INTRINSIC_ROUNDEVEN
    { 86,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #86 = G_INTRINSIC_LLRINT
    { 85,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #85 = G_INTRINSIC_LRINT
    { 84,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #84 = G_INTRINSIC_ROUND
    { 83,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #83 = G_INTRINSIC_TRUNC
    { 82,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	69,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #82 = G_INTRINSIC_FPTRUNC_ROUND
    { 81,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #81 = G_CONSTANT_FOLD_BARRIER
    { 80,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #80 = G_FREEZE
    { 79,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #79 = G_BITCAST
    { 78,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #78 = G_INTTOPTR
    { 77,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #77 = G_PTRTOINT
    { 76,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #76 = G_CONCAT_VECTORS
    { 75,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #75 = G_BUILD_VECTOR_TRUNC
    { 74,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #74 = G_BUILD_VECTOR
    { 73,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #73 = G_MERGE_VALUES
    { 72,	4,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	63,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #72 = G_INSERT
    { 71,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #71 = G_UNMERGE_VALUES
    { 70,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	58,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #70 = G_EXTRACT
    { 69,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	51,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #69 = G_CONSTANT_POOL
    { 68,	5,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	53,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #68 = G_PTRAUTH_GLOBAL_VALUE
    { 67,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	51,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #67 = G_GLOBAL_VALUE
    { 66,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	51,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #66 = G_FRAME_INDEX
    { 65,	1,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	50,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #65 = G_PHI
    { 64,	1,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	50,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #64 = G_IMPLICIT_DEF
    { 63,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #63 = G_XOR
    { 62,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #62 = G_OR
    { 61,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #61 = G_AND
    { 60,	4,	2,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	46,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #60 = G_UDIVREM
    { 59,	4,	2,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	46,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #59 = G_SDIVREM
    { 58,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #58 = G_UREM
    { 57,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #57 = G_SREM
    { 56,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #56 = G_UDIV
    { 55,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #55 = G_SDIV
    { 54,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #54 = G_MUL
    { 53,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #53 = G_SUB
    { 52,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #52 = G_ADD
    { 51,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	40,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #51 = G_ASSERT_ALIGN
    { 50,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	40,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #50 = G_ASSERT_ZEXT
    { 49,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	40,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #49 = G_ASSERT_SEXT
    { 48,	1,	0,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL },  // Inst #48 = CONVERGENCECTRL_GLUE
    { 47,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	13,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL },  // Inst #47 = CONVERGENCECTRL_LOOP
    { 46,	1,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL },  // Inst #46 = CONVERGENCECTRL_ANCHOR
    { 45,	1,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL },  // Inst #45 = CONVERGENCECTRL_ENTRY
    { 44,	1,	0,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #44 = JUMP_TABLE_DEBUG_INFO
    { 43,	0,	0,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #43 = MEMBARRIER
    { 42,	0,	0,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #42 = FAKE_USE
    { 41,	0,	0,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #41 = ICALL_BRANCH_FUNNEL
    { 40,	3,	0,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	37,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #40 = PATCHABLE_TYPED_EVENT_CALL
    { 39,	2,	0,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	35,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #39 = PATCHABLE_EVENT_CALL
    { 38,	0,	0,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #38 = PATCHABLE_TAIL_CALL
    { 37,	0,	0,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #37 = PATCHABLE_FUNCTION_EXIT
    { 36,	0,	0,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #36 = PATCHABLE_RET
    { 35,	0,	0,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #35 = PATCHABLE_FUNCTION_ENTER
    { 34,	0,	0,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #34 = PATCHABLE_OP
    { 33,	1,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #33 = FAULTING_OP
    { 32,	2,	0,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	33,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #32 = LOCAL_ESCAPE
    { 31,	0,	0,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #31 = STATEPOINT
    { 30,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	30,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #30 = PREALLOCATED_ARG
    { 29,	1,	0,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #29 = PREALLOCATED_SETUP
    { 28,	1,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	29,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #28 = LOAD_STACK_GUARD
    { 27,	6,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	23,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #27 = PATCHPOINT
    { 26,	0,	0,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #26 = FENTRY_CALL
    { 25,	2,	0,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	21,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #25 = STACKMAP
    { 24,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	19,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #24 = ARITH_FENCE
    { 23,	4,	0,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	15,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #23 = PSEUDO_PROBE
    { 22,	1,	0,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #22 = LIFETIME_END
    { 21,	1,	0,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #21 = LIFETIME_START
    { 20,	0,	0,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #20 = BUNDLE
    { 19,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	13,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #19 = COPY
    { 18,	2,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	13,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #18 = REG_SEQUENCE
    { 17,	1,	0,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #17 = DBG_LABEL
    { 16,	0,	0,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #16 = DBG_PHI
    { 15,	0,	0,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #15 = DBG_INSTR_REF
    { 14,	0,	0,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #14 = DBG_VALUE_LIST
    { 13,	0,	0,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #13 = DBG_VALUE
    { 12,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #12 = COPY_TO_REGCLASS
    { 11,	4,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	9,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #11 = SUBREG_TO_REG
    { 10,	1,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #10 = IMPLICIT_DEF
    { 9,	4,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	5,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #9 = INSERT_SUBREG
    { 8,	3,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #8 = EXTRACT_SUBREG
    { 7,	0,	0,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #7 = KILL
    { 6,	1,	0,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #6 = ANNOTATION_LABEL
    { 5,	1,	0,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #5 = GC_LABEL
    { 4,	1,	0,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #4 = EH_LABEL
    { 3,	1,	0,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #3 = CFI_INSTRUCTION
    { 2,	0,	0,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #2 = INLINEASM_BR
    { 1,	0,	0,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1 = INLINEASM
    { 0,	1,	1,	0,	0,	0,	0,	MSP430ImpOpBase + 0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #0 = PHI
  }, {
    /* 0 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 1 */
    /* 1 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 2 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 5 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 9 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 13 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 15 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 19 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) },
    /* 21 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 23 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 29 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 },
    /* 30 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 33 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 35 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 37 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 40 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
    /* 43 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
    /* 46 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
    /* 50 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
    /* 51 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 53 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 58 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
    /* 61 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
    /* 63 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
    /* 67 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
    /* 69 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 72 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 77 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 82 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
    /* 87 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
    /* 91 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
    /* 94 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 98 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 101 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
    /* 104 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
    /* 108 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
    /* 112 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
    /* 115 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
    /* 120 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
    /* 124 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
    /* 127 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
    /* 131 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
    /* 134 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 138 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
    /* 142 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
    /* 144 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
    /* 148 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
    /* 152 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 155 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 158 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 162 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 165 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 168 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 171 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 174 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 178 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 181 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(1) },
    /* 185 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 188 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 191 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 194 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 197 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 201 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 204 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(1) },
    /* 208 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 211 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 214 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 216 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 218 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 221 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 223 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 225 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 227 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 229 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 232 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 234 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 236 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 238 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 239 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 240 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(1) },
    /* 243 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(1) },
    /* 246 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 248 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 249 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
    /* 251 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
    /* 253 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 257 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 261 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 264 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
  }, {
    /* 0 */
    /* 0 */ MSP430::SR,
    /* 1 */ MSP430::SR, MSP430::SR,
    /* 3 */ MSP430::SP, MSP430::SR,
    /* 5 */ MSP430::SP, MSP430::SP, MSP430::SR,
    /* 8 */ MSP430::SP, MSP430::R11, MSP430::R12, MSP430::R13, MSP430::R14, MSP430::R15, MSP430::SR,
    /* 15 */ MSP430::SP, MSP430::SP,
  }
};


#ifdef __GNUC__
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Woverlength-strings"
#endif
extern const char MSP430InstrNameData[] = {
  /* 0 */ "G_FLOG10\0"
  /* 9 */ "G_FEXP10\0"
  /* 18 */ "G_FLOG2\0"
  /* 26 */ "G_FEXP2\0"
  /* 34 */ "Sra16\0"
  /* 40 */ "Rrcl16\0"
  /* 47 */ "Shl16\0"
  /* 53 */ "Srl16\0"
  /* 59 */ "Select16\0"
  /* 68 */ "Sra8\0"
  /* 73 */ "Rrcl8\0"
  /* 79 */ "Shl8\0"
  /* 84 */ "Srl8\0"
  /* 89 */ "MOVZX16rm8\0"
  /* 100 */ "MOVZX16rr8\0"
  /* 111 */ "Select8\0"
  /* 119 */ "G_FMA\0"
  /* 125 */ "G_STRICT_FMA\0"
  /* 138 */ "G_FSUB\0"
  /* 145 */ "G_STRICT_FSUB\0"
  /* 159 */ "G_ATOMICRMW_FSUB\0"
  /* 176 */ "G_SUB\0"
  /* 182 */ "G_ATOMICRMW_SUB\0"
  /* 198 */ "JCC\0"
  /* 202 */ "G_INTRINSIC\0"
  /* 214 */ "G_FPTRUNC\0"
  /* 224 */ "G_INTRINSIC_TRUNC\0"
  /* 242 */ "G_TRUNC\0"
  /* 250 */ "G_BUILD_VECTOR_TRUNC\0"
  /* 271 */ "G_DYN_STACKALLOC\0"
  /* 288 */ "G_FMAD\0"
  /* 295 */ "G_INDEXED_SEXTLOAD\0"
  /* 314 */ "G_SEXTLOAD\0"
  /* 325 */ "G_INDEXED_ZEXTLOAD\0"
  /* 344 */ "G_ZEXTLOAD\0"
  /* 355 */ "G_INDEXED_LOAD\0"
  /* 370 */ "G_LOAD\0"
  /* 377 */ "G_VECREDUCE_FADD\0"
  /* 394 */ "G_FADD\0"
  /* 401 */ "G_VECREDUCE_SEQ_FADD\0"
  /* 422 */ "G_STRICT_FADD\0"
  /* 436 */ "G_ATOMICRMW_FADD\0"
  /* 453 */ "G_VECREDUCE_ADD\0"
  /* 469 */ "G_ADD\0"
  /* 475 */ "G_PTR_ADD\0"
  /* 485 */ "G_ATOMICRMW_ADD\0"
  /* 501 */ "G_ATOMICRMW_NAND\0"
  /* 518 */ "G_VECREDUCE_AND\0"
  /* 534 */ "G_AND\0"
  /* 540 */ "G_ATOMICRMW_AND\0"
  /* 556 */ "LIFETIME_END\0"
  /* 569 */ "G_BRCOND\0"
  /* 578 */ "G_LLROUND\0"
  /* 588 */ "G_LROUND\0"
  /* 597 */ "G_INTRINSIC_ROUND\0"
  /* 615 */ "G_INTRINSIC_FPTRUNC_ROUND\0"
  /* 641 */ "LOAD_STACK_GUARD\0"
  /* 658 */ "PSEUDO_PROBE\0"
  /* 671 */ "G_SSUBE\0"
  /* 679 */ "G_USUBE\0"
  /* 687 */ "G_FENCE\0"
  /* 695 */ "ARITH_FENCE\0"
  /* 707 */ "REG_SEQUENCE\0"
  /* 720 */ "G_SADDE\0"
  /* 728 */ "G_UADDE\0"
  /* 736 */ "G_GET_FPMODE\0"
  /* 749 */ "G_RESET_FPMODE\0"
  /* 764 */ "G_SET_FPMODE\0"
  /* 777 */ "G_FMINNUM_IEEE\0"
  /* 792 */ "G_FMAXNUM_IEEE\0"
  /* 807 */ "G_VSCALE\0"
  /* 816 */ "G_JUMP_TABLE\0"
  /* 829 */ "BUNDLE\0"
  /* 836 */ "G_MEMCPY_INLINE\0"
  /* 852 */ "LOCAL_ESCAPE\0"
  /* 865 */ "G_STACKRESTORE\0"
  /* 880 */ "G_INDEXED_STORE\0"
  /* 896 */ "G_STORE\0"
  /* 904 */ "G_BITREVERSE\0"
  /* 917 */ "FAKE_USE\0"
  /* 926 */ "DBG_VALUE\0"
  /* 936 */ "G_GLOBAL_VALUE\0"
  /* 951 */ "G_PTRAUTH_GLOBAL_VALUE\0"
  /* 974 */ "CONVERGENCECTRL_GLUE\0"
  /* 995 */ "G_STACKSAVE\0"
  /* 1007 */ "G_MEMMOVE\0"
  /* 1017 */ "G_FREEZE\0"
  /* 1026 */ "G_FCANONICALIZE\0"
  /* 1042 */ "G_CTLZ_ZERO_UNDEF\0"
  /* 1060 */ "G_CTTZ_ZERO_UNDEF\0"
  /* 1078 */ "G_IMPLICIT_DEF\0"
  /* 1093 */ "DBG_INSTR_REF\0"
  /* 1107 */ "G_FNEG\0"
  /* 1114 */ "EXTRACT_SUBREG\0"
  /* 1129 */ "INSERT_SUBREG\0"
  /* 1143 */ "G_SEXT_INREG\0"
  /* 1156 */ "SUBREG_TO_REG\0"
  /* 1170 */ "G_ATOMIC_CMPXCHG\0"
  /* 1187 */ "G_ATOMICRMW_XCHG\0"
  /* 1204 */ "G_FLOG\0"
  /* 1211 */ "G_VAARG\0"
  /* 1219 */ "PREALLOCATED_ARG\0"
  /* 1236 */ "G_PREFETCH\0"
  /* 1247 */ "G_SMULH\0"
  /* 1255 */ "G_UMULH\0"
  /* 1263 */ "G_FTANH\0"
  /* 1271 */ "G_FSINH\0"
  /* 1279 */ "G_FCOSH\0"
  /* 1287 */ "DBG_PHI\0"
  /* 1295 */ "G_FPTOSI\0"
  /* 1304 */ "RETI\0"
  /* 1309 */ "G_FPTOUI\0"
  /* 1318 */ "G_FPOWI\0"
  /* 1326 */ "G_PTRMASK\0"
  /* 1336 */ "GC_LABEL\0"
  /* 1345 */ "DBG_LABEL\0"
  /* 1355 */ "EH_LABEL\0"
  /* 1364 */ "ANNOTATION_LABEL\0"
  /* 1381 */ "ICALL_BRANCH_FUNNEL\0"
  /* 1401 */ "G_FSHL\0"
  /* 1408 */ "G_SHL\0"
  /* 1414 */ "G_FCEIL\0"
  /* 1422 */ "PATCHABLE_TAIL_CALL\0"
  /* 1442 */ "PATCHABLE_TYPED_EVENT_CALL\0"
  /* 1469 */ "PATCHABLE_EVENT_CALL\0"
  /* 1490 */ "FENTRY_CALL\0"
  /* 1502 */ "KILL\0"
  /* 1507 */ "G_CONSTANT_POOL\0"
  /* 1523 */ "G_ROTL\0"
  /* 1530 */ "G_VECREDUCE_FMUL\0"
  /* 1547 */ "G_FMUL\0"
  /* 1554 */ "G_VECREDUCE_SEQ_FMUL\0"
  /* 1575 */ "G_STRICT_FMUL\0"
  /* 1589 */ "G_VECREDUCE_MUL\0"
  /* 1605 */ "G_MUL\0"
  /* 1611 */ "G_FREM\0"
  /* 1618 */ "G_STRICT_FREM\0"
  /* 1632 */ "G_SREM\0"
  /* 1639 */ "G_UREM\0"
  /* 1646 */ "G_SDIVREM\0"
  /* 1656 */ "G_UDIVREM\0"
  /* 1666 */ "INLINEASM\0"
  /* 1676 */ "G_VECREDUCE_FMINIMUM\0"
  /* 1697 */ "G_FMINIMUM\0"
  /* 1708 */ "G_VECREDUCE_FMAXIMUM\0"
  /* 1729 */ "G_FMAXIMUM\0"
  /* 1740 */ "G_FMINNUM\0"
  /* 1750 */ "G_FMAXNUM\0"
  /* 1760 */ "G_FATAN\0"
  /* 1768 */ "G_FTAN\0"
  /* 1775 */ "G_INTRINSIC_ROUNDEVEN\0"
  /* 1797 */ "G_ASSERT_ALIGN\0"
  /* 1812 */ "G_FCOPYSIGN\0"
  /* 1824 */ "G_VECREDUCE_FMIN\0"
  /* 1841 */ "G_ATOMICRMW_FMIN\0"
  /* 1858 */ "G_VECREDUCE_SMIN\0"
  /* 1875 */ "G_SMIN\0"
  /* 1882 */ "G_VECREDUCE_UMIN\0"
  /* 1899 */ "G_UMIN\0"
  /* 1906 */ "G_ATOMICRMW_UMIN\0"
  /* 1923 */ "G_ATOMICRMW_MIN\0"
  /* 1939 */ "G_FASIN\0"
  /* 1947 */ "G_FSIN\0"
  /* 1954 */ "CFI_INSTRUCTION\0"
  /* 1970 */ "ADJCALLSTACKDOWN\0"
  /* 1987 */ "G_SSUBO\0"
  /* 1995 */ "G_USUBO\0"
  /* 2003 */ "G_SADDO\0"
  /* 2011 */ "G_UADDO\0"
  /* 2019 */ "JUMP_TABLE_DEBUG_INFO\0"
  /* 2041 */ "G_SMULO\0"
  /* 2049 */ "G_UMULO\0"
  /* 2057 */ "G_BZERO\0"
  /* 2065 */ "STACKMAP\0"
  /* 2074 */ "G_DEBUGTRAP\0"
  /* 2086 */ "G_UBSANTRAP\0"
  /* 2098 */ "G_TRAP\0"
  /* 2105 */ "G_ATOMICRMW_UDEC_WRAP\0"
  /* 2127 */ "G_ATOMICRMW_UINC_WRAP\0"
  /* 2149 */ "G_BSWAP\0"
  /* 2157 */ "G_SITOFP\0"
  /* 2166 */ "G_UITOFP\0"
  /* 2175 */ "G_FCMP\0"
  /* 2182 */ "G_ICMP\0"
  /* 2189 */ "G_SCMP\0"
  /* 2196 */ "G_UCMP\0"
  /* 2203 */ "JMP\0"
  /* 2207 */ "CONVERGENCECTRL_LOOP\0"
  /* 2228 */ "G_CTPOP\0"
  /* 2236 */ "PATCHABLE_OP\0"
  /* 2249 */ "FAULTING_OP\0"
  /* 2261 */ "ADJCALLSTACKUP\0"
  /* 2276 */ "PREALLOCATED_SETUP\0"
  /* 2295 */ "G_FLDEXP\0"
  /* 2304 */ "G_STRICT_FLDEXP\0"
  /* 2320 */ "G_FEXP\0"
  /* 2327 */ "G_FFREXP\0"
  /* 2336 */ "G_BR\0"
  /* 2341 */ "INLINEASM_BR\0"
  /* 2354 */ "G_BLOCK_ADDR\0"
  /* 2367 */ "MEMBARRIER\0"
  /* 2378 */ "G_CONSTANT_FOLD_BARRIER\0"
  /* 2402 */ "PATCHABLE_FUNCTION_ENTER\0"
  /* 2427 */ "G_READCYCLECOUNTER\0"
  /* 2446 */ "G_READSTEADYCOUNTER\0"
  /* 2466 */ "G_READ_REGISTER\0"
  /* 2482 */ "G_WRITE_REGISTER\0"
  /* 2499 */ "G_ASHR\0"
  /* 2506 */ "G_FSHR\0"
  /* 2513 */ "G_LSHR\0"
  /* 2520 */ "CONVERGENCECTRL_ANCHOR\0"
  /* 2543 */ "G_FFLOOR\0"
  /* 2552 */ "G_EXTRACT_SUBVECTOR\0"
  /* 2572 */ "G_INSERT_SUBVECTOR\0"
  /* 2591 */ "G_BUILD_VECTOR\0"
  /* 2606 */ "G_SHUFFLE_VECTOR\0"
  /* 2623 */ "G_SPLAT_VECTOR\0"
  /* 2638 */ "G_VECREDUCE_XOR\0"
  /* 2654 */ "G_XOR\0"
  /* 2660 */ "G_ATOMICRMW_XOR\0"
  /* 2676 */ "G_VECREDUCE_OR\0"
  /* 2691 */ "G_OR\0"
  /* 2696 */ "G_ATOMICRMW_OR\0"
  /* 2711 */ "G_ROTR\0"
  /* 2718 */ "G_INTTOPTR\0"
  /* 2729 */ "G_FABS\0"
  /* 2736 */ "G_ABS\0"
  /* 2742 */ "G_UNMERGE_VALUES\0"
  /* 2759 */ "G_MERGE_VALUES\0"
  /* 2774 */ "G_FACOS\0"
  /* 2782 */ "G_FCOS\0"
  /* 2789 */ "G_CONCAT_VECTORS\0"
  /* 2806 */ "COPY_TO_REGCLASS\0"
  /* 2823 */ "G_IS_FPCLASS\0"
  /* 2836 */ "G_ATOMIC_CMPXCHG_WITH_SUCCESS\0"
  /* 2866 */ "G_VECTOR_COMPRESS\0"
  /* 2884 */ "G_INTRINSIC_W_SIDE_EFFECTS\0"
  /* 2911 */ "G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS\0"
  /* 2949 */ "G_SSUBSAT\0"
  /* 2959 */ "G_USUBSAT\0"
  /* 2969 */ "G_SADDSAT\0"
  /* 2979 */ "G_UADDSAT\0"
  /* 2989 */ "G_SSHLSAT\0"
  /* 2999 */ "G_USHLSAT\0"
  /* 3009 */ "G_SMULFIXSAT\0"
  /* 3022 */ "G_UMULFIXSAT\0"
  /* 3035 */ "G_SDIVFIXSAT\0"
  /* 3048 */ "G_UDIVFIXSAT\0"
  /* 3061 */ "G_EXTRACT\0"
  /* 3071 */ "G_SELECT\0"
  /* 3080 */ "G_BRINDIRECT\0"
  /* 3093 */ "PATCHABLE_RET\0"
  /* 3107 */ "G_MEMSET\0"
  /* 3116 */ "PATCHABLE_FUNCTION_EXIT\0"
  /* 3140 */ "G_BRJT\0"
  /* 3147 */ "G_EXTRACT_VECTOR_ELT\0"
  /* 3168 */ "G_INSERT_VECTOR_ELT\0"
  /* 3188 */ "G_FCONSTANT\0"
  /* 3200 */ "G_CONSTANT\0"
  /* 3211 */ "G_INTRINSIC_CONVERGENT\0"
  /* 3234 */ "STATEPOINT\0"
  /* 3245 */ "PATCHPOINT\0"
  /* 3256 */ "G_PTRTOINT\0"
  /* 3267 */ "G_FRINT\0"
  /* 3275 */ "G_INTRINSIC_LLRINT\0"
  /* 3294 */ "G_INTRINSIC_LRINT\0"
  /* 3312 */ "G_FNEARBYINT\0"
  /* 3325 */ "G_VASTART\0"
  /* 3335 */ "LIFETIME_START\0"
  /* 3350 */ "G_INVOKE_REGION_START\0"
  /* 3372 */ "G_INSERT\0"
  /* 3381 */ "G_FSQRT\0"
  /* 3389 */ "G_STRICT_FSQRT\0"
  /* 3404 */ "G_BITCAST\0"
  /* 3414 */ "G_ADDRSPACE_CAST\0"
  /* 3431 */ "DBG_VALUE_LIST\0"
  /* 3446 */ "G_FPEXT\0"
  /* 3454 */ "G_SEXT\0"
  /* 3461 */ "G_ASSERT_SEXT\0"
  /* 3475 */ "G_ANYEXT\0"
  /* 3484 */ "G_ZEXT\0"
  /* 3491 */ "G_ASSERT_ZEXT\0"
  /* 3505 */ "G_FDIV\0"
  /* 3512 */ "G_STRICT_FDIV\0"
  /* 3526 */ "G_SDIV\0"
  /* 3533 */ "G_UDIV\0"
  /* 3540 */ "G_GET_FPENV\0"
  /* 3552 */ "G_RESET_FPENV\0"
  /* 3566 */ "G_SET_FPENV\0"
  /* 3578 */ "G_FPOW\0"
  /* 3585 */ "G_VECREDUCE_FMAX\0"
  /* 3602 */ "G_ATOMICRMW_FMAX\0"
  /* 3619 */ "G_VECREDUCE_SMAX\0"
  /* 3636 */ "G_SMAX\0"
  /* 3643 */ "G_VECREDUCE_UMAX\0"
  /* 3660 */ "G_UMAX\0"
  /* 3667 */ "G_ATOMICRMW_UMAX\0"
  /* 3684 */ "G_ATOMICRMW_MAX\0"
  /* 3700 */ "G_FRAME_INDEX\0"
  /* 3714 */ "G_SBFX\0"
  /* 3721 */ "G_UBFX\0"
  /* 3728 */ "G_SMULFIX\0"
  /* 3738 */ "G_UMULFIX\0"
  /* 3748 */ "G_SDIVFIX\0"
  /* 3758 */ "G_UDIVFIX\0"
  /* 3768 */ "G_MEMCPY\0"
  /* 3777 */ "COPY\0"
  /* 3782 */ "CONVERGENCECTRL_ENTRY\0"
  /* 3804 */ "G_CTLZ\0"
  /* 3811 */ "G_CTTZ\0"
  /* 3818 */ "PUSH16c\0"
  /* 3826 */ "SUB16mc\0"
  /* 3834 */ "SUBC16mc\0"
  /* 3843 */ "ADDC16mc\0"
  /* 3852 */ "BIC16mc\0"
  /* 3860 */ "DADD16mc\0"
  /* 3869 */ "AND16mc\0"
  /* 3877 */ "CMP16mc\0"
  /* 3885 */ "XOR16mc\0"
  /* 3893 */ "BIS16mc\0"
  /* 3901 */ "BIT16mc\0"
  /* 3909 */ "MOV16mc\0"
  /* 3917 */ "SUB8mc\0"
  /* 3924 */ "SUBC8mc\0"
  /* 3932 */ "ADDC8mc\0"
  /* 3940 */ "BIC8mc\0"
  /* 3947 */ "DADD8mc\0"
  /* 3955 */ "AND8mc\0"
  /* 3962 */ "CMP8mc\0"
  /* 3969 */ "XOR8mc\0"
  /* 3976 */ "BIS8mc\0"
  /* 3983 */ "BIT8mc\0"
  /* 3990 */ "MOV8mc\0"
  /* 3997 */ "SUB16rc\0"
  /* 4005 */ "SUBC16rc\0"
  /* 4014 */ "ADDC16rc\0"
  /* 4023 */ "BIC16rc\0"
  /* 4031 */ "DADD16rc\0"
  /* 4040 */ "AND16rc\0"
  /* 4048 */ "CMP16rc\0"
  /* 4056 */ "XOR16rc\0"
  /* 4064 */ "BIS16rc\0"
  /* 4072 */ "BIT16rc\0"
  /* 4080 */ "MOV16rc\0"
  /* 4088 */ "SUB8rc\0"
  /* 4095 */ "SUBC8rc\0"
  /* 4103 */ "ADDC8rc\0"
  /* 4111 */ "BIC8rc\0"
  /* 4118 */ "DADD8rc\0"
  /* 4126 */ "AND8rc\0"
  /* 4133 */ "CMP8rc\0"
  /* 4140 */ "XOR8rc\0"
  /* 4147 */ "BIS8rc\0"
  /* 4154 */ "BIT8rc\0"
  /* 4161 */ "MOV8rc\0"
  /* 4168 */ "ADDframe\0"
  /* 4177 */ "PUSH16i\0"
  /* 4185 */ "Bi\0"
  /* 4188 */ "CALLi\0"
  /* 4194 */ "SUB16mi\0"
  /* 4202 */ "SUBC16mi\0"
  /* 4211 */ "ADDC16mi\0"
  /* 4220 */ "BIC16mi\0"
  /* 4228 */ "DADD16mi\0"
  /* 4237 */ "AND16mi\0"
  /* 4245 */ "CMP16mi\0"
  /* 4253 */ "XOR16mi\0"
  /* 4261 */ "BIS16mi\0"
  /* 4269 */ "BIT16mi\0"
  /* 4277 */ "MOV16mi\0"
  /* 4285 */ "SUB8mi\0"
  /* 4292 */ "SUBC8mi\0"
  /* 4300 */ "ADDC8mi\0"
  /* 4308 */ "BIC8mi\0"
  /* 4315 */ "DADD8mi\0"
  /* 4323 */ "AND8mi\0"
  /* 4330 */ "CMP8mi\0"
  /* 4337 */ "XOR8mi\0"
  /* 4344 */ "BIS8mi\0"
  /* 4351 */ "BIT8mi\0"
  /* 4358 */ "MOV8mi\0"
  /* 4365 */ "SUB16ri\0"
  /* 4373 */ "SUBC16ri\0"
  /* 4382 */ "ADDC16ri\0"
  /* 4391 */ "BIC16ri\0"
  /* 4399 */ "DADD16ri\0"
  /* 4408 */ "AND16ri\0"
  /* 4416 */ "CMP16ri\0"
  /* 4424 */ "XOR16ri\0"
  /* 4432 */ "BIS16ri\0"
  /* 4440 */ "BIT16ri\0"
  /* 4448 */ "MOV16ri\0"
  /* 4456 */ "SUB8ri\0"
  /* 4463 */ "SUBC8ri\0"
  /* 4471 */ "ADDC8ri\0"
  /* 4479 */ "BIC8ri\0"
  /* 4486 */ "DADD8ri\0"
  /* 4494 */ "AND8ri\0"
  /* 4501 */ "CMP8ri\0"
  /* 4508 */ "XOR8ri\0"
  /* 4515 */ "BIS8ri\0"
  /* 4522 */ "BIT8ri\0"
  /* 4529 */ "MOV8ri\0"
  /* 4536 */ "RRA16m\0"
  /* 4543 */ "SWPB16m\0"
  /* 4551 */ "RRC16m\0"
  /* 4558 */ "SEXT16m\0"
  /* 4566 */ "RRA8m\0"
  /* 4572 */ "RRC8m\0"
  /* 4578 */ "Bm\0"
  /* 4581 */ "CALLm\0"
  /* 4587 */ "SUB16mm\0"
  /* 4595 */ "SUBC16mm\0"
  /* 4604 */ "ADDC16mm\0"
  /* 4613 */ "BIC16mm\0"
  /* 4621 */ "DADD16mm\0"
  /* 4630 */ "AND16mm\0"
  /* 4638 */ "CMP16mm\0"
  /* 4646 */ "XOR16mm\0"
  /* 4654 */ "BIS16mm\0"
  /* 4662 */ "BIT16mm\0"
  /* 4670 */ "MOV16mm\0"
  /* 4678 */ "SUB8mm\0"
  /* 4685 */ "SUBC8mm\0"
  /* 4693 */ "ADDC8mm\0"
  /* 4701 */ "BIC8mm\0"
  /* 4708 */ "DADD8mm\0"
  /* 4716 */ "AND8mm\0"
  /* 4723 */ "CMP8mm\0"
  /* 4730 */ "XOR8mm\0"
  /* 4737 */ "BIS8mm\0"
  /* 4744 */ "BIT8mm\0"
  /* 4751 */ "MOV8mm\0"
  /* 4758 */ "SUB16rm\0"
  /* 4766 */ "SUBC16rm\0"
  /* 4775 */ "ADDC16rm\0"
  /* 4784 */ "BIC16rm\0"
  /* 4792 */ "DADD16rm\0"
  /* 4801 */ "AND16rm\0"
  /* 4809 */ "CMP16rm\0"
  /* 4817 */ "XOR16rm\0"
  /* 4825 */ "BIS16rm\0"
  /* 4833 */ "BIT16rm\0"
  /* 4841 */ "MOV16rm\0"
  /* 4849 */ "SUB8rm\0"
  /* 4856 */ "SUBC8rm\0"
  /* 4864 */ "ADDC8rm\0"
  /* 4872 */ "BIC8rm\0"
  /* 4879 */ "DADD8rm\0"
  /* 4887 */ "AND8rm\0"
  /* 4894 */ "CMP8rm\0"
  /* 4901 */ "XOR8rm\0"
  /* 4908 */ "BIS8rm\0"
  /* 4915 */ "BIT8rm\0"
  /* 4922 */ "MOV8rm\0"
  /* 4929 */ "RRA16n\0"
  /* 4936 */ "SWPB16n\0"
  /* 4944 */ "RRC16n\0"
  /* 4951 */ "SEXT16n\0"
  /* 4959 */ "RRA8n\0"
  /* 4965 */ "RRC8n\0"
  /* 4971 */ "CALLn\0"
  /* 4977 */ "SUB16mn\0"
  /* 4985 */ "SUBC16mn\0"
  /* 4994 */ "ADDC16mn\0"
  /* 5003 */ "BIC16mn\0"
  /* 5011 */ "DADD16mn\0"
  /* 5020 */ "AND16mn\0"
  /* 5028 */ "CMP16mn\0"
  /* 5036 */ "XOR16mn\0"
  /* 5044 */ "BIS16mn\0"
  /* 5052 */ "BIT16mn\0"
  /* 5060 */ "MOV16mn\0"
  /* 5068 */ "SUB8mn\0"
  /* 5075 */ "SUBC8mn\0"
  /* 5083 */ "ADDC8mn\0"
  /* 5091 */ "BIC8mn\0"
  /* 5098 */ "DADD8mn\0"
  /* 5106 */ "AND8mn\0"
  /* 5113 */ "CMP8mn\0"
  /* 5120 */ "XOR8mn\0"
  /* 5127 */ "BIS8mn\0"
  /* 5134 */ "BIT8mn\0"
  /* 5141 */ "MOV8mn\0"
  /* 5148 */ "SUB16rn\0"
  /* 5156 */ "SUBC16rn\0"
  /* 5165 */ "ADDC16rn\0"
  /* 5174 */ "BIC16rn\0"
  /* 5182 */ "DADD16rn\0"
  /* 5191 */ "AND16rn\0"
  /* 5199 */ "CMP16rn\0"
  /* 5207 */ "XOR16rn\0"
  /* 5215 */ "BIS16rn\0"
  /* 5223 */ "BIT16rn\0"
  /* 5231 */ "MOV16rn\0"
  /* 5239 */ "SUB8rn\0"
  /* 5246 */ "SUBC8rn\0"
  /* 5254 */ "ADDC8rn\0"
  /* 5262 */ "BIC8rn\0"
  /* 5269 */ "DADD8rn\0"
  /* 5277 */ "AND8rn\0"
  /* 5284 */ "CMP8rn\0"
  /* 5291 */ "XOR8rn\0"
  /* 5298 */ "BIS8rn\0"
  /* 5305 */ "BIT8rn\0"
  /* 5312 */ "MOV8rn\0"
  /* 5319 */ "RRA16p\0"
  /* 5326 */ "SWPB16p\0"
  /* 5334 */ "RRC16p\0"
  /* 5341 */ "SEXT16p\0"
  /* 5349 */ "RRA8p\0"
  /* 5355 */ "RRC8p\0"
  /* 5361 */ "CALLp\0"
  /* 5367 */ "SUB16mp\0"
  /* 5375 */ "SUBC16mp\0"
  /* 5384 */ "ADDC16mp\0"
  /* 5393 */ "BIC16mp\0"
  /* 5401 */ "DADD16mp\0"
  /* 5410 */ "AND16mp\0"
  /* 5418 */ "CMP16mp\0"
  /* 5426 */ "XOR16mp\0"
  /* 5434 */ "BIS16mp\0"
  /* 5442 */ "BIT16mp\0"
  /* 5450 */ "SUB8mp\0"
  /* 5457 */ "SUBC8mp\0"
  /* 5465 */ "ADDC8mp\0"
  /* 5473 */ "BIC8mp\0"
  /* 5480 */ "DADD8mp\0"
  /* 5488 */ "AND8mp\0"
  /* 5495 */ "CMP8mp\0"
  /* 5502 */ "XOR8mp\0"
  /* 5509 */ "BIS8mp\0"
  /* 5516 */ "BIT8mp\0"
  /* 5523 */ "SUB16rp\0"
  /* 5531 */ "SUBC16rp\0"
  /* 5540 */ "ADDC16rp\0"
  /* 5549 */ "BIC16rp\0"
  /* 5557 */ "DADD16rp\0"
  /* 5566 */ "AND16rp\0"
  /* 5574 */ "CMP16rp\0"
  /* 5582 */ "XOR16rp\0"
  /* 5590 */ "BIS16rp\0"
  /* 5598 */ "BIT16rp\0"
  /* 5606 */ "MOV16rp\0"
  /* 5614 */ "SUB8rp\0"
  /* 5621 */ "SUBC8rp\0"
  /* 5629 */ "ADDC8rp\0"
  /* 5637 */ "BIC8rp\0"
  /* 5644 */ "DADD8rp\0"
  /* 5652 */ "AND8rp\0"
  /* 5659 */ "CMP8rp\0"
  /* 5666 */ "XOR8rp\0"
  /* 5673 */ "BIS8rp\0"
  /* 5680 */ "BIT8rp\0"
  /* 5687 */ "MOV8rp\0"
  /* 5694 */ "RRA16r\0"
  /* 5701 */ "SWPB16r\0"
  /* 5709 */ "RRC16r\0"
  /* 5716 */ "PUSH16r\0"
  /* 5724 */ "POP16r\0"
  /* 5731 */ "SEXT16r\0"
  /* 5739 */ "ZEXT16r\0"
  /* 5747 */ "RRA8r\0"
  /* 5753 */ "RRC8r\0"
  /* 5759 */ "PUSH8r\0"
  /* 5766 */ "Br\0"
  /* 5769 */ "CALLr\0"
  /* 5775 */ "SUB16mr\0"
  /* 5783 */ "SUBC16mr\0"
  /* 5792 */ "ADDC16mr\0"
  /* 5801 */ "BIC16mr\0"
  /* 5809 */ "DADD16mr\0"
  /* 5818 */ "AND16mr\0"
  /* 5826 */ "CMP16mr\0"
  /* 5834 */ "XOR16mr\0"
  /* 5842 */ "BIS16mr\0"
  /* 5850 */ "BIT16mr\0"
  /* 5858 */ "MOV16mr\0"
  /* 5866 */ "SUB8mr\0"
  /* 5873 */ "SUBC8mr\0"
  /* 5881 */ "ADDC8mr\0"
  /* 5889 */ "BIC8mr\0"
  /* 5896 */ "DADD8mr\0"
  /* 5904 */ "AND8mr\0"
  /* 5911 */ "CMP8mr\0"
  /* 5918 */ "XOR8mr\0"
  /* 5925 */ "BIS8mr\0"
  /* 5932 */ "BIT8mr\0"
  /* 5939 */ "MOV8mr\0"
  /* 5946 */ "SUB16rr\0"
  /* 5954 */ "SUBC16rr\0"
  /* 5963 */ "ADDC16rr\0"
  /* 5972 */ "BIC16rr\0"
  /* 5980 */ "DADD16rr\0"
  /* 5989 */ "AND16rr\0"
  /* 5997 */ "CMP16rr\0"
  /* 6005 */ "XOR16rr\0"
  /* 6013 */ "BIS16rr\0"
  /* 6021 */ "BIT16rr\0"
  /* 6029 */ "MOV16rr\0"
  /* 6037 */ "SUB8rr\0"
  /* 6044 */ "SUBC8rr\0"
  /* 6052 */ "ADDC8rr\0"
  /* 6060 */ "BIC8rr\0"
  /* 6067 */ "DADD8rr\0"
  /* 6075 */ "AND8rr\0"
  /* 6082 */ "CMP8rr\0"
  /* 6089 */ "XOR8rr\0"
  /* 6096 */ "BIS8rr\0"
  /* 6103 */ "BIT8rr\0"
  /* 6110 */ "MOV8rr\0"
};
#ifdef __GNUC__
#pragma GCC diagnostic pop
#endif

extern const unsigned MSP430InstrNameIndices[] = {
    1291U, 1666U, 2341U, 1954U, 1355U, 1336U, 1364U, 1502U, 
    1114U, 1129U, 1080U, 1156U, 2806U, 926U, 3431U, 1093U, 
    1287U, 1345U, 707U, 3777U, 829U, 3335U, 556U, 658U, 
    695U, 2065U, 1490U, 3245U, 641U, 2276U, 1219U, 3234U, 
    852U, 2249U, 2236U, 2402U, 3093U, 3116U, 1422U, 1469U, 
    1442U, 1381U, 917U, 2367U, 2019U, 3782U, 2520U, 2207U, 
    974U, 3461U, 3491U, 1797U, 469U, 176U, 1605U, 3526U, 
    3533U, 1632U, 1639U, 1646U, 1656U, 534U, 2691U, 2654U, 
    1078U, 1289U, 3700U, 936U, 951U, 1507U, 3061U, 2742U, 
    3372U, 2759U, 2591U, 250U, 2789U, 3256U, 2718U, 3404U, 
    1017U, 2378U, 615U, 224U, 597U, 3294U, 3275U, 1775U, 
    2427U, 2446U, 370U, 314U, 344U, 355U, 295U, 325U, 
    896U, 880U, 2836U, 1170U, 1187U, 485U, 182U, 540U, 
    501U, 2696U, 2660U, 3684U, 1923U, 3667U, 1906U, 436U, 
    159U, 3602U, 1841U, 2127U, 2105U, 687U, 1236U, 569U, 
    3080U, 3350U, 202U, 2884U, 3211U, 2911U, 3475U, 242U, 
    3200U, 3188U, 3325U, 1211U, 3454U, 1143U, 3484U, 1408U, 
    2513U, 2499U, 1401U, 2506U, 2711U, 1523U, 2182U, 2175U, 
    2189U, 2196U, 3071U, 2011U, 728U, 1995U, 679U, 2003U, 
    720U, 1987U, 671U, 2049U, 2041U, 1255U, 1247U, 2979U, 
    2969U, 2959U, 2949U, 2999U, 2989U, 3728U, 3738U, 3009U, 
    3022U, 3748U, 3758U, 3035U, 3048U, 394U, 138U, 1547U, 
    119U, 288U, 3505U, 1611U, 3578U, 1318U, 2320U, 26U, 
    9U, 1204U, 18U, 0U, 2295U, 2327U, 1107U, 3446U, 
    214U, 1295U, 1309U, 2157U, 2166U, 2729U, 1812U, 2823U, 
    1026U, 1740U, 1750U, 777U, 792U, 1697U, 1729U, 3540U, 
    3566U, 3552U, 736U, 764U, 749U, 475U, 1326U, 1875U, 
    3636U, 1899U, 3660U, 2736U, 588U, 578U, 2336U, 3140U, 
    807U, 2572U, 2552U, 3168U, 3147U, 2606U, 2623U, 2866U, 
    3811U, 1060U, 3804U, 1042U, 2228U, 2149U, 904U, 1414U, 
    2782U, 1947U, 1768U, 2774U, 1939U, 1760U, 1279U, 1271U, 
    1263U, 3381U, 2543U, 3267U, 3312U, 3414U, 2354U, 816U, 
    271U, 995U, 865U, 422U, 145U, 1575U, 3512U, 1618U, 
    125U, 3389U, 2304U, 2466U, 2482U, 3768U, 836U, 1007U, 
    3107U, 2057U, 2098U, 2074U, 2086U, 401U, 1554U, 377U, 
    1530U, 3585U, 1824U, 1708U, 1676U, 453U, 1589U, 518U, 
    2676U, 2638U, 3619U, 1858U, 3643U, 1882U, 3714U, 3721U, 
    3861U, 4229U, 4622U, 5012U, 5402U, 5810U, 4032U, 4400U, 
    4793U, 5183U, 5558U, 5981U, 3948U, 4316U, 4709U, 5099U, 
    5481U, 5897U, 4119U, 4487U, 4880U, 5270U, 5645U, 6068U, 
    3843U, 4211U, 4604U, 4994U, 5384U, 5792U, 4014U, 4382U, 
    4775U, 5165U, 5540U, 5963U, 3932U, 4300U, 4693U, 5083U, 
    5465U, 5881U, 4103U, 4471U, 4864U, 5254U, 5629U, 6052U, 
    4168U, 1970U, 2261U, 3869U, 4237U, 4630U, 5020U, 5410U, 
    5818U, 4040U, 4408U, 4801U, 5191U, 5566U, 5989U, 3955U, 
    4323U, 4716U, 5106U, 5488U, 5904U, 4126U, 4494U, 4887U, 
    5277U, 5652U, 6075U, 3852U, 4220U, 4613U, 5003U, 5393U, 
    5801U, 4023U, 4391U, 4784U, 5174U, 5549U, 5972U, 3940U, 
    4308U, 4701U, 5091U, 5473U, 5889U, 4111U, 4479U, 4872U, 
    5262U, 5637U, 6060U, 3893U, 4261U, 4654U, 5044U, 5434U, 
    5842U, 4064U, 4432U, 4825U, 5215U, 5590U, 6013U, 3976U, 
    4344U, 4737U, 5127U, 5509U, 5925U, 4147U, 4515U, 4908U, 
    5298U, 5673U, 6096U, 3901U, 4269U, 4662U, 5052U, 5442U, 
    5850U, 4072U, 4440U, 4833U, 5223U, 5598U, 6021U, 3983U, 
    4351U, 4744U, 5134U, 5516U, 5932U, 4154U, 4522U, 4915U, 
    5305U, 5680U, 6103U, 4185U, 4578U, 5766U, 4188U, 4581U, 
    4971U, 5361U, 5769U, 3877U, 4245U, 4638U, 5028U, 5418U, 
    5826U, 4048U, 4416U, 4809U, 5199U, 5574U, 5997U, 3962U, 
    4330U, 4723U, 5113U, 5495U, 5911U, 4133U, 4501U, 4894U, 
    5284U, 5659U, 6082U, 3860U, 4228U, 4621U, 5011U, 5401U, 
    5809U, 4031U, 4399U, 4792U, 5182U, 5557U, 5980U, 3947U, 
    4315U, 4708U, 5098U, 5480U, 5896U, 4118U, 4486U, 4879U, 
    5269U, 5644U, 6067U, 198U, 2203U, 3909U, 4277U, 4670U, 
    5060U, 5858U, 4080U, 4448U, 4841U, 5231U, 5606U, 6029U, 
    3990U, 4358U, 4751U, 5141U, 5939U, 4161U, 4529U, 4922U, 
    5312U, 5687U, 6110U, 89U, 100U, 5724U, 3818U, 4177U, 
    5716U, 5759U, 3103U, 1304U, 4536U, 4929U, 5319U, 5694U, 
    4566U, 4959U, 5349U, 5747U, 4551U, 4944U, 5334U, 5709U, 
    4572U, 4965U, 5355U, 5753U, 40U, 73U, 4558U, 4951U, 
    5341U, 5731U, 3826U, 4194U, 4587U, 4977U, 5367U, 5775U, 
    3997U, 4365U, 4758U, 5148U, 5523U, 5946U, 3917U, 4285U, 
    4678U, 5068U, 5450U, 5866U, 4088U, 4456U, 4849U, 5239U, 
    5614U, 6037U, 3834U, 4202U, 4595U, 4985U, 5375U, 5783U, 
    4005U, 4373U, 4766U, 5156U, 5531U, 5954U, 3924U, 4292U, 
    4685U, 5075U, 5457U, 5873U, 4095U, 4463U, 4856U, 5246U, 
    5621U, 6044U, 4543U, 4936U, 5326U, 5701U, 59U, 111U, 
    47U, 79U, 34U, 68U, 53U, 84U, 3885U, 4253U, 
    4646U, 5036U, 5426U, 5834U, 4056U, 4424U, 4817U, 5207U, 
    5582U, 6005U, 3969U, 4337U, 4730U, 5120U, 5502U, 5918U, 
    4140U, 4508U, 4901U, 5291U, 5666U, 6089U, 5739U, 
};

static inline void InitMSP430MCInstrInfo(MCInstrInfo *II) {
  II->InitMCInstrInfo(MSP430Descs.Insts, MSP430InstrNameIndices, MSP430InstrNameData, nullptr, nullptr, 639);
}

} // end namespace llvm
#endif // GET_INSTRINFO_MC_DESC

#ifdef GET_INSTRINFO_HEADER
#undef GET_INSTRINFO_HEADER
namespace llvm {
struct MSP430GenInstrInfo : public TargetInstrInfo {
  explicit MSP430GenInstrInfo(unsigned CFSetupOpcode = ~0u, unsigned CFDestroyOpcode = ~0u, unsigned CatchRetOpcode = ~0u, unsigned ReturnOpcode = ~0u);
  ~MSP430GenInstrInfo() override = default;

};
} // end namespace llvm
#endif // GET_INSTRINFO_HEADER

#ifdef GET_INSTRINFO_HELPER_DECLS
#undef GET_INSTRINFO_HELPER_DECLS


#endif // GET_INSTRINFO_HELPER_DECLS

#ifdef GET_INSTRINFO_HELPERS
#undef GET_INSTRINFO_HELPERS

#endif // GET_INSTRINFO_HELPERS

#ifdef GET_INSTRINFO_CTOR_DTOR
#undef GET_INSTRINFO_CTOR_DTOR
namespace llvm {
extern const MSP430InstrTable MSP430Descs;
extern const unsigned MSP430InstrNameIndices[];
extern const char MSP430InstrNameData[];
MSP430GenInstrInfo::MSP430GenInstrInfo(unsigned CFSetupOpcode, unsigned CFDestroyOpcode, unsigned CatchRetOpcode, unsigned ReturnOpcode)
  : TargetInstrInfo(CFSetupOpcode, CFDestroyOpcode, CatchRetOpcode, ReturnOpcode) {
  InitMCInstrInfo(MSP430Descs.Insts, MSP430InstrNameIndices, MSP430InstrNameData, nullptr, nullptr, 639);
}
} // end namespace llvm
#endif // GET_INSTRINFO_CTOR_DTOR

#ifdef GET_INSTRINFO_OPERAND_ENUM
#undef GET_INSTRINFO_OPERAND_ENUM
namespace llvm {
namespace MSP430 {
namespace OpName {
enum {
  OPERAND_LAST
};
} // end namespace OpName
} // end namespace MSP430
} // end namespace llvm
#endif //GET_INSTRINFO_OPERAND_ENUM

#ifdef GET_INSTRINFO_NAMED_OPS
#undef GET_INSTRINFO_NAMED_OPS
namespace llvm {
namespace MSP430 {
LLVM_READONLY
int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx) {
  return -1;
}
} // end namespace MSP430
} // end namespace llvm
#endif //GET_INSTRINFO_NAMED_OPS

#ifdef GET_INSTRINFO_OPERAND_TYPES_ENUM
#undef GET_INSTRINFO_OPERAND_TYPES_ENUM
namespace llvm {
namespace MSP430 {
namespace OpTypes {
enum OperandType {
  cc = 0,
  cg8imm = 1,
  cg16imm = 2,
  f32imm = 3,
  f64imm = 4,
  i1imm = 5,
  i8imm = 6,
  i16imm = 7,
  i32imm = 8,
  i64imm = 9,
  indreg = 10,
  jmptarget = 11,
  memdst = 12,
  memsrc = 13,
  postreg = 14,
  ptype0 = 15,
  ptype1 = 16,
  ptype2 = 17,
  ptype3 = 18,
  ptype4 = 19,
  ptype5 = 20,
  type0 = 21,
  type1 = 22,
  type2 = 23,
  type3 = 24,
  type4 = 25,
  type5 = 26,
  untyped_imm_0 = 27,
  GR8 = 28,
  GR16 = 29,
  OPERAND_TYPE_LIST_END
};
} // end namespace OpTypes
} // end namespace MSP430
} // end namespace llvm
#endif // GET_INSTRINFO_OPERAND_TYPES_ENUM

#ifdef GET_INSTRINFO_OPERAND_TYPE
#undef GET_INSTRINFO_OPERAND_TYPE
namespace llvm {
namespace MSP430 {
LLVM_READONLY
static int getOperandType(uint16_t Opcode, uint16_t OpIdx) {
  static const uint16_t Offsets[] = {
    /* PHI */
    0,
    /* INLINEASM */
    1,
    /* INLINEASM_BR */
    1,
    /* CFI_INSTRUCTION */
    1,
    /* EH_LABEL */
    2,
    /* GC_LABEL */
    3,
    /* ANNOTATION_LABEL */
    4,
    /* KILL */
    5,
    /* EXTRACT_SUBREG */
    5,
    /* INSERT_SUBREG */
    8,
    /* IMPLICIT_DEF */
    12,
    /* SUBREG_TO_REG */
    13,
    /* COPY_TO_REGCLASS */
    17,
    /* DBG_VALUE */
    20,
    /* DBG_VALUE_LIST */
    20,
    /* DBG_INSTR_REF */
    20,
    /* DBG_PHI */
    20,
    /* DBG_LABEL */
    20,
    /* REG_SEQUENCE */
    21,
    /* COPY */
    23,
    /* BUNDLE */
    25,
    /* LIFETIME_START */
    25,
    /* LIFETIME_END */
    26,
    /* PSEUDO_PROBE */
    27,
    /* ARITH_FENCE */
    31,
    /* STACKMAP */
    33,
    /* FENTRY_CALL */
    35,
    /* PATCHPOINT */
    35,
    /* LOAD_STACK_GUARD */
    41,
    /* PREALLOCATED_SETUP */
    42,
    /* PREALLOCATED_ARG */
    43,
    /* STATEPOINT */
    46,
    /* LOCAL_ESCAPE */
    46,
    /* FAULTING_OP */
    48,
    /* PATCHABLE_OP */
    49,
    /* PATCHABLE_FUNCTION_ENTER */
    49,
    /* PATCHABLE_RET */
    49,
    /* PATCHABLE_FUNCTION_EXIT */
    49,
    /* PATCHABLE_TAIL_CALL */
    49,
    /* PATCHABLE_EVENT_CALL */
    49,
    /* PATCHABLE_TYPED_EVENT_CALL */
    51,
    /* ICALL_BRANCH_FUNNEL */
    54,
    /* FAKE_USE */
    54,
    /* MEMBARRIER */
    54,
    /* JUMP_TABLE_DEBUG_INFO */
    54,
    /* CONVERGENCECTRL_ENTRY */
    55,
    /* CONVERGENCECTRL_ANCHOR */
    56,
    /* CONVERGENCECTRL_LOOP */
    57,
    /* CONVERGENCECTRL_GLUE */
    59,
    /* G_ASSERT_SEXT */
    60,
    /* G_ASSERT_ZEXT */
    63,
    /* G_ASSERT_ALIGN */
    66,
    /* G_ADD */
    69,
    /* G_SUB */
    72,
    /* G_MUL */
    75,
    /* G_SDIV */
    78,
    /* G_UDIV */
    81,
    /* G_SREM */
    84,
    /* G_UREM */
    87,
    /* G_SDIVREM */
    90,
    /* G_UDIVREM */
    94,
    /* G_AND */
    98,
    /* G_OR */
    101,
    /* G_XOR */
    104,
    /* G_IMPLICIT_DEF */
    107,
    /* G_PHI */
    108,
    /* G_FRAME_INDEX */
    109,
    /* G_GLOBAL_VALUE */
    111,
    /* G_PTRAUTH_GLOBAL_VALUE */
    113,
    /* G_CONSTANT_POOL */
    118,
    /* G_EXTRACT */
    120,
    /* G_UNMERGE_VALUES */
    123,
    /* G_INSERT */
    125,
    /* G_MERGE_VALUES */
    129,
    /* G_BUILD_VECTOR */
    131,
    /* G_BUILD_VECTOR_TRUNC */
    133,
    /* G_CONCAT_VECTORS */
    135,
    /* G_PTRTOINT */
    137,
    /* G_INTTOPTR */
    139,
    /* G_BITCAST */
    141,
    /* G_FREEZE */
    143,
    /* G_CONSTANT_FOLD_BARRIER */
    145,
    /* G_INTRINSIC_FPTRUNC_ROUND */
    147,
    /* G_INTRINSIC_TRUNC */
    150,
    /* G_INTRINSIC_ROUND */
    152,
    /* G_INTRINSIC_LRINT */
    154,
    /* G_INTRINSIC_LLRINT */
    156,
    /* G_INTRINSIC_ROUNDEVEN */
    158,
    /* G_READCYCLECOUNTER */
    160,
    /* G_READSTEADYCOUNTER */
    161,
    /* G_LOAD */
    162,
    /* G_SEXTLOAD */
    164,
    /* G_ZEXTLOAD */
    166,
    /* G_INDEXED_LOAD */
    168,
    /* G_INDEXED_SEXTLOAD */
    173,
    /* G_INDEXED_ZEXTLOAD */
    178,
    /* G_STORE */
    183,
    /* G_INDEXED_STORE */
    185,
    /* G_ATOMIC_CMPXCHG_WITH_SUCCESS */
    190,
    /* G_ATOMIC_CMPXCHG */
    195,
    /* G_ATOMICRMW_XCHG */
    199,
    /* G_ATOMICRMW_ADD */
    202,
    /* G_ATOMICRMW_SUB */
    205,
    /* G_ATOMICRMW_AND */
    208,
    /* G_ATOMICRMW_NAND */
    211,
    /* G_ATOMICRMW_OR */
    214,
    /* G_ATOMICRMW_XOR */
    217,
    /* G_ATOMICRMW_MAX */
    220,
    /* G_ATOMICRMW_MIN */
    223,
    /* G_ATOMICRMW_UMAX */
    226,
    /* G_ATOMICRMW_UMIN */
    229,
    /* G_ATOMICRMW_FADD */
    232,
    /* G_ATOMICRMW_FSUB */
    235,
    /* G_ATOMICRMW_FMAX */
    238,
    /* G_ATOMICRMW_FMIN */
    241,
    /* G_ATOMICRMW_UINC_WRAP */
    244,
    /* G_ATOMICRMW_UDEC_WRAP */
    247,
    /* G_FENCE */
    250,
    /* G_PREFETCH */
    252,
    /* G_BRCOND */
    256,
    /* G_BRINDIRECT */
    258,
    /* G_INVOKE_REGION_START */
    259,
    /* G_INTRINSIC */
    259,
    /* G_INTRINSIC_W_SIDE_EFFECTS */
    260,
    /* G_INTRINSIC_CONVERGENT */
    261,
    /* G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS */
    262,
    /* G_ANYEXT */
    263,
    /* G_TRUNC */
    265,
    /* G_CONSTANT */
    267,
    /* G_FCONSTANT */
    269,
    /* G_VASTART */
    271,
    /* G_VAARG */
    272,
    /* G_SEXT */
    275,
    /* G_SEXT_INREG */
    277,
    /* G_ZEXT */
    280,
    /* G_SHL */
    282,
    /* G_LSHR */
    285,
    /* G_ASHR */
    288,
    /* G_FSHL */
    291,
    /* G_FSHR */
    295,
    /* G_ROTR */
    299,
    /* G_ROTL */
    302,
    /* G_ICMP */
    305,
    /* G_FCMP */
    309,
    /* G_SCMP */
    313,
    /* G_UCMP */
    316,
    /* G_SELECT */
    319,
    /* G_UADDO */
    323,
    /* G_UADDE */
    327,
    /* G_USUBO */
    332,
    /* G_USUBE */
    336,
    /* G_SADDO */
    341,
    /* G_SADDE */
    345,
    /* G_SSUBO */
    350,
    /* G_SSUBE */
    354,
    /* G_UMULO */
    359,
    /* G_SMULO */
    363,
    /* G_UMULH */
    367,
    /* G_SMULH */
    370,
    /* G_UADDSAT */
    373,
    /* G_SADDSAT */
    376,
    /* G_USUBSAT */
    379,
    /* G_SSUBSAT */
    382,
    /* G_USHLSAT */
    385,
    /* G_SSHLSAT */
    388,
    /* G_SMULFIX */
    391,
    /* G_UMULFIX */
    395,
    /* G_SMULFIXSAT */
    399,
    /* G_UMULFIXSAT */
    403,
    /* G_SDIVFIX */
    407,
    /* G_UDIVFIX */
    411,
    /* G_SDIVFIXSAT */
    415,
    /* G_UDIVFIXSAT */
    419,
    /* G_FADD */
    423,
    /* G_FSUB */
    426,
    /* G_FMUL */
    429,
    /* G_FMA */
    432,
    /* G_FMAD */
    436,
    /* G_FDIV */
    440,
    /* G_FREM */
    443,
    /* G_FPOW */
    446,
    /* G_FPOWI */
    449,
    /* G_FEXP */
    452,
    /* G_FEXP2 */
    454,
    /* G_FEXP10 */
    456,
    /* G_FLOG */
    458,
    /* G_FLOG2 */
    460,
    /* G_FLOG10 */
    462,
    /* G_FLDEXP */
    464,
    /* G_FFREXP */
    467,
    /* G_FNEG */
    470,
    /* G_FPEXT */
    472,
    /* G_FPTRUNC */
    474,
    /* G_FPTOSI */
    476,
    /* G_FPTOUI */
    478,
    /* G_SITOFP */
    480,
    /* G_UITOFP */
    482,
    /* G_FABS */
    484,
    /* G_FCOPYSIGN */
    486,
    /* G_IS_FPCLASS */
    489,
    /* G_FCANONICALIZE */
    492,
    /* G_FMINNUM */
    494,
    /* G_FMAXNUM */
    497,
    /* G_FMINNUM_IEEE */
    500,
    /* G_FMAXNUM_IEEE */
    503,
    /* G_FMINIMUM */
    506,
    /* G_FMAXIMUM */
    509,
    /* G_GET_FPENV */
    512,
    /* G_SET_FPENV */
    513,
    /* G_RESET_FPENV */
    514,
    /* G_GET_FPMODE */
    514,
    /* G_SET_FPMODE */
    515,
    /* G_RESET_FPMODE */
    516,
    /* G_PTR_ADD */
    516,
    /* G_PTRMASK */
    519,
    /* G_SMIN */
    522,
    /* G_SMAX */
    525,
    /* G_UMIN */
    528,
    /* G_UMAX */
    531,
    /* G_ABS */
    534,
    /* G_LROUND */
    536,
    /* G_LLROUND */
    538,
    /* G_BR */
    540,
    /* G_BRJT */
    541,
    /* G_VSCALE */
    544,
    /* G_INSERT_SUBVECTOR */
    546,
    /* G_EXTRACT_SUBVECTOR */
    550,
    /* G_INSERT_VECTOR_ELT */
    553,
    /* G_EXTRACT_VECTOR_ELT */
    557,
    /* G_SHUFFLE_VECTOR */
    560,
    /* G_SPLAT_VECTOR */
    564,
    /* G_VECTOR_COMPRESS */
    566,
    /* G_CTTZ */
    570,
    /* G_CTTZ_ZERO_UNDEF */
    572,
    /* G_CTLZ */
    574,
    /* G_CTLZ_ZERO_UNDEF */
    576,
    /* G_CTPOP */
    578,
    /* G_BSWAP */
    580,
    /* G_BITREVERSE */
    582,
    /* G_FCEIL */
    584,
    /* G_FCOS */
    586,
    /* G_FSIN */
    588,
    /* G_FTAN */
    590,
    /* G_FACOS */
    592,
    /* G_FASIN */
    594,
    /* G_FATAN */
    596,
    /* G_FCOSH */
    598,
    /* G_FSINH */
    600,
    /* G_FTANH */
    602,
    /* G_FSQRT */
    604,
    /* G_FFLOOR */
    606,
    /* G_FRINT */
    608,
    /* G_FNEARBYINT */
    610,
    /* G_ADDRSPACE_CAST */
    612,
    /* G_BLOCK_ADDR */
    614,
    /* G_JUMP_TABLE */
    616,
    /* G_DYN_STACKALLOC */
    618,
    /* G_STACKSAVE */
    621,
    /* G_STACKRESTORE */
    622,
    /* G_STRICT_FADD */
    623,
    /* G_STRICT_FSUB */
    626,
    /* G_STRICT_FMUL */
    629,
    /* G_STRICT_FDIV */
    632,
    /* G_STRICT_FREM */
    635,
    /* G_STRICT_FMA */
    638,
    /* G_STRICT_FSQRT */
    642,
    /* G_STRICT_FLDEXP */
    644,
    /* G_READ_REGISTER */
    647,
    /* G_WRITE_REGISTER */
    649,
    /* G_MEMCPY */
    651,
    /* G_MEMCPY_INLINE */
    655,
    /* G_MEMMOVE */
    658,
    /* G_MEMSET */
    662,
    /* G_BZERO */
    666,
    /* G_TRAP */
    669,
    /* G_DEBUGTRAP */
    669,
    /* G_UBSANTRAP */
    669,
    /* G_VECREDUCE_SEQ_FADD */
    670,
    /* G_VECREDUCE_SEQ_FMUL */
    673,
    /* G_VECREDUCE_FADD */
    676,
    /* G_VECREDUCE_FMUL */
    678,
    /* G_VECREDUCE_FMAX */
    680,
    /* G_VECREDUCE_FMIN */
    682,
    /* G_VECREDUCE_FMAXIMUM */
    684,
    /* G_VECREDUCE_FMINIMUM */
    686,
    /* G_VECREDUCE_ADD */
    688,
    /* G_VECREDUCE_MUL */
    690,
    /* G_VECREDUCE_AND */
    692,
    /* G_VECREDUCE_OR */
    694,
    /* G_VECREDUCE_XOR */
    696,
    /* G_VECREDUCE_SMAX */
    698,
    /* G_VECREDUCE_SMIN */
    700,
    /* G_VECREDUCE_UMAX */
    702,
    /* G_VECREDUCE_UMIN */
    704,
    /* G_SBFX */
    706,
    /* G_UBFX */
    710,
    /* ADD16mc */
    714,
    /* ADD16mi */
    717,
    /* ADD16mm */
    720,
    /* ADD16mn */
    724,
    /* ADD16mp */
    727,
    /* ADD16mr */
    730,
    /* ADD16rc */
    733,
    /* ADD16ri */
    736,
    /* ADD16rm */
    739,
    /* ADD16rn */
    743,
    /* ADD16rp */
    746,
    /* ADD16rr */
    750,
    /* ADD8mc */
    753,
    /* ADD8mi */
    756,
    /* ADD8mm */
    759,
    /* ADD8mn */
    763,
    /* ADD8mp */
    766,
    /* ADD8mr */
    769,
    /* ADD8rc */
    772,
    /* ADD8ri */
    775,
    /* ADD8rm */
    778,
    /* ADD8rn */
    782,
    /* ADD8rp */
    785,
    /* ADD8rr */
    789,
    /* ADDC16mc */
    792,
    /* ADDC16mi */
    795,
    /* ADDC16mm */
    798,
    /* ADDC16mn */
    802,
    /* ADDC16mp */
    805,
    /* ADDC16mr */
    808,
    /* ADDC16rc */
    811,
    /* ADDC16ri */
    814,
    /* ADDC16rm */
    817,
    /* ADDC16rn */
    821,
    /* ADDC16rp */
    824,
    /* ADDC16rr */
    828,
    /* ADDC8mc */
    831,
    /* ADDC8mi */
    834,
    /* ADDC8mm */
    837,
    /* ADDC8mn */
    841,
    /* ADDC8mp */
    844,
    /* ADDC8mr */
    847,
    /* ADDC8rc */
    850,
    /* ADDC8ri */
    853,
    /* ADDC8rm */
    856,
    /* ADDC8rn */
    860,
    /* ADDC8rp */
    863,
    /* ADDC8rr */
    867,
    /* ADDframe */
    870,
    /* ADJCALLSTACKDOWN */
    873,
    /* ADJCALLSTACKUP */
    875,
    /* AND16mc */
    877,
    /* AND16mi */
    880,
    /* AND16mm */
    883,
    /* AND16mn */
    887,
    /* AND16mp */
    890,
    /* AND16mr */
    893,
    /* AND16rc */
    896,
    /* AND16ri */
    899,
    /* AND16rm */
    902,
    /* AND16rn */
    906,
    /* AND16rp */
    909,
    /* AND16rr */
    913,
    /* AND8mc */
    916,
    /* AND8mi */
    919,
    /* AND8mm */
    922,
    /* AND8mn */
    926,
    /* AND8mp */
    929,
    /* AND8mr */
    932,
    /* AND8rc */
    935,
    /* AND8ri */
    938,
    /* AND8rm */
    941,
    /* AND8rn */
    945,
    /* AND8rp */
    948,
    /* AND8rr */
    952,
    /* BIC16mc */
    955,
    /* BIC16mi */
    958,
    /* BIC16mm */
    961,
    /* BIC16mn */
    965,
    /* BIC16mp */
    968,
    /* BIC16mr */
    971,
    /* BIC16rc */
    974,
    /* BIC16ri */
    977,
    /* BIC16rm */
    980,
    /* BIC16rn */
    984,
    /* BIC16rp */
    987,
    /* BIC16rr */
    991,
    /* BIC8mc */
    994,
    /* BIC8mi */
    997,
    /* BIC8mm */
    1000,
    /* BIC8mn */
    1004,
    /* BIC8mp */
    1007,
    /* BIC8mr */
    1010,
    /* BIC8rc */
    1013,
    /* BIC8ri */
    1016,
    /* BIC8rm */
    1019,
    /* BIC8rn */
    1023,
    /* BIC8rp */
    1026,
    /* BIC8rr */
    1030,
    /* BIS16mc */
    1033,
    /* BIS16mi */
    1036,
    /* BIS16mm */
    1039,
    /* BIS16mn */
    1043,
    /* BIS16mp */
    1046,
    /* BIS16mr */
    1049,
    /* BIS16rc */
    1052,
    /* BIS16ri */
    1055,
    /* BIS16rm */
    1058,
    /* BIS16rn */
    1062,
    /* BIS16rp */
    1065,
    /* BIS16rr */
    1069,
    /* BIS8mc */
    1072,
    /* BIS8mi */
    1075,
    /* BIS8mm */
    1078,
    /* BIS8mn */
    1082,
    /* BIS8mp */
    1085,
    /* BIS8mr */
    1088,
    /* BIS8rc */
    1091,
    /* BIS8ri */
    1094,
    /* BIS8rm */
    1097,
    /* BIS8rn */
    1101,
    /* BIS8rp */
    1104,
    /* BIS8rr */
    1108,
    /* BIT16mc */
    1111,
    /* BIT16mi */
    1114,
    /* BIT16mm */
    1117,
    /* BIT16mn */
    1121,
    /* BIT16mp */
    1124,
    /* BIT16mr */
    1127,
    /* BIT16rc */
    1130,
    /* BIT16ri */
    1132,
    /* BIT16rm */
    1134,
    /* BIT16rn */
    1137,
    /* BIT16rp */
    1139,
    /* BIT16rr */
    1141,
    /* BIT8mc */
    1143,
    /* BIT8mi */
    1146,
    /* BIT8mm */
    1149,
    /* BIT8mn */
    1153,
    /* BIT8mp */
    1156,
    /* BIT8mr */
    1159,
    /* BIT8rc */
    1162,
    /* BIT8ri */
    1164,
    /* BIT8rm */
    1166,
    /* BIT8rn */
    1169,
    /* BIT8rp */
    1171,
    /* BIT8rr */
    1173,
    /* Bi */
    1175,
    /* Bm */
    1176,
    /* Br */
    1178,
    /* CALLi */
    1179,
    /* CALLm */
    1180,
    /* CALLn */
    1182,
    /* CALLp */
    1183,
    /* CALLr */
    1184,
    /* CMP16mc */
    1185,
    /* CMP16mi */
    1188,
    /* CMP16mm */
    1191,
    /* CMP16mn */
    1195,
    /* CMP16mp */
    1198,
    /* CMP16mr */
    1201,
    /* CMP16rc */
    1204,
    /* CMP16ri */
    1206,
    /* CMP16rm */
    1208,
    /* CMP16rn */
    1211,
    /* CMP16rp */
    1213,
    /* CMP16rr */
    1215,
    /* CMP8mc */
    1217,
    /* CMP8mi */
    1220,
    /* CMP8mm */
    1223,
    /* CMP8mn */
    1227,
    /* CMP8mp */
    1230,
    /* CMP8mr */
    1233,
    /* CMP8rc */
    1236,
    /* CMP8ri */
    1238,
    /* CMP8rm */
    1240,
    /* CMP8rn */
    1243,
    /* CMP8rp */
    1245,
    /* CMP8rr */
    1247,
    /* DADD16mc */
    1249,
    /* DADD16mi */
    1252,
    /* DADD16mm */
    1255,
    /* DADD16mn */
    1259,
    /* DADD16mp */
    1262,
    /* DADD16mr */
    1265,
    /* DADD16rc */
    1268,
    /* DADD16ri */
    1271,
    /* DADD16rm */
    1274,
    /* DADD16rn */
    1278,
    /* DADD16rp */
    1281,
    /* DADD16rr */
    1285,
    /* DADD8mc */
    1288,
    /* DADD8mi */
    1291,
    /* DADD8mm */
    1294,
    /* DADD8mn */
    1298,
    /* DADD8mp */
    1301,
    /* DADD8mr */
    1304,
    /* DADD8rc */
    1307,
    /* DADD8ri */
    1310,
    /* DADD8rm */
    1313,
    /* DADD8rn */
    1317,
    /* DADD8rp */
    1320,
    /* DADD8rr */
    1324,
    /* JCC */
    1327,
    /* JMP */
    1329,
    /* MOV16mc */
    1330,
    /* MOV16mi */
    1333,
    /* MOV16mm */
    1336,
    /* MOV16mn */
    1340,
    /* MOV16mr */
    1343,
    /* MOV16rc */
    1346,
    /* MOV16ri */
    1348,
    /* MOV16rm */
    1350,
    /* MOV16rn */
    1353,
    /* MOV16rp */
    1355,
    /* MOV16rr */
    1358,
    /* MOV8mc */
    1360,
    /* MOV8mi */
    1363,
    /* MOV8mm */
    1366,
    /* MOV8mn */
    1370,
    /* MOV8mr */
    1373,
    /* MOV8rc */
    1376,
    /* MOV8ri */
    1378,
    /* MOV8rm */
    1380,
    /* MOV8rn */
    1383,
    /* MOV8rp */
    1385,
    /* MOV8rr */
    1388,
    /* MOVZX16rm8 */
    1390,
    /* MOVZX16rr8 */
    1393,
    /* POP16r */
    1395,
    /* PUSH16c */
    1396,
    /* PUSH16i */
    1397,
    /* PUSH16r */
    1398,
    /* PUSH8r */
    1399,
    /* RET */
    1400,
    /* RETI */
    1400,
    /* RRA16m */
    1400,
    /* RRA16n */
    1402,
    /* RRA16p */
    1403,
    /* RRA16r */
    1404,
    /* RRA8m */
    1406,
    /* RRA8n */
    1408,
    /* RRA8p */
    1409,
    /* RRA8r */
    1410,
    /* RRC16m */
    1412,
    /* RRC16n */
    1414,
    /* RRC16p */
    1415,
    /* RRC16r */
    1416,
    /* RRC8m */
    1418,
    /* RRC8n */
    1420,
    /* RRC8p */
    1421,
    /* RRC8r */
    1422,
    /* Rrcl16 */
    1424,
    /* Rrcl8 */
    1426,
    /* SEXT16m */
    1428,
    /* SEXT16n */
    1430,
    /* SEXT16p */
    1431,
    /* SEXT16r */
    1432,
    /* SUB16mc */
    1434,
    /* SUB16mi */
    1437,
    /* SUB16mm */
    1440,
    /* SUB16mn */
    1444,
    /* SUB16mp */
    1447,
    /* SUB16mr */
    1450,
    /* SUB16rc */
    1453,
    /* SUB16ri */
    1456,
    /* SUB16rm */
    1459,
    /* SUB16rn */
    1463,
    /* SUB16rp */
    1466,
    /* SUB16rr */
    1470,
    /* SUB8mc */
    1473,
    /* SUB8mi */
    1476,
    /* SUB8mm */
    1479,
    /* SUB8mn */
    1483,
    /* SUB8mp */
    1486,
    /* SUB8mr */
    1489,
    /* SUB8rc */
    1492,
    /* SUB8ri */
    1495,
    /* SUB8rm */
    1498,
    /* SUB8rn */
    1502,
    /* SUB8rp */
    1505,
    /* SUB8rr */
    1509,
    /* SUBC16mc */
    1512,
    /* SUBC16mi */
    1515,
    /* SUBC16mm */
    1518,
    /* SUBC16mn */
    1522,
    /* SUBC16mp */
    1525,
    /* SUBC16mr */
    1528,
    /* SUBC16rc */
    1531,
    /* SUBC16ri */
    1534,
    /* SUBC16rm */
    1537,
    /* SUBC16rn */
    1541,
    /* SUBC16rp */
    1544,
    /* SUBC16rr */
    1548,
    /* SUBC8mc */
    1551,
    /* SUBC8mi */
    1554,
    /* SUBC8mm */
    1557,
    /* SUBC8mn */
    1561,
    /* SUBC8mp */
    1564,
    /* SUBC8mr */
    1567,
    /* SUBC8rc */
    1570,
    /* SUBC8ri */
    1573,
    /* SUBC8rm */
    1576,
    /* SUBC8rn */
    1580,
    /* SUBC8rp */
    1583,
    /* SUBC8rr */
    1587,
    /* SWPB16m */
    1590,
    /* SWPB16n */
    1592,
    /* SWPB16p */
    1593,
    /* SWPB16r */
    1594,
    /* Select16 */
    1596,
    /* Select8 */
    1600,
    /* Shl16 */
    1604,
    /* Shl8 */
    1607,
    /* Sra16 */
    1610,
    /* Sra8 */
    1613,
    /* Srl16 */
    1616,
    /* Srl8 */
    1619,
    /* XOR16mc */
    1622,
    /* XOR16mi */
    1625,
    /* XOR16mm */
    1628,
    /* XOR16mn */
    1632,
    /* XOR16mp */
    1635,
    /* XOR16mr */
    1638,
    /* XOR16rc */
    1641,
    /* XOR16ri */
    1644,
    /* XOR16rm */
    1647,
    /* XOR16rn */
    1651,
    /* XOR16rp */
    1654,
    /* XOR16rr */
    1658,
    /* XOR8mc */
    1661,
    /* XOR8mi */
    1664,
    /* XOR8mm */
    1667,
    /* XOR8mn */
    1671,
    /* XOR8mp */
    1674,
    /* XOR8mr */
    1677,
    /* XOR8rc */
    1680,
    /* XOR8ri */
    1683,
    /* XOR8rm */
    1686,
    /* XOR8rn */
    1690,
    /* XOR8rp */
    1693,
    /* XOR8rr */
    1697,
    /* ZEXT16r */
    1700,
  };

  using namespace OpTypes;
  static const int8_t OpcodeOperandTypes[] = {
    
    /* PHI */
    -1, 
    /* INLINEASM */
    /* INLINEASM_BR */
    /* CFI_INSTRUCTION */
    i32imm, 
    /* EH_LABEL */
    i32imm, 
    /* GC_LABEL */
    i32imm, 
    /* ANNOTATION_LABEL */
    i32imm, 
    /* KILL */
    /* EXTRACT_SUBREG */
    -1, -1, i32imm, 
    /* INSERT_SUBREG */
    -1, -1, -1, i32imm, 
    /* IMPLICIT_DEF */
    -1, 
    /* SUBREG_TO_REG */
    -1, -1, -1, i32imm, 
    /* COPY_TO_REGCLASS */
    -1, -1, i32imm, 
    /* DBG_VALUE */
    /* DBG_VALUE_LIST */
    /* DBG_INSTR_REF */
    /* DBG_PHI */
    /* DBG_LABEL */
    -1, 
    /* REG_SEQUENCE */
    -1, -1, 
    /* COPY */
    -1, -1, 
    /* BUNDLE */
    /* LIFETIME_START */
    i32imm, 
    /* LIFETIME_END */
    i32imm, 
    /* PSEUDO_PROBE */
    i64imm, i64imm, i8imm, i32imm, 
    /* ARITH_FENCE */
    -1, -1, 
    /* STACKMAP */
    i64imm, i32imm, 
    /* FENTRY_CALL */
    /* PATCHPOINT */
    -1, i64imm, i32imm, -1, i32imm, i32imm, 
    /* LOAD_STACK_GUARD */
    -1, 
    /* PREALLOCATED_SETUP */
    i32imm, 
    /* PREALLOCATED_ARG */
    -1, i32imm, i32imm, 
    /* STATEPOINT */
    /* LOCAL_ESCAPE */
    -1, i32imm, 
    /* FAULTING_OP */
    -1, 
    /* PATCHABLE_OP */
    /* PATCHABLE_FUNCTION_ENTER */
    /* PATCHABLE_RET */
    /* PATCHABLE_FUNCTION_EXIT */
    /* PATCHABLE_TAIL_CALL */
    /* PATCHABLE_EVENT_CALL */
    -1, -1, 
    /* PATCHABLE_TYPED_EVENT_CALL */
    -1, -1, -1, 
    /* ICALL_BRANCH_FUNNEL */
    /* FAKE_USE */
    /* MEMBARRIER */
    /* JUMP_TABLE_DEBUG_INFO */
    i64imm, 
    /* CONVERGENCECTRL_ENTRY */
    -1, 
    /* CONVERGENCECTRL_ANCHOR */
    -1, 
    /* CONVERGENCECTRL_LOOP */
    -1, -1, 
    /* CONVERGENCECTRL_GLUE */
    -1, 
    /* G_ASSERT_SEXT */
    type0, type0, untyped_imm_0, 
    /* G_ASSERT_ZEXT */
    type0, type0, untyped_imm_0, 
    /* G_ASSERT_ALIGN */
    type0, type0, untyped_imm_0, 
    /* G_ADD */
    type0, type0, type0, 
    /* G_SUB */
    type0, type0, type0, 
    /* G_MUL */
    type0, type0, type0, 
    /* G_SDIV */
    type0, type0, type0, 
    /* G_UDIV */
    type0, type0, type0, 
    /* G_SREM */
    type0, type0, type0, 
    /* G_UREM */
    type0, type0, type0, 
    /* G_SDIVREM */
    type0, type0, type0, type0, 
    /* G_UDIVREM */
    type0, type0, type0, type0, 
    /* G_AND */
    type0, type0, type0, 
    /* G_OR */
    type0, type0, type0, 
    /* G_XOR */
    type0, type0, type0, 
    /* G_IMPLICIT_DEF */
    type0, 
    /* G_PHI */
    type0, 
    /* G_FRAME_INDEX */
    type0, -1, 
    /* G_GLOBAL_VALUE */
    type0, -1, 
    /* G_PTRAUTH_GLOBAL_VALUE */
    type0, -1, i32imm, type1, i64imm, 
    /* G_CONSTANT_POOL */
    type0, -1, 
    /* G_EXTRACT */
    type0, type1, untyped_imm_0, 
    /* G_UNMERGE_VALUES */
    type0, type1, 
    /* G_INSERT */
    type0, type0, type1, untyped_imm_0, 
    /* G_MERGE_VALUES */
    type0, type1, 
    /* G_BUILD_VECTOR */
    type0, type1, 
    /* G_BUILD_VECTOR_TRUNC */
    type0, type1, 
    /* G_CONCAT_VECTORS */
    type0, type1, 
    /* G_PTRTOINT */
    type0, type1, 
    /* G_INTTOPTR */
    type0, type1, 
    /* G_BITCAST */
    type0, type1, 
    /* G_FREEZE */
    type0, type0, 
    /* G_CONSTANT_FOLD_BARRIER */
    type0, type0, 
    /* G_INTRINSIC_FPTRUNC_ROUND */
    type0, type1, i32imm, 
    /* G_INTRINSIC_TRUNC */
    type0, type0, 
    /* G_INTRINSIC_ROUND */
    type0, type0, 
    /* G_INTRINSIC_LRINT */
    type0, type1, 
    /* G_INTRINSIC_LLRINT */
    type0, type1, 
    /* G_INTRINSIC_ROUNDEVEN */
    type0, type0, 
    /* G_READCYCLECOUNTER */
    type0, 
    /* G_READSTEADYCOUNTER */
    type0, 
    /* G_LOAD */
    type0, ptype1, 
    /* G_SEXTLOAD */
    type0, ptype1, 
    /* G_ZEXTLOAD */
    type0, ptype1, 
    /* G_INDEXED_LOAD */
    type0, ptype1, ptype1, type2, -1, 
    /* G_INDEXED_SEXTLOAD */
    type0, ptype1, ptype1, type2, -1, 
    /* G_INDEXED_ZEXTLOAD */
    type0, ptype1, ptype1, type2, -1, 
    /* G_STORE */
    type0, ptype1, 
    /* G_INDEXED_STORE */
    ptype0, type1, ptype0, ptype2, -1, 
    /* G_ATOMIC_CMPXCHG_WITH_SUCCESS */
    type0, type1, type2, type0, type0, 
    /* G_ATOMIC_CMPXCHG */
    type0, ptype1, type0, type0, 
    /* G_ATOMICRMW_XCHG */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_ADD */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_SUB */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_AND */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_NAND */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_OR */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_XOR */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_MAX */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_MIN */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_UMAX */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_UMIN */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_FADD */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_FSUB */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_FMAX */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_FMIN */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_UINC_WRAP */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_UDEC_WRAP */
    type0, ptype1, type0, 
    /* G_FENCE */
    i32imm, i32imm, 
    /* G_PREFETCH */
    ptype0, i32imm, i32imm, i32imm, 
    /* G_BRCOND */
    type0, -1, 
    /* G_BRINDIRECT */
    type0, 
    /* G_INVOKE_REGION_START */
    /* G_INTRINSIC */
    -1, 
    /* G_INTRINSIC_W_SIDE_EFFECTS */
    -1, 
    /* G_INTRINSIC_CONVERGENT */
    -1, 
    /* G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS */
    -1, 
    /* G_ANYEXT */
    type0, type1, 
    /* G_TRUNC */
    type0, type1, 
    /* G_CONSTANT */
    type0, -1, 
    /* G_FCONSTANT */
    type0, -1, 
    /* G_VASTART */
    type0, 
    /* G_VAARG */
    type0, type1, -1, 
    /* G_SEXT */
    type0, type1, 
    /* G_SEXT_INREG */
    type0, type0, untyped_imm_0, 
    /* G_ZEXT */
    type0, type1, 
    /* G_SHL */
    type0, type0, type1, 
    /* G_LSHR */
    type0, type0, type1, 
    /* G_ASHR */
    type0, type0, type1, 
    /* G_FSHL */
    type0, type0, type0, type1, 
    /* G_FSHR */
    type0, type0, type0, type1, 
    /* G_ROTR */
    type0, type0, type1, 
    /* G_ROTL */
    type0, type0, type1, 
    /* G_ICMP */
    type0, -1, type1, type1, 
    /* G_FCMP */
    type0, -1, type1, type1, 
    /* G_SCMP */
    type0, type1, type1, 
    /* G_UCMP */
    type0, type1, type1, 
    /* G_SELECT */
    type0, type1, type0, type0, 
    /* G_UADDO */
    type0, type1, type0, type0, 
    /* G_UADDE */
    type0, type1, type0, type0, type1, 
    /* G_USUBO */
    type0, type1, type0, type0, 
    /* G_USUBE */
    type0, type1, type0, type0, type1, 
    /* G_SADDO */
    type0, type1, type0, type0, 
    /* G_SADDE */
    type0, type1, type0, type0, type1, 
    /* G_SSUBO */
    type0, type1, type0, type0, 
    /* G_SSUBE */
    type0, type1, type0, type0, type1, 
    /* G_UMULO */
    type0, type1, type0, type0, 
    /* G_SMULO */
    type0, type1, type0, type0, 
    /* G_UMULH */
    type0, type0, type0, 
    /* G_SMULH */
    type0, type0, type0, 
    /* G_UADDSAT */
    type0, type0, type0, 
    /* G_SADDSAT */
    type0, type0, type0, 
    /* G_USUBSAT */
    type0, type0, type0, 
    /* G_SSUBSAT */
    type0, type0, type0, 
    /* G_USHLSAT */
    type0, type0, type1, 
    /* G_SSHLSAT */
    type0, type0, type1, 
    /* G_SMULFIX */
    type0, type0, type0, untyped_imm_0, 
    /* G_UMULFIX */
    type0, type0, type0, untyped_imm_0, 
    /* G_SMULFIXSAT */
    type0, type0, type0, untyped_imm_0, 
    /* G_UMULFIXSAT */
    type0, type0, type0, untyped_imm_0, 
    /* G_SDIVFIX */
    type0, type0, type0, untyped_imm_0, 
    /* G_UDIVFIX */
    type0, type0, type0, untyped_imm_0, 
    /* G_SDIVFIXSAT */
    type0, type0, type0, untyped_imm_0, 
    /* G_UDIVFIXSAT */
    type0, type0, type0, untyped_imm_0, 
    /* G_FADD */
    type0, type0, type0, 
    /* G_FSUB */
    type0, type0, type0, 
    /* G_FMUL */
    type0, type0, type0, 
    /* G_FMA */
    type0, type0, type0, type0, 
    /* G_FMAD */
    type0, type0, type0, type0, 
    /* G_FDIV */
    type0, type0, type0, 
    /* G_FREM */
    type0, type0, type0, 
    /* G_FPOW */
    type0, type0, type0, 
    /* G_FPOWI */
    type0, type0, type1, 
    /* G_FEXP */
    type0, type0, 
    /* G_FEXP2 */
    type0, type0, 
    /* G_FEXP10 */
    type0, type0, 
    /* G_FLOG */
    type0, type0, 
    /* G_FLOG2 */
    type0, type0, 
    /* G_FLOG10 */
    type0, type0, 
    /* G_FLDEXP */
    type0, type0, type1, 
    /* G_FFREXP */
    type0, type1, type0, 
    /* G_FNEG */
    type0, type0, 
    /* G_FPEXT */
    type0, type1, 
    /* G_FPTRUNC */
    type0, type1, 
    /* G_FPTOSI */
    type0, type1, 
    /* G_FPTOUI */
    type0, type1, 
    /* G_SITOFP */
    type0, type1, 
    /* G_UITOFP */
    type0, type1, 
    /* G_FABS */
    type0, type0, 
    /* G_FCOPYSIGN */
    type0, type0, type1, 
    /* G_IS_FPCLASS */
    type0, type1, -1, 
    /* G_FCANONICALIZE */
    type0, type0, 
    /* G_FMINNUM */
    type0, type0, type0, 
    /* G_FMAXNUM */
    type0, type0, type0, 
    /* G_FMINNUM_IEEE */
    type0, type0, type0, 
    /* G_FMAXNUM_IEEE */
    type0, type0, type0, 
    /* G_FMINIMUM */
    type0, type0, type0, 
    /* G_FMAXIMUM */
    type0, type0, type0, 
    /* G_GET_FPENV */
    type0, 
    /* G_SET_FPENV */
    type0, 
    /* G_RESET_FPENV */
    /* G_GET_FPMODE */
    type0, 
    /* G_SET_FPMODE */
    type0, 
    /* G_RESET_FPMODE */
    /* G_PTR_ADD */
    ptype0, ptype0, type1, 
    /* G_PTRMASK */
    ptype0, ptype0, type1, 
    /* G_SMIN */
    type0, type0, type0, 
    /* G_SMAX */
    type0, type0, type0, 
    /* G_UMIN */
    type0, type0, type0, 
    /* G_UMAX */
    type0, type0, type0, 
    /* G_ABS */
    type0, type0, 
    /* G_LROUND */
    type0, type1, 
    /* G_LLROUND */
    type0, type1, 
    /* G_BR */
    -1, 
    /* G_BRJT */
    ptype0, -1, type1, 
    /* G_VSCALE */
    type0, -1, 
    /* G_INSERT_SUBVECTOR */
    type0, type0, type1, untyped_imm_0, 
    /* G_EXTRACT_SUBVECTOR */
    type0, type0, untyped_imm_0, 
    /* G_INSERT_VECTOR_ELT */
    type0, type0, type1, type2, 
    /* G_EXTRACT_VECTOR_ELT */
    type0, type1, type2, 
    /* G_SHUFFLE_VECTOR */
    type0, type1, type1, -1, 
    /* G_SPLAT_VECTOR */
    type0, type1, 
    /* G_VECTOR_COMPRESS */
    type0, type0, type1, type0, 
    /* G_CTTZ */
    type0, type1, 
    /* G_CTTZ_ZERO_UNDEF */
    type0, type1, 
    /* G_CTLZ */
    type0, type1, 
    /* G_CTLZ_ZERO_UNDEF */
    type0, type1, 
    /* G_CTPOP */
    type0, type1, 
    /* G_BSWAP */
    type0, type0, 
    /* G_BITREVERSE */
    type0, type0, 
    /* G_FCEIL */
    type0, type0, 
    /* G_FCOS */
    type0, type0, 
    /* G_FSIN */
    type0, type0, 
    /* G_FTAN */
    type0, type0, 
    /* G_FACOS */
    type0, type0, 
    /* G_FASIN */
    type0, type0, 
    /* G_FATAN */
    type0, type0, 
    /* G_FCOSH */
    type0, type0, 
    /* G_FSINH */
    type0, type0, 
    /* G_FTANH */
    type0, type0, 
    /* G_FSQRT */
    type0, type0, 
    /* G_FFLOOR */
    type0, type0, 
    /* G_FRINT */
    type0, type0, 
    /* G_FNEARBYINT */
    type0, type0, 
    /* G_ADDRSPACE_CAST */
    type0, type1, 
    /* G_BLOCK_ADDR */
    type0, -1, 
    /* G_JUMP_TABLE */
    type0, -1, 
    /* G_DYN_STACKALLOC */
    ptype0, type1, i32imm, 
    /* G_STACKSAVE */
    ptype0, 
    /* G_STACKRESTORE */
    ptype0, 
    /* G_STRICT_FADD */
    type0, type0, type0, 
    /* G_STRICT_FSUB */
    type0, type0, type0, 
    /* G_STRICT_FMUL */
    type0, type0, type0, 
    /* G_STRICT_FDIV */
    type0, type0, type0, 
    /* G_STRICT_FREM */
    type0, type0, type0, 
    /* G_STRICT_FMA */
    type0, type0, type0, type0, 
    /* G_STRICT_FSQRT */
    type0, type0, 
    /* G_STRICT_FLDEXP */
    type0, type0, type1, 
    /* G_READ_REGISTER */
    type0, -1, 
    /* G_WRITE_REGISTER */
    -1, type0, 
    /* G_MEMCPY */
    ptype0, ptype1, type2, untyped_imm_0, 
    /* G_MEMCPY_INLINE */
    ptype0, ptype1, type2, 
    /* G_MEMMOVE */
    ptype0, ptype1, type2, untyped_imm_0, 
    /* G_MEMSET */
    ptype0, type1, type2, untyped_imm_0, 
    /* G_BZERO */
    ptype0, type1, untyped_imm_0, 
    /* G_TRAP */
    /* G_DEBUGTRAP */
    /* G_UBSANTRAP */
    i8imm, 
    /* G_VECREDUCE_SEQ_FADD */
    type0, type1, type2, 
    /* G_VECREDUCE_SEQ_FMUL */
    type0, type1, type2, 
    /* G_VECREDUCE_FADD */
    type0, type1, 
    /* G_VECREDUCE_FMUL */
    type0, type1, 
    /* G_VECREDUCE_FMAX */
    type0, type1, 
    /* G_VECREDUCE_FMIN */
    type0, type1, 
    /* G_VECREDUCE_FMAXIMUM */
    type0, type1, 
    /* G_VECREDUCE_FMINIMUM */
    type0, type1, 
    /* G_VECREDUCE_ADD */
    type0, type1, 
    /* G_VECREDUCE_MUL */
    type0, type1, 
    /* G_VECREDUCE_AND */
    type0, type1, 
    /* G_VECREDUCE_OR */
    type0, type1, 
    /* G_VECREDUCE_XOR */
    type0, type1, 
    /* G_VECREDUCE_SMAX */
    type0, type1, 
    /* G_VECREDUCE_SMIN */
    type0, type1, 
    /* G_VECREDUCE_UMAX */
    type0, type1, 
    /* G_VECREDUCE_UMIN */
    type0, type1, 
    /* G_SBFX */
    type0, type0, type1, type1, 
    /* G_UBFX */
    type0, type0, type1, type1, 
    /* ADD16mc */
    GR16, i16imm, cg16imm, 
    /* ADD16mi */
    GR16, i16imm, i16imm, 
    /* ADD16mm */
    GR16, i16imm, GR16, i16imm, 
    /* ADD16mn */
    GR16, i16imm, GR16, 
    /* ADD16mp */
    GR16, i16imm, GR16, 
    /* ADD16mr */
    GR16, i16imm, GR16, 
    /* ADD16rc */
    GR16, GR16, cg16imm, 
    /* ADD16ri */
    GR16, GR16, i16imm, 
    /* ADD16rm */
    GR16, GR16, GR16, i16imm, 
    /* ADD16rn */
    GR16, GR16, GR16, 
    /* ADD16rp */
    GR16, GR16, GR16, GR16, 
    /* ADD16rr */
    GR16, GR16, GR16, 
    /* ADD8mc */
    GR16, i16imm, cg8imm, 
    /* ADD8mi */
    GR16, i16imm, i8imm, 
    /* ADD8mm */
    GR16, i16imm, GR16, i16imm, 
    /* ADD8mn */
    GR16, i16imm, GR16, 
    /* ADD8mp */
    GR16, i16imm, GR16, 
    /* ADD8mr */
    GR16, i16imm, GR8, 
    /* ADD8rc */
    GR8, GR8, cg8imm, 
    /* ADD8ri */
    GR8, GR8, i8imm, 
    /* ADD8rm */
    GR8, GR8, GR16, i16imm, 
    /* ADD8rn */
    GR8, GR8, GR16, 
    /* ADD8rp */
    GR8, GR16, GR8, GR16, 
    /* ADD8rr */
    GR8, GR8, GR8, 
    /* ADDC16mc */
    GR16, i16imm, cg16imm, 
    /* ADDC16mi */
    GR16, i16imm, i16imm, 
    /* ADDC16mm */
    GR16, i16imm, GR16, i16imm, 
    /* ADDC16mn */
    GR16, i16imm, GR16, 
    /* ADDC16mp */
    GR16, i16imm, GR16, 
    /* ADDC16mr */
    GR16, i16imm, GR16, 
    /* ADDC16rc */
    GR16, GR16, cg16imm, 
    /* ADDC16ri */
    GR16, GR16, i16imm, 
    /* ADDC16rm */
    GR16, GR16, GR16, i16imm, 
    /* ADDC16rn */
    GR16, GR16, GR16, 
    /* ADDC16rp */
    GR16, GR16, GR16, GR16, 
    /* ADDC16rr */
    GR16, GR16, GR16, 
    /* ADDC8mc */
    GR16, i16imm, cg8imm, 
    /* ADDC8mi */
    GR16, i16imm, i8imm, 
    /* ADDC8mm */
    GR16, i16imm, GR16, i16imm, 
    /* ADDC8mn */
    GR16, i16imm, GR16, 
    /* ADDC8mp */
    GR16, i16imm, GR16, 
    /* ADDC8mr */
    GR16, i16imm, GR8, 
    /* ADDC8rc */
    GR8, GR8, cg8imm, 
    /* ADDC8ri */
    GR8, GR8, i8imm, 
    /* ADDC8rm */
    GR8, GR8, GR16, i16imm, 
    /* ADDC8rn */
    GR8, GR8, GR16, 
    /* ADDC8rp */
    GR8, GR16, GR8, GR16, 
    /* ADDC8rr */
    GR8, GR8, GR8, 
    /* ADDframe */
    GR16, i16imm, i16imm, 
    /* ADJCALLSTACKDOWN */
    i16imm, i16imm, 
    /* ADJCALLSTACKUP */
    i16imm, i16imm, 
    /* AND16mc */
    GR16, i16imm, cg16imm, 
    /* AND16mi */
    GR16, i16imm, i16imm, 
    /* AND16mm */
    GR16, i16imm, GR16, i16imm, 
    /* AND16mn */
    GR16, i16imm, GR16, 
    /* AND16mp */
    GR16, i16imm, GR16, 
    /* AND16mr */
    GR16, i16imm, GR16, 
    /* AND16rc */
    GR16, GR16, cg16imm, 
    /* AND16ri */
    GR16, GR16, i16imm, 
    /* AND16rm */
    GR16, GR16, GR16, i16imm, 
    /* AND16rn */
    GR16, GR16, GR16, 
    /* AND16rp */
    GR16, GR16, GR16, GR16, 
    /* AND16rr */
    GR16, GR16, GR16, 
    /* AND8mc */
    GR16, i16imm, cg8imm, 
    /* AND8mi */
    GR16, i16imm, i8imm, 
    /* AND8mm */
    GR16, i16imm, GR16, i16imm, 
    /* AND8mn */
    GR16, i16imm, GR16, 
    /* AND8mp */
    GR16, i16imm, GR16, 
    /* AND8mr */
    GR16, i16imm, GR8, 
    /* AND8rc */
    GR8, GR8, cg8imm, 
    /* AND8ri */
    GR8, GR8, i8imm, 
    /* AND8rm */
    GR8, GR8, GR16, i16imm, 
    /* AND8rn */
    GR8, GR8, GR16, 
    /* AND8rp */
    GR8, GR16, GR8, GR16, 
    /* AND8rr */
    GR8, GR8, GR8, 
    /* BIC16mc */
    GR16, i16imm, cg16imm, 
    /* BIC16mi */
    GR16, i16imm, i16imm, 
    /* BIC16mm */
    GR16, i16imm, GR16, i16imm, 
    /* BIC16mn */
    GR16, i16imm, GR16, 
    /* BIC16mp */
    GR16, i16imm, GR16, 
    /* BIC16mr */
    GR16, i16imm, GR16, 
    /* BIC16rc */
    GR16, GR16, cg16imm, 
    /* BIC16ri */
    GR16, GR16, i16imm, 
    /* BIC16rm */
    GR16, GR16, GR16, i16imm, 
    /* BIC16rn */
    GR16, GR16, GR16, 
    /* BIC16rp */
    GR16, GR16, GR16, GR16, 
    /* BIC16rr */
    GR16, GR16, GR16, 
    /* BIC8mc */
    GR16, i16imm, cg8imm, 
    /* BIC8mi */
    GR16, i16imm, i8imm, 
    /* BIC8mm */
    GR16, i16imm, GR16, i16imm, 
    /* BIC8mn */
    GR16, i16imm, GR16, 
    /* BIC8mp */
    GR16, i16imm, GR16, 
    /* BIC8mr */
    GR16, i16imm, GR8, 
    /* BIC8rc */
    GR8, GR8, cg8imm, 
    /* BIC8ri */
    GR8, GR8, i8imm, 
    /* BIC8rm */
    GR8, GR8, GR16, i16imm, 
    /* BIC8rn */
    GR8, GR8, GR16, 
    /* BIC8rp */
    GR8, GR16, GR8, GR16, 
    /* BIC8rr */
    GR8, GR8, GR8, 
    /* BIS16mc */
    GR16, i16imm, cg16imm, 
    /* BIS16mi */
    GR16, i16imm, i16imm, 
    /* BIS16mm */
    GR16, i16imm, GR16, i16imm, 
    /* BIS16mn */
    GR16, i16imm, GR16, 
    /* BIS16mp */
    GR16, i16imm, GR16, 
    /* BIS16mr */
    GR16, i16imm, GR16, 
    /* BIS16rc */
    GR16, GR16, cg16imm, 
    /* BIS16ri */
    GR16, GR16, i16imm, 
    /* BIS16rm */
    GR16, GR16, GR16, i16imm, 
    /* BIS16rn */
    GR16, GR16, GR16, 
    /* BIS16rp */
    GR16, GR16, GR16, GR16, 
    /* BIS16rr */
    GR16, GR16, GR16, 
    /* BIS8mc */
    GR16, i16imm, cg8imm, 
    /* BIS8mi */
    GR16, i16imm, i8imm, 
    /* BIS8mm */
    GR16, i16imm, GR16, i16imm, 
    /* BIS8mn */
    GR16, i16imm, GR16, 
    /* BIS8mp */
    GR16, i16imm, GR16, 
    /* BIS8mr */
    GR16, i16imm, GR8, 
    /* BIS8rc */
    GR8, GR8, cg8imm, 
    /* BIS8ri */
    GR8, GR8, i8imm, 
    /* BIS8rm */
    GR8, GR8, GR16, i16imm, 
    /* BIS8rn */
    GR8, GR8, GR16, 
    /* BIS8rp */
    GR8, GR16, GR8, GR16, 
    /* BIS8rr */
    GR8, GR8, GR8, 
    /* BIT16mc */
    GR16, i16imm, cg16imm, 
    /* BIT16mi */
    GR16, i16imm, i16imm, 
    /* BIT16mm */
    GR16, i16imm, GR16, i16imm, 
    /* BIT16mn */
    GR16, i16imm, GR16, 
    /* BIT16mp */
    GR16, i16imm, GR16, 
    /* BIT16mr */
    GR16, i16imm, GR16, 
    /* BIT16rc */
    GR16, cg16imm, 
    /* BIT16ri */
    GR16, i16imm, 
    /* BIT16rm */
    GR16, GR16, i16imm, 
    /* BIT16rn */
    GR16, GR16, 
    /* BIT16rp */
    GR16, GR16, 
    /* BIT16rr */
    GR16, GR16, 
    /* BIT8mc */
    GR16, i16imm, cg8imm, 
    /* BIT8mi */
    GR16, i16imm, i8imm, 
    /* BIT8mm */
    GR16, i16imm, GR16, i16imm, 
    /* BIT8mn */
    GR16, i16imm, GR16, 
    /* BIT8mp */
    GR16, i16imm, GR16, 
    /* BIT8mr */
    GR16, i16imm, GR8, 
    /* BIT8rc */
    GR8, cg8imm, 
    /* BIT8ri */
    GR8, i8imm, 
    /* BIT8rm */
    GR8, GR16, i16imm, 
    /* BIT8rn */
    GR8, GR16, 
    /* BIT8rp */
    GR8, GR16, 
    /* BIT8rr */
    GR8, GR8, 
    /* Bi */
    i16imm, 
    /* Bm */
    GR16, i16imm, 
    /* Br */
    GR16, 
    /* CALLi */
    i16imm, 
    /* CALLm */
    GR16, i16imm, 
    /* CALLn */
    GR16, 
    /* CALLp */
    GR16, 
    /* CALLr */
    GR16, 
    /* CMP16mc */
    GR16, i16imm, cg16imm, 
    /* CMP16mi */
    GR16, i16imm, i16imm, 
    /* CMP16mm */
    GR16, i16imm, GR16, i16imm, 
    /* CMP16mn */
    GR16, i16imm, GR16, 
    /* CMP16mp */
    GR16, i16imm, GR16, 
    /* CMP16mr */
    GR16, i16imm, GR16, 
    /* CMP16rc */
    GR16, cg16imm, 
    /* CMP16ri */
    GR16, i16imm, 
    /* CMP16rm */
    GR16, GR16, i16imm, 
    /* CMP16rn */
    GR16, GR16, 
    /* CMP16rp */
    GR16, GR16, 
    /* CMP16rr */
    GR16, GR16, 
    /* CMP8mc */
    GR16, i16imm, cg8imm, 
    /* CMP8mi */
    GR16, i16imm, i8imm, 
    /* CMP8mm */
    GR16, i16imm, GR16, i16imm, 
    /* CMP8mn */
    GR16, i16imm, GR16, 
    /* CMP8mp */
    GR16, i16imm, GR16, 
    /* CMP8mr */
    GR16, i16imm, GR8, 
    /* CMP8rc */
    GR8, cg8imm, 
    /* CMP8ri */
    GR8, i8imm, 
    /* CMP8rm */
    GR8, GR16, i16imm, 
    /* CMP8rn */
    GR8, GR16, 
    /* CMP8rp */
    GR8, GR16, 
    /* CMP8rr */
    GR8, GR8, 
    /* DADD16mc */
    GR16, i16imm, cg16imm, 
    /* DADD16mi */
    GR16, i16imm, i16imm, 
    /* DADD16mm */
    GR16, i16imm, GR16, i16imm, 
    /* DADD16mn */
    GR16, i16imm, GR16, 
    /* DADD16mp */
    GR16, i16imm, GR16, 
    /* DADD16mr */
    GR16, i16imm, GR16, 
    /* DADD16rc */
    GR16, GR16, cg16imm, 
    /* DADD16ri */
    GR16, GR16, i16imm, 
    /* DADD16rm */
    GR16, GR16, GR16, i16imm, 
    /* DADD16rn */
    GR16, GR16, GR16, 
    /* DADD16rp */
    GR16, GR16, GR16, GR16, 
    /* DADD16rr */
    GR16, GR16, GR16, 
    /* DADD8mc */
    GR16, i16imm, cg8imm, 
    /* DADD8mi */
    GR16, i16imm, i8imm, 
    /* DADD8mm */
    GR16, i16imm, GR16, i16imm, 
    /* DADD8mn */
    GR16, i16imm, GR16, 
    /* DADD8mp */
    GR16, i16imm, GR16, 
    /* DADD8mr */
    GR16, i16imm, GR8, 
    /* DADD8rc */
    GR8, GR8, cg8imm, 
    /* DADD8ri */
    GR8, GR8, i8imm, 
    /* DADD8rm */
    GR8, GR8, GR16, i16imm, 
    /* DADD8rn */
    GR8, GR8, GR16, 
    /* DADD8rp */
    GR8, GR16, GR8, GR16, 
    /* DADD8rr */
    GR8, GR8, GR8, 
    /* JCC */
    jmptarget, cc, 
    /* JMP */
    jmptarget, 
    /* MOV16mc */
    GR16, i16imm, cg16imm, 
    /* MOV16mi */
    GR16, i16imm, i16imm, 
    /* MOV16mm */
    GR16, i16imm, GR16, i16imm, 
    /* MOV16mn */
    GR16, i16imm, GR16, 
    /* MOV16mr */
    GR16, i16imm, GR16, 
    /* MOV16rc */
    GR16, cg16imm, 
    /* MOV16ri */
    GR16, i16imm, 
    /* MOV16rm */
    GR16, GR16, i16imm, 
    /* MOV16rn */
    GR16, GR16, 
    /* MOV16rp */
    GR16, GR16, GR16, 
    /* MOV16rr */
    GR16, GR16, 
    /* MOV8mc */
    GR16, i16imm, cg8imm, 
    /* MOV8mi */
    GR16, i16imm, i8imm, 
    /* MOV8mm */
    GR16, i16imm, GR16, i16imm, 
    /* MOV8mn */
    GR16, i16imm, GR16, 
    /* MOV8mr */
    GR16, i16imm, GR8, 
    /* MOV8rc */
    GR8, cg8imm, 
    /* MOV8ri */
    GR8, i8imm, 
    /* MOV8rm */
    GR8, GR16, i16imm, 
    /* MOV8rn */
    GR8, GR16, 
    /* MOV8rp */
    GR8, GR16, GR16, 
    /* MOV8rr */
    GR8, GR8, 
    /* MOVZX16rm8 */
    GR16, GR16, i16imm, 
    /* MOVZX16rr8 */
    GR16, GR8, 
    /* POP16r */
    GR16, 
    /* PUSH16c */
    cg16imm, 
    /* PUSH16i */
    i16imm, 
    /* PUSH16r */
    GR16, 
    /* PUSH8r */
    GR8, 
    /* RET */
    /* RETI */
    /* RRA16m */
    GR16, i16imm, 
    /* RRA16n */
    GR16, 
    /* RRA16p */
    GR16, 
    /* RRA16r */
    GR16, GR16, 
    /* RRA8m */
    GR16, i16imm, 
    /* RRA8n */
    GR16, 
    /* RRA8p */
    GR16, 
    /* RRA8r */
    GR8, GR8, 
    /* RRC16m */
    GR16, i16imm, 
    /* RRC16n */
    GR16, 
    /* RRC16p */
    GR16, 
    /* RRC16r */
    GR16, GR16, 
    /* RRC8m */
    GR16, i16imm, 
    /* RRC8n */
    GR16, 
    /* RRC8p */
    GR16, 
    /* RRC8r */
    GR8, GR8, 
    /* Rrcl16 */
    GR16, GR16, 
    /* Rrcl8 */
    GR8, GR8, 
    /* SEXT16m */
    GR16, i16imm, 
    /* SEXT16n */
    GR16, 
    /* SEXT16p */
    GR16, 
    /* SEXT16r */
    GR16, GR16, 
    /* SUB16mc */
    GR16, i16imm, cg16imm, 
    /* SUB16mi */
    GR16, i16imm, i16imm, 
    /* SUB16mm */
    GR16, i16imm, GR16, i16imm, 
    /* SUB16mn */
    GR16, i16imm, GR16, 
    /* SUB16mp */
    GR16, i16imm, GR16, 
    /* SUB16mr */
    GR16, i16imm, GR16, 
    /* SUB16rc */
    GR16, GR16, cg16imm, 
    /* SUB16ri */
    GR16, GR16, i16imm, 
    /* SUB16rm */
    GR16, GR16, GR16, i16imm, 
    /* SUB16rn */
    GR16, GR16, GR16, 
    /* SUB16rp */
    GR16, GR16, GR16, GR16, 
    /* SUB16rr */
    GR16, GR16, GR16, 
    /* SUB8mc */
    GR16, i16imm, cg8imm, 
    /* SUB8mi */
    GR16, i16imm, i8imm, 
    /* SUB8mm */
    GR16, i16imm, GR16, i16imm, 
    /* SUB8mn */
    GR16, i16imm, GR16, 
    /* SUB8mp */
    GR16, i16imm, GR16, 
    /* SUB8mr */
    GR16, i16imm, GR8, 
    /* SUB8rc */
    GR8, GR8, cg8imm, 
    /* SUB8ri */
    GR8, GR8, i8imm, 
    /* SUB8rm */
    GR8, GR8, GR16, i16imm, 
    /* SUB8rn */
    GR8, GR8, GR16, 
    /* SUB8rp */
    GR8, GR16, GR8, GR16, 
    /* SUB8rr */
    GR8, GR8, GR8, 
    /* SUBC16mc */
    GR16, i16imm, cg16imm, 
    /* SUBC16mi */
    GR16, i16imm, i16imm, 
    /* SUBC16mm */
    GR16, i16imm, GR16, i16imm, 
    /* SUBC16mn */
    GR16, i16imm, GR16, 
    /* SUBC16mp */
    GR16, i16imm, GR16, 
    /* SUBC16mr */
    GR16, i16imm, GR16, 
    /* SUBC16rc */
    GR16, GR16, cg16imm, 
    /* SUBC16ri */
    GR16, GR16, i16imm, 
    /* SUBC16rm */
    GR16, GR16, GR16, i16imm, 
    /* SUBC16rn */
    GR16, GR16, GR16, 
    /* SUBC16rp */
    GR16, GR16, GR16, GR16, 
    /* SUBC16rr */
    GR16, GR16, GR16, 
    /* SUBC8mc */
    GR16, i16imm, cg8imm, 
    /* SUBC8mi */
    GR16, i16imm, i8imm, 
    /* SUBC8mm */
    GR16, i16imm, GR16, i16imm, 
    /* SUBC8mn */
    GR16, i16imm, GR16, 
    /* SUBC8mp */
    GR16, i16imm, GR16, 
    /* SUBC8mr */
    GR16, i16imm, GR8, 
    /* SUBC8rc */
    GR8, GR8, cg8imm, 
    /* SUBC8ri */
    GR8, GR8, i8imm, 
    /* SUBC8rm */
    GR8, GR8, GR16, i16imm, 
    /* SUBC8rn */
    GR8, GR8, GR16, 
    /* SUBC8rp */
    GR8, GR16, GR8, GR16, 
    /* SUBC8rr */
    GR8, GR8, GR8, 
    /* SWPB16m */
    GR16, i16imm, 
    /* SWPB16n */
    GR16, 
    /* SWPB16p */
    GR16, 
    /* SWPB16r */
    GR16, GR16, 
    /* Select16 */
    GR16, GR16, GR16, i8imm, 
    /* Select8 */
    GR8, GR8, GR8, i8imm, 
    /* Shl16 */
    GR16, GR16, GR8, 
    /* Shl8 */
    GR8, GR8, GR8, 
    /* Sra16 */
    GR16, GR16, GR8, 
    /* Sra8 */
    GR8, GR8, GR8, 
    /* Srl16 */
    GR16, GR16, GR8, 
    /* Srl8 */
    GR8, GR8, GR8, 
    /* XOR16mc */
    GR16, i16imm, cg16imm, 
    /* XOR16mi */
    GR16, i16imm, i16imm, 
    /* XOR16mm */
    GR16, i16imm, GR16, i16imm, 
    /* XOR16mn */
    GR16, i16imm, GR16, 
    /* XOR16mp */
    GR16, i16imm, GR16, 
    /* XOR16mr */
    GR16, i16imm, GR16, 
    /* XOR16rc */
    GR16, GR16, cg16imm, 
    /* XOR16ri */
    GR16, GR16, i16imm, 
    /* XOR16rm */
    GR16, GR16, GR16, i16imm, 
    /* XOR16rn */
    GR16, GR16, GR16, 
    /* XOR16rp */
    GR16, GR16, GR16, GR16, 
    /* XOR16rr */
    GR16, GR16, GR16, 
    /* XOR8mc */
    GR16, i16imm, cg8imm, 
    /* XOR8mi */
    GR16, i16imm, i8imm, 
    /* XOR8mm */
    GR16, i16imm, GR16, i16imm, 
    /* XOR8mn */
    GR16, i16imm, GR16, 
    /* XOR8mp */
    GR16, i16imm, GR16, 
    /* XOR8mr */
    GR16, i16imm, GR8, 
    /* XOR8rc */
    GR8, GR8, cg8imm, 
    /* XOR8ri */
    GR8, GR8, i8imm, 
    /* XOR8rm */
    GR8, GR8, GR16, i16imm, 
    /* XOR8rn */
    GR8, GR8, GR16, 
    /* XOR8rp */
    GR8, GR16, GR8, GR16, 
    /* XOR8rr */
    GR8, GR8, GR8, 
    /* ZEXT16r */
    GR16, GR16, 
  };
  return OpcodeOperandTypes[Offsets[Opcode] + OpIdx];
}
} // end namespace MSP430
} // end namespace llvm
#endif // GET_INSTRINFO_OPERAND_TYPE

#ifdef GET_INSTRINFO_MEM_OPERAND_SIZE
#undef GET_INSTRINFO_MEM_OPERAND_SIZE
namespace llvm {
namespace MSP430 {
LLVM_READONLY
static int getMemOperandSize(int OpType) {
  switch (OpType) {
  default: return 0;
  }
}
} // end namespace MSP430
} // end namespace llvm
#endif // GET_INSTRINFO_MEM_OPERAND_SIZE

#ifdef GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP
#undef GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP
namespace llvm {
namespace MSP430 {
LLVM_READONLY static unsigned
getLogicalOperandSize(uint16_t Opcode, uint16_t LogicalOpIdx) {
  return LogicalOpIdx;
}
LLVM_READONLY static inline unsigned
getLogicalOperandIdx(uint16_t Opcode, uint16_t LogicalOpIdx) {
  auto S = 0U;
  for (auto i = 0U; i < LogicalOpIdx; ++i)
    S += getLogicalOperandSize(Opcode, i);
  return S;
}
} // end namespace MSP430
} // end namespace llvm
#endif // GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP

#ifdef GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP
#undef GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP
namespace llvm {
namespace MSP430 {
LLVM_READONLY static int
getLogicalOperandType(uint16_t Opcode, uint16_t LogicalOpIdx) {
  return -1;
}
} // end namespace MSP430
} // end namespace llvm
#endif // GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP

#ifdef GET_INSTRINFO_MC_HELPER_DECLS
#undef GET_INSTRINFO_MC_HELPER_DECLS

namespace llvm {
class MCInst;
class FeatureBitset;

namespace MSP430_MC {

void verifyInstructionPredicates(unsigned Opcode, const FeatureBitset &Features);

} // end namespace MSP430_MC
} // end namespace llvm

#endif // GET_INSTRINFO_MC_HELPER_DECLS

#ifdef GET_INSTRINFO_MC_HELPERS
#undef GET_INSTRINFO_MC_HELPERS

namespace llvm {
namespace MSP430_MC {

} // end namespace MSP430_MC
} // end namespace llvm

#endif // GET_GENISTRINFO_MC_HELPERS

#if (defined(ENABLE_INSTR_PREDICATE_VERIFIER) && !defined(NDEBUG)) ||\
    defined(GET_AVAILABLE_OPCODE_CHECKER)
#define GET_COMPUTE_FEATURES
#endif
#ifdef GET_COMPUTE_FEATURES
#undef GET_COMPUTE_FEATURES
namespace llvm {
namespace MSP430_MC {

// Bits for subtarget features that participate in instruction matching.
enum SubtargetFeatureBits : uint8_t {
};

inline FeatureBitset computeAvailableFeatures(const FeatureBitset &FB) {
  FeatureBitset Features;
  return Features;
}

inline FeatureBitset computeRequiredFeatures(unsigned Opcode) {
  enum : uint8_t {
    CEFBS_None,
  };

  static constexpr FeatureBitset FeatureBitsets[] = {
    {}, // CEFBS_None
  };
  static constexpr uint8_t RequiredFeaturesRefs[] = {
    CEFBS_None, // PHI = 0
    CEFBS_None, // INLINEASM = 1
    CEFBS_None, // INLINEASM_BR = 2
    CEFBS_None, // CFI_INSTRUCTION = 3
    CEFBS_None, // EH_LABEL = 4
    CEFBS_None, // GC_LABEL = 5
    CEFBS_None, // ANNOTATION_LABEL = 6
    CEFBS_None, // KILL = 7
    CEFBS_None, // EXTRACT_SUBREG = 8
    CEFBS_None, // INSERT_SUBREG = 9
    CEFBS_None, // IMPLICIT_DEF = 10
    CEFBS_None, // SUBREG_TO_REG = 11
    CEFBS_None, // COPY_TO_REGCLASS = 12
    CEFBS_None, // DBG_VALUE = 13
    CEFBS_None, // DBG_VALUE_LIST = 14
    CEFBS_None, // DBG_INSTR_REF = 15
    CEFBS_None, // DBG_PHI = 16
    CEFBS_None, // DBG_LABEL = 17
    CEFBS_None, // REG_SEQUENCE = 18
    CEFBS_None, // COPY = 19
    CEFBS_None, // BUNDLE = 20
    CEFBS_None, // LIFETIME_START = 21
    CEFBS_None, // LIFETIME_END = 22
    CEFBS_None, // PSEUDO_PROBE = 23
    CEFBS_None, // ARITH_FENCE = 24
    CEFBS_None, // STACKMAP = 25
    CEFBS_None, // FENTRY_CALL = 26
    CEFBS_None, // PATCHPOINT = 27
    CEFBS_None, // LOAD_STACK_GUARD = 28
    CEFBS_None, // PREALLOCATED_SETUP = 29
    CEFBS_None, // PREALLOCATED_ARG = 30
    CEFBS_None, // STATEPOINT = 31
    CEFBS_None, // LOCAL_ESCAPE = 32
    CEFBS_None, // FAULTING_OP = 33
    CEFBS_None, // PATCHABLE_OP = 34
    CEFBS_None, // PATCHABLE_FUNCTION_ENTER = 35
    CEFBS_None, // PATCHABLE_RET = 36
    CEFBS_None, // PATCHABLE_FUNCTION_EXIT = 37
    CEFBS_None, // PATCHABLE_TAIL_CALL = 38
    CEFBS_None, // PATCHABLE_EVENT_CALL = 39
    CEFBS_None, // PATCHABLE_TYPED_EVENT_CALL = 40
    CEFBS_None, // ICALL_BRANCH_FUNNEL = 41
    CEFBS_None, // FAKE_USE = 42
    CEFBS_None, // MEMBARRIER = 43
    CEFBS_None, // JUMP_TABLE_DEBUG_INFO = 44
    CEFBS_None, // CONVERGENCECTRL_ENTRY = 45
    CEFBS_None, // CONVERGENCECTRL_ANCHOR = 46
    CEFBS_None, // CONVERGENCECTRL_LOOP = 47
    CEFBS_None, // CONVERGENCECTRL_GLUE = 48
    CEFBS_None, // G_ASSERT_SEXT = 49
    CEFBS_None, // G_ASSERT_ZEXT = 50
    CEFBS_None, // G_ASSERT_ALIGN = 51
    CEFBS_None, // G_ADD = 52
    CEFBS_None, // G_SUB = 53
    CEFBS_None, // G_MUL = 54
    CEFBS_None, // G_SDIV = 55
    CEFBS_None, // G_UDIV = 56
    CEFBS_None, // G_SREM = 57
    CEFBS_None, // G_UREM = 58
    CEFBS_None, // G_SDIVREM = 59
    CEFBS_None, // G_UDIVREM = 60
    CEFBS_None, // G_AND = 61
    CEFBS_None, // G_OR = 62
    CEFBS_None, // G_XOR = 63
    CEFBS_None, // G_IMPLICIT_DEF = 64
    CEFBS_None, // G_PHI = 65
    CEFBS_None, // G_FRAME_INDEX = 66
    CEFBS_None, // G_GLOBAL_VALUE = 67
    CEFBS_None, // G_PTRAUTH_GLOBAL_VALUE = 68
    CEFBS_None, // G_CONSTANT_POOL = 69
    CEFBS_None, // G_EXTRACT = 70
    CEFBS_None, // G_UNMERGE_VALUES = 71
    CEFBS_None, // G_INSERT = 72
    CEFBS_None, // G_MERGE_VALUES = 73
    CEFBS_None, // G_BUILD_VECTOR = 74
    CEFBS_None, // G_BUILD_VECTOR_TRUNC = 75
    CEFBS_None, // G_CONCAT_VECTORS = 76
    CEFBS_None, // G_PTRTOINT = 77
    CEFBS_None, // G_INTTOPTR = 78
    CEFBS_None, // G_BITCAST = 79
    CEFBS_None, // G_FREEZE = 80
    CEFBS_None, // G_CONSTANT_FOLD_BARRIER = 81
    CEFBS_None, // G_INTRINSIC_FPTRUNC_ROUND = 82
    CEFBS_None, // G_INTRINSIC_TRUNC = 83
    CEFBS_None, // G_INTRINSIC_ROUND = 84
    CEFBS_None, // G_INTRINSIC_LRINT = 85
    CEFBS_None, // G_INTRINSIC_LLRINT = 86
    CEFBS_None, // G_INTRINSIC_ROUNDEVEN = 87
    CEFBS_None, // G_READCYCLECOUNTER = 88
    CEFBS_None, // G_READSTEADYCOUNTER = 89
    CEFBS_None, // G_LOAD = 90
    CEFBS_None, // G_SEXTLOAD = 91
    CEFBS_None, // G_ZEXTLOAD = 92
    CEFBS_None, // G_INDEXED_LOAD = 93
    CEFBS_None, // G_INDEXED_SEXTLOAD = 94
    CEFBS_None, // G_INDEXED_ZEXTLOAD = 95
    CEFBS_None, // G_STORE = 96
    CEFBS_None, // G_INDEXED_STORE = 97
    CEFBS_None, // G_ATOMIC_CMPXCHG_WITH_SUCCESS = 98
    CEFBS_None, // G_ATOMIC_CMPXCHG = 99
    CEFBS_None, // G_ATOMICRMW_XCHG = 100
    CEFBS_None, // G_ATOMICRMW_ADD = 101
    CEFBS_None, // G_ATOMICRMW_SUB = 102
    CEFBS_None, // G_ATOMICRMW_AND = 103
    CEFBS_None, // G_ATOMICRMW_NAND = 104
    CEFBS_None, // G_ATOMICRMW_OR = 105
    CEFBS_None, // G_ATOMICRMW_XOR = 106
    CEFBS_None, // G_ATOMICRMW_MAX = 107
    CEFBS_None, // G_ATOMICRMW_MIN = 108
    CEFBS_None, // G_ATOMICRMW_UMAX = 109
    CEFBS_None, // G_ATOMICRMW_UMIN = 110
    CEFBS_None, // G_ATOMICRMW_FADD = 111
    CEFBS_None, // G_ATOMICRMW_FSUB = 112
    CEFBS_None, // G_ATOMICRMW_FMAX = 113
    CEFBS_None, // G_ATOMICRMW_FMIN = 114
    CEFBS_None, // G_ATOMICRMW_UINC_WRAP = 115
    CEFBS_None, // G_ATOMICRMW_UDEC_WRAP = 116
    CEFBS_None, // G_FENCE = 117
    CEFBS_None, // G_PREFETCH = 118
    CEFBS_None, // G_BRCOND = 119
    CEFBS_None, // G_BRINDIRECT = 120
    CEFBS_None, // G_INVOKE_REGION_START = 121
    CEFBS_None, // G_INTRINSIC = 122
    CEFBS_None, // G_INTRINSIC_W_SIDE_EFFECTS = 123
    CEFBS_None, // G_INTRINSIC_CONVERGENT = 124
    CEFBS_None, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS = 125
    CEFBS_None, // G_ANYEXT = 126
    CEFBS_None, // G_TRUNC = 127
    CEFBS_None, // G_CONSTANT = 128
    CEFBS_None, // G_FCONSTANT = 129
    CEFBS_None, // G_VASTART = 130
    CEFBS_None, // G_VAARG = 131
    CEFBS_None, // G_SEXT = 132
    CEFBS_None, // G_SEXT_INREG = 133
    CEFBS_None, // G_ZEXT = 134
    CEFBS_None, // G_SHL = 135
    CEFBS_None, // G_LSHR = 136
    CEFBS_None, // G_ASHR = 137
    CEFBS_None, // G_FSHL = 138
    CEFBS_None, // G_FSHR = 139
    CEFBS_None, // G_ROTR = 140
    CEFBS_None, // G_ROTL = 141
    CEFBS_None, // G_ICMP = 142
    CEFBS_None, // G_FCMP = 143
    CEFBS_None, // G_SCMP = 144
    CEFBS_None, // G_UCMP = 145
    CEFBS_None, // G_SELECT = 146
    CEFBS_None, // G_UADDO = 147
    CEFBS_None, // G_UADDE = 148
    CEFBS_None, // G_USUBO = 149
    CEFBS_None, // G_USUBE = 150
    CEFBS_None, // G_SADDO = 151
    CEFBS_None, // G_SADDE = 152
    CEFBS_None, // G_SSUBO = 153
    CEFBS_None, // G_SSUBE = 154
    CEFBS_None, // G_UMULO = 155
    CEFBS_None, // G_SMULO = 156
    CEFBS_None, // G_UMULH = 157
    CEFBS_None, // G_SMULH = 158
    CEFBS_None, // G_UADDSAT = 159
    CEFBS_None, // G_SADDSAT = 160
    CEFBS_None, // G_USUBSAT = 161
    CEFBS_None, // G_SSUBSAT = 162
    CEFBS_None, // G_USHLSAT = 163
    CEFBS_None, // G_SSHLSAT = 164
    CEFBS_None, // G_SMULFIX = 165
    CEFBS_None, // G_UMULFIX = 166
    CEFBS_None, // G_SMULFIXSAT = 167
    CEFBS_None, // G_UMULFIXSAT = 168
    CEFBS_None, // G_SDIVFIX = 169
    CEFBS_None, // G_UDIVFIX = 170
    CEFBS_None, // G_SDIVFIXSAT = 171
    CEFBS_None, // G_UDIVFIXSAT = 172
    CEFBS_None, // G_FADD = 173
    CEFBS_None, // G_FSUB = 174
    CEFBS_None, // G_FMUL = 175
    CEFBS_None, // G_FMA = 176
    CEFBS_None, // G_FMAD = 177
    CEFBS_None, // G_FDIV = 178
    CEFBS_None, // G_FREM = 179
    CEFBS_None, // G_FPOW = 180
    CEFBS_None, // G_FPOWI = 181
    CEFBS_None, // G_FEXP = 182
    CEFBS_None, // G_FEXP2 = 183
    CEFBS_None, // G_FEXP10 = 184
    CEFBS_None, // G_FLOG = 185
    CEFBS_None, // G_FLOG2 = 186
    CEFBS_None, // G_FLOG10 = 187
    CEFBS_None, // G_FLDEXP = 188
    CEFBS_None, // G_FFREXP = 189
    CEFBS_None, // G_FNEG = 190
    CEFBS_None, // G_FPEXT = 191
    CEFBS_None, // G_FPTRUNC = 192
    CEFBS_None, // G_FPTOSI = 193
    CEFBS_None, // G_FPTOUI = 194
    CEFBS_None, // G_SITOFP = 195
    CEFBS_None, // G_UITOFP = 196
    CEFBS_None, // G_FABS = 197
    CEFBS_None, // G_FCOPYSIGN = 198
    CEFBS_None, // G_IS_FPCLASS = 199
    CEFBS_None, // G_FCANONICALIZE = 200
    CEFBS_None, // G_FMINNUM = 201
    CEFBS_None, // G_FMAXNUM = 202
    CEFBS_None, // G_FMINNUM_IEEE = 203
    CEFBS_None, // G_FMAXNUM_IEEE = 204
    CEFBS_None, // G_FMINIMUM = 205
    CEFBS_None, // G_FMAXIMUM = 206
    CEFBS_None, // G_GET_FPENV = 207
    CEFBS_None, // G_SET_FPENV = 208
    CEFBS_None, // G_RESET_FPENV = 209
    CEFBS_None, // G_GET_FPMODE = 210
    CEFBS_None, // G_SET_FPMODE = 211
    CEFBS_None, // G_RESET_FPMODE = 212
    CEFBS_None, // G_PTR_ADD = 213
    CEFBS_None, // G_PTRMASK = 214
    CEFBS_None, // G_SMIN = 215
    CEFBS_None, // G_SMAX = 216
    CEFBS_None, // G_UMIN = 217
    CEFBS_None, // G_UMAX = 218
    CEFBS_None, // G_ABS = 219
    CEFBS_None, // G_LROUND = 220
    CEFBS_None, // G_LLROUND = 221
    CEFBS_None, // G_BR = 222
    CEFBS_None, // G_BRJT = 223
    CEFBS_None, // G_VSCALE = 224
    CEFBS_None, // G_INSERT_SUBVECTOR = 225
    CEFBS_None, // G_EXTRACT_SUBVECTOR = 226
    CEFBS_None, // G_INSERT_VECTOR_ELT = 227
    CEFBS_None, // G_EXTRACT_VECTOR_ELT = 228
    CEFBS_None, // G_SHUFFLE_VECTOR = 229
    CEFBS_None, // G_SPLAT_VECTOR = 230
    CEFBS_None, // G_VECTOR_COMPRESS = 231
    CEFBS_None, // G_CTTZ = 232
    CEFBS_None, // G_CTTZ_ZERO_UNDEF = 233
    CEFBS_None, // G_CTLZ = 234
    CEFBS_None, // G_CTLZ_ZERO_UNDEF = 235
    CEFBS_None, // G_CTPOP = 236
    CEFBS_None, // G_BSWAP = 237
    CEFBS_None, // G_BITREVERSE = 238
    CEFBS_None, // G_FCEIL = 239
    CEFBS_None, // G_FCOS = 240
    CEFBS_None, // G_FSIN = 241
    CEFBS_None, // G_FTAN = 242
    CEFBS_None, // G_FACOS = 243
    CEFBS_None, // G_FASIN = 244
    CEFBS_None, // G_FATAN = 245
    CEFBS_None, // G_FCOSH = 246
    CEFBS_None, // G_FSINH = 247
    CEFBS_None, // G_FTANH = 248
    CEFBS_None, // G_FSQRT = 249
    CEFBS_None, // G_FFLOOR = 250
    CEFBS_None, // G_FRINT = 251
    CEFBS_None, // G_FNEARBYINT = 252
    CEFBS_None, // G_ADDRSPACE_CAST = 253
    CEFBS_None, // G_BLOCK_ADDR = 254
    CEFBS_None, // G_JUMP_TABLE = 255
    CEFBS_None, // G_DYN_STACKALLOC = 256
    CEFBS_None, // G_STACKSAVE = 257
    CEFBS_None, // G_STACKRESTORE = 258
    CEFBS_None, // G_STRICT_FADD = 259
    CEFBS_None, // G_STRICT_FSUB = 260
    CEFBS_None, // G_STRICT_FMUL = 261
    CEFBS_None, // G_STRICT_FDIV = 262
    CEFBS_None, // G_STRICT_FREM = 263
    CEFBS_None, // G_STRICT_FMA = 264
    CEFBS_None, // G_STRICT_FSQRT = 265
    CEFBS_None, // G_STRICT_FLDEXP = 266
    CEFBS_None, // G_READ_REGISTER = 267
    CEFBS_None, // G_WRITE_REGISTER = 268
    CEFBS_None, // G_MEMCPY = 269
    CEFBS_None, // G_MEMCPY_INLINE = 270
    CEFBS_None, // G_MEMMOVE = 271
    CEFBS_None, // G_MEMSET = 272
    CEFBS_None, // G_BZERO = 273
    CEFBS_None, // G_TRAP = 274
    CEFBS_None, // G_DEBUGTRAP = 275
    CEFBS_None, // G_UBSANTRAP = 276
    CEFBS_None, // G_VECREDUCE_SEQ_FADD = 277
    CEFBS_None, // G_VECREDUCE_SEQ_FMUL = 278
    CEFBS_None, // G_VECREDUCE_FADD = 279
    CEFBS_None, // G_VECREDUCE_FMUL = 280
    CEFBS_None, // G_VECREDUCE_FMAX = 281
    CEFBS_None, // G_VECREDUCE_FMIN = 282
    CEFBS_None, // G_VECREDUCE_FMAXIMUM = 283
    CEFBS_None, // G_VECREDUCE_FMINIMUM = 284
    CEFBS_None, // G_VECREDUCE_ADD = 285
    CEFBS_None, // G_VECREDUCE_MUL = 286
    CEFBS_None, // G_VECREDUCE_AND = 287
    CEFBS_None, // G_VECREDUCE_OR = 288
    CEFBS_None, // G_VECREDUCE_XOR = 289
    CEFBS_None, // G_VECREDUCE_SMAX = 290
    CEFBS_None, // G_VECREDUCE_SMIN = 291
    CEFBS_None, // G_VECREDUCE_UMAX = 292
    CEFBS_None, // G_VECREDUCE_UMIN = 293
    CEFBS_None, // G_SBFX = 294
    CEFBS_None, // G_UBFX = 295
    CEFBS_None, // ADD16mc = 296
    CEFBS_None, // ADD16mi = 297
    CEFBS_None, // ADD16mm = 298
    CEFBS_None, // ADD16mn = 299
    CEFBS_None, // ADD16mp = 300
    CEFBS_None, // ADD16mr = 301
    CEFBS_None, // ADD16rc = 302
    CEFBS_None, // ADD16ri = 303
    CEFBS_None, // ADD16rm = 304
    CEFBS_None, // ADD16rn = 305
    CEFBS_None, // ADD16rp = 306
    CEFBS_None, // ADD16rr = 307
    CEFBS_None, // ADD8mc = 308
    CEFBS_None, // ADD8mi = 309
    CEFBS_None, // ADD8mm = 310
    CEFBS_None, // ADD8mn = 311
    CEFBS_None, // ADD8mp = 312
    CEFBS_None, // ADD8mr = 313
    CEFBS_None, // ADD8rc = 314
    CEFBS_None, // ADD8ri = 315
    CEFBS_None, // ADD8rm = 316
    CEFBS_None, // ADD8rn = 317
    CEFBS_None, // ADD8rp = 318
    CEFBS_None, // ADD8rr = 319
    CEFBS_None, // ADDC16mc = 320
    CEFBS_None, // ADDC16mi = 321
    CEFBS_None, // ADDC16mm = 322
    CEFBS_None, // ADDC16mn = 323
    CEFBS_None, // ADDC16mp = 324
    CEFBS_None, // ADDC16mr = 325
    CEFBS_None, // ADDC16rc = 326
    CEFBS_None, // ADDC16ri = 327
    CEFBS_None, // ADDC16rm = 328
    CEFBS_None, // ADDC16rn = 329
    CEFBS_None, // ADDC16rp = 330
    CEFBS_None, // ADDC16rr = 331
    CEFBS_None, // ADDC8mc = 332
    CEFBS_None, // ADDC8mi = 333
    CEFBS_None, // ADDC8mm = 334
    CEFBS_None, // ADDC8mn = 335
    CEFBS_None, // ADDC8mp = 336
    CEFBS_None, // ADDC8mr = 337
    CEFBS_None, // ADDC8rc = 338
    CEFBS_None, // ADDC8ri = 339
    CEFBS_None, // ADDC8rm = 340
    CEFBS_None, // ADDC8rn = 341
    CEFBS_None, // ADDC8rp = 342
    CEFBS_None, // ADDC8rr = 343
    CEFBS_None, // ADDframe = 344
    CEFBS_None, // ADJCALLSTACKDOWN = 345
    CEFBS_None, // ADJCALLSTACKUP = 346
    CEFBS_None, // AND16mc = 347
    CEFBS_None, // AND16mi = 348
    CEFBS_None, // AND16mm = 349
    CEFBS_None, // AND16mn = 350
    CEFBS_None, // AND16mp = 351
    CEFBS_None, // AND16mr = 352
    CEFBS_None, // AND16rc = 353
    CEFBS_None, // AND16ri = 354
    CEFBS_None, // AND16rm = 355
    CEFBS_None, // AND16rn = 356
    CEFBS_None, // AND16rp = 357
    CEFBS_None, // AND16rr = 358
    CEFBS_None, // AND8mc = 359
    CEFBS_None, // AND8mi = 360
    CEFBS_None, // AND8mm = 361
    CEFBS_None, // AND8mn = 362
    CEFBS_None, // AND8mp = 363
    CEFBS_None, // AND8mr = 364
    CEFBS_None, // AND8rc = 365
    CEFBS_None, // AND8ri = 366
    CEFBS_None, // AND8rm = 367
    CEFBS_None, // AND8rn = 368
    CEFBS_None, // AND8rp = 369
    CEFBS_None, // AND8rr = 370
    CEFBS_None, // BIC16mc = 371
    CEFBS_None, // BIC16mi = 372
    CEFBS_None, // BIC16mm = 373
    CEFBS_None, // BIC16mn = 374
    CEFBS_None, // BIC16mp = 375
    CEFBS_None, // BIC16mr = 376
    CEFBS_None, // BIC16rc = 377
    CEFBS_None, // BIC16ri = 378
    CEFBS_None, // BIC16rm = 379
    CEFBS_None, // BIC16rn = 380
    CEFBS_None, // BIC16rp = 381
    CEFBS_None, // BIC16rr = 382
    CEFBS_None, // BIC8mc = 383
    CEFBS_None, // BIC8mi = 384
    CEFBS_None, // BIC8mm = 385
    CEFBS_None, // BIC8mn = 386
    CEFBS_None, // BIC8mp = 387
    CEFBS_None, // BIC8mr = 388
    CEFBS_None, // BIC8rc = 389
    CEFBS_None, // BIC8ri = 390
    CEFBS_None, // BIC8rm = 391
    CEFBS_None, // BIC8rn = 392
    CEFBS_None, // BIC8rp = 393
    CEFBS_None, // BIC8rr = 394
    CEFBS_None, // BIS16mc = 395
    CEFBS_None, // BIS16mi = 396
    CEFBS_None, // BIS16mm = 397
    CEFBS_None, // BIS16mn = 398
    CEFBS_None, // BIS16mp = 399
    CEFBS_None, // BIS16mr = 400
    CEFBS_None, // BIS16rc = 401
    CEFBS_None, // BIS16ri = 402
    CEFBS_None, // BIS16rm = 403
    CEFBS_None, // BIS16rn = 404
    CEFBS_None, // BIS16rp = 405
    CEFBS_None, // BIS16rr = 406
    CEFBS_None, // BIS8mc = 407
    CEFBS_None, // BIS8mi = 408
    CEFBS_None, // BIS8mm = 409
    CEFBS_None, // BIS8mn = 410
    CEFBS_None, // BIS8mp = 411
    CEFBS_None, // BIS8mr = 412
    CEFBS_None, // BIS8rc = 413
    CEFBS_None, // BIS8ri = 414
    CEFBS_None, // BIS8rm = 415
    CEFBS_None, // BIS8rn = 416
    CEFBS_None, // BIS8rp = 417
    CEFBS_None, // BIS8rr = 418
    CEFBS_None, // BIT16mc = 419
    CEFBS_None, // BIT16mi = 420
    CEFBS_None, // BIT16mm = 421
    CEFBS_None, // BIT16mn = 422
    CEFBS_None, // BIT16mp = 423
    CEFBS_None, // BIT16mr = 424
    CEFBS_None, // BIT16rc = 425
    CEFBS_None, // BIT16ri = 426
    CEFBS_None, // BIT16rm = 427
    CEFBS_None, // BIT16rn = 428
    CEFBS_None, // BIT16rp = 429
    CEFBS_None, // BIT16rr = 430
    CEFBS_None, // BIT8mc = 431
    CEFBS_None, // BIT8mi = 432
    CEFBS_None, // BIT8mm = 433
    CEFBS_None, // BIT8mn = 434
    CEFBS_None, // BIT8mp = 435
    CEFBS_None, // BIT8mr = 436
    CEFBS_None, // BIT8rc = 437
    CEFBS_None, // BIT8ri = 438
    CEFBS_None, // BIT8rm = 439
    CEFBS_None, // BIT8rn = 440
    CEFBS_None, // BIT8rp = 441
    CEFBS_None, // BIT8rr = 442
    CEFBS_None, // Bi = 443
    CEFBS_None, // Bm = 444
    CEFBS_None, // Br = 445
    CEFBS_None, // CALLi = 446
    CEFBS_None, // CALLm = 447
    CEFBS_None, // CALLn = 448
    CEFBS_None, // CALLp = 449
    CEFBS_None, // CALLr = 450
    CEFBS_None, // CMP16mc = 451
    CEFBS_None, // CMP16mi = 452
    CEFBS_None, // CMP16mm = 453
    CEFBS_None, // CMP16mn = 454
    CEFBS_None, // CMP16mp = 455
    CEFBS_None, // CMP16mr = 456
    CEFBS_None, // CMP16rc = 457
    CEFBS_None, // CMP16ri = 458
    CEFBS_None, // CMP16rm = 459
    CEFBS_None, // CMP16rn = 460
    CEFBS_None, // CMP16rp = 461
    CEFBS_None, // CMP16rr = 462
    CEFBS_None, // CMP8mc = 463
    CEFBS_None, // CMP8mi = 464
    CEFBS_None, // CMP8mm = 465
    CEFBS_None, // CMP8mn = 466
    CEFBS_None, // CMP8mp = 467
    CEFBS_None, // CMP8mr = 468
    CEFBS_None, // CMP8rc = 469
    CEFBS_None, // CMP8ri = 470
    CEFBS_None, // CMP8rm = 471
    CEFBS_None, // CMP8rn = 472
    CEFBS_None, // CMP8rp = 473
    CEFBS_None, // CMP8rr = 474
    CEFBS_None, // DADD16mc = 475
    CEFBS_None, // DADD16mi = 476
    CEFBS_None, // DADD16mm = 477
    CEFBS_None, // DADD16mn = 478
    CEFBS_None, // DADD16mp = 479
    CEFBS_None, // DADD16mr = 480
    CEFBS_None, // DADD16rc = 481
    CEFBS_None, // DADD16ri = 482
    CEFBS_None, // DADD16rm = 483
    CEFBS_None, // DADD16rn = 484
    CEFBS_None, // DADD16rp = 485
    CEFBS_None, // DADD16rr = 486
    CEFBS_None, // DADD8mc = 487
    CEFBS_None, // DADD8mi = 488
    CEFBS_None, // DADD8mm = 489
    CEFBS_None, // DADD8mn = 490
    CEFBS_None, // DADD8mp = 491
    CEFBS_None, // DADD8mr = 492
    CEFBS_None, // DADD8rc = 493
    CEFBS_None, // DADD8ri = 494
    CEFBS_None, // DADD8rm = 495
    CEFBS_None, // DADD8rn = 496
    CEFBS_None, // DADD8rp = 497
    CEFBS_None, // DADD8rr = 498
    CEFBS_None, // JCC = 499
    CEFBS_None, // JMP = 500
    CEFBS_None, // MOV16mc = 501
    CEFBS_None, // MOV16mi = 502
    CEFBS_None, // MOV16mm = 503
    CEFBS_None, // MOV16mn = 504
    CEFBS_None, // MOV16mr = 505
    CEFBS_None, // MOV16rc = 506
    CEFBS_None, // MOV16ri = 507
    CEFBS_None, // MOV16rm = 508
    CEFBS_None, // MOV16rn = 509
    CEFBS_None, // MOV16rp = 510
    CEFBS_None, // MOV16rr = 511
    CEFBS_None, // MOV8mc = 512
    CEFBS_None, // MOV8mi = 513
    CEFBS_None, // MOV8mm = 514
    CEFBS_None, // MOV8mn = 515
    CEFBS_None, // MOV8mr = 516
    CEFBS_None, // MOV8rc = 517
    CEFBS_None, // MOV8ri = 518
    CEFBS_None, // MOV8rm = 519
    CEFBS_None, // MOV8rn = 520
    CEFBS_None, // MOV8rp = 521
    CEFBS_None, // MOV8rr = 522
    CEFBS_None, // MOVZX16rm8 = 523
    CEFBS_None, // MOVZX16rr8 = 524
    CEFBS_None, // POP16r = 525
    CEFBS_None, // PUSH16c = 526
    CEFBS_None, // PUSH16i = 527
    CEFBS_None, // PUSH16r = 528
    CEFBS_None, // PUSH8r = 529
    CEFBS_None, // RET = 530
    CEFBS_None, // RETI = 531
    CEFBS_None, // RRA16m = 532
    CEFBS_None, // RRA16n = 533
    CEFBS_None, // RRA16p = 534
    CEFBS_None, // RRA16r = 535
    CEFBS_None, // RRA8m = 536
    CEFBS_None, // RRA8n = 537
    CEFBS_None, // RRA8p = 538
    CEFBS_None, // RRA8r = 539
    CEFBS_None, // RRC16m = 540
    CEFBS_None, // RRC16n = 541
    CEFBS_None, // RRC16p = 542
    CEFBS_None, // RRC16r = 543
    CEFBS_None, // RRC8m = 544
    CEFBS_None, // RRC8n = 545
    CEFBS_None, // RRC8p = 546
    CEFBS_None, // RRC8r = 547
    CEFBS_None, // Rrcl16 = 548
    CEFBS_None, // Rrcl8 = 549
    CEFBS_None, // SEXT16m = 550
    CEFBS_None, // SEXT16n = 551
    CEFBS_None, // SEXT16p = 552
    CEFBS_None, // SEXT16r = 553
    CEFBS_None, // SUB16mc = 554
    CEFBS_None, // SUB16mi = 555
    CEFBS_None, // SUB16mm = 556
    CEFBS_None, // SUB16mn = 557
    CEFBS_None, // SUB16mp = 558
    CEFBS_None, // SUB16mr = 559
    CEFBS_None, // SUB16rc = 560
    CEFBS_None, // SUB16ri = 561
    CEFBS_None, // SUB16rm = 562
    CEFBS_None, // SUB16rn = 563
    CEFBS_None, // SUB16rp = 564
    CEFBS_None, // SUB16rr = 565
    CEFBS_None, // SUB8mc = 566
    CEFBS_None, // SUB8mi = 567
    CEFBS_None, // SUB8mm = 568
    CEFBS_None, // SUB8mn = 569
    CEFBS_None, // SUB8mp = 570
    CEFBS_None, // SUB8mr = 571
    CEFBS_None, // SUB8rc = 572
    CEFBS_None, // SUB8ri = 573
    CEFBS_None, // SUB8rm = 574
    CEFBS_None, // SUB8rn = 575
    CEFBS_None, // SUB8rp = 576
    CEFBS_None, // SUB8rr = 577
    CEFBS_None, // SUBC16mc = 578
    CEFBS_None, // SUBC16mi = 579
    CEFBS_None, // SUBC16mm = 580
    CEFBS_None, // SUBC16mn = 581
    CEFBS_None, // SUBC16mp = 582
    CEFBS_None, // SUBC16mr = 583
    CEFBS_None, // SUBC16rc = 584
    CEFBS_None, // SUBC16ri = 585
    CEFBS_None, // SUBC16rm = 586
    CEFBS_None, // SUBC16rn = 587
    CEFBS_None, // SUBC16rp = 588
    CEFBS_None, // SUBC16rr = 589
    CEFBS_None, // SUBC8mc = 590
    CEFBS_None, // SUBC8mi = 591
    CEFBS_None, // SUBC8mm = 592
    CEFBS_None, // SUBC8mn = 593
    CEFBS_None, // SUBC8mp = 594
    CEFBS_None, // SUBC8mr = 595
    CEFBS_None, // SUBC8rc = 596
    CEFBS_None, // SUBC8ri = 597
    CEFBS_None, // SUBC8rm = 598
    CEFBS_None, // SUBC8rn = 599
    CEFBS_None, // SUBC8rp = 600
    CEFBS_None, // SUBC8rr = 601
    CEFBS_None, // SWPB16m = 602
    CEFBS_None, // SWPB16n = 603
    CEFBS_None, // SWPB16p = 604
    CEFBS_None, // SWPB16r = 605
    CEFBS_None, // Select16 = 606
    CEFBS_None, // Select8 = 607
    CEFBS_None, // Shl16 = 608
    CEFBS_None, // Shl8 = 609
    CEFBS_None, // Sra16 = 610
    CEFBS_None, // Sra8 = 611
    CEFBS_None, // Srl16 = 612
    CEFBS_None, // Srl8 = 613
    CEFBS_None, // XOR16mc = 614
    CEFBS_None, // XOR16mi = 615
    CEFBS_None, // XOR16mm = 616
    CEFBS_None, // XOR16mn = 617
    CEFBS_None, // XOR16mp = 618
    CEFBS_None, // XOR16mr = 619
    CEFBS_None, // XOR16rc = 620
    CEFBS_None, // XOR16ri = 621
    CEFBS_None, // XOR16rm = 622
    CEFBS_None, // XOR16rn = 623
    CEFBS_None, // XOR16rp = 624
    CEFBS_None, // XOR16rr = 625
    CEFBS_None, // XOR8mc = 626
    CEFBS_None, // XOR8mi = 627
    CEFBS_None, // XOR8mm = 628
    CEFBS_None, // XOR8mn = 629
    CEFBS_None, // XOR8mp = 630
    CEFBS_None, // XOR8mr = 631
    CEFBS_None, // XOR8rc = 632
    CEFBS_None, // XOR8ri = 633
    CEFBS_None, // XOR8rm = 634
    CEFBS_None, // XOR8rn = 635
    CEFBS_None, // XOR8rp = 636
    CEFBS_None, // XOR8rr = 637
    CEFBS_None, // ZEXT16r = 638
  };

  assert(Opcode < 639);
  return FeatureBitsets[RequiredFeaturesRefs[Opcode]];
}

} // end namespace MSP430_MC
} // end namespace llvm
#endif // GET_COMPUTE_FEATURES

#ifdef GET_AVAILABLE_OPCODE_CHECKER
#undef GET_AVAILABLE_OPCODE_CHECKER
namespace llvm {
namespace MSP430_MC {
bool isOpcodeAvailable(unsigned Opcode, const FeatureBitset &Features) {
  FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
  FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
  FeatureBitset MissingFeatures =
      (AvailableFeatures & RequiredFeatures) ^
      RequiredFeatures;
  return !MissingFeatures.any();
}
} // end namespace MSP430_MC
} // end namespace llvm
#endif // GET_AVAILABLE_OPCODE_CHECKER

#ifdef ENABLE_INSTR_PREDICATE_VERIFIER
#undef ENABLE_INSTR_PREDICATE_VERIFIER
#include <sstream>

namespace llvm {
namespace MSP430_MC {

#ifndef NDEBUG
static const char *SubtargetFeatureNames[] = {
  nullptr
};

#endif // NDEBUG

void verifyInstructionPredicates(
    unsigned Opcode, const FeatureBitset &Features) {
#ifndef NDEBUG
  FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
  FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
  FeatureBitset MissingFeatures =
      (AvailableFeatures & RequiredFeatures) ^
      RequiredFeatures;
  if (MissingFeatures.any()) {
    std::ostringstream Msg;
    Msg << "Attempting to emit " << &MSP430InstrNameData[MSP430InstrNameIndices[Opcode]]
        << " instruction but the ";
    for (unsigned i = 0, e = MissingFeatures.size(); i != e; ++i)
      if (MissingFeatures.test(i))
        Msg << SubtargetFeatureNames[i] << " ";
    Msg << "predicate(s) are not met";
    report_fatal_error(Msg.str().c_str());
  }
#endif // NDEBUG
}
} // end namespace MSP430_MC
} // end namespace llvm
#endif // ENABLE_INSTR_PREDICATE_VERIFIER