/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |* *| |* Target Instruction Enum Values and Descriptors *| |* *| |* Automatically generated file, do not edit! *| |* *| \*===----------------------------------------------------------------------===*/ #ifdef GET_INSTRINFO_ENUM #undef GET_INSTRINFO_ENUM namespace llvm { namespace SP { enum { … }; } // end namespace SP } // end namespace llvm #endif // GET_INSTRINFO_ENUM #ifdef GET_INSTRINFO_SCHED_ENUM #undef GET_INSTRINFO_SCHED_ENUM namespace llvm { namespace SP { namespace Sched { enum { NoInstrModel = 0, IIC_iu_instr = 1, IIC_fpu_normal_instr = 2, IIC_jmp_or_call = 3, IIC_fpu_abs = 4, IIC_fpu_fast_instr = 5, IIC_fpu_divd = 6, IIC_fpu_divs = 7, IIC_fpu_muld = 8, IIC_fpu_muls = 9, IIC_fpu_negs = 10, IIC_fpu_sqrtd = 11, IIC_fpu_sqrts = 12, IIC_fpu_stod = 13, IIC_ldd = 14, IIC_iu_or_fpu_instr = 15, IIC_iu_div = 16, IIC_smac_umac = 17, IIC_iu_smul = 18, IIC_st = 19, IIC_std = 20, IIC_iu_umul = 21, SCHED_LIST_END = 22 }; } // end namespace Sched } // end namespace SP } // end namespace llvm #endif // GET_INSTRINFO_SCHED_ENUM #if defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR) namespace llvm { struct SparcInstrTable { MCInstrDesc Insts[810]; static_assert(alignof(MCInstrDesc) >= alignof(MCOperandInfo), "Unwanted padding between Insts and OperandInfo"); MCOperandInfo OperandInfo[544]; static_assert(alignof(MCOperandInfo) >= alignof(MCPhysReg), "Unwanted padding between OperandInfo and ImplicitOps"); MCPhysReg ImplicitOps[32]; }; } // end namespace llvm #endif // defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR) #ifdef GET_INSTRINFO_MC_DESC #undef GET_INSTRINFO_MC_DESC namespace llvm { static_assert(sizeof(MCOperandInfo) % sizeof(MCPhysReg) == 0); static constexpr unsigned SparcImpOpBase = sizeof SparcInstrTable::OperandInfo / (sizeof(MCPhysReg)); extern const SparcInstrTable SparcDescs = { { { 809, 3, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 176, 0, 0x0ULL }, // Inst #809 = XORrr { 808, 3, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 173, 0, 0x0ULL }, // Inst #808 = XORri { 807, 3, 1, 4, 1, 0, 1, SparcImpOpBase + 4, 176, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #807 = XORCCrr { 806, 3, 1, 4, 1, 0, 1, SparcImpOpBase + 4, 173, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #806 = XORCCri { 805, 3, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 176, 0, 0x0ULL }, // Inst #805 = XNORrr { 804, 3, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 173, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #804 = XNORri { 803, 3, 1, 4, 1, 0, 1, SparcImpOpBase + 4, 176, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #803 = XNORCCrr { 802, 3, 1, 4, 1, 0, 1, SparcImpOpBase + 4, 173, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #802 = XNORCCri { 801, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 179, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #801 = XMULXHI { 800, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 179, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #800 = XMULX { 799, 2, 0, 4, 1, 0, 1, SparcImpOpBase + 18, 375, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #799 = WRWIMrr { 798, 2, 0, 4, 1, 0, 1, SparcImpOpBase + 18, 168, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #798 = WRWIMri { 797, 2, 0, 4, 1, 0, 1, SparcImpOpBase + 17, 375, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #797 = WRTBRrr { 796, 2, 0, 4, 1, 0, 1, SparcImpOpBase + 17, 168, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #796 = WRTBRri { 795, 2, 0, 4, 1, 0, 1, SparcImpOpBase + 15, 375, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #795 = WRPSRrr { 794, 2, 0, 4, 1, 0, 1, SparcImpOpBase + 15, 168, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #794 = WRPSRri { 793, 3, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 541, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #793 = WRPRrr { 792, 3, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 538, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #792 = WRPRri { 791, 3, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 535, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #791 = WRASRrr { 790, 3, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 532, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #790 = WRASRri { 789, 5, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 527, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #789 = V9MOVFCCrr { 788, 5, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 522, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #788 = V9MOVFCCri { 787, 5, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 517, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #787 = V9FMOVS_FCC { 786, 5, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 512, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #786 = V9FMOVQ_FCC { 785, 5, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 507, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #785 = V9FMOVD_FCC { 784, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 504, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #784 = V9FCMPS { 783, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 501, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #783 = V9FCMPQ { 782, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 504, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #782 = V9FCMPES { 781, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 501, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #781 = V9FCMPEQ { 780, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 238, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #780 = V9FCMPED { 779, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 238, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #779 = V9FCMPD { 778, 1, 0, 4, 0, 0, 0, SparcImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #778 = UNIMP { 777, 3, 1, 4, 21, 0, 1, SparcImpOpBase + 30, 176, 0, 0x0ULL }, // Inst #777 = UMULrr { 776, 3, 1, 4, 21, 0, 1, SparcImpOpBase + 30, 173, 0, 0x0ULL }, // Inst #776 = UMULri { 775, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 179, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #775 = UMULXHI { 774, 3, 1, 4, 21, 0, 2, SparcImpOpBase + 28, 176, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #774 = UMULCCrr { 773, 3, 1, 4, 21, 0, 2, SparcImpOpBase + 28, 173, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #773 = UMULCCri { 772, 4, 1, 4, 17, 2, 2, SparcImpOpBase + 24, 405, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #772 = UMACrr { 771, 4, 1, 4, 17, 2, 2, SparcImpOpBase + 24, 401, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #771 = UMACri { 770, 3, 1, 4, 16, 1, 1, SparcImpOpBase + 22, 176, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #770 = UDIVrr { 769, 3, 1, 4, 16, 1, 1, SparcImpOpBase + 22, 173, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #769 = UDIVri { 768, 3, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 179, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #768 = UDIVXrr { 767, 3, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 173, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #767 = UDIVXri { 766, 3, 1, 4, 16, 1, 2, SparcImpOpBase + 19, 176, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #766 = UDIVCCrr { 765, 3, 1, 4, 16, 1, 2, SparcImpOpBase + 19, 173, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #765 = UDIVCCri { 764, 3, 0, 4, 0, 1, 0, SparcImpOpBase + 4, 398, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #764 = TXCCrr { 763, 3, 0, 4, 0, 1, 0, SparcImpOpBase + 4, 494, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #763 = TXCCri { 762, 3, 1, 4, 1, 0, 1, SparcImpOpBase + 4, 176, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #762 = TSUBCCrr { 761, 3, 1, 4, 1, 0, 1, SparcImpOpBase + 4, 173, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #761 = TSUBCCri { 760, 3, 1, 4, 1, 0, 1, SparcImpOpBase + 4, 176, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #760 = TSUBCCTVrr { 759, 3, 1, 4, 1, 0, 1, SparcImpOpBase + 4, 173, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #759 = TSUBCCTVri { 758, 3, 0, 4, 0, 1, 0, SparcImpOpBase + 4, 398, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #758 = TRAPrr { 757, 3, 0, 4, 0, 1, 0, SparcImpOpBase + 4, 494, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #757 = TRAPri { 756, 4, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 283, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #756 = TLS_LDrr { 755, 4, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 283, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #755 = TLS_LDXrr { 754, 2, 0, 4, 3, 1, 0, SparcImpOpBase + 7, 13, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #754 = TLS_CALL { 753, 4, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 497, 0, 0x0ULL }, // Inst #753 = TLS_ADDrr { 752, 3, 0, 4, 0, 1, 0, SparcImpOpBase + 4, 398, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #752 = TICCrr { 751, 3, 0, 4, 0, 1, 0, SparcImpOpBase + 4, 494, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #751 = TICCri { 750, 2, 0, 4, 1, 0, 0, SparcImpOpBase + 0, 35, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #750 = TAIL_CALLri { 749, 1, 0, 4, 0, 0, 0, SparcImpOpBase + 0, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #749 = TAIL_CALL { 748, 3, 1, 4, 1, 0, 1, SparcImpOpBase + 4, 176, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #748 = TADDCCrr { 747, 3, 1, 4, 1, 0, 1, SparcImpOpBase + 4, 173, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #747 = TADDCCri { 746, 3, 1, 4, 1, 0, 1, SparcImpOpBase + 4, 176, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #746 = TADDCCTVrr { 745, 3, 1, 4, 1, 0, 1, SparcImpOpBase + 4, 173, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #745 = TADDCCTVri { 744, 0, 0, 4, 1, 0, 0, SparcImpOpBase + 0, 1, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #744 = TA5 { 743, 0, 0, 4, 1, 0, 0, SparcImpOpBase + 0, 1, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #743 = TA3 { 742, 0, 0, 4, 1, 0, 0, SparcImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #742 = TA1 { 741, 4, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 490, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #741 = SWAPrr { 740, 4, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 481, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #740 = SWAPri { 739, 5, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 485, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #739 = SWAPArr { 738, 4, 1, 4, 1, 1, 0, SparcImpOpBase + 8, 481, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #738 = SWAPAri { 737, 3, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 176, 0, 0x0ULL }, // Inst #737 = SUBrr { 736, 3, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 173, 0, 0x0ULL }, // Inst #736 = SUBri { 735, 3, 1, 4, 1, 1, 1, SparcImpOpBase + 5, 176, 0, 0x0ULL }, // Inst #735 = SUBErr { 734, 3, 1, 4, 1, 1, 1, SparcImpOpBase + 5, 173, 0, 0x0ULL }, // Inst #734 = SUBEri { 733, 3, 1, 4, 1, 1, 0, SparcImpOpBase + 4, 176, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #733 = SUBCrr { 732, 3, 1, 4, 1, 1, 0, SparcImpOpBase + 4, 173, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #732 = SUBCri { 731, 3, 1, 4, 1, 0, 1, SparcImpOpBase + 4, 176, 0|(1ULL<<MCID::HasPostISelHook), 0x0ULL }, // Inst #731 = SUBCCrr { 730, 3, 1, 4, 1, 0, 1, SparcImpOpBase + 4, 173, 0|(1ULL<<MCID::HasPostISelHook), 0x0ULL }, // Inst #730 = SUBCCri { 729, 3, 0, 4, 19, 0, 0, SparcImpOpBase + 0, 416, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #729 = STrr { 728, 3, 0, 4, 19, 0, 0, SparcImpOpBase + 0, 409, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #728 = STri { 727, 3, 0, 4, 19, 0, 0, SparcImpOpBase + 0, 478, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #727 = STXrr { 726, 3, 0, 4, 19, 0, 0, SparcImpOpBase + 0, 471, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #726 = STXri { 725, 2, 0, 4, 1, 1, 0, SparcImpOpBase + 10, 182, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #725 = STXFSRrr { 724, 2, 0, 4, 1, 1, 0, SparcImpOpBase + 10, 35, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #724 = STXFSRri { 723, 4, 0, 4, 19, 0, 0, SparcImpOpBase + 0, 474, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #723 = STXArr { 722, 3, 0, 4, 19, 1, 0, SparcImpOpBase + 8, 471, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #722 = STXAri { 721, 3, 0, 4, 19, 0, 0, SparcImpOpBase + 0, 468, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #721 = STQFrr { 720, 3, 0, 4, 19, 0, 0, SparcImpOpBase + 0, 461, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #720 = STQFri { 719, 4, 0, 4, 19, 0, 0, SparcImpOpBase + 0, 464, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #719 = STQFArr { 718, 3, 0, 4, 19, 1, 0, SparcImpOpBase + 8, 461, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #718 = STQFAri { 717, 3, 0, 4, 19, 0, 0, SparcImpOpBase + 0, 416, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #717 = STHrr { 716, 3, 0, 4, 19, 0, 0, SparcImpOpBase + 0, 409, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #716 = STHri { 715, 4, 0, 4, 19, 0, 0, SparcImpOpBase + 0, 412, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #715 = STHArr { 714, 3, 0, 4, 19, 1, 0, SparcImpOpBase + 8, 409, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #714 = STHAri { 713, 3, 0, 4, 19, 0, 0, SparcImpOpBase + 0, 458, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #713 = STFrr { 712, 3, 0, 4, 19, 0, 0, SparcImpOpBase + 0, 451, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #712 = STFri { 711, 2, 0, 4, 19, 1, 0, SparcImpOpBase + 10, 182, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #711 = STFSRrr { 710, 2, 0, 4, 19, 1, 0, SparcImpOpBase + 10, 35, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #710 = STFSRri { 709, 4, 0, 4, 19, 0, 0, SparcImpOpBase + 0, 454, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #709 = STFArr { 708, 3, 0, 4, 19, 1, 0, SparcImpOpBase + 8, 451, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #708 = STFAri { 707, 3, 0, 4, 19, 0, 0, SparcImpOpBase + 0, 448, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #707 = STDrr { 706, 3, 0, 4, 19, 0, 0, SparcImpOpBase + 0, 425, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #706 = STDri { 705, 3, 0, 4, 20, 0, 0, SparcImpOpBase + 0, 445, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #705 = STDFrr { 704, 3, 0, 4, 20, 0, 0, SparcImpOpBase + 0, 438, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #704 = STDFri { 703, 2, 0, 4, 20, 0, 1, SparcImpOpBase + 16, 182, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #703 = STDFQrr { 702, 2, 0, 4, 20, 0, 1, SparcImpOpBase + 16, 35, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #702 = STDFQri { 701, 4, 0, 4, 19, 0, 0, SparcImpOpBase + 0, 441, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #701 = STDFArr { 700, 3, 0, 4, 19, 1, 0, SparcImpOpBase + 8, 438, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #700 = STDFAri { 699, 3, 0, 4, 20, 0, 0, SparcImpOpBase + 0, 435, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #699 = STDCrr { 698, 3, 0, 4, 20, 0, 0, SparcImpOpBase + 0, 432, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #698 = STDCri { 697, 2, 0, 4, 20, 1, 0, SparcImpOpBase + 31, 182, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #697 = STDCQrr { 696, 2, 0, 4, 20, 1, 0, SparcImpOpBase + 31, 35, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #696 = STDCQri { 695, 4, 0, 4, 19, 0, 0, SparcImpOpBase + 0, 428, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #695 = STDArr { 694, 3, 0, 4, 19, 1, 0, SparcImpOpBase + 8, 425, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #694 = STDAri { 693, 3, 0, 4, 19, 0, 0, SparcImpOpBase + 0, 422, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #693 = STCrr { 692, 3, 0, 4, 19, 0, 0, SparcImpOpBase + 0, 419, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #692 = STCri { 691, 2, 0, 4, 19, 1, 0, SparcImpOpBase + 9, 182, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #691 = STCSRrr { 690, 2, 0, 4, 19, 1, 0, SparcImpOpBase + 9, 35, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #690 = STCSRri { 689, 3, 0, 4, 19, 0, 0, SparcImpOpBase + 0, 416, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #689 = STBrr { 688, 3, 0, 4, 19, 0, 0, SparcImpOpBase + 0, 409, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #688 = STBri { 687, 4, 0, 4, 19, 0, 0, SparcImpOpBase + 0, 412, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #687 = STBArr { 686, 3, 0, 4, 19, 1, 0, SparcImpOpBase + 8, 409, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #686 = STBAri { 685, 0, 0, 4, 1, 0, 0, SparcImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #685 = STBAR { 684, 4, 0, 4, 19, 0, 0, SparcImpOpBase + 0, 412, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #684 = STArr { 683, 3, 0, 4, 19, 1, 0, SparcImpOpBase + 8, 409, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #683 = STAri { 682, 3, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 176, 0, 0x0ULL }, // Inst #682 = SRLrr { 681, 3, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 398, 0, 0x0ULL }, // Inst #681 = SRLri { 680, 3, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 395, 0, 0x0ULL }, // Inst #680 = SRLXrr { 679, 3, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 392, 0, 0x0ULL }, // Inst #679 = SRLXri { 678, 3, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 176, 0, 0x0ULL }, // Inst #678 = SRArr { 677, 3, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 398, 0, 0x0ULL }, // Inst #677 = SRAri { 676, 3, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 395, 0, 0x0ULL }, // Inst #676 = SRAXrr { 675, 3, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 392, 0, 0x0ULL }, // Inst #675 = SRAXri { 674, 3, 1, 4, 18, 0, 1, SparcImpOpBase + 30, 176, 0, 0x0ULL }, // Inst #674 = SMULrr { 673, 3, 1, 4, 18, 0, 1, SparcImpOpBase + 30, 173, 0, 0x0ULL }, // Inst #673 = SMULri { 672, 3, 1, 4, 18, 0, 2, SparcImpOpBase + 28, 176, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #672 = SMULCCrr { 671, 3, 1, 4, 18, 0, 2, SparcImpOpBase + 28, 173, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #671 = SMULCCri { 670, 4, 1, 4, 17, 2, 2, SparcImpOpBase + 24, 405, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #670 = SMACrr { 669, 4, 1, 4, 17, 2, 2, SparcImpOpBase + 24, 401, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #669 = SMACri { 668, 3, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 176, 0, 0x0ULL }, // Inst #668 = SLLrr { 667, 3, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 398, 0, 0x0ULL }, // Inst #667 = SLLri { 666, 3, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 395, 0, 0x0ULL }, // Inst #666 = SLLXrr { 665, 3, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 392, 0, 0x0ULL }, // Inst #665 = SLLXri { 664, 1, 0, 4, 1, 0, 0, SparcImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #664 = SIR { 663, 0, 0, 4, 0, 0, 0, SparcImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #663 = SIAM { 662, 0, 0, 4, 0, 0, 0, SparcImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #662 = SHUTDOWN { 661, 2, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 168, 0, 0x0ULL }, // Inst #661 = SETHIi { 660, 3, 1, 4, 16, 1, 1, SparcImpOpBase + 22, 176, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #660 = SDIVrr { 659, 3, 1, 4, 16, 1, 1, SparcImpOpBase + 22, 173, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #659 = SDIVri { 658, 3, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 179, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #658 = SDIVXrr { 657, 3, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 173, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #657 = SDIVXri { 656, 3, 1, 4, 16, 1, 2, SparcImpOpBase + 19, 176, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #656 = SDIVCCrr { 655, 3, 1, 4, 16, 1, 2, SparcImpOpBase + 19, 173, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #655 = SDIVCCri { 654, 3, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 176, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #654 = SAVErr { 653, 3, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 173, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #653 = SAVEri { 652, 0, 0, 4, 1, 0, 0, SparcImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #652 = SAVED { 651, 2, 0, 4, 3, 0, 0, SparcImpOpBase + 0, 182, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #651 = RETTrr { 650, 2, 0, 4, 3, 0, 0, SparcImpOpBase + 0, 35, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #650 = RETTri { 649, 0, 0, 4, 1, 0, 0, SparcImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #649 = RETRY { 648, 1, 0, 4, 3, 0, 0, SparcImpOpBase + 0, 1, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #648 = RETL { 647, 1, 0, 4, 3, 0, 0, SparcImpOpBase + 0, 1, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #647 = RET { 646, 3, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 176, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #646 = RESTORErr { 645, 3, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 173, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #645 = RESTOREri { 644, 0, 0, 4, 1, 0, 0, SparcImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #644 = RESTORED { 643, 1, 1, 4, 1, 1, 0, SparcImpOpBase + 18, 389, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #643 = RDWIM { 642, 1, 1, 4, 1, 1, 0, SparcImpOpBase + 17, 389, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #642 = RDTBR { 641, 1, 1, 4, 1, 1, 0, SparcImpOpBase + 15, 389, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #641 = RDPSR { 640, 2, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 390, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #640 = RDPR { 639, 1, 1, 4, 1, 1, 0, SparcImpOpBase + 16, 389, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #639 = RDFQ { 638, 2, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 387, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #638 = RDASR { 637, 2, 0, 4, 1, 0, 1, SparcImpOpBase + 15, 375, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #637 = PWRPSRrr { 636, 2, 0, 4, 1, 0, 1, SparcImpOpBase + 15, 168, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #636 = PWRPSRri { 635, 3, 0, 4, 1, 0, 0, SparcImpOpBase + 0, 384, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #635 = PREFETCHr { 634, 3, 0, 4, 1, 0, 0, SparcImpOpBase + 0, 377, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #634 = PREFETCHi { 633, 4, 0, 4, 0, 0, 0, SparcImpOpBase + 0, 380, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #633 = PREFETCHAr { 632, 3, 0, 4, 1, 1, 0, SparcImpOpBase + 8, 377, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #632 = PREFETCHAi { 631, 2, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 375, 0, 0x0ULL }, // Inst #631 = POPCrr { 630, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 190, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #630 = PDISTN { 629, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 190, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #629 = PDIST { 628, 3, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 176, 0, 0x0ULL }, // Inst #628 = ORrr { 627, 3, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 173, 0, 0x0ULL }, // Inst #627 = ORri { 626, 3, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 176, 0, 0x0ULL }, // Inst #626 = ORNrr { 625, 3, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 173, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #625 = ORNri { 624, 3, 1, 4, 1, 0, 1, SparcImpOpBase + 4, 176, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #624 = ORNCCrr { 623, 3, 1, 4, 1, 0, 1, SparcImpOpBase + 4, 173, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #623 = ORNCCri { 622, 3, 1, 4, 1, 0, 1, SparcImpOpBase + 4, 176, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #622 = ORCCrr { 621, 3, 1, 4, 1, 0, 1, SparcImpOpBase + 4, 173, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #621 = ORCCri { 620, 0, 0, 4, 0, 0, 0, SparcImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #620 = NOP { 619, 3, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 179, 0, 0x0ULL }, // Inst #619 = MULXrr { 618, 3, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 173, 0, 0x0ULL }, // Inst #618 = MULXri { 617, 3, 1, 4, 1, 2, 2, SparcImpOpBase + 11, 176, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #617 = MULSCCrr { 616, 3, 1, 4, 1, 2, 2, SparcImpOpBase + 11, 173, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #616 = MULSCCri { 615, 2, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 373, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #615 = MOVXTOD { 614, 4, 1, 4, 0, 1, 0, SparcImpOpBase + 4, 359, 0, 0x0ULL }, // Inst #614 = MOVXCCrr { 613, 4, 1, 4, 0, 1, 0, SparcImpOpBase + 4, 355, 0, 0x0ULL }, // Inst #613 = MOVXCCri { 612, 2, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 373, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #612 = MOVWTOS { 611, 2, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 353, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #611 = MOVSTOUW { 610, 2, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 353, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #610 = MOVSTOSW { 609, 5, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 368, 0, 0x0ULL }, // Inst #609 = MOVRrr { 608, 5, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 363, 0, 0x0ULL }, // Inst #608 = MOVRri { 607, 4, 1, 4, 0, 1, 0, SparcImpOpBase + 4, 359, 0, 0x0ULL }, // Inst #607 = MOVICCrr { 606, 4, 1, 4, 0, 1, 0, SparcImpOpBase + 4, 355, 0, 0x0ULL }, // Inst #606 = MOVICCri { 605, 4, 1, 4, 0, 1, 0, SparcImpOpBase + 3, 359, 0, 0x0ULL }, // Inst #605 = MOVFCCrr { 604, 4, 1, 4, 0, 1, 0, SparcImpOpBase + 3, 355, 0, 0x0ULL }, // Inst #604 = MOVFCCri { 603, 2, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 353, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #603 = MOVDTOX { 602, 1, 0, 4, 1, 0, 0, SparcImpOpBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #602 = MEMBARi { 601, 2, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 351, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #601 = LZCNT { 600, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 290, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #600 = LDrr { 599, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 287, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #599 = LDri { 598, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 348, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #598 = LDXrr { 597, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 345, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #597 = LDXri { 596, 2, 0, 4, 1, 0, 1, SparcImpOpBase + 10, 182, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #596 = LDXFSRrr { 595, 2, 0, 4, 1, 0, 1, SparcImpOpBase + 10, 35, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #595 = LDXFSRri { 594, 4, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 279, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #594 = LDXArr { 593, 3, 1, 4, 1, 1, 0, SparcImpOpBase + 8, 345, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #593 = LDXAri { 592, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 290, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #592 = LDUHrr { 591, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 287, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #591 = LDUHri { 590, 4, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 283, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #590 = LDUHArr { 589, 3, 1, 4, 1, 1, 0, SparcImpOpBase + 8, 287, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #589 = LDUHAri { 588, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 290, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #588 = LDUBrr { 587, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 287, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #587 = LDUBri { 586, 4, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 283, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #586 = LDUBArr { 585, 3, 1, 4, 1, 1, 0, SparcImpOpBase + 8, 287, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #585 = LDUBAri { 584, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 348, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #584 = LDSWrr { 583, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 345, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #583 = LDSWri { 582, 4, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 279, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #582 = LDSWArr { 581, 3, 1, 4, 1, 1, 0, SparcImpOpBase + 8, 345, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #581 = LDSWAri { 580, 3, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 290, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #580 = LDSTUBrr { 579, 3, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 287, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #579 = LDSTUBri { 578, 4, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 283, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #578 = LDSTUBArr { 577, 3, 1, 4, 1, 1, 0, SparcImpOpBase + 8, 287, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #577 = LDSTUBAri { 576, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 290, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #576 = LDSHrr { 575, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 287, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #575 = LDSHri { 574, 4, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 283, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #574 = LDSHArr { 573, 3, 1, 4, 1, 1, 0, SparcImpOpBase + 8, 287, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #573 = LDSHAri { 572, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 290, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #572 = LDSBrr { 571, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 287, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #571 = LDSBri { 570, 4, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 283, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #570 = LDSBArr { 569, 3, 1, 4, 1, 1, 0, SparcImpOpBase + 8, 287, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #569 = LDSBAri { 568, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 342, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #568 = LDQFrr { 567, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 335, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #567 = LDQFri { 566, 4, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 338, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #566 = LDQFArr { 565, 3, 1, 4, 1, 1, 0, SparcImpOpBase + 8, 335, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #565 = LDQFAri { 564, 3, 1, 4, 15, 0, 0, SparcImpOpBase + 0, 332, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #564 = LDFrr { 563, 3, 1, 4, 15, 0, 0, SparcImpOpBase + 0, 325, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #563 = LDFri { 562, 2, 0, 4, 15, 0, 1, SparcImpOpBase + 10, 182, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #562 = LDFSRrr { 561, 2, 0, 4, 15, 0, 1, SparcImpOpBase + 10, 35, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #561 = LDFSRri { 560, 4, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 328, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #560 = LDFArr { 559, 3, 1, 4, 1, 1, 0, SparcImpOpBase + 8, 325, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #559 = LDFAri { 558, 3, 1, 4, 14, 0, 0, SparcImpOpBase + 0, 322, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #558 = LDDrr { 557, 3, 1, 4, 14, 0, 0, SparcImpOpBase + 0, 299, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #557 = LDDri { 556, 3, 1, 4, 14, 0, 0, SparcImpOpBase + 0, 319, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #556 = LDDFrr { 555, 3, 1, 4, 14, 0, 0, SparcImpOpBase + 0, 312, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #555 = LDDFri { 554, 4, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 315, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #554 = LDDFArr { 553, 3, 1, 4, 1, 1, 0, SparcImpOpBase + 8, 312, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #553 = LDDFAri { 552, 3, 1, 4, 14, 0, 0, SparcImpOpBase + 0, 309, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #552 = LDDCrr { 551, 3, 1, 4, 14, 0, 0, SparcImpOpBase + 0, 306, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #551 = LDDCri { 550, 4, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 302, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #550 = LDDArr { 549, 3, 1, 4, 1, 1, 0, SparcImpOpBase + 8, 299, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #549 = LDDAri { 548, 3, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 296, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #548 = LDCrr { 547, 3, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 293, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #547 = LDCri { 546, 2, 0, 4, 1, 0, 1, SparcImpOpBase + 9, 182, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #546 = LDCSRrr { 545, 2, 0, 4, 1, 0, 1, SparcImpOpBase + 9, 35, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #545 = LDCSRri { 544, 4, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 283, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #544 = LDArr { 543, 3, 1, 4, 1, 1, 0, SparcImpOpBase + 8, 287, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #543 = LDAri { 542, 3, 1, 4, 3, 0, 0, SparcImpOpBase + 0, 290, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #542 = JMPLrr { 541, 3, 1, 4, 3, 0, 0, SparcImpOpBase + 0, 287, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #541 = JMPLri { 540, 4, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 283, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #540 = GDOP_LDrr { 539, 4, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 279, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #539 = GDOP_LDXrr { 538, 2, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 270, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #538 = FZEROS { 537, 2, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 268, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #537 = FZERO { 536, 2, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 230, 0, 0x0ULL }, // Inst #536 = FXTOS { 535, 2, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 232, 0, 0x0ULL }, // Inst #535 = FXTOQ { 534, 2, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 212, 0, 0x0ULL }, // Inst #534 = FXTOD { 533, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 221, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #533 = FXORS { 532, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 190, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #532 = FXOR { 531, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 221, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #531 = FXNORS { 530, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 190, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #530 = FXNOR { 529, 3, 1, 4, 5, 0, 0, SparcImpOpBase + 0, 221, 0, 0x0ULL }, // Inst #529 = FSUBS { 528, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 218, 0, 0x0ULL }, // Inst #528 = FSUBQ { 527, 3, 1, 4, 5, 0, 0, SparcImpOpBase + 0, 190, 0, 0x0ULL }, // Inst #527 = FSUBD { 526, 2, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 234, 0, 0x0ULL }, // Inst #526 = FSTOX { 525, 2, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 236, 0, 0x0ULL }, // Inst #525 = FSTOQ { 524, 2, 1, 4, 5, 0, 0, SparcImpOpBase + 0, 216, 0, 0x0ULL }, // Inst #524 = FSTOI { 523, 2, 1, 4, 13, 0, 0, SparcImpOpBase + 0, 234, 0, 0x0ULL }, // Inst #523 = FSTOD { 522, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 190, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #522 = FSRL32 { 521, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 190, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #521 = FSRL16 { 520, 2, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 216, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #520 = FSRC2S { 519, 2, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 212, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #519 = FSRC2 { 518, 2, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 216, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #518 = FSRC1S { 517, 2, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 212, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #517 = FSRC1 { 516, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 190, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #516 = FSRA32 { 515, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 190, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #515 = FSRA16 { 514, 2, 1, 4, 12, 0, 0, SparcImpOpBase + 0, 216, 0, 0x0ULL }, // Inst #514 = FSQRTS { 513, 2, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 214, 0, 0x0ULL }, // Inst #513 = FSQRTQ { 512, 2, 1, 4, 11, 0, 0, SparcImpOpBase + 0, 212, 0, 0x0ULL }, // Inst #512 = FSQRTD { 511, 3, 1, 4, 8, 0, 0, SparcImpOpBase + 0, 276, 0, 0x0ULL }, // Inst #511 = FSMULD { 510, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 190, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #510 = FSLL32 { 509, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 190, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #509 = FSLL16 { 508, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 190, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #508 = FSLAS32 { 507, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 190, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #507 = FSLAS16 { 506, 2, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 272, 0, 0x0ULL }, // Inst #506 = FQTOX { 505, 2, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 274, 0, 0x0ULL }, // Inst #505 = FQTOS { 504, 2, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 274, 0, 0x0ULL }, // Inst #504 = FQTOI { 503, 2, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 272, 0, 0x0ULL }, // Inst #503 = FQTOD { 502, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 190, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #502 = FPSUB32S { 501, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 190, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #501 = FPSUB32 { 500, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 190, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #500 = FPSUB16S { 499, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 190, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #499 = FPSUB16 { 498, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 190, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #498 = FPMERGE { 497, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 190, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #497 = FPADD64 { 496, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 190, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #496 = FPADD32S { 495, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 190, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #495 = FPADD32 { 494, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 190, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #494 = FPADD16S { 493, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 190, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #493 = FPADD16 { 492, 2, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 212, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #492 = FPACKFIX { 491, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 190, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #491 = FPACK32 { 490, 2, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 212, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #490 = FPACK16 { 489, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 221, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #489 = FORS { 488, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 221, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #488 = FORNOT2S { 487, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 190, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #487 = FORNOT2 { 486, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 221, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #486 = FORNOT1S { 485, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 190, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #485 = FORNOT1 { 484, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 190, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #484 = FOR { 483, 2, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 270, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #483 = FONES { 482, 2, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 268, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #482 = FONE { 481, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 190, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #481 = FNSMULD { 480, 2, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 216, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #480 = FNOT2S { 479, 2, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 212, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #479 = FNOT2 { 478, 2, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 216, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #478 = FNOT1S { 477, 2, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 212, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #477 = FNOT1 { 476, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 221, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #476 = FNORS { 475, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 190, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #475 = FNOR { 474, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 190, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #474 = FNMULS { 473, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 190, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #473 = FNMULD { 472, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 190, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #472 = FNHADDS { 471, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 190, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #471 = FNHADDD { 470, 2, 1, 4, 10, 0, 0, SparcImpOpBase + 0, 216, 0, 0x0ULL }, // Inst #470 = FNEGS { 469, 2, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 214, 0, 0x0ULL }, // Inst #469 = FNEGQ { 468, 2, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 212, 0, 0x0ULL }, // Inst #468 = FNEGD { 467, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 221, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #467 = FNANDS { 466, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 190, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #466 = FNAND { 465, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 190, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #465 = FNADDS { 464, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 190, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #464 = FNADDD { 463, 3, 1, 4, 9, 0, 0, SparcImpOpBase + 0, 221, 0, 0x0ULL }, // Inst #463 = FMULS { 462, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 218, 0, 0x0ULL }, // Inst #462 = FMULQ { 461, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 190, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #461 = FMULD8ULX16 { 460, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 190, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #460 = FMULD8SUX16 { 459, 3, 1, 4, 8, 0, 0, SparcImpOpBase + 0, 190, 0, 0x0ULL }, // Inst #459 = FMULD { 458, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 190, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #458 = FMUL8X16AU { 457, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 190, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #457 = FMUL8X16AL { 456, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 190, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #456 = FMUL8X16 { 455, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 190, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #455 = FMUL8ULX16 { 454, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 190, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #454 = FMUL8SUX16 { 453, 4, 1, 4, 0, 1, 0, SparcImpOpBase + 4, 264, 0, 0x0ULL }, // Inst #453 = FMOVS_XCC { 452, 4, 1, 4, 0, 1, 0, SparcImpOpBase + 4, 264, 0, 0x0ULL }, // Inst #452 = FMOVS_ICC { 451, 4, 1, 4, 0, 1, 0, SparcImpOpBase + 3, 264, 0, 0x0ULL }, // Inst #451 = FMOVS_FCC { 450, 2, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 216, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #450 = FMOVS { 449, 5, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 259, 0, 0x0ULL }, // Inst #449 = FMOVRS { 448, 5, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 254, 0, 0x0ULL }, // Inst #448 = FMOVRQ { 447, 5, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 249, 0, 0x0ULL }, // Inst #447 = FMOVRD { 446, 4, 1, 4, 0, 1, 0, SparcImpOpBase + 4, 245, 0, 0x0ULL }, // Inst #446 = FMOVQ_XCC { 445, 4, 1, 4, 0, 1, 0, SparcImpOpBase + 4, 245, 0, 0x0ULL }, // Inst #445 = FMOVQ_ICC { 444, 4, 1, 4, 0, 1, 0, SparcImpOpBase + 3, 245, 0, 0x0ULL }, // Inst #444 = FMOVQ_FCC { 443, 2, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 214, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #443 = FMOVQ { 442, 4, 1, 4, 0, 1, 0, SparcImpOpBase + 4, 241, 0, 0x0ULL }, // Inst #442 = FMOVD_XCC { 441, 4, 1, 4, 0, 1, 0, SparcImpOpBase + 4, 241, 0, 0x0ULL }, // Inst #441 = FMOVD_ICC { 440, 4, 1, 4, 0, 1, 0, SparcImpOpBase + 3, 241, 0, 0x0ULL }, // Inst #440 = FMOVD_FCC { 439, 2, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 212, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #439 = FMOVD { 438, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 190, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #438 = FMEAN16 { 437, 2, 0, 4, 1, 0, 0, SparcImpOpBase + 0, 182, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #437 = FLUSHrr { 436, 2, 0, 4, 1, 0, 0, SparcImpOpBase + 0, 35, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #436 = FLUSHri { 435, 0, 0, 4, 1, 0, 0, SparcImpOpBase + 0, 1, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #435 = FLUSHW { 434, 0, 0, 4, 1, 0, 0, SparcImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #434 = FLUSH { 433, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 238, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #433 = FLCMPS { 432, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 238, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #432 = FLCMPD { 431, 2, 1, 4, 5, 0, 0, SparcImpOpBase + 0, 216, 0, 0x0ULL }, // Inst #431 = FITOS { 430, 2, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 236, 0, 0x0ULL }, // Inst #430 = FITOQ { 429, 2, 1, 4, 5, 0, 0, SparcImpOpBase + 0, 234, 0, 0x0ULL }, // Inst #429 = FITOD { 428, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 190, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #428 = FHSUBS { 427, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 190, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #427 = FHSUBD { 426, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 190, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #426 = FHADDS { 425, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 190, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #425 = FHADDD { 424, 2, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 212, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #424 = FEXPAND { 423, 2, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 212, 0, 0x0ULL }, // Inst #423 = FDTOX { 422, 2, 1, 4, 5, 0, 0, SparcImpOpBase + 0, 230, 0, 0x0ULL }, // Inst #422 = FDTOS { 421, 2, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 232, 0, 0x0ULL }, // Inst #421 = FDTOQ { 420, 2, 1, 4, 5, 0, 0, SparcImpOpBase + 0, 230, 0, 0x0ULL }, // Inst #420 = FDTOI { 419, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 227, 0, 0x0ULL }, // Inst #419 = FDMULQ { 418, 3, 1, 4, 7, 0, 0, SparcImpOpBase + 0, 221, 0, 0x0ULL }, // Inst #418 = FDIVS { 417, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 218, 0, 0x0ULL }, // Inst #417 = FDIVQ { 416, 3, 1, 4, 6, 0, 0, SparcImpOpBase + 0, 190, 0, 0x0ULL }, // Inst #416 = FDIVD { 415, 2, 0, 4, 5, 0, 1, SparcImpOpBase + 3, 216, 0, 0x0ULL }, // Inst #415 = FCMPS_V9 { 414, 2, 0, 4, 5, 0, 1, SparcImpOpBase + 3, 216, 0, 0x0ULL }, // Inst #414 = FCMPS { 413, 2, 0, 4, 0, 0, 1, SparcImpOpBase + 3, 214, 0, 0x0ULL }, // Inst #413 = FCMPQ_V9 { 412, 2, 0, 4, 0, 0, 1, SparcImpOpBase + 3, 214, 0, 0x0ULL }, // Inst #412 = FCMPQ { 411, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 224, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #411 = FCMPNE32 { 410, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 224, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #410 = FCMPNE16 { 409, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 224, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #409 = FCMPLE32 { 408, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 224, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #408 = FCMPLE16 { 407, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 224, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #407 = FCMPGT32 { 406, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 224, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #406 = FCMPGT16 { 405, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 224, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #405 = FCMPEQ32 { 404, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 224, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #404 = FCMPEQ16 { 403, 2, 0, 4, 5, 0, 1, SparcImpOpBase + 3, 212, 0, 0x0ULL }, // Inst #403 = FCMPD_V9 { 402, 2, 0, 4, 5, 0, 1, SparcImpOpBase + 3, 212, 0, 0x0ULL }, // Inst #402 = FCMPD { 401, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 190, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #401 = FCHKSM16 { 400, 2, 0, 4, 2, 1, 0, SparcImpOpBase + 3, 13, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #400 = FBCOND_V9 { 399, 2, 0, 4, 2, 1, 0, SparcImpOpBase + 3, 13, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #399 = FBCONDA_V9 { 398, 2, 0, 4, 2, 1, 0, SparcImpOpBase + 3, 13, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #398 = FBCONDA { 397, 2, 0, 4, 2, 1, 0, SparcImpOpBase + 3, 13, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #397 = FBCOND { 396, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 221, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #396 = FANDS { 395, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 221, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #395 = FANDNOT2S { 394, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 190, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #394 = FANDNOT2 { 393, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 221, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #393 = FANDNOT1S { 392, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 190, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #392 = FANDNOT1 { 391, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 190, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #391 = FAND { 390, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 190, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #390 = FALIGNADATA { 389, 3, 1, 4, 5, 0, 0, SparcImpOpBase + 0, 221, 0, 0x0ULL }, // Inst #389 = FADDS { 388, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 218, 0, 0x0ULL }, // Inst #388 = FADDQ { 387, 3, 1, 4, 5, 0, 0, SparcImpOpBase + 0, 190, 0, 0x0ULL }, // Inst #387 = FADDD { 386, 2, 1, 4, 4, 0, 0, SparcImpOpBase + 0, 216, 0, 0x0ULL }, // Inst #386 = FABSS { 385, 2, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 214, 0, 0x0ULL }, // Inst #385 = FABSQ { 384, 2, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 212, 0, 0x0ULL }, // Inst #384 = FABSD { 383, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 179, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #383 = EDGE8N { 382, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 179, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #382 = EDGE8LN { 381, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 179, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #381 = EDGE8L { 380, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 179, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #380 = EDGE8 { 379, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 179, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #379 = EDGE32N { 378, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 179, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #378 = EDGE32LN { 377, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 179, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #377 = EDGE32L { 376, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 179, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #376 = EDGE32 { 375, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 179, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #375 = EDGE16N { 374, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 179, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #374 = EDGE16LN { 373, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 179, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #373 = EDGE16L { 372, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 179, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #372 = EDGE16 { 371, 0, 0, 4, 1, 0, 0, SparcImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #371 = DONE { 370, 1, 0, 4, 0, 0, 0, SparcImpOpBase + 0, 211, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #370 = CMASK8 { 369, 1, 0, 4, 0, 0, 0, SparcImpOpBase + 0, 211, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #369 = CMASK32 { 368, 1, 0, 4, 0, 0, 0, SparcImpOpBase + 0, 211, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #368 = CMASK16 { 367, 2, 0, 4, 0, 0, 0, SparcImpOpBase + 0, 13, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #367 = CBCONDA { 366, 2, 0, 4, 0, 0, 0, SparcImpOpBase + 0, 13, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #366 = CBCOND { 365, 5, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 206, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #365 = CASXArr { 364, 4, 1, 4, 0, 1, 0, SparcImpOpBase + 8, 202, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #364 = CASXAri { 363, 5, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 197, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #363 = CASArr { 362, 4, 1, 4, 0, 1, 0, SparcImpOpBase + 8, 193, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #362 = CASAri { 361, 2, 0, 4, 3, 1, 0, SparcImpOpBase + 7, 182, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #361 = CALLrr { 360, 2, 0, 4, 3, 1, 0, SparcImpOpBase + 7, 35, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #360 = CALLri { 359, 1, 0, 4, 3, 1, 0, SparcImpOpBase + 7, 0, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #359 = CALL { 358, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 190, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #358 = BSHUFFLE { 357, 2, 0, 4, 1, 1, 0, SparcImpOpBase + 4, 13, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #357 = BPXCCNT { 356, 2, 0, 4, 1, 1, 0, SparcImpOpBase + 4, 13, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #356 = BPXCCANT { 355, 2, 0, 4, 1, 1, 0, SparcImpOpBase + 4, 13, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #355 = BPXCCA { 354, 2, 0, 4, 1, 1, 0, SparcImpOpBase + 4, 13, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #354 = BPXCC { 353, 3, 0, 4, 0, 0, 0, SparcImpOpBase + 0, 187, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #353 = BPRNT { 352, 3, 0, 4, 0, 0, 0, SparcImpOpBase + 0, 187, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #352 = BPRANT { 351, 3, 0, 4, 0, 0, 0, SparcImpOpBase + 0, 187, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #351 = BPRA { 350, 3, 0, 4, 0, 0, 0, SparcImpOpBase + 0, 187, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #350 = BPR { 349, 2, 0, 4, 1, 1, 0, SparcImpOpBase + 4, 13, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #349 = BPICCNT { 348, 2, 0, 4, 1, 1, 0, SparcImpOpBase + 4, 13, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #348 = BPICCANT { 347, 2, 0, 4, 1, 1, 0, SparcImpOpBase + 4, 13, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #347 = BPICCA { 346, 2, 0, 4, 1, 1, 0, SparcImpOpBase + 4, 13, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #346 = BPICC { 345, 3, 0, 4, 2, 0, 0, SparcImpOpBase + 0, 184, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #345 = BPFCCNT { 344, 3, 0, 4, 2, 0, 0, SparcImpOpBase + 0, 184, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #344 = BPFCCANT { 343, 3, 0, 4, 2, 0, 0, SparcImpOpBase + 0, 184, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #343 = BPFCCA { 342, 3, 0, 4, 2, 0, 0, SparcImpOpBase + 0, 184, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #342 = BPFCC { 341, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 179, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #341 = BMASK { 340, 2, 0, 4, 1, 0, 0, SparcImpOpBase + 0, 182, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #340 = BINDrr { 339, 2, 0, 4, 1, 0, 0, SparcImpOpBase + 0, 35, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #339 = BINDri { 338, 2, 0, 4, 1, 1, 0, SparcImpOpBase + 4, 13, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #338 = BCONDA { 337, 2, 0, 4, 1, 1, 0, SparcImpOpBase + 4, 13, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #337 = BCOND { 336, 1, 0, 4, 0, 0, 0, SparcImpOpBase + 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #336 = BA { 335, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 179, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #335 = ARRAY8 { 334, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 179, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #334 = ARRAY32 { 333, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 179, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #333 = ARRAY16 { 332, 3, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 176, 0, 0x0ULL }, // Inst #332 = ANDrr { 331, 3, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 173, 0, 0x0ULL }, // Inst #331 = ANDri { 330, 3, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 176, 0, 0x0ULL }, // Inst #330 = ANDNrr { 329, 3, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 173, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #329 = ANDNri { 328, 3, 1, 4, 1, 0, 1, SparcImpOpBase + 4, 176, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #328 = ANDNCCrr { 327, 3, 1, 4, 1, 0, 1, SparcImpOpBase + 4, 173, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #327 = ANDNCCri { 326, 3, 1, 4, 1, 0, 1, SparcImpOpBase + 4, 176, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #326 = ANDCCrr { 325, 3, 1, 4, 1, 0, 1, SparcImpOpBase + 4, 173, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #325 = ANDCCri { 324, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 179, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #324 = ALIGNADDRL { 323, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 179, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #323 = ALIGNADDR { 322, 3, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 176, 0, 0x0ULL }, // Inst #322 = ADDrr { 321, 3, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 173, 0, 0x0ULL }, // Inst #321 = ADDri { 320, 3, 1, 4, 0, 1, 1, SparcImpOpBase + 5, 179, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #320 = ADDXCCC { 319, 3, 1, 4, 0, 1, 0, SparcImpOpBase + 4, 179, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #319 = ADDXC { 318, 3, 1, 4, 1, 1, 1, SparcImpOpBase + 5, 176, 0, 0x0ULL }, // Inst #318 = ADDErr { 317, 3, 1, 4, 1, 1, 1, SparcImpOpBase + 5, 173, 0, 0x0ULL }, // Inst #317 = ADDEri { 316, 3, 1, 4, 1, 1, 0, SparcImpOpBase + 4, 176, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #316 = ADDCrr { 315, 3, 1, 4, 1, 1, 0, SparcImpOpBase + 4, 173, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #315 = ADDCri { 314, 3, 1, 4, 1, 0, 1, SparcImpOpBase + 4, 176, 0, 0x0ULL }, // Inst #314 = ADDCCrr { 313, 3, 1, 4, 1, 0, 1, SparcImpOpBase + 4, 173, 0, 0x0ULL }, // Inst #313 = ADDCCri { 312, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 170, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #312 = SETX { 311, 2, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 168, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #311 = SET { 310, 4, 1, 4, 0, 1, 0, SparcImpOpBase + 4, 164, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #310 = SELECT_CC_QFP_XCC { 309, 4, 1, 4, 0, 1, 0, SparcImpOpBase + 4, 164, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #309 = SELECT_CC_QFP_ICC { 308, 4, 1, 4, 0, 1, 0, SparcImpOpBase + 3, 164, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #308 = SELECT_CC_QFP_FCC { 307, 4, 1, 4, 0, 1, 0, SparcImpOpBase + 4, 160, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #307 = SELECT_CC_Int_XCC { 306, 4, 1, 4, 0, 1, 0, SparcImpOpBase + 4, 160, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #306 = SELECT_CC_Int_ICC { 305, 4, 1, 4, 0, 1, 0, SparcImpOpBase + 3, 160, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #305 = SELECT_CC_Int_FCC { 304, 4, 1, 4, 0, 1, 0, SparcImpOpBase + 4, 156, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #304 = SELECT_CC_FP_XCC { 303, 4, 1, 4, 0, 1, 0, SparcImpOpBase + 4, 156, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #303 = SELECT_CC_FP_ICC { 302, 4, 1, 4, 0, 1, 0, SparcImpOpBase + 3, 156, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #302 = SELECT_CC_FP_FCC { 301, 4, 1, 4, 0, 1, 0, SparcImpOpBase + 4, 152, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #301 = SELECT_CC_DFP_XCC { 300, 4, 1, 4, 0, 1, 0, SparcImpOpBase + 4, 152, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #300 = SELECT_CC_DFP_ICC { 299, 4, 1, 4, 0, 1, 0, SparcImpOpBase + 3, 152, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #299 = SELECT_CC_DFP_FCC { 298, 1, 1, 4, 0, 0, 1, SparcImpOpBase + 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #298 = GETPCX { 297, 2, 0, 4, 0, 1, 1, SparcImpOpBase + 0, 21, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #297 = ADJCALLSTACKUP { 296, 2, 0, 4, 0, 1, 1, SparcImpOpBase + 0, 21, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #296 = ADJCALLSTACKDOWN { 295, 4, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 148, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #295 = G_UBFX { 294, 4, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 148, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #294 = G_SBFX { 293, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #293 = G_VECREDUCE_UMIN { 292, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #292 = G_VECREDUCE_UMAX { 291, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #291 = G_VECREDUCE_SMIN { 290, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #290 = G_VECREDUCE_SMAX { 289, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #289 = G_VECREDUCE_XOR { 288, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #288 = G_VECREDUCE_OR { 287, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #287 = G_VECREDUCE_AND { 286, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #286 = G_VECREDUCE_MUL { 285, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #285 = G_VECREDUCE_ADD { 284, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #284 = G_VECREDUCE_FMINIMUM { 283, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #283 = G_VECREDUCE_FMAXIMUM { 282, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #282 = G_VECREDUCE_FMIN { 281, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #281 = G_VECREDUCE_FMAX { 280, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #280 = G_VECREDUCE_FMUL { 279, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #279 = G_VECREDUCE_FADD { 278, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 131, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #278 = G_VECREDUCE_SEQ_FMUL { 277, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 131, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #277 = G_VECREDUCE_SEQ_FADD { 276, 1, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 1, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #276 = G_UBSANTRAP { 275, 0, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 1, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #275 = G_DEBUGTRAP { 274, 0, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 1, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #274 = G_TRAP { 273, 3, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 58, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #273 = G_BZERO { 272, 4, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 144, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #272 = G_MEMSET { 271, 4, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 144, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #271 = G_MEMMOVE { 270, 3, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 131, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #270 = G_MEMCPY_INLINE { 269, 4, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 144, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #269 = G_MEMCPY { 268, 2, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 142, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #268 = G_WRITE_REGISTER { 267, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #267 = G_READ_REGISTER { 266, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #266 = G_STRICT_FLDEXP { 265, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #265 = G_STRICT_FSQRT { 264, 4, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 46, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #264 = G_STRICT_FMA { 263, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #263 = G_STRICT_FREM { 262, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #262 = G_STRICT_FDIV { 261, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #261 = G_STRICT_FMUL { 260, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #260 = G_STRICT_FSUB { 259, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #259 = G_STRICT_FADD { 258, 1, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #258 = G_STACKRESTORE { 257, 1, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #257 = G_STACKSAVE { 256, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 69, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #256 = G_DYN_STACKALLOC { 255, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #255 = G_JUMP_TABLE { 254, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #254 = G_BLOCK_ADDR { 253, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #253 = G_ADDRSPACE_CAST { 252, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #252 = G_FNEARBYINT { 251, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #251 = G_FRINT { 250, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #250 = G_FFLOOR { 249, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #249 = G_FSQRT { 248, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #248 = G_FTANH { 247, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #247 = G_FSINH { 246, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #246 = G_FCOSH { 245, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #245 = G_FATAN { 244, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #244 = G_FASIN { 243, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #243 = G_FACOS { 242, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #242 = G_FTAN { 241, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #241 = G_FSIN { 240, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #240 = G_FCOS { 239, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #239 = G_FCEIL { 238, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #238 = G_BITREVERSE { 237, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #237 = G_BSWAP { 236, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #236 = G_CTPOP { 235, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #235 = G_CTLZ_ZERO_UNDEF { 234, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #234 = G_CTLZ { 233, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #233 = G_CTTZ_ZERO_UNDEF { 232, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #232 = G_CTTZ { 231, 4, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 138, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #231 = G_VECTOR_COMPRESS { 230, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #230 = G_SPLAT_VECTOR { 229, 4, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 134, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #229 = G_SHUFFLE_VECTOR { 228, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 131, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #228 = G_EXTRACT_VECTOR_ELT { 227, 4, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 127, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #227 = G_INSERT_VECTOR_ELT { 226, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 40, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #226 = G_EXTRACT_SUBVECTOR { 225, 4, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 63, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #225 = G_INSERT_SUBVECTOR { 224, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #224 = G_VSCALE { 223, 3, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 124, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #223 = G_BRJT { 222, 1, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #222 = G_BR { 221, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #221 = G_LLROUND { 220, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #220 = G_LROUND { 219, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #219 = G_ABS { 218, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #218 = G_UMAX { 217, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #217 = G_UMIN { 216, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #216 = G_SMAX { 215, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #215 = G_SMIN { 214, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #214 = G_PTRMASK { 213, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #213 = G_PTR_ADD { 212, 0, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 1, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #212 = G_RESET_FPMODE { 211, 1, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #211 = G_SET_FPMODE { 210, 1, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #210 = G_GET_FPMODE { 209, 0, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 1, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #209 = G_RESET_FPENV { 208, 1, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #208 = G_SET_FPENV { 207, 1, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #207 = G_GET_FPENV { 206, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #206 = G_FMAXIMUM { 205, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #205 = G_FMINIMUM { 204, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #204 = G_FMAXNUM_IEEE { 203, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #203 = G_FMINNUM_IEEE { 202, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #202 = G_FMAXNUM { 201, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #201 = G_FMINNUM { 200, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #200 = G_FCANONICALIZE { 199, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 98, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #199 = G_IS_FPCLASS { 198, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #198 = G_FCOPYSIGN { 197, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #197 = G_FABS { 196, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #196 = G_UITOFP { 195, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #195 = G_SITOFP { 194, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #194 = G_FPTOUI { 193, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #193 = G_FPTOSI { 192, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #192 = G_FPTRUNC { 191, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #191 = G_FPEXT { 190, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #190 = G_FNEG { 189, 3, 2, 0, 0, 0, 0, SparcImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #189 = G_FFREXP { 188, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #188 = G_FLDEXP { 187, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #187 = G_FLOG10 { 186, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #186 = G_FLOG2 { 185, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #185 = G_FLOG { 184, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #184 = G_FEXP10 { 183, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #183 = G_FEXP2 { 182, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #182 = G_FEXP { 181, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #181 = G_FPOWI { 180, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #180 = G_FPOW { 179, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #179 = G_FREM { 178, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #178 = G_FDIV { 177, 4, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 46, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #177 = G_FMAD { 176, 4, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 46, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #176 = G_FMA { 175, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #175 = G_FMUL { 174, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #174 = G_FSUB { 173, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #173 = G_FADD { 172, 4, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #172 = G_UDIVFIXSAT { 171, 4, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #171 = G_SDIVFIXSAT { 170, 4, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #170 = G_UDIVFIX { 169, 4, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #169 = G_SDIVFIX { 168, 4, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #168 = G_UMULFIXSAT { 167, 4, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #167 = G_SMULFIXSAT { 166, 4, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #166 = G_UMULFIX { 165, 4, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #165 = G_SMULFIX { 164, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #164 = G_SSHLSAT { 163, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #163 = G_USHLSAT { 162, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #162 = G_SSUBSAT { 161, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #161 = G_USUBSAT { 160, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #160 = G_SADDSAT { 159, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #159 = G_UADDSAT { 158, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #158 = G_SMULH { 157, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #157 = G_UMULH { 156, 4, 2, 0, 0, 0, 0, SparcImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #156 = G_SMULO { 155, 4, 2, 0, 0, 0, 0, SparcImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #155 = G_UMULO { 154, 5, 2, 0, 0, 0, 0, SparcImpOpBase + 0, 115, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #154 = G_SSUBE { 153, 4, 2, 0, 0, 0, 0, SparcImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #153 = G_SSUBO { 152, 5, 2, 0, 0, 0, 0, SparcImpOpBase + 0, 115, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #152 = G_SADDE { 151, 4, 2, 0, 0, 0, 0, SparcImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #151 = G_SADDO { 150, 5, 2, 0, 0, 0, 0, SparcImpOpBase + 0, 115, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #150 = G_USUBE { 149, 4, 2, 0, 0, 0, 0, SparcImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #149 = G_USUBO { 148, 5, 2, 0, 0, 0, 0, SparcImpOpBase + 0, 115, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #148 = G_UADDE { 147, 4, 2, 0, 0, 0, 0, SparcImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #147 = G_UADDO { 146, 4, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #146 = G_SELECT { 145, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 112, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #145 = G_UCMP { 144, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 112, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #144 = G_SCMP { 143, 4, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 108, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #143 = G_FCMP { 142, 4, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 108, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #142 = G_ICMP { 141, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #141 = G_ROTL { 140, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #140 = G_ROTR { 139, 4, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 104, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #139 = G_FSHR { 138, 4, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 104, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #138 = G_FSHL { 137, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #137 = G_ASHR { 136, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #136 = G_LSHR { 135, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #135 = G_SHL { 134, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #134 = G_ZEXT { 133, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 40, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #133 = G_SEXT_INREG { 132, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #132 = G_SEXT { 131, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 98, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #131 = G_VAARG { 130, 1, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #130 = G_VASTART { 129, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #129 = G_FCONSTANT { 128, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #128 = G_CONSTANT { 127, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #127 = G_TRUNC { 126, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #126 = G_ANYEXT { 125, 1, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #125 = G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS { 124, 1, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #124 = G_INTRINSIC_CONVERGENT { 123, 1, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #123 = G_INTRINSIC_W_SIDE_EFFECTS { 122, 1, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #122 = G_INTRINSIC { 121, 0, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 1, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #121 = G_INVOKE_REGION_START { 120, 1, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #120 = G_BRINDIRECT { 119, 2, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #119 = G_BRCOND { 118, 4, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 94, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #118 = G_PREFETCH { 117, 2, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 21, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #117 = G_FENCE { 116, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #116 = G_ATOMICRMW_UDEC_WRAP { 115, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #115 = G_ATOMICRMW_UINC_WRAP { 114, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #114 = G_ATOMICRMW_FMIN { 113, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #113 = G_ATOMICRMW_FMAX { 112, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #112 = G_ATOMICRMW_FSUB { 111, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #111 = G_ATOMICRMW_FADD { 110, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #110 = G_ATOMICRMW_UMIN { 109, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #109 = G_ATOMICRMW_UMAX { 108, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #108 = G_ATOMICRMW_MIN { 107, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #107 = G_ATOMICRMW_MAX { 106, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #106 = G_ATOMICRMW_XOR { 105, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #105 = G_ATOMICRMW_OR { 104, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #104 = G_ATOMICRMW_NAND { 103, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #103 = G_ATOMICRMW_AND { 102, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #102 = G_ATOMICRMW_SUB { 101, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #101 = G_ATOMICRMW_ADD { 100, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #100 = G_ATOMICRMW_XCHG { 99, 4, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #99 = G_ATOMIC_CMPXCHG { 98, 5, 2, 0, 0, 0, 0, SparcImpOpBase + 0, 82, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #98 = G_ATOMIC_CMPXCHG_WITH_SUCCESS { 97, 5, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 77, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #97 = G_INDEXED_STORE { 96, 2, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #96 = G_STORE { 95, 5, 2, 0, 0, 0, 0, SparcImpOpBase + 0, 72, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #95 = G_INDEXED_ZEXTLOAD { 94, 5, 2, 0, 0, 0, 0, SparcImpOpBase + 0, 72, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #94 = G_INDEXED_SEXTLOAD { 93, 5, 2, 0, 0, 0, 0, SparcImpOpBase + 0, 72, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #93 = G_INDEXED_LOAD { 92, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #92 = G_ZEXTLOAD { 91, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #91 = G_SEXTLOAD { 90, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #90 = G_LOAD { 89, 1, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #89 = G_READSTEADYCOUNTER { 88, 1, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #88 = G_READCYCLECOUNTER { 87, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #87 = G_INTRINSIC_ROUNDEVEN { 86, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #86 = G_INTRINSIC_LLRINT { 85, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #85 = G_INTRINSIC_LRINT { 84, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #84 = G_INTRINSIC_ROUND { 83, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #83 = G_INTRINSIC_TRUNC { 82, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 69, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #82 = G_INTRINSIC_FPTRUNC_ROUND { 81, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #81 = G_CONSTANT_FOLD_BARRIER { 80, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #80 = G_FREEZE { 79, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #79 = G_BITCAST { 78, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #78 = G_INTTOPTR { 77, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #77 = G_PTRTOINT { 76, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #76 = G_CONCAT_VECTORS { 75, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #75 = G_BUILD_VECTOR_TRUNC { 74, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #74 = G_BUILD_VECTOR { 73, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #73 = G_MERGE_VALUES { 72, 4, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 63, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #72 = G_INSERT { 71, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #71 = G_UNMERGE_VALUES { 70, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 58, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #70 = G_EXTRACT { 69, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #69 = G_CONSTANT_POOL { 68, 5, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 53, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #68 = G_PTRAUTH_GLOBAL_VALUE { 67, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #67 = G_GLOBAL_VALUE { 66, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #66 = G_FRAME_INDEX { 65, 1, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #65 = G_PHI { 64, 1, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #64 = G_IMPLICIT_DEF { 63, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #63 = G_XOR { 62, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #62 = G_OR { 61, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #61 = G_AND { 60, 4, 2, 0, 0, 0, 0, SparcImpOpBase + 0, 46, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #60 = G_UDIVREM { 59, 4, 2, 0, 0, 0, 0, SparcImpOpBase + 0, 46, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #59 = G_SDIVREM { 58, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #58 = G_UREM { 57, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #57 = G_SREM { 56, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #56 = G_UDIV { 55, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #55 = G_SDIV { 54, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #54 = G_MUL { 53, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #53 = G_SUB { 52, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #52 = G_ADD { 51, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 40, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #51 = G_ASSERT_ALIGN { 50, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 40, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #50 = G_ASSERT_ZEXT { 49, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 40, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #49 = G_ASSERT_SEXT { 48, 1, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #48 = CONVERGENCECTRL_GLUE { 47, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 13, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #47 = CONVERGENCECTRL_LOOP { 46, 1, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #46 = CONVERGENCECTRL_ANCHOR { 45, 1, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #45 = CONVERGENCECTRL_ENTRY { 44, 1, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL }, // Inst #44 = JUMP_TABLE_DEBUG_INFO { 43, 0, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #43 = MEMBARRIER { 42, 0, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #42 = FAKE_USE { 41, 0, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #41 = ICALL_BRANCH_FUNNEL { 40, 3, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 37, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #40 = PATCHABLE_TYPED_EVENT_CALL { 39, 2, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 35, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #39 = PATCHABLE_EVENT_CALL { 38, 0, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #38 = PATCHABLE_TAIL_CALL { 37, 0, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #37 = PATCHABLE_FUNCTION_EXIT { 36, 0, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #36 = PATCHABLE_RET { 35, 0, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #35 = PATCHABLE_FUNCTION_ENTER { 34, 0, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #34 = PATCHABLE_OP { 33, 1, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #33 = FAULTING_OP { 32, 2, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 33, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #32 = LOCAL_ESCAPE { 31, 0, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #31 = STATEPOINT { 30, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 30, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #30 = PREALLOCATED_ARG { 29, 1, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #29 = PREALLOCATED_SETUP { 28, 1, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 29, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x0ULL }, // Inst #28 = LOAD_STACK_GUARD { 27, 6, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 23, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #27 = PATCHPOINT { 26, 0, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #26 = FENTRY_CALL { 25, 2, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 21, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #25 = STACKMAP { 24, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 19, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL }, // Inst #24 = ARITH_FENCE { 23, 4, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 15, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #23 = PSEUDO_PROBE { 22, 1, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL }, // Inst #22 = LIFETIME_END { 21, 1, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL }, // Inst #21 = LIFETIME_START { 20, 0, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #20 = BUNDLE { 19, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 13, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // Inst #19 = COPY { 18, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 13, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // Inst #18 = REG_SEQUENCE { 17, 1, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL }, // Inst #17 = DBG_LABEL { 16, 0, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #16 = DBG_PHI { 15, 0, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #15 = DBG_INSTR_REF { 14, 0, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #14 = DBG_VALUE_LIST { 13, 0, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #13 = DBG_VALUE { 12, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // Inst #12 = COPY_TO_REGCLASS { 11, 4, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 9, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #11 = SUBREG_TO_REG { 10, 1, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // Inst #10 = IMPLICIT_DEF { 9, 4, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 5, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #9 = INSERT_SUBREG { 8, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 2, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #8 = EXTRACT_SUBREG { 7, 0, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #7 = KILL { 6, 1, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // Inst #6 = ANNOTATION_LABEL { 5, 1, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // Inst #5 = GC_LABEL { 4, 1, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // Inst #4 = EH_LABEL { 3, 1, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // Inst #3 = CFI_INSTRUCTION { 2, 0, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2 = INLINEASM_BR { 1, 0, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #1 = INLINEASM { 0, 1, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #0 = PHI }, { /* 0 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 1 */ /* 1 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, /* 2 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, /* 5 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, /* 9 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, /* 13 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 15 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, /* 19 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) }, /* 21 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, /* 23 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, /* 29 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, /* 30 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, /* 33 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, /* 35 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 37 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 40 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 }, /* 43 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, /* 46 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, /* 50 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, /* 51 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 53 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, /* 58 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 }, /* 61 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, /* 63 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 }, /* 67 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, /* 69 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, /* 72 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 77 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 82 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, /* 87 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, /* 91 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, /* 94 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, /* 98 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 101 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, /* 104 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, /* 108 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, /* 112 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, /* 115 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, /* 120 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 }, /* 124 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, /* 127 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, /* 131 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, /* 134 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 138 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, /* 142 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, /* 144 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 }, /* 148 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, /* 152 */ { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, /* 156 */ { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, /* 160 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, /* 164 */ { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, /* 168 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, /* 170 */ { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 173 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, /* 176 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 179 */ { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 182 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, /* 184 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SP::FCCRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 187 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 190 */ { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 193 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, /* 197 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 202 */ { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, /* 206 */ { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 211 */ { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 212 */ { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 214 */ { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 216 */ { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 218 */ { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 221 */ { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 224 */ { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 227 */ { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 230 */ { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 232 */ { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 234 */ { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 236 */ { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 238 */ { SP::FCCRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 241 */ { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 245 */ { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 249 */ { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 254 */ { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 259 */ { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 264 */ { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 268 */ { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, /* 270 */ { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, /* 272 */ { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 274 */ { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 276 */ { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 279 */ { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 283 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 287 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 290 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, /* 293 */ { SP::CoprocRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 296 */ { SP::CoprocRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, /* 299 */ { SP::IntPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 302 */ { SP::IntPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 306 */ { SP::CoprocPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 309 */ { SP::CoprocPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, /* 312 */ { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 315 */ { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 319 */ { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, /* 322 */ { SP::IntPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, /* 325 */ { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 328 */ { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 332 */ { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, /* 335 */ { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 338 */ { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 342 */ { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, /* 345 */ { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 348 */ { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, /* 351 */ { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 353 */ { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 355 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 359 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 363 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 368 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 373 */ { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 375 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 377 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 380 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 384 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 387 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::ASRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 389 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 390 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::PRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 392 */ { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 395 */ { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 398 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 401 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { SP::ASRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 405 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::ASRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 409 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 412 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 416 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 419 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SP::CoprocRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 422 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { SP::CoprocRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 425 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SP::IntPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 428 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { SP::IntPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 432 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SP::CoprocPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 435 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { SP::CoprocPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 438 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 441 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 445 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 448 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { SP::IntPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 451 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 454 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 458 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 461 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 464 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 468 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 471 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 474 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 478 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 481 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, /* 485 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, /* 490 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, /* 494 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 497 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 501 */ { SP::FCCRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 504 */ { SP::FCCRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 507 */ { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FCCRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 512 */ { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FCCRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 517 */ { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FCCRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 522 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FCCRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 527 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FCCRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 532 */ { SP::ASRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, /* 535 */ { SP::ASRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 538 */ { SP::PRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, /* 541 */ { SP::PRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }, { /* 0 */ /* 0 */ SP::O6, SP::O6, /* 2 */ SP::O7, /* 3 */ SP::FCC0, /* 4 */ SP::ICC, /* 5 */ SP::ICC, SP::ICC, /* 7 */ SP::O6, /* 8 */ SP::ASR3, /* 9 */ SP::CPSR, /* 10 */ SP::FSR, /* 11 */ SP::Y, SP::ICC, SP::Y, SP::ICC, /* 15 */ SP::PSR, /* 16 */ SP::FQ, /* 17 */ SP::TBR, /* 18 */ SP::WIM, /* 19 */ SP::Y, SP::Y, SP::ICC, /* 22 */ SP::Y, SP::Y, /* 24 */ SP::Y, SP::ASR18, SP::Y, SP::ASR18, /* 28 */ SP::Y, SP::ICC, /* 30 */ SP::Y, /* 31 */ SP::CPQ, } }; #ifdef __GNUC__ #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Woverlength-strings" #endif extern const char SparcInstrNameData[] = { /* 0 */ "G_FLOG10\0" /* 9 */ "G_FEXP10\0" /* 18 */ "TA1\0" /* 22 */ "FSRC1\0" /* 28 */ "FANDNOT1\0" /* 37 */ "FNOT1\0" /* 43 */ "FORNOT1\0" /* 51 */ "FSRA32\0" /* 58 */ "FPSUB32\0" /* 66 */ "FPADD32\0" /* 74 */ "EDGE32\0" /* 81 */ "FCMPLE32\0" /* 90 */ "FCMPNE32\0" /* 99 */ "FPACK32\0" /* 107 */ "CMASK32\0" /* 115 */ "FSLL32\0" /* 122 */ "FSRL32\0" /* 129 */ "FCMPEQ32\0" /* 138 */ "FSLAS32\0" /* 146 */ "FCMPGT32\0" /* 155 */ "ARRAY32\0" /* 163 */ "FSRC2\0" /* 169 */ "G_FLOG2\0" /* 177 */ "G_FEXP2\0" /* 185 */ "FANDNOT2\0" /* 194 */ "FNOT2\0" /* 200 */ "FORNOT2\0" /* 208 */ "TA3\0" /* 212 */ "FPADD64\0" /* 220 */ "TA5\0" /* 224 */ "FSRA16\0" /* 231 */ "FPSUB16\0" /* 239 */ "FPADD16\0" /* 247 */ "EDGE16\0" /* 254 */ "FCMPLE16\0" /* 263 */ "FCMPNE16\0" /* 272 */ "FPACK16\0" /* 280 */ "CMASK16\0" /* 288 */ "FSLL16\0" /* 295 */ "FSRL16\0" /* 302 */ "FCHKSM16\0" /* 311 */ "FMEAN16\0" /* 319 */ "FCMPEQ16\0" /* 328 */ "FSLAS16\0" /* 336 */ "FCMPGT16\0" /* 345 */ "FMUL8X16\0" /* 354 */ "FMULD8ULX16\0" /* 366 */ "FMUL8ULX16\0" /* 377 */ "FMULD8SUX16\0" /* 389 */ "FMUL8SUX16\0" /* 400 */ "ARRAY16\0" /* 408 */ "EDGE8\0" /* 414 */ "CMASK8\0" /* 421 */ "ARRAY8\0" /* 428 */ "FBCONDA_V9\0" /* 439 */ "FBCOND_V9\0" /* 449 */ "FCMPD_V9\0" /* 458 */ "FCMPQ_V9\0" /* 467 */ "FCMPS_V9\0" /* 476 */ "BA\0" /* 479 */ "BPFCCA\0" /* 486 */ "BPICCA\0" /* 493 */ "BPXCCA\0" /* 500 */ "CBCONDA\0" /* 508 */ "FBCONDA\0" /* 516 */ "G_FMA\0" /* 522 */ "G_STRICT_FMA\0" /* 535 */ "BPRA\0" /* 540 */ "FALIGNADATA\0" /* 552 */ "G_FSUB\0" /* 559 */ "G_STRICT_FSUB\0" /* 573 */ "G_ATOMICRMW_FSUB\0" /* 590 */ "G_SUB\0" /* 596 */ "G_ATOMICRMW_SUB\0" /* 612 */ "ADDXCCC\0" /* 620 */ "BPFCC\0" /* 626 */ "V9FMOVD_FCC\0" /* 638 */ "SELECT_CC_DFP_FCC\0" /* 656 */ "SELECT_CC_QFP_FCC\0" /* 674 */ "SELECT_CC_FP_FCC\0" /* 691 */ "V9FMOVQ_FCC\0" /* 703 */ "V9FMOVS_FCC\0" /* 715 */ "SELECT_CC_Int_FCC\0" /* 733 */ "BPICC\0" /* 739 */ "FMOVD_ICC\0" /* 749 */ "SELECT_CC_DFP_ICC\0" /* 767 */ "SELECT_CC_QFP_ICC\0" /* 785 */ "SELECT_CC_FP_ICC\0" /* 802 */ "FMOVQ_ICC\0" /* 812 */ "FMOVS_ICC\0" /* 822 */ "SELECT_CC_Int_ICC\0" /* 840 */ "BPXCC\0" /* 846 */ "FMOVD_XCC\0" /* 856 */ "SELECT_CC_DFP_XCC\0" /* 874 */ "SELECT_CC_QFP_XCC\0" /* 892 */ "SELECT_CC_FP_XCC\0" /* 909 */ "FMOVQ_XCC\0" /* 919 */ "FMOVS_XCC\0" /* 929 */ "SELECT_CC_Int_XCC\0" /* 947 */ "G_INTRINSIC\0" /* 959 */ "G_FPTRUNC\0" /* 969 */ "G_INTRINSIC_TRUNC\0" /* 987 */ "G_TRUNC\0" /* 995 */ "G_BUILD_VECTOR_TRUNC\0" /* 1016 */ "G_DYN_STACKALLOC\0" /* 1033 */ "ADDXC\0" /* 1039 */ "G_FMAD\0" /* 1046 */ "G_INDEXED_SEXTLOAD\0" /* 1065 */ "G_SEXTLOAD\0" /* 1076 */ "G_INDEXED_ZEXTLOAD\0" /* 1095 */ "G_ZEXTLOAD\0" /* 1106 */ "G_INDEXED_LOAD\0" /* 1121 */ "G_LOAD\0" /* 1128 */ "FSUBD\0" /* 1134 */ "FHSUBD\0" /* 1141 */ "G_VECREDUCE_FADD\0" /* 1158 */ "G_FADD\0" /* 1165 */ "G_VECREDUCE_SEQ_FADD\0" /* 1186 */ "G_STRICT_FADD\0" /* 1200 */ "G_ATOMICRMW_FADD\0" /* 1217 */ "G_VECREDUCE_ADD\0" /* 1233 */ "G_ADD\0" /* 1239 */ "G_PTR_ADD\0" /* 1249 */ "G_ATOMICRMW_ADD\0" /* 1265 */ "FADDD\0" /* 1271 */ "FHADDD\0" /* 1278 */ "FNHADDD\0" /* 1286 */ "FNADDD\0" /* 1293 */ "V9FCMPED\0" /* 1302 */ "RESTORED\0" /* 1311 */ "SAVED\0" /* 1317 */ "FNEGD\0" /* 1323 */ "FMULD\0" /* 1329 */ "FNMULD\0" /* 1336 */ "FSMULD\0" /* 1343 */ "FNSMULD\0" /* 1351 */ "FAND\0" /* 1356 */ "FNAND\0" /* 1362 */ "G_ATOMICRMW_NAND\0" /* 1379 */ "FEXPAND\0" /* 1387 */ "G_VECREDUCE_AND\0" /* 1403 */ "G_AND\0" /* 1409 */ "G_ATOMICRMW_AND\0" /* 1425 */ "LIFETIME_END\0" /* 1438 */ "CBCOND\0" /* 1445 */ "FBCOND\0" /* 1452 */ "G_BRCOND\0" /* 1461 */ "G_LLROUND\0" /* 1471 */ "G_LROUND\0" /* 1480 */ "G_INTRINSIC_ROUND\0" /* 1498 */ "G_INTRINSIC_FPTRUNC_ROUND\0" /* 1524 */ "FITOD\0" /* 1530 */ "FQTOD\0" /* 1536 */ "FSTOD\0" /* 1542 */ "FXTOD\0" /* 1548 */ "MOVXTOD\0" /* 1556 */ "V9FCMPD\0" /* 1564 */ "FLCMPD\0" /* 1571 */ "LOAD_STACK_GUARD\0" /* 1588 */ "FMOVRD\0" /* 1595 */ "FABSD\0" /* 1601 */ "FSQRTD\0" /* 1608 */ "FDIVD\0" /* 1614 */ "FMOVD\0" /* 1620 */ "PSEUDO_PROBE\0" /* 1633 */ "G_SSUBE\0" /* 1641 */ "G_USUBE\0" /* 1649 */ "G_FENCE\0" /* 1657 */ "ARITH_FENCE\0" /* 1669 */ "REG_SEQUENCE\0" /* 1682 */ "G_SADDE\0" /* 1690 */ "G_UADDE\0" /* 1698 */ "G_GET_FPMODE\0" /* 1711 */ "G_RESET_FPMODE\0" /* 1726 */ "G_SET_FPMODE\0" /* 1739 */ "G_FMINNUM_IEEE\0" /* 1754 */ "G_FMAXNUM_IEEE\0" /* 1769 */ "FPMERGE\0" /* 1777 */ "G_VSCALE\0" /* 1786 */ "G_JUMP_TABLE\0" /* 1799 */ "BUNDLE\0" /* 1806 */ "BSHUFFLE\0" /* 1815 */ "G_MEMCPY_INLINE\0" /* 1831 */ "DONE\0" /* 1836 */ "FONE\0" /* 1841 */ "LOCAL_ESCAPE\0" /* 1854 */ "G_STACKRESTORE\0" /* 1869 */ "G_INDEXED_STORE\0" /* 1885 */ "G_STORE\0" /* 1893 */ "G_BITREVERSE\0" /* 1906 */ "FAKE_USE\0" /* 1915 */ "DBG_VALUE\0" /* 1925 */ "G_GLOBAL_VALUE\0" /* 1940 */ "G_PTRAUTH_GLOBAL_VALUE\0" /* 1963 */ "CONVERGENCECTRL_GLUE\0" /* 1984 */ "G_STACKSAVE\0" /* 1996 */ "G_MEMMOVE\0" /* 2006 */ "G_FREEZE\0" /* 2015 */ "G_FCANONICALIZE\0" /* 2031 */ "G_CTLZ_ZERO_UNDEF\0" /* 2049 */ "G_CTTZ_ZERO_UNDEF\0" /* 2067 */ "G_IMPLICIT_DEF\0" /* 2082 */ "DBG_INSTR_REF\0" /* 2096 */ "G_FNEG\0" /* 2103 */ "EXTRACT_SUBREG\0" /* 2118 */ "INSERT_SUBREG\0" /* 2132 */ "G_SEXT_INREG\0" /* 2145 */ "SUBREG_TO_REG\0" /* 2159 */ "G_ATOMIC_CMPXCHG\0" /* 2176 */ "G_ATOMICRMW_XCHG\0" /* 2193 */ "G_FLOG\0" /* 2200 */ "G_VAARG\0" /* 2208 */ "PREALLOCATED_ARG\0" /* 2225 */ "G_PREFETCH\0" /* 2236 */ "G_SMULH\0" /* 2244 */ "G_UMULH\0" /* 2252 */ "G_FTANH\0" /* 2260 */ "G_FSINH\0" /* 2268 */ "G_FCOSH\0" /* 2276 */ "FLUSH\0" /* 2282 */ "DBG_PHI\0" /* 2290 */ "UMULXHI\0" /* 2298 */ "XMULXHI\0" /* 2306 */ "FDTOI\0" /* 2312 */ "FQTOI\0" /* 2318 */ "FSTOI\0" /* 2324 */ "G_FPTOSI\0" /* 2333 */ "G_FPTOUI\0" /* 2342 */ "G_FPOWI\0" /* 2350 */ "BMASK\0" /* 2356 */ "G_PTRMASK\0" /* 2366 */ "EDGE32L\0" /* 2374 */ "EDGE16L\0" /* 2382 */ "EDGE8L\0" /* 2389 */ "FMUL8X16AL\0" /* 2400 */ "GC_LABEL\0" /* 2409 */ "DBG_LABEL\0" /* 2419 */ "EH_LABEL\0" /* 2428 */ "ANNOTATION_LABEL\0" /* 2445 */ "ICALL_BRANCH_FUNNEL\0" /* 2465 */ "G_FSHL\0" /* 2472 */ "G_SHL\0" /* 2478 */ "G_FCEIL\0" /* 2486 */ "PATCHABLE_TAIL_CALL\0" /* 2506 */ "TLS_CALL\0" /* 2515 */ "PATCHABLE_TYPED_EVENT_CALL\0" /* 2542 */ "PATCHABLE_EVENT_CALL\0" /* 2563 */ "FENTRY_CALL\0" /* 2575 */ "KILL\0" /* 2580 */ "G_CONSTANT_POOL\0" /* 2596 */ "ALIGNADDRL\0" /* 2607 */ "RETL\0" /* 2612 */ "G_ROTL\0" /* 2619 */ "G_VECREDUCE_FMUL\0" /* 2636 */ "G_FMUL\0" /* 2643 */ "G_VECREDUCE_SEQ_FMUL\0" /* 2664 */ "G_STRICT_FMUL\0" /* 2678 */ "G_VECREDUCE_MUL\0" /* 2694 */ "G_MUL\0" /* 2700 */ "SIAM\0" /* 2705 */ "G_FREM\0" /* 2712 */ "G_STRICT_FREM\0" /* 2726 */ "G_SREM\0" /* 2733 */ "G_UREM\0" /* 2740 */ "G_SDIVREM\0" /* 2750 */ "G_UDIVREM\0" /* 2760 */ "RDWIM\0" /* 2766 */ "INLINEASM\0" /* 2776 */ "G_VECREDUCE_FMINIMUM\0" /* 2797 */ "G_FMINIMUM\0" /* 2808 */ "G_VECREDUCE_FMAXIMUM\0" /* 2829 */ "G_FMAXIMUM\0" /* 2840 */ "G_FMINNUM\0" /* 2850 */ "G_FMAXNUM\0" /* 2860 */ "EDGE32N\0" /* 2868 */ "EDGE16N\0" /* 2876 */ "EDGE8N\0" /* 2883 */ "G_FATAN\0" /* 2891 */ "G_FTAN\0" /* 2898 */ "G_INTRINSIC_ROUNDEVEN\0" /* 2920 */ "G_ASSERT_ALIGN\0" /* 2935 */ "G_FCOPYSIGN\0" /* 2947 */ "G_VECREDUCE_FMIN\0" /* 2964 */ "G_ATOMICRMW_FMIN\0" /* 2981 */ "G_VECREDUCE_SMIN\0" /* 2998 */ "G_SMIN\0" /* 3005 */ "G_VECREDUCE_UMIN\0" /* 3022 */ "G_UMIN\0" /* 3029 */ "G_ATOMICRMW_UMIN\0" /* 3046 */ "G_ATOMICRMW_MIN\0" /* 3062 */ "G_FASIN\0" /* 3070 */ "G_FSIN\0" /* 3077 */ "EDGE32LN\0" /* 3086 */ "EDGE16LN\0" /* 3095 */ "EDGE8LN\0" /* 3103 */ "CFI_INSTRUCTION\0" /* 3119 */ "PDISTN\0" /* 3126 */ "ADJCALLSTACKDOWN\0" /* 3143 */ "SHUTDOWN\0" /* 3152 */ "G_SSUBO\0" /* 3160 */ "G_USUBO\0" /* 3168 */ "G_SADDO\0" /* 3176 */ "G_UADDO\0" /* 3184 */ "JUMP_TABLE_DEBUG_INFO\0" /* 3206 */ "G_SMULO\0" /* 3214 */ "G_UMULO\0" /* 3222 */ "G_BZERO\0" /* 3230 */ "FZERO\0" /* 3236 */ "STACKMAP\0" /* 3245 */ "G_DEBUGTRAP\0" /* 3257 */ "G_UBSANTRAP\0" /* 3269 */ "G_TRAP\0" /* 3276 */ "G_ATOMICRMW_UDEC_WRAP\0" /* 3298 */ "G_ATOMICRMW_UINC_WRAP\0" /* 3320 */ "G_BSWAP\0" /* 3328 */ "G_SITOFP\0" /* 3337 */ "G_UITOFP\0" /* 3346 */ "G_FCMP\0" /* 3353 */ "G_ICMP\0" /* 3360 */ "G_SCMP\0" /* 3367 */ "G_UCMP\0" /* 3374 */ "UNIMP\0" /* 3380 */ "NOP\0" /* 3384 */ "CONVERGENCECTRL_LOOP\0" /* 3405 */ "G_CTPOP\0" /* 3413 */ "PATCHABLE_OP\0" /* 3426 */ "FAULTING_OP\0" /* 3438 */ "ADJCALLSTACKUP\0" /* 3453 */ "PREALLOCATED_SETUP\0" /* 3472 */ "G_FLDEXP\0" /* 3481 */ "G_STRICT_FLDEXP\0" /* 3497 */ "G_FEXP\0" /* 3504 */ "G_FFREXP\0" /* 3513 */ "FSUBQ\0" /* 3519 */ "FADDQ\0" /* 3525 */ "V9FCMPEQ\0" /* 3534 */ "RDFQ\0" /* 3539 */ "FNEGQ\0" /* 3545 */ "FDMULQ\0" /* 3552 */ "FMULQ\0" /* 3558 */ "FDTOQ\0" /* 3564 */ "FITOQ\0" /* 3570 */ "FSTOQ\0" /* 3576 */ "FXTOQ\0" /* 3582 */ "V9FCMPQ\0" /* 3590 */ "FMOVRQ\0" /* 3597 */ "FABSQ\0" /* 3603 */ "FSQRTQ\0" /* 3610 */ "FDIVQ\0" /* 3616 */ "FMOVQ\0" /* 3622 */ "STBAR\0" /* 3628 */ "RDTBR\0" /* 3634 */ "G_BR\0" /* 3639 */ "INLINEASM_BR\0" /* 3652 */ "ALIGNADDR\0" /* 3662 */ "G_BLOCK_ADDR\0" /* 3675 */ "MEMBARRIER\0" /* 3686 */ "G_CONSTANT_FOLD_BARRIER\0" /* 3710 */ "PATCHABLE_FUNCTION_ENTER\0" /* 3735 */ "G_READCYCLECOUNTER\0" /* 3754 */ "G_READSTEADYCOUNTER\0" /* 3774 */ "G_READ_REGISTER\0" /* 3790 */ "G_WRITE_REGISTER\0" /* 3807 */ "G_ASHR\0" /* 3814 */ "G_FSHR\0" /* 3821 */ "G_LSHR\0" /* 3828 */ "SIR\0" /* 3832 */ "FOR\0" /* 3836 */ "CONVERGENCECTRL_ANCHOR\0" /* 3859 */ "FNOR\0" /* 3864 */ "FXNOR\0" /* 3870 */ "G_FFLOOR\0" /* 3879 */ "G_EXTRACT_SUBVECTOR\0" /* 3899 */ "G_INSERT_SUBVECTOR\0" /* 3918 */ "G_BUILD_VECTOR\0" /* 3933 */ "G_SHUFFLE_VECTOR\0" /* 3950 */ "G_SPLAT_VECTOR\0" /* 3965 */ "FXOR\0" /* 3970 */ "G_VECREDUCE_XOR\0" /* 3986 */ "G_XOR\0" /* 3992 */ "G_ATOMICRMW_XOR\0" /* 4008 */ "G_VECREDUCE_OR\0" /* 4023 */ "G_OR\0" /* 4028 */ "G_ATOMICRMW_OR\0" /* 4043 */ "BPR\0" /* 4047 */ "RDPR\0" /* 4052 */ "RDASR\0" /* 4058 */ "RDPSR\0" /* 4064 */ "G_ROTR\0" /* 4071 */ "G_INTTOPTR\0" /* 4082 */ "FSRC1S\0" /* 4089 */ "FANDNOT1S\0" /* 4099 */ "FNOT1S\0" /* 4106 */ "FORNOT1S\0" /* 4115 */ "FPSUB32S\0" /* 4124 */ "FPADD32S\0" /* 4133 */ "FSRC2S\0" /* 4140 */ "FANDNOT2S\0" /* 4150 */ "FNOT2S\0" /* 4157 */ "FORNOT2S\0" /* 4166 */ "FPSUB16S\0" /* 4175 */ "FPADD16S\0" /* 4184 */ "G_FABS\0" /* 4191 */ "G_ABS\0" /* 4197 */ "FSUBS\0" /* 4203 */ "FHSUBS\0" /* 4210 */ "FADDS\0" /* 4216 */ "FHADDS\0" /* 4223 */ "FNHADDS\0" /* 4231 */ "FNADDS\0" /* 4238 */ "FANDS\0" /* 4244 */ "FNANDS\0" /* 4251 */ "FONES\0" /* 4257 */ "V9FCMPES\0" /* 4266 */ "G_UNMERGE_VALUES\0" /* 4283 */ "G_MERGE_VALUES\0" /* 4298 */ "FNEGS\0" /* 4304 */ "FMULS\0" /* 4310 */ "FNMULS\0" /* 4317 */ "G_FACOS\0" /* 4325 */ "G_FCOS\0" /* 4332 */ "FZEROS\0" /* 4339 */ "FDTOS\0" /* 4345 */ "FITOS\0" /* 4351 */ "FQTOS\0" /* 4357 */ "MOVWTOS\0" /* 4365 */ "FXTOS\0" /* 4371 */ "V9FCMPS\0" /* 4379 */ "FLCMPS\0" /* 4386 */ "FORS\0" /* 4391 */ "FNORS\0" /* 4397 */ "FXNORS\0" /* 4404 */ "G_CONCAT_VECTORS\0" /* 4421 */ "FXORS\0" /* 4427 */ "FMOVRS\0" /* 4434 */ "COPY_TO_REGCLASS\0" /* 4451 */ "G_IS_FPCLASS\0" /* 4464 */ "FABSS\0" /* 4470 */ "G_ATOMIC_CMPXCHG_WITH_SUCCESS\0" /* 4500 */ "G_VECTOR_COMPRESS\0" /* 4518 */ "G_INTRINSIC_W_SIDE_EFFECTS\0" /* 4545 */ "G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS\0" /* 4583 */ "FSQRTS\0" /* 4590 */ "FDIVS\0" /* 4596 */ "FMOVS\0" /* 4602 */ "G_SSUBSAT\0" /* 4612 */ "G_USUBSAT\0" /* 4622 */ "G_SADDSAT\0" /* 4632 */ "G_UADDSAT\0" /* 4642 */ "G_SSHLSAT\0" /* 4652 */ "G_USHLSAT\0" /* 4662 */ "G_SMULFIXSAT\0" /* 4675 */ "G_UMULFIXSAT\0" /* 4688 */ "G_SDIVFIXSAT\0" /* 4701 */ "G_UDIVFIXSAT\0" /* 4714 */ "G_EXTRACT\0" /* 4724 */ "G_SELECT\0" /* 4733 */ "G_BRINDIRECT\0" /* 4746 */ "PATCHABLE_RET\0" /* 4760 */ "G_MEMSET\0" /* 4769 */ "PATCHABLE_FUNCTION_EXIT\0" /* 4793 */ "G_BRJT\0" /* 4800 */ "G_EXTRACT_VECTOR_ELT\0" /* 4821 */ "G_INSERT_VECTOR_ELT\0" /* 4841 */ "BPFCCANT\0" /* 4850 */ "BPICCANT\0" /* 4859 */ "BPXCCANT\0" /* 4868 */ "BPRANT\0" /* 4875 */ "G_FCONSTANT\0" /* 4887 */ "G_CONSTANT\0" /* 4898 */ "BPFCCNT\0" /* 4906 */ "BPICCNT\0" /* 4914 */ "BPXCCNT\0" /* 4922 */ "LZCNT\0" /* 4928 */ "G_INTRINSIC_CONVERGENT\0" /* 4951 */ "STATEPOINT\0" /* 4962 */ "PATCHPOINT\0" /* 4973 */ "G_PTRTOINT\0" /* 4984 */ "G_FRINT\0" /* 4992 */ "G_INTRINSIC_LLRINT\0" /* 5011 */ "G_INTRINSIC_LRINT\0" /* 5029 */ "G_FNEARBYINT\0" /* 5042 */ "BPRNT\0" /* 5048 */ "G_VASTART\0" /* 5058 */ "LIFETIME_START\0" /* 5073 */ "G_INVOKE_REGION_START\0" /* 5095 */ "G_INSERT\0" /* 5104 */ "G_FSQRT\0" /* 5112 */ "G_STRICT_FSQRT\0" /* 5127 */ "G_BITCAST\0" /* 5137 */ "G_ADDRSPACE_CAST\0" /* 5154 */ "PDIST\0" /* 5160 */ "DBG_VALUE_LIST\0" /* 5175 */ "G_FPEXT\0" /* 5183 */ "G_SEXT\0" /* 5190 */ "G_ASSERT_SEXT\0" /* 5204 */ "G_ANYEXT\0" /* 5213 */ "G_ZEXT\0" /* 5220 */ "G_ASSERT_ZEXT\0" /* 5234 */ "FMUL8X16AU\0" /* 5245 */ "G_FDIV\0" /* 5252 */ "G_STRICT_FDIV\0" /* 5266 */ "G_SDIV\0" /* 5273 */ "G_UDIV\0" /* 5280 */ "G_GET_FPENV\0" /* 5292 */ "G_RESET_FPENV\0" /* 5306 */ "G_SET_FPENV\0" /* 5318 */ "FLUSHW\0" /* 5325 */ "G_FPOW\0" /* 5332 */ "MOVSTOSW\0" /* 5341 */ "MOVSTOUW\0" /* 5350 */ "G_VECREDUCE_FMAX\0" /* 5367 */ "G_ATOMICRMW_FMAX\0" /* 5384 */ "G_VECREDUCE_SMAX\0" /* 5401 */ "G_SMAX\0" /* 5408 */ "G_VECREDUCE_UMAX\0" /* 5425 */ "G_UMAX\0" /* 5432 */ "G_ATOMICRMW_UMAX\0" /* 5449 */ "G_ATOMICRMW_MAX\0" /* 5465 */ "GETPCX\0" /* 5472 */ "G_FRAME_INDEX\0" /* 5486 */ "G_SBFX\0" /* 5493 */ "G_UBFX\0" /* 5500 */ "FPACKFIX\0" /* 5509 */ "G_SMULFIX\0" /* 5519 */ "G_UMULFIX\0" /* 5529 */ "G_SDIVFIX\0" /* 5539 */ "G_UDIVFIX\0" /* 5549 */ "XMULX\0" /* 5555 */ "FDTOX\0" /* 5561 */ "MOVDTOX\0" /* 5569 */ "FQTOX\0" /* 5575 */ "FSTOX\0" /* 5581 */ "SETX\0" /* 5586 */ "G_MEMCPY\0" /* 5595 */ "COPY\0" /* 5600 */ "RETRY\0" /* 5606 */ "CONVERGENCECTRL_ENTRY\0" /* 5628 */ "G_CTLZ\0" /* 5635 */ "G_CTTZ\0" /* 5642 */ "PREFETCHAi\0" /* 5653 */ "PREFETCHi\0" /* 5663 */ "SETHIi\0" /* 5670 */ "MEMBARi\0" /* 5678 */ "LDSBAri\0" /* 5686 */ "STBAri\0" /* 5693 */ "LDUBAri\0" /* 5701 */ "LDSTUBAri\0" /* 5711 */ "LDDAri\0" /* 5718 */ "LDAri\0" /* 5724 */ "STDAri\0" /* 5731 */ "LDDFAri\0" /* 5739 */ "LDFAri\0" /* 5746 */ "STDFAri\0" /* 5754 */ "LDQFAri\0" /* 5762 */ "STQFAri\0" /* 5770 */ "STFAri\0" /* 5777 */ "LDSHAri\0" /* 5785 */ "STHAri\0" /* 5792 */ "LDUHAri\0" /* 5800 */ "SWAPAri\0" /* 5808 */ "SRAri\0" /* 5814 */ "CASAri\0" /* 5821 */ "STAri\0" /* 5827 */ "LDSWAri\0" /* 5835 */ "LDXAri\0" /* 5842 */ "CASXAri\0" /* 5850 */ "STXAri\0" /* 5857 */ "LDSBri\0" /* 5864 */ "STBri\0" /* 5870 */ "LDUBri\0" /* 5877 */ "SUBri\0" /* 5883 */ "LDSTUBri\0" /* 5892 */ "SMACri\0" /* 5899 */ "UMACri\0" /* 5906 */ "SUBCri\0" /* 5913 */ "TSUBCCri\0" /* 5922 */ "TADDCCri\0" /* 5931 */ "ANDCCri\0" /* 5939 */ "V9MOVFCCri\0" /* 5950 */ "TICCri\0" /* 5957 */ "MOVICCri\0" /* 5966 */ "SMULCCri\0" /* 5975 */ "UMULCCri\0" /* 5984 */ "ANDNCCri\0" /* 5993 */ "ORNCCri\0" /* 6001 */ "XNORCCri\0" /* 6010 */ "XORCCri\0" /* 6018 */ "MULSCCri\0" /* 6027 */ "SDIVCCri\0" /* 6036 */ "UDIVCCri\0" /* 6045 */ "TXCCri\0" /* 6052 */ "MOVXCCri\0" /* 6061 */ "ADDCri\0" /* 6068 */ "LDDCri\0" /* 6075 */ "LDCri\0" /* 6081 */ "STDCri\0" /* 6088 */ "STCri\0" /* 6094 */ "ADDri\0" /* 6100 */ "LDDri\0" /* 6106 */ "LDri\0" /* 6111 */ "ANDri\0" /* 6117 */ "BINDri\0" /* 6124 */ "STDri\0" /* 6130 */ "SUBEri\0" /* 6137 */ "ADDEri\0" /* 6144 */ "RESTOREri\0" /* 6154 */ "SAVEri\0" /* 6161 */ "LDDFri\0" /* 6168 */ "LDFri\0" /* 6174 */ "STDFri\0" /* 6181 */ "LDQFri\0" /* 6188 */ "STQFri\0" /* 6195 */ "STFri\0" /* 6201 */ "LDSHri\0" /* 6208 */ "FLUSHri\0" /* 6216 */ "STHri\0" /* 6222 */ "LDUHri\0" /* 6229 */ "TAIL_CALLri\0" /* 6241 */ "SLLri\0" /* 6247 */ "JMPLri\0" /* 6254 */ "SRLri\0" /* 6260 */ "SMULri\0" /* 6267 */ "UMULri\0" /* 6274 */ "WRWIMri\0" /* 6282 */ "ANDNri\0" /* 6289 */ "ORNri\0" /* 6295 */ "TRAPri\0" /* 6302 */ "SWAPri\0" /* 6309 */ "STDCQri\0" /* 6317 */ "STDFQri\0" /* 6325 */ "WRTBRri\0" /* 6333 */ "XNORri\0" /* 6340 */ "XORri\0" /* 6346 */ "WRPRri\0" /* 6353 */ "WRASRri\0" /* 6361 */ "LDCSRri\0" /* 6369 */ "STCSRri\0" /* 6377 */ "LDFSRri\0" /* 6385 */ "STFSRri\0" /* 6393 */ "LDXFSRri\0" /* 6402 */ "STXFSRri\0" /* 6411 */ "PWRPSRri\0" /* 6420 */ "MOVRri\0" /* 6427 */ "STri\0" /* 6432 */ "RETTri\0" /* 6439 */ "SDIVri\0" /* 6446 */ "UDIVri\0" /* 6453 */ "TSUBCCTVri\0" /* 6464 */ "TADDCCTVri\0" /* 6475 */ "LDSWri\0" /* 6482 */ "SRAXri\0" /* 6489 */ "LDXri\0" /* 6495 */ "SLLXri\0" /* 6502 */ "SRLXri\0" /* 6509 */ "MULXri\0" /* 6516 */ "STXri\0" /* 6522 */ "SDIVXri\0" /* 6530 */ "UDIVXri\0" /* 6538 */ "PREFETCHAr\0" /* 6549 */ "PREFETCHr\0" /* 6559 */ "LDSBArr\0" /* 6567 */ "STBArr\0" /* 6574 */ "LDUBArr\0" /* 6582 */ "LDSTUBArr\0" /* 6592 */ "LDDArr\0" /* 6599 */ "LDArr\0" /* 6605 */ "STDArr\0" /* 6612 */ "LDDFArr\0" /* 6620 */ "LDFArr\0" /* 6627 */ "STDFArr\0" /* 6635 */ "LDQFArr\0" /* 6643 */ "STQFArr\0" /* 6651 */ "STFArr\0" /* 6658 */ "LDSHArr\0" /* 6666 */ "STHArr\0" /* 6673 */ "LDUHArr\0" /* 6681 */ "SWAPArr\0" /* 6689 */ "SRArr\0" /* 6695 */ "CASArr\0" /* 6702 */ "STArr\0" /* 6708 */ "LDSWArr\0" /* 6716 */ "LDXArr\0" /* 6723 */ "CASXArr\0" /* 6731 */ "STXArr\0" /* 6738 */ "LDSBrr\0" /* 6745 */ "STBrr\0" /* 6751 */ "LDUBrr\0" /* 6758 */ "SUBrr\0" /* 6764 */ "LDSTUBrr\0" /* 6773 */ "SMACrr\0" /* 6780 */ "UMACrr\0" /* 6787 */ "SUBCrr\0" /* 6794 */ "TSUBCCrr\0" /* 6803 */ "TADDCCrr\0" /* 6812 */ "ANDCCrr\0" /* 6820 */ "V9MOVFCCrr\0" /* 6831 */ "TICCrr\0" /* 6838 */ "MOVICCrr\0" /* 6847 */ "SMULCCrr\0" /* 6856 */ "UMULCCrr\0" /* 6865 */ "ANDNCCrr\0" /* 6874 */ "ORNCCrr\0" /* 6882 */ "XNORCCrr\0" /* 6891 */ "XORCCrr\0" /* 6899 */ "MULSCCrr\0" /* 6908 */ "SDIVCCrr\0" /* 6917 */ "UDIVCCrr\0" /* 6926 */ "TXCCrr\0" /* 6933 */ "MOVXCCrr\0" /* 6942 */ "ADDCrr\0" /* 6949 */ "LDDCrr\0" /* 6956 */ "LDCrr\0" /* 6962 */ "STDCrr\0" /* 6969 */ "POPCrr\0" /* 6976 */ "STCrr\0" /* 6982 */ "TLS_ADDrr\0" /* 6992 */ "LDDrr\0" /* 6998 */ "GDOP_LDrr\0" /* 7008 */ "TLS_LDrr\0" /* 7017 */ "ANDrr\0" /* 7023 */ "BINDrr\0" /* 7030 */ "STDrr\0" /* 7036 */ "SUBErr\0" /* 7043 */ "ADDErr\0" /* 7050 */ "RESTORErr\0" /* 7060 */ "SAVErr\0" /* 7067 */ "LDDFrr\0" /* 7074 */ "LDFrr\0" /* 7080 */ "STDFrr\0" /* 7087 */ "LDQFrr\0" /* 7094 */ "STQFrr\0" /* 7101 */ "STFrr\0" /* 7107 */ "LDSHrr\0" /* 7114 */ "FLUSHrr\0" /* 7122 */ "STHrr\0" /* 7128 */ "LDUHrr\0" /* 7135 */ "CALLrr\0" /* 7142 */ "SLLrr\0" /* 7148 */ "JMPLrr\0" /* 7155 */ "SRLrr\0" /* 7161 */ "SMULrr\0" /* 7168 */ "UMULrr\0" /* 7175 */ "WRWIMrr\0" /* 7183 */ "ANDNrr\0" /* 7190 */ "ORNrr\0" /* 7196 */ "TRAPrr\0" /* 7203 */ "SWAPrr\0" /* 7210 */ "STDCQrr\0" /* 7218 */ "STDFQrr\0" /* 7226 */ "WRTBRrr\0" /* 7234 */ "XNORrr\0" /* 7241 */ "XORrr\0" /* 7247 */ "WRPRrr\0" /* 7254 */ "WRASRrr\0" /* 7262 */ "LDCSRrr\0" /* 7270 */ "STCSRrr\0" /* 7278 */ "LDFSRrr\0" /* 7286 */ "STFSRrr\0" /* 7294 */ "LDXFSRrr\0" /* 7303 */ "STXFSRrr\0" /* 7312 */ "PWRPSRrr\0" /* 7321 */ "MOVRrr\0" /* 7328 */ "STrr\0" /* 7333 */ "RETTrr\0" /* 7340 */ "SDIVrr\0" /* 7347 */ "UDIVrr\0" /* 7354 */ "TSUBCCTVrr\0" /* 7365 */ "TADDCCTVrr\0" /* 7376 */ "LDSWrr\0" /* 7383 */ "SRAXrr\0" /* 7390 */ "GDOP_LDXrr\0" /* 7401 */ "TLS_LDXrr\0" /* 7411 */ "SLLXrr\0" /* 7418 */ "SRLXrr\0" /* 7425 */ "MULXrr\0" /* 7432 */ "STXrr\0" /* 7438 */ "SDIVXrr\0" /* 7446 */ "UDIVXrr\0" }; #ifdef __GNUC__ #pragma GCC diagnostic pop #endif extern const unsigned SparcInstrNameIndices[] = { 2286U, 2766U, 3639U, 3103U, 2419U, 2400U, 2428U, 2575U, 2103U, 2118U, 2069U, 2145U, 4434U, 1915U, 5160U, 2082U, 2282U, 2409U, 1669U, 5595U, 1799U, 5058U, 1425U, 1620U, 1657U, 3236U, 2563U, 4962U, 1571U, 3453U, 2208U, 4951U, 1841U, 3426U, 3413U, 3710U, 4746U, 4769U, 2486U, 2542U, 2515U, 2445U, 1906U, 3675U, 3184U, 5606U, 3836U, 3384U, 1963U, 5190U, 5220U, 2920U, 1233U, 590U, 2694U, 5266U, 5273U, 2726U, 2733U, 2740U, 2750U, 1403U, 4023U, 3986U, 2067U, 2284U, 5472U, 1925U, 1940U, 2580U, 4714U, 4266U, 5095U, 4283U, 3918U, 995U, 4404U, 4973U, 4071U, 5127U, 2006U, 3686U, 1498U, 969U, 1480U, 5011U, 4992U, 2898U, 3735U, 3754U, 1121U, 1065U, 1095U, 1106U, 1046U, 1076U, 1885U, 1869U, 4470U, 2159U, 2176U, 1249U, 596U, 1409U, 1362U, 4028U, 3992U, 5449U, 3046U, 5432U, 3029U, 1200U, 573U, 5367U, 2964U, 3298U, 3276U, 1649U, 2225U, 1452U, 4733U, 5073U, 947U, 4518U, 4928U, 4545U, 5204U, 987U, 4887U, 4875U, 5048U, 2200U, 5183U, 2132U, 5213U, 2472U, 3821U, 3807U, 2465U, 3814U, 4064U, 2612U, 3353U, 3346U, 3360U, 3367U, 4724U, 3176U, 1690U, 3160U, 1641U, 3168U, 1682U, 3152U, 1633U, 3214U, 3206U, 2244U, 2236U, 4632U, 4622U, 4612U, 4602U, 4652U, 4642U, 5509U, 5519U, 4662U, 4675U, 5529U, 5539U, 4688U, 4701U, 1158U, 552U, 2636U, 516U, 1039U, 5245U, 2705U, 5325U, 2342U, 3497U, 177U, 9U, 2193U, 169U, 0U, 3472U, 3504U, 2096U, 5175U, 959U, 2324U, 2333U, 3328U, 3337U, 4184U, 2935U, 4451U, 2015U, 2840U, 2850U, 1739U, 1754U, 2797U, 2829U, 5280U, 5306U, 5292U, 1698U, 1726U, 1711U, 1239U, 2356U, 2998U, 5401U, 3022U, 5425U, 4191U, 1471U, 1461U, 3634U, 4793U, 1777U, 3899U, 3879U, 4821U, 4800U, 3933U, 3950U, 4500U, 5635U, 2049U, 5628U, 2031U, 3405U, 3320U, 1893U, 2478U, 4325U, 3070U, 2891U, 4317U, 3062U, 2883U, 2268U, 2260U, 2252U, 5104U, 3870U, 4984U, 5029U, 5137U, 3662U, 1786U, 1016U, 1984U, 1854U, 1186U, 559U, 2664U, 5252U, 2712U, 522U, 5112U, 3481U, 3774U, 3790U, 5586U, 1815U, 1996U, 4760U, 3222U, 3269U, 3245U, 3257U, 1165U, 2643U, 1141U, 2619U, 5350U, 2947U, 2808U, 2776U, 1217U, 2678U, 1387U, 4008U, 3970U, 5384U, 2981U, 5408U, 3005U, 5486U, 5493U, 3126U, 3438U, 5465U, 638U, 749U, 856U, 674U, 785U, 892U, 715U, 822U, 929U, 656U, 767U, 874U, 4765U, 5581U, 5923U, 6804U, 6061U, 6942U, 6137U, 7043U, 1033U, 612U, 6094U, 6986U, 3652U, 2596U, 5931U, 6812U, 5984U, 6865U, 6282U, 7183U, 6111U, 7017U, 400U, 155U, 421U, 476U, 1439U, 501U, 6117U, 7023U, 2350U, 620U, 479U, 4841U, 4898U, 733U, 486U, 4850U, 4906U, 4043U, 535U, 4868U, 5042U, 840U, 493U, 4859U, 4914U, 1806U, 2501U, 6234U, 7135U, 5814U, 6695U, 5842U, 6723U, 1438U, 500U, 280U, 107U, 414U, 1831U, 247U, 2374U, 3086U, 2868U, 74U, 2366U, 3077U, 2860U, 408U, 2382U, 3095U, 2876U, 1595U, 3597U, 4464U, 1265U, 3519U, 4210U, 540U, 1351U, 28U, 4089U, 185U, 4140U, 4238U, 1445U, 508U, 428U, 439U, 302U, 1558U, 449U, 319U, 129U, 336U, 146U, 254U, 81U, 263U, 90U, 3584U, 458U, 4373U, 467U, 1608U, 3610U, 4590U, 3545U, 2306U, 3558U, 4339U, 5555U, 1379U, 1271U, 4216U, 1134U, 4203U, 1524U, 3564U, 4345U, 1564U, 4379U, 2276U, 5318U, 6208U, 7114U, 311U, 1614U, 628U, 739U, 846U, 3616U, 693U, 802U, 909U, 1588U, 3590U, 4427U, 4596U, 705U, 812U, 919U, 389U, 366U, 345U, 2389U, 5234U, 1323U, 377U, 354U, 3552U, 4304U, 1286U, 4231U, 1356U, 4244U, 1317U, 3539U, 4298U, 1278U, 4223U, 1329U, 4310U, 3859U, 4391U, 37U, 4099U, 194U, 4150U, 1343U, 1836U, 4251U, 3832U, 43U, 4106U, 200U, 4157U, 4386U, 272U, 99U, 5500U, 239U, 4175U, 66U, 4124U, 212U, 1769U, 231U, 4166U, 58U, 4115U, 1530U, 2312U, 4351U, 5569U, 328U, 138U, 288U, 115U, 1336U, 1601U, 3603U, 4583U, 224U, 51U, 22U, 4082U, 163U, 4133U, 295U, 122U, 1536U, 2318U, 3570U, 5575U, 1128U, 3513U, 4197U, 3864U, 4397U, 3965U, 4421U, 1542U, 3576U, 4365U, 3230U, 4332U, 7390U, 6998U, 6247U, 7148U, 5718U, 6599U, 6361U, 7262U, 6075U, 6956U, 5711U, 6592U, 6068U, 6949U, 5731U, 6612U, 6161U, 7067U, 6100U, 6992U, 5739U, 6620U, 6377U, 7278U, 6168U, 7074U, 5754U, 6635U, 6181U, 7087U, 5678U, 6559U, 5857U, 6738U, 5777U, 6658U, 6201U, 7107U, 5701U, 6582U, 5883U, 6764U, 5827U, 6708U, 6475U, 7376U, 5693U, 6574U, 5870U, 6751U, 5792U, 6673U, 6222U, 7128U, 5835U, 6716U, 6393U, 7294U, 6489U, 7395U, 6106U, 7003U, 4922U, 5670U, 5561U, 5941U, 6822U, 5957U, 6838U, 6420U, 7321U, 5332U, 5341U, 4357U, 6052U, 6933U, 1548U, 6018U, 6899U, 6509U, 7425U, 3380U, 6003U, 6884U, 5993U, 6874U, 6289U, 7190U, 6335U, 7236U, 5154U, 3119U, 6969U, 5642U, 6538U, 5653U, 6549U, 6411U, 7312U, 4052U, 3534U, 4047U, 4058U, 3628U, 2760U, 1302U, 6144U, 7050U, 4756U, 2607U, 5600U, 6432U, 7333U, 1311U, 6154U, 7060U, 6027U, 6908U, 6522U, 7438U, 6439U, 7340U, 5663U, 3143U, 2700U, 3828U, 6495U, 7411U, 6241U, 7142U, 5892U, 6773U, 5966U, 6847U, 6260U, 7161U, 6482U, 7383U, 5808U, 6689U, 6502U, 7418U, 6254U, 7155U, 5821U, 6702U, 3622U, 5686U, 6567U, 5864U, 6745U, 6369U, 7270U, 6088U, 6976U, 5724U, 6605U, 6309U, 7210U, 6081U, 6962U, 5746U, 6627U, 6317U, 7218U, 6174U, 7080U, 6124U, 7030U, 5770U, 6651U, 6385U, 7286U, 6195U, 7101U, 5785U, 6666U, 6216U, 7122U, 5762U, 6643U, 6188U, 7094U, 5850U, 6731U, 6402U, 7303U, 6516U, 7432U, 6427U, 7328U, 5914U, 6795U, 5906U, 6787U, 6130U, 7036U, 5877U, 6758U, 5800U, 6681U, 6302U, 7203U, 18U, 208U, 220U, 6464U, 7365U, 5922U, 6803U, 2496U, 6229U, 5950U, 6831U, 6982U, 2506U, 7401U, 7008U, 6295U, 7196U, 6453U, 7354U, 5913U, 6794U, 6045U, 6926U, 6036U, 6917U, 6530U, 7446U, 6446U, 7347U, 5899U, 6780U, 5975U, 6856U, 2290U, 6267U, 7168U, 3374U, 1556U, 1293U, 3525U, 4257U, 3582U, 4371U, 626U, 691U, 703U, 5939U, 6820U, 6353U, 7254U, 6346U, 7247U, 6412U, 7313U, 6325U, 7226U, 6274U, 7175U, 5549U, 2298U, 6001U, 6882U, 6333U, 7234U, 6010U, 6891U, 6340U, 7241U, }; static inline void InitSparcMCInstrInfo(MCInstrInfo *II) { II->InitMCInstrInfo(SparcDescs.Insts, SparcInstrNameIndices, SparcInstrNameData, nullptr, nullptr, 810); } } // end namespace llvm #endif // GET_INSTRINFO_MC_DESC #ifdef GET_INSTRINFO_HEADER #undef GET_INSTRINFO_HEADER namespace llvm { struct SparcGenInstrInfo : public TargetInstrInfo { explicit SparcGenInstrInfo(unsigned CFSetupOpcode = ~0u, unsigned CFDestroyOpcode = ~0u, unsigned CatchRetOpcode = ~0u, unsigned ReturnOpcode = ~0u); ~SparcGenInstrInfo() override = default; }; } // end namespace llvm #endif // GET_INSTRINFO_HEADER #ifdef GET_INSTRINFO_HELPER_DECLS #undef GET_INSTRINFO_HELPER_DECLS #endif // GET_INSTRINFO_HELPER_DECLS #ifdef GET_INSTRINFO_HELPERS #undef GET_INSTRINFO_HELPERS #endif // GET_INSTRINFO_HELPERS #ifdef GET_INSTRINFO_CTOR_DTOR #undef GET_INSTRINFO_CTOR_DTOR namespace llvm { extern const SparcInstrTable SparcDescs; extern const unsigned SparcInstrNameIndices[]; extern const char SparcInstrNameData[]; SparcGenInstrInfo::SparcGenInstrInfo(unsigned CFSetupOpcode, unsigned CFDestroyOpcode, unsigned CatchRetOpcode, unsigned ReturnOpcode) : TargetInstrInfo(CFSetupOpcode, CFDestroyOpcode, CatchRetOpcode, ReturnOpcode) { InitMCInstrInfo(SparcDescs.Insts, SparcInstrNameIndices, SparcInstrNameData, nullptr, nullptr, 810); } } // end namespace llvm #endif // GET_INSTRINFO_CTOR_DTOR #ifdef GET_INSTRINFO_OPERAND_ENUM #undef GET_INSTRINFO_OPERAND_ENUM namespace llvm { namespace SP { namespace OpName { enum { OPERAND_LAST }; } // end namespace OpName } // end namespace SP } // end namespace llvm #endif //GET_INSTRINFO_OPERAND_ENUM #ifdef GET_INSTRINFO_NAMED_OPS #undef GET_INSTRINFO_NAMED_OPS namespace llvm { namespace SP { LLVM_READONLY int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx) { return -1; } } // end namespace SP } // end namespace llvm #endif //GET_INSTRINFO_NAMED_OPS #ifdef GET_INSTRINFO_OPERAND_TYPES_ENUM #undef GET_INSTRINFO_OPERAND_TYPES_ENUM namespace llvm { namespace SP { namespace OpTypes { enum OperandType { ASITag = 0, CCOp = 1, MEMri = 2, MEMrr = 3, MembarTag = 4, PrefetchTag = 5, RegCCOp = 6, TailRelocSymGOTLoad = 7, TailRelocSymTLSAdd = 8, TailRelocSymTLSCall = 9, TailRelocSymTLSLoad = 10, bprtarget = 11, bprtarget16 = 12, brtarget = 13, calltarget = 14, f32imm = 15, f64imm = 16, getPCX = 17, i1imm = 18, i8imm = 19, i16imm = 20, i32imm = 21, i64imm = 22, ptype0 = 23, ptype1 = 24, ptype2 = 25, ptype3 = 26, ptype4 = 27, ptype5 = 28, shift_imm5 = 29, shift_imm6 = 30, simm13Op = 31, type0 = 32, type1 = 33, type2 = 34, type3 = 35, type4 = 36, type5 = 37, untyped_imm_0 = 38, ASRRegs = 39, CoprocPair = 40, CoprocRegs = 41, DFPRegs = 42, FCCRegs = 43, FPRegs = 44, GPRIncomingArg = 45, GPROutgoingArg = 46, I64Regs = 47, IntPair = 48, IntRegs = 49, LowDFPRegs = 50, LowQFPRegs = 51, PRRegs = 52, QFPRegs = 53, OPERAND_TYPE_LIST_END }; } // end namespace OpTypes } // end namespace SP } // end namespace llvm #endif // GET_INSTRINFO_OPERAND_TYPES_ENUM #ifdef GET_INSTRINFO_OPERAND_TYPE #undef GET_INSTRINFO_OPERAND_TYPE namespace llvm { namespace SP { LLVM_READONLY static int getOperandType(uint16_t Opcode, uint16_t OpIdx) { static const uint16_t Offsets[] = { /* PHI */ 0, /* INLINEASM */ 1, /* INLINEASM_BR */ 1, /* CFI_INSTRUCTION */ 1, /* EH_LABEL */ 2, /* GC_LABEL */ 3, /* ANNOTATION_LABEL */ 4, /* KILL */ 5, /* EXTRACT_SUBREG */ 5, /* INSERT_SUBREG */ 8, /* IMPLICIT_DEF */ 12, /* SUBREG_TO_REG */ 13, /* COPY_TO_REGCLASS */ 17, /* DBG_VALUE */ 20, /* DBG_VALUE_LIST */ 20, /* DBG_INSTR_REF */ 20, /* DBG_PHI */ 20, /* DBG_LABEL */ 20, /* REG_SEQUENCE */ 21, /* COPY */ 23, /* BUNDLE */ 25, /* LIFETIME_START */ 25, /* LIFETIME_END */ 26, /* PSEUDO_PROBE */ 27, /* ARITH_FENCE */ 31, /* STACKMAP */ 33, /* FENTRY_CALL */ 35, /* PATCHPOINT */ 35, /* LOAD_STACK_GUARD */ 41, /* PREALLOCATED_SETUP */ 42, /* PREALLOCATED_ARG */ 43, /* STATEPOINT */ 46, /* LOCAL_ESCAPE */ 46, /* FAULTING_OP */ 48, /* PATCHABLE_OP */ 49, /* PATCHABLE_FUNCTION_ENTER */ 49, /* PATCHABLE_RET */ 49, /* PATCHABLE_FUNCTION_EXIT */ 49, /* PATCHABLE_TAIL_CALL */ 49, /* PATCHABLE_EVENT_CALL */ 49, /* PATCHABLE_TYPED_EVENT_CALL */ 51, /* ICALL_BRANCH_FUNNEL */ 54, /* FAKE_USE */ 54, /* MEMBARRIER */ 54, /* JUMP_TABLE_DEBUG_INFO */ 54, /* CONVERGENCECTRL_ENTRY */ 55, /* CONVERGENCECTRL_ANCHOR */ 56, /* CONVERGENCECTRL_LOOP */ 57, /* CONVERGENCECTRL_GLUE */ 59, /* G_ASSERT_SEXT */ 60, /* G_ASSERT_ZEXT */ 63, /* G_ASSERT_ALIGN */ 66, /* G_ADD */ 69, /* G_SUB */ 72, /* G_MUL */ 75, /* G_SDIV */ 78, /* G_UDIV */ 81, /* G_SREM */ 84, /* G_UREM */ 87, /* G_SDIVREM */ 90, /* G_UDIVREM */ 94, /* G_AND */ 98, /* G_OR */ 101, /* G_XOR */ 104, /* G_IMPLICIT_DEF */ 107, /* G_PHI */ 108, /* G_FRAME_INDEX */ 109, /* G_GLOBAL_VALUE */ 111, /* G_PTRAUTH_GLOBAL_VALUE */ 113, /* G_CONSTANT_POOL */ 118, /* G_EXTRACT */ 120, /* G_UNMERGE_VALUES */ 123, /* G_INSERT */ 125, /* G_MERGE_VALUES */ 129, /* G_BUILD_VECTOR */ 131, /* G_BUILD_VECTOR_TRUNC */ 133, /* G_CONCAT_VECTORS */ 135, /* G_PTRTOINT */ 137, /* G_INTTOPTR */ 139, /* G_BITCAST */ 141, /* G_FREEZE */ 143, /* G_CONSTANT_FOLD_BARRIER */ 145, /* G_INTRINSIC_FPTRUNC_ROUND */ 147, /* G_INTRINSIC_TRUNC */ 150, /* G_INTRINSIC_ROUND */ 152, /* G_INTRINSIC_LRINT */ 154, /* G_INTRINSIC_LLRINT */ 156, /* G_INTRINSIC_ROUNDEVEN */ 158, /* G_READCYCLECOUNTER */ 160, /* G_READSTEADYCOUNTER */ 161, /* G_LOAD */ 162, /* G_SEXTLOAD */ 164, /* G_ZEXTLOAD */ 166, /* G_INDEXED_LOAD */ 168, /* G_INDEXED_SEXTLOAD */ 173, /* G_INDEXED_ZEXTLOAD */ 178, /* G_STORE */ 183, /* G_INDEXED_STORE */ 185, /* G_ATOMIC_CMPXCHG_WITH_SUCCESS */ 190, /* G_ATOMIC_CMPXCHG */ 195, /* G_ATOMICRMW_XCHG */ 199, /* G_ATOMICRMW_ADD */ 202, /* G_ATOMICRMW_SUB */ 205, /* G_ATOMICRMW_AND */ 208, /* G_ATOMICRMW_NAND */ 211, /* G_ATOMICRMW_OR */ 214, /* G_ATOMICRMW_XOR */ 217, /* G_ATOMICRMW_MAX */ 220, /* G_ATOMICRMW_MIN */ 223, /* G_ATOMICRMW_UMAX */ 226, /* G_ATOMICRMW_UMIN */ 229, /* G_ATOMICRMW_FADD */ 232, /* G_ATOMICRMW_FSUB */ 235, /* G_ATOMICRMW_FMAX */ 238, /* G_ATOMICRMW_FMIN */ 241, /* G_ATOMICRMW_UINC_WRAP */ 244, /* G_ATOMICRMW_UDEC_WRAP */ 247, /* G_FENCE */ 250, /* G_PREFETCH */ 252, /* G_BRCOND */ 256, /* G_BRINDIRECT */ 258, /* G_INVOKE_REGION_START */ 259, /* G_INTRINSIC */ 259, /* G_INTRINSIC_W_SIDE_EFFECTS */ 260, /* G_INTRINSIC_CONVERGENT */ 261, /* G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS */ 262, /* G_ANYEXT */ 263, /* G_TRUNC */ 265, /* G_CONSTANT */ 267, /* G_FCONSTANT */ 269, /* G_VASTART */ 271, /* G_VAARG */ 272, /* G_SEXT */ 275, /* G_SEXT_INREG */ 277, /* G_ZEXT */ 280, /* G_SHL */ 282, /* G_LSHR */ 285, /* G_ASHR */ 288, /* G_FSHL */ 291, /* G_FSHR */ 295, /* G_ROTR */ 299, /* G_ROTL */ 302, /* G_ICMP */ 305, /* G_FCMP */ 309, /* G_SCMP */ 313, /* G_UCMP */ 316, /* G_SELECT */ 319, /* G_UADDO */ 323, /* G_UADDE */ 327, /* G_USUBO */ 332, /* G_USUBE */ 336, /* G_SADDO */ 341, /* G_SADDE */ 345, /* G_SSUBO */ 350, /* G_SSUBE */ 354, /* G_UMULO */ 359, /* G_SMULO */ 363, /* G_UMULH */ 367, /* G_SMULH */ 370, /* G_UADDSAT */ 373, /* G_SADDSAT */ 376, /* G_USUBSAT */ 379, /* G_SSUBSAT */ 382, /* G_USHLSAT */ 385, /* G_SSHLSAT */ 388, /* G_SMULFIX */ 391, /* G_UMULFIX */ 395, /* G_SMULFIXSAT */ 399, /* G_UMULFIXSAT */ 403, /* G_SDIVFIX */ 407, /* G_UDIVFIX */ 411, /* G_SDIVFIXSAT */ 415, /* G_UDIVFIXSAT */ 419, /* G_FADD */ 423, /* G_FSUB */ 426, /* G_FMUL */ 429, /* G_FMA */ 432, /* G_FMAD */ 436, /* G_FDIV */ 440, /* G_FREM */ 443, /* G_FPOW */ 446, /* G_FPOWI */ 449, /* G_FEXP */ 452, /* G_FEXP2 */ 454, /* G_FEXP10 */ 456, /* G_FLOG */ 458, /* G_FLOG2 */ 460, /* G_FLOG10 */ 462, /* G_FLDEXP */ 464, /* G_FFREXP */ 467, /* G_FNEG */ 470, /* G_FPEXT */ 472, /* G_FPTRUNC */ 474, /* G_FPTOSI */ 476, /* G_FPTOUI */ 478, /* G_SITOFP */ 480, /* G_UITOFP */ 482, /* G_FABS */ 484, /* G_FCOPYSIGN */ 486, /* G_IS_FPCLASS */ 489, /* G_FCANONICALIZE */ 492, /* G_FMINNUM */ 494, /* G_FMAXNUM */ 497, /* G_FMINNUM_IEEE */ 500, /* G_FMAXNUM_IEEE */ 503, /* G_FMINIMUM */ 506, /* G_FMAXIMUM */ 509, /* G_GET_FPENV */ 512, /* G_SET_FPENV */ 513, /* G_RESET_FPENV */ 514, /* G_GET_FPMODE */ 514, /* G_SET_FPMODE */ 515, /* G_RESET_FPMODE */ 516, /* G_PTR_ADD */ 516, /* G_PTRMASK */ 519, /* G_SMIN */ 522, /* G_SMAX */ 525, /* G_UMIN */ 528, /* G_UMAX */ 531, /* G_ABS */ 534, /* G_LROUND */ 536, /* G_LLROUND */ 538, /* G_BR */ 540, /* G_BRJT */ 541, /* G_VSCALE */ 544, /* G_INSERT_SUBVECTOR */ 546, /* G_EXTRACT_SUBVECTOR */ 550, /* G_INSERT_VECTOR_ELT */ 553, /* G_EXTRACT_VECTOR_ELT */ 557, /* G_SHUFFLE_VECTOR */ 560, /* G_SPLAT_VECTOR */ 564, /* G_VECTOR_COMPRESS */ 566, /* G_CTTZ */ 570, /* G_CTTZ_ZERO_UNDEF */ 572, /* G_CTLZ */ 574, /* G_CTLZ_ZERO_UNDEF */ 576, /* G_CTPOP */ 578, /* G_BSWAP */ 580, /* G_BITREVERSE */ 582, /* G_FCEIL */ 584, /* G_FCOS */ 586, /* G_FSIN */ 588, /* G_FTAN */ 590, /* G_FACOS */ 592, /* G_FASIN */ 594, /* G_FATAN */ 596, /* G_FCOSH */ 598, /* G_FSINH */ 600, /* G_FTANH */ 602, /* G_FSQRT */ 604, /* G_FFLOOR */ 606, /* G_FRINT */ 608, /* G_FNEARBYINT */ 610, /* G_ADDRSPACE_CAST */ 612, /* G_BLOCK_ADDR */ 614, /* G_JUMP_TABLE */ 616, /* G_DYN_STACKALLOC */ 618, /* G_STACKSAVE */ 621, /* G_STACKRESTORE */ 622, /* G_STRICT_FADD */ 623, /* G_STRICT_FSUB */ 626, /* G_STRICT_FMUL */ 629, /* G_STRICT_FDIV */ 632, /* G_STRICT_FREM */ 635, /* G_STRICT_FMA */ 638, /* G_STRICT_FSQRT */ 642, /* G_STRICT_FLDEXP */ 644, /* G_READ_REGISTER */ 647, /* G_WRITE_REGISTER */ 649, /* G_MEMCPY */ 651, /* G_MEMCPY_INLINE */ 655, /* G_MEMMOVE */ 658, /* G_MEMSET */ 662, /* G_BZERO */ 666, /* G_TRAP */ 669, /* G_DEBUGTRAP */ 669, /* G_UBSANTRAP */ 669, /* G_VECREDUCE_SEQ_FADD */ 670, /* G_VECREDUCE_SEQ_FMUL */ 673, /* G_VECREDUCE_FADD */ 676, /* G_VECREDUCE_FMUL */ 678, /* G_VECREDUCE_FMAX */ 680, /* G_VECREDUCE_FMIN */ 682, /* G_VECREDUCE_FMAXIMUM */ 684, /* G_VECREDUCE_FMINIMUM */ 686, /* G_VECREDUCE_ADD */ 688, /* G_VECREDUCE_MUL */ 690, /* G_VECREDUCE_AND */ 692, /* G_VECREDUCE_OR */ 694, /* G_VECREDUCE_XOR */ 696, /* G_VECREDUCE_SMAX */ 698, /* G_VECREDUCE_SMIN */ 700, /* G_VECREDUCE_UMAX */ 702, /* G_VECREDUCE_UMIN */ 704, /* G_SBFX */ 706, /* G_UBFX */ 710, /* ADJCALLSTACKDOWN */ 714, /* ADJCALLSTACKUP */ 716, /* GETPCX */ 718, /* SELECT_CC_DFP_FCC */ 719, /* SELECT_CC_DFP_ICC */ 723, /* SELECT_CC_DFP_XCC */ 727, /* SELECT_CC_FP_FCC */ 731, /* SELECT_CC_FP_ICC */ 735, /* SELECT_CC_FP_XCC */ 739, /* SELECT_CC_Int_FCC */ 743, /* SELECT_CC_Int_ICC */ 747, /* SELECT_CC_Int_XCC */ 751, /* SELECT_CC_QFP_FCC */ 755, /* SELECT_CC_QFP_ICC */ 759, /* SELECT_CC_QFP_XCC */ 763, /* SET */ 767, /* SETX */ 769, /* ADDCCri */ 772, /* ADDCCrr */ 775, /* ADDCri */ 778, /* ADDCrr */ 781, /* ADDEri */ 784, /* ADDErr */ 787, /* ADDXC */ 790, /* ADDXCCC */ 793, /* ADDri */ 796, /* ADDrr */ 799, /* ALIGNADDR */ 802, /* ALIGNADDRL */ 805, /* ANDCCri */ 808, /* ANDCCrr */ 811, /* ANDNCCri */ 814, /* ANDNCCrr */ 817, /* ANDNri */ 820, /* ANDNrr */ 823, /* ANDri */ 826, /* ANDrr */ 829, /* ARRAY16 */ 832, /* ARRAY32 */ 835, /* ARRAY8 */ 838, /* BA */ 841, /* BCOND */ 842, /* BCONDA */ 844, /* BINDri */ 846, /* BINDrr */ 848, /* BMASK */ 850, /* BPFCC */ 853, /* BPFCCA */ 856, /* BPFCCANT */ 859, /* BPFCCNT */ 862, /* BPICC */ 865, /* BPICCA */ 867, /* BPICCANT */ 869, /* BPICCNT */ 871, /* BPR */ 873, /* BPRA */ 876, /* BPRANT */ 879, /* BPRNT */ 882, /* BPXCC */ 885, /* BPXCCA */ 887, /* BPXCCANT */ 889, /* BPXCCNT */ 891, /* BSHUFFLE */ 893, /* CALL */ 896, /* CALLri */ 897, /* CALLrr */ 899, /* CASAri */ 901, /* CASArr */ 905, /* CASXAri */ 910, /* CASXArr */ 914, /* CBCOND */ 919, /* CBCONDA */ 921, /* CMASK16 */ 923, /* CMASK32 */ 924, /* CMASK8 */ 925, /* DONE */ 926, /* EDGE16 */ 926, /* EDGE16L */ 929, /* EDGE16LN */ 932, /* EDGE16N */ 935, /* EDGE32 */ 938, /* EDGE32L */ 941, /* EDGE32LN */ 944, /* EDGE32N */ 947, /* EDGE8 */ 950, /* EDGE8L */ 953, /* EDGE8LN */ 956, /* EDGE8N */ 959, /* FABSD */ 962, /* FABSQ */ 964, /* FABSS */ 966, /* FADDD */ 968, /* FADDQ */ 971, /* FADDS */ 974, /* FALIGNADATA */ 977, /* FAND */ 980, /* FANDNOT1 */ 983, /* FANDNOT1S */ 986, /* FANDNOT2 */ 989, /* FANDNOT2S */ 992, /* FANDS */ 995, /* FBCOND */ 998, /* FBCONDA */ 1000, /* FBCONDA_V9 */ 1002, /* FBCOND_V9 */ 1004, /* FCHKSM16 */ 1006, /* FCMPD */ 1009, /* FCMPD_V9 */ 1011, /* FCMPEQ16 */ 1013, /* FCMPEQ32 */ 1016, /* FCMPGT16 */ 1019, /* FCMPGT32 */ 1022, /* FCMPLE16 */ 1025, /* FCMPLE32 */ 1028, /* FCMPNE16 */ 1031, /* FCMPNE32 */ 1034, /* FCMPQ */ 1037, /* FCMPQ_V9 */ 1039, /* FCMPS */ 1041, /* FCMPS_V9 */ 1043, /* FDIVD */ 1045, /* FDIVQ */ 1048, /* FDIVS */ 1051, /* FDMULQ */ 1054, /* FDTOI */ 1057, /* FDTOQ */ 1059, /* FDTOS */ 1061, /* FDTOX */ 1063, /* FEXPAND */ 1065, /* FHADDD */ 1067, /* FHADDS */ 1070, /* FHSUBD */ 1073, /* FHSUBS */ 1076, /* FITOD */ 1079, /* FITOQ */ 1081, /* FITOS */ 1083, /* FLCMPD */ 1085, /* FLCMPS */ 1088, /* FLUSH */ 1091, /* FLUSHW */ 1091, /* FLUSHri */ 1091, /* FLUSHrr */ 1093, /* FMEAN16 */ 1095, /* FMOVD */ 1098, /* FMOVD_FCC */ 1100, /* FMOVD_ICC */ 1104, /* FMOVD_XCC */ 1108, /* FMOVQ */ 1112, /* FMOVQ_FCC */ 1114, /* FMOVQ_ICC */ 1118, /* FMOVQ_XCC */ 1122, /* FMOVRD */ 1126, /* FMOVRQ */ 1131, /* FMOVRS */ 1136, /* FMOVS */ 1141, /* FMOVS_FCC */ 1143, /* FMOVS_ICC */ 1147, /* FMOVS_XCC */ 1151, /* FMUL8SUX16 */ 1155, /* FMUL8ULX16 */ 1158, /* FMUL8X16 */ 1161, /* FMUL8X16AL */ 1164, /* FMUL8X16AU */ 1167, /* FMULD */ 1170, /* FMULD8SUX16 */ 1173, /* FMULD8ULX16 */ 1176, /* FMULQ */ 1179, /* FMULS */ 1182, /* FNADDD */ 1185, /* FNADDS */ 1188, /* FNAND */ 1191, /* FNANDS */ 1194, /* FNEGD */ 1197, /* FNEGQ */ 1199, /* FNEGS */ 1201, /* FNHADDD */ 1203, /* FNHADDS */ 1206, /* FNMULD */ 1209, /* FNMULS */ 1212, /* FNOR */ 1215, /* FNORS */ 1218, /* FNOT1 */ 1221, /* FNOT1S */ 1223, /* FNOT2 */ 1225, /* FNOT2S */ 1227, /* FNSMULD */ 1229, /* FONE */ 1232, /* FONES */ 1234, /* FOR */ 1236, /* FORNOT1 */ 1239, /* FORNOT1S */ 1242, /* FORNOT2 */ 1245, /* FORNOT2S */ 1248, /* FORS */ 1251, /* FPACK16 */ 1254, /* FPACK32 */ 1256, /* FPACKFIX */ 1259, /* FPADD16 */ 1261, /* FPADD16S */ 1264, /* FPADD32 */ 1267, /* FPADD32S */ 1270, /* FPADD64 */ 1273, /* FPMERGE */ 1276, /* FPSUB16 */ 1279, /* FPSUB16S */ 1282, /* FPSUB32 */ 1285, /* FPSUB32S */ 1288, /* FQTOD */ 1291, /* FQTOI */ 1293, /* FQTOS */ 1295, /* FQTOX */ 1297, /* FSLAS16 */ 1299, /* FSLAS32 */ 1302, /* FSLL16 */ 1305, /* FSLL32 */ 1308, /* FSMULD */ 1311, /* FSQRTD */ 1314, /* FSQRTQ */ 1316, /* FSQRTS */ 1318, /* FSRA16 */ 1320, /* FSRA32 */ 1323, /* FSRC1 */ 1326, /* FSRC1S */ 1328, /* FSRC2 */ 1330, /* FSRC2S */ 1332, /* FSRL16 */ 1334, /* FSRL32 */ 1337, /* FSTOD */ 1340, /* FSTOI */ 1342, /* FSTOQ */ 1344, /* FSTOX */ 1346, /* FSUBD */ 1348, /* FSUBQ */ 1351, /* FSUBS */ 1354, /* FXNOR */ 1357, /* FXNORS */ 1360, /* FXOR */ 1363, /* FXORS */ 1366, /* FXTOD */ 1369, /* FXTOQ */ 1371, /* FXTOS */ 1373, /* FZERO */ 1375, /* FZEROS */ 1377, /* GDOP_LDXrr */ 1379, /* GDOP_LDrr */ 1383, /* JMPLri */ 1387, /* JMPLrr */ 1390, /* LDAri */ 1393, /* LDArr */ 1396, /* LDCSRri */ 1400, /* LDCSRrr */ 1402, /* LDCri */ 1404, /* LDCrr */ 1407, /* LDDAri */ 1410, /* LDDArr */ 1413, /* LDDCri */ 1417, /* LDDCrr */ 1420, /* LDDFAri */ 1423, /* LDDFArr */ 1426, /* LDDFri */ 1430, /* LDDFrr */ 1433, /* LDDri */ 1436, /* LDDrr */ 1439, /* LDFAri */ 1442, /* LDFArr */ 1445, /* LDFSRri */ 1449, /* LDFSRrr */ 1451, /* LDFri */ 1453, /* LDFrr */ 1456, /* LDQFAri */ 1459, /* LDQFArr */ 1462, /* LDQFri */ 1466, /* LDQFrr */ 1469, /* LDSBAri */ 1472, /* LDSBArr */ 1475, /* LDSBri */ 1479, /* LDSBrr */ 1482, /* LDSHAri */ 1485, /* LDSHArr */ 1488, /* LDSHri */ 1492, /* LDSHrr */ 1495, /* LDSTUBAri */ 1498, /* LDSTUBArr */ 1501, /* LDSTUBri */ 1505, /* LDSTUBrr */ 1508, /* LDSWAri */ 1511, /* LDSWArr */ 1514, /* LDSWri */ 1518, /* LDSWrr */ 1521, /* LDUBAri */ 1524, /* LDUBArr */ 1527, /* LDUBri */ 1531, /* LDUBrr */ 1534, /* LDUHAri */ 1537, /* LDUHArr */ 1540, /* LDUHri */ 1544, /* LDUHrr */ 1547, /* LDXAri */ 1550, /* LDXArr */ 1553, /* LDXFSRri */ 1557, /* LDXFSRrr */ 1559, /* LDXri */ 1561, /* LDXrr */ 1564, /* LDri */ 1567, /* LDrr */ 1570, /* LZCNT */ 1573, /* MEMBARi */ 1575, /* MOVDTOX */ 1576, /* MOVFCCri */ 1578, /* MOVFCCrr */ 1582, /* MOVICCri */ 1586, /* MOVICCrr */ 1590, /* MOVRri */ 1594, /* MOVRrr */ 1599, /* MOVSTOSW */ 1604, /* MOVSTOUW */ 1606, /* MOVWTOS */ 1608, /* MOVXCCri */ 1610, /* MOVXCCrr */ 1614, /* MOVXTOD */ 1618, /* MULSCCri */ 1620, /* MULSCCrr */ 1623, /* MULXri */ 1626, /* MULXrr */ 1629, /* NOP */ 1632, /* ORCCri */ 1632, /* ORCCrr */ 1635, /* ORNCCri */ 1638, /* ORNCCrr */ 1641, /* ORNri */ 1644, /* ORNrr */ 1647, /* ORri */ 1650, /* ORrr */ 1653, /* PDIST */ 1656, /* PDISTN */ 1659, /* POPCrr */ 1662, /* PREFETCHAi */ 1664, /* PREFETCHAr */ 1667, /* PREFETCHi */ 1671, /* PREFETCHr */ 1674, /* PWRPSRri */ 1677, /* PWRPSRrr */ 1679, /* RDASR */ 1681, /* RDFQ */ 1683, /* RDPR */ 1684, /* RDPSR */ 1686, /* RDTBR */ 1687, /* RDWIM */ 1688, /* RESTORED */ 1689, /* RESTOREri */ 1689, /* RESTORErr */ 1692, /* RET */ 1695, /* RETL */ 1696, /* RETRY */ 1697, /* RETTri */ 1697, /* RETTrr */ 1699, /* SAVED */ 1701, /* SAVEri */ 1701, /* SAVErr */ 1704, /* SDIVCCri */ 1707, /* SDIVCCrr */ 1710, /* SDIVXri */ 1713, /* SDIVXrr */ 1716, /* SDIVri */ 1719, /* SDIVrr */ 1722, /* SETHIi */ 1725, /* SHUTDOWN */ 1727, /* SIAM */ 1727, /* SIR */ 1727, /* SLLXri */ 1728, /* SLLXrr */ 1731, /* SLLri */ 1734, /* SLLrr */ 1737, /* SMACri */ 1740, /* SMACrr */ 1744, /* SMULCCri */ 1748, /* SMULCCrr */ 1751, /* SMULri */ 1754, /* SMULrr */ 1757, /* SRAXri */ 1760, /* SRAXrr */ 1763, /* SRAri */ 1766, /* SRArr */ 1769, /* SRLXri */ 1772, /* SRLXrr */ 1775, /* SRLri */ 1778, /* SRLrr */ 1781, /* STAri */ 1784, /* STArr */ 1787, /* STBAR */ 1791, /* STBAri */ 1791, /* STBArr */ 1794, /* STBri */ 1798, /* STBrr */ 1801, /* STCSRri */ 1804, /* STCSRrr */ 1806, /* STCri */ 1808, /* STCrr */ 1811, /* STDAri */ 1814, /* STDArr */ 1817, /* STDCQri */ 1821, /* STDCQrr */ 1823, /* STDCri */ 1825, /* STDCrr */ 1828, /* STDFAri */ 1831, /* STDFArr */ 1834, /* STDFQri */ 1838, /* STDFQrr */ 1840, /* STDFri */ 1842, /* STDFrr */ 1845, /* STDri */ 1848, /* STDrr */ 1851, /* STFAri */ 1854, /* STFArr */ 1857, /* STFSRri */ 1861, /* STFSRrr */ 1863, /* STFri */ 1865, /* STFrr */ 1868, /* STHAri */ 1871, /* STHArr */ 1874, /* STHri */ 1878, /* STHrr */ 1881, /* STQFAri */ 1884, /* STQFArr */ 1887, /* STQFri */ 1891, /* STQFrr */ 1894, /* STXAri */ 1897, /* STXArr */ 1900, /* STXFSRri */ 1904, /* STXFSRrr */ 1906, /* STXri */ 1908, /* STXrr */ 1911, /* STri */ 1914, /* STrr */ 1917, /* SUBCCri */ 1920, /* SUBCCrr */ 1923, /* SUBCri */ 1926, /* SUBCrr */ 1929, /* SUBEri */ 1932, /* SUBErr */ 1935, /* SUBri */ 1938, /* SUBrr */ 1941, /* SWAPAri */ 1944, /* SWAPArr */ 1948, /* SWAPri */ 1953, /* SWAPrr */ 1957, /* TA1 */ 1961, /* TA3 */ 1961, /* TA5 */ 1961, /* TADDCCTVri */ 1961, /* TADDCCTVrr */ 1964, /* TADDCCri */ 1967, /* TADDCCrr */ 1970, /* TAIL_CALL */ 1973, /* TAIL_CALLri */ 1974, /* TICCri */ 1976, /* TICCrr */ 1979, /* TLS_ADDrr */ 1982, /* TLS_CALL */ 1986, /* TLS_LDXrr */ 1988, /* TLS_LDrr */ 1992, /* TRAPri */ 1996, /* TRAPrr */ 1999, /* TSUBCCTVri */ 2002, /* TSUBCCTVrr */ 2005, /* TSUBCCri */ 2008, /* TSUBCCrr */ 2011, /* TXCCri */ 2014, /* TXCCrr */ 2017, /* UDIVCCri */ 2020, /* UDIVCCrr */ 2023, /* UDIVXri */ 2026, /* UDIVXrr */ 2029, /* UDIVri */ 2032, /* UDIVrr */ 2035, /* UMACri */ 2038, /* UMACrr */ 2042, /* UMULCCri */ 2046, /* UMULCCrr */ 2049, /* UMULXHI */ 2052, /* UMULri */ 2055, /* UMULrr */ 2058, /* UNIMP */ 2061, /* V9FCMPD */ 2062, /* V9FCMPED */ 2065, /* V9FCMPEQ */ 2068, /* V9FCMPES */ 2071, /* V9FCMPQ */ 2074, /* V9FCMPS */ 2077, /* V9FMOVD_FCC */ 2080, /* V9FMOVQ_FCC */ 2085, /* V9FMOVS_FCC */ 2090, /* V9MOVFCCri */ 2095, /* V9MOVFCCrr */ 2100, /* WRASRri */ 2105, /* WRASRrr */ 2108, /* WRPRri */ 2111, /* WRPRrr */ 2114, /* WRPSRri */ 2117, /* WRPSRrr */ 2119, /* WRTBRri */ 2121, /* WRTBRrr */ 2123, /* WRWIMri */ 2125, /* WRWIMrr */ 2127, /* XMULX */ 2129, /* XMULXHI */ 2132, /* XNORCCri */ 2135, /* XNORCCrr */ 2138, /* XNORri */ 2141, /* XNORrr */ 2144, /* XORCCri */ 2147, /* XORCCrr */ 2150, /* XORri */ 2153, /* XORrr */ 2156, }; using namespace OpTypes; static const int8_t OpcodeOperandTypes[] = { /* PHI */ -1, /* INLINEASM */ /* INLINEASM_BR */ /* CFI_INSTRUCTION */ i32imm, /* EH_LABEL */ i32imm, /* GC_LABEL */ i32imm, /* ANNOTATION_LABEL */ i32imm, /* KILL */ /* EXTRACT_SUBREG */ -1, -1, i32imm, /* INSERT_SUBREG */ -1, -1, -1, i32imm, /* IMPLICIT_DEF */ -1, /* SUBREG_TO_REG */ -1, -1, -1, i32imm, /* COPY_TO_REGCLASS */ -1, -1, i32imm, /* DBG_VALUE */ /* DBG_VALUE_LIST */ /* DBG_INSTR_REF */ /* DBG_PHI */ /* DBG_LABEL */ -1, /* REG_SEQUENCE */ -1, -1, /* COPY */ -1, -1, /* BUNDLE */ /* LIFETIME_START */ i32imm, /* LIFETIME_END */ i32imm, /* PSEUDO_PROBE */ i64imm, i64imm, i8imm, i32imm, /* ARITH_FENCE */ -1, -1, /* STACKMAP */ i64imm, i32imm, /* FENTRY_CALL */ /* PATCHPOINT */ -1, i64imm, i32imm, -1, i32imm, i32imm, /* LOAD_STACK_GUARD */ -1, /* PREALLOCATED_SETUP */ i32imm, /* PREALLOCATED_ARG */ -1, i32imm, i32imm, /* STATEPOINT */ /* LOCAL_ESCAPE */ -1, i32imm, /* FAULTING_OP */ -1, /* PATCHABLE_OP */ /* PATCHABLE_FUNCTION_ENTER */ /* PATCHABLE_RET */ /* PATCHABLE_FUNCTION_EXIT */ /* PATCHABLE_TAIL_CALL */ /* PATCHABLE_EVENT_CALL */ -1, -1, /* PATCHABLE_TYPED_EVENT_CALL */ -1, -1, -1, /* ICALL_BRANCH_FUNNEL */ /* FAKE_USE */ /* MEMBARRIER */ /* JUMP_TABLE_DEBUG_INFO */ i64imm, /* CONVERGENCECTRL_ENTRY */ -1, /* CONVERGENCECTRL_ANCHOR */ -1, /* CONVERGENCECTRL_LOOP */ -1, -1, /* CONVERGENCECTRL_GLUE */ -1, /* G_ASSERT_SEXT */ type0, type0, untyped_imm_0, /* G_ASSERT_ZEXT */ type0, type0, untyped_imm_0, /* G_ASSERT_ALIGN */ type0, type0, untyped_imm_0, /* G_ADD */ type0, type0, type0, /* G_SUB */ type0, type0, type0, /* G_MUL */ type0, type0, type0, /* G_SDIV */ type0, type0, type0, /* G_UDIV */ type0, type0, type0, /* G_SREM */ type0, type0, type0, /* G_UREM */ type0, type0, type0, /* G_SDIVREM */ type0, type0, type0, type0, /* G_UDIVREM */ type0, type0, type0, type0, /* G_AND */ type0, type0, type0, /* G_OR */ type0, type0, type0, /* G_XOR */ type0, type0, type0, /* G_IMPLICIT_DEF */ type0, /* G_PHI */ type0, /* G_FRAME_INDEX */ type0, -1, /* G_GLOBAL_VALUE */ type0, -1, /* G_PTRAUTH_GLOBAL_VALUE */ type0, -1, i32imm, type1, i64imm, /* G_CONSTANT_POOL */ type0, -1, /* G_EXTRACT */ type0, type1, untyped_imm_0, /* G_UNMERGE_VALUES */ type0, type1, /* G_INSERT */ type0, type0, type1, untyped_imm_0, /* G_MERGE_VALUES */ type0, type1, /* G_BUILD_VECTOR */ type0, type1, /* G_BUILD_VECTOR_TRUNC */ type0, type1, /* G_CONCAT_VECTORS */ type0, type1, /* G_PTRTOINT */ type0, type1, /* G_INTTOPTR */ type0, type1, /* G_BITCAST */ type0, type1, /* G_FREEZE */ type0, type0, /* G_CONSTANT_FOLD_BARRIER */ type0, type0, /* G_INTRINSIC_FPTRUNC_ROUND */ type0, type1, i32imm, /* G_INTRINSIC_TRUNC */ type0, type0, /* G_INTRINSIC_ROUND */ type0, type0, /* G_INTRINSIC_LRINT */ type0, type1, /* G_INTRINSIC_LLRINT */ type0, type1, /* G_INTRINSIC_ROUNDEVEN */ type0, type0, /* G_READCYCLECOUNTER */ type0, /* G_READSTEADYCOUNTER */ type0, /* G_LOAD */ type0, ptype1, /* G_SEXTLOAD */ type0, ptype1, /* G_ZEXTLOAD */ type0, ptype1, /* G_INDEXED_LOAD */ type0, ptype1, ptype1, type2, -1, /* G_INDEXED_SEXTLOAD */ type0, ptype1, ptype1, type2, -1, /* G_INDEXED_ZEXTLOAD */ type0, ptype1, ptype1, type2, -1, /* G_STORE */ type0, ptype1, /* G_INDEXED_STORE */ ptype0, type1, ptype0, ptype2, -1, /* G_ATOMIC_CMPXCHG_WITH_SUCCESS */ type0, type1, type2, type0, type0, /* G_ATOMIC_CMPXCHG */ type0, ptype1, type0, type0, /* G_ATOMICRMW_XCHG */ type0, ptype1, type0, /* G_ATOMICRMW_ADD */ type0, ptype1, type0, /* G_ATOMICRMW_SUB */ type0, ptype1, type0, /* G_ATOMICRMW_AND */ type0, ptype1, type0, /* G_ATOMICRMW_NAND */ type0, ptype1, type0, /* G_ATOMICRMW_OR */ type0, ptype1, type0, /* G_ATOMICRMW_XOR */ type0, ptype1, type0, /* G_ATOMICRMW_MAX */ type0, ptype1, type0, /* G_ATOMICRMW_MIN */ type0, ptype1, type0, /* G_ATOMICRMW_UMAX */ type0, ptype1, type0, /* G_ATOMICRMW_UMIN */ type0, ptype1, type0, /* G_ATOMICRMW_FADD */ type0, ptype1, type0, /* G_ATOMICRMW_FSUB */ type0, ptype1, type0, /* G_ATOMICRMW_FMAX */ type0, ptype1, type0, /* G_ATOMICRMW_FMIN */ type0, ptype1, type0, /* G_ATOMICRMW_UINC_WRAP */ type0, ptype1, type0, /* G_ATOMICRMW_UDEC_WRAP */ type0, ptype1, type0, /* G_FENCE */ i32imm, i32imm, /* G_PREFETCH */ ptype0, i32imm, i32imm, i32imm, /* G_BRCOND */ type0, -1, /* G_BRINDIRECT */ type0, /* G_INVOKE_REGION_START */ /* G_INTRINSIC */ -1, /* G_INTRINSIC_W_SIDE_EFFECTS */ -1, /* G_INTRINSIC_CONVERGENT */ -1, /* G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS */ -1, /* G_ANYEXT */ type0, type1, /* G_TRUNC */ type0, type1, /* G_CONSTANT */ type0, -1, /* G_FCONSTANT */ type0, -1, /* G_VASTART */ type0, /* G_VAARG */ type0, type1, -1, /* G_SEXT */ type0, type1, /* G_SEXT_INREG */ type0, type0, untyped_imm_0, /* G_ZEXT */ type0, type1, /* G_SHL */ type0, type0, type1, /* G_LSHR */ type0, type0, type1, /* G_ASHR */ type0, type0, type1, /* G_FSHL */ type0, type0, type0, type1, /* G_FSHR */ type0, type0, type0, type1, /* G_ROTR */ type0, type0, type1, /* G_ROTL */ type0, type0, type1, /* G_ICMP */ type0, -1, type1, type1, /* G_FCMP */ type0, -1, type1, type1, /* G_SCMP */ type0, type1, type1, /* G_UCMP */ type0, type1, type1, /* G_SELECT */ type0, type1, type0, type0, /* G_UADDO */ type0, type1, type0, type0, /* G_UADDE */ type0, type1, type0, type0, type1, /* G_USUBO */ type0, type1, type0, type0, /* G_USUBE */ type0, type1, type0, type0, type1, /* G_SADDO */ type0, type1, type0, type0, /* G_SADDE */ type0, type1, type0, type0, type1, /* G_SSUBO */ type0, type1, type0, type0, /* G_SSUBE */ type0, type1, type0, type0, type1, /* G_UMULO */ type0, type1, type0, type0, /* G_SMULO */ type0, type1, type0, type0, /* G_UMULH */ type0, type0, type0, /* G_SMULH */ type0, type0, type0, /* G_UADDSAT */ type0, type0, type0, /* G_SADDSAT */ type0, type0, type0, /* G_USUBSAT */ type0, type0, type0, /* G_SSUBSAT */ type0, type0, type0, /* G_USHLSAT */ type0, type0, type1, /* G_SSHLSAT */ type0, type0, type1, /* G_SMULFIX */ type0, type0, type0, untyped_imm_0, /* G_UMULFIX */ type0, type0, type0, untyped_imm_0, /* G_SMULFIXSAT */ type0, type0, type0, untyped_imm_0, /* G_UMULFIXSAT */ type0, type0, type0, untyped_imm_0, /* G_SDIVFIX */ type0, type0, type0, untyped_imm_0, /* G_UDIVFIX */ type0, type0, type0, untyped_imm_0, /* G_SDIVFIXSAT */ type0, type0, type0, untyped_imm_0, /* G_UDIVFIXSAT */ type0, type0, type0, untyped_imm_0, /* G_FADD */ type0, type0, type0, /* G_FSUB */ type0, type0, type0, /* G_FMUL */ type0, type0, type0, /* G_FMA */ type0, type0, type0, type0, /* G_FMAD */ type0, type0, type0, type0, /* G_FDIV */ type0, type0, type0, /* G_FREM */ type0, type0, type0, /* G_FPOW */ type0, type0, type0, /* G_FPOWI */ type0, type0, type1, /* G_FEXP */ type0, type0, /* G_FEXP2 */ type0, type0, /* G_FEXP10 */ type0, type0, /* G_FLOG */ type0, type0, /* G_FLOG2 */ type0, type0, /* G_FLOG10 */ type0, type0, /* G_FLDEXP */ type0, type0, type1, /* G_FFREXP */ type0, type1, type0, /* G_FNEG */ type0, type0, /* G_FPEXT */ type0, type1, /* G_FPTRUNC */ type0, type1, /* G_FPTOSI */ type0, type1, /* G_FPTOUI */ type0, type1, /* G_SITOFP */ type0, type1, /* G_UITOFP */ type0, type1, /* G_FABS */ type0, type0, /* G_FCOPYSIGN */ type0, type0, type1, /* G_IS_FPCLASS */ type0, type1, -1, /* G_FCANONICALIZE */ type0, type0, /* G_FMINNUM */ type0, type0, type0, /* G_FMAXNUM */ type0, type0, type0, /* G_FMINNUM_IEEE */ type0, type0, type0, /* G_FMAXNUM_IEEE */ type0, type0, type0, /* G_FMINIMUM */ type0, type0, type0, /* G_FMAXIMUM */ type0, type0, type0, /* G_GET_FPENV */ type0, /* G_SET_FPENV */ type0, /* G_RESET_FPENV */ /* G_GET_FPMODE */ type0, /* G_SET_FPMODE */ type0, /* G_RESET_FPMODE */ /* G_PTR_ADD */ ptype0, ptype0, type1, /* G_PTRMASK */ ptype0, ptype0, type1, /* G_SMIN */ type0, type0, type0, /* G_SMAX */ type0, type0, type0, /* G_UMIN */ type0, type0, type0, /* G_UMAX */ type0, type0, type0, /* G_ABS */ type0, type0, /* G_LROUND */ type0, type1, /* G_LLROUND */ type0, type1, /* G_BR */ -1, /* G_BRJT */ ptype0, -1, type1, /* G_VSCALE */ type0, -1, /* G_INSERT_SUBVECTOR */ type0, type0, type1, untyped_imm_0, /* G_EXTRACT_SUBVECTOR */ type0, type0, untyped_imm_0, /* G_INSERT_VECTOR_ELT */ type0, type0, type1, type2, /* G_EXTRACT_VECTOR_ELT */ type0, type1, type2, /* G_SHUFFLE_VECTOR */ type0, type1, type1, -1, /* G_SPLAT_VECTOR */ type0, type1, /* G_VECTOR_COMPRESS */ type0, type0, type1, type0, /* G_CTTZ */ type0, type1, /* G_CTTZ_ZERO_UNDEF */ type0, type1, /* G_CTLZ */ type0, type1, /* G_CTLZ_ZERO_UNDEF */ type0, type1, /* G_CTPOP */ type0, type1, /* G_BSWAP */ type0, type0, /* G_BITREVERSE */ type0, type0, /* G_FCEIL */ type0, type0, /* G_FCOS */ type0, type0, /* G_FSIN */ type0, type0, /* G_FTAN */ type0, type0, /* G_FACOS */ type0, type0, /* G_FASIN */ type0, type0, /* G_FATAN */ type0, type0, /* G_FCOSH */ type0, type0, /* G_FSINH */ type0, type0, /* G_FTANH */ type0, type0, /* G_FSQRT */ type0, type0, /* G_FFLOOR */ type0, type0, /* G_FRINT */ type0, type0, /* G_FNEARBYINT */ type0, type0, /* G_ADDRSPACE_CAST */ type0, type1, /* G_BLOCK_ADDR */ type0, -1, /* G_JUMP_TABLE */ type0, -1, /* G_DYN_STACKALLOC */ ptype0, type1, i32imm, /* G_STACKSAVE */ ptype0, /* G_STACKRESTORE */ ptype0, /* G_STRICT_FADD */ type0, type0, type0, /* G_STRICT_FSUB */ type0, type0, type0, /* G_STRICT_FMUL */ type0, type0, type0, /* G_STRICT_FDIV */ type0, type0, type0, /* G_STRICT_FREM */ type0, type0, type0, /* G_STRICT_FMA */ type0, type0, type0, type0, /* G_STRICT_FSQRT */ type0, type0, /* G_STRICT_FLDEXP */ type0, type0, type1, /* G_READ_REGISTER */ type0, -1, /* G_WRITE_REGISTER */ -1, type0, /* G_MEMCPY */ ptype0, ptype1, type2, untyped_imm_0, /* G_MEMCPY_INLINE */ ptype0, ptype1, type2, /* G_MEMMOVE */ ptype0, ptype1, type2, untyped_imm_0, /* G_MEMSET */ ptype0, type1, type2, untyped_imm_0, /* G_BZERO */ ptype0, type1, untyped_imm_0, /* G_TRAP */ /* G_DEBUGTRAP */ /* G_UBSANTRAP */ i8imm, /* G_VECREDUCE_SEQ_FADD */ type0, type1, type2, /* G_VECREDUCE_SEQ_FMUL */ type0, type1, type2, /* G_VECREDUCE_FADD */ type0, type1, /* G_VECREDUCE_FMUL */ type0, type1, /* G_VECREDUCE_FMAX */ type0, type1, /* G_VECREDUCE_FMIN */ type0, type1, /* G_VECREDUCE_FMAXIMUM */ type0, type1, /* G_VECREDUCE_FMINIMUM */ type0, type1, /* G_VECREDUCE_ADD */ type0, type1, /* G_VECREDUCE_MUL */ type0, type1, /* G_VECREDUCE_AND */ type0, type1, /* G_VECREDUCE_OR */ type0, type1, /* G_VECREDUCE_XOR */ type0, type1, /* G_VECREDUCE_SMAX */ type0, type1, /* G_VECREDUCE_SMIN */ type0, type1, /* G_VECREDUCE_UMAX */ type0, type1, /* G_VECREDUCE_UMIN */ type0, type1, /* G_SBFX */ type0, type0, type1, type1, /* G_UBFX */ type0, type0, type1, type1, /* ADJCALLSTACKDOWN */ i32imm, i32imm, /* ADJCALLSTACKUP */ i32imm, i32imm, /* GETPCX */ getPCX, /* SELECT_CC_DFP_FCC */ DFPRegs, DFPRegs, DFPRegs, i32imm, /* SELECT_CC_DFP_ICC */ DFPRegs, DFPRegs, DFPRegs, i32imm, /* SELECT_CC_DFP_XCC */ DFPRegs, DFPRegs, DFPRegs, i32imm, /* SELECT_CC_FP_FCC */ FPRegs, FPRegs, FPRegs, i32imm, /* SELECT_CC_FP_ICC */ FPRegs, FPRegs, FPRegs, i32imm, /* SELECT_CC_FP_XCC */ FPRegs, FPRegs, FPRegs, i32imm, /* SELECT_CC_Int_FCC */ IntRegs, IntRegs, IntRegs, i32imm, /* SELECT_CC_Int_ICC */ IntRegs, IntRegs, IntRegs, i32imm, /* SELECT_CC_Int_XCC */ IntRegs, IntRegs, IntRegs, i32imm, /* SELECT_CC_QFP_FCC */ QFPRegs, QFPRegs, QFPRegs, i32imm, /* SELECT_CC_QFP_ICC */ QFPRegs, QFPRegs, QFPRegs, i32imm, /* SELECT_CC_QFP_XCC */ QFPRegs, QFPRegs, QFPRegs, i32imm, /* SET */ IntRegs, i32imm, /* SETX */ I64Regs, i64imm, I64Regs, /* ADDCCri */ IntRegs, IntRegs, simm13Op, /* ADDCCrr */ IntRegs, IntRegs, IntRegs, /* ADDCri */ IntRegs, IntRegs, simm13Op, /* ADDCrr */ IntRegs, IntRegs, IntRegs, /* ADDEri */ IntRegs, IntRegs, simm13Op, /* ADDErr */ IntRegs, IntRegs, IntRegs, /* ADDXC */ I64Regs, I64Regs, I64Regs, /* ADDXCCC */ I64Regs, I64Regs, I64Regs, /* ADDri */ IntRegs, IntRegs, simm13Op, /* ADDrr */ IntRegs, IntRegs, IntRegs, /* ALIGNADDR */ I64Regs, I64Regs, I64Regs, /* ALIGNADDRL */ I64Regs, I64Regs, I64Regs, /* ANDCCri */ IntRegs, IntRegs, simm13Op, /* ANDCCrr */ IntRegs, IntRegs, IntRegs, /* ANDNCCri */ IntRegs, IntRegs, simm13Op, /* ANDNCCrr */ IntRegs, IntRegs, IntRegs, /* ANDNri */ IntRegs, IntRegs, simm13Op, /* ANDNrr */ IntRegs, IntRegs, IntRegs, /* ANDri */ IntRegs, IntRegs, simm13Op, /* ANDrr */ IntRegs, IntRegs, IntRegs, /* ARRAY16 */ I64Regs, I64Regs, I64Regs, /* ARRAY32 */ I64Regs, I64Regs, I64Regs, /* ARRAY8 */ I64Regs, I64Regs, I64Regs, /* BA */ brtarget, /* BCOND */ brtarget, CCOp, /* BCONDA */ brtarget, CCOp, /* BINDri */ -1, i32imm, /* BINDrr */ -1, -1, /* BMASK */ I64Regs, I64Regs, I64Regs, /* BPFCC */ bprtarget, CCOp, FCCRegs, /* BPFCCA */ bprtarget, CCOp, FCCRegs, /* BPFCCANT */ bprtarget, CCOp, FCCRegs, /* BPFCCNT */ bprtarget, CCOp, FCCRegs, /* BPICC */ bprtarget, CCOp, /* BPICCA */ bprtarget, CCOp, /* BPICCANT */ bprtarget, CCOp, /* BPICCNT */ bprtarget, CCOp, /* BPR */ bprtarget16, RegCCOp, I64Regs, /* BPRA */ bprtarget16, RegCCOp, I64Regs, /* BPRANT */ bprtarget16, RegCCOp, I64Regs, /* BPRNT */ bprtarget16, RegCCOp, I64Regs, /* BPXCC */ bprtarget, CCOp, /* BPXCCA */ bprtarget, CCOp, /* BPXCCANT */ bprtarget, CCOp, /* BPXCCNT */ bprtarget, CCOp, /* BSHUFFLE */ DFPRegs, DFPRegs, DFPRegs, /* CALL */ calltarget, /* CALLri */ -1, i32imm, /* CALLrr */ -1, -1, /* CASAri */ IntRegs, IntRegs, IntRegs, IntRegs, /* CASArr */ IntRegs, IntRegs, IntRegs, IntRegs, ASITag, /* CASXAri */ I64Regs, I64Regs, I64Regs, I64Regs, /* CASXArr */ I64Regs, I64Regs, I64Regs, I64Regs, ASITag, /* CBCOND */ brtarget, CCOp, /* CBCONDA */ brtarget, CCOp, /* CMASK16 */ I64Regs, /* CMASK32 */ I64Regs, /* CMASK8 */ I64Regs, /* DONE */ /* EDGE16 */ I64Regs, I64Regs, I64Regs, /* EDGE16L */ I64Regs, I64Regs, I64Regs, /* EDGE16LN */ I64Regs, I64Regs, I64Regs, /* EDGE16N */ I64Regs, I64Regs, I64Regs, /* EDGE32 */ I64Regs, I64Regs, I64Regs, /* EDGE32L */ I64Regs, I64Regs, I64Regs, /* EDGE32LN */ I64Regs, I64Regs, I64Regs, /* EDGE32N */ I64Regs, I64Regs, I64Regs, /* EDGE8 */ I64Regs, I64Regs, I64Regs, /* EDGE8L */ I64Regs, I64Regs, I64Regs, /* EDGE8LN */ I64Regs, I64Regs, I64Regs, /* EDGE8N */ I64Regs, I64Regs, I64Regs, /* FABSD */ DFPRegs, DFPRegs, /* FABSQ */ QFPRegs, QFPRegs, /* FABSS */ FPRegs, FPRegs, /* FADDD */ DFPRegs, DFPRegs, DFPRegs, /* FADDQ */ QFPRegs, QFPRegs, QFPRegs, /* FADDS */ FPRegs, FPRegs, FPRegs, /* FALIGNADATA */ DFPRegs, DFPRegs, DFPRegs, /* FAND */ DFPRegs, DFPRegs, DFPRegs, /* FANDNOT1 */ DFPRegs, DFPRegs, DFPRegs, /* FANDNOT1S */ FPRegs, FPRegs, FPRegs, /* FANDNOT2 */ DFPRegs, DFPRegs, DFPRegs, /* FANDNOT2S */ FPRegs, FPRegs, FPRegs, /* FANDS */ FPRegs, FPRegs, FPRegs, /* FBCOND */ brtarget, CCOp, /* FBCONDA */ brtarget, CCOp, /* FBCONDA_V9 */ bprtarget, CCOp, /* FBCOND_V9 */ bprtarget, CCOp, /* FCHKSM16 */ DFPRegs, DFPRegs, DFPRegs, /* FCMPD */ DFPRegs, DFPRegs, /* FCMPD_V9 */ DFPRegs, DFPRegs, /* FCMPEQ16 */ I64Regs, DFPRegs, DFPRegs, /* FCMPEQ32 */ I64Regs, DFPRegs, DFPRegs, /* FCMPGT16 */ I64Regs, DFPRegs, DFPRegs, /* FCMPGT32 */ I64Regs, DFPRegs, DFPRegs, /* FCMPLE16 */ I64Regs, DFPRegs, DFPRegs, /* FCMPLE32 */ I64Regs, DFPRegs, DFPRegs, /* FCMPNE16 */ I64Regs, DFPRegs, DFPRegs, /* FCMPNE32 */ I64Regs, DFPRegs, DFPRegs, /* FCMPQ */ QFPRegs, QFPRegs, /* FCMPQ_V9 */ QFPRegs, QFPRegs, /* FCMPS */ FPRegs, FPRegs, /* FCMPS_V9 */ FPRegs, FPRegs, /* FDIVD */ DFPRegs, DFPRegs, DFPRegs, /* FDIVQ */ QFPRegs, QFPRegs, QFPRegs, /* FDIVS */ FPRegs, FPRegs, FPRegs, /* FDMULQ */ QFPRegs, DFPRegs, DFPRegs, /* FDTOI */ FPRegs, DFPRegs, /* FDTOQ */ QFPRegs, DFPRegs, /* FDTOS */ FPRegs, DFPRegs, /* FDTOX */ DFPRegs, DFPRegs, /* FEXPAND */ DFPRegs, DFPRegs, /* FHADDD */ DFPRegs, DFPRegs, DFPRegs, /* FHADDS */ DFPRegs, DFPRegs, DFPRegs, /* FHSUBD */ DFPRegs, DFPRegs, DFPRegs, /* FHSUBS */ DFPRegs, DFPRegs, DFPRegs, /* FITOD */ DFPRegs, FPRegs, /* FITOQ */ QFPRegs, FPRegs, /* FITOS */ FPRegs, FPRegs, /* FLCMPD */ FCCRegs, DFPRegs, DFPRegs, /* FLCMPS */ FCCRegs, DFPRegs, DFPRegs, /* FLUSH */ /* FLUSHW */ /* FLUSHri */ -1, i32imm, /* FLUSHrr */ -1, -1, /* FMEAN16 */ DFPRegs, DFPRegs, DFPRegs, /* FMOVD */ DFPRegs, DFPRegs, /* FMOVD_FCC */ DFPRegs, DFPRegs, DFPRegs, CCOp, /* FMOVD_ICC */ DFPRegs, DFPRegs, DFPRegs, CCOp, /* FMOVD_XCC */ DFPRegs, DFPRegs, DFPRegs, CCOp, /* FMOVQ */ QFPRegs, QFPRegs, /* FMOVQ_FCC */ QFPRegs, QFPRegs, QFPRegs, CCOp, /* FMOVQ_ICC */ QFPRegs, QFPRegs, QFPRegs, CCOp, /* FMOVQ_XCC */ QFPRegs, QFPRegs, QFPRegs, CCOp, /* FMOVRD */ DFPRegs, I64Regs, DFPRegs, DFPRegs, RegCCOp, /* FMOVRQ */ QFPRegs, I64Regs, QFPRegs, QFPRegs, RegCCOp, /* FMOVRS */ FPRegs, I64Regs, FPRegs, FPRegs, RegCCOp, /* FMOVS */ FPRegs, FPRegs, /* FMOVS_FCC */ FPRegs, FPRegs, FPRegs, CCOp, /* FMOVS_ICC */ FPRegs, FPRegs, FPRegs, CCOp, /* FMOVS_XCC */ FPRegs, FPRegs, FPRegs, CCOp, /* FMUL8SUX16 */ DFPRegs, DFPRegs, DFPRegs, /* FMUL8ULX16 */ DFPRegs, DFPRegs, DFPRegs, /* FMUL8X16 */ DFPRegs, DFPRegs, DFPRegs, /* FMUL8X16AL */ DFPRegs, DFPRegs, DFPRegs, /* FMUL8X16AU */ DFPRegs, DFPRegs, DFPRegs, /* FMULD */ DFPRegs, DFPRegs, DFPRegs, /* FMULD8SUX16 */ DFPRegs, DFPRegs, DFPRegs, /* FMULD8ULX16 */ DFPRegs, DFPRegs, DFPRegs, /* FMULQ */ QFPRegs, QFPRegs, QFPRegs, /* FMULS */ FPRegs, FPRegs, FPRegs, /* FNADDD */ DFPRegs, DFPRegs, DFPRegs, /* FNADDS */ DFPRegs, DFPRegs, DFPRegs, /* FNAND */ DFPRegs, DFPRegs, DFPRegs, /* FNANDS */ FPRegs, FPRegs, FPRegs, /* FNEGD */ DFPRegs, DFPRegs, /* FNEGQ */ QFPRegs, QFPRegs, /* FNEGS */ FPRegs, FPRegs, /* FNHADDD */ DFPRegs, DFPRegs, DFPRegs, /* FNHADDS */ DFPRegs, DFPRegs, DFPRegs, /* FNMULD */ DFPRegs, DFPRegs, DFPRegs, /* FNMULS */ DFPRegs, DFPRegs, DFPRegs, /* FNOR */ DFPRegs, DFPRegs, DFPRegs, /* FNORS */ FPRegs, FPRegs, FPRegs, /* FNOT1 */ DFPRegs, DFPRegs, /* FNOT1S */ FPRegs, FPRegs, /* FNOT2 */ DFPRegs, DFPRegs, /* FNOT2S */ FPRegs, FPRegs, /* FNSMULD */ DFPRegs, DFPRegs, DFPRegs, /* FONE */ DFPRegs, DFPRegs, /* FONES */ FPRegs, FPRegs, /* FOR */ DFPRegs, DFPRegs, DFPRegs, /* FORNOT1 */ DFPRegs, DFPRegs, DFPRegs, /* FORNOT1S */ FPRegs, FPRegs, FPRegs, /* FORNOT2 */ DFPRegs, DFPRegs, DFPRegs, /* FORNOT2S */ FPRegs, FPRegs, FPRegs, /* FORS */ FPRegs, FPRegs, FPRegs, /* FPACK16 */ DFPRegs, DFPRegs, /* FPACK32 */ DFPRegs, DFPRegs, DFPRegs, /* FPACKFIX */ DFPRegs, DFPRegs, /* FPADD16 */ DFPRegs, DFPRegs, DFPRegs, /* FPADD16S */ DFPRegs, DFPRegs, DFPRegs, /* FPADD32 */ DFPRegs, DFPRegs, DFPRegs, /* FPADD32S */ DFPRegs, DFPRegs, DFPRegs, /* FPADD64 */ DFPRegs, DFPRegs, DFPRegs, /* FPMERGE */ DFPRegs, DFPRegs, DFPRegs, /* FPSUB16 */ DFPRegs, DFPRegs, DFPRegs, /* FPSUB16S */ DFPRegs, DFPRegs, DFPRegs, /* FPSUB32 */ DFPRegs, DFPRegs, DFPRegs, /* FPSUB32S */ DFPRegs, DFPRegs, DFPRegs, /* FQTOD */ DFPRegs, QFPRegs, /* FQTOI */ FPRegs, QFPRegs, /* FQTOS */ FPRegs, QFPRegs, /* FQTOX */ DFPRegs, QFPRegs, /* FSLAS16 */ DFPRegs, DFPRegs, DFPRegs, /* FSLAS32 */ DFPRegs, DFPRegs, DFPRegs, /* FSLL16 */ DFPRegs, DFPRegs, DFPRegs, /* FSLL32 */ DFPRegs, DFPRegs, DFPRegs, /* FSMULD */ DFPRegs, FPRegs, FPRegs, /* FSQRTD */ DFPRegs, DFPRegs, /* FSQRTQ */ QFPRegs, QFPRegs, /* FSQRTS */ FPRegs, FPRegs, /* FSRA16 */ DFPRegs, DFPRegs, DFPRegs, /* FSRA32 */ DFPRegs, DFPRegs, DFPRegs, /* FSRC1 */ DFPRegs, DFPRegs, /* FSRC1S */ FPRegs, FPRegs, /* FSRC2 */ DFPRegs, DFPRegs, /* FSRC2S */ FPRegs, FPRegs, /* FSRL16 */ DFPRegs, DFPRegs, DFPRegs, /* FSRL32 */ DFPRegs, DFPRegs, DFPRegs, /* FSTOD */ DFPRegs, FPRegs, /* FSTOI */ FPRegs, FPRegs, /* FSTOQ */ QFPRegs, FPRegs, /* FSTOX */ DFPRegs, FPRegs, /* FSUBD */ DFPRegs, DFPRegs, DFPRegs, /* FSUBQ */ QFPRegs, QFPRegs, QFPRegs, /* FSUBS */ FPRegs, FPRegs, FPRegs, /* FXNOR */ DFPRegs, DFPRegs, DFPRegs, /* FXNORS */ FPRegs, FPRegs, FPRegs, /* FXOR */ DFPRegs, DFPRegs, DFPRegs, /* FXORS */ FPRegs, FPRegs, FPRegs, /* FXTOD */ DFPRegs, DFPRegs, /* FXTOQ */ QFPRegs, DFPRegs, /* FXTOS */ FPRegs, DFPRegs, /* FZERO */ DFPRegs, DFPRegs, /* FZEROS */ FPRegs, FPRegs, /* GDOP_LDXrr */ I64Regs, -1, -1, TailRelocSymGOTLoad, /* GDOP_LDrr */ IntRegs, -1, -1, TailRelocSymGOTLoad, /* JMPLri */ IntRegs, -1, i32imm, /* JMPLrr */ IntRegs, -1, -1, /* LDAri */ IntRegs, -1, i32imm, /* LDArr */ IntRegs, -1, -1, ASITag, /* LDCSRri */ -1, i32imm, /* LDCSRrr */ -1, -1, /* LDCri */ CoprocRegs, -1, i32imm, /* LDCrr */ CoprocRegs, -1, -1, /* LDDAri */ IntPair, -1, i32imm, /* LDDArr */ IntPair, -1, -1, ASITag, /* LDDCri */ CoprocPair, -1, i32imm, /* LDDCrr */ CoprocPair, -1, -1, /* LDDFAri */ DFPRegs, -1, i32imm, /* LDDFArr */ DFPRegs, -1, -1, ASITag, /* LDDFri */ DFPRegs, -1, i32imm, /* LDDFrr */ DFPRegs, -1, -1, /* LDDri */ IntPair, -1, i32imm, /* LDDrr */ IntPair, -1, -1, /* LDFAri */ FPRegs, -1, i32imm, /* LDFArr */ FPRegs, -1, -1, ASITag, /* LDFSRri */ -1, i32imm, /* LDFSRrr */ -1, -1, /* LDFri */ FPRegs, -1, i32imm, /* LDFrr */ FPRegs, -1, -1, /* LDQFAri */ QFPRegs, -1, i32imm, /* LDQFArr */ QFPRegs, -1, -1, ASITag, /* LDQFri */ QFPRegs, -1, i32imm, /* LDQFrr */ QFPRegs, -1, -1, /* LDSBAri */ IntRegs, -1, i32imm, /* LDSBArr */ IntRegs, -1, -1, ASITag, /* LDSBri */ IntRegs, -1, i32imm, /* LDSBrr */ IntRegs, -1, -1, /* LDSHAri */ IntRegs, -1, i32imm, /* LDSHArr */ IntRegs, -1, -1, ASITag, /* LDSHri */ IntRegs, -1, i32imm, /* LDSHrr */ IntRegs, -1, -1, /* LDSTUBAri */ IntRegs, -1, i32imm, /* LDSTUBArr */ IntRegs, -1, -1, ASITag, /* LDSTUBri */ IntRegs, -1, i32imm, /* LDSTUBrr */ IntRegs, -1, -1, /* LDSWAri */ I64Regs, -1, i32imm, /* LDSWArr */ I64Regs, -1, -1, ASITag, /* LDSWri */ I64Regs, -1, i32imm, /* LDSWrr */ I64Regs, -1, -1, /* LDUBAri */ IntRegs, -1, i32imm, /* LDUBArr */ IntRegs, -1, -1, ASITag, /* LDUBri */ IntRegs, -1, i32imm, /* LDUBrr */ IntRegs, -1, -1, /* LDUHAri */ IntRegs, -1, i32imm, /* LDUHArr */ IntRegs, -1, -1, ASITag, /* LDUHri */ IntRegs, -1, i32imm, /* LDUHrr */ IntRegs, -1, -1, /* LDXAri */ I64Regs, -1, i32imm, /* LDXArr */ I64Regs, -1, -1, ASITag, /* LDXFSRri */ -1, i32imm, /* LDXFSRrr */ -1, -1, /* LDXri */ I64Regs, -1, i32imm, /* LDXrr */ I64Regs, -1, -1, /* LDri */ IntRegs, -1, i32imm, /* LDrr */ IntRegs, -1, -1, /* LZCNT */ I64Regs, I64Regs, /* MEMBARi */ MembarTag, /* MOVDTOX */ I64Regs, DFPRegs, /* MOVFCCri */ IntRegs, i32imm, IntRegs, CCOp, /* MOVFCCrr */ IntRegs, IntRegs, IntRegs, CCOp, /* MOVICCri */ IntRegs, i32imm, IntRegs, CCOp, /* MOVICCrr */ IntRegs, IntRegs, IntRegs, CCOp, /* MOVRri */ IntRegs, I64Regs, i32imm, IntRegs, RegCCOp, /* MOVRrr */ IntRegs, I64Regs, IntRegs, IntRegs, RegCCOp, /* MOVSTOSW */ I64Regs, DFPRegs, /* MOVSTOUW */ I64Regs, DFPRegs, /* MOVWTOS */ DFPRegs, I64Regs, /* MOVXCCri */ IntRegs, i32imm, IntRegs, CCOp, /* MOVXCCrr */ IntRegs, IntRegs, IntRegs, CCOp, /* MOVXTOD */ DFPRegs, I64Regs, /* MULSCCri */ IntRegs, IntRegs, simm13Op, /* MULSCCrr */ IntRegs, IntRegs, IntRegs, /* MULXri */ IntRegs, IntRegs, i64imm, /* MULXrr */ I64Regs, I64Regs, I64Regs, /* NOP */ /* ORCCri */ IntRegs, IntRegs, simm13Op, /* ORCCrr */ IntRegs, IntRegs, IntRegs, /* ORNCCri */ IntRegs, IntRegs, simm13Op, /* ORNCCrr */ IntRegs, IntRegs, IntRegs, /* ORNri */ IntRegs, IntRegs, simm13Op, /* ORNrr */ IntRegs, IntRegs, IntRegs, /* ORri */ IntRegs, IntRegs, simm13Op, /* ORrr */ IntRegs, IntRegs, IntRegs, /* PDIST */ DFPRegs, DFPRegs, DFPRegs, /* PDISTN */ DFPRegs, DFPRegs, DFPRegs, /* POPCrr */ IntRegs, IntRegs, /* PREFETCHAi */ -1, i32imm, PrefetchTag, /* PREFETCHAr */ -1, -1, ASITag, PrefetchTag, /* PREFETCHi */ -1, i32imm, PrefetchTag, /* PREFETCHr */ -1, -1, PrefetchTag, /* PWRPSRri */ IntRegs, simm13Op, /* PWRPSRrr */ IntRegs, IntRegs, /* RDASR */ IntRegs, ASRRegs, /* RDFQ */ IntRegs, /* RDPR */ IntRegs, PRRegs, /* RDPSR */ IntRegs, /* RDTBR */ IntRegs, /* RDWIM */ IntRegs, /* RESTORED */ /* RESTOREri */ IntRegs, IntRegs, simm13Op, /* RESTORErr */ IntRegs, IntRegs, IntRegs, /* RET */ i32imm, /* RETL */ i32imm, /* RETRY */ /* RETTri */ -1, i32imm, /* RETTrr */ -1, -1, /* SAVED */ /* SAVEri */ IntRegs, IntRegs, simm13Op, /* SAVErr */ IntRegs, IntRegs, IntRegs, /* SDIVCCri */ IntRegs, IntRegs, simm13Op, /* SDIVCCrr */ IntRegs, IntRegs, IntRegs, /* SDIVXri */ IntRegs, IntRegs, i64imm, /* SDIVXrr */ I64Regs, I64Regs, I64Regs, /* SDIVri */ IntRegs, IntRegs, simm13Op, /* SDIVrr */ IntRegs, IntRegs, IntRegs, /* SETHIi */ IntRegs, i32imm, /* SHUTDOWN */ /* SIAM */ /* SIR */ simm13Op, /* SLLXri */ I64Regs, I64Regs, shift_imm6, /* SLLXrr */ I64Regs, I64Regs, IntRegs, /* SLLri */ IntRegs, IntRegs, shift_imm5, /* SLLrr */ IntRegs, IntRegs, IntRegs, /* SMACri */ IntRegs, IntRegs, simm13Op, ASRRegs, /* SMACrr */ IntRegs, IntRegs, IntRegs, ASRRegs, /* SMULCCri */ IntRegs, IntRegs, simm13Op, /* SMULCCrr */ IntRegs, IntRegs, IntRegs, /* SMULri */ IntRegs, IntRegs, simm13Op, /* SMULrr */ IntRegs, IntRegs, IntRegs, /* SRAXri */ I64Regs, I64Regs, shift_imm6, /* SRAXrr */ I64Regs, I64Regs, IntRegs, /* SRAri */ IntRegs, IntRegs, shift_imm5, /* SRArr */ IntRegs, IntRegs, IntRegs, /* SRLXri */ I64Regs, I64Regs, shift_imm6, /* SRLXrr */ I64Regs, I64Regs, IntRegs, /* SRLri */ IntRegs, IntRegs, shift_imm5, /* SRLrr */ IntRegs, IntRegs, IntRegs, /* STAri */ -1, i32imm, IntRegs, /* STArr */ -1, -1, IntRegs, ASITag, /* STBAR */ /* STBAri */ -1, i32imm, IntRegs, /* STBArr */ -1, -1, IntRegs, ASITag, /* STBri */ -1, i32imm, IntRegs, /* STBrr */ -1, -1, IntRegs, /* STCSRri */ -1, i32imm, /* STCSRrr */ -1, -1, /* STCri */ -1, i32imm, CoprocRegs, /* STCrr */ -1, -1, CoprocRegs, /* STDAri */ -1, i32imm, IntPair, /* STDArr */ -1, -1, IntPair, ASITag, /* STDCQri */ -1, i32imm, /* STDCQrr */ -1, -1, /* STDCri */ -1, i32imm, CoprocPair, /* STDCrr */ -1, -1, CoprocPair, /* STDFAri */ -1, i32imm, DFPRegs, /* STDFArr */ -1, -1, DFPRegs, ASITag, /* STDFQri */ -1, i32imm, /* STDFQrr */ -1, -1, /* STDFri */ -1, i32imm, DFPRegs, /* STDFrr */ -1, -1, DFPRegs, /* STDri */ -1, i32imm, IntPair, /* STDrr */ -1, -1, IntPair, /* STFAri */ -1, i32imm, FPRegs, /* STFArr */ -1, -1, FPRegs, ASITag, /* STFSRri */ -1, i32imm, /* STFSRrr */ -1, -1, /* STFri */ -1, i32imm, FPRegs, /* STFrr */ -1, -1, FPRegs, /* STHAri */ -1, i32imm, IntRegs, /* STHArr */ -1, -1, IntRegs, ASITag, /* STHri */ -1, i32imm, IntRegs, /* STHrr */ -1, -1, IntRegs, /* STQFAri */ -1, i32imm, QFPRegs, /* STQFArr */ -1, -1, QFPRegs, ASITag, /* STQFri */ -1, i32imm, QFPRegs, /* STQFrr */ -1, -1, QFPRegs, /* STXAri */ -1, i32imm, I64Regs, /* STXArr */ -1, -1, I64Regs, ASITag, /* STXFSRri */ -1, i32imm, /* STXFSRrr */ -1, -1, /* STXri */ -1, i32imm, I64Regs, /* STXrr */ -1, -1, I64Regs, /* STri */ -1, i32imm, IntRegs, /* STrr */ -1, -1, IntRegs, /* SUBCCri */ IntRegs, IntRegs, simm13Op, /* SUBCCrr */ IntRegs, IntRegs, IntRegs, /* SUBCri */ IntRegs, IntRegs, simm13Op, /* SUBCrr */ IntRegs, IntRegs, IntRegs, /* SUBEri */ IntRegs, IntRegs, simm13Op, /* SUBErr */ IntRegs, IntRegs, IntRegs, /* SUBri */ IntRegs, IntRegs, simm13Op, /* SUBrr */ IntRegs, IntRegs, IntRegs, /* SWAPAri */ IntRegs, -1, i32imm, IntRegs, /* SWAPArr */ IntRegs, -1, -1, ASITag, IntRegs, /* SWAPri */ IntRegs, -1, i32imm, IntRegs, /* SWAPrr */ IntRegs, -1, -1, IntRegs, /* TA1 */ /* TA3 */ /* TA5 */ /* TADDCCTVri */ IntRegs, IntRegs, simm13Op, /* TADDCCTVrr */ IntRegs, IntRegs, IntRegs, /* TADDCCri */ IntRegs, IntRegs, simm13Op, /* TADDCCrr */ IntRegs, IntRegs, IntRegs, /* TAIL_CALL */ calltarget, /* TAIL_CALLri */ -1, i32imm, /* TICCri */ IntRegs, i32imm, CCOp, /* TICCrr */ IntRegs, IntRegs, CCOp, /* TLS_ADDrr */ IntRegs, IntRegs, IntRegs, TailRelocSymTLSAdd, /* TLS_CALL */ calltarget, TailRelocSymTLSCall, /* TLS_LDXrr */ IntRegs, -1, -1, TailRelocSymTLSLoad, /* TLS_LDrr */ IntRegs, -1, -1, TailRelocSymTLSLoad, /* TRAPri */ IntRegs, i32imm, CCOp, /* TRAPrr */ IntRegs, IntRegs, CCOp, /* TSUBCCTVri */ IntRegs, IntRegs, simm13Op, /* TSUBCCTVrr */ IntRegs, IntRegs, IntRegs, /* TSUBCCri */ IntRegs, IntRegs, simm13Op, /* TSUBCCrr */ IntRegs, IntRegs, IntRegs, /* TXCCri */ IntRegs, i32imm, CCOp, /* TXCCrr */ IntRegs, IntRegs, CCOp, /* UDIVCCri */ IntRegs, IntRegs, simm13Op, /* UDIVCCrr */ IntRegs, IntRegs, IntRegs, /* UDIVXri */ IntRegs, IntRegs, i64imm, /* UDIVXrr */ I64Regs, I64Regs, I64Regs, /* UDIVri */ IntRegs, IntRegs, simm13Op, /* UDIVrr */ IntRegs, IntRegs, IntRegs, /* UMACri */ IntRegs, IntRegs, simm13Op, ASRRegs, /* UMACrr */ IntRegs, IntRegs, IntRegs, ASRRegs, /* UMULCCri */ IntRegs, IntRegs, simm13Op, /* UMULCCrr */ IntRegs, IntRegs, IntRegs, /* UMULXHI */ I64Regs, I64Regs, I64Regs, /* UMULri */ IntRegs, IntRegs, simm13Op, /* UMULrr */ IntRegs, IntRegs, IntRegs, /* UNIMP */ i32imm, /* V9FCMPD */ FCCRegs, DFPRegs, DFPRegs, /* V9FCMPED */ FCCRegs, DFPRegs, DFPRegs, /* V9FCMPEQ */ FCCRegs, QFPRegs, QFPRegs, /* V9FCMPES */ FCCRegs, FPRegs, FPRegs, /* V9FCMPQ */ FCCRegs, QFPRegs, QFPRegs, /* V9FCMPS */ FCCRegs, FPRegs, FPRegs, /* V9FMOVD_FCC */ DFPRegs, FCCRegs, DFPRegs, DFPRegs, CCOp, /* V9FMOVQ_FCC */ QFPRegs, FCCRegs, QFPRegs, QFPRegs, CCOp, /* V9FMOVS_FCC */ FPRegs, FCCRegs, FPRegs, FPRegs, CCOp, /* V9MOVFCCri */ IntRegs, FCCRegs, i32imm, IntRegs, CCOp, /* V9MOVFCCrr */ IntRegs, FCCRegs, IntRegs, IntRegs, CCOp, /* WRASRri */ ASRRegs, IntRegs, simm13Op, /* WRASRrr */ ASRRegs, IntRegs, IntRegs, /* WRPRri */ PRRegs, IntRegs, simm13Op, /* WRPRrr */ PRRegs, IntRegs, IntRegs, /* WRPSRri */ IntRegs, simm13Op, /* WRPSRrr */ IntRegs, IntRegs, /* WRTBRri */ IntRegs, simm13Op, /* WRTBRrr */ IntRegs, IntRegs, /* WRWIMri */ IntRegs, simm13Op, /* WRWIMrr */ IntRegs, IntRegs, /* XMULX */ I64Regs, I64Regs, I64Regs, /* XMULXHI */ I64Regs, I64Regs, I64Regs, /* XNORCCri */ IntRegs, IntRegs, simm13Op, /* XNORCCrr */ IntRegs, IntRegs, IntRegs, /* XNORri */ IntRegs, IntRegs, simm13Op, /* XNORrr */ IntRegs, IntRegs, IntRegs, /* XORCCri */ IntRegs, IntRegs, simm13Op, /* XORCCrr */ IntRegs, IntRegs, IntRegs, /* XORri */ IntRegs, IntRegs, simm13Op, /* XORrr */ IntRegs, IntRegs, IntRegs, }; return OpcodeOperandTypes[Offsets[Opcode] + OpIdx]; } } // end namespace SP } // end namespace llvm #endif // GET_INSTRINFO_OPERAND_TYPE #ifdef GET_INSTRINFO_MEM_OPERAND_SIZE #undef GET_INSTRINFO_MEM_OPERAND_SIZE namespace llvm { namespace SP { LLVM_READONLY static int getMemOperandSize(int OpType) { switch (OpType) { default: return 0; } } } // end namespace SP } // end namespace llvm #endif // GET_INSTRINFO_MEM_OPERAND_SIZE #ifdef GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP #undef GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP namespace llvm { namespace Sparc { LLVM_READONLY static unsigned getLogicalOperandSize(uint16_t Opcode, uint16_t LogicalOpIdx) { return LogicalOpIdx; } LLVM_READONLY static inline unsigned getLogicalOperandIdx(uint16_t Opcode, uint16_t LogicalOpIdx) { auto S = 0U; for (auto i = 0U; i < LogicalOpIdx; ++i) S += getLogicalOperandSize(Opcode, i); return S; } } // end namespace Sparc } // end namespace llvm #endif // GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP #ifdef GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP #undef GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP namespace llvm { namespace Sparc { LLVM_READONLY static int getLogicalOperandType(uint16_t Opcode, uint16_t LogicalOpIdx) { return -1; } } // end namespace Sparc } // end namespace llvm #endif // GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP #ifdef GET_INSTRINFO_MC_HELPER_DECLS #undef GET_INSTRINFO_MC_HELPER_DECLS namespace llvm { class MCInst; class FeatureBitset; namespace Sparc_MC { void verifyInstructionPredicates(unsigned Opcode, const FeatureBitset &Features); } // end namespace Sparc_MC } // end namespace llvm #endif // GET_INSTRINFO_MC_HELPER_DECLS #ifdef GET_INSTRINFO_MC_HELPERS #undef GET_INSTRINFO_MC_HELPERS namespace llvm { namespace Sparc_MC { } // end namespace Sparc_MC } // end namespace llvm #endif // GET_GENISTRINFO_MC_HELPERS #if (defined(ENABLE_INSTR_PREDICATE_VERIFIER) && !defined(NDEBUG)) ||\ defined(GET_AVAILABLE_OPCODE_CHECKER) #define GET_COMPUTE_FEATURES #endif #ifdef GET_COMPUTE_FEATURES #undef GET_COMPUTE_FEATURES namespace llvm { namespace Sparc_MC { // Bits for subtarget features that participate in instruction matching. enum SubtargetFeatureBits : uint8_t { Feature_UseSoftMulDivBit = 6, Feature_HasV9Bit = 2, Feature_HasVISBit = 3, Feature_HasVIS2Bit = 4, Feature_HasVIS3Bit = 5, Feature_HasCASABit = 0, Feature_HasPWRPSRBit = 1, }; inline FeatureBitset computeAvailableFeatures(const FeatureBitset &FB) { FeatureBitset Features; if (FB[Sparc::FeatureSoftMulDiv]) Features.set(Feature_UseSoftMulDivBit); if (FB[Sparc::FeatureV9]) Features.set(Feature_HasV9Bit); if (FB[Sparc::FeatureVIS]) Features.set(Feature_HasVISBit); if (FB[Sparc::FeatureVIS2]) Features.set(Feature_HasVIS2Bit); if (FB[Sparc::FeatureVIS3]) Features.set(Feature_HasVIS3Bit); if (FB[Sparc::LeonCASA] || FB[Sparc::FeatureV9]) Features.set(Feature_HasCASABit); if (FB[Sparc::FeaturePWRPSR]) Features.set(Feature_HasPWRPSRBit); return Features; } inline FeatureBitset computeRequiredFeatures(unsigned Opcode) { enum : uint8_t { CEFBS_None, CEFBS_HasCASA, CEFBS_HasPWRPSR, CEFBS_HasV9, CEFBS_HasVIS, CEFBS_HasVIS2, CEFBS_HasVIS3, }; static constexpr FeatureBitset FeatureBitsets[] = { {}, // CEFBS_None {Feature_HasCASABit, }, {Feature_HasPWRPSRBit, }, {Feature_HasV9Bit, }, {Feature_HasVISBit, }, {Feature_HasVIS2Bit, }, {Feature_HasVIS3Bit, }, }; static constexpr uint8_t RequiredFeaturesRefs[] = { CEFBS_None, // PHI = 0 CEFBS_None, // INLINEASM = 1 CEFBS_None, // INLINEASM_BR = 2 CEFBS_None, // CFI_INSTRUCTION = 3 CEFBS_None, // EH_LABEL = 4 CEFBS_None, // GC_LABEL = 5 CEFBS_None, // ANNOTATION_LABEL = 6 CEFBS_None, // KILL = 7 CEFBS_None, // EXTRACT_SUBREG = 8 CEFBS_None, // INSERT_SUBREG = 9 CEFBS_None, // IMPLICIT_DEF = 10 CEFBS_None, // SUBREG_TO_REG = 11 CEFBS_None, // COPY_TO_REGCLASS = 12 CEFBS_None, // DBG_VALUE = 13 CEFBS_None, // DBG_VALUE_LIST = 14 CEFBS_None, // DBG_INSTR_REF = 15 CEFBS_None, // DBG_PHI = 16 CEFBS_None, // DBG_LABEL = 17 CEFBS_None, // REG_SEQUENCE = 18 CEFBS_None, // COPY = 19 CEFBS_None, // BUNDLE = 20 CEFBS_None, // LIFETIME_START = 21 CEFBS_None, // LIFETIME_END = 22 CEFBS_None, // PSEUDO_PROBE = 23 CEFBS_None, // ARITH_FENCE = 24 CEFBS_None, // STACKMAP = 25 CEFBS_None, // FENTRY_CALL = 26 CEFBS_None, // PATCHPOINT = 27 CEFBS_None, // LOAD_STACK_GUARD = 28 CEFBS_None, // PREALLOCATED_SETUP = 29 CEFBS_None, // PREALLOCATED_ARG = 30 CEFBS_None, // STATEPOINT = 31 CEFBS_None, // LOCAL_ESCAPE = 32 CEFBS_None, // FAULTING_OP = 33 CEFBS_None, // PATCHABLE_OP = 34 CEFBS_None, // PATCHABLE_FUNCTION_ENTER = 35 CEFBS_None, // PATCHABLE_RET = 36 CEFBS_None, // PATCHABLE_FUNCTION_EXIT = 37 CEFBS_None, // PATCHABLE_TAIL_CALL = 38 CEFBS_None, // PATCHABLE_EVENT_CALL = 39 CEFBS_None, // PATCHABLE_TYPED_EVENT_CALL = 40 CEFBS_None, // ICALL_BRANCH_FUNNEL = 41 CEFBS_None, // FAKE_USE = 42 CEFBS_None, // MEMBARRIER = 43 CEFBS_None, // JUMP_TABLE_DEBUG_INFO = 44 CEFBS_None, // CONVERGENCECTRL_ENTRY = 45 CEFBS_None, // CONVERGENCECTRL_ANCHOR = 46 CEFBS_None, // CONVERGENCECTRL_LOOP = 47 CEFBS_None, // CONVERGENCECTRL_GLUE = 48 CEFBS_None, // G_ASSERT_SEXT = 49 CEFBS_None, // G_ASSERT_ZEXT = 50 CEFBS_None, // G_ASSERT_ALIGN = 51 CEFBS_None, // G_ADD = 52 CEFBS_None, // G_SUB = 53 CEFBS_None, // G_MUL = 54 CEFBS_None, // G_SDIV = 55 CEFBS_None, // G_UDIV = 56 CEFBS_None, // G_SREM = 57 CEFBS_None, // G_UREM = 58 CEFBS_None, // G_SDIVREM = 59 CEFBS_None, // G_UDIVREM = 60 CEFBS_None, // G_AND = 61 CEFBS_None, // G_OR = 62 CEFBS_None, // G_XOR = 63 CEFBS_None, // G_IMPLICIT_DEF = 64 CEFBS_None, // G_PHI = 65 CEFBS_None, // G_FRAME_INDEX = 66 CEFBS_None, // G_GLOBAL_VALUE = 67 CEFBS_None, // G_PTRAUTH_GLOBAL_VALUE = 68 CEFBS_None, // G_CONSTANT_POOL = 69 CEFBS_None, // G_EXTRACT = 70 CEFBS_None, // G_UNMERGE_VALUES = 71 CEFBS_None, // G_INSERT = 72 CEFBS_None, // G_MERGE_VALUES = 73 CEFBS_None, // G_BUILD_VECTOR = 74 CEFBS_None, // G_BUILD_VECTOR_TRUNC = 75 CEFBS_None, // G_CONCAT_VECTORS = 76 CEFBS_None, // G_PTRTOINT = 77 CEFBS_None, // G_INTTOPTR = 78 CEFBS_None, // G_BITCAST = 79 CEFBS_None, // G_FREEZE = 80 CEFBS_None, // G_CONSTANT_FOLD_BARRIER = 81 CEFBS_None, // G_INTRINSIC_FPTRUNC_ROUND = 82 CEFBS_None, // G_INTRINSIC_TRUNC = 83 CEFBS_None, // G_INTRINSIC_ROUND = 84 CEFBS_None, // G_INTRINSIC_LRINT = 85 CEFBS_None, // G_INTRINSIC_LLRINT = 86 CEFBS_None, // G_INTRINSIC_ROUNDEVEN = 87 CEFBS_None, // G_READCYCLECOUNTER = 88 CEFBS_None, // G_READSTEADYCOUNTER = 89 CEFBS_None, // G_LOAD = 90 CEFBS_None, // G_SEXTLOAD = 91 CEFBS_None, // G_ZEXTLOAD = 92 CEFBS_None, // G_INDEXED_LOAD = 93 CEFBS_None, // G_INDEXED_SEXTLOAD = 94 CEFBS_None, // G_INDEXED_ZEXTLOAD = 95 CEFBS_None, // G_STORE = 96 CEFBS_None, // G_INDEXED_STORE = 97 CEFBS_None, // G_ATOMIC_CMPXCHG_WITH_SUCCESS = 98 CEFBS_None, // G_ATOMIC_CMPXCHG = 99 CEFBS_None, // G_ATOMICRMW_XCHG = 100 CEFBS_None, // G_ATOMICRMW_ADD = 101 CEFBS_None, // G_ATOMICRMW_SUB = 102 CEFBS_None, // G_ATOMICRMW_AND = 103 CEFBS_None, // G_ATOMICRMW_NAND = 104 CEFBS_None, // G_ATOMICRMW_OR = 105 CEFBS_None, // G_ATOMICRMW_XOR = 106 CEFBS_None, // G_ATOMICRMW_MAX = 107 CEFBS_None, // G_ATOMICRMW_MIN = 108 CEFBS_None, // G_ATOMICRMW_UMAX = 109 CEFBS_None, // G_ATOMICRMW_UMIN = 110 CEFBS_None, // G_ATOMICRMW_FADD = 111 CEFBS_None, // G_ATOMICRMW_FSUB = 112 CEFBS_None, // G_ATOMICRMW_FMAX = 113 CEFBS_None, // G_ATOMICRMW_FMIN = 114 CEFBS_None, // G_ATOMICRMW_UINC_WRAP = 115 CEFBS_None, // G_ATOMICRMW_UDEC_WRAP = 116 CEFBS_None, // G_FENCE = 117 CEFBS_None, // G_PREFETCH = 118 CEFBS_None, // G_BRCOND = 119 CEFBS_None, // G_BRINDIRECT = 120 CEFBS_None, // G_INVOKE_REGION_START = 121 CEFBS_None, // G_INTRINSIC = 122 CEFBS_None, // G_INTRINSIC_W_SIDE_EFFECTS = 123 CEFBS_None, // G_INTRINSIC_CONVERGENT = 124 CEFBS_None, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS = 125 CEFBS_None, // G_ANYEXT = 126 CEFBS_None, // G_TRUNC = 127 CEFBS_None, // G_CONSTANT = 128 CEFBS_None, // G_FCONSTANT = 129 CEFBS_None, // G_VASTART = 130 CEFBS_None, // G_VAARG = 131 CEFBS_None, // G_SEXT = 132 CEFBS_None, // G_SEXT_INREG = 133 CEFBS_None, // G_ZEXT = 134 CEFBS_None, // G_SHL = 135 CEFBS_None, // G_LSHR = 136 CEFBS_None, // G_ASHR = 137 CEFBS_None, // G_FSHL = 138 CEFBS_None, // G_FSHR = 139 CEFBS_None, // G_ROTR = 140 CEFBS_None, // G_ROTL = 141 CEFBS_None, // G_ICMP = 142 CEFBS_None, // G_FCMP = 143 CEFBS_None, // G_SCMP = 144 CEFBS_None, // G_UCMP = 145 CEFBS_None, // G_SELECT = 146 CEFBS_None, // G_UADDO = 147 CEFBS_None, // G_UADDE = 148 CEFBS_None, // G_USUBO = 149 CEFBS_None, // G_USUBE = 150 CEFBS_None, // G_SADDO = 151 CEFBS_None, // G_SADDE = 152 CEFBS_None, // G_SSUBO = 153 CEFBS_None, // G_SSUBE = 154 CEFBS_None, // G_UMULO = 155 CEFBS_None, // G_SMULO = 156 CEFBS_None, // G_UMULH = 157 CEFBS_None, // G_SMULH = 158 CEFBS_None, // G_UADDSAT = 159 CEFBS_None, // G_SADDSAT = 160 CEFBS_None, // G_USUBSAT = 161 CEFBS_None, // G_SSUBSAT = 162 CEFBS_None, // G_USHLSAT = 163 CEFBS_None, // G_SSHLSAT = 164 CEFBS_None, // G_SMULFIX = 165 CEFBS_None, // G_UMULFIX = 166 CEFBS_None, // G_SMULFIXSAT = 167 CEFBS_None, // G_UMULFIXSAT = 168 CEFBS_None, // G_SDIVFIX = 169 CEFBS_None, // G_UDIVFIX = 170 CEFBS_None, // G_SDIVFIXSAT = 171 CEFBS_None, // G_UDIVFIXSAT = 172 CEFBS_None, // G_FADD = 173 CEFBS_None, // G_FSUB = 174 CEFBS_None, // G_FMUL = 175 CEFBS_None, // G_FMA = 176 CEFBS_None, // G_FMAD = 177 CEFBS_None, // G_FDIV = 178 CEFBS_None, // G_FREM = 179 CEFBS_None, // G_FPOW = 180 CEFBS_None, // G_FPOWI = 181 CEFBS_None, // G_FEXP = 182 CEFBS_None, // G_FEXP2 = 183 CEFBS_None, // G_FEXP10 = 184 CEFBS_None, // G_FLOG = 185 CEFBS_None, // G_FLOG2 = 186 CEFBS_None, // G_FLOG10 = 187 CEFBS_None, // G_FLDEXP = 188 CEFBS_None, // G_FFREXP = 189 CEFBS_None, // G_FNEG = 190 CEFBS_None, // G_FPEXT = 191 CEFBS_None, // G_FPTRUNC = 192 CEFBS_None, // G_FPTOSI = 193 CEFBS_None, // G_FPTOUI = 194 CEFBS_None, // G_SITOFP = 195 CEFBS_None, // G_UITOFP = 196 CEFBS_None, // G_FABS = 197 CEFBS_None, // G_FCOPYSIGN = 198 CEFBS_None, // G_IS_FPCLASS = 199 CEFBS_None, // G_FCANONICALIZE = 200 CEFBS_None, // G_FMINNUM = 201 CEFBS_None, // G_FMAXNUM = 202 CEFBS_None, // G_FMINNUM_IEEE = 203 CEFBS_None, // G_FMAXNUM_IEEE = 204 CEFBS_None, // G_FMINIMUM = 205 CEFBS_None, // G_FMAXIMUM = 206 CEFBS_None, // G_GET_FPENV = 207 CEFBS_None, // G_SET_FPENV = 208 CEFBS_None, // G_RESET_FPENV = 209 CEFBS_None, // G_GET_FPMODE = 210 CEFBS_None, // G_SET_FPMODE = 211 CEFBS_None, // G_RESET_FPMODE = 212 CEFBS_None, // G_PTR_ADD = 213 CEFBS_None, // G_PTRMASK = 214 CEFBS_None, // G_SMIN = 215 CEFBS_None, // G_SMAX = 216 CEFBS_None, // G_UMIN = 217 CEFBS_None, // G_UMAX = 218 CEFBS_None, // G_ABS = 219 CEFBS_None, // G_LROUND = 220 CEFBS_None, // G_LLROUND = 221 CEFBS_None, // G_BR = 222 CEFBS_None, // G_BRJT = 223 CEFBS_None, // G_VSCALE = 224 CEFBS_None, // G_INSERT_SUBVECTOR = 225 CEFBS_None, // G_EXTRACT_SUBVECTOR = 226 CEFBS_None, // G_INSERT_VECTOR_ELT = 227 CEFBS_None, // G_EXTRACT_VECTOR_ELT = 228 CEFBS_None, // G_SHUFFLE_VECTOR = 229 CEFBS_None, // G_SPLAT_VECTOR = 230 CEFBS_None, // G_VECTOR_COMPRESS = 231 CEFBS_None, // G_CTTZ = 232 CEFBS_None, // G_CTTZ_ZERO_UNDEF = 233 CEFBS_None, // G_CTLZ = 234 CEFBS_None, // G_CTLZ_ZERO_UNDEF = 235 CEFBS_None, // G_CTPOP = 236 CEFBS_None, // G_BSWAP = 237 CEFBS_None, // G_BITREVERSE = 238 CEFBS_None, // G_FCEIL = 239 CEFBS_None, // G_FCOS = 240 CEFBS_None, // G_FSIN = 241 CEFBS_None, // G_FTAN = 242 CEFBS_None, // G_FACOS = 243 CEFBS_None, // G_FASIN = 244 CEFBS_None, // G_FATAN = 245 CEFBS_None, // G_FCOSH = 246 CEFBS_None, // G_FSINH = 247 CEFBS_None, // G_FTANH = 248 CEFBS_None, // G_FSQRT = 249 CEFBS_None, // G_FFLOOR = 250 CEFBS_None, // G_FRINT = 251 CEFBS_None, // G_FNEARBYINT = 252 CEFBS_None, // G_ADDRSPACE_CAST = 253 CEFBS_None, // G_BLOCK_ADDR = 254 CEFBS_None, // G_JUMP_TABLE = 255 CEFBS_None, // G_DYN_STACKALLOC = 256 CEFBS_None, // G_STACKSAVE = 257 CEFBS_None, // G_STACKRESTORE = 258 CEFBS_None, // G_STRICT_FADD = 259 CEFBS_None, // G_STRICT_FSUB = 260 CEFBS_None, // G_STRICT_FMUL = 261 CEFBS_None, // G_STRICT_FDIV = 262 CEFBS_None, // G_STRICT_FREM = 263 CEFBS_None, // G_STRICT_FMA = 264 CEFBS_None, // G_STRICT_FSQRT = 265 CEFBS_None, // G_STRICT_FLDEXP = 266 CEFBS_None, // G_READ_REGISTER = 267 CEFBS_None, // G_WRITE_REGISTER = 268 CEFBS_None, // G_MEMCPY = 269 CEFBS_None, // G_MEMCPY_INLINE = 270 CEFBS_None, // G_MEMMOVE = 271 CEFBS_None, // G_MEMSET = 272 CEFBS_None, // G_BZERO = 273 CEFBS_None, // G_TRAP = 274 CEFBS_None, // G_DEBUGTRAP = 275 CEFBS_None, // G_UBSANTRAP = 276 CEFBS_None, // G_VECREDUCE_SEQ_FADD = 277 CEFBS_None, // G_VECREDUCE_SEQ_FMUL = 278 CEFBS_None, // G_VECREDUCE_FADD = 279 CEFBS_None, // G_VECREDUCE_FMUL = 280 CEFBS_None, // G_VECREDUCE_FMAX = 281 CEFBS_None, // G_VECREDUCE_FMIN = 282 CEFBS_None, // G_VECREDUCE_FMAXIMUM = 283 CEFBS_None, // G_VECREDUCE_FMINIMUM = 284 CEFBS_None, // G_VECREDUCE_ADD = 285 CEFBS_None, // G_VECREDUCE_MUL = 286 CEFBS_None, // G_VECREDUCE_AND = 287 CEFBS_None, // G_VECREDUCE_OR = 288 CEFBS_None, // G_VECREDUCE_XOR = 289 CEFBS_None, // G_VECREDUCE_SMAX = 290 CEFBS_None, // G_VECREDUCE_SMIN = 291 CEFBS_None, // G_VECREDUCE_UMAX = 292 CEFBS_None, // G_VECREDUCE_UMIN = 293 CEFBS_None, // G_SBFX = 294 CEFBS_None, // G_UBFX = 295 CEFBS_None, // ADJCALLSTACKDOWN = 296 CEFBS_None, // ADJCALLSTACKUP = 297 CEFBS_None, // GETPCX = 298 CEFBS_None, // SELECT_CC_DFP_FCC = 299 CEFBS_None, // SELECT_CC_DFP_ICC = 300 CEFBS_None, // SELECT_CC_DFP_XCC = 301 CEFBS_None, // SELECT_CC_FP_FCC = 302 CEFBS_None, // SELECT_CC_FP_ICC = 303 CEFBS_None, // SELECT_CC_FP_XCC = 304 CEFBS_None, // SELECT_CC_Int_FCC = 305 CEFBS_None, // SELECT_CC_Int_ICC = 306 CEFBS_None, // SELECT_CC_Int_XCC = 307 CEFBS_None, // SELECT_CC_QFP_FCC = 308 CEFBS_None, // SELECT_CC_QFP_ICC = 309 CEFBS_None, // SELECT_CC_QFP_XCC = 310 CEFBS_None, // SET = 311 CEFBS_HasV9, // SETX = 312 CEFBS_None, // ADDCCri = 313 CEFBS_None, // ADDCCrr = 314 CEFBS_None, // ADDCri = 315 CEFBS_None, // ADDCrr = 316 CEFBS_None, // ADDEri = 317 CEFBS_None, // ADDErr = 318 CEFBS_HasVIS3, // ADDXC = 319 CEFBS_HasVIS3, // ADDXCCC = 320 CEFBS_None, // ADDri = 321 CEFBS_None, // ADDrr = 322 CEFBS_HasVIS, // ALIGNADDR = 323 CEFBS_HasVIS, // ALIGNADDRL = 324 CEFBS_None, // ANDCCri = 325 CEFBS_None, // ANDCCrr = 326 CEFBS_None, // ANDNCCri = 327 CEFBS_None, // ANDNCCrr = 328 CEFBS_None, // ANDNri = 329 CEFBS_None, // ANDNrr = 330 CEFBS_None, // ANDri = 331 CEFBS_None, // ANDrr = 332 CEFBS_HasVIS, // ARRAY16 = 333 CEFBS_HasVIS, // ARRAY32 = 334 CEFBS_HasVIS, // ARRAY8 = 335 CEFBS_None, // BA = 336 CEFBS_None, // BCOND = 337 CEFBS_None, // BCONDA = 338 CEFBS_None, // BINDri = 339 CEFBS_None, // BINDrr = 340 CEFBS_HasVIS2, // BMASK = 341 CEFBS_HasV9, // BPFCC = 342 CEFBS_HasV9, // BPFCCA = 343 CEFBS_HasV9, // BPFCCANT = 344 CEFBS_HasV9, // BPFCCNT = 345 CEFBS_HasV9, // BPICC = 346 CEFBS_HasV9, // BPICCA = 347 CEFBS_HasV9, // BPICCANT = 348 CEFBS_HasV9, // BPICCNT = 349 CEFBS_None, // BPR = 350 CEFBS_None, // BPRA = 351 CEFBS_None, // BPRANT = 352 CEFBS_None, // BPRNT = 353 CEFBS_None, // BPXCC = 354 CEFBS_None, // BPXCCA = 355 CEFBS_None, // BPXCCANT = 356 CEFBS_None, // BPXCCNT = 357 CEFBS_HasVIS2, // BSHUFFLE = 358 CEFBS_None, // CALL = 359 CEFBS_None, // CALLri = 360 CEFBS_None, // CALLrr = 361 CEFBS_HasV9, // CASAri = 362 CEFBS_HasCASA, // CASArr = 363 CEFBS_HasV9, // CASXAri = 364 CEFBS_HasV9, // CASXArr = 365 CEFBS_None, // CBCOND = 366 CEFBS_None, // CBCONDA = 367 CEFBS_HasVIS3, // CMASK16 = 368 CEFBS_HasVIS3, // CMASK32 = 369 CEFBS_HasVIS3, // CMASK8 = 370 CEFBS_HasV9, // DONE = 371 CEFBS_HasVIS, // EDGE16 = 372 CEFBS_HasVIS, // EDGE16L = 373 CEFBS_HasVIS2, // EDGE16LN = 374 CEFBS_HasVIS2, // EDGE16N = 375 CEFBS_HasVIS, // EDGE32 = 376 CEFBS_HasVIS, // EDGE32L = 377 CEFBS_HasVIS2, // EDGE32LN = 378 CEFBS_HasVIS2, // EDGE32N = 379 CEFBS_HasVIS, // EDGE8 = 380 CEFBS_HasVIS, // EDGE8L = 381 CEFBS_HasVIS2, // EDGE8LN = 382 CEFBS_HasVIS2, // EDGE8N = 383 CEFBS_HasV9, // FABSD = 384 CEFBS_HasV9, // FABSQ = 385 CEFBS_None, // FABSS = 386 CEFBS_None, // FADDD = 387 CEFBS_None, // FADDQ = 388 CEFBS_None, // FADDS = 389 CEFBS_HasVIS, // FALIGNADATA = 390 CEFBS_HasVIS, // FAND = 391 CEFBS_HasVIS, // FANDNOT1 = 392 CEFBS_HasVIS, // FANDNOT1S = 393 CEFBS_HasVIS, // FANDNOT2 = 394 CEFBS_HasVIS, // FANDNOT2S = 395 CEFBS_HasVIS, // FANDS = 396 CEFBS_None, // FBCOND = 397 CEFBS_None, // FBCONDA = 398 CEFBS_HasV9, // FBCONDA_V9 = 399 CEFBS_HasV9, // FBCOND_V9 = 400 CEFBS_HasVIS3, // FCHKSM16 = 401 CEFBS_None, // FCMPD = 402 CEFBS_HasV9, // FCMPD_V9 = 403 CEFBS_HasVIS, // FCMPEQ16 = 404 CEFBS_HasVIS, // FCMPEQ32 = 405 CEFBS_HasVIS, // FCMPGT16 = 406 CEFBS_HasVIS, // FCMPGT32 = 407 CEFBS_HasVIS, // FCMPLE16 = 408 CEFBS_HasVIS, // FCMPLE32 = 409 CEFBS_HasVIS, // FCMPNE16 = 410 CEFBS_HasVIS, // FCMPNE32 = 411 CEFBS_None, // FCMPQ = 412 CEFBS_HasV9, // FCMPQ_V9 = 413 CEFBS_None, // FCMPS = 414 CEFBS_HasV9, // FCMPS_V9 = 415 CEFBS_None, // FDIVD = 416 CEFBS_None, // FDIVQ = 417 CEFBS_None, // FDIVS = 418 CEFBS_None, // FDMULQ = 419 CEFBS_None, // FDTOI = 420 CEFBS_None, // FDTOQ = 421 CEFBS_None, // FDTOS = 422 CEFBS_None, // FDTOX = 423 CEFBS_HasVIS, // FEXPAND = 424 CEFBS_HasVIS3, // FHADDD = 425 CEFBS_HasVIS3, // FHADDS = 426 CEFBS_HasVIS3, // FHSUBD = 427 CEFBS_HasVIS3, // FHSUBS = 428 CEFBS_None, // FITOD = 429 CEFBS_None, // FITOQ = 430 CEFBS_None, // FITOS = 431 CEFBS_HasVIS3, // FLCMPD = 432 CEFBS_HasVIS3, // FLCMPS = 433 CEFBS_None, // FLUSH = 434 CEFBS_HasV9, // FLUSHW = 435 CEFBS_None, // FLUSHri = 436 CEFBS_None, // FLUSHrr = 437 CEFBS_HasVIS3, // FMEAN16 = 438 CEFBS_HasV9, // FMOVD = 439 CEFBS_HasV9, // FMOVD_FCC = 440 CEFBS_HasV9, // FMOVD_ICC = 441 CEFBS_None, // FMOVD_XCC = 442 CEFBS_HasV9, // FMOVQ = 443 CEFBS_HasV9, // FMOVQ_FCC = 444 CEFBS_HasV9, // FMOVQ_ICC = 445 CEFBS_None, // FMOVQ_XCC = 446 CEFBS_None, // FMOVRD = 447 CEFBS_None, // FMOVRQ = 448 CEFBS_None, // FMOVRS = 449 CEFBS_None, // FMOVS = 450 CEFBS_HasV9, // FMOVS_FCC = 451 CEFBS_HasV9, // FMOVS_ICC = 452 CEFBS_None, // FMOVS_XCC = 453 CEFBS_HasVIS, // FMUL8SUX16 = 454 CEFBS_HasVIS, // FMUL8ULX16 = 455 CEFBS_HasVIS, // FMUL8X16 = 456 CEFBS_HasVIS, // FMUL8X16AL = 457 CEFBS_HasVIS, // FMUL8X16AU = 458 CEFBS_None, // FMULD = 459 CEFBS_HasVIS, // FMULD8SUX16 = 460 CEFBS_HasVIS, // FMULD8ULX16 = 461 CEFBS_None, // FMULQ = 462 CEFBS_None, // FMULS = 463 CEFBS_HasVIS3, // FNADDD = 464 CEFBS_HasVIS3, // FNADDS = 465 CEFBS_HasVIS, // FNAND = 466 CEFBS_HasVIS, // FNANDS = 467 CEFBS_HasV9, // FNEGD = 468 CEFBS_HasV9, // FNEGQ = 469 CEFBS_None, // FNEGS = 470 CEFBS_HasVIS3, // FNHADDD = 471 CEFBS_HasVIS3, // FNHADDS = 472 CEFBS_HasVIS3, // FNMULD = 473 CEFBS_HasVIS3, // FNMULS = 474 CEFBS_HasVIS, // FNOR = 475 CEFBS_HasVIS, // FNORS = 476 CEFBS_HasVIS, // FNOT1 = 477 CEFBS_HasVIS, // FNOT1S = 478 CEFBS_HasVIS, // FNOT2 = 479 CEFBS_HasVIS, // FNOT2S = 480 CEFBS_HasVIS3, // FNSMULD = 481 CEFBS_HasVIS, // FONE = 482 CEFBS_HasVIS, // FONES = 483 CEFBS_HasVIS, // FOR = 484 CEFBS_HasVIS, // FORNOT1 = 485 CEFBS_HasVIS, // FORNOT1S = 486 CEFBS_HasVIS, // FORNOT2 = 487 CEFBS_HasVIS, // FORNOT2S = 488 CEFBS_HasVIS, // FORS = 489 CEFBS_HasVIS, // FPACK16 = 490 CEFBS_HasVIS, // FPACK32 = 491 CEFBS_HasVIS, // FPACKFIX = 492 CEFBS_HasVIS, // FPADD16 = 493 CEFBS_HasVIS, // FPADD16S = 494 CEFBS_HasVIS, // FPADD32 = 495 CEFBS_HasVIS, // FPADD32S = 496 CEFBS_HasVIS3, // FPADD64 = 497 CEFBS_HasVIS, // FPMERGE = 498 CEFBS_HasVIS, // FPSUB16 = 499 CEFBS_HasVIS, // FPSUB16S = 500 CEFBS_HasVIS, // FPSUB32 = 501 CEFBS_HasVIS, // FPSUB32S = 502 CEFBS_None, // FQTOD = 503 CEFBS_None, // FQTOI = 504 CEFBS_None, // FQTOS = 505 CEFBS_None, // FQTOX = 506 CEFBS_HasVIS3, // FSLAS16 = 507 CEFBS_HasVIS3, // FSLAS32 = 508 CEFBS_HasVIS3, // FSLL16 = 509 CEFBS_HasVIS3, // FSLL32 = 510 CEFBS_None, // FSMULD = 511 CEFBS_None, // FSQRTD = 512 CEFBS_None, // FSQRTQ = 513 CEFBS_None, // FSQRTS = 514 CEFBS_HasVIS3, // FSRA16 = 515 CEFBS_HasVIS3, // FSRA32 = 516 CEFBS_HasVIS, // FSRC1 = 517 CEFBS_HasVIS, // FSRC1S = 518 CEFBS_HasVIS, // FSRC2 = 519 CEFBS_HasVIS, // FSRC2S = 520 CEFBS_HasVIS3, // FSRL16 = 521 CEFBS_HasVIS3, // FSRL32 = 522 CEFBS_None, // FSTOD = 523 CEFBS_None, // FSTOI = 524 CEFBS_None, // FSTOQ = 525 CEFBS_None, // FSTOX = 526 CEFBS_None, // FSUBD = 527 CEFBS_None, // FSUBQ = 528 CEFBS_None, // FSUBS = 529 CEFBS_HasVIS, // FXNOR = 530 CEFBS_HasVIS, // FXNORS = 531 CEFBS_HasVIS, // FXOR = 532 CEFBS_HasVIS, // FXORS = 533 CEFBS_None, // FXTOD = 534 CEFBS_None, // FXTOQ = 535 CEFBS_None, // FXTOS = 536 CEFBS_HasVIS, // FZERO = 537 CEFBS_HasVIS, // FZEROS = 538 CEFBS_None, // GDOP_LDXrr = 539 CEFBS_None, // GDOP_LDrr = 540 CEFBS_None, // JMPLri = 541 CEFBS_None, // JMPLrr = 542 CEFBS_HasV9, // LDAri = 543 CEFBS_None, // LDArr = 544 CEFBS_None, // LDCSRri = 545 CEFBS_None, // LDCSRrr = 546 CEFBS_None, // LDCri = 547 CEFBS_None, // LDCrr = 548 CEFBS_HasV9, // LDDAri = 549 CEFBS_None, // LDDArr = 550 CEFBS_None, // LDDCri = 551 CEFBS_None, // LDDCrr = 552 CEFBS_HasV9, // LDDFAri = 553 CEFBS_HasV9, // LDDFArr = 554 CEFBS_None, // LDDFri = 555 CEFBS_None, // LDDFrr = 556 CEFBS_None, // LDDri = 557 CEFBS_None, // LDDrr = 558 CEFBS_HasV9, // LDFAri = 559 CEFBS_HasV9, // LDFArr = 560 CEFBS_None, // LDFSRri = 561 CEFBS_None, // LDFSRrr = 562 CEFBS_None, // LDFri = 563 CEFBS_None, // LDFrr = 564 CEFBS_HasV9, // LDQFAri = 565 CEFBS_HasV9, // LDQFArr = 566 CEFBS_HasV9, // LDQFri = 567 CEFBS_HasV9, // LDQFrr = 568 CEFBS_HasV9, // LDSBAri = 569 CEFBS_None, // LDSBArr = 570 CEFBS_None, // LDSBri = 571 CEFBS_None, // LDSBrr = 572 CEFBS_HasV9, // LDSHAri = 573 CEFBS_None, // LDSHArr = 574 CEFBS_None, // LDSHri = 575 CEFBS_None, // LDSHrr = 576 CEFBS_HasV9, // LDSTUBAri = 577 CEFBS_None, // LDSTUBArr = 578 CEFBS_None, // LDSTUBri = 579 CEFBS_None, // LDSTUBrr = 580 CEFBS_None, // LDSWAri = 581 CEFBS_None, // LDSWArr = 582 CEFBS_None, // LDSWri = 583 CEFBS_None, // LDSWrr = 584 CEFBS_HasV9, // LDUBAri = 585 CEFBS_None, // LDUBArr = 586 CEFBS_None, // LDUBri = 587 CEFBS_None, // LDUBrr = 588 CEFBS_HasV9, // LDUHAri = 589 CEFBS_None, // LDUHArr = 590 CEFBS_None, // LDUHri = 591 CEFBS_None, // LDUHrr = 592 CEFBS_None, // LDXAri = 593 CEFBS_None, // LDXArr = 594 CEFBS_HasV9, // LDXFSRri = 595 CEFBS_HasV9, // LDXFSRrr = 596 CEFBS_None, // LDXri = 597 CEFBS_None, // LDXrr = 598 CEFBS_None, // LDri = 599 CEFBS_None, // LDrr = 600 CEFBS_HasVIS3, // LZCNT = 601 CEFBS_HasV9, // MEMBARi = 602 CEFBS_HasVIS3, // MOVDTOX = 603 CEFBS_HasV9, // MOVFCCri = 604 CEFBS_HasV9, // MOVFCCrr = 605 CEFBS_HasV9, // MOVICCri = 606 CEFBS_HasV9, // MOVICCrr = 607 CEFBS_None, // MOVRri = 608 CEFBS_None, // MOVRrr = 609 CEFBS_HasVIS3, // MOVSTOSW = 610 CEFBS_HasVIS3, // MOVSTOUW = 611 CEFBS_HasVIS3, // MOVWTOS = 612 CEFBS_None, // MOVXCCri = 613 CEFBS_None, // MOVXCCrr = 614 CEFBS_HasVIS3, // MOVXTOD = 615 CEFBS_None, // MULSCCri = 616 CEFBS_None, // MULSCCrr = 617 CEFBS_None, // MULXri = 618 CEFBS_None, // MULXrr = 619 CEFBS_None, // NOP = 620 CEFBS_None, // ORCCri = 621 CEFBS_None, // ORCCrr = 622 CEFBS_None, // ORNCCri = 623 CEFBS_None, // ORNCCrr = 624 CEFBS_None, // ORNri = 625 CEFBS_None, // ORNrr = 626 CEFBS_None, // ORri = 627 CEFBS_None, // ORrr = 628 CEFBS_HasVIS, // PDIST = 629 CEFBS_HasVIS3, // PDISTN = 630 CEFBS_HasV9, // POPCrr = 631 CEFBS_HasV9, // PREFETCHAi = 632 CEFBS_HasV9, // PREFETCHAr = 633 CEFBS_HasV9, // PREFETCHi = 634 CEFBS_HasV9, // PREFETCHr = 635 CEFBS_HasPWRPSR, // PWRPSRri = 636 CEFBS_HasPWRPSR, // PWRPSRrr = 637 CEFBS_None, // RDASR = 638 CEFBS_HasV9, // RDFQ = 639 CEFBS_HasV9, // RDPR = 640 CEFBS_None, // RDPSR = 641 CEFBS_None, // RDTBR = 642 CEFBS_None, // RDWIM = 643 CEFBS_HasV9, // RESTORED = 644 CEFBS_None, // RESTOREri = 645 CEFBS_None, // RESTORErr = 646 CEFBS_None, // RET = 647 CEFBS_None, // RETL = 648 CEFBS_HasV9, // RETRY = 649 CEFBS_None, // RETTri = 650 CEFBS_None, // RETTrr = 651 CEFBS_HasV9, // SAVED = 652 CEFBS_None, // SAVEri = 653 CEFBS_None, // SAVErr = 654 CEFBS_None, // SDIVCCri = 655 CEFBS_None, // SDIVCCrr = 656 CEFBS_None, // SDIVXri = 657 CEFBS_None, // SDIVXrr = 658 CEFBS_None, // SDIVri = 659 CEFBS_None, // SDIVrr = 660 CEFBS_None, // SETHIi = 661 CEFBS_HasVIS, // SHUTDOWN = 662 CEFBS_HasVIS2, // SIAM = 663 CEFBS_HasV9, // SIR = 664 CEFBS_None, // SLLXri = 665 CEFBS_None, // SLLXrr = 666 CEFBS_None, // SLLri = 667 CEFBS_None, // SLLrr = 668 CEFBS_None, // SMACri = 669 CEFBS_None, // SMACrr = 670 CEFBS_None, // SMULCCri = 671 CEFBS_None, // SMULCCrr = 672 CEFBS_None, // SMULri = 673 CEFBS_None, // SMULrr = 674 CEFBS_None, // SRAXri = 675 CEFBS_None, // SRAXrr = 676 CEFBS_None, // SRAri = 677 CEFBS_None, // SRArr = 678 CEFBS_None, // SRLXri = 679 CEFBS_None, // SRLXrr = 680 CEFBS_None, // SRLri = 681 CEFBS_None, // SRLrr = 682 CEFBS_HasV9, // STAri = 683 CEFBS_None, // STArr = 684 CEFBS_None, // STBAR = 685 CEFBS_HasV9, // STBAri = 686 CEFBS_None, // STBArr = 687 CEFBS_None, // STBri = 688 CEFBS_None, // STBrr = 689 CEFBS_None, // STCSRri = 690 CEFBS_None, // STCSRrr = 691 CEFBS_None, // STCri = 692 CEFBS_None, // STCrr = 693 CEFBS_HasV9, // STDAri = 694 CEFBS_None, // STDArr = 695 CEFBS_None, // STDCQri = 696 CEFBS_None, // STDCQrr = 697 CEFBS_None, // STDCri = 698 CEFBS_None, // STDCrr = 699 CEFBS_HasV9, // STDFAri = 700 CEFBS_HasV9, // STDFArr = 701 CEFBS_None, // STDFQri = 702 CEFBS_None, // STDFQrr = 703 CEFBS_None, // STDFri = 704 CEFBS_None, // STDFrr = 705 CEFBS_None, // STDri = 706 CEFBS_None, // STDrr = 707 CEFBS_HasV9, // STFAri = 708 CEFBS_HasV9, // STFArr = 709 CEFBS_None, // STFSRri = 710 CEFBS_None, // STFSRrr = 711 CEFBS_None, // STFri = 712 CEFBS_None, // STFrr = 713 CEFBS_HasV9, // STHAri = 714 CEFBS_None, // STHArr = 715 CEFBS_None, // STHri = 716 CEFBS_None, // STHrr = 717 CEFBS_HasV9, // STQFAri = 718 CEFBS_HasV9, // STQFArr = 719 CEFBS_HasV9, // STQFri = 720 CEFBS_HasV9, // STQFrr = 721 CEFBS_None, // STXAri = 722 CEFBS_None, // STXArr = 723 CEFBS_HasV9, // STXFSRri = 724 CEFBS_HasV9, // STXFSRrr = 725 CEFBS_None, // STXri = 726 CEFBS_None, // STXrr = 727 CEFBS_None, // STri = 728 CEFBS_None, // STrr = 729 CEFBS_None, // SUBCCri = 730 CEFBS_None, // SUBCCrr = 731 CEFBS_None, // SUBCri = 732 CEFBS_None, // SUBCrr = 733 CEFBS_None, // SUBEri = 734 CEFBS_None, // SUBErr = 735 CEFBS_None, // SUBri = 736 CEFBS_None, // SUBrr = 737 CEFBS_HasV9, // SWAPAri = 738 CEFBS_None, // SWAPArr = 739 CEFBS_None, // SWAPri = 740 CEFBS_None, // SWAPrr = 741 CEFBS_None, // TA1 = 742 CEFBS_None, // TA3 = 743 CEFBS_None, // TA5 = 744 CEFBS_None, // TADDCCTVri = 745 CEFBS_None, // TADDCCTVrr = 746 CEFBS_None, // TADDCCri = 747 CEFBS_None, // TADDCCrr = 748 CEFBS_None, // TAIL_CALL = 749 CEFBS_None, // TAIL_CALLri = 750 CEFBS_HasV9, // TICCri = 751 CEFBS_HasV9, // TICCrr = 752 CEFBS_None, // TLS_ADDrr = 753 CEFBS_None, // TLS_CALL = 754 CEFBS_None, // TLS_LDXrr = 755 CEFBS_None, // TLS_LDrr = 756 CEFBS_None, // TRAPri = 757 CEFBS_None, // TRAPrr = 758 CEFBS_None, // TSUBCCTVri = 759 CEFBS_None, // TSUBCCTVrr = 760 CEFBS_None, // TSUBCCri = 761 CEFBS_None, // TSUBCCrr = 762 CEFBS_None, // TXCCri = 763 CEFBS_None, // TXCCrr = 764 CEFBS_None, // UDIVCCri = 765 CEFBS_None, // UDIVCCrr = 766 CEFBS_None, // UDIVXri = 767 CEFBS_None, // UDIVXrr = 768 CEFBS_None, // UDIVri = 769 CEFBS_None, // UDIVrr = 770 CEFBS_None, // UMACri = 771 CEFBS_None, // UMACrr = 772 CEFBS_None, // UMULCCri = 773 CEFBS_None, // UMULCCrr = 774 CEFBS_HasVIS3, // UMULXHI = 775 CEFBS_None, // UMULri = 776 CEFBS_None, // UMULrr = 777 CEFBS_None, // UNIMP = 778 CEFBS_None, // V9FCMPD = 779 CEFBS_None, // V9FCMPED = 780 CEFBS_None, // V9FCMPEQ = 781 CEFBS_None, // V9FCMPES = 782 CEFBS_None, // V9FCMPQ = 783 CEFBS_None, // V9FCMPS = 784 CEFBS_HasV9, // V9FMOVD_FCC = 785 CEFBS_HasV9, // V9FMOVQ_FCC = 786 CEFBS_HasV9, // V9FMOVS_FCC = 787 CEFBS_HasV9, // V9MOVFCCri = 788 CEFBS_HasV9, // V9MOVFCCrr = 789 CEFBS_None, // WRASRri = 790 CEFBS_None, // WRASRrr = 791 CEFBS_HasV9, // WRPRri = 792 CEFBS_HasV9, // WRPRrr = 793 CEFBS_None, // WRPSRri = 794 CEFBS_None, // WRPSRrr = 795 CEFBS_None, // WRTBRri = 796 CEFBS_None, // WRTBRrr = 797 CEFBS_None, // WRWIMri = 798 CEFBS_None, // WRWIMrr = 799 CEFBS_HasVIS3, // XMULX = 800 CEFBS_HasVIS3, // XMULXHI = 801 CEFBS_None, // XNORCCri = 802 CEFBS_None, // XNORCCrr = 803 CEFBS_None, // XNORri = 804 CEFBS_None, // XNORrr = 805 CEFBS_None, // XORCCri = 806 CEFBS_None, // XORCCrr = 807 CEFBS_None, // XORri = 808 CEFBS_None, // XORrr = 809 }; assert(Opcode < 810); return FeatureBitsets[RequiredFeaturesRefs[Opcode]]; } } // end namespace Sparc_MC } // end namespace llvm #endif // GET_COMPUTE_FEATURES #ifdef GET_AVAILABLE_OPCODE_CHECKER #undef GET_AVAILABLE_OPCODE_CHECKER namespace llvm { namespace Sparc_MC { bool isOpcodeAvailable(unsigned Opcode, const FeatureBitset &Features) { FeatureBitset AvailableFeatures = computeAvailableFeatures(Features); FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode); FeatureBitset MissingFeatures = (AvailableFeatures & RequiredFeatures) ^ RequiredFeatures; return !MissingFeatures.any(); } } // end namespace Sparc_MC } // end namespace llvm #endif // GET_AVAILABLE_OPCODE_CHECKER #ifdef ENABLE_INSTR_PREDICATE_VERIFIER #undef ENABLE_INSTR_PREDICATE_VERIFIER #include <sstream> namespace llvm { namespace Sparc_MC { #ifndef NDEBUG static const char *SubtargetFeatureNames[] = { "Feature_HasCASA", "Feature_HasPWRPSR", "Feature_HasV9", "Feature_HasVIS", "Feature_HasVIS2", "Feature_HasVIS3", "Feature_UseSoftMulDiv", nullptr }; #endif // NDEBUG void verifyInstructionPredicates( unsigned Opcode, const FeatureBitset &Features) { #ifndef NDEBUG FeatureBitset AvailableFeatures = computeAvailableFeatures(Features); FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode); FeatureBitset MissingFeatures = (AvailableFeatures & RequiredFeatures) ^ RequiredFeatures; if (MissingFeatures.any()) { std::ostringstream Msg; Msg << "Attempting to emit " << &SparcInstrNameData[SparcInstrNameIndices[Opcode]] << " instruction but the "; for (unsigned i = 0, e = MissingFeatures.size(); i != e; ++i) if (MissingFeatures.test(i)) Msg << SubtargetFeatureNames[i] << " "; Msg << "predicate(s) are not met"; report_fatal_error(Msg.str().c_str()); } #endif // NDEBUG } } // end namespace Sparc_MC } // end namespace llvm #endif // ENABLE_INSTR_PREDICATE_VERIFIER
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