SparcGenMCCodeEmitter.inc | Explore in Territory

/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
|*                                                                            *|
|* Machine Code Emitter                                                       *|
|*                                                                            *|
|* Automatically generated file, do not edit!                                 *|
|*                                                                            *|
\*===----------------------------------------------------------------------===*/

uint64_t SparcMCCodeEmitter::getBinaryCodeForInstr(const MCInst &MI,
    SmallVectorImpl<MCFixup> &Fixups,
    const MCSubtargetInfo &STI) const { … }

#ifdef GET_OPERAND_BIT_OFFSET
#undef GET_OPERAND_BIT_OFFSET

uint32_t SparcMCCodeEmitter::getOperandBitOffset(const MCInst &MI,
    unsigned OpNum,
    const MCSubtargetInfo &STI) const {
  switch (MI.getOpcode()) {
    case SP::DONE:
    case SP::FLUSH:
    case SP::FLUSHW:
    case SP::NOP:
    case SP::RESTORED:
    case SP::RETRY:
    case SP::SAVED:
    case SP::SHUTDOWN:
    case SP::SIAM:
    case SP::STBAR:
    case SP::TA1:
    case SP::TA3:
    case SP::TA5: {
      break;
    }
    case SP::CALL:
    case SP::TAIL_CALL:
    case SP::TLS_CALL: {
      switch (OpNum) {
      case 0:
        // op: disp
        return 0;
      }
      break;
    }
    case SP::BPR:
    case SP::BPRA:
    case SP::BPRANT:
    case SP::BPRNT: {
      switch (OpNum) {
      case 0:
        // op: imm16
        return 0;
      case 2:
        // op: rs1
        return 14;
      case 1:
        // op: rcond
        return 25;
      }
      break;
    }
    case SP::BCOND:
    case SP::BCONDA:
    case SP::CBCOND:
    case SP::CBCONDA:
    case SP::FBCOND:
    case SP::FBCONDA: {
      switch (OpNum) {
      case 0:
        // op: imm22
        return 0;
      case 1:
        // op: cond
        return 25;
      }
      break;
    }
    case SP::BA:
    case SP::UNIMP: {
      switch (OpNum) {
      case 0:
        // op: imm22
        return 0;
      }
      break;
    }
    case SP::V9MOVFCCrr: {
      switch (OpNum) {
      case 0:
        // op: rd
        return 25;
      case 1:
        // op: cc
        return 11;
      case 4:
        // op: cond
        return 14;
      case 2:
        // op: rs2
        return 0;
      }
      break;
    }
    case SP::V9MOVFCCri: {
      switch (OpNum) {
      case 0:
        // op: rd
        return 25;
      case 1:
        // op: cc
        return 11;
      case 4:
        // op: cond
        return 14;
      case 2:
        // op: simm11
        return 0;
      }
      break;
    }
    case SP::FMOVRD:
    case SP::FMOVRQ:
    case SP::FMOVRS:
    case SP::MOVRrr: {
      switch (OpNum) {
      case 0:
        // op: rd
        return 25;
      case 1:
        // op: rs1
        return 14;
      case 2:
        // op: rs2
        return 0;
      case 4:
        // op: rcond
        return 10;
      }
      break;
    }
    case SP::ADDCCrr:
    case SP::ADDCrr:
    case SP::ADDErr:
    case SP::ADDXC:
    case SP::ADDXCCC:
    case SP::ADDrr:
    case SP::ALIGNADDR:
    case SP::ALIGNADDRL:
    case SP::ANDCCrr:
    case SP::ANDNCCrr:
    case SP::ANDNrr:
    case SP::ANDrr:
    case SP::ARRAY8:
    case SP::ARRAY16:
    case SP::ARRAY32:
    case SP::BMASK:
    case SP::BSHUFFLE:
    case SP::CASAri:
    case SP::CASXAri:
    case SP::EDGE8:
    case SP::EDGE8L:
    case SP::EDGE8LN:
    case SP::EDGE8N:
    case SP::EDGE16:
    case SP::EDGE16L:
    case SP::EDGE16LN:
    case SP::EDGE16N:
    case SP::EDGE32:
    case SP::EDGE32L:
    case SP::EDGE32LN:
    case SP::EDGE32N:
    case SP::FADDD:
    case SP::FADDQ:
    case SP::FADDS:
    case SP::FALIGNADATA:
    case SP::FAND:
    case SP::FANDNOT1:
    case SP::FANDNOT1S:
    case SP::FANDNOT2:
    case SP::FANDNOT2S:
    case SP::FANDS:
    case SP::FCHKSM16:
    case SP::FCMPEQ16:
    case SP::FCMPEQ32:
    case SP::FCMPGT16:
    case SP::FCMPGT32:
    case SP::FCMPLE16:
    case SP::FCMPLE32:
    case SP::FCMPNE16:
    case SP::FCMPNE32:
    case SP::FDIVD:
    case SP::FDIVQ:
    case SP::FDIVS:
    case SP::FDMULQ:
    case SP::FHADDD:
    case SP::FHADDS:
    case SP::FHSUBD:
    case SP::FHSUBS:
    case SP::FLCMPD:
    case SP::FLCMPS:
    case SP::FMEAN16:
    case SP::FMUL8SUX16:
    case SP::FMUL8ULX16:
    case SP::FMUL8X16:
    case SP::FMUL8X16AL:
    case SP::FMUL8X16AU:
    case SP::FMULD:
    case SP::FMULD8SUX16:
    case SP::FMULD8ULX16:
    case SP::FMULQ:
    case SP::FMULS:
    case SP::FNADDD:
    case SP::FNADDS:
    case SP::FNAND:
    case SP::FNANDS:
    case SP::FNHADDD:
    case SP::FNHADDS:
    case SP::FNMULD:
    case SP::FNMULS:
    case SP::FNOR:
    case SP::FNORS:
    case SP::FNSMULD:
    case SP::FOR:
    case SP::FORNOT1:
    case SP::FORNOT1S:
    case SP::FORNOT2:
    case SP::FORNOT2S:
    case SP::FORS:
    case SP::FPACK32:
    case SP::FPADD16:
    case SP::FPADD16S:
    case SP::FPADD32:
    case SP::FPADD32S:
    case SP::FPADD64:
    case SP::FPMERGE:
    case SP::FPSUB16:
    case SP::FPSUB16S:
    case SP::FPSUB32:
    case SP::FPSUB32S:
    case SP::FSLAS16:
    case SP::FSLAS32:
    case SP::FSLL16:
    case SP::FSLL32:
    case SP::FSMULD:
    case SP::FSRA16:
    case SP::FSRA32:
    case SP::FSRL16:
    case SP::FSRL32:
    case SP::FSUBD:
    case SP::FSUBQ:
    case SP::FSUBS:
    case SP::FXNOR:
    case SP::FXNORS:
    case SP::FXOR:
    case SP::FXORS:
    case SP::GDOP_LDXrr:
    case SP::GDOP_LDrr:
    case SP::JMPLrr:
    case SP::LDCrr:
    case SP::LDDCrr:
    case SP::LDDFrr:
    case SP::LDDrr:
    case SP::LDFrr:
    case SP::LDQFrr:
    case SP::LDSBrr:
    case SP::LDSHrr:
    case SP::LDSTUBrr:
    case SP::LDSWrr:
    case SP::LDUBrr:
    case SP::LDUHrr:
    case SP::LDXrr:
    case SP::LDrr:
    case SP::MULSCCrr:
    case SP::MULXrr:
    case SP::ORCCrr:
    case SP::ORNCCrr:
    case SP::ORNrr:
    case SP::ORrr:
    case SP::PDIST:
    case SP::PDISTN:
    case SP::RESTORErr:
    case SP::SAVErr:
    case SP::SDIVCCrr:
    case SP::SDIVXrr:
    case SP::SDIVrr:
    case SP::SLLXrr:
    case SP::SLLrr:
    case SP::SMACrr:
    case SP::SMULCCrr:
    case SP::SMULrr:
    case SP::SRAXrr:
    case SP::SRArr:
    case SP::SRLXrr:
    case SP::SRLrr:
    case SP::SUBCCrr:
    case SP::SUBCrr:
    case SP::SUBErr:
    case SP::SUBrr:
    case SP::SWAPrr:
    case SP::TADDCCTVrr:
    case SP::TADDCCrr:
    case SP::TLS_ADDrr:
    case SP::TLS_LDXrr:
    case SP::TLS_LDrr:
    case SP::TSUBCCTVrr:
    case SP::TSUBCCrr:
    case SP::UDIVCCrr:
    case SP::UDIVXrr:
    case SP::UDIVrr:
    case SP::UMACrr:
    case SP::UMULCCrr:
    case SP::UMULXHI:
    case SP::UMULrr:
    case SP::V9FCMPD:
    case SP::V9FCMPED:
    case SP::V9FCMPEQ:
    case SP::V9FCMPES:
    case SP::V9FCMPQ:
    case SP::V9FCMPS:
    case SP::WRASRrr:
    case SP::WRPRrr:
    case SP::XMULX:
    case SP::XMULXHI:
    case SP::XNORCCrr:
    case SP::XNORrr:
    case SP::XORCCrr:
    case SP::XORrr: {
      switch (OpNum) {
      case 0:
        // op: rd
        return 25;
      case 1:
        // op: rs1
        return 14;
      case 2:
        // op: rs2
        return 0;
      }
      break;
    }
    case SP::SLLXri:
    case SP::SLLri:
    case SP::SRAXri:
    case SP::SRAri:
    case SP::SRLXri:
    case SP::SRLri: {
      switch (OpNum) {
      case 0:
        // op: rd
        return 25;
      case 1:
        // op: rs1
        return 14;
      case 2:
        // op: shcnt
        return 0;
      }
      break;
    }
    case SP::MOVRri: {
      switch (OpNum) {
      case 0:
        // op: rd
        return 25;
      case 1:
        // op: rs1
        return 14;
      case 2:
        // op: simm10
        return 0;
      case 4:
        // op: rcond
        return 10;
      }
      break;
    }
    case SP::ADDCCri:
    case SP::ADDCri:
    case SP::ADDEri:
    case SP::ADDri:
    case SP::ANDCCri:
    case SP::ANDNCCri:
    case SP::ANDNri:
    case SP::ANDri:
    case SP::JMPLri:
    case SP::LDAri:
    case SP::LDCri:
    case SP::LDDAri:
    case SP::LDDCri:
    case SP::LDDFAri:
    case SP::LDDFri:
    case SP::LDDri:
    case SP::LDFAri:
    case SP::LDFri:
    case SP::LDQFAri:
    case SP::LDQFri:
    case SP::LDSBAri:
    case SP::LDSBri:
    case SP::LDSHAri:
    case SP::LDSHri:
    case SP::LDSTUBAri:
    case SP::LDSTUBri:
    case SP::LDSWAri:
    case SP::LDSWri:
    case SP::LDUBAri:
    case SP::LDUBri:
    case SP::LDUHAri:
    case SP::LDUHri:
    case SP::LDXAri:
    case SP::LDXri:
    case SP::LDri:
    case SP::MULSCCri:
    case SP::MULXri:
    case SP::ORCCri:
    case SP::ORNCCri:
    case SP::ORNri:
    case SP::ORri:
    case SP::RESTOREri:
    case SP::SAVEri:
    case SP::SDIVCCri:
    case SP::SDIVXri:
    case SP::SDIVri:
    case SP::SMACri:
    case SP::SMULCCri:
    case SP::SMULri:
    case SP::SUBCCri:
    case SP::SUBCri:
    case SP::SUBEri:
    case SP::SUBri:
    case SP::SWAPAri:
    case SP::SWAPri:
    case SP::TADDCCTVri:
    case SP::TADDCCri:
    case SP::TSUBCCTVri:
    case SP::TSUBCCri:
    case SP::UDIVCCri:
    case SP::UDIVXri:
    case SP::UDIVri:
    case SP::UMACri:
    case SP::UMULCCri:
    case SP::UMULri:
    case SP::WRASRri:
    case SP::WRPRri:
    case SP::XNORCCri:
    case SP::XNORri:
    case SP::XORCCri:
    case SP::XORri: {
      switch (OpNum) {
      case 0:
        // op: rd
        return 25;
      case 1:
        // op: rs1
        return 14;
      case 2:
        // op: simm13
        return 0;
      }
      break;
    }
    case SP::LDArr:
    case SP::LDDArr:
    case SP::LDDFArr:
    case SP::LDFArr:
    case SP::LDQFArr:
    case SP::LDSBArr:
    case SP::LDSHArr:
    case SP::LDSTUBArr:
    case SP::LDSWArr:
    case SP::LDUBArr:
    case SP::LDUHArr:
    case SP::LDXArr:
    case SP::SWAPArr: {
      switch (OpNum) {
      case 0:
        // op: rd
        return 25;
      case 1:
        // op: rs1
        return 14;
      case 3:
        // op: asi
        return 5;
      case 2:
        // op: rs2
        return 0;
      }
      break;
    }
    case SP::CASArr:
    case SP::CASXArr: {
      switch (OpNum) {
      case 0:
        // op: rd
        return 25;
      case 1:
        // op: rs1
        return 14;
      case 4:
        // op: asi
        return 5;
      case 2:
        // op: rs2
        return 0;
      }
      break;
    }
    case SP::FNOT1:
    case SP::FNOT1S:
    case SP::FSRC1:
    case SP::FSRC1S:
    case SP::RDASR:
    case SP::RDPR: {
      switch (OpNum) {
      case 0:
        // op: rd
        return 25;
      case 1:
        // op: rs1
        return 14;
      }
      break;
    }
    case SP::FABSD:
    case SP::FABSQ:
    case SP::FABSS:
    case SP::FDTOI:
    case SP::FDTOQ:
    case SP::FDTOS:
    case SP::FDTOX:
    case SP::FEXPAND:
    case SP::FITOD:
    case SP::FITOQ:
    case SP::FITOS:
    case SP::FMOVD:
    case SP::FMOVQ:
    case SP::FMOVS:
    case SP::FNEGD:
    case SP::FNEGQ:
    case SP::FNEGS:
    case SP::FNOT2:
    case SP::FNOT2S:
    case SP::FPACK16:
    case SP::FPACKFIX:
    case SP::FQTOD:
    case SP::FQTOI:
    case SP::FQTOS:
    case SP::FQTOX:
    case SP::FSQRTD:
    case SP::FSQRTQ:
    case SP::FSQRTS:
    case SP::FSRC2:
    case SP::FSRC2S:
    case SP::FSTOD:
    case SP::FSTOI:
    case SP::FSTOQ:
    case SP::FSTOX:
    case SP::FXTOD:
    case SP::FXTOQ:
    case SP::FXTOS:
    case SP::LZCNT:
    case SP::MOVDTOX:
    case SP::MOVSTOSW:
    case SP::MOVSTOUW:
    case SP::MOVWTOS:
    case SP::MOVXTOD:
    case SP::POPCrr: {
      switch (OpNum) {
      case 0:
        // op: rd
        return 25;
      case 1:
        // op: rs2
        return 0;
      }
      break;
    }
    case SP::FMOVD_FCC:
    case SP::FMOVD_ICC:
    case SP::FMOVD_XCC:
    case SP::FMOVQ_FCC:
    case SP::FMOVQ_ICC:
    case SP::FMOVQ_XCC:
    case SP::FMOVS_FCC:
    case SP::FMOVS_ICC:
    case SP::FMOVS_XCC:
    case SP::MOVFCCrr:
    case SP::MOVICCrr:
    case SP::MOVXCCrr: {
      switch (OpNum) {
      case 0:
        // op: rd
        return 25;
      case 3:
        // op: cond
        return 14;
      case 1:
        // op: rs2
        return 0;
      }
      break;
    }
    case SP::MOVFCCri:
    case SP::MOVICCri:
    case SP::MOVXCCri: {
      switch (OpNum) {
      case 0:
        // op: rd
        return 25;
      case 3:
        // op: cond
        return 14;
      case 1:
        // op: simm11
        return 0;
      }
      break;
    }
    case SP::V9FMOVD_FCC:
    case SP::V9FMOVQ_FCC:
    case SP::V9FMOVS_FCC: {
      switch (OpNum) {
      case 0:
        // op: rd
        return 25;
      case 4:
        // op: cond
        return 14;
      case 1:
        // op: opf_cc
        return 11;
      case 2:
        // op: rs2
        return 0;
      }
      break;
    }
    case SP::FONE:
    case SP::FONES:
    case SP::FZERO:
    case SP::FZEROS:
    case SP::RDFQ:
    case SP::RDPSR:
    case SP::RDTBR:
    case SP::RDWIM: {
      switch (OpNum) {
      case 0:
        // op: rd
        return 25;
      }
      break;
    }
    case SP::BINDrr:
    case SP::CALLrr:
    case SP::FCMPD:
    case SP::FCMPD_V9:
    case SP::FCMPQ:
    case SP::FCMPQ_V9:
    case SP::FCMPS:
    case SP::FCMPS_V9:
    case SP::FLUSHrr:
    case SP::LDCSRrr:
    case SP::LDFSRrr:
    case SP::LDXFSRrr:
    case SP::PWRPSRrr:
    case SP::RETTrr:
    case SP::STCSRrr:
    case SP::STDCQrr:
    case SP::STDFQrr:
    case SP::STFSRrr:
    case SP::STXFSRrr:
    case SP::WRPSRrr:
    case SP::WRTBRrr:
    case SP::WRWIMrr: {
      switch (OpNum) {
      case 0:
        // op: rs1
        return 14;
      case 1:
        // op: rs2
        return 0;
      }
      break;
    }
    case SP::BINDri:
    case SP::CALLri:
    case SP::FLUSHri:
    case SP::LDCSRri:
    case SP::LDFSRri:
    case SP::LDXFSRri:
    case SP::PWRPSRri:
    case SP::RETTri:
    case SP::STCSRri:
    case SP::STDCQri:
    case SP::STDFQri:
    case SP::STFSRri:
    case SP::STXFSRri:
    case SP::TAIL_CALLri:
    case SP::WRPSRri:
    case SP::WRTBRri:
    case SP::WRWIMri: {
      switch (OpNum) {
      case 0:
        // op: rs1
        return 14;
      case 1:
        // op: simm13
        return 0;
      }
      break;
    }
    case SP::TICCri:
    case SP::TRAPri:
    case SP::TXCCri: {
      switch (OpNum) {
      case 0:
        // op: rs1
        return 14;
      case 2:
        // op: cond
        return 25;
      case 1:
        // op: imm
        return 0;
      }
      break;
    }
    case SP::TICCrr:
    case SP::TRAPrr:
    case SP::TXCCrr: {
      switch (OpNum) {
      case 0:
        // op: rs1
        return 14;
      case 2:
        // op: cond
        return 25;
      case 1:
        // op: rs2
        return 0;
      }
      break;
    }
    case SP::CMASK8:
    case SP::CMASK16:
    case SP::CMASK32: {
      switch (OpNum) {
      case 0:
        // op: rs2
        return 0;
      }
      break;
    }
    case SP::MEMBARi:
    case SP::RET:
    case SP::RETL:
    case SP::SIR: {
      switch (OpNum) {
      case 0:
        // op: simm13
        return 0;
      }
      break;
    }
    case SP::BPICC:
    case SP::BPICCA:
    case SP::BPICCANT:
    case SP::BPICCNT:
    case SP::BPXCC:
    case SP::BPXCCA:
    case SP::BPXCCANT:
    case SP::BPXCCNT:
    case SP::FBCONDA_V9:
    case SP::FBCOND_V9: {
      switch (OpNum) {
      case 1:
        // op: cond
        return 25;
      case 0:
        // op: imm19
        return 0;
      }
      break;
    }
    case SP::SETHIi: {
      switch (OpNum) {
      case 1:
        // op: imm22
        return 0;
      case 0:
        // op: rd
        return 25;
      }
      break;
    }
    case SP::BPFCC:
    case SP::BPFCCA:
    case SP::BPFCCANT:
    case SP::BPFCCNT: {
      switch (OpNum) {
      case 2:
        // op: cc
        return 20;
      case 1:
        // op: cond
        return 25;
      case 0:
        // op: imm19
        return 0;
      }
      break;
    }
    case SP::PREFETCHr:
    case SP::STBrr:
    case SP::STCrr:
    case SP::STDCrr:
    case SP::STDFrr:
    case SP::STDrr:
    case SP::STFrr:
    case SP::STHrr:
    case SP::STQFrr:
    case SP::STXrr:
    case SP::STrr: {
      switch (OpNum) {
      case 2:
        // op: rd
        return 25;
      case 0:
        // op: rs1
        return 14;
      case 1:
        // op: rs2
        return 0;
      }
      break;
    }
    case SP::PREFETCHAi:
    case SP::PREFETCHi:
    case SP::STAri:
    case SP::STBAri:
    case SP::STBri:
    case SP::STCri:
    case SP::STDAri:
    case SP::STDCri:
    case SP::STDFAri:
    case SP::STDFri:
    case SP::STDri:
    case SP::STFAri:
    case SP::STFri:
    case SP::STHAri:
    case SP::STHri:
    case SP::STQFAri:
    case SP::STQFri:
    case SP::STXAri:
    case SP::STXri:
    case SP::STri: {
      switch (OpNum) {
      case 2:
        // op: rd
        return 25;
      case 0:
        // op: rs1
        return 14;
      case 1:
        // op: simm13
        return 0;
      }
      break;
    }
    case SP::STArr:
    case SP::STBArr:
    case SP::STDArr:
    case SP::STDFArr:
    case SP::STFArr:
    case SP::STHArr:
    case SP::STQFArr:
    case SP::STXArr: {
      switch (OpNum) {
      case 2:
        // op: rd
        return 25;
      case 0:
        // op: rs1
        return 14;
      case 3:
        // op: asi
        return 5;
      case 1:
        // op: rs2
        return 0;
      }
      break;
    }
    case SP::PREFETCHAr: {
      switch (OpNum) {
      case 3:
        // op: rd
        return 25;
      case 0:
        // op: rs1
        return 14;
      case 2:
        // op: asi
        return 5;
      case 1:
        // op: rs2
        return 0;
      }
      break;
    }
  }
  std::string msg;
  raw_string_ostream Msg(msg);
  Msg << "Not supported instr[opcode]: " << MI << "[" << OpNum << "]";
  report_fatal_error(Msg.str().c_str());
}

#endif // GET_OPERAND_BIT_OFFSET
llvm/lib/Target/Sparc/SparcGenMCCodeEmitter.inc
