llvm/lib/Target/VE/VEGenMCCodeEmitter.inc

/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
|*                                                                            *|
|* Machine Code Emitter                                                       *|
|*                                                                            *|
|* Automatically generated file, do not edit!                                 *|
|*                                                                            *|
\*===----------------------------------------------------------------------===*/

uint64_t VEMCCodeEmitter::getBinaryCodeForInstr(const MCInst &MI,
    SmallVectorImpl<MCFixup> &Fixups,
    const MCSubtargetInfo &STI) const { … }

#ifdef GET_OPERAND_BIT_OFFSET
#undef GET_OPERAND_BIT_OFFSET

uint32_t VEMCCodeEmitter::getOperandBitOffset(const MCInst &MI,
    unsigned OpNum,
    const MCSubtargetInfo &STI) const {
  switch (MI.getOpcode()) {
    case VE::FENCEI:
    case VE::MONC:
    case VE::MONCHDB:
    case VE::NOP:
    case VE::RET:
    case VE::SVOB: {
      break;
    }
    case VE::BCFDiri:
    case VE::BCFDiri_nt:
    case VE::BCFDiri_t:
    case VE::BCFDizi:
    case VE::BCFDizi_nt:
    case VE::BCFDizi_t:
    case VE::BCFDrri:
    case VE::BCFDrri_nt:
    case VE::BCFDrri_t:
    case VE::BCFDrzi:
    case VE::BCFDrzi_nt:
    case VE::BCFDrzi_t:
    case VE::BCFLiri:
    case VE::BCFLiri_nt:
    case VE::BCFLiri_t:
    case VE::BCFLizi:
    case VE::BCFLizi_nt:
    case VE::BCFLizi_t:
    case VE::BCFLrri:
    case VE::BCFLrri_nt:
    case VE::BCFLrri_t:
    case VE::BCFLrzi:
    case VE::BCFLrzi_nt:
    case VE::BCFLrzi_t:
    case VE::BCFSiri:
    case VE::BCFSiri_nt:
    case VE::BCFSiri_t:
    case VE::BCFSizi:
    case VE::BCFSizi_nt:
    case VE::BCFSizi_t:
    case VE::BCFSrri:
    case VE::BCFSrri_nt:
    case VE::BCFSrri_t:
    case VE::BCFSrzi:
    case VE::BCFSrzi_nt:
    case VE::BCFSrzi_t:
    case VE::BCFWiri:
    case VE::BCFWiri_nt:
    case VE::BCFWiri_t:
    case VE::BCFWizi:
    case VE::BCFWizi_nt:
    case VE::BCFWizi_t:
    case VE::BCFWrri:
    case VE::BCFWrri_nt:
    case VE::BCFWrri_t:
    case VE::BCFWrzi:
    case VE::BCFWrzi_nt:
    case VE::BCFWrzi_t:
    case VE::BRCFDir:
    case VE::BRCFDir_nt:
    case VE::BRCFDir_t:
    case VE::BRCFDiz:
    case VE::BRCFDiz_nt:
    case VE::BRCFDiz_t:
    case VE::BRCFDrr:
    case VE::BRCFDrr_nt:
    case VE::BRCFDrr_t:
    case VE::BRCFDrz:
    case VE::BRCFDrz_nt:
    case VE::BRCFDrz_t:
    case VE::BRCFLir:
    case VE::BRCFLir_nt:
    case VE::BRCFLir_t:
    case VE::BRCFLiz:
    case VE::BRCFLiz_nt:
    case VE::BRCFLiz_t:
    case VE::BRCFLrr:
    case VE::BRCFLrr_nt:
    case VE::BRCFLrr_t:
    case VE::BRCFLrz:
    case VE::BRCFLrz_nt:
    case VE::BRCFLrz_t:
    case VE::BRCFSir:
    case VE::BRCFSir_nt:
    case VE::BRCFSir_t:
    case VE::BRCFSiz:
    case VE::BRCFSiz_nt:
    case VE::BRCFSiz_t:
    case VE::BRCFSrr:
    case VE::BRCFSrr_nt:
    case VE::BRCFSrr_t:
    case VE::BRCFSrz:
    case VE::BRCFSrz_nt:
    case VE::BRCFSrz_t:
    case VE::BRCFWir:
    case VE::BRCFWir_nt:
    case VE::BRCFWir_t:
    case VE::BRCFWiz:
    case VE::BRCFWiz_nt:
    case VE::BRCFWiz_t:
    case VE::BRCFWrr:
    case VE::BRCFWrr_nt:
    case VE::BRCFWrr_t:
    case VE::BRCFWrz:
    case VE::BRCFWrz_nt:
    case VE::BRCFWrz_t: {
      switch (OpNum) {
      case 0:
        // op: cond
        return 48;
      case 1:
        // op: sy
        return 40;
      case 2:
        // op: sz
        return 32;
      case 3:
        // op: imm32
        return 0;
      }
      break;
    }
    case VE::BRCFDa:
    case VE::BRCFDa_nt:
    case VE::BRCFDa_t:
    case VE::BRCFDna:
    case VE::BRCFDna_nt:
    case VE::BRCFDna_t:
    case VE::BRCFLa:
    case VE::BRCFLa_nt:
    case VE::BRCFLa_t:
    case VE::BRCFLna:
    case VE::BRCFLna_nt:
    case VE::BRCFLna_t:
    case VE::BRCFSa:
    case VE::BRCFSa_nt:
    case VE::BRCFSa_t:
    case VE::BRCFSna:
    case VE::BRCFSna_nt:
    case VE::BRCFSna_t:
    case VE::BRCFWa:
    case VE::BRCFWa_nt:
    case VE::BRCFWa_t:
    case VE::BRCFWna:
    case VE::BRCFWna_nt:
    case VE::BRCFWna_t: {
      switch (OpNum) {
      case 0:
        // op: imm32
        return 0;
      }
      break;
    }
    case VE::FENCEC: {
      switch (OpNum) {
      case 0:
        // op: kind
        return 40;
      }
      break;
    }
    case VE::FENCEM: {
      switch (OpNum) {
      case 0:
        // op: kind
        return 48;
      }
      break;
    }
    case VE::ADDSLim:
    case VE::ADDSLrm:
    case VE::ADDSLrr:
    case VE::ADDSWSXim:
    case VE::ADDSWSXrm:
    case VE::ADDSWSXrr:
    case VE::ADDSWZXim:
    case VE::ADDSWZXrm:
    case VE::ADDSWZXrr:
    case VE::ADDULim:
    case VE::ADDULrm:
    case VE::ADDULrr:
    case VE::ADDUWim:
    case VE::ADDUWrm:
    case VE::ADDUWrr:
    case VE::ANDim:
    case VE::ANDrm:
    case VE::ANDrr:
    case VE::CMPSLim:
    case VE::CMPSLir:
    case VE::CMPSLrm:
    case VE::CMPSLrr:
    case VE::CMPSWSXim:
    case VE::CMPSWSXir:
    case VE::CMPSWSXrm:
    case VE::CMPSWSXrr:
    case VE::CMPSWZXim:
    case VE::CMPSWZXir:
    case VE::CMPSWZXrm:
    case VE::CMPSWZXrr:
    case VE::CMPULim:
    case VE::CMPULir:
    case VE::CMPULrm:
    case VE::CMPULrr:
    case VE::CMPUWim:
    case VE::CMPUWir:
    case VE::CMPUWrm:
    case VE::CMPUWrr:
    case VE::DIVSLim:
    case VE::DIVSLir:
    case VE::DIVSLrm:
    case VE::DIVSLrr:
    case VE::DIVSWSXim:
    case VE::DIVSWSXir:
    case VE::DIVSWSXrm:
    case VE::DIVSWSXrr:
    case VE::DIVSWZXim:
    case VE::DIVSWZXir:
    case VE::DIVSWZXrm:
    case VE::DIVSWZXrr:
    case VE::DIVULim:
    case VE::DIVULir:
    case VE::DIVULrm:
    case VE::DIVULrr:
    case VE::DIVUWim:
    case VE::DIVUWir:
    case VE::DIVUWrm:
    case VE::DIVUWrr:
    case VE::EQVim:
    case VE::EQVrm:
    case VE::EQVrr:
    case VE::FADDDim:
    case VE::FADDDir:
    case VE::FADDDrm:
    case VE::FADDDrr:
    case VE::FADDQim:
    case VE::FADDQir:
    case VE::FADDQrm:
    case VE::FADDQrr:
    case VE::FADDSim:
    case VE::FADDSir:
    case VE::FADDSrm:
    case VE::FADDSrr:
    case VE::FCMPDim:
    case VE::FCMPDir:
    case VE::FCMPDrm:
    case VE::FCMPDrr:
    case VE::FCMPQim:
    case VE::FCMPQir:
    case VE::FCMPQrm:
    case VE::FCMPQrr:
    case VE::FCMPSim:
    case VE::FCMPSir:
    case VE::FCMPSrm:
    case VE::FCMPSrr:
    case VE::FDIVDim:
    case VE::FDIVDir:
    case VE::FDIVDrm:
    case VE::FDIVDrr:
    case VE::FDIVSim:
    case VE::FDIVSir:
    case VE::FDIVSrm:
    case VE::FDIVSrr:
    case VE::FIDCRii:
    case VE::FIDCRri:
    case VE::FMAXDim:
    case VE::FMAXDir:
    case VE::FMAXDrm:
    case VE::FMAXDrr:
    case VE::FMAXSim:
    case VE::FMAXSir:
    case VE::FMAXSrm:
    case VE::FMAXSrr:
    case VE::FMINDim:
    case VE::FMINDir:
    case VE::FMINDrm:
    case VE::FMINDrr:
    case VE::FMINSim:
    case VE::FMINSir:
    case VE::FMINSrm:
    case VE::FMINSrr:
    case VE::FMULDim:
    case VE::FMULDir:
    case VE::FMULDrm:
    case VE::FMULDrr:
    case VE::FMULQim:
    case VE::FMULQir:
    case VE::FMULQrm:
    case VE::FMULQrr:
    case VE::FMULSim:
    case VE::FMULSir:
    case VE::FMULSrm:
    case VE::FMULSrr:
    case VE::FSUBDim:
    case VE::FSUBDir:
    case VE::FSUBDrm:
    case VE::FSUBDrr:
    case VE::FSUBQim:
    case VE::FSUBQir:
    case VE::FSUBQrm:
    case VE::FSUBQrr:
    case VE::FSUBSim:
    case VE::FSUBSir:
    case VE::FSUBSrm:
    case VE::FSUBSrr:
    case VE::LCRir:
    case VE::LCRiz:
    case VE::LCRrr:
    case VE::LCRrz:
    case VE::MAXSLim:
    case VE::MAXSLrm:
    case VE::MAXSLrr:
    case VE::MAXSWSXim:
    case VE::MAXSWSXrm:
    case VE::MAXSWSXrr:
    case VE::MAXSWZXim:
    case VE::MAXSWZXrm:
    case VE::MAXSWZXrr:
    case VE::MINSLim:
    case VE::MINSLrm:
    case VE::MINSLrr:
    case VE::MINSWSXim:
    case VE::MINSWSXrm:
    case VE::MINSWSXrr:
    case VE::MINSWZXim:
    case VE::MINSWZXrm:
    case VE::MINSWZXrr:
    case VE::MRGim:
    case VE::MRGir:
    case VE::MRGrm:
    case VE::MRGrr:
    case VE::MULSLWim:
    case VE::MULSLWrm:
    case VE::MULSLWrr:
    case VE::MULSLim:
    case VE::MULSLrm:
    case VE::MULSLrr:
    case VE::MULSWSXim:
    case VE::MULSWSXrm:
    case VE::MULSWSXrr:
    case VE::MULSWZXim:
    case VE::MULSWZXrm:
    case VE::MULSWZXrr:
    case VE::MULULim:
    case VE::MULULrm:
    case VE::MULULrr:
    case VE::MULUWim:
    case VE::MULUWrm:
    case VE::MULUWrr:
    case VE::NNDim:
    case VE::NNDir:
    case VE::NNDrm:
    case VE::NNDrr:
    case VE::ORim:
    case VE::ORrm:
    case VE::ORrr:
    case VE::SUBSLim:
    case VE::SUBSLir:
    case VE::SUBSLrm:
    case VE::SUBSLrr:
    case VE::SUBSWSXim:
    case VE::SUBSWSXir:
    case VE::SUBSWSXrm:
    case VE::SUBSWSXrr:
    case VE::SUBSWZXim:
    case VE::SUBSWZXir:
    case VE::SUBSWZXrm:
    case VE::SUBSWZXrr:
    case VE::SUBULim:
    case VE::SUBULir:
    case VE::SUBULrm:
    case VE::SUBULrr:
    case VE::SUBUWim:
    case VE::SUBUWir:
    case VE::SUBUWrm:
    case VE::SUBUWrr:
    case VE::TSCRirr:
    case VE::TSCRizr:
    case VE::TSCRrrr:
    case VE::TSCRrzr:
    case VE::XORim:
    case VE::XORrm:
    case VE::XORrr: {
      switch (OpNum) {
      case 0:
        // op: sx
        return 48;
      case 1:
        // op: sy
        return 40;
      case 2:
        // op: sz
        return 32;
      }
      break;
    }
    case VE::CVTDLi:
    case VE::CVTDLr:
    case VE::CVTDQi:
    case VE::CVTDQr:
    case VE::CVTDSi:
    case VE::CVTDSr:
    case VE::CVTDWi:
    case VE::CVTDWr:
    case VE::CVTQDi:
    case VE::CVTQDr:
    case VE::CVTQSi:
    case VE::CVTQSr:
    case VE::CVTSDi:
    case VE::CVTSDr:
    case VE::CVTSQi:
    case VE::CVTSQr:
    case VE::CVTSWi:
    case VE::CVTSWr:
    case VE::SMIR: {
      switch (OpNum) {
      case 0:
        // op: sx
        return 48;
      case 1:
        // op: sy
        return 40;
      }
      break;
    }
    case VE::LHMBri:
    case VE::LHMBzi:
    case VE::LHMHri:
    case VE::LHMHzi:
    case VE::LHMLri:
    case VE::LHMLzi:
    case VE::LHMWri:
    case VE::LHMWzi: {
      switch (OpNum) {
      case 0:
        // op: sx
        return 48;
      case 1:
        // op: sz
        return 32;
      case 2:
        // op: imm32
        return 0;
      }
      break;
    }
    case VE::BSICrii:
    case VE::BSICrri:
    case VE::BSICzii:
    case VE::BSICzri:
    case VE::DLDLSXrii:
    case VE::DLDLSXrri:
    case VE::DLDLSXzii:
    case VE::DLDLSXzri:
    case VE::DLDLZXrii:
    case VE::DLDLZXrri:
    case VE::DLDLZXzii:
    case VE::DLDLZXzri:
    case VE::DLDUrii:
    case VE::DLDUrri:
    case VE::DLDUzii:
    case VE::DLDUzri:
    case VE::DLDrii:
    case VE::DLDrri:
    case VE::DLDzii:
    case VE::DLDzri:
    case VE::LD1BSXrii:
    case VE::LD1BSXrri:
    case VE::LD1BSXzii:
    case VE::LD1BSXzri:
    case VE::LD1BZXrii:
    case VE::LD1BZXrri:
    case VE::LD1BZXzii:
    case VE::LD1BZXzri:
    case VE::LD2BSXrii:
    case VE::LD2BSXrri:
    case VE::LD2BSXzii:
    case VE::LD2BSXzri:
    case VE::LD2BZXrii:
    case VE::LD2BZXrri:
    case VE::LD2BZXzii:
    case VE::LD2BZXzri:
    case VE::LDLSXrii:
    case VE::LDLSXrri:
    case VE::LDLSXzii:
    case VE::LDLSXzri:
    case VE::LDLZXrii:
    case VE::LDLZXrri:
    case VE::LDLZXzii:
    case VE::LDLZXzri:
    case VE::LDUrii:
    case VE::LDUrri:
    case VE::LDUzii:
    case VE::LDUzri:
    case VE::LDrii:
    case VE::LDrri:
    case VE::LDzii:
    case VE::LDzri:
    case VE::LEASLrii:
    case VE::LEASLrri:
    case VE::LEASLzii:
    case VE::LEASLzri:
    case VE::LEArii:
    case VE::LEArri:
    case VE::LEAzii:
    case VE::LEAzri: {
      switch (OpNum) {
      case 0:
        // op: sx
        return 48;
      case 1:
        // op: sz
        return 32;
      case 2:
        // op: sy
        return 40;
      case 3:
        // op: imm32
        return 0;
      }
      break;
    }
    case VE::ATMAMrii:
    case VE::ATMAMrir:
    case VE::ATMAMzii:
    case VE::ATMAMzir:
    case VE::CASLrii:
    case VE::CASLrir:
    case VE::CASLzii:
    case VE::CASLzir:
    case VE::CASWrii:
    case VE::CASWrir:
    case VE::CASWzii:
    case VE::CASWzir:
    case VE::TS1AMLrii:
    case VE::TS1AMLrir:
    case VE::TS1AMLzii:
    case VE::TS1AMLzir:
    case VE::TS1AMWrii:
    case VE::TS1AMWrir:
    case VE::TS1AMWzii:
    case VE::TS1AMWzir:
    case VE::TS2AMrii:
    case VE::TS2AMrir:
    case VE::TS2AMzii:
    case VE::TS2AMzir:
    case VE::TS3AMrii:
    case VE::TS3AMrir:
    case VE::TS3AMzii:
    case VE::TS3AMzir: {
      switch (OpNum) {
      case 0:
        // op: sx
        return 48;
      case 1:
        // op: sz
        return 32;
      case 3:
        // op: sy
        return 40;
      case 2:
        // op: imm32
        return 0;
      }
      break;
    }
    case VE::BRVm:
    case VE::BRVr:
    case VE::LDZm:
    case VE::LDZr:
    case VE::PCNTm:
    case VE::PCNTr: {
      switch (OpNum) {
      case 0:
        // op: sx
        return 48;
      case 1:
        // op: sz
        return 32;
      }
      break;
    }
    case VE::CVTLDi:
    case VE::CVTLDr:
    case VE::CVTWDSXi:
    case VE::CVTWDSXr:
    case VE::CVTWDZXi:
    case VE::CVTWDZXr:
    case VE::CVTWSSXi:
    case VE::CVTWSSXr:
    case VE::CVTWSZXi:
    case VE::CVTWSZXr: {
      switch (OpNum) {
      case 0:
        // op: sx
        return 48;
      case 2:
        // op: sy
        return 40;
      case 1:
        // op: rd
        return 32;
      }
      break;
    }
    case VE::ADDSLri:
    case VE::ADDSWSXri:
    case VE::ADDSWZXri:
    case VE::ADDULri:
    case VE::ADDUWri:
    case VE::ANDri:
    case VE::BSWPmi:
    case VE::BSWPri:
    case VE::EQVri:
    case VE::MAXSLri:
    case VE::MAXSWSXri:
    case VE::MAXSWZXri:
    case VE::MINSLri:
    case VE::MINSWSXri:
    case VE::MINSWZXri:
    case VE::MULSLWri:
    case VE::MULSLri:
    case VE::MULSWSXri:
    case VE::MULSWZXri:
    case VE::MULULri:
    case VE::MULUWri:
    case VE::ORri:
    case VE::SLALmi:
    case VE::SLALmr:
    case VE::SLALri:
    case VE::SLALrr:
    case VE::SLAWSXmi:
    case VE::SLAWSXmr:
    case VE::SLAWSXri:
    case VE::SLAWSXrr:
    case VE::SLAWZXmi:
    case VE::SLAWZXmr:
    case VE::SLAWZXri:
    case VE::SLAWZXrr:
    case VE::SLLmi:
    case VE::SLLmr:
    case VE::SLLri:
    case VE::SLLrr:
    case VE::SRALmi:
    case VE::SRALmr:
    case VE::SRALri:
    case VE::SRALrr:
    case VE::SRAWSXmi:
    case VE::SRAWSXmr:
    case VE::SRAWSXri:
    case VE::SRAWSXrr:
    case VE::SRAWZXmi:
    case VE::SRAWZXmr:
    case VE::SRAWZXri:
    case VE::SRAWZXrr:
    case VE::SRLmi:
    case VE::SRLmr:
    case VE::SRLri:
    case VE::SRLrr:
    case VE::XORri: {
      switch (OpNum) {
      case 0:
        // op: sx
        return 48;
      case 2:
        // op: sy
        return 40;
      case 1:
        // op: sz
        return 32;
      }
      break;
    }
    case VE::LVSvi:
    case VE::LVSvr: {
      switch (OpNum) {
      case 0:
        // op: sx
        return 48;
      case 2:
        // op: sy
        return 40;
      case 1:
        // op: vx
        return 24;
      }
      break;
    }
    case VE::SVMmi:
    case VE::SVMmr: {
      switch (OpNum) {
      case 0:
        // op: sx
        return 48;
      case 2:
        // op: sy
        return 40;
      case 1:
        // op: vz
        return 8;
      }
      break;
    }
    case VE::CMOVDim:
    case VE::CMOVDir:
    case VE::CMOVDrm:
    case VE::CMOVDrr:
    case VE::CMOVLim:
    case VE::CMOVLir:
    case VE::CMOVLrm:
    case VE::CMOVLrr:
    case VE::CMOVSim:
    case VE::CMOVSir:
    case VE::CMOVSrm:
    case VE::CMOVSrr:
    case VE::CMOVWim:
    case VE::CMOVWir:
    case VE::CMOVWrm:
    case VE::CMOVWrr: {
      switch (OpNum) {
      case 0:
        // op: sx
        return 48;
      case 2:
        // op: sy
        return 40;
      case 3:
        // op: sz
        return 32;
      case 1:
        // op: cfw
        return 0;
      }
      break;
    }
    case VE::SRDmri:
    case VE::SRDmrr:
    case VE::SRDrri:
    case VE::SRDrrr: {
      switch (OpNum) {
      case 0:
        // op: sx
        return 48;
      case 3:
        // op: sy
        return 40;
      case 1:
        // op: sz
        return 32;
      }
      break;
    }
    case VE::SLDrmi:
    case VE::SLDrmr:
    case VE::SLDrri:
    case VE::SLDrrr: {
      switch (OpNum) {
      case 0:
        // op: sx
        return 48;
      case 3:
        // op: sy
        return 40;
      case 2:
        // op: sz
        return 32;
      }
      break;
    }
    case VE::SFR:
    case VE::SIC:
    case VE::SMVL:
    case VE::SPM:
    case VE::SVL: {
      switch (OpNum) {
      case 0:
        // op: sx
        return 48;
      }
      break;
    }
    case VE::VST2DNCOTirv:
    case VE::VST2DNCOTirvL:
    case VE::VST2DNCOTirvl:
    case VE::VST2DNCOTizv:
    case VE::VST2DNCOTizvL:
    case VE::VST2DNCOTizvl:
    case VE::VST2DNCOTrrv:
    case VE::VST2DNCOTrrvL:
    case VE::VST2DNCOTrrvl:
    case VE::VST2DNCOTrzv:
    case VE::VST2DNCOTrzvL:
    case VE::VST2DNCOTrzvl:
    case VE::VST2DNCirv:
    case VE::VST2DNCirvL:
    case VE::VST2DNCirvl:
    case VE::VST2DNCizv:
    case VE::VST2DNCizvL:
    case VE::VST2DNCizvl:
    case VE::VST2DNCrrv:
    case VE::VST2DNCrrvL:
    case VE::VST2DNCrrvl:
    case VE::VST2DNCrzv:
    case VE::VST2DNCrzvL:
    case VE::VST2DNCrzvl:
    case VE::VST2DOTirv:
    case VE::VST2DOTirvL:
    case VE::VST2DOTirvl:
    case VE::VST2DOTizv:
    case VE::VST2DOTizvL:
    case VE::VST2DOTizvl:
    case VE::VST2DOTrrv:
    case VE::VST2DOTrrvL:
    case VE::VST2DOTrrvl:
    case VE::VST2DOTrzv:
    case VE::VST2DOTrzvL:
    case VE::VST2DOTrzvl:
    case VE::VST2Dirv:
    case VE::VST2DirvL:
    case VE::VST2Dirvl:
    case VE::VST2Dizv:
    case VE::VST2DizvL:
    case VE::VST2Dizvl:
    case VE::VST2Drrv:
    case VE::VST2DrrvL:
    case VE::VST2Drrvl:
    case VE::VST2Drzv:
    case VE::VST2DrzvL:
    case VE::VST2Drzvl:
    case VE::VSTL2DNCOTirv:
    case VE::VSTL2DNCOTirvL:
    case VE::VSTL2DNCOTirvl:
    case VE::VSTL2DNCOTizv:
    case VE::VSTL2DNCOTizvL:
    case VE::VSTL2DNCOTizvl:
    case VE::VSTL2DNCOTrrv:
    case VE::VSTL2DNCOTrrvL:
    case VE::VSTL2DNCOTrrvl:
    case VE::VSTL2DNCOTrzv:
    case VE::VSTL2DNCOTrzvL:
    case VE::VSTL2DNCOTrzvl:
    case VE::VSTL2DNCirv:
    case VE::VSTL2DNCirvL:
    case VE::VSTL2DNCirvl:
    case VE::VSTL2DNCizv:
    case VE::VSTL2DNCizvL:
    case VE::VSTL2DNCizvl:
    case VE::VSTL2DNCrrv:
    case VE::VSTL2DNCrrvL:
    case VE::VSTL2DNCrrvl:
    case VE::VSTL2DNCrzv:
    case VE::VSTL2DNCrzvL:
    case VE::VSTL2DNCrzvl:
    case VE::VSTL2DOTirv:
    case VE::VSTL2DOTirvL:
    case VE::VSTL2DOTirvl:
    case VE::VSTL2DOTizv:
    case VE::VSTL2DOTizvL:
    case VE::VSTL2DOTizvl:
    case VE::VSTL2DOTrrv:
    case VE::VSTL2DOTrrvL:
    case VE::VSTL2DOTrrvl:
    case VE::VSTL2DOTrzv:
    case VE::VSTL2DOTrzvL:
    case VE::VSTL2DOTrzvl:
    case VE::VSTL2Dirv:
    case VE::VSTL2DirvL:
    case VE::VSTL2Dirvl:
    case VE::VSTL2Dizv:
    case VE::VSTL2DizvL:
    case VE::VSTL2Dizvl:
    case VE::VSTL2Drrv:
    case VE::VSTL2DrrvL:
    case VE::VSTL2Drrvl:
    case VE::VSTL2Drzv:
    case VE::VSTL2DrzvL:
    case VE::VSTL2Drzvl:
    case VE::VSTLNCOTirv:
    case VE::VSTLNCOTirvL:
    case VE::VSTLNCOTirvl:
    case VE::VSTLNCOTizv:
    case VE::VSTLNCOTizvL:
    case VE::VSTLNCOTizvl:
    case VE::VSTLNCOTrrv:
    case VE::VSTLNCOTrrvL:
    case VE::VSTLNCOTrrvl:
    case VE::VSTLNCOTrzv:
    case VE::VSTLNCOTrzvL:
    case VE::VSTLNCOTrzvl:
    case VE::VSTLNCirv:
    case VE::VSTLNCirvL:
    case VE::VSTLNCirvl:
    case VE::VSTLNCizv:
    case VE::VSTLNCizvL:
    case VE::VSTLNCizvl:
    case VE::VSTLNCrrv:
    case VE::VSTLNCrrvL:
    case VE::VSTLNCrrvl:
    case VE::VSTLNCrzv:
    case VE::VSTLNCrzvL:
    case VE::VSTLNCrzvl:
    case VE::VSTLOTirv:
    case VE::VSTLOTirvL:
    case VE::VSTLOTirvl:
    case VE::VSTLOTizv:
    case VE::VSTLOTizvL:
    case VE::VSTLOTizvl:
    case VE::VSTLOTrrv:
    case VE::VSTLOTrrvL:
    case VE::VSTLOTrrvl:
    case VE::VSTLOTrzv:
    case VE::VSTLOTrzvL:
    case VE::VSTLOTrzvl:
    case VE::VSTLirv:
    case VE::VSTLirvL:
    case VE::VSTLirvl:
    case VE::VSTLizv:
    case VE::VSTLizvL:
    case VE::VSTLizvl:
    case VE::VSTLrrv:
    case VE::VSTLrrvL:
    case VE::VSTLrrvl:
    case VE::VSTLrzv:
    case VE::VSTLrzvL:
    case VE::VSTLrzvl:
    case VE::VSTNCOTirv:
    case VE::VSTNCOTirvL:
    case VE::VSTNCOTirvl:
    case VE::VSTNCOTizv:
    case VE::VSTNCOTizvL:
    case VE::VSTNCOTizvl:
    case VE::VSTNCOTrrv:
    case VE::VSTNCOTrrvL:
    case VE::VSTNCOTrrvl:
    case VE::VSTNCOTrzv:
    case VE::VSTNCOTrzvL:
    case VE::VSTNCOTrzvl:
    case VE::VSTNCirv:
    case VE::VSTNCirvL:
    case VE::VSTNCirvl:
    case VE::VSTNCizv:
    case VE::VSTNCizvL:
    case VE::VSTNCizvl:
    case VE::VSTNCrrv:
    case VE::VSTNCrrvL:
    case VE::VSTNCrrvl:
    case VE::VSTNCrzv:
    case VE::VSTNCrzvL:
    case VE::VSTNCrzvl:
    case VE::VSTOTirv:
    case VE::VSTOTirvL:
    case VE::VSTOTirvl:
    case VE::VSTOTizv:
    case VE::VSTOTizvL:
    case VE::VSTOTizvl:
    case VE::VSTOTrrv:
    case VE::VSTOTrrvL:
    case VE::VSTOTrrvl:
    case VE::VSTOTrzv:
    case VE::VSTOTrzvL:
    case VE::VSTOTrzvl:
    case VE::VSTU2DNCOTirv:
    case VE::VSTU2DNCOTirvL:
    case VE::VSTU2DNCOTirvl:
    case VE::VSTU2DNCOTizv:
    case VE::VSTU2DNCOTizvL:
    case VE::VSTU2DNCOTizvl:
    case VE::VSTU2DNCOTrrv:
    case VE::VSTU2DNCOTrrvL:
    case VE::VSTU2DNCOTrrvl:
    case VE::VSTU2DNCOTrzv:
    case VE::VSTU2DNCOTrzvL:
    case VE::VSTU2DNCOTrzvl:
    case VE::VSTU2DNCirv:
    case VE::VSTU2DNCirvL:
    case VE::VSTU2DNCirvl:
    case VE::VSTU2DNCizv:
    case VE::VSTU2DNCizvL:
    case VE::VSTU2DNCizvl:
    case VE::VSTU2DNCrrv:
    case VE::VSTU2DNCrrvL:
    case VE::VSTU2DNCrrvl:
    case VE::VSTU2DNCrzv:
    case VE::VSTU2DNCrzvL:
    case VE::VSTU2DNCrzvl:
    case VE::VSTU2DOTirv:
    case VE::VSTU2DOTirvL:
    case VE::VSTU2DOTirvl:
    case VE::VSTU2DOTizv:
    case VE::VSTU2DOTizvL:
    case VE::VSTU2DOTizvl:
    case VE::VSTU2DOTrrv:
    case VE::VSTU2DOTrrvL:
    case VE::VSTU2DOTrrvl:
    case VE::VSTU2DOTrzv:
    case VE::VSTU2DOTrzvL:
    case VE::VSTU2DOTrzvl:
    case VE::VSTU2Dirv:
    case VE::VSTU2DirvL:
    case VE::VSTU2Dirvl:
    case VE::VSTU2Dizv:
    case VE::VSTU2DizvL:
    case VE::VSTU2Dizvl:
    case VE::VSTU2Drrv:
    case VE::VSTU2DrrvL:
    case VE::VSTU2Drrvl:
    case VE::VSTU2Drzv:
    case VE::VSTU2DrzvL:
    case VE::VSTU2Drzvl:
    case VE::VSTUNCOTirv:
    case VE::VSTUNCOTirvL:
    case VE::VSTUNCOTirvl:
    case VE::VSTUNCOTizv:
    case VE::VSTUNCOTizvL:
    case VE::VSTUNCOTizvl:
    case VE::VSTUNCOTrrv:
    case VE::VSTUNCOTrrvL:
    case VE::VSTUNCOTrrvl:
    case VE::VSTUNCOTrzv:
    case VE::VSTUNCOTrzvL:
    case VE::VSTUNCOTrzvl:
    case VE::VSTUNCirv:
    case VE::VSTUNCirvL:
    case VE::VSTUNCirvl:
    case VE::VSTUNCizv:
    case VE::VSTUNCizvL:
    case VE::VSTUNCizvl:
    case VE::VSTUNCrrv:
    case VE::VSTUNCrrvL:
    case VE::VSTUNCrrvl:
    case VE::VSTUNCrzv:
    case VE::VSTUNCrzvL:
    case VE::VSTUNCrzvl:
    case VE::VSTUOTirv:
    case VE::VSTUOTirvL:
    case VE::VSTUOTirvl:
    case VE::VSTUOTizv:
    case VE::VSTUOTizvL:
    case VE::VSTUOTizvl:
    case VE::VSTUOTrrv:
    case VE::VSTUOTrrvL:
    case VE::VSTUOTrrvl:
    case VE::VSTUOTrzv:
    case VE::VSTUOTrzvL:
    case VE::VSTUOTrzvl:
    case VE::VSTUirv:
    case VE::VSTUirvL:
    case VE::VSTUirvl:
    case VE::VSTUizv:
    case VE::VSTUizvL:
    case VE::VSTUizvl:
    case VE::VSTUrrv:
    case VE::VSTUrrvL:
    case VE::VSTUrrvl:
    case VE::VSTUrzv:
    case VE::VSTUrzvL:
    case VE::VSTUrzvl:
    case VE::VSTirv:
    case VE::VSTirvL:
    case VE::VSTirvl:
    case VE::VSTizv:
    case VE::VSTizvL:
    case VE::VSTizvl:
    case VE::VSTrrv:
    case VE::VSTrrvL:
    case VE::VSTrrvl:
    case VE::VSTrzv:
    case VE::VSTrzvL:
    case VE::VSTrzvl: {
      switch (OpNum) {
      case 0:
        // op: sy
        return 40;
      case 1:
        // op: sz
        return 32;
      case 2:
        // op: vx
        return 24;
      }
      break;
    }
    case VE::PFCHVNCir:
    case VE::PFCHVNCirL:
    case VE::PFCHVNCirl:
    case VE::PFCHVNCiz:
    case VE::PFCHVNCizL:
    case VE::PFCHVNCizl:
    case VE::PFCHVNCrr:
    case VE::PFCHVNCrrL:
    case VE::PFCHVNCrrl:
    case VE::PFCHVNCrz:
    case VE::PFCHVNCrzL:
    case VE::PFCHVNCrzl:
    case VE::PFCHVir:
    case VE::PFCHVirL:
    case VE::PFCHVirl:
    case VE::PFCHViz:
    case VE::PFCHVizL:
    case VE::PFCHVizl:
    case VE::PFCHVrr:
    case VE::PFCHVrrL:
    case VE::PFCHVrrl:
    case VE::PFCHVrz:
    case VE::PFCHVrzL:
    case VE::PFCHVrzl: {
      switch (OpNum) {
      case 0:
        // op: sy
        return 40;
      case 1:
        // op: sz
        return 32;
      }
      break;
    }
    case VE::LFRi:
    case VE::LFRr:
    case VE::LPM:
    case VE::LVIXi:
    case VE::LVIXr:
    case VE::LVLi:
    case VE::LVLr: {
      switch (OpNum) {
      case 0:
        // op: sy
        return 40;
      }
      break;
    }
    case VE::BCFDari:
    case VE::BCFDari_nt:
    case VE::BCFDari_t:
    case VE::BCFDazi:
    case VE::BCFDazi_nt:
    case VE::BCFDazi_t:
    case VE::BCFDnari:
    case VE::BCFDnari_nt:
    case VE::BCFDnari_t:
    case VE::BCFDnazi:
    case VE::BCFDnazi_nt:
    case VE::BCFDnazi_t:
    case VE::BCFLari:
    case VE::BCFLari_nt:
    case VE::BCFLari_t:
    case VE::BCFLazi:
    case VE::BCFLazi_nt:
    case VE::BCFLazi_t:
    case VE::BCFLnari:
    case VE::BCFLnari_nt:
    case VE::BCFLnari_t:
    case VE::BCFLnazi:
    case VE::BCFLnazi_nt:
    case VE::BCFLnazi_t:
    case VE::BCFSari:
    case VE::BCFSari_nt:
    case VE::BCFSari_t:
    case VE::BCFSazi:
    case VE::BCFSazi_nt:
    case VE::BCFSazi_t:
    case VE::BCFSnari:
    case VE::BCFSnari_nt:
    case VE::BCFSnari_t:
    case VE::BCFSnazi:
    case VE::BCFSnazi_nt:
    case VE::BCFSnazi_t:
    case VE::BCFWari:
    case VE::BCFWari_nt:
    case VE::BCFWari_t:
    case VE::BCFWazi:
    case VE::BCFWazi_nt:
    case VE::BCFWazi_t:
    case VE::BCFWnari:
    case VE::BCFWnari_nt:
    case VE::BCFWnari_t:
    case VE::BCFWnazi:
    case VE::BCFWnazi_nt:
    case VE::BCFWnazi_t: {
      switch (OpNum) {
      case 0:
        // op: sz
        return 32;
      case 1:
        // op: imm32
        return 0;
      }
      break;
    }
    case VE::PFCHrii:
    case VE::PFCHrri:
    case VE::PFCHzii:
    case VE::PFCHzri: {
      switch (OpNum) {
      case 0:
        // op: sz
        return 32;
      case 1:
        // op: sy
        return 40;
      case 2:
        // op: imm32
        return 0;
      }
      break;
    }
    case VE::CALLr: {
      switch (OpNum) {
      case 0:
        // op: sz
        return 32;
      }
      break;
    }
    case VE::PVFMADLOvvv:
    case VE::PVFMADLOvvvL:
    case VE::PVFMADLOvvvL_v:
    case VE::PVFMADLOvvv_v:
    case VE::PVFMADLOvvvl:
    case VE::PVFMADLOvvvl_v:
    case VE::PVFMADUPvvv:
    case VE::PVFMADUPvvvL:
    case VE::PVFMADUPvvvL_v:
    case VE::PVFMADUPvvv_v:
    case VE::PVFMADUPvvvl:
    case VE::PVFMADUPvvvl_v:
    case VE::PVFMADvvv:
    case VE::PVFMADvvvL:
    case VE::PVFMADvvvL_v:
    case VE::PVFMADvvv_v:
    case VE::PVFMADvvvl:
    case VE::PVFMADvvvl_v:
    case VE::PVFMSBLOvvv:
    case VE::PVFMSBLOvvvL:
    case VE::PVFMSBLOvvvL_v:
    case VE::PVFMSBLOvvv_v:
    case VE::PVFMSBLOvvvl:
    case VE::PVFMSBLOvvvl_v:
    case VE::PVFMSBUPvvv:
    case VE::PVFMSBUPvvvL:
    case VE::PVFMSBUPvvvL_v:
    case VE::PVFMSBUPvvv_v:
    case VE::PVFMSBUPvvvl:
    case VE::PVFMSBUPvvvl_v:
    case VE::PVFMSBvvv:
    case VE::PVFMSBvvvL:
    case VE::PVFMSBvvvL_v:
    case VE::PVFMSBvvv_v:
    case VE::PVFMSBvvvl:
    case VE::PVFMSBvvvl_v:
    case VE::PVFNMADLOvvv:
    case VE::PVFNMADLOvvvL:
    case VE::PVFNMADLOvvvL_v:
    case VE::PVFNMADLOvvv_v:
    case VE::PVFNMADLOvvvl:
    case VE::PVFNMADLOvvvl_v:
    case VE::PVFNMADUPvvv:
    case VE::PVFNMADUPvvvL:
    case VE::PVFNMADUPvvvL_v:
    case VE::PVFNMADUPvvv_v:
    case VE::PVFNMADUPvvvl:
    case VE::PVFNMADUPvvvl_v:
    case VE::PVFNMADvvv:
    case VE::PVFNMADvvvL:
    case VE::PVFNMADvvvL_v:
    case VE::PVFNMADvvv_v:
    case VE::PVFNMADvvvl:
    case VE::PVFNMADvvvl_v:
    case VE::PVFNMSBLOvvv:
    case VE::PVFNMSBLOvvvL:
    case VE::PVFNMSBLOvvvL_v:
    case VE::PVFNMSBLOvvv_v:
    case VE::PVFNMSBLOvvvl:
    case VE::PVFNMSBLOvvvl_v:
    case VE::PVFNMSBUPvvv:
    case VE::PVFNMSBUPvvvL:
    case VE::PVFNMSBUPvvvL_v:
    case VE::PVFNMSBUPvvv_v:
    case VE::PVFNMSBUPvvvl:
    case VE::PVFNMSBUPvvvl_v:
    case VE::PVFNMSBvvv:
    case VE::PVFNMSBvvvL:
    case VE::PVFNMSBvvvL_v:
    case VE::PVFNMSBvvv_v:
    case VE::PVFNMSBvvvl:
    case VE::PVFNMSBvvvl_v:
    case VE::VFMADDvvv:
    case VE::VFMADDvvvL:
    case VE::VFMADDvvvL_v:
    case VE::VFMADDvvv_v:
    case VE::VFMADDvvvl:
    case VE::VFMADDvvvl_v:
    case VE::VFMADSvvv:
    case VE::VFMADSvvvL:
    case VE::VFMADSvvvL_v:
    case VE::VFMADSvvv_v:
    case VE::VFMADSvvvl:
    case VE::VFMADSvvvl_v:
    case VE::VFMSBDvvv:
    case VE::VFMSBDvvvL:
    case VE::VFMSBDvvvL_v:
    case VE::VFMSBDvvv_v:
    case VE::VFMSBDvvvl:
    case VE::VFMSBDvvvl_v:
    case VE::VFMSBSvvv:
    case VE::VFMSBSvvvL:
    case VE::VFMSBSvvvL_v:
    case VE::VFMSBSvvv_v:
    case VE::VFMSBSvvvl:
    case VE::VFMSBSvvvl_v:
    case VE::VFNMADDvvv:
    case VE::VFNMADDvvvL:
    case VE::VFNMADDvvvL_v:
    case VE::VFNMADDvvv_v:
    case VE::VFNMADDvvvl:
    case VE::VFNMADDvvvl_v:
    case VE::VFNMADSvvv:
    case VE::VFNMADSvvvL:
    case VE::VFNMADSvvvL_v:
    case VE::VFNMADSvvv_v:
    case VE::VFNMADSvvvl:
    case VE::VFNMADSvvvl_v:
    case VE::VFNMSBDvvv:
    case VE::VFNMSBDvvvL:
    case VE::VFNMSBDvvvL_v:
    case VE::VFNMSBDvvv_v:
    case VE::VFNMSBDvvvl:
    case VE::VFNMSBDvvvl_v:
    case VE::VFNMSBSvvv:
    case VE::VFNMSBSvvvL:
    case VE::VFNMSBSvvvL_v:
    case VE::VFNMSBSvvv_v:
    case VE::VFNMSBSvvvl:
    case VE::VFNMSBSvvvl_v: {
      switch (OpNum) {
      case 0:
        // op: vx
        return 24;
      case 1:
        // op: vy
        return 16;
      case 2:
        // op: vz
        return 8;
      case 3:
        // op: vw
        return 0;
      }
      break;
    }
    case VE::ANDMmm:
    case VE::EQVMmm:
    case VE::NNDMmm:
    case VE::ORMmm:
    case VE::PVADDSLOvv:
    case VE::PVADDSLOvvL:
    case VE::PVADDSLOvvL_v:
    case VE::PVADDSLOvv_v:
    case VE::PVADDSLOvvl:
    case VE::PVADDSLOvvl_v:
    case VE::PVADDSUPvv:
    case VE::PVADDSUPvvL:
    case VE::PVADDSUPvvL_v:
    case VE::PVADDSUPvv_v:
    case VE::PVADDSUPvvl:
    case VE::PVADDSUPvvl_v:
    case VE::PVADDSvv:
    case VE::PVADDSvvL:
    case VE::PVADDSvvL_v:
    case VE::PVADDSvv_v:
    case VE::PVADDSvvl:
    case VE::PVADDSvvl_v:
    case VE::PVADDULOvv:
    case VE::PVADDULOvvL:
    case VE::PVADDULOvvL_v:
    case VE::PVADDULOvv_v:
    case VE::PVADDULOvvl:
    case VE::PVADDULOvvl_v:
    case VE::PVADDUUPvv:
    case VE::PVADDUUPvvL:
    case VE::PVADDUUPvvL_v:
    case VE::PVADDUUPvv_v:
    case VE::PVADDUUPvvl:
    case VE::PVADDUUPvvl_v:
    case VE::PVADDUvv:
    case VE::PVADDUvvL:
    case VE::PVADDUvvL_v:
    case VE::PVADDUvv_v:
    case VE::PVADDUvvl:
    case VE::PVADDUvvl_v:
    case VE::PVANDLOvv:
    case VE::PVANDLOvvL:
    case VE::PVANDLOvvL_v:
    case VE::PVANDLOvv_v:
    case VE::PVANDLOvvl:
    case VE::PVANDLOvvl_v:
    case VE::PVANDUPvv:
    case VE::PVANDUPvvL:
    case VE::PVANDUPvvL_v:
    case VE::PVANDUPvv_v:
    case VE::PVANDUPvvl:
    case VE::PVANDUPvvl_v:
    case VE::PVANDvv:
    case VE::PVANDvvL:
    case VE::PVANDvvL_v:
    case VE::PVANDvv_v:
    case VE::PVANDvvl:
    case VE::PVANDvvl_v:
    case VE::PVCMPSLOvv:
    case VE::PVCMPSLOvvL:
    case VE::PVCMPSLOvvL_v:
    case VE::PVCMPSLOvv_v:
    case VE::PVCMPSLOvvl:
    case VE::PVCMPSLOvvl_v:
    case VE::PVCMPSUPvv:
    case VE::PVCMPSUPvvL:
    case VE::PVCMPSUPvvL_v:
    case VE::PVCMPSUPvv_v:
    case VE::PVCMPSUPvvl:
    case VE::PVCMPSUPvvl_v:
    case VE::PVCMPSvv:
    case VE::PVCMPSvvL:
    case VE::PVCMPSvvL_v:
    case VE::PVCMPSvv_v:
    case VE::PVCMPSvvl:
    case VE::PVCMPSvvl_v:
    case VE::PVCMPULOvv:
    case VE::PVCMPULOvvL:
    case VE::PVCMPULOvvL_v:
    case VE::PVCMPULOvv_v:
    case VE::PVCMPULOvvl:
    case VE::PVCMPULOvvl_v:
    case VE::PVCMPUUPvv:
    case VE::PVCMPUUPvvL:
    case VE::PVCMPUUPvvL_v:
    case VE::PVCMPUUPvv_v:
    case VE::PVCMPUUPvvl:
    case VE::PVCMPUUPvvl_v:
    case VE::PVCMPUvv:
    case VE::PVCMPUvvL:
    case VE::PVCMPUvvL_v:
    case VE::PVCMPUvv_v:
    case VE::PVCMPUvvl:
    case VE::PVCMPUvvl_v:
    case VE::PVEQVLOvv:
    case VE::PVEQVLOvvL:
    case VE::PVEQVLOvvL_v:
    case VE::PVEQVLOvv_v:
    case VE::PVEQVLOvvl:
    case VE::PVEQVLOvvl_v:
    case VE::PVEQVUPvv:
    case VE::PVEQVUPvvL:
    case VE::PVEQVUPvvL_v:
    case VE::PVEQVUPvv_v:
    case VE::PVEQVUPvvl:
    case VE::PVEQVUPvvl_v:
    case VE::PVEQVvv:
    case VE::PVEQVvvL:
    case VE::PVEQVvvL_v:
    case VE::PVEQVvv_v:
    case VE::PVEQVvvl:
    case VE::PVEQVvvl_v:
    case VE::PVFADDLOvv:
    case VE::PVFADDLOvvL:
    case VE::PVFADDLOvvL_v:
    case VE::PVFADDLOvv_v:
    case VE::PVFADDLOvvl:
    case VE::PVFADDLOvvl_v:
    case VE::PVFADDUPvv:
    case VE::PVFADDUPvvL:
    case VE::PVFADDUPvvL_v:
    case VE::PVFADDUPvv_v:
    case VE::PVFADDUPvvl:
    case VE::PVFADDUPvvl_v:
    case VE::PVFADDvv:
    case VE::PVFADDvvL:
    case VE::PVFADDvvL_v:
    case VE::PVFADDvv_v:
    case VE::PVFADDvvl:
    case VE::PVFADDvvl_v:
    case VE::PVFCMPLOvv:
    case VE::PVFCMPLOvvL:
    case VE::PVFCMPLOvvL_v:
    case VE::PVFCMPLOvv_v:
    case VE::PVFCMPLOvvl:
    case VE::PVFCMPLOvvl_v:
    case VE::PVFCMPUPvv:
    case VE::PVFCMPUPvvL:
    case VE::PVFCMPUPvvL_v:
    case VE::PVFCMPUPvv_v:
    case VE::PVFCMPUPvvl:
    case VE::PVFCMPUPvvl_v:
    case VE::PVFCMPvv:
    case VE::PVFCMPvvL:
    case VE::PVFCMPvvL_v:
    case VE::PVFCMPvv_v:
    case VE::PVFCMPvvl:
    case VE::PVFCMPvvl_v:
    case VE::PVFMAXLOvv:
    case VE::PVFMAXLOvvL:
    case VE::PVFMAXLOvvL_v:
    case VE::PVFMAXLOvv_v:
    case VE::PVFMAXLOvvl:
    case VE::PVFMAXLOvvl_v:
    case VE::PVFMAXUPvv:
    case VE::PVFMAXUPvvL:
    case VE::PVFMAXUPvvL_v:
    case VE::PVFMAXUPvv_v:
    case VE::PVFMAXUPvvl:
    case VE::PVFMAXUPvvl_v:
    case VE::PVFMAXvv:
    case VE::PVFMAXvvL:
    case VE::PVFMAXvvL_v:
    case VE::PVFMAXvv_v:
    case VE::PVFMAXvvl:
    case VE::PVFMAXvvl_v:
    case VE::PVFMINLOvv:
    case VE::PVFMINLOvvL:
    case VE::PVFMINLOvvL_v:
    case VE::PVFMINLOvv_v:
    case VE::PVFMINLOvvl:
    case VE::PVFMINLOvvl_v:
    case VE::PVFMINUPvv:
    case VE::PVFMINUPvvL:
    case VE::PVFMINUPvvL_v:
    case VE::PVFMINUPvv_v:
    case VE::PVFMINUPvvl:
    case VE::PVFMINUPvvl_v:
    case VE::PVFMINvv:
    case VE::PVFMINvvL:
    case VE::PVFMINvvL_v:
    case VE::PVFMINvv_v:
    case VE::PVFMINvvl:
    case VE::PVFMINvvl_v:
    case VE::PVFMKSLOv:
    case VE::PVFMKSLOvL:
    case VE::PVFMKSLOvl:
    case VE::PVFMKSUPv:
    case VE::PVFMKSUPvL:
    case VE::PVFMKSUPvl:
    case VE::PVFMKWLOv:
    case VE::PVFMKWLOvL:
    case VE::PVFMKWLOvl:
    case VE::PVFMKWUPv:
    case VE::PVFMKWUPvL:
    case VE::PVFMKWUPvl:
    case VE::PVFMULLOvv:
    case VE::PVFMULLOvvL:
    case VE::PVFMULLOvvL_v:
    case VE::PVFMULLOvv_v:
    case VE::PVFMULLOvvl:
    case VE::PVFMULLOvvl_v:
    case VE::PVFMULUPvv:
    case VE::PVFMULUPvvL:
    case VE::PVFMULUPvvL_v:
    case VE::PVFMULUPvv_v:
    case VE::PVFMULUPvvl:
    case VE::PVFMULUPvvl_v:
    case VE::PVFMULvv:
    case VE::PVFMULvvL:
    case VE::PVFMULvvL_v:
    case VE::PVFMULvv_v:
    case VE::PVFMULvvl:
    case VE::PVFMULvvl_v:
    case VE::PVFSUBLOvv:
    case VE::PVFSUBLOvvL:
    case VE::PVFSUBLOvvL_v:
    case VE::PVFSUBLOvv_v:
    case VE::PVFSUBLOvvl:
    case VE::PVFSUBLOvvl_v:
    case VE::PVFSUBUPvv:
    case VE::PVFSUBUPvvL:
    case VE::PVFSUBUPvvL_v:
    case VE::PVFSUBUPvv_v:
    case VE::PVFSUBUPvvl:
    case VE::PVFSUBUPvvl_v:
    case VE::PVFSUBvv:
    case VE::PVFSUBvvL:
    case VE::PVFSUBvvL_v:
    case VE::PVFSUBvv_v:
    case VE::PVFSUBvvl:
    case VE::PVFSUBvvl_v:
    case VE::PVMAXSLOvv:
    case VE::PVMAXSLOvvL:
    case VE::PVMAXSLOvvL_v:
    case VE::PVMAXSLOvv_v:
    case VE::PVMAXSLOvvl:
    case VE::PVMAXSLOvvl_v:
    case VE::PVMAXSUPvv:
    case VE::PVMAXSUPvvL:
    case VE::PVMAXSUPvvL_v:
    case VE::PVMAXSUPvv_v:
    case VE::PVMAXSUPvvl:
    case VE::PVMAXSUPvvl_v:
    case VE::PVMAXSvv:
    case VE::PVMAXSvvL:
    case VE::PVMAXSvvL_v:
    case VE::PVMAXSvv_v:
    case VE::PVMAXSvvl:
    case VE::PVMAXSvvl_v:
    case VE::PVMINSLOvv:
    case VE::PVMINSLOvvL:
    case VE::PVMINSLOvvL_v:
    case VE::PVMINSLOvv_v:
    case VE::PVMINSLOvvl:
    case VE::PVMINSLOvvl_v:
    case VE::PVMINSUPvv:
    case VE::PVMINSUPvvL:
    case VE::PVMINSUPvvL_v:
    case VE::PVMINSUPvv_v:
    case VE::PVMINSUPvvl:
    case VE::PVMINSUPvvl_v:
    case VE::PVMINSvv:
    case VE::PVMINSvvL:
    case VE::PVMINSvvL_v:
    case VE::PVMINSvv_v:
    case VE::PVMINSvvl:
    case VE::PVMINSvvl_v:
    case VE::PVORLOvv:
    case VE::PVORLOvvL:
    case VE::PVORLOvvL_v:
    case VE::PVORLOvv_v:
    case VE::PVORLOvvl:
    case VE::PVORLOvvl_v:
    case VE::PVORUPvv:
    case VE::PVORUPvvL:
    case VE::PVORUPvvL_v:
    case VE::PVORUPvv_v:
    case VE::PVORUPvvl:
    case VE::PVORUPvvl_v:
    case VE::PVORvv:
    case VE::PVORvvL:
    case VE::PVORvvL_v:
    case VE::PVORvv_v:
    case VE::PVORvvl:
    case VE::PVORvvl_v:
    case VE::PVSUBSLOvv:
    case VE::PVSUBSLOvvL:
    case VE::PVSUBSLOvvL_v:
    case VE::PVSUBSLOvv_v:
    case VE::PVSUBSLOvvl:
    case VE::PVSUBSLOvvl_v:
    case VE::PVSUBSUPvv:
    case VE::PVSUBSUPvvL:
    case VE::PVSUBSUPvvL_v:
    case VE::PVSUBSUPvv_v:
    case VE::PVSUBSUPvvl:
    case VE::PVSUBSUPvvl_v:
    case VE::PVSUBSvv:
    case VE::PVSUBSvvL:
    case VE::PVSUBSvvL_v:
    case VE::PVSUBSvv_v:
    case VE::PVSUBSvvl:
    case VE::PVSUBSvvl_v:
    case VE::PVSUBULOvv:
    case VE::PVSUBULOvvL:
    case VE::PVSUBULOvvL_v:
    case VE::PVSUBULOvv_v:
    case VE::PVSUBULOvvl:
    case VE::PVSUBULOvvl_v:
    case VE::PVSUBUUPvv:
    case VE::PVSUBUUPvvL:
    case VE::PVSUBUUPvvL_v:
    case VE::PVSUBUUPvv_v:
    case VE::PVSUBUUPvvl:
    case VE::PVSUBUUPvvl_v:
    case VE::PVSUBUvv:
    case VE::PVSUBUvvL:
    case VE::PVSUBUvvL_v:
    case VE::PVSUBUvv_v:
    case VE::PVSUBUvvl:
    case VE::PVSUBUvvl_v:
    case VE::PVXORLOvv:
    case VE::PVXORLOvvL:
    case VE::PVXORLOvvL_v:
    case VE::PVXORLOvv_v:
    case VE::PVXORLOvvl:
    case VE::PVXORLOvvl_v:
    case VE::PVXORUPvv:
    case VE::PVXORUPvvL:
    case VE::PVXORUPvvL_v:
    case VE::PVXORUPvv_v:
    case VE::PVXORUPvvl:
    case VE::PVXORUPvvl_v:
    case VE::PVXORvv:
    case VE::PVXORvvL:
    case VE::PVXORvvL_v:
    case VE::PVXORvv_v:
    case VE::PVXORvvl:
    case VE::PVXORvvl_v:
    case VE::VADDSLvv:
    case VE::VADDSLvvL:
    case VE::VADDSLvvL_v:
    case VE::VADDSLvv_v:
    case VE::VADDSLvvl:
    case VE::VADDSLvvl_v:
    case VE::VADDSWSXvv:
    case VE::VADDSWSXvvL:
    case VE::VADDSWSXvvL_v:
    case VE::VADDSWSXvv_v:
    case VE::VADDSWSXvvl:
    case VE::VADDSWSXvvl_v:
    case VE::VADDSWZXvv:
    case VE::VADDSWZXvvL:
    case VE::VADDSWZXvvL_v:
    case VE::VADDSWZXvv_v:
    case VE::VADDSWZXvvl:
    case VE::VADDSWZXvvl_v:
    case VE::VADDULvv:
    case VE::VADDULvvL:
    case VE::VADDULvvL_v:
    case VE::VADDULvv_v:
    case VE::VADDULvvl:
    case VE::VADDULvvl_v:
    case VE::VADDUWvv:
    case VE::VADDUWvvL:
    case VE::VADDUWvvL_v:
    case VE::VADDUWvv_v:
    case VE::VADDUWvvl:
    case VE::VADDUWvvl_v:
    case VE::VANDvv:
    case VE::VANDvvL:
    case VE::VANDvvL_v:
    case VE::VANDvv_v:
    case VE::VANDvvl:
    case VE::VANDvvl_v:
    case VE::VCMPSLvv:
    case VE::VCMPSLvvL:
    case VE::VCMPSLvvL_v:
    case VE::VCMPSLvv_v:
    case VE::VCMPSLvvl:
    case VE::VCMPSLvvl_v:
    case VE::VCMPSWSXvv:
    case VE::VCMPSWSXvvL:
    case VE::VCMPSWSXvvL_v:
    case VE::VCMPSWSXvv_v:
    case VE::VCMPSWSXvvl:
    case VE::VCMPSWSXvvl_v:
    case VE::VCMPSWZXvv:
    case VE::VCMPSWZXvvL:
    case VE::VCMPSWZXvvL_v:
    case VE::VCMPSWZXvv_v:
    case VE::VCMPSWZXvvl:
    case VE::VCMPSWZXvvl_v:
    case VE::VCMPULvv:
    case VE::VCMPULvvL:
    case VE::VCMPULvvL_v:
    case VE::VCMPULvv_v:
    case VE::VCMPULvvl:
    case VE::VCMPULvvl_v:
    case VE::VCMPUWvv:
    case VE::VCMPUWvvL:
    case VE::VCMPUWvvL_v:
    case VE::VCMPUWvv_v:
    case VE::VCMPUWvvl:
    case VE::VCMPUWvvl_v:
    case VE::VDIVSLvv:
    case VE::VDIVSLvvL:
    case VE::VDIVSLvvL_v:
    case VE::VDIVSLvv_v:
    case VE::VDIVSLvvl:
    case VE::VDIVSLvvl_v:
    case VE::VDIVSWSXvv:
    case VE::VDIVSWSXvvL:
    case VE::VDIVSWSXvvL_v:
    case VE::VDIVSWSXvv_v:
    case VE::VDIVSWSXvvl:
    case VE::VDIVSWSXvvl_v:
    case VE::VDIVSWZXvv:
    case VE::VDIVSWZXvvL:
    case VE::VDIVSWZXvvL_v:
    case VE::VDIVSWZXvv_v:
    case VE::VDIVSWZXvvl:
    case VE::VDIVSWZXvvl_v:
    case VE::VDIVULvv:
    case VE::VDIVULvvL:
    case VE::VDIVULvvL_v:
    case VE::VDIVULvv_v:
    case VE::VDIVULvvl:
    case VE::VDIVULvvl_v:
    case VE::VDIVUWvv:
    case VE::VDIVUWvvL:
    case VE::VDIVUWvvL_v:
    case VE::VDIVUWvv_v:
    case VE::VDIVUWvvl:
    case VE::VDIVUWvvl_v:
    case VE::VEQVvv:
    case VE::VEQVvvL:
    case VE::VEQVvvL_v:
    case VE::VEQVvv_v:
    case VE::VEQVvvl:
    case VE::VEQVvvl_v:
    case VE::VFADDDvv:
    case VE::VFADDDvvL:
    case VE::VFADDDvvL_v:
    case VE::VFADDDvv_v:
    case VE::VFADDDvvl:
    case VE::VFADDDvvl_v:
    case VE::VFADDSvv:
    case VE::VFADDSvvL:
    case VE::VFADDSvvL_v:
    case VE::VFADDSvv_v:
    case VE::VFADDSvvl:
    case VE::VFADDSvvl_v:
    case VE::VFCMPDvv:
    case VE::VFCMPDvvL:
    case VE::VFCMPDvvL_v:
    case VE::VFCMPDvv_v:
    case VE::VFCMPDvvl:
    case VE::VFCMPDvvl_v:
    case VE::VFCMPSvv:
    case VE::VFCMPSvvL:
    case VE::VFCMPSvvL_v:
    case VE::VFCMPSvv_v:
    case VE::VFCMPSvvl:
    case VE::VFCMPSvvl_v:
    case VE::VFDIVDvv:
    case VE::VFDIVDvvL:
    case VE::VFDIVDvvL_v:
    case VE::VFDIVDvv_v:
    case VE::VFDIVDvvl:
    case VE::VFDIVDvvl_v:
    case VE::VFDIVSvv:
    case VE::VFDIVSvvL:
    case VE::VFDIVSvvL_v:
    case VE::VFDIVSvv_v:
    case VE::VFDIVSvvl:
    case VE::VFDIVSvvl_v:
    case VE::VFMAXDvv:
    case VE::VFMAXDvvL:
    case VE::VFMAXDvvL_v:
    case VE::VFMAXDvv_v:
    case VE::VFMAXDvvl:
    case VE::VFMAXDvvl_v:
    case VE::VFMAXSvv:
    case VE::VFMAXSvvL:
    case VE::VFMAXSvvL_v:
    case VE::VFMAXSvv_v:
    case VE::VFMAXSvvl:
    case VE::VFMAXSvvl_v:
    case VE::VFMINDvv:
    case VE::VFMINDvvL:
    case VE::VFMINDvvL_v:
    case VE::VFMINDvv_v:
    case VE::VFMINDvvl:
    case VE::VFMINDvvl_v:
    case VE::VFMINSvv:
    case VE::VFMINSvvL:
    case VE::VFMINSvvL_v:
    case VE::VFMINSvv_v:
    case VE::VFMINSvvl:
    case VE::VFMINSvvl_v:
    case VE::VFMKDv:
    case VE::VFMKDvL:
    case VE::VFMKDvl:
    case VE::VFMKLv:
    case VE::VFMKLvL:
    case VE::VFMKLvl:
    case VE::VFMKSv:
    case VE::VFMKSvL:
    case VE::VFMKSvl:
    case VE::VFMKWv:
    case VE::VFMKWvL:
    case VE::VFMKWvl:
    case VE::VFMULDvv:
    case VE::VFMULDvvL:
    case VE::VFMULDvvL_v:
    case VE::VFMULDvv_v:
    case VE::VFMULDvvl:
    case VE::VFMULDvvl_v:
    case VE::VFMULSvv:
    case VE::VFMULSvvL:
    case VE::VFMULSvvL_v:
    case VE::VFMULSvv_v:
    case VE::VFMULSvvl:
    case VE::VFMULSvvl_v:
    case VE::VFSUBDvv:
    case VE::VFSUBDvvL:
    case VE::VFSUBDvvL_v:
    case VE::VFSUBDvv_v:
    case VE::VFSUBDvvl:
    case VE::VFSUBDvvl_v:
    case VE::VFSUBSvv:
    case VE::VFSUBSvvL:
    case VE::VFSUBSvvL_v:
    case VE::VFSUBSvv_v:
    case VE::VFSUBSvvl:
    case VE::VFSUBSvvl_v:
    case VE::VMAXSLvv:
    case VE::VMAXSLvvL:
    case VE::VMAXSLvvL_v:
    case VE::VMAXSLvv_v:
    case VE::VMAXSLvvl:
    case VE::VMAXSLvvl_v:
    case VE::VMAXSWSXvv:
    case VE::VMAXSWSXvvL:
    case VE::VMAXSWSXvvL_v:
    case VE::VMAXSWSXvv_v:
    case VE::VMAXSWSXvvl:
    case VE::VMAXSWSXvvl_v:
    case VE::VMAXSWZXvv:
    case VE::VMAXSWZXvvL:
    case VE::VMAXSWZXvvL_v:
    case VE::VMAXSWZXvv_v:
    case VE::VMAXSWZXvvl:
    case VE::VMAXSWZXvvl_v:
    case VE::VMINSLvv:
    case VE::VMINSLvvL:
    case VE::VMINSLvvL_v:
    case VE::VMINSLvv_v:
    case VE::VMINSLvvl:
    case VE::VMINSLvvl_v:
    case VE::VMINSWSXvv:
    case VE::VMINSWSXvvL:
    case VE::VMINSWSXvvL_v:
    case VE::VMINSWSXvv_v:
    case VE::VMINSWSXvvl:
    case VE::VMINSWSXvvl_v:
    case VE::VMINSWZXvv:
    case VE::VMINSWZXvvL:
    case VE::VMINSWZXvvL_v:
    case VE::VMINSWZXvv_v:
    case VE::VMINSWZXvvl:
    case VE::VMINSWZXvvl_v:
    case VE::VMRGWvv:
    case VE::VMRGWvvL:
    case VE::VMRGWvvL_v:
    case VE::VMRGWvv_v:
    case VE::VMRGWvvl:
    case VE::VMRGWvvl_v:
    case VE::VMRGvv:
    case VE::VMRGvvL:
    case VE::VMRGvvL_v:
    case VE::VMRGvv_v:
    case VE::VMRGvvl:
    case VE::VMRGvvl_v:
    case VE::VMULSLWvv:
    case VE::VMULSLWvvL:
    case VE::VMULSLWvvL_v:
    case VE::VMULSLWvv_v:
    case VE::VMULSLWvvl:
    case VE::VMULSLWvvl_v:
    case VE::VMULSLvv:
    case VE::VMULSLvvL:
    case VE::VMULSLvvL_v:
    case VE::VMULSLvv_v:
    case VE::VMULSLvvl:
    case VE::VMULSLvvl_v:
    case VE::VMULSWSXvv:
    case VE::VMULSWSXvvL:
    case VE::VMULSWSXvvL_v:
    case VE::VMULSWSXvv_v:
    case VE::VMULSWSXvvl:
    case VE::VMULSWSXvvl_v:
    case VE::VMULSWZXvv:
    case VE::VMULSWZXvvL:
    case VE::VMULSWZXvvL_v:
    case VE::VMULSWZXvv_v:
    case VE::VMULSWZXvvl:
    case VE::VMULSWZXvvl_v:
    case VE::VMULULvv:
    case VE::VMULULvvL:
    case VE::VMULULvvL_v:
    case VE::VMULULvv_v:
    case VE::VMULULvvl:
    case VE::VMULULvvl_v:
    case VE::VMULUWvv:
    case VE::VMULUWvvL:
    case VE::VMULUWvvL_v:
    case VE::VMULUWvv_v:
    case VE::VMULUWvvl:
    case VE::VMULUWvvl_v:
    case VE::VORvv:
    case VE::VORvvL:
    case VE::VORvvL_v:
    case VE::VORvv_v:
    case VE::VORvvl:
    case VE::VORvvl_v:
    case VE::VSUBSLvv:
    case VE::VSUBSLvvL:
    case VE::VSUBSLvvL_v:
    case VE::VSUBSLvv_v:
    case VE::VSUBSLvvl:
    case VE::VSUBSLvvl_v:
    case VE::VSUBSWSXvv:
    case VE::VSUBSWSXvvL:
    case VE::VSUBSWSXvvL_v:
    case VE::VSUBSWSXvv_v:
    case VE::VSUBSWSXvvl:
    case VE::VSUBSWSXvvl_v:
    case VE::VSUBSWZXvv:
    case VE::VSUBSWZXvvL:
    case VE::VSUBSWZXvvL_v:
    case VE::VSUBSWZXvv_v:
    case VE::VSUBSWZXvvl:
    case VE::VSUBSWZXvvl_v:
    case VE::VSUBULvv:
    case VE::VSUBULvvL:
    case VE::VSUBULvvL_v:
    case VE::VSUBULvv_v:
    case VE::VSUBULvvl:
    case VE::VSUBULvvl_v:
    case VE::VSUBUWvv:
    case VE::VSUBUWvvL:
    case VE::VSUBUWvvL_v:
    case VE::VSUBUWvv_v:
    case VE::VSUBUWvvl:
    case VE::VSUBUWvvl_v:
    case VE::VXORvv:
    case VE::VXORvvL:
    case VE::VXORvvL_v:
    case VE::VXORvv_v:
    case VE::VXORvvl:
    case VE::VXORvvl_v:
    case VE::XORMmm: {
      switch (OpNum) {
      case 0:
        // op: vx
        return 24;
      case 1:
        // op: vy
        return 16;
      case 2:
        // op: vz
        return 8;
      }
      break;
    }
    case VE::NEGMm:
    case VE::PVCVTSWLOv:
    case VE::PVCVTSWLOvL:
    case VE::PVCVTSWLOvL_v:
    case VE::PVCVTSWLOv_v:
    case VE::PVCVTSWLOvl:
    case VE::PVCVTSWLOvl_v:
    case VE::PVCVTSWUPv:
    case VE::PVCVTSWUPvL:
    case VE::PVCVTSWUPvL_v:
    case VE::PVCVTSWUPv_v:
    case VE::PVCVTSWUPvl:
    case VE::PVCVTSWUPvl_v:
    case VE::PVCVTSWv:
    case VE::PVCVTSWvL:
    case VE::PVCVTSWvL_v:
    case VE::PVCVTSWv_v:
    case VE::PVCVTSWvl:
    case VE::PVCVTSWvl_v:
    case VE::PVRCPLOv:
    case VE::PVRCPLOvL:
    case VE::PVRCPLOvL_v:
    case VE::PVRCPLOv_v:
    case VE::PVRCPLOvl:
    case VE::PVRCPLOvl_v:
    case VE::PVRCPUPv:
    case VE::PVRCPUPvL:
    case VE::PVRCPUPvL_v:
    case VE::PVRCPUPv_v:
    case VE::PVRCPUPvl:
    case VE::PVRCPUPvl_v:
    case VE::PVRCPv:
    case VE::PVRCPvL:
    case VE::PVRCPvL_v:
    case VE::PVRCPv_v:
    case VE::PVRCPvl:
    case VE::PVRCPvl_v:
    case VE::PVRSQRTLONEXv:
    case VE::PVRSQRTLONEXvL:
    case VE::PVRSQRTLONEXvL_v:
    case VE::PVRSQRTLONEXv_v:
    case VE::PVRSQRTLONEXvl:
    case VE::PVRSQRTLONEXvl_v:
    case VE::PVRSQRTLOv:
    case VE::PVRSQRTLOvL:
    case VE::PVRSQRTLOvL_v:
    case VE::PVRSQRTLOv_v:
    case VE::PVRSQRTLOvl:
    case VE::PVRSQRTLOvl_v:
    case VE::PVRSQRTNEXv:
    case VE::PVRSQRTNEXvL:
    case VE::PVRSQRTNEXvL_v:
    case VE::PVRSQRTNEXv_v:
    case VE::PVRSQRTNEXvl:
    case VE::PVRSQRTNEXvl_v:
    case VE::PVRSQRTUPNEXv:
    case VE::PVRSQRTUPNEXvL:
    case VE::PVRSQRTUPNEXvL_v:
    case VE::PVRSQRTUPNEXv_v:
    case VE::PVRSQRTUPNEXvl:
    case VE::PVRSQRTUPNEXvl_v:
    case VE::PVRSQRTUPv:
    case VE::PVRSQRTUPvL:
    case VE::PVRSQRTUPvL_v:
    case VE::PVRSQRTUPv_v:
    case VE::PVRSQRTUPvl:
    case VE::PVRSQRTUPvl_v:
    case VE::PVRSQRTv:
    case VE::PVRSQRTvL:
    case VE::PVRSQRTvL_v:
    case VE::PVRSQRTv_v:
    case VE::PVRSQRTvl:
    case VE::PVRSQRTvl_v:
    case VE::VCVTDLv:
    case VE::VCVTDLvL:
    case VE::VCVTDLvL_v:
    case VE::VCVTDLv_v:
    case VE::VCVTDLvl:
    case VE::VCVTDLvl_v:
    case VE::VCVTDSv:
    case VE::VCVTDSvL:
    case VE::VCVTDSvL_v:
    case VE::VCVTDSv_v:
    case VE::VCVTDSvl:
    case VE::VCVTDSvl_v:
    case VE::VCVTDWv:
    case VE::VCVTDWvL:
    case VE::VCVTDWvL_v:
    case VE::VCVTDWv_v:
    case VE::VCVTDWvl:
    case VE::VCVTDWvl_v:
    case VE::VCVTSDv:
    case VE::VCVTSDvL:
    case VE::VCVTSDvL_v:
    case VE::VCVTSDv_v:
    case VE::VCVTSDvl:
    case VE::VCVTSDvl_v:
    case VE::VCVTSWv:
    case VE::VCVTSWvL:
    case VE::VCVTSWvL_v:
    case VE::VCVTSWv_v:
    case VE::VCVTSWvl:
    case VE::VCVTSWvl_v:
    case VE::VFRMAXDFSTv:
    case VE::VFRMAXDFSTvL:
    case VE::VFRMAXDFSTvL_v:
    case VE::VFRMAXDFSTv_v:
    case VE::VFRMAXDFSTvl:
    case VE::VFRMAXDFSTvl_v:
    case VE::VFRMAXDLSTv:
    case VE::VFRMAXDLSTvL:
    case VE::VFRMAXDLSTvL_v:
    case VE::VFRMAXDLSTv_v:
    case VE::VFRMAXDLSTvl:
    case VE::VFRMAXDLSTvl_v:
    case VE::VFRMAXSFSTv:
    case VE::VFRMAXSFSTvL:
    case VE::VFRMAXSFSTvL_v:
    case VE::VFRMAXSFSTv_v:
    case VE::VFRMAXSFSTvl:
    case VE::VFRMAXSFSTvl_v:
    case VE::VFRMAXSLSTv:
    case VE::VFRMAXSLSTvL:
    case VE::VFRMAXSLSTvL_v:
    case VE::VFRMAXSLSTv_v:
    case VE::VFRMAXSLSTvl:
    case VE::VFRMAXSLSTvl_v:
    case VE::VFRMINDFSTv:
    case VE::VFRMINDFSTvL:
    case VE::VFRMINDFSTvL_v:
    case VE::VFRMINDFSTv_v:
    case VE::VFRMINDFSTvl:
    case VE::VFRMINDFSTvl_v:
    case VE::VFRMINDLSTv:
    case VE::VFRMINDLSTvL:
    case VE::VFRMINDLSTvL_v:
    case VE::VFRMINDLSTv_v:
    case VE::VFRMINDLSTvl:
    case VE::VFRMINDLSTvl_v:
    case VE::VFRMINSFSTv:
    case VE::VFRMINSFSTvL:
    case VE::VFRMINSFSTvL_v:
    case VE::VFRMINSFSTv_v:
    case VE::VFRMINSFSTvl:
    case VE::VFRMINSFSTvl_v:
    case VE::VFRMINSLSTv:
    case VE::VFRMINSLSTvL:
    case VE::VFRMINSLSTvL_v:
    case VE::VFRMINSLSTv_v:
    case VE::VFRMINSLSTvl:
    case VE::VFRMINSLSTvl_v:
    case VE::VFSQRTDv:
    case VE::VFSQRTDvL:
    case VE::VFSQRTDvL_v:
    case VE::VFSQRTDv_v:
    case VE::VFSQRTDvl:
    case VE::VFSQRTDvl_v:
    case VE::VFSQRTSv:
    case VE::VFSQRTSvL:
    case VE::VFSQRTSvL_v:
    case VE::VFSQRTSv_v:
    case VE::VFSQRTSvl:
    case VE::VFSQRTSvl_v:
    case VE::VFSUMDv:
    case VE::VFSUMDvL:
    case VE::VFSUMDvL_v:
    case VE::VFSUMDv_v:
    case VE::VFSUMDvl:
    case VE::VFSUMDvl_v:
    case VE::VFSUMSv:
    case VE::VFSUMSvL:
    case VE::VFSUMSvL_v:
    case VE::VFSUMSv_v:
    case VE::VFSUMSvl:
    case VE::VFSUMSvl_v:
    case VE::VRANDv:
    case VE::VRANDvL:
    case VE::VRANDvL_v:
    case VE::VRANDv_v:
    case VE::VRANDvl:
    case VE::VRANDvl_v:
    case VE::VRCPDv:
    case VE::VRCPDvL:
    case VE::VRCPDvL_v:
    case VE::VRCPDv_v:
    case VE::VRCPDvl:
    case VE::VRCPDvl_v:
    case VE::VRCPSv:
    case VE::VRCPSvL:
    case VE::VRCPSvL_v:
    case VE::VRCPSv_v:
    case VE::VRCPSvl:
    case VE::VRCPSvl_v:
    case VE::VRMAXSLFSTv:
    case VE::VRMAXSLFSTvL:
    case VE::VRMAXSLFSTvL_v:
    case VE::VRMAXSLFSTv_v:
    case VE::VRMAXSLFSTvl:
    case VE::VRMAXSLFSTvl_v:
    case VE::VRMAXSLLSTv:
    case VE::VRMAXSLLSTvL:
    case VE::VRMAXSLLSTvL_v:
    case VE::VRMAXSLLSTv_v:
    case VE::VRMAXSLLSTvl:
    case VE::VRMAXSLLSTvl_v:
    case VE::VRMAXSWFSTSXv:
    case VE::VRMAXSWFSTSXvL:
    case VE::VRMAXSWFSTSXvL_v:
    case VE::VRMAXSWFSTSXv_v:
    case VE::VRMAXSWFSTSXvl:
    case VE::VRMAXSWFSTSXvl_v:
    case VE::VRMAXSWFSTZXv:
    case VE::VRMAXSWFSTZXvL:
    case VE::VRMAXSWFSTZXvL_v:
    case VE::VRMAXSWFSTZXv_v:
    case VE::VRMAXSWFSTZXvl:
    case VE::VRMAXSWFSTZXvl_v:
    case VE::VRMAXSWLSTSXv:
    case VE::VRMAXSWLSTSXvL:
    case VE::VRMAXSWLSTSXvL_v:
    case VE::VRMAXSWLSTSXv_v:
    case VE::VRMAXSWLSTSXvl:
    case VE::VRMAXSWLSTSXvl_v:
    case VE::VRMAXSWLSTZXv:
    case VE::VRMAXSWLSTZXvL:
    case VE::VRMAXSWLSTZXvL_v:
    case VE::VRMAXSWLSTZXv_v:
    case VE::VRMAXSWLSTZXvl:
    case VE::VRMAXSWLSTZXvl_v:
    case VE::VRMINSLFSTv:
    case VE::VRMINSLFSTvL:
    case VE::VRMINSLFSTvL_v:
    case VE::VRMINSLFSTv_v:
    case VE::VRMINSLFSTvl:
    case VE::VRMINSLFSTvl_v:
    case VE::VRMINSLLSTv:
    case VE::VRMINSLLSTvL:
    case VE::VRMINSLLSTvL_v:
    case VE::VRMINSLLSTv_v:
    case VE::VRMINSLLSTvl:
    case VE::VRMINSLLSTvl_v:
    case VE::VRMINSWFSTSXv:
    case VE::VRMINSWFSTSXvL:
    case VE::VRMINSWFSTSXvL_v:
    case VE::VRMINSWFSTSXv_v:
    case VE::VRMINSWFSTSXvl:
    case VE::VRMINSWFSTSXvl_v:
    case VE::VRMINSWFSTZXv:
    case VE::VRMINSWFSTZXvL:
    case VE::VRMINSWFSTZXvL_v:
    case VE::VRMINSWFSTZXv_v:
    case VE::VRMINSWFSTZXvl:
    case VE::VRMINSWFSTZXvl_v:
    case VE::VRMINSWLSTSXv:
    case VE::VRMINSWLSTSXvL:
    case VE::VRMINSWLSTSXvL_v:
    case VE::VRMINSWLSTSXv_v:
    case VE::VRMINSWLSTSXvl:
    case VE::VRMINSWLSTSXvl_v:
    case VE::VRMINSWLSTZXv:
    case VE::VRMINSWLSTZXvL:
    case VE::VRMINSWLSTZXvL_v:
    case VE::VRMINSWLSTZXv_v:
    case VE::VRMINSWLSTZXvl:
    case VE::VRMINSWLSTZXvl_v:
    case VE::VRORv:
    case VE::VRORvL:
    case VE::VRORvL_v:
    case VE::VRORv_v:
    case VE::VRORvl:
    case VE::VRORvl_v:
    case VE::VRSQRTDNEXv:
    case VE::VRSQRTDNEXvL:
    case VE::VRSQRTDNEXvL_v:
    case VE::VRSQRTDNEXv_v:
    case VE::VRSQRTDNEXvl:
    case VE::VRSQRTDNEXvl_v:
    case VE::VRSQRTDv:
    case VE::VRSQRTDvL:
    case VE::VRSQRTDvL_v:
    case VE::VRSQRTDv_v:
    case VE::VRSQRTDvl:
    case VE::VRSQRTDvl_v:
    case VE::VRSQRTSNEXv:
    case VE::VRSQRTSNEXvL:
    case VE::VRSQRTSNEXvL_v:
    case VE::VRSQRTSNEXv_v:
    case VE::VRSQRTSNEXvl:
    case VE::VRSQRTSNEXvl_v:
    case VE::VRSQRTSv:
    case VE::VRSQRTSvL:
    case VE::VRSQRTSvL_v:
    case VE::VRSQRTSv_v:
    case VE::VRSQRTSvl:
    case VE::VRSQRTSvl_v:
    case VE::VRXORv:
    case VE::VRXORvL:
    case VE::VRXORvL_v:
    case VE::VRXORv_v:
    case VE::VRXORvl:
    case VE::VRXORvl_v:
    case VE::VSUMLv:
    case VE::VSUMLvL:
    case VE::VSUMLvL_v:
    case VE::VSUMLv_v:
    case VE::VSUMLvl:
    case VE::VSUMLvl_v:
    case VE::VSUMWSXv:
    case VE::VSUMWSXvL:
    case VE::VSUMWSXvL_v:
    case VE::VSUMWSXv_v:
    case VE::VSUMWSXvl:
    case VE::VSUMWSXvl_v:
    case VE::VSUMWZXv:
    case VE::VSUMWZXvL:
    case VE::VSUMWZXvL_v:
    case VE::VSUMWZXv_v:
    case VE::VSUMWZXvl:
    case VE::VSUMWZXvl_v: {
      switch (OpNum) {
      case 0:
        // op: vx
        return 24;
      case 1:
        // op: vy
        return 16;
      }
      break;
    }
    case VE::PVBRVLOv:
    case VE::PVBRVLOvL:
    case VE::PVBRVLOvL_v:
    case VE::PVBRVLOv_v:
    case VE::PVBRVLOvl:
    case VE::PVBRVLOvl_v:
    case VE::PVBRVUPv:
    case VE::PVBRVUPvL:
    case VE::PVBRVUPvL_v:
    case VE::PVBRVUPv_v:
    case VE::PVBRVUPvl:
    case VE::PVBRVUPvl_v:
    case VE::PVBRVv:
    case VE::PVBRVvL:
    case VE::PVBRVvL_v:
    case VE::PVBRVv_v:
    case VE::PVBRVvl:
    case VE::PVBRVvl_v:
    case VE::PVLDZLOv:
    case VE::PVLDZLOvL:
    case VE::PVLDZLOvL_v:
    case VE::PVLDZLOv_v:
    case VE::PVLDZLOvl:
    case VE::PVLDZLOvl_v:
    case VE::PVLDZUPv:
    case VE::PVLDZUPvL:
    case VE::PVLDZUPvL_v:
    case VE::PVLDZUPv_v:
    case VE::PVLDZUPvl:
    case VE::PVLDZUPvl_v:
    case VE::PVLDZv:
    case VE::PVLDZvL:
    case VE::PVLDZvL_v:
    case VE::PVLDZv_v:
    case VE::PVLDZvl:
    case VE::PVLDZvl_v:
    case VE::PVPCNTLOv:
    case VE::PVPCNTLOvL:
    case VE::PVPCNTLOvL_v:
    case VE::PVPCNTLOv_v:
    case VE::PVPCNTLOvl:
    case VE::PVPCNTLOvl_v:
    case VE::PVPCNTUPv:
    case VE::PVPCNTUPvL:
    case VE::PVPCNTUPvL_v:
    case VE::PVPCNTUPv_v:
    case VE::PVPCNTUPvl:
    case VE::PVPCNTUPvl_v:
    case VE::PVPCNTv:
    case VE::PVPCNTvL:
    case VE::PVPCNTvL_v:
    case VE::PVPCNTv_v:
    case VE::PVPCNTvl:
    case VE::PVPCNTvl_v:
    case VE::VBRVv:
    case VE::VBRVvL:
    case VE::VBRVvL_v:
    case VE::VBRVv_v:
    case VE::VBRVvl:
    case VE::VBRVvl_v:
    case VE::VCPv:
    case VE::VCPvL:
    case VE::VCPvL_v:
    case VE::VCPv_v:
    case VE::VCPvl:
    case VE::VCPvl_v:
    case VE::VEXv:
    case VE::VEXvL:
    case VE::VEXvL_v:
    case VE::VEXv_v:
    case VE::VEXvl:
    case VE::VEXvl_v:
    case VE::VLDZv:
    case VE::VLDZvL:
    case VE::VLDZvL_v:
    case VE::VLDZv_v:
    case VE::VLDZvl:
    case VE::VLDZvl_v:
    case VE::VPCNTv:
    case VE::VPCNTvL:
    case VE::VPCNTvL_v:
    case VE::VPCNTv_v:
    case VE::VPCNTvl:
    case VE::VPCNTvl_v: {
      switch (OpNum) {
      case 0:
        // op: vx
        return 24;
      case 1:
        // op: vz
        return 8;
      }
      break;
    }
    case VE::PVCVTWSLOv:
    case VE::PVCVTWSLOvL:
    case VE::PVCVTWSLOvL_v:
    case VE::PVCVTWSLOv_v:
    case VE::PVCVTWSLOvl:
    case VE::PVCVTWSLOvl_v:
    case VE::PVCVTWSUPv:
    case VE::PVCVTWSUPvL:
    case VE::PVCVTWSUPvL_v:
    case VE::PVCVTWSUPv_v:
    case VE::PVCVTWSUPvl:
    case VE::PVCVTWSUPvl_v:
    case VE::PVCVTWSv:
    case VE::PVCVTWSvL:
    case VE::PVCVTWSvL_v:
    case VE::PVCVTWSv_v:
    case VE::PVCVTWSvl:
    case VE::PVCVTWSvl_v:
    case VE::PVSLALOvv:
    case VE::PVSLALOvvL:
    case VE::PVSLALOvvL_v:
    case VE::PVSLALOvv_v:
    case VE::PVSLALOvvl:
    case VE::PVSLALOvvl_v:
    case VE::PVSLAUPvv:
    case VE::PVSLAUPvvL:
    case VE::PVSLAUPvvL_v:
    case VE::PVSLAUPvv_v:
    case VE::PVSLAUPvvl:
    case VE::PVSLAUPvvl_v:
    case VE::PVSLAvv:
    case VE::PVSLAvvL:
    case VE::PVSLAvvL_v:
    case VE::PVSLAvv_v:
    case VE::PVSLAvvl:
    case VE::PVSLAvvl_v:
    case VE::PVSLLLOvv:
    case VE::PVSLLLOvvL:
    case VE::PVSLLLOvvL_v:
    case VE::PVSLLLOvv_v:
    case VE::PVSLLLOvvl:
    case VE::PVSLLLOvvl_v:
    case VE::PVSLLUPvv:
    case VE::PVSLLUPvvL:
    case VE::PVSLLUPvvL_v:
    case VE::PVSLLUPvv_v:
    case VE::PVSLLUPvvl:
    case VE::PVSLLUPvvl_v:
    case VE::PVSLLvv:
    case VE::PVSLLvvL:
    case VE::PVSLLvvL_v:
    case VE::PVSLLvv_v:
    case VE::PVSLLvvl:
    case VE::PVSLLvvl_v:
    case VE::PVSRALOvv:
    case VE::PVSRALOvvL:
    case VE::PVSRALOvvL_v:
    case VE::PVSRALOvv_v:
    case VE::PVSRALOvvl:
    case VE::PVSRALOvvl_v:
    case VE::PVSRAUPvv:
    case VE::PVSRAUPvvL:
    case VE::PVSRAUPvvL_v:
    case VE::PVSRAUPvv_v:
    case VE::PVSRAUPvvl:
    case VE::PVSRAUPvvl_v:
    case VE::PVSRAvv:
    case VE::PVSRAvvL:
    case VE::PVSRAvvL_v:
    case VE::PVSRAvv_v:
    case VE::PVSRAvvl:
    case VE::PVSRAvvl_v:
    case VE::PVSRLLOvv:
    case VE::PVSRLLOvvL:
    case VE::PVSRLLOvvL_v:
    case VE::PVSRLLOvv_v:
    case VE::PVSRLLOvvl:
    case VE::PVSRLLOvvl_v:
    case VE::PVSRLUPvv:
    case VE::PVSRLUPvvL:
    case VE::PVSRLUPvvL_v:
    case VE::PVSRLUPvv_v:
    case VE::PVSRLUPvvl:
    case VE::PVSRLUPvvl_v:
    case VE::PVSRLvv:
    case VE::PVSRLvvL:
    case VE::PVSRLvvL_v:
    case VE::PVSRLvv_v:
    case VE::PVSRLvvl:
    case VE::PVSRLvvl_v:
    case VE::VCVTLDv:
    case VE::VCVTLDvL:
    case VE::VCVTLDvL_v:
    case VE::VCVTLDv_v:
    case VE::VCVTLDvl:
    case VE::VCVTLDvl_v:
    case VE::VCVTWDSXv:
    case VE::VCVTWDSXvL:
    case VE::VCVTWDSXvL_v:
    case VE::VCVTWDSXv_v:
    case VE::VCVTWDSXvl:
    case VE::VCVTWDSXvl_v:
    case VE::VCVTWDZXv:
    case VE::VCVTWDZXvL:
    case VE::VCVTWDZXvL_v:
    case VE::VCVTWDZXv_v:
    case VE::VCVTWDZXvl:
    case VE::VCVTWDZXvl_v:
    case VE::VCVTWSSXv:
    case VE::VCVTWSSXvL:
    case VE::VCVTWSSXvL_v:
    case VE::VCVTWSSXv_v:
    case VE::VCVTWSSXvl:
    case VE::VCVTWSSXvl_v:
    case VE::VCVTWSZXv:
    case VE::VCVTWSZXvL:
    case VE::VCVTWSZXvL_v:
    case VE::VCVTWSZXv_v:
    case VE::VCVTWSZXvl:
    case VE::VCVTWSZXvl_v:
    case VE::VSLALvv:
    case VE::VSLALvvL:
    case VE::VSLALvvL_v:
    case VE::VSLALvv_v:
    case VE::VSLALvvl:
    case VE::VSLALvvl_v:
    case VE::VSLAWSXvv:
    case VE::VSLAWSXvvL:
    case VE::VSLAWSXvvL_v:
    case VE::VSLAWSXvv_v:
    case VE::VSLAWSXvvl:
    case VE::VSLAWSXvvl_v:
    case VE::VSLAWZXvv:
    case VE::VSLAWZXvvL:
    case VE::VSLAWZXvvL_v:
    case VE::VSLAWZXvv_v:
    case VE::VSLAWZXvvl:
    case VE::VSLAWZXvvl_v:
    case VE::VSLLvv:
    case VE::VSLLvvL:
    case VE::VSLLvvL_v:
    case VE::VSLLvv_v:
    case VE::VSLLvvl:
    case VE::VSLLvvl_v:
    case VE::VSRALvv:
    case VE::VSRALvvL:
    case VE::VSRALvvL_v:
    case VE::VSRALvv_v:
    case VE::VSRALvvl:
    case VE::VSRALvvl_v:
    case VE::VSRAWSXvv:
    case VE::VSRAWSXvvL:
    case VE::VSRAWSXvvL_v:
    case VE::VSRAWSXvv_v:
    case VE::VSRAWSXvvl:
    case VE::VSRAWSXvvl_v:
    case VE::VSRAWZXvv:
    case VE::VSRAWZXvvL:
    case VE::VSRAWZXvvL_v:
    case VE::VSRAWZXvv_v:
    case VE::VSRAWZXvvl:
    case VE::VSRAWZXvvl_v:
    case VE::VSRLvv:
    case VE::VSRLvvL:
    case VE::VSRLvvL_v:
    case VE::VSRLvv_v:
    case VE::VSRLvvl:
    case VE::VSRLvvl_v: {
      switch (OpNum) {
      case 0:
        // op: vx
        return 24;
      case 2:
        // op: vy
        return 16;
      case 1:
        // op: vz
        return 8;
      }
      break;
    }
    case VE::PVFMKSLOa:
    case VE::PVFMKSLOaL:
    case VE::PVFMKSLOal:
    case VE::PVFMKSLOna:
    case VE::PVFMKSLOnaL:
    case VE::PVFMKSLOnal:
    case VE::PVFMKSUPa:
    case VE::PVFMKSUPaL:
    case VE::PVFMKSUPal:
    case VE::PVFMKSUPna:
    case VE::PVFMKSUPnaL:
    case VE::PVFMKSUPnal:
    case VE::PVFMKWLOa:
    case VE::PVFMKWLOaL:
    case VE::PVFMKWLOal:
    case VE::PVFMKWLOna:
    case VE::PVFMKWLOnaL:
    case VE::PVFMKWLOnal:
    case VE::PVFMKWUPa:
    case VE::PVFMKWUPaL:
    case VE::PVFMKWUPal:
    case VE::PVFMKWUPna:
    case VE::PVFMKWUPnaL:
    case VE::PVFMKWUPnal:
    case VE::PVSEQ:
    case VE::PVSEQL:
    case VE::PVSEQLO:
    case VE::PVSEQLOL:
    case VE::PVSEQLOL_v:
    case VE::PVSEQLO_v:
    case VE::PVSEQLOl:
    case VE::PVSEQLOl_v:
    case VE::PVSEQL_v:
    case VE::PVSEQUP:
    case VE::PVSEQUPL:
    case VE::PVSEQUPL_v:
    case VE::PVSEQUP_v:
    case VE::PVSEQUPl:
    case VE::PVSEQUPl_v:
    case VE::PVSEQ_v:
    case VE::PVSEQl:
    case VE::PVSEQl_v:
    case VE::VFMKDa:
    case VE::VFMKDaL:
    case VE::VFMKDal:
    case VE::VFMKDna:
    case VE::VFMKDnaL:
    case VE::VFMKDnal:
    case VE::VFMKLa:
    case VE::VFMKLaL:
    case VE::VFMKLal:
    case VE::VFMKLna:
    case VE::VFMKLnaL:
    case VE::VFMKLnal:
    case VE::VFMKSa:
    case VE::VFMKSaL:
    case VE::VFMKSal:
    case VE::VFMKSna:
    case VE::VFMKSnaL:
    case VE::VFMKSnal:
    case VE::VFMKWa:
    case VE::VFMKWaL:
    case VE::VFMKWal:
    case VE::VFMKWna:
    case VE::VFMKWnaL:
    case VE::VFMKWnal:
    case VE::VSEQ:
    case VE::VSEQL:
    case VE::VSEQL_v:
    case VE::VSEQ_v:
    case VE::VSEQl:
    case VE::VSEQl_v: {
      switch (OpNum) {
      case 0:
        // op: vx
        return 24;
      }
      break;
    }
    case VE::PVFMKSLOam:
    case VE::PVFMKSLOamL:
    case VE::PVFMKSLOaml:
    case VE::PVFMKSLOnam:
    case VE::PVFMKSLOnamL:
    case VE::PVFMKSLOnaml:
    case VE::PVFMKSUPam:
    case VE::PVFMKSUPamL:
    case VE::PVFMKSUPaml:
    case VE::PVFMKSUPnam:
    case VE::PVFMKSUPnamL:
    case VE::PVFMKSUPnaml:
    case VE::PVFMKWLOam:
    case VE::PVFMKWLOamL:
    case VE::PVFMKWLOaml:
    case VE::PVFMKWLOnam:
    case VE::PVFMKWLOnamL:
    case VE::PVFMKWLOnaml:
    case VE::PVFMKWUPam:
    case VE::PVFMKWUPamL:
    case VE::PVFMKWUPaml:
    case VE::PVFMKWUPnam:
    case VE::PVFMKWUPnamL:
    case VE::PVFMKWUPnaml:
    case VE::PVSEQLOm:
    case VE::PVSEQLOmL:
    case VE::PVSEQLOmL_v:
    case VE::PVSEQLOm_v:
    case VE::PVSEQLOml:
    case VE::PVSEQLOml_v:
    case VE::PVSEQUPm:
    case VE::PVSEQUPmL:
    case VE::PVSEQUPmL_v:
    case VE::PVSEQUPm_v:
    case VE::PVSEQUPml:
    case VE::PVSEQUPml_v:
    case VE::PVSEQm:
    case VE::PVSEQmL:
    case VE::PVSEQmL_v:
    case VE::PVSEQm_v:
    case VE::PVSEQml:
    case VE::PVSEQml_v:
    case VE::VFMKDam:
    case VE::VFMKDamL:
    case VE::VFMKDaml:
    case VE::VFMKDnam:
    case VE::VFMKDnamL:
    case VE::VFMKDnaml:
    case VE::VFMKLam:
    case VE::VFMKLamL:
    case VE::VFMKLaml:
    case VE::VFMKLnam:
    case VE::VFMKLnamL:
    case VE::VFMKLnaml:
    case VE::VFMKSam:
    case VE::VFMKSamL:
    case VE::VFMKSaml:
    case VE::VFMKSnam:
    case VE::VFMKSnamL:
    case VE::VFMKSnaml:
    case VE::VFMKWam:
    case VE::VFMKWamL:
    case VE::VFMKWaml:
    case VE::VFMKWnam:
    case VE::VFMKWnamL:
    case VE::VFMKWnaml:
    case VE::VSEQm:
    case VE::VSEQmL:
    case VE::VSEQmL_v:
    case VE::VSEQm_v:
    case VE::VSEQml:
    case VE::VSEQml_v: {
      switch (OpNum) {
      case 1:
        // op: m
        return 48;
      case 0:
        // op: vx
        return 24;
      }
      break;
    }
    case VE::PVFMADLOivv:
    case VE::PVFMADLOivvL:
    case VE::PVFMADLOivvL_v:
    case VE::PVFMADLOivv_v:
    case VE::PVFMADLOivvl:
    case VE::PVFMADLOivvl_v:
    case VE::PVFMADLOrvv:
    case VE::PVFMADLOrvvL:
    case VE::PVFMADLOrvvL_v:
    case VE::PVFMADLOrvv_v:
    case VE::PVFMADLOrvvl:
    case VE::PVFMADLOrvvl_v:
    case VE::PVFMADUPivv:
    case VE::PVFMADUPivvL:
    case VE::PVFMADUPivvL_v:
    case VE::PVFMADUPivv_v:
    case VE::PVFMADUPivvl:
    case VE::PVFMADUPivvl_v:
    case VE::PVFMADUPrvv:
    case VE::PVFMADUPrvvL:
    case VE::PVFMADUPrvvL_v:
    case VE::PVFMADUPrvv_v:
    case VE::PVFMADUPrvvl:
    case VE::PVFMADUPrvvl_v:
    case VE::PVFMADivv:
    case VE::PVFMADivvL:
    case VE::PVFMADivvL_v:
    case VE::PVFMADivv_v:
    case VE::PVFMADivvl:
    case VE::PVFMADivvl_v:
    case VE::PVFMADrvv:
    case VE::PVFMADrvvL:
    case VE::PVFMADrvvL_v:
    case VE::PVFMADrvv_v:
    case VE::PVFMADrvvl:
    case VE::PVFMADrvvl_v:
    case VE::PVFMSBLOivv:
    case VE::PVFMSBLOivvL:
    case VE::PVFMSBLOivvL_v:
    case VE::PVFMSBLOivv_v:
    case VE::PVFMSBLOivvl:
    case VE::PVFMSBLOivvl_v:
    case VE::PVFMSBLOrvv:
    case VE::PVFMSBLOrvvL:
    case VE::PVFMSBLOrvvL_v:
    case VE::PVFMSBLOrvv_v:
    case VE::PVFMSBLOrvvl:
    case VE::PVFMSBLOrvvl_v:
    case VE::PVFMSBUPivv:
    case VE::PVFMSBUPivvL:
    case VE::PVFMSBUPivvL_v:
    case VE::PVFMSBUPivv_v:
    case VE::PVFMSBUPivvl:
    case VE::PVFMSBUPivvl_v:
    case VE::PVFMSBUPrvv:
    case VE::PVFMSBUPrvvL:
    case VE::PVFMSBUPrvvL_v:
    case VE::PVFMSBUPrvv_v:
    case VE::PVFMSBUPrvvl:
    case VE::PVFMSBUPrvvl_v:
    case VE::PVFMSBivv:
    case VE::PVFMSBivvL:
    case VE::PVFMSBivvL_v:
    case VE::PVFMSBivv_v:
    case VE::PVFMSBivvl:
    case VE::PVFMSBivvl_v:
    case VE::PVFMSBrvv:
    case VE::PVFMSBrvvL:
    case VE::PVFMSBrvvL_v:
    case VE::PVFMSBrvv_v:
    case VE::PVFMSBrvvl:
    case VE::PVFMSBrvvl_v:
    case VE::PVFNMADLOivv:
    case VE::PVFNMADLOivvL:
    case VE::PVFNMADLOivvL_v:
    case VE::PVFNMADLOivv_v:
    case VE::PVFNMADLOivvl:
    case VE::PVFNMADLOivvl_v:
    case VE::PVFNMADLOrvv:
    case VE::PVFNMADLOrvvL:
    case VE::PVFNMADLOrvvL_v:
    case VE::PVFNMADLOrvv_v:
    case VE::PVFNMADLOrvvl:
    case VE::PVFNMADLOrvvl_v:
    case VE::PVFNMADUPivv:
    case VE::PVFNMADUPivvL:
    case VE::PVFNMADUPivvL_v:
    case VE::PVFNMADUPivv_v:
    case VE::PVFNMADUPivvl:
    case VE::PVFNMADUPivvl_v:
    case VE::PVFNMADUPrvv:
    case VE::PVFNMADUPrvvL:
    case VE::PVFNMADUPrvvL_v:
    case VE::PVFNMADUPrvv_v:
    case VE::PVFNMADUPrvvl:
    case VE::PVFNMADUPrvvl_v:
    case VE::PVFNMADivv:
    case VE::PVFNMADivvL:
    case VE::PVFNMADivvL_v:
    case VE::PVFNMADivv_v:
    case VE::PVFNMADivvl:
    case VE::PVFNMADivvl_v:
    case VE::PVFNMADrvv:
    case VE::PVFNMADrvvL:
    case VE::PVFNMADrvvL_v:
    case VE::PVFNMADrvv_v:
    case VE::PVFNMADrvvl:
    case VE::PVFNMADrvvl_v:
    case VE::PVFNMSBLOivv:
    case VE::PVFNMSBLOivvL:
    case VE::PVFNMSBLOivvL_v:
    case VE::PVFNMSBLOivv_v:
    case VE::PVFNMSBLOivvl:
    case VE::PVFNMSBLOivvl_v:
    case VE::PVFNMSBLOrvv:
    case VE::PVFNMSBLOrvvL:
    case VE::PVFNMSBLOrvvL_v:
    case VE::PVFNMSBLOrvv_v:
    case VE::PVFNMSBLOrvvl:
    case VE::PVFNMSBLOrvvl_v:
    case VE::PVFNMSBUPivv:
    case VE::PVFNMSBUPivvL:
    case VE::PVFNMSBUPivvL_v:
    case VE::PVFNMSBUPivv_v:
    case VE::PVFNMSBUPivvl:
    case VE::PVFNMSBUPivvl_v:
    case VE::PVFNMSBUPrvv:
    case VE::PVFNMSBUPrvvL:
    case VE::PVFNMSBUPrvvL_v:
    case VE::PVFNMSBUPrvv_v:
    case VE::PVFNMSBUPrvvl:
    case VE::PVFNMSBUPrvvl_v:
    case VE::PVFNMSBivv:
    case VE::PVFNMSBivvL:
    case VE::PVFNMSBivvL_v:
    case VE::PVFNMSBivv_v:
    case VE::PVFNMSBivvl:
    case VE::PVFNMSBivvl_v:
    case VE::PVFNMSBrvv:
    case VE::PVFNMSBrvvL:
    case VE::PVFNMSBrvvL_v:
    case VE::PVFNMSBrvv_v:
    case VE::PVFNMSBrvvl:
    case VE::PVFNMSBrvvl_v:
    case VE::VFMADDivv:
    case VE::VFMADDivvL:
    case VE::VFMADDivvL_v:
    case VE::VFMADDivv_v:
    case VE::VFMADDivvl:
    case VE::VFMADDivvl_v:
    case VE::VFMADDrvv:
    case VE::VFMADDrvvL:
    case VE::VFMADDrvvL_v:
    case VE::VFMADDrvv_v:
    case VE::VFMADDrvvl:
    case VE::VFMADDrvvl_v:
    case VE::VFMADSivv:
    case VE::VFMADSivvL:
    case VE::VFMADSivvL_v:
    case VE::VFMADSivv_v:
    case VE::VFMADSivvl:
    case VE::VFMADSivvl_v:
    case VE::VFMADSrvv:
    case VE::VFMADSrvvL:
    case VE::VFMADSrvvL_v:
    case VE::VFMADSrvv_v:
    case VE::VFMADSrvvl:
    case VE::VFMADSrvvl_v:
    case VE::VFMSBDivv:
    case VE::VFMSBDivvL:
    case VE::VFMSBDivvL_v:
    case VE::VFMSBDivv_v:
    case VE::VFMSBDivvl:
    case VE::VFMSBDivvl_v:
    case VE::VFMSBDrvv:
    case VE::VFMSBDrvvL:
    case VE::VFMSBDrvvL_v:
    case VE::VFMSBDrvv_v:
    case VE::VFMSBDrvvl:
    case VE::VFMSBDrvvl_v:
    case VE::VFMSBSivv:
    case VE::VFMSBSivvL:
    case VE::VFMSBSivvL_v:
    case VE::VFMSBSivv_v:
    case VE::VFMSBSivvl:
    case VE::VFMSBSivvl_v:
    case VE::VFMSBSrvv:
    case VE::VFMSBSrvvL:
    case VE::VFMSBSrvvL_v:
    case VE::VFMSBSrvv_v:
    case VE::VFMSBSrvvl:
    case VE::VFMSBSrvvl_v:
    case VE::VFNMADDivv:
    case VE::VFNMADDivvL:
    case VE::VFNMADDivvL_v:
    case VE::VFNMADDivv_v:
    case VE::VFNMADDivvl:
    case VE::VFNMADDivvl_v:
    case VE::VFNMADDrvv:
    case VE::VFNMADDrvvL:
    case VE::VFNMADDrvvL_v:
    case VE::VFNMADDrvv_v:
    case VE::VFNMADDrvvl:
    case VE::VFNMADDrvvl_v:
    case VE::VFNMADSivv:
    case VE::VFNMADSivvL:
    case VE::VFNMADSivvL_v:
    case VE::VFNMADSivv_v:
    case VE::VFNMADSivvl:
    case VE::VFNMADSivvl_v:
    case VE::VFNMADSrvv:
    case VE::VFNMADSrvvL:
    case VE::VFNMADSrvvL_v:
    case VE::VFNMADSrvv_v:
    case VE::VFNMADSrvvl:
    case VE::VFNMADSrvvl_v:
    case VE::VFNMSBDivv:
    case VE::VFNMSBDivvL:
    case VE::VFNMSBDivvL_v:
    case VE::VFNMSBDivv_v:
    case VE::VFNMSBDivvl:
    case VE::VFNMSBDivvl_v:
    case VE::VFNMSBDrvv:
    case VE::VFNMSBDrvvL:
    case VE::VFNMSBDrvvL_v:
    case VE::VFNMSBDrvv_v:
    case VE::VFNMSBDrvvl:
    case VE::VFNMSBDrvvl_v:
    case VE::VFNMSBSivv:
    case VE::VFNMSBSivvL:
    case VE::VFNMSBSivvL_v:
    case VE::VFNMSBSivv_v:
    case VE::VFNMSBSivvl:
    case VE::VFNMSBSivvl_v:
    case VE::VFNMSBSrvv:
    case VE::VFNMSBSrvvL:
    case VE::VFNMSBSrvvL_v:
    case VE::VFNMSBSrvv_v:
    case VE::VFNMSBSrvvl:
    case VE::VFNMSBSrvvl_v: {
      switch (OpNum) {
      case 1:
        // op: sy
        return 40;
      case 0:
        // op: vx
        return 24;
      case 2:
        // op: vz
        return 8;
      case 3:
        // op: vw
        return 0;
      }
      break;
    }
    case VE::PVADDSLOiv:
    case VE::PVADDSLOivL:
    case VE::PVADDSLOivL_v:
    case VE::PVADDSLOiv_v:
    case VE::PVADDSLOivl:
    case VE::PVADDSLOivl_v:
    case VE::PVADDSLOrv:
    case VE::PVADDSLOrvL:
    case VE::PVADDSLOrvL_v:
    case VE::PVADDSLOrv_v:
    case VE::PVADDSLOrvl:
    case VE::PVADDSLOrvl_v:
    case VE::PVADDSUPiv:
    case VE::PVADDSUPivL:
    case VE::PVADDSUPivL_v:
    case VE::PVADDSUPiv_v:
    case VE::PVADDSUPivl:
    case VE::PVADDSUPivl_v:
    case VE::PVADDSUPrv:
    case VE::PVADDSUPrvL:
    case VE::PVADDSUPrvL_v:
    case VE::PVADDSUPrv_v:
    case VE::PVADDSUPrvl:
    case VE::PVADDSUPrvl_v:
    case VE::PVADDSiv:
    case VE::PVADDSivL:
    case VE::PVADDSivL_v:
    case VE::PVADDSiv_v:
    case VE::PVADDSivl:
    case VE::PVADDSivl_v:
    case VE::PVADDSrv:
    case VE::PVADDSrvL:
    case VE::PVADDSrvL_v:
    case VE::PVADDSrv_v:
    case VE::PVADDSrvl:
    case VE::PVADDSrvl_v:
    case VE::PVADDULOiv:
    case VE::PVADDULOivL:
    case VE::PVADDULOivL_v:
    case VE::PVADDULOiv_v:
    case VE::PVADDULOivl:
    case VE::PVADDULOivl_v:
    case VE::PVADDULOrv:
    case VE::PVADDULOrvL:
    case VE::PVADDULOrvL_v:
    case VE::PVADDULOrv_v:
    case VE::PVADDULOrvl:
    case VE::PVADDULOrvl_v:
    case VE::PVADDUUPiv:
    case VE::PVADDUUPivL:
    case VE::PVADDUUPivL_v:
    case VE::PVADDUUPiv_v:
    case VE::PVADDUUPivl:
    case VE::PVADDUUPivl_v:
    case VE::PVADDUUPrv:
    case VE::PVADDUUPrvL:
    case VE::PVADDUUPrvL_v:
    case VE::PVADDUUPrv_v:
    case VE::PVADDUUPrvl:
    case VE::PVADDUUPrvl_v:
    case VE::PVADDUiv:
    case VE::PVADDUivL:
    case VE::PVADDUivL_v:
    case VE::PVADDUiv_v:
    case VE::PVADDUivl:
    case VE::PVADDUivl_v:
    case VE::PVADDUrv:
    case VE::PVADDUrvL:
    case VE::PVADDUrvL_v:
    case VE::PVADDUrv_v:
    case VE::PVADDUrvl:
    case VE::PVADDUrvl_v:
    case VE::PVANDLOmv:
    case VE::PVANDLOmvL:
    case VE::PVANDLOmvL_v:
    case VE::PVANDLOmv_v:
    case VE::PVANDLOmvl:
    case VE::PVANDLOmvl_v:
    case VE::PVANDLOrv:
    case VE::PVANDLOrvL:
    case VE::PVANDLOrvL_v:
    case VE::PVANDLOrv_v:
    case VE::PVANDLOrvl:
    case VE::PVANDLOrvl_v:
    case VE::PVANDUPmv:
    case VE::PVANDUPmvL:
    case VE::PVANDUPmvL_v:
    case VE::PVANDUPmv_v:
    case VE::PVANDUPmvl:
    case VE::PVANDUPmvl_v:
    case VE::PVANDUPrv:
    case VE::PVANDUPrvL:
    case VE::PVANDUPrvL_v:
    case VE::PVANDUPrv_v:
    case VE::PVANDUPrvl:
    case VE::PVANDUPrvl_v:
    case VE::PVANDmv:
    case VE::PVANDmvL:
    case VE::PVANDmvL_v:
    case VE::PVANDmv_v:
    case VE::PVANDmvl:
    case VE::PVANDmvl_v:
    case VE::PVANDrv:
    case VE::PVANDrvL:
    case VE::PVANDrvL_v:
    case VE::PVANDrv_v:
    case VE::PVANDrvl:
    case VE::PVANDrvl_v:
    case VE::PVCMPSLOiv:
    case VE::PVCMPSLOivL:
    case VE::PVCMPSLOivL_v:
    case VE::PVCMPSLOiv_v:
    case VE::PVCMPSLOivl:
    case VE::PVCMPSLOivl_v:
    case VE::PVCMPSLOrv:
    case VE::PVCMPSLOrvL:
    case VE::PVCMPSLOrvL_v:
    case VE::PVCMPSLOrv_v:
    case VE::PVCMPSLOrvl:
    case VE::PVCMPSLOrvl_v:
    case VE::PVCMPSUPiv:
    case VE::PVCMPSUPivL:
    case VE::PVCMPSUPivL_v:
    case VE::PVCMPSUPiv_v:
    case VE::PVCMPSUPivl:
    case VE::PVCMPSUPivl_v:
    case VE::PVCMPSUPrv:
    case VE::PVCMPSUPrvL:
    case VE::PVCMPSUPrvL_v:
    case VE::PVCMPSUPrv_v:
    case VE::PVCMPSUPrvl:
    case VE::PVCMPSUPrvl_v:
    case VE::PVCMPSiv:
    case VE::PVCMPSivL:
    case VE::PVCMPSivL_v:
    case VE::PVCMPSiv_v:
    case VE::PVCMPSivl:
    case VE::PVCMPSivl_v:
    case VE::PVCMPSrv:
    case VE::PVCMPSrvL:
    case VE::PVCMPSrvL_v:
    case VE::PVCMPSrv_v:
    case VE::PVCMPSrvl:
    case VE::PVCMPSrvl_v:
    case VE::PVCMPULOiv:
    case VE::PVCMPULOivL:
    case VE::PVCMPULOivL_v:
    case VE::PVCMPULOiv_v:
    case VE::PVCMPULOivl:
    case VE::PVCMPULOivl_v:
    case VE::PVCMPULOrv:
    case VE::PVCMPULOrvL:
    case VE::PVCMPULOrvL_v:
    case VE::PVCMPULOrv_v:
    case VE::PVCMPULOrvl:
    case VE::PVCMPULOrvl_v:
    case VE::PVCMPUUPiv:
    case VE::PVCMPUUPivL:
    case VE::PVCMPUUPivL_v:
    case VE::PVCMPUUPiv_v:
    case VE::PVCMPUUPivl:
    case VE::PVCMPUUPivl_v:
    case VE::PVCMPUUPrv:
    case VE::PVCMPUUPrvL:
    case VE::PVCMPUUPrvL_v:
    case VE::PVCMPUUPrv_v:
    case VE::PVCMPUUPrvl:
    case VE::PVCMPUUPrvl_v:
    case VE::PVCMPUiv:
    case VE::PVCMPUivL:
    case VE::PVCMPUivL_v:
    case VE::PVCMPUiv_v:
    case VE::PVCMPUivl:
    case VE::PVCMPUivl_v:
    case VE::PVCMPUrv:
    case VE::PVCMPUrvL:
    case VE::PVCMPUrvL_v:
    case VE::PVCMPUrv_v:
    case VE::PVCMPUrvl:
    case VE::PVCMPUrvl_v:
    case VE::PVEQVLOmv:
    case VE::PVEQVLOmvL:
    case VE::PVEQVLOmvL_v:
    case VE::PVEQVLOmv_v:
    case VE::PVEQVLOmvl:
    case VE::PVEQVLOmvl_v:
    case VE::PVEQVLOrv:
    case VE::PVEQVLOrvL:
    case VE::PVEQVLOrvL_v:
    case VE::PVEQVLOrv_v:
    case VE::PVEQVLOrvl:
    case VE::PVEQVLOrvl_v:
    case VE::PVEQVUPmv:
    case VE::PVEQVUPmvL:
    case VE::PVEQVUPmvL_v:
    case VE::PVEQVUPmv_v:
    case VE::PVEQVUPmvl:
    case VE::PVEQVUPmvl_v:
    case VE::PVEQVUPrv:
    case VE::PVEQVUPrvL:
    case VE::PVEQVUPrvL_v:
    case VE::PVEQVUPrv_v:
    case VE::PVEQVUPrvl:
    case VE::PVEQVUPrvl_v:
    case VE::PVEQVmv:
    case VE::PVEQVmvL:
    case VE::PVEQVmvL_v:
    case VE::PVEQVmv_v:
    case VE::PVEQVmvl:
    case VE::PVEQVmvl_v:
    case VE::PVEQVrv:
    case VE::PVEQVrvL:
    case VE::PVEQVrvL_v:
    case VE::PVEQVrv_v:
    case VE::PVEQVrvl:
    case VE::PVEQVrvl_v:
    case VE::PVFADDLOiv:
    case VE::PVFADDLOivL:
    case VE::PVFADDLOivL_v:
    case VE::PVFADDLOiv_v:
    case VE::PVFADDLOivl:
    case VE::PVFADDLOivl_v:
    case VE::PVFADDLOrv:
    case VE::PVFADDLOrvL:
    case VE::PVFADDLOrvL_v:
    case VE::PVFADDLOrv_v:
    case VE::PVFADDLOrvl:
    case VE::PVFADDLOrvl_v:
    case VE::PVFADDUPiv:
    case VE::PVFADDUPivL:
    case VE::PVFADDUPivL_v:
    case VE::PVFADDUPiv_v:
    case VE::PVFADDUPivl:
    case VE::PVFADDUPivl_v:
    case VE::PVFADDUPrv:
    case VE::PVFADDUPrvL:
    case VE::PVFADDUPrvL_v:
    case VE::PVFADDUPrv_v:
    case VE::PVFADDUPrvl:
    case VE::PVFADDUPrvl_v:
    case VE::PVFADDiv:
    case VE::PVFADDivL:
    case VE::PVFADDivL_v:
    case VE::PVFADDiv_v:
    case VE::PVFADDivl:
    case VE::PVFADDivl_v:
    case VE::PVFADDrv:
    case VE::PVFADDrvL:
    case VE::PVFADDrvL_v:
    case VE::PVFADDrv_v:
    case VE::PVFADDrvl:
    case VE::PVFADDrvl_v:
    case VE::PVFCMPLOiv:
    case VE::PVFCMPLOivL:
    case VE::PVFCMPLOivL_v:
    case VE::PVFCMPLOiv_v:
    case VE::PVFCMPLOivl:
    case VE::PVFCMPLOivl_v:
    case VE::PVFCMPLOrv:
    case VE::PVFCMPLOrvL:
    case VE::PVFCMPLOrvL_v:
    case VE::PVFCMPLOrv_v:
    case VE::PVFCMPLOrvl:
    case VE::PVFCMPLOrvl_v:
    case VE::PVFCMPUPiv:
    case VE::PVFCMPUPivL:
    case VE::PVFCMPUPivL_v:
    case VE::PVFCMPUPiv_v:
    case VE::PVFCMPUPivl:
    case VE::PVFCMPUPivl_v:
    case VE::PVFCMPUPrv:
    case VE::PVFCMPUPrvL:
    case VE::PVFCMPUPrvL_v:
    case VE::PVFCMPUPrv_v:
    case VE::PVFCMPUPrvl:
    case VE::PVFCMPUPrvl_v:
    case VE::PVFCMPiv:
    case VE::PVFCMPivL:
    case VE::PVFCMPivL_v:
    case VE::PVFCMPiv_v:
    case VE::PVFCMPivl:
    case VE::PVFCMPivl_v:
    case VE::PVFCMPrv:
    case VE::PVFCMPrvL:
    case VE::PVFCMPrvL_v:
    case VE::PVFCMPrv_v:
    case VE::PVFCMPrvl:
    case VE::PVFCMPrvl_v:
    case VE::PVFMAXLOiv:
    case VE::PVFMAXLOivL:
    case VE::PVFMAXLOivL_v:
    case VE::PVFMAXLOiv_v:
    case VE::PVFMAXLOivl:
    case VE::PVFMAXLOivl_v:
    case VE::PVFMAXLOrv:
    case VE::PVFMAXLOrvL:
    case VE::PVFMAXLOrvL_v:
    case VE::PVFMAXLOrv_v:
    case VE::PVFMAXLOrvl:
    case VE::PVFMAXLOrvl_v:
    case VE::PVFMAXUPiv:
    case VE::PVFMAXUPivL:
    case VE::PVFMAXUPivL_v:
    case VE::PVFMAXUPiv_v:
    case VE::PVFMAXUPivl:
    case VE::PVFMAXUPivl_v:
    case VE::PVFMAXUPrv:
    case VE::PVFMAXUPrvL:
    case VE::PVFMAXUPrvL_v:
    case VE::PVFMAXUPrv_v:
    case VE::PVFMAXUPrvl:
    case VE::PVFMAXUPrvl_v:
    case VE::PVFMAXiv:
    case VE::PVFMAXivL:
    case VE::PVFMAXivL_v:
    case VE::PVFMAXiv_v:
    case VE::PVFMAXivl:
    case VE::PVFMAXivl_v:
    case VE::PVFMAXrv:
    case VE::PVFMAXrvL:
    case VE::PVFMAXrvL_v:
    case VE::PVFMAXrv_v:
    case VE::PVFMAXrvl:
    case VE::PVFMAXrvl_v:
    case VE::PVFMINLOiv:
    case VE::PVFMINLOivL:
    case VE::PVFMINLOivL_v:
    case VE::PVFMINLOiv_v:
    case VE::PVFMINLOivl:
    case VE::PVFMINLOivl_v:
    case VE::PVFMINLOrv:
    case VE::PVFMINLOrvL:
    case VE::PVFMINLOrvL_v:
    case VE::PVFMINLOrv_v:
    case VE::PVFMINLOrvl:
    case VE::PVFMINLOrvl_v:
    case VE::PVFMINUPiv:
    case VE::PVFMINUPivL:
    case VE::PVFMINUPivL_v:
    case VE::PVFMINUPiv_v:
    case VE::PVFMINUPivl:
    case VE::PVFMINUPivl_v:
    case VE::PVFMINUPrv:
    case VE::PVFMINUPrvL:
    case VE::PVFMINUPrvL_v:
    case VE::PVFMINUPrv_v:
    case VE::PVFMINUPrvl:
    case VE::PVFMINUPrvl_v:
    case VE::PVFMINiv:
    case VE::PVFMINivL:
    case VE::PVFMINivL_v:
    case VE::PVFMINiv_v:
    case VE::PVFMINivl:
    case VE::PVFMINivl_v:
    case VE::PVFMINrv:
    case VE::PVFMINrvL:
    case VE::PVFMINrvL_v:
    case VE::PVFMINrv_v:
    case VE::PVFMINrvl:
    case VE::PVFMINrvl_v:
    case VE::PVFMULLOiv:
    case VE::PVFMULLOivL:
    case VE::PVFMULLOivL_v:
    case VE::PVFMULLOiv_v:
    case VE::PVFMULLOivl:
    case VE::PVFMULLOivl_v:
    case VE::PVFMULLOrv:
    case VE::PVFMULLOrvL:
    case VE::PVFMULLOrvL_v:
    case VE::PVFMULLOrv_v:
    case VE::PVFMULLOrvl:
    case VE::PVFMULLOrvl_v:
    case VE::PVFMULUPiv:
    case VE::PVFMULUPivL:
    case VE::PVFMULUPivL_v:
    case VE::PVFMULUPiv_v:
    case VE::PVFMULUPivl:
    case VE::PVFMULUPivl_v:
    case VE::PVFMULUPrv:
    case VE::PVFMULUPrvL:
    case VE::PVFMULUPrvL_v:
    case VE::PVFMULUPrv_v:
    case VE::PVFMULUPrvl:
    case VE::PVFMULUPrvl_v:
    case VE::PVFMULiv:
    case VE::PVFMULivL:
    case VE::PVFMULivL_v:
    case VE::PVFMULiv_v:
    case VE::PVFMULivl:
    case VE::PVFMULivl_v:
    case VE::PVFMULrv:
    case VE::PVFMULrvL:
    case VE::PVFMULrvL_v:
    case VE::PVFMULrv_v:
    case VE::PVFMULrvl:
    case VE::PVFMULrvl_v:
    case VE::PVFSUBLOiv:
    case VE::PVFSUBLOivL:
    case VE::PVFSUBLOivL_v:
    case VE::PVFSUBLOiv_v:
    case VE::PVFSUBLOivl:
    case VE::PVFSUBLOivl_v:
    case VE::PVFSUBLOrv:
    case VE::PVFSUBLOrvL:
    case VE::PVFSUBLOrvL_v:
    case VE::PVFSUBLOrv_v:
    case VE::PVFSUBLOrvl:
    case VE::PVFSUBLOrvl_v:
    case VE::PVFSUBUPiv:
    case VE::PVFSUBUPivL:
    case VE::PVFSUBUPivL_v:
    case VE::PVFSUBUPiv_v:
    case VE::PVFSUBUPivl:
    case VE::PVFSUBUPivl_v:
    case VE::PVFSUBUPrv:
    case VE::PVFSUBUPrvL:
    case VE::PVFSUBUPrvL_v:
    case VE::PVFSUBUPrv_v:
    case VE::PVFSUBUPrvl:
    case VE::PVFSUBUPrvl_v:
    case VE::PVFSUBiv:
    case VE::PVFSUBivL:
    case VE::PVFSUBivL_v:
    case VE::PVFSUBiv_v:
    case VE::PVFSUBivl:
    case VE::PVFSUBivl_v:
    case VE::PVFSUBrv:
    case VE::PVFSUBrvL:
    case VE::PVFSUBrvL_v:
    case VE::PVFSUBrv_v:
    case VE::PVFSUBrvl:
    case VE::PVFSUBrvl_v:
    case VE::PVMAXSLOiv:
    case VE::PVMAXSLOivL:
    case VE::PVMAXSLOivL_v:
    case VE::PVMAXSLOiv_v:
    case VE::PVMAXSLOivl:
    case VE::PVMAXSLOivl_v:
    case VE::PVMAXSLOrv:
    case VE::PVMAXSLOrvL:
    case VE::PVMAXSLOrvL_v:
    case VE::PVMAXSLOrv_v:
    case VE::PVMAXSLOrvl:
    case VE::PVMAXSLOrvl_v:
    case VE::PVMAXSUPiv:
    case VE::PVMAXSUPivL:
    case VE::PVMAXSUPivL_v:
    case VE::PVMAXSUPiv_v:
    case VE::PVMAXSUPivl:
    case VE::PVMAXSUPivl_v:
    case VE::PVMAXSUPrv:
    case VE::PVMAXSUPrvL:
    case VE::PVMAXSUPrvL_v:
    case VE::PVMAXSUPrv_v:
    case VE::PVMAXSUPrvl:
    case VE::PVMAXSUPrvl_v:
    case VE::PVMAXSiv:
    case VE::PVMAXSivL:
    case VE::PVMAXSivL_v:
    case VE::PVMAXSiv_v:
    case VE::PVMAXSivl:
    case VE::PVMAXSivl_v:
    case VE::PVMAXSrv:
    case VE::PVMAXSrvL:
    case VE::PVMAXSrvL_v:
    case VE::PVMAXSrv_v:
    case VE::PVMAXSrvl:
    case VE::PVMAXSrvl_v:
    case VE::PVMINSLOiv:
    case VE::PVMINSLOivL:
    case VE::PVMINSLOivL_v:
    case VE::PVMINSLOiv_v:
    case VE::PVMINSLOivl:
    case VE::PVMINSLOivl_v:
    case VE::PVMINSLOrv:
    case VE::PVMINSLOrvL:
    case VE::PVMINSLOrvL_v:
    case VE::PVMINSLOrv_v:
    case VE::PVMINSLOrvl:
    case VE::PVMINSLOrvl_v:
    case VE::PVMINSUPiv:
    case VE::PVMINSUPivL:
    case VE::PVMINSUPivL_v:
    case VE::PVMINSUPiv_v:
    case VE::PVMINSUPivl:
    case VE::PVMINSUPivl_v:
    case VE::PVMINSUPrv:
    case VE::PVMINSUPrvL:
    case VE::PVMINSUPrvL_v:
    case VE::PVMINSUPrv_v:
    case VE::PVMINSUPrvl:
    case VE::PVMINSUPrvl_v:
    case VE::PVMINSiv:
    case VE::PVMINSivL:
    case VE::PVMINSivL_v:
    case VE::PVMINSiv_v:
    case VE::PVMINSivl:
    case VE::PVMINSivl_v:
    case VE::PVMINSrv:
    case VE::PVMINSrvL:
    case VE::PVMINSrvL_v:
    case VE::PVMINSrv_v:
    case VE::PVMINSrvl:
    case VE::PVMINSrvl_v:
    case VE::PVORLOmv:
    case VE::PVORLOmvL:
    case VE::PVORLOmvL_v:
    case VE::PVORLOmv_v:
    case VE::PVORLOmvl:
    case VE::PVORLOmvl_v:
    case VE::PVORLOrv:
    case VE::PVORLOrvL:
    case VE::PVORLOrvL_v:
    case VE::PVORLOrv_v:
    case VE::PVORLOrvl:
    case VE::PVORLOrvl_v:
    case VE::PVORUPmv:
    case VE::PVORUPmvL:
    case VE::PVORUPmvL_v:
    case VE::PVORUPmv_v:
    case VE::PVORUPmvl:
    case VE::PVORUPmvl_v:
    case VE::PVORUPrv:
    case VE::PVORUPrvL:
    case VE::PVORUPrvL_v:
    case VE::PVORUPrv_v:
    case VE::PVORUPrvl:
    case VE::PVORUPrvl_v:
    case VE::PVORmv:
    case VE::PVORmvL:
    case VE::PVORmvL_v:
    case VE::PVORmv_v:
    case VE::PVORmvl:
    case VE::PVORmvl_v:
    case VE::PVORrv:
    case VE::PVORrvL:
    case VE::PVORrvL_v:
    case VE::PVORrv_v:
    case VE::PVORrvl:
    case VE::PVORrvl_v:
    case VE::PVSUBSLOiv:
    case VE::PVSUBSLOivL:
    case VE::PVSUBSLOivL_v:
    case VE::PVSUBSLOiv_v:
    case VE::PVSUBSLOivl:
    case VE::PVSUBSLOivl_v:
    case VE::PVSUBSLOrv:
    case VE::PVSUBSLOrvL:
    case VE::PVSUBSLOrvL_v:
    case VE::PVSUBSLOrv_v:
    case VE::PVSUBSLOrvl:
    case VE::PVSUBSLOrvl_v:
    case VE::PVSUBSUPiv:
    case VE::PVSUBSUPivL:
    case VE::PVSUBSUPivL_v:
    case VE::PVSUBSUPiv_v:
    case VE::PVSUBSUPivl:
    case VE::PVSUBSUPivl_v:
    case VE::PVSUBSUPrv:
    case VE::PVSUBSUPrvL:
    case VE::PVSUBSUPrvL_v:
    case VE::PVSUBSUPrv_v:
    case VE::PVSUBSUPrvl:
    case VE::PVSUBSUPrvl_v:
    case VE::PVSUBSiv:
    case VE::PVSUBSivL:
    case VE::PVSUBSivL_v:
    case VE::PVSUBSiv_v:
    case VE::PVSUBSivl:
    case VE::PVSUBSivl_v:
    case VE::PVSUBSrv:
    case VE::PVSUBSrvL:
    case VE::PVSUBSrvL_v:
    case VE::PVSUBSrv_v:
    case VE::PVSUBSrvl:
    case VE::PVSUBSrvl_v:
    case VE::PVSUBULOiv:
    case VE::PVSUBULOivL:
    case VE::PVSUBULOivL_v:
    case VE::PVSUBULOiv_v:
    case VE::PVSUBULOivl:
    case VE::PVSUBULOivl_v:
    case VE::PVSUBULOrv:
    case VE::PVSUBULOrvL:
    case VE::PVSUBULOrvL_v:
    case VE::PVSUBULOrv_v:
    case VE::PVSUBULOrvl:
    case VE::PVSUBULOrvl_v:
    case VE::PVSUBUUPiv:
    case VE::PVSUBUUPivL:
    case VE::PVSUBUUPivL_v:
    case VE::PVSUBUUPiv_v:
    case VE::PVSUBUUPivl:
    case VE::PVSUBUUPivl_v:
    case VE::PVSUBUUPrv:
    case VE::PVSUBUUPrvL:
    case VE::PVSUBUUPrvL_v:
    case VE::PVSUBUUPrv_v:
    case VE::PVSUBUUPrvl:
    case VE::PVSUBUUPrvl_v:
    case VE::PVSUBUiv:
    case VE::PVSUBUivL:
    case VE::PVSUBUivL_v:
    case VE::PVSUBUiv_v:
    case VE::PVSUBUivl:
    case VE::PVSUBUivl_v:
    case VE::PVSUBUrv:
    case VE::PVSUBUrvL:
    case VE::PVSUBUrvL_v:
    case VE::PVSUBUrv_v:
    case VE::PVSUBUrvl:
    case VE::PVSUBUrvl_v:
    case VE::PVXORLOmv:
    case VE::PVXORLOmvL:
    case VE::PVXORLOmvL_v:
    case VE::PVXORLOmv_v:
    case VE::PVXORLOmvl:
    case VE::PVXORLOmvl_v:
    case VE::PVXORLOrv:
    case VE::PVXORLOrvL:
    case VE::PVXORLOrvL_v:
    case VE::PVXORLOrv_v:
    case VE::PVXORLOrvl:
    case VE::PVXORLOrvl_v:
    case VE::PVXORUPmv:
    case VE::PVXORUPmvL:
    case VE::PVXORUPmvL_v:
    case VE::PVXORUPmv_v:
    case VE::PVXORUPmvl:
    case VE::PVXORUPmvl_v:
    case VE::PVXORUPrv:
    case VE::PVXORUPrvL:
    case VE::PVXORUPrvL_v:
    case VE::PVXORUPrv_v:
    case VE::PVXORUPrvl:
    case VE::PVXORUPrvl_v:
    case VE::PVXORmv:
    case VE::PVXORmvL:
    case VE::PVXORmvL_v:
    case VE::PVXORmv_v:
    case VE::PVXORmvl:
    case VE::PVXORmvl_v:
    case VE::PVXORrv:
    case VE::PVXORrvL:
    case VE::PVXORrvL_v:
    case VE::PVXORrv_v:
    case VE::PVXORrvl:
    case VE::PVXORrvl_v:
    case VE::VADDSLiv:
    case VE::VADDSLivL:
    case VE::VADDSLivL_v:
    case VE::VADDSLiv_v:
    case VE::VADDSLivl:
    case VE::VADDSLivl_v:
    case VE::VADDSLrv:
    case VE::VADDSLrvL:
    case VE::VADDSLrvL_v:
    case VE::VADDSLrv_v:
    case VE::VADDSLrvl:
    case VE::VADDSLrvl_v:
    case VE::VADDSWSXiv:
    case VE::VADDSWSXivL:
    case VE::VADDSWSXivL_v:
    case VE::VADDSWSXiv_v:
    case VE::VADDSWSXivl:
    case VE::VADDSWSXivl_v:
    case VE::VADDSWSXrv:
    case VE::VADDSWSXrvL:
    case VE::VADDSWSXrvL_v:
    case VE::VADDSWSXrv_v:
    case VE::VADDSWSXrvl:
    case VE::VADDSWSXrvl_v:
    case VE::VADDSWZXiv:
    case VE::VADDSWZXivL:
    case VE::VADDSWZXivL_v:
    case VE::VADDSWZXiv_v:
    case VE::VADDSWZXivl:
    case VE::VADDSWZXivl_v:
    case VE::VADDSWZXrv:
    case VE::VADDSWZXrvL:
    case VE::VADDSWZXrvL_v:
    case VE::VADDSWZXrv_v:
    case VE::VADDSWZXrvl:
    case VE::VADDSWZXrvl_v:
    case VE::VADDULiv:
    case VE::VADDULivL:
    case VE::VADDULivL_v:
    case VE::VADDULiv_v:
    case VE::VADDULivl:
    case VE::VADDULivl_v:
    case VE::VADDULrv:
    case VE::VADDULrvL:
    case VE::VADDULrvL_v:
    case VE::VADDULrv_v:
    case VE::VADDULrvl:
    case VE::VADDULrvl_v:
    case VE::VADDUWiv:
    case VE::VADDUWivL:
    case VE::VADDUWivL_v:
    case VE::VADDUWiv_v:
    case VE::VADDUWivl:
    case VE::VADDUWivl_v:
    case VE::VADDUWrv:
    case VE::VADDUWrvL:
    case VE::VADDUWrvL_v:
    case VE::VADDUWrv_v:
    case VE::VADDUWrvl:
    case VE::VADDUWrvl_v:
    case VE::VANDmv:
    case VE::VANDmvL:
    case VE::VANDmvL_v:
    case VE::VANDmv_v:
    case VE::VANDmvl:
    case VE::VANDmvl_v:
    case VE::VANDrv:
    case VE::VANDrvL:
    case VE::VANDrvL_v:
    case VE::VANDrv_v:
    case VE::VANDrvl:
    case VE::VANDrvl_v:
    case VE::VCMPSLiv:
    case VE::VCMPSLivL:
    case VE::VCMPSLivL_v:
    case VE::VCMPSLiv_v:
    case VE::VCMPSLivl:
    case VE::VCMPSLivl_v:
    case VE::VCMPSLrv:
    case VE::VCMPSLrvL:
    case VE::VCMPSLrvL_v:
    case VE::VCMPSLrv_v:
    case VE::VCMPSLrvl:
    case VE::VCMPSLrvl_v:
    case VE::VCMPSWSXiv:
    case VE::VCMPSWSXivL:
    case VE::VCMPSWSXivL_v:
    case VE::VCMPSWSXiv_v:
    case VE::VCMPSWSXivl:
    case VE::VCMPSWSXivl_v:
    case VE::VCMPSWSXrv:
    case VE::VCMPSWSXrvL:
    case VE::VCMPSWSXrvL_v:
    case VE::VCMPSWSXrv_v:
    case VE::VCMPSWSXrvl:
    case VE::VCMPSWSXrvl_v:
    case VE::VCMPSWZXiv:
    case VE::VCMPSWZXivL:
    case VE::VCMPSWZXivL_v:
    case VE::VCMPSWZXiv_v:
    case VE::VCMPSWZXivl:
    case VE::VCMPSWZXivl_v:
    case VE::VCMPSWZXrv:
    case VE::VCMPSWZXrvL:
    case VE::VCMPSWZXrvL_v:
    case VE::VCMPSWZXrv_v:
    case VE::VCMPSWZXrvl:
    case VE::VCMPSWZXrvl_v:
    case VE::VCMPULiv:
    case VE::VCMPULivL:
    case VE::VCMPULivL_v:
    case VE::VCMPULiv_v:
    case VE::VCMPULivl:
    case VE::VCMPULivl_v:
    case VE::VCMPULrv:
    case VE::VCMPULrvL:
    case VE::VCMPULrvL_v:
    case VE::VCMPULrv_v:
    case VE::VCMPULrvl:
    case VE::VCMPULrvl_v:
    case VE::VCMPUWiv:
    case VE::VCMPUWivL:
    case VE::VCMPUWivL_v:
    case VE::VCMPUWiv_v:
    case VE::VCMPUWivl:
    case VE::VCMPUWivl_v:
    case VE::VCMPUWrv:
    case VE::VCMPUWrvL:
    case VE::VCMPUWrvL_v:
    case VE::VCMPUWrv_v:
    case VE::VCMPUWrvl:
    case VE::VCMPUWrvl_v:
    case VE::VDIVSLiv:
    case VE::VDIVSLivL:
    case VE::VDIVSLivL_v:
    case VE::VDIVSLiv_v:
    case VE::VDIVSLivl:
    case VE::VDIVSLivl_v:
    case VE::VDIVSLrv:
    case VE::VDIVSLrvL:
    case VE::VDIVSLrvL_v:
    case VE::VDIVSLrv_v:
    case VE::VDIVSLrvl:
    case VE::VDIVSLrvl_v:
    case VE::VDIVSWSXiv:
    case VE::VDIVSWSXivL:
    case VE::VDIVSWSXivL_v:
    case VE::VDIVSWSXiv_v:
    case VE::VDIVSWSXivl:
    case VE::VDIVSWSXivl_v:
    case VE::VDIVSWSXrv:
    case VE::VDIVSWSXrvL:
    case VE::VDIVSWSXrvL_v:
    case VE::VDIVSWSXrv_v:
    case VE::VDIVSWSXrvl:
    case VE::VDIVSWSXrvl_v:
    case VE::VDIVSWZXiv:
    case VE::VDIVSWZXivL:
    case VE::VDIVSWZXivL_v:
    case VE::VDIVSWZXiv_v:
    case VE::VDIVSWZXivl:
    case VE::VDIVSWZXivl_v:
    case VE::VDIVSWZXrv:
    case VE::VDIVSWZXrvL:
    case VE::VDIVSWZXrvL_v:
    case VE::VDIVSWZXrv_v:
    case VE::VDIVSWZXrvl:
    case VE::VDIVSWZXrvl_v:
    case VE::VDIVULiv:
    case VE::VDIVULivL:
    case VE::VDIVULivL_v:
    case VE::VDIVULiv_v:
    case VE::VDIVULivl:
    case VE::VDIVULivl_v:
    case VE::VDIVULrv:
    case VE::VDIVULrvL:
    case VE::VDIVULrvL_v:
    case VE::VDIVULrv_v:
    case VE::VDIVULrvl:
    case VE::VDIVULrvl_v:
    case VE::VDIVUWiv:
    case VE::VDIVUWivL:
    case VE::VDIVUWivL_v:
    case VE::VDIVUWiv_v:
    case VE::VDIVUWivl:
    case VE::VDIVUWivl_v:
    case VE::VDIVUWrv:
    case VE::VDIVUWrvL:
    case VE::VDIVUWrvL_v:
    case VE::VDIVUWrv_v:
    case VE::VDIVUWrvl:
    case VE::VDIVUWrvl_v:
    case VE::VEQVmv:
    case VE::VEQVmvL:
    case VE::VEQVmvL_v:
    case VE::VEQVmv_v:
    case VE::VEQVmvl:
    case VE::VEQVmvl_v:
    case VE::VEQVrv:
    case VE::VEQVrvL:
    case VE::VEQVrvL_v:
    case VE::VEQVrv_v:
    case VE::VEQVrvl:
    case VE::VEQVrvl_v:
    case VE::VFADDDiv:
    case VE::VFADDDivL:
    case VE::VFADDDivL_v:
    case VE::VFADDDiv_v:
    case VE::VFADDDivl:
    case VE::VFADDDivl_v:
    case VE::VFADDDrv:
    case VE::VFADDDrvL:
    case VE::VFADDDrvL_v:
    case VE::VFADDDrv_v:
    case VE::VFADDDrvl:
    case VE::VFADDDrvl_v:
    case VE::VFADDSiv:
    case VE::VFADDSivL:
    case VE::VFADDSivL_v:
    case VE::VFADDSiv_v:
    case VE::VFADDSivl:
    case VE::VFADDSivl_v:
    case VE::VFADDSrv:
    case VE::VFADDSrvL:
    case VE::VFADDSrvL_v:
    case VE::VFADDSrv_v:
    case VE::VFADDSrvl:
    case VE::VFADDSrvl_v:
    case VE::VFCMPDiv:
    case VE::VFCMPDivL:
    case VE::VFCMPDivL_v:
    case VE::VFCMPDiv_v:
    case VE::VFCMPDivl:
    case VE::VFCMPDivl_v:
    case VE::VFCMPDrv:
    case VE::VFCMPDrvL:
    case VE::VFCMPDrvL_v:
    case VE::VFCMPDrv_v:
    case VE::VFCMPDrvl:
    case VE::VFCMPDrvl_v:
    case VE::VFCMPSiv:
    case VE::VFCMPSivL:
    case VE::VFCMPSivL_v:
    case VE::VFCMPSiv_v:
    case VE::VFCMPSivl:
    case VE::VFCMPSivl_v:
    case VE::VFCMPSrv:
    case VE::VFCMPSrvL:
    case VE::VFCMPSrvL_v:
    case VE::VFCMPSrv_v:
    case VE::VFCMPSrvl:
    case VE::VFCMPSrvl_v:
    case VE::VFDIVDiv:
    case VE::VFDIVDivL:
    case VE::VFDIVDivL_v:
    case VE::VFDIVDiv_v:
    case VE::VFDIVDivl:
    case VE::VFDIVDivl_v:
    case VE::VFDIVDrv:
    case VE::VFDIVDrvL:
    case VE::VFDIVDrvL_v:
    case VE::VFDIVDrv_v:
    case VE::VFDIVDrvl:
    case VE::VFDIVDrvl_v:
    case VE::VFDIVSiv:
    case VE::VFDIVSivL:
    case VE::VFDIVSivL_v:
    case VE::VFDIVSiv_v:
    case VE::VFDIVSivl:
    case VE::VFDIVSivl_v:
    case VE::VFDIVSrv:
    case VE::VFDIVSrvL:
    case VE::VFDIVSrvL_v:
    case VE::VFDIVSrv_v:
    case VE::VFDIVSrvl:
    case VE::VFDIVSrvl_v:
    case VE::VFMAXDiv:
    case VE::VFMAXDivL:
    case VE::VFMAXDivL_v:
    case VE::VFMAXDiv_v:
    case VE::VFMAXDivl:
    case VE::VFMAXDivl_v:
    case VE::VFMAXDrv:
    case VE::VFMAXDrvL:
    case VE::VFMAXDrvL_v:
    case VE::VFMAXDrv_v:
    case VE::VFMAXDrvl:
    case VE::VFMAXDrvl_v:
    case VE::VFMAXSiv:
    case VE::VFMAXSivL:
    case VE::VFMAXSivL_v:
    case VE::VFMAXSiv_v:
    case VE::VFMAXSivl:
    case VE::VFMAXSivl_v:
    case VE::VFMAXSrv:
    case VE::VFMAXSrvL:
    case VE::VFMAXSrvL_v:
    case VE::VFMAXSrv_v:
    case VE::VFMAXSrvl:
    case VE::VFMAXSrvl_v:
    case VE::VFMINDiv:
    case VE::VFMINDivL:
    case VE::VFMINDivL_v:
    case VE::VFMINDiv_v:
    case VE::VFMINDivl:
    case VE::VFMINDivl_v:
    case VE::VFMINDrv:
    case VE::VFMINDrvL:
    case VE::VFMINDrvL_v:
    case VE::VFMINDrv_v:
    case VE::VFMINDrvl:
    case VE::VFMINDrvl_v:
    case VE::VFMINSiv:
    case VE::VFMINSivL:
    case VE::VFMINSivL_v:
    case VE::VFMINSiv_v:
    case VE::VFMINSivl:
    case VE::VFMINSivl_v:
    case VE::VFMINSrv:
    case VE::VFMINSrvL:
    case VE::VFMINSrvL_v:
    case VE::VFMINSrv_v:
    case VE::VFMINSrvl:
    case VE::VFMINSrvl_v:
    case VE::VFMULDiv:
    case VE::VFMULDivL:
    case VE::VFMULDivL_v:
    case VE::VFMULDiv_v:
    case VE::VFMULDivl:
    case VE::VFMULDivl_v:
    case VE::VFMULDrv:
    case VE::VFMULDrvL:
    case VE::VFMULDrvL_v:
    case VE::VFMULDrv_v:
    case VE::VFMULDrvl:
    case VE::VFMULDrvl_v:
    case VE::VFMULSiv:
    case VE::VFMULSivL:
    case VE::VFMULSivL_v:
    case VE::VFMULSiv_v:
    case VE::VFMULSivl:
    case VE::VFMULSivl_v:
    case VE::VFMULSrv:
    case VE::VFMULSrvL:
    case VE::VFMULSrvL_v:
    case VE::VFMULSrv_v:
    case VE::VFMULSrvl:
    case VE::VFMULSrvl_v:
    case VE::VFSUBDiv:
    case VE::VFSUBDivL:
    case VE::VFSUBDivL_v:
    case VE::VFSUBDiv_v:
    case VE::VFSUBDivl:
    case VE::VFSUBDivl_v:
    case VE::VFSUBDrv:
    case VE::VFSUBDrvL:
    case VE::VFSUBDrvL_v:
    case VE::VFSUBDrv_v:
    case VE::VFSUBDrvl:
    case VE::VFSUBDrvl_v:
    case VE::VFSUBSiv:
    case VE::VFSUBSivL:
    case VE::VFSUBSivL_v:
    case VE::VFSUBSiv_v:
    case VE::VFSUBSivl:
    case VE::VFSUBSivl_v:
    case VE::VFSUBSrv:
    case VE::VFSUBSrvL:
    case VE::VFSUBSrvL_v:
    case VE::VFSUBSrv_v:
    case VE::VFSUBSrvl:
    case VE::VFSUBSrvl_v:
    case VE::VMAXSLiv:
    case VE::VMAXSLivL:
    case VE::VMAXSLivL_v:
    case VE::VMAXSLiv_v:
    case VE::VMAXSLivl:
    case VE::VMAXSLivl_v:
    case VE::VMAXSLrv:
    case VE::VMAXSLrvL:
    case VE::VMAXSLrvL_v:
    case VE::VMAXSLrv_v:
    case VE::VMAXSLrvl:
    case VE::VMAXSLrvl_v:
    case VE::VMAXSWSXiv:
    case VE::VMAXSWSXivL:
    case VE::VMAXSWSXivL_v:
    case VE::VMAXSWSXiv_v:
    case VE::VMAXSWSXivl:
    case VE::VMAXSWSXivl_v:
    case VE::VMAXSWSXrv:
    case VE::VMAXSWSXrvL:
    case VE::VMAXSWSXrvL_v:
    case VE::VMAXSWSXrv_v:
    case VE::VMAXSWSXrvl:
    case VE::VMAXSWSXrvl_v:
    case VE::VMAXSWZXiv:
    case VE::VMAXSWZXivL:
    case VE::VMAXSWZXivL_v:
    case VE::VMAXSWZXiv_v:
    case VE::VMAXSWZXivl:
    case VE::VMAXSWZXivl_v:
    case VE::VMAXSWZXrv:
    case VE::VMAXSWZXrvL:
    case VE::VMAXSWZXrvL_v:
    case VE::VMAXSWZXrv_v:
    case VE::VMAXSWZXrvl:
    case VE::VMAXSWZXrvl_v:
    case VE::VMINSLiv:
    case VE::VMINSLivL:
    case VE::VMINSLivL_v:
    case VE::VMINSLiv_v:
    case VE::VMINSLivl:
    case VE::VMINSLivl_v:
    case VE::VMINSLrv:
    case VE::VMINSLrvL:
    case VE::VMINSLrvL_v:
    case VE::VMINSLrv_v:
    case VE::VMINSLrvl:
    case VE::VMINSLrvl_v:
    case VE::VMINSWSXiv:
    case VE::VMINSWSXivL:
    case VE::VMINSWSXivL_v:
    case VE::VMINSWSXiv_v:
    case VE::VMINSWSXivl:
    case VE::VMINSWSXivl_v:
    case VE::VMINSWSXrv:
    case VE::VMINSWSXrvL:
    case VE::VMINSWSXrvL_v:
    case VE::VMINSWSXrv_v:
    case VE::VMINSWSXrvl:
    case VE::VMINSWSXrvl_v:
    case VE::VMINSWZXiv:
    case VE::VMINSWZXivL:
    case VE::VMINSWZXivL_v:
    case VE::VMINSWZXiv_v:
    case VE::VMINSWZXivl:
    case VE::VMINSWZXivl_v:
    case VE::VMINSWZXrv:
    case VE::VMINSWZXrvL:
    case VE::VMINSWZXrvL_v:
    case VE::VMINSWZXrv_v:
    case VE::VMINSWZXrvl:
    case VE::VMINSWZXrvl_v:
    case VE::VMRGWiv:
    case VE::VMRGWivL:
    case VE::VMRGWivL_v:
    case VE::VMRGWiv_v:
    case VE::VMRGWivl:
    case VE::VMRGWivl_v:
    case VE::VMRGWrv:
    case VE::VMRGWrvL:
    case VE::VMRGWrvL_v:
    case VE::VMRGWrv_v:
    case VE::VMRGWrvl:
    case VE::VMRGWrvl_v:
    case VE::VMRGiv:
    case VE::VMRGivL:
    case VE::VMRGivL_v:
    case VE::VMRGiv_v:
    case VE::VMRGivl:
    case VE::VMRGivl_v:
    case VE::VMRGrv:
    case VE::VMRGrvL:
    case VE::VMRGrvL_v:
    case VE::VMRGrv_v:
    case VE::VMRGrvl:
    case VE::VMRGrvl_v:
    case VE::VMULSLWiv:
    case VE::VMULSLWivL:
    case VE::VMULSLWivL_v:
    case VE::VMULSLWiv_v:
    case VE::VMULSLWivl:
    case VE::VMULSLWivl_v:
    case VE::VMULSLWrv:
    case VE::VMULSLWrvL:
    case VE::VMULSLWrvL_v:
    case VE::VMULSLWrv_v:
    case VE::VMULSLWrvl:
    case VE::VMULSLWrvl_v:
    case VE::VMULSLiv:
    case VE::VMULSLivL:
    case VE::VMULSLivL_v:
    case VE::VMULSLiv_v:
    case VE::VMULSLivl:
    case VE::VMULSLivl_v:
    case VE::VMULSLrv:
    case VE::VMULSLrvL:
    case VE::VMULSLrvL_v:
    case VE::VMULSLrv_v:
    case VE::VMULSLrvl:
    case VE::VMULSLrvl_v:
    case VE::VMULSWSXiv:
    case VE::VMULSWSXivL:
    case VE::VMULSWSXivL_v:
    case VE::VMULSWSXiv_v:
    case VE::VMULSWSXivl:
    case VE::VMULSWSXivl_v:
    case VE::VMULSWSXrv:
    case VE::VMULSWSXrvL:
    case VE::VMULSWSXrvL_v:
    case VE::VMULSWSXrv_v:
    case VE::VMULSWSXrvl:
    case VE::VMULSWSXrvl_v:
    case VE::VMULSWZXiv:
    case VE::VMULSWZXivL:
    case VE::VMULSWZXivL_v:
    case VE::VMULSWZXiv_v:
    case VE::VMULSWZXivl:
    case VE::VMULSWZXivl_v:
    case VE::VMULSWZXrv:
    case VE::VMULSWZXrvL:
    case VE::VMULSWZXrvL_v:
    case VE::VMULSWZXrv_v:
    case VE::VMULSWZXrvl:
    case VE::VMULSWZXrvl_v:
    case VE::VMULULiv:
    case VE::VMULULivL:
    case VE::VMULULivL_v:
    case VE::VMULULiv_v:
    case VE::VMULULivl:
    case VE::VMULULivl_v:
    case VE::VMULULrv:
    case VE::VMULULrvL:
    case VE::VMULULrvL_v:
    case VE::VMULULrv_v:
    case VE::VMULULrvl:
    case VE::VMULULrvl_v:
    case VE::VMULUWiv:
    case VE::VMULUWivL:
    case VE::VMULUWivL_v:
    case VE::VMULUWiv_v:
    case VE::VMULUWivl:
    case VE::VMULUWivl_v:
    case VE::VMULUWrv:
    case VE::VMULUWrvL:
    case VE::VMULUWrvL_v:
    case VE::VMULUWrv_v:
    case VE::VMULUWrvl:
    case VE::VMULUWrvl_v:
    case VE::VMViv:
    case VE::VMVivL:
    case VE::VMVivL_v:
    case VE::VMViv_v:
    case VE::VMVivl:
    case VE::VMVivl_v:
    case VE::VMVrv:
    case VE::VMVrvL:
    case VE::VMVrvL_v:
    case VE::VMVrv_v:
    case VE::VMVrvl:
    case VE::VMVrvl_v:
    case VE::VORmv:
    case VE::VORmvL:
    case VE::VORmvL_v:
    case VE::VORmv_v:
    case VE::VORmvl:
    case VE::VORmvl_v:
    case VE::VORrv:
    case VE::VORrvL:
    case VE::VORrvL_v:
    case VE::VORrv_v:
    case VE::VORrvl:
    case VE::VORrvl_v:
    case VE::VSUBSLiv:
    case VE::VSUBSLivL:
    case VE::VSUBSLivL_v:
    case VE::VSUBSLiv_v:
    case VE::VSUBSLivl:
    case VE::VSUBSLivl_v:
    case VE::VSUBSLrv:
    case VE::VSUBSLrvL:
    case VE::VSUBSLrvL_v:
    case VE::VSUBSLrv_v:
    case VE::VSUBSLrvl:
    case VE::VSUBSLrvl_v:
    case VE::VSUBSWSXiv:
    case VE::VSUBSWSXivL:
    case VE::VSUBSWSXivL_v:
    case VE::VSUBSWSXiv_v:
    case VE::VSUBSWSXivl:
    case VE::VSUBSWSXivl_v:
    case VE::VSUBSWSXrv:
    case VE::VSUBSWSXrvL:
    case VE::VSUBSWSXrvL_v:
    case VE::VSUBSWSXrv_v:
    case VE::VSUBSWSXrvl:
    case VE::VSUBSWSXrvl_v:
    case VE::VSUBSWZXiv:
    case VE::VSUBSWZXivL:
    case VE::VSUBSWZXivL_v:
    case VE::VSUBSWZXiv_v:
    case VE::VSUBSWZXivl:
    case VE::VSUBSWZXivl_v:
    case VE::VSUBSWZXrv:
    case VE::VSUBSWZXrvL:
    case VE::VSUBSWZXrvL_v:
    case VE::VSUBSWZXrv_v:
    case VE::VSUBSWZXrvl:
    case VE::VSUBSWZXrvl_v:
    case VE::VSUBULiv:
    case VE::VSUBULivL:
    case VE::VSUBULivL_v:
    case VE::VSUBULiv_v:
    case VE::VSUBULivl:
    case VE::VSUBULivl_v:
    case VE::VSUBULrv:
    case VE::VSUBULrvL:
    case VE::VSUBULrvL_v:
    case VE::VSUBULrv_v:
    case VE::VSUBULrvl:
    case VE::VSUBULrvl_v:
    case VE::VSUBUWiv:
    case VE::VSUBUWivL:
    case VE::VSUBUWivL_v:
    case VE::VSUBUWiv_v:
    case VE::VSUBUWivl:
    case VE::VSUBUWivl_v:
    case VE::VSUBUWrv:
    case VE::VSUBUWrvL:
    case VE::VSUBUWrvL_v:
    case VE::VSUBUWrv_v:
    case VE::VSUBUWrvl:
    case VE::VSUBUWrvl_v:
    case VE::VXORmv:
    case VE::VXORmvL:
    case VE::VXORmvL_v:
    case VE::VXORmv_v:
    case VE::VXORmvl:
    case VE::VXORmvl_v:
    case VE::VXORrv:
    case VE::VXORrvL:
    case VE::VXORrvL_v:
    case VE::VXORrv_v:
    case VE::VXORrvl:
    case VE::VXORrvl_v: {
      switch (OpNum) {
      case 1:
        // op: sy
        return 40;
      case 0:
        // op: vx
        return 24;
      case 2:
        // op: vz
        return 8;
      }
      break;
    }
    case VE::PVBRDi:
    case VE::PVBRDiL:
    case VE::PVBRDiL_v:
    case VE::PVBRDi_v:
    case VE::PVBRDil:
    case VE::PVBRDil_v:
    case VE::PVBRDr:
    case VE::PVBRDrL:
    case VE::PVBRDrL_v:
    case VE::PVBRDr_v:
    case VE::PVBRDrl:
    case VE::PVBRDrl_v:
    case VE::VBRDLi:
    case VE::VBRDLiL:
    case VE::VBRDLiL_v:
    case VE::VBRDLi_v:
    case VE::VBRDLil:
    case VE::VBRDLil_v:
    case VE::VBRDLr:
    case VE::VBRDLrL:
    case VE::VBRDLrL_v:
    case VE::VBRDLr_v:
    case VE::VBRDLrl:
    case VE::VBRDLrl_v:
    case VE::VBRDUi:
    case VE::VBRDUiL:
    case VE::VBRDUiL_v:
    case VE::VBRDUi_v:
    case VE::VBRDUil:
    case VE::VBRDUil_v:
    case VE::VBRDUr:
    case VE::VBRDUrL:
    case VE::VBRDUrL_v:
    case VE::VBRDUr_v:
    case VE::VBRDUrl:
    case VE::VBRDUrl_v:
    case VE::VBRDi:
    case VE::VBRDiL:
    case VE::VBRDiL_v:
    case VE::VBRDi_v:
    case VE::VBRDil:
    case VE::VBRDil_v:
    case VE::VBRDr:
    case VE::VBRDrL:
    case VE::VBRDrL_v:
    case VE::VBRDr_v:
    case VE::VBRDrl:
    case VE::VBRDrl_v: {
      switch (OpNum) {
      case 1:
        // op: sy
        return 40;
      case 0:
        // op: vx
        return 24;
      }
      break;
    }
    case VE::LSVim:
    case VE::LSVim_v:
    case VE::LSVir:
    case VE::LSVir_v:
    case VE::LSVrm:
    case VE::LSVrm_v:
    case VE::LSVrr:
    case VE::LSVrr_v:
    case VE::LVMim:
    case VE::LVMim_m:
    case VE::LVMir:
    case VE::LVMir_m:
    case VE::LVMrm:
    case VE::LVMrm_m:
    case VE::LVMrr:
    case VE::LVMrr_m:
    case VE::VLD2DNCir:
    case VE::VLD2DNCirL:
    case VE::VLD2DNCirL_v:
    case VE::VLD2DNCir_v:
    case VE::VLD2DNCirl:
    case VE::VLD2DNCirl_v:
    case VE::VLD2DNCiz:
    case VE::VLD2DNCizL:
    case VE::VLD2DNCizL_v:
    case VE::VLD2DNCiz_v:
    case VE::VLD2DNCizl:
    case VE::VLD2DNCizl_v:
    case VE::VLD2DNCrr:
    case VE::VLD2DNCrrL:
    case VE::VLD2DNCrrL_v:
    case VE::VLD2DNCrr_v:
    case VE::VLD2DNCrrl:
    case VE::VLD2DNCrrl_v:
    case VE::VLD2DNCrz:
    case VE::VLD2DNCrzL:
    case VE::VLD2DNCrzL_v:
    case VE::VLD2DNCrz_v:
    case VE::VLD2DNCrzl:
    case VE::VLD2DNCrzl_v:
    case VE::VLD2Dir:
    case VE::VLD2DirL:
    case VE::VLD2DirL_v:
    case VE::VLD2Dir_v:
    case VE::VLD2Dirl:
    case VE::VLD2Dirl_v:
    case VE::VLD2Diz:
    case VE::VLD2DizL:
    case VE::VLD2DizL_v:
    case VE::VLD2Diz_v:
    case VE::VLD2Dizl:
    case VE::VLD2Dizl_v:
    case VE::VLD2Drr:
    case VE::VLD2DrrL:
    case VE::VLD2DrrL_v:
    case VE::VLD2Drr_v:
    case VE::VLD2Drrl:
    case VE::VLD2Drrl_v:
    case VE::VLD2Drz:
    case VE::VLD2DrzL:
    case VE::VLD2DrzL_v:
    case VE::VLD2Drz_v:
    case VE::VLD2Drzl:
    case VE::VLD2Drzl_v:
    case VE::VLDL2DSXNCir:
    case VE::VLDL2DSXNCirL:
    case VE::VLDL2DSXNCirL_v:
    case VE::VLDL2DSXNCir_v:
    case VE::VLDL2DSXNCirl:
    case VE::VLDL2DSXNCirl_v:
    case VE::VLDL2DSXNCiz:
    case VE::VLDL2DSXNCizL:
    case VE::VLDL2DSXNCizL_v:
    case VE::VLDL2DSXNCiz_v:
    case VE::VLDL2DSXNCizl:
    case VE::VLDL2DSXNCizl_v:
    case VE::VLDL2DSXNCrr:
    case VE::VLDL2DSXNCrrL:
    case VE::VLDL2DSXNCrrL_v:
    case VE::VLDL2DSXNCrr_v:
    case VE::VLDL2DSXNCrrl:
    case VE::VLDL2DSXNCrrl_v:
    case VE::VLDL2DSXNCrz:
    case VE::VLDL2DSXNCrzL:
    case VE::VLDL2DSXNCrzL_v:
    case VE::VLDL2DSXNCrz_v:
    case VE::VLDL2DSXNCrzl:
    case VE::VLDL2DSXNCrzl_v:
    case VE::VLDL2DSXir:
    case VE::VLDL2DSXirL:
    case VE::VLDL2DSXirL_v:
    case VE::VLDL2DSXir_v:
    case VE::VLDL2DSXirl:
    case VE::VLDL2DSXirl_v:
    case VE::VLDL2DSXiz:
    case VE::VLDL2DSXizL:
    case VE::VLDL2DSXizL_v:
    case VE::VLDL2DSXiz_v:
    case VE::VLDL2DSXizl:
    case VE::VLDL2DSXizl_v:
    case VE::VLDL2DSXrr:
    case VE::VLDL2DSXrrL:
    case VE::VLDL2DSXrrL_v:
    case VE::VLDL2DSXrr_v:
    case VE::VLDL2DSXrrl:
    case VE::VLDL2DSXrrl_v:
    case VE::VLDL2DSXrz:
    case VE::VLDL2DSXrzL:
    case VE::VLDL2DSXrzL_v:
    case VE::VLDL2DSXrz_v:
    case VE::VLDL2DSXrzl:
    case VE::VLDL2DSXrzl_v:
    case VE::VLDL2DZXNCir:
    case VE::VLDL2DZXNCirL:
    case VE::VLDL2DZXNCirL_v:
    case VE::VLDL2DZXNCir_v:
    case VE::VLDL2DZXNCirl:
    case VE::VLDL2DZXNCirl_v:
    case VE::VLDL2DZXNCiz:
    case VE::VLDL2DZXNCizL:
    case VE::VLDL2DZXNCizL_v:
    case VE::VLDL2DZXNCiz_v:
    case VE::VLDL2DZXNCizl:
    case VE::VLDL2DZXNCizl_v:
    case VE::VLDL2DZXNCrr:
    case VE::VLDL2DZXNCrrL:
    case VE::VLDL2DZXNCrrL_v:
    case VE::VLDL2DZXNCrr_v:
    case VE::VLDL2DZXNCrrl:
    case VE::VLDL2DZXNCrrl_v:
    case VE::VLDL2DZXNCrz:
    case VE::VLDL2DZXNCrzL:
    case VE::VLDL2DZXNCrzL_v:
    case VE::VLDL2DZXNCrz_v:
    case VE::VLDL2DZXNCrzl:
    case VE::VLDL2DZXNCrzl_v:
    case VE::VLDL2DZXir:
    case VE::VLDL2DZXirL:
    case VE::VLDL2DZXirL_v:
    case VE::VLDL2DZXir_v:
    case VE::VLDL2DZXirl:
    case VE::VLDL2DZXirl_v:
    case VE::VLDL2DZXiz:
    case VE::VLDL2DZXizL:
    case VE::VLDL2DZXizL_v:
    case VE::VLDL2DZXiz_v:
    case VE::VLDL2DZXizl:
    case VE::VLDL2DZXizl_v:
    case VE::VLDL2DZXrr:
    case VE::VLDL2DZXrrL:
    case VE::VLDL2DZXrrL_v:
    case VE::VLDL2DZXrr_v:
    case VE::VLDL2DZXrrl:
    case VE::VLDL2DZXrrl_v:
    case VE::VLDL2DZXrz:
    case VE::VLDL2DZXrzL:
    case VE::VLDL2DZXrzL_v:
    case VE::VLDL2DZXrz_v:
    case VE::VLDL2DZXrzl:
    case VE::VLDL2DZXrzl_v:
    case VE::VLDLSXNCir:
    case VE::VLDLSXNCirL:
    case VE::VLDLSXNCirL_v:
    case VE::VLDLSXNCir_v:
    case VE::VLDLSXNCirl:
    case VE::VLDLSXNCirl_v:
    case VE::VLDLSXNCiz:
    case VE::VLDLSXNCizL:
    case VE::VLDLSXNCizL_v:
    case VE::VLDLSXNCiz_v:
    case VE::VLDLSXNCizl:
    case VE::VLDLSXNCizl_v:
    case VE::VLDLSXNCrr:
    case VE::VLDLSXNCrrL:
    case VE::VLDLSXNCrrL_v:
    case VE::VLDLSXNCrr_v:
    case VE::VLDLSXNCrrl:
    case VE::VLDLSXNCrrl_v:
    case VE::VLDLSXNCrz:
    case VE::VLDLSXNCrzL:
    case VE::VLDLSXNCrzL_v:
    case VE::VLDLSXNCrz_v:
    case VE::VLDLSXNCrzl:
    case VE::VLDLSXNCrzl_v:
    case VE::VLDLSXir:
    case VE::VLDLSXirL:
    case VE::VLDLSXirL_v:
    case VE::VLDLSXir_v:
    case VE::VLDLSXirl:
    case VE::VLDLSXirl_v:
    case VE::VLDLSXiz:
    case VE::VLDLSXizL:
    case VE::VLDLSXizL_v:
    case VE::VLDLSXiz_v:
    case VE::VLDLSXizl:
    case VE::VLDLSXizl_v:
    case VE::VLDLSXrr:
    case VE::VLDLSXrrL:
    case VE::VLDLSXrrL_v:
    case VE::VLDLSXrr_v:
    case VE::VLDLSXrrl:
    case VE::VLDLSXrrl_v:
    case VE::VLDLSXrz:
    case VE::VLDLSXrzL:
    case VE::VLDLSXrzL_v:
    case VE::VLDLSXrz_v:
    case VE::VLDLSXrzl:
    case VE::VLDLSXrzl_v:
    case VE::VLDLZXNCir:
    case VE::VLDLZXNCirL:
    case VE::VLDLZXNCirL_v:
    case VE::VLDLZXNCir_v:
    case VE::VLDLZXNCirl:
    case VE::VLDLZXNCirl_v:
    case VE::VLDLZXNCiz:
    case VE::VLDLZXNCizL:
    case VE::VLDLZXNCizL_v:
    case VE::VLDLZXNCiz_v:
    case VE::VLDLZXNCizl:
    case VE::VLDLZXNCizl_v:
    case VE::VLDLZXNCrr:
    case VE::VLDLZXNCrrL:
    case VE::VLDLZXNCrrL_v:
    case VE::VLDLZXNCrr_v:
    case VE::VLDLZXNCrrl:
    case VE::VLDLZXNCrrl_v:
    case VE::VLDLZXNCrz:
    case VE::VLDLZXNCrzL:
    case VE::VLDLZXNCrzL_v:
    case VE::VLDLZXNCrz_v:
    case VE::VLDLZXNCrzl:
    case VE::VLDLZXNCrzl_v:
    case VE::VLDLZXir:
    case VE::VLDLZXirL:
    case VE::VLDLZXirL_v:
    case VE::VLDLZXir_v:
    case VE::VLDLZXirl:
    case VE::VLDLZXirl_v:
    case VE::VLDLZXiz:
    case VE::VLDLZXizL:
    case VE::VLDLZXizL_v:
    case VE::VLDLZXiz_v:
    case VE::VLDLZXizl:
    case VE::VLDLZXizl_v:
    case VE::VLDLZXrr:
    case VE::VLDLZXrrL:
    case VE::VLDLZXrrL_v:
    case VE::VLDLZXrr_v:
    case VE::VLDLZXrrl:
    case VE::VLDLZXrrl_v:
    case VE::VLDLZXrz:
    case VE::VLDLZXrzL:
    case VE::VLDLZXrzL_v:
    case VE::VLDLZXrz_v:
    case VE::VLDLZXrzl:
    case VE::VLDLZXrzl_v:
    case VE::VLDNCir:
    case VE::VLDNCirL:
    case VE::VLDNCirL_v:
    case VE::VLDNCir_v:
    case VE::VLDNCirl:
    case VE::VLDNCirl_v:
    case VE::VLDNCiz:
    case VE::VLDNCizL:
    case VE::VLDNCizL_v:
    case VE::VLDNCiz_v:
    case VE::VLDNCizl:
    case VE::VLDNCizl_v:
    case VE::VLDNCrr:
    case VE::VLDNCrrL:
    case VE::VLDNCrrL_v:
    case VE::VLDNCrr_v:
    case VE::VLDNCrrl:
    case VE::VLDNCrrl_v:
    case VE::VLDNCrz:
    case VE::VLDNCrzL:
    case VE::VLDNCrzL_v:
    case VE::VLDNCrz_v:
    case VE::VLDNCrzl:
    case VE::VLDNCrzl_v:
    case VE::VLDU2DNCir:
    case VE::VLDU2DNCirL:
    case VE::VLDU2DNCirL_v:
    case VE::VLDU2DNCir_v:
    case VE::VLDU2DNCirl:
    case VE::VLDU2DNCirl_v:
    case VE::VLDU2DNCiz:
    case VE::VLDU2DNCizL:
    case VE::VLDU2DNCizL_v:
    case VE::VLDU2DNCiz_v:
    case VE::VLDU2DNCizl:
    case VE::VLDU2DNCizl_v:
    case VE::VLDU2DNCrr:
    case VE::VLDU2DNCrrL:
    case VE::VLDU2DNCrrL_v:
    case VE::VLDU2DNCrr_v:
    case VE::VLDU2DNCrrl:
    case VE::VLDU2DNCrrl_v:
    case VE::VLDU2DNCrz:
    case VE::VLDU2DNCrzL:
    case VE::VLDU2DNCrzL_v:
    case VE::VLDU2DNCrz_v:
    case VE::VLDU2DNCrzl:
    case VE::VLDU2DNCrzl_v:
    case VE::VLDU2Dir:
    case VE::VLDU2DirL:
    case VE::VLDU2DirL_v:
    case VE::VLDU2Dir_v:
    case VE::VLDU2Dirl:
    case VE::VLDU2Dirl_v:
    case VE::VLDU2Diz:
    case VE::VLDU2DizL:
    case VE::VLDU2DizL_v:
    case VE::VLDU2Diz_v:
    case VE::VLDU2Dizl:
    case VE::VLDU2Dizl_v:
    case VE::VLDU2Drr:
    case VE::VLDU2DrrL:
    case VE::VLDU2DrrL_v:
    case VE::VLDU2Drr_v:
    case VE::VLDU2Drrl:
    case VE::VLDU2Drrl_v:
    case VE::VLDU2Drz:
    case VE::VLDU2DrzL:
    case VE::VLDU2DrzL_v:
    case VE::VLDU2Drz_v:
    case VE::VLDU2Drzl:
    case VE::VLDU2Drzl_v:
    case VE::VLDUNCir:
    case VE::VLDUNCirL:
    case VE::VLDUNCirL_v:
    case VE::VLDUNCir_v:
    case VE::VLDUNCirl:
    case VE::VLDUNCirl_v:
    case VE::VLDUNCiz:
    case VE::VLDUNCizL:
    case VE::VLDUNCizL_v:
    case VE::VLDUNCiz_v:
    case VE::VLDUNCizl:
    case VE::VLDUNCizl_v:
    case VE::VLDUNCrr:
    case VE::VLDUNCrrL:
    case VE::VLDUNCrrL_v:
    case VE::VLDUNCrr_v:
    case VE::VLDUNCrrl:
    case VE::VLDUNCrrl_v:
    case VE::VLDUNCrz:
    case VE::VLDUNCrzL:
    case VE::VLDUNCrzL_v:
    case VE::VLDUNCrz_v:
    case VE::VLDUNCrzl:
    case VE::VLDUNCrzl_v:
    case VE::VLDUir:
    case VE::VLDUirL:
    case VE::VLDUirL_v:
    case VE::VLDUir_v:
    case VE::VLDUirl:
    case VE::VLDUirl_v:
    case VE::VLDUiz:
    case VE::VLDUizL:
    case VE::VLDUizL_v:
    case VE::VLDUiz_v:
    case VE::VLDUizl:
    case VE::VLDUizl_v:
    case VE::VLDUrr:
    case VE::VLDUrrL:
    case VE::VLDUrrL_v:
    case VE::VLDUrr_v:
    case VE::VLDUrrl:
    case VE::VLDUrrl_v:
    case VE::VLDUrz:
    case VE::VLDUrzL:
    case VE::VLDUrzL_v:
    case VE::VLDUrz_v:
    case VE::VLDUrzl:
    case VE::VLDUrzl_v:
    case VE::VLDir:
    case VE::VLDirL:
    case VE::VLDirL_v:
    case VE::VLDir_v:
    case VE::VLDirl:
    case VE::VLDirl_v:
    case VE::VLDiz:
    case VE::VLDizL:
    case VE::VLDizL_v:
    case VE::VLDiz_v:
    case VE::VLDizl:
    case VE::VLDizl_v:
    case VE::VLDrr:
    case VE::VLDrrL:
    case VE::VLDrrL_v:
    case VE::VLDrr_v:
    case VE::VLDrrl:
    case VE::VLDrrl_v:
    case VE::VLDrz:
    case VE::VLDrzL:
    case VE::VLDrzL_v:
    case VE::VLDrz_v:
    case VE::VLDrzl:
    case VE::VLDrzl_v: {
      switch (OpNum) {
      case 1:
        // op: sy
        return 40;
      case 2:
        // op: sz
        return 32;
      case 0:
        // op: vx
        return 24;
      }
      break;
    }
    case VE::VSCLNCOTsirv:
    case VE::VSCLNCOTsirvL:
    case VE::VSCLNCOTsirvl:
    case VE::VSCLNCOTsizv:
    case VE::VSCLNCOTsizvL:
    case VE::VSCLNCOTsizvl:
    case VE::VSCLNCOTsrrv:
    case VE::VSCLNCOTsrrvL:
    case VE::VSCLNCOTsrrvl:
    case VE::VSCLNCOTsrzv:
    case VE::VSCLNCOTsrzvL:
    case VE::VSCLNCOTsrzvl:
    case VE::VSCLNCsirv:
    case VE::VSCLNCsirvL:
    case VE::VSCLNCsirvl:
    case VE::VSCLNCsizv:
    case VE::VSCLNCsizvL:
    case VE::VSCLNCsizvl:
    case VE::VSCLNCsrrv:
    case VE::VSCLNCsrrvL:
    case VE::VSCLNCsrrvl:
    case VE::VSCLNCsrzv:
    case VE::VSCLNCsrzvL:
    case VE::VSCLNCsrzvl:
    case VE::VSCLOTsirv:
    case VE::VSCLOTsirvL:
    case VE::VSCLOTsirvl:
    case VE::VSCLOTsizv:
    case VE::VSCLOTsizvL:
    case VE::VSCLOTsizvl:
    case VE::VSCLOTsrrv:
    case VE::VSCLOTsrrvL:
    case VE::VSCLOTsrrvl:
    case VE::VSCLOTsrzv:
    case VE::VSCLOTsrzvL:
    case VE::VSCLOTsrzvl:
    case VE::VSCLsirv:
    case VE::VSCLsirvL:
    case VE::VSCLsirvl:
    case VE::VSCLsizv:
    case VE::VSCLsizvL:
    case VE::VSCLsizvl:
    case VE::VSCLsrrv:
    case VE::VSCLsrrvL:
    case VE::VSCLsrrvl:
    case VE::VSCLsrzv:
    case VE::VSCLsrzvL:
    case VE::VSCLsrzvl:
    case VE::VSCNCOTsirv:
    case VE::VSCNCOTsirvL:
    case VE::VSCNCOTsirvl:
    case VE::VSCNCOTsizv:
    case VE::VSCNCOTsizvL:
    case VE::VSCNCOTsizvl:
    case VE::VSCNCOTsrrv:
    case VE::VSCNCOTsrrvL:
    case VE::VSCNCOTsrrvl:
    case VE::VSCNCOTsrzv:
    case VE::VSCNCOTsrzvL:
    case VE::VSCNCOTsrzvl:
    case VE::VSCNCsirv:
    case VE::VSCNCsirvL:
    case VE::VSCNCsirvl:
    case VE::VSCNCsizv:
    case VE::VSCNCsizvL:
    case VE::VSCNCsizvl:
    case VE::VSCNCsrrv:
    case VE::VSCNCsrrvL:
    case VE::VSCNCsrrvl:
    case VE::VSCNCsrzv:
    case VE::VSCNCsrzvL:
    case VE::VSCNCsrzvl:
    case VE::VSCOTsirv:
    case VE::VSCOTsirvL:
    case VE::VSCOTsirvl:
    case VE::VSCOTsizv:
    case VE::VSCOTsizvL:
    case VE::VSCOTsizvl:
    case VE::VSCOTsrrv:
    case VE::VSCOTsrrvL:
    case VE::VSCOTsrrvl:
    case VE::VSCOTsrzv:
    case VE::VSCOTsrzvL:
    case VE::VSCOTsrzvl:
    case VE::VSCUNCOTsirv:
    case VE::VSCUNCOTsirvL:
    case VE::VSCUNCOTsirvl:
    case VE::VSCUNCOTsizv:
    case VE::VSCUNCOTsizvL:
    case VE::VSCUNCOTsizvl:
    case VE::VSCUNCOTsrrv:
    case VE::VSCUNCOTsrrvL:
    case VE::VSCUNCOTsrrvl:
    case VE::VSCUNCOTsrzv:
    case VE::VSCUNCOTsrzvL:
    case VE::VSCUNCOTsrzvl:
    case VE::VSCUNCsirv:
    case VE::VSCUNCsirvL:
    case VE::VSCUNCsirvl:
    case VE::VSCUNCsizv:
    case VE::VSCUNCsizvL:
    case VE::VSCUNCsizvl:
    case VE::VSCUNCsrrv:
    case VE::VSCUNCsrrvL:
    case VE::VSCUNCsrrvl:
    case VE::VSCUNCsrzv:
    case VE::VSCUNCsrzvL:
    case VE::VSCUNCsrzvl:
    case VE::VSCUOTsirv:
    case VE::VSCUOTsirvL:
    case VE::VSCUOTsirvl:
    case VE::VSCUOTsizv:
    case VE::VSCUOTsizvL:
    case VE::VSCUOTsizvl:
    case VE::VSCUOTsrrv:
    case VE::VSCUOTsrrvL:
    case VE::VSCUOTsrrvl:
    case VE::VSCUOTsrzv:
    case VE::VSCUOTsrzvL:
    case VE::VSCUOTsrzvl:
    case VE::VSCUsirv:
    case VE::VSCUsirvL:
    case VE::VSCUsirvl:
    case VE::VSCUsizv:
    case VE::VSCUsizvL:
    case VE::VSCUsizvl:
    case VE::VSCUsrrv:
    case VE::VSCUsrrvL:
    case VE::VSCUsrrvl:
    case VE::VSCUsrzv:
    case VE::VSCUsrzvL:
    case VE::VSCUsrzvl:
    case VE::VSCsirv:
    case VE::VSCsirvL:
    case VE::VSCsirvl:
    case VE::VSCsizv:
    case VE::VSCsizvL:
    case VE::VSCsizvl:
    case VE::VSCsrrv:
    case VE::VSCsrrvL:
    case VE::VSCsrrvl:
    case VE::VSCsrzv:
    case VE::VSCsrzvL:
    case VE::VSCsrzvl: {
      switch (OpNum) {
      case 1:
        // op: sy
        return 40;
      case 2:
        // op: sz
        return 32;
      case 3:
        // op: vx
        return 24;
      case 0:
        // op: sw
        return 0;
      }
      break;
    }
    case VE::VSCLNCOTvirv:
    case VE::VSCLNCOTvirvL:
    case VE::VSCLNCOTvirvl:
    case VE::VSCLNCOTvizv:
    case VE::VSCLNCOTvizvL:
    case VE::VSCLNCOTvizvl:
    case VE::VSCLNCOTvrrv:
    case VE::VSCLNCOTvrrvL:
    case VE::VSCLNCOTvrrvl:
    case VE::VSCLNCOTvrzv:
    case VE::VSCLNCOTvrzvL:
    case VE::VSCLNCOTvrzvl:
    case VE::VSCLNCvirv:
    case VE::VSCLNCvirvL:
    case VE::VSCLNCvirvl:
    case VE::VSCLNCvizv:
    case VE::VSCLNCvizvL:
    case VE::VSCLNCvizvl:
    case VE::VSCLNCvrrv:
    case VE::VSCLNCvrrvL:
    case VE::VSCLNCvrrvl:
    case VE::VSCLNCvrzv:
    case VE::VSCLNCvrzvL:
    case VE::VSCLNCvrzvl:
    case VE::VSCLOTvirv:
    case VE::VSCLOTvirvL:
    case VE::VSCLOTvirvl:
    case VE::VSCLOTvizv:
    case VE::VSCLOTvizvL:
    case VE::VSCLOTvizvl:
    case VE::VSCLOTvrrv:
    case VE::VSCLOTvrrvL:
    case VE::VSCLOTvrrvl:
    case VE::VSCLOTvrzv:
    case VE::VSCLOTvrzvL:
    case VE::VSCLOTvrzvl:
    case VE::VSCLvirv:
    case VE::VSCLvirvL:
    case VE::VSCLvirvl:
    case VE::VSCLvizv:
    case VE::VSCLvizvL:
    case VE::VSCLvizvl:
    case VE::VSCLvrrv:
    case VE::VSCLvrrvL:
    case VE::VSCLvrrvl:
    case VE::VSCLvrzv:
    case VE::VSCLvrzvL:
    case VE::VSCLvrzvl:
    case VE::VSCNCOTvirv:
    case VE::VSCNCOTvirvL:
    case VE::VSCNCOTvirvl:
    case VE::VSCNCOTvizv:
    case VE::VSCNCOTvizvL:
    case VE::VSCNCOTvizvl:
    case VE::VSCNCOTvrrv:
    case VE::VSCNCOTvrrvL:
    case VE::VSCNCOTvrrvl:
    case VE::VSCNCOTvrzv:
    case VE::VSCNCOTvrzvL:
    case VE::VSCNCOTvrzvl:
    case VE::VSCNCvirv:
    case VE::VSCNCvirvL:
    case VE::VSCNCvirvl:
    case VE::VSCNCvizv:
    case VE::VSCNCvizvL:
    case VE::VSCNCvizvl:
    case VE::VSCNCvrrv:
    case VE::VSCNCvrrvL:
    case VE::VSCNCvrrvl:
    case VE::VSCNCvrzv:
    case VE::VSCNCvrzvL:
    case VE::VSCNCvrzvl:
    case VE::VSCOTvirv:
    case VE::VSCOTvirvL:
    case VE::VSCOTvirvl:
    case VE::VSCOTvizv:
    case VE::VSCOTvizvL:
    case VE::VSCOTvizvl:
    case VE::VSCOTvrrv:
    case VE::VSCOTvrrvL:
    case VE::VSCOTvrrvl:
    case VE::VSCOTvrzv:
    case VE::VSCOTvrzvL:
    case VE::VSCOTvrzvl:
    case VE::VSCUNCOTvirv:
    case VE::VSCUNCOTvirvL:
    case VE::VSCUNCOTvirvl:
    case VE::VSCUNCOTvizv:
    case VE::VSCUNCOTvizvL:
    case VE::VSCUNCOTvizvl:
    case VE::VSCUNCOTvrrv:
    case VE::VSCUNCOTvrrvL:
    case VE::VSCUNCOTvrrvl:
    case VE::VSCUNCOTvrzv:
    case VE::VSCUNCOTvrzvL:
    case VE::VSCUNCOTvrzvl:
    case VE::VSCUNCvirv:
    case VE::VSCUNCvirvL:
    case VE::VSCUNCvirvl:
    case VE::VSCUNCvizv:
    case VE::VSCUNCvizvL:
    case VE::VSCUNCvizvl:
    case VE::VSCUNCvrrv:
    case VE::VSCUNCvrrvL:
    case VE::VSCUNCvrrvl:
    case VE::VSCUNCvrzv:
    case VE::VSCUNCvrzvL:
    case VE::VSCUNCvrzvl:
    case VE::VSCUOTvirv:
    case VE::VSCUOTvirvL:
    case VE::VSCUOTvirvl:
    case VE::VSCUOTvizv:
    case VE::VSCUOTvizvL:
    case VE::VSCUOTvizvl:
    case VE::VSCUOTvrrv:
    case VE::VSCUOTvrrvL:
    case VE::VSCUOTvrrvl:
    case VE::VSCUOTvrzv:
    case VE::VSCUOTvrzvL:
    case VE::VSCUOTvrzvl:
    case VE::VSCUvirv:
    case VE::VSCUvirvL:
    case VE::VSCUvirvl:
    case VE::VSCUvizv:
    case VE::VSCUvizvL:
    case VE::VSCUvizvl:
    case VE::VSCUvrrv:
    case VE::VSCUvrrvL:
    case VE::VSCUvrrvl:
    case VE::VSCUvrzv:
    case VE::VSCUvrzvL:
    case VE::VSCUvrzvl:
    case VE::VSCvirv:
    case VE::VSCvirvL:
    case VE::VSCvirvl:
    case VE::VSCvizv:
    case VE::VSCvizvL:
    case VE::VSCvizvl:
    case VE::VSCvrrv:
    case VE::VSCvrrvL:
    case VE::VSCvrrvl:
    case VE::VSCvrzv:
    case VE::VSCvrzvL:
    case VE::VSCvrzvl: {
      switch (OpNum) {
      case 1:
        // op: sy
        return 40;
      case 2:
        // op: sz
        return 32;
      case 3:
        // op: vx
        return 24;
      case 0:
        // op: vy
        return 16;
      }
      break;
    }
    case VE::LZVMm:
    case VE::LZVMmL:
    case VE::LZVMml:
    case VE::PCVMm:
    case VE::PCVMmL:
    case VE::PCVMml:
    case VE::TOVMm:
    case VE::TOVMmL:
    case VE::TOVMml: {
      switch (OpNum) {
      case 1:
        // op: vy
        return 16;
      case 0:
        // op: sx
        return 48;
      }
      break;
    }
    case VE::PVCVTSWLOvm:
    case VE::PVCVTSWLOvmL:
    case VE::PVCVTSWLOvmL_v:
    case VE::PVCVTSWLOvm_v:
    case VE::PVCVTSWLOvml:
    case VE::PVCVTSWLOvml_v:
    case VE::PVCVTSWUPvm:
    case VE::PVCVTSWUPvmL:
    case VE::PVCVTSWUPvmL_v:
    case VE::PVCVTSWUPvm_v:
    case VE::PVCVTSWUPvml:
    case VE::PVCVTSWUPvml_v:
    case VE::PVCVTSWvm:
    case VE::PVCVTSWvmL:
    case VE::PVCVTSWvmL_v:
    case VE::PVCVTSWvm_v:
    case VE::PVCVTSWvml:
    case VE::PVCVTSWvml_v:
    case VE::PVRCPLOvm:
    case VE::PVRCPLOvmL:
    case VE::PVRCPLOvmL_v:
    case VE::PVRCPLOvm_v:
    case VE::PVRCPLOvml:
    case VE::PVRCPLOvml_v:
    case VE::PVRCPUPvm:
    case VE::PVRCPUPvmL:
    case VE::PVRCPUPvmL_v:
    case VE::PVRCPUPvm_v:
    case VE::PVRCPUPvml:
    case VE::PVRCPUPvml_v:
    case VE::PVRCPvm:
    case VE::PVRCPvmL:
    case VE::PVRCPvmL_v:
    case VE::PVRCPvm_v:
    case VE::PVRCPvml:
    case VE::PVRCPvml_v:
    case VE::PVRSQRTLONEXvm:
    case VE::PVRSQRTLONEXvmL:
    case VE::PVRSQRTLONEXvmL_v:
    case VE::PVRSQRTLONEXvm_v:
    case VE::PVRSQRTLONEXvml:
    case VE::PVRSQRTLONEXvml_v:
    case VE::PVRSQRTLOvm:
    case VE::PVRSQRTLOvmL:
    case VE::PVRSQRTLOvmL_v:
    case VE::PVRSQRTLOvm_v:
    case VE::PVRSQRTLOvml:
    case VE::PVRSQRTLOvml_v:
    case VE::PVRSQRTNEXvm:
    case VE::PVRSQRTNEXvmL:
    case VE::PVRSQRTNEXvmL_v:
    case VE::PVRSQRTNEXvm_v:
    case VE::PVRSQRTNEXvml:
    case VE::PVRSQRTNEXvml_v:
    case VE::PVRSQRTUPNEXvm:
    case VE::PVRSQRTUPNEXvmL:
    case VE::PVRSQRTUPNEXvmL_v:
    case VE::PVRSQRTUPNEXvm_v:
    case VE::PVRSQRTUPNEXvml:
    case VE::PVRSQRTUPNEXvml_v:
    case VE::PVRSQRTUPvm:
    case VE::PVRSQRTUPvmL:
    case VE::PVRSQRTUPvmL_v:
    case VE::PVRSQRTUPvm_v:
    case VE::PVRSQRTUPvml:
    case VE::PVRSQRTUPvml_v:
    case VE::PVRSQRTvm:
    case VE::PVRSQRTvmL:
    case VE::PVRSQRTvmL_v:
    case VE::PVRSQRTvm_v:
    case VE::PVRSQRTvml:
    case VE::PVRSQRTvml_v:
    case VE::VCVTDLvm:
    case VE::VCVTDLvmL:
    case VE::VCVTDLvmL_v:
    case VE::VCVTDLvm_v:
    case VE::VCVTDLvml:
    case VE::VCVTDLvml_v:
    case VE::VCVTDSvm:
    case VE::VCVTDSvmL:
    case VE::VCVTDSvmL_v:
    case VE::VCVTDSvm_v:
    case VE::VCVTDSvml:
    case VE::VCVTDSvml_v:
    case VE::VCVTDWvm:
    case VE::VCVTDWvmL:
    case VE::VCVTDWvmL_v:
    case VE::VCVTDWvm_v:
    case VE::VCVTDWvml:
    case VE::VCVTDWvml_v:
    case VE::VCVTSDvm:
    case VE::VCVTSDvmL:
    case VE::VCVTSDvmL_v:
    case VE::VCVTSDvm_v:
    case VE::VCVTSDvml:
    case VE::VCVTSDvml_v:
    case VE::VCVTSWvm:
    case VE::VCVTSWvmL:
    case VE::VCVTSWvmL_v:
    case VE::VCVTSWvm_v:
    case VE::VCVTSWvml:
    case VE::VCVTSWvml_v:
    case VE::VFRMAXDFSTvm:
    case VE::VFRMAXDFSTvmL:
    case VE::VFRMAXDFSTvmL_v:
    case VE::VFRMAXDFSTvm_v:
    case VE::VFRMAXDFSTvml:
    case VE::VFRMAXDFSTvml_v:
    case VE::VFRMAXDLSTvm:
    case VE::VFRMAXDLSTvmL:
    case VE::VFRMAXDLSTvmL_v:
    case VE::VFRMAXDLSTvm_v:
    case VE::VFRMAXDLSTvml:
    case VE::VFRMAXDLSTvml_v:
    case VE::VFRMAXSFSTvm:
    case VE::VFRMAXSFSTvmL:
    case VE::VFRMAXSFSTvmL_v:
    case VE::VFRMAXSFSTvm_v:
    case VE::VFRMAXSFSTvml:
    case VE::VFRMAXSFSTvml_v:
    case VE::VFRMAXSLSTvm:
    case VE::VFRMAXSLSTvmL:
    case VE::VFRMAXSLSTvmL_v:
    case VE::VFRMAXSLSTvm_v:
    case VE::VFRMAXSLSTvml:
    case VE::VFRMAXSLSTvml_v:
    case VE::VFRMINDFSTvm:
    case VE::VFRMINDFSTvmL:
    case VE::VFRMINDFSTvmL_v:
    case VE::VFRMINDFSTvm_v:
    case VE::VFRMINDFSTvml:
    case VE::VFRMINDFSTvml_v:
    case VE::VFRMINDLSTvm:
    case VE::VFRMINDLSTvmL:
    case VE::VFRMINDLSTvmL_v:
    case VE::VFRMINDLSTvm_v:
    case VE::VFRMINDLSTvml:
    case VE::VFRMINDLSTvml_v:
    case VE::VFRMINSFSTvm:
    case VE::VFRMINSFSTvmL:
    case VE::VFRMINSFSTvmL_v:
    case VE::VFRMINSFSTvm_v:
    case VE::VFRMINSFSTvml:
    case VE::VFRMINSFSTvml_v:
    case VE::VFRMINSLSTvm:
    case VE::VFRMINSLSTvmL:
    case VE::VFRMINSLSTvmL_v:
    case VE::VFRMINSLSTvm_v:
    case VE::VFRMINSLSTvml:
    case VE::VFRMINSLSTvml_v:
    case VE::VFSQRTDvm:
    case VE::VFSQRTDvmL:
    case VE::VFSQRTDvmL_v:
    case VE::VFSQRTDvm_v:
    case VE::VFSQRTDvml:
    case VE::VFSQRTDvml_v:
    case VE::VFSQRTSvm:
    case VE::VFSQRTSvmL:
    case VE::VFSQRTSvmL_v:
    case VE::VFSQRTSvm_v:
    case VE::VFSQRTSvml:
    case VE::VFSQRTSvml_v:
    case VE::VFSUMDvm:
    case VE::VFSUMDvmL:
    case VE::VFSUMDvmL_v:
    case VE::VFSUMDvm_v:
    case VE::VFSUMDvml:
    case VE::VFSUMDvml_v:
    case VE::VFSUMSvm:
    case VE::VFSUMSvmL:
    case VE::VFSUMSvmL_v:
    case VE::VFSUMSvm_v:
    case VE::VFSUMSvml:
    case VE::VFSUMSvml_v:
    case VE::VRANDvm:
    case VE::VRANDvmL:
    case VE::VRANDvmL_v:
    case VE::VRANDvm_v:
    case VE::VRANDvml:
    case VE::VRANDvml_v:
    case VE::VRCPDvm:
    case VE::VRCPDvmL:
    case VE::VRCPDvmL_v:
    case VE::VRCPDvm_v:
    case VE::VRCPDvml:
    case VE::VRCPDvml_v:
    case VE::VRCPSvm:
    case VE::VRCPSvmL:
    case VE::VRCPSvmL_v:
    case VE::VRCPSvm_v:
    case VE::VRCPSvml:
    case VE::VRCPSvml_v:
    case VE::VRMAXSLFSTvm:
    case VE::VRMAXSLFSTvmL:
    case VE::VRMAXSLFSTvmL_v:
    case VE::VRMAXSLFSTvm_v:
    case VE::VRMAXSLFSTvml:
    case VE::VRMAXSLFSTvml_v:
    case VE::VRMAXSLLSTvm:
    case VE::VRMAXSLLSTvmL:
    case VE::VRMAXSLLSTvmL_v:
    case VE::VRMAXSLLSTvm_v:
    case VE::VRMAXSLLSTvml:
    case VE::VRMAXSLLSTvml_v:
    case VE::VRMAXSWFSTSXvm:
    case VE::VRMAXSWFSTSXvmL:
    case VE::VRMAXSWFSTSXvmL_v:
    case VE::VRMAXSWFSTSXvm_v:
    case VE::VRMAXSWFSTSXvml:
    case VE::VRMAXSWFSTSXvml_v:
    case VE::VRMAXSWFSTZXvm:
    case VE::VRMAXSWFSTZXvmL:
    case VE::VRMAXSWFSTZXvmL_v:
    case VE::VRMAXSWFSTZXvm_v:
    case VE::VRMAXSWFSTZXvml:
    case VE::VRMAXSWFSTZXvml_v:
    case VE::VRMAXSWLSTSXvm:
    case VE::VRMAXSWLSTSXvmL:
    case VE::VRMAXSWLSTSXvmL_v:
    case VE::VRMAXSWLSTSXvm_v:
    case VE::VRMAXSWLSTSXvml:
    case VE::VRMAXSWLSTSXvml_v:
    case VE::VRMAXSWLSTZXvm:
    case VE::VRMAXSWLSTZXvmL:
    case VE::VRMAXSWLSTZXvmL_v:
    case VE::VRMAXSWLSTZXvm_v:
    case VE::VRMAXSWLSTZXvml:
    case VE::VRMAXSWLSTZXvml_v:
    case VE::VRMINSLFSTvm:
    case VE::VRMINSLFSTvmL:
    case VE::VRMINSLFSTvmL_v:
    case VE::VRMINSLFSTvm_v:
    case VE::VRMINSLFSTvml:
    case VE::VRMINSLFSTvml_v:
    case VE::VRMINSLLSTvm:
    case VE::VRMINSLLSTvmL:
    case VE::VRMINSLLSTvmL_v:
    case VE::VRMINSLLSTvm_v:
    case VE::VRMINSLLSTvml:
    case VE::VRMINSLLSTvml_v:
    case VE::VRMINSWFSTSXvm:
    case VE::VRMINSWFSTSXvmL:
    case VE::VRMINSWFSTSXvmL_v:
    case VE::VRMINSWFSTSXvm_v:
    case VE::VRMINSWFSTSXvml:
    case VE::VRMINSWFSTSXvml_v:
    case VE::VRMINSWFSTZXvm:
    case VE::VRMINSWFSTZXvmL:
    case VE::VRMINSWFSTZXvmL_v:
    case VE::VRMINSWFSTZXvm_v:
    case VE::VRMINSWFSTZXvml:
    case VE::VRMINSWFSTZXvml_v:
    case VE::VRMINSWLSTSXvm:
    case VE::VRMINSWLSTSXvmL:
    case VE::VRMINSWLSTSXvmL_v:
    case VE::VRMINSWLSTSXvm_v:
    case VE::VRMINSWLSTSXvml:
    case VE::VRMINSWLSTSXvml_v:
    case VE::VRMINSWLSTZXvm:
    case VE::VRMINSWLSTZXvmL:
    case VE::VRMINSWLSTZXvmL_v:
    case VE::VRMINSWLSTZXvm_v:
    case VE::VRMINSWLSTZXvml:
    case VE::VRMINSWLSTZXvml_v:
    case VE::VRORvm:
    case VE::VRORvmL:
    case VE::VRORvmL_v:
    case VE::VRORvm_v:
    case VE::VRORvml:
    case VE::VRORvml_v:
    case VE::VRSQRTDNEXvm:
    case VE::VRSQRTDNEXvmL:
    case VE::VRSQRTDNEXvmL_v:
    case VE::VRSQRTDNEXvm_v:
    case VE::VRSQRTDNEXvml:
    case VE::VRSQRTDNEXvml_v:
    case VE::VRSQRTDvm:
    case VE::VRSQRTDvmL:
    case VE::VRSQRTDvmL_v:
    case VE::VRSQRTDvm_v:
    case VE::VRSQRTDvml:
    case VE::VRSQRTDvml_v:
    case VE::VRSQRTSNEXvm:
    case VE::VRSQRTSNEXvmL:
    case VE::VRSQRTSNEXvmL_v:
    case VE::VRSQRTSNEXvm_v:
    case VE::VRSQRTSNEXvml:
    case VE::VRSQRTSNEXvml_v:
    case VE::VRSQRTSvm:
    case VE::VRSQRTSvmL:
    case VE::VRSQRTSvmL_v:
    case VE::VRSQRTSvm_v:
    case VE::VRSQRTSvml:
    case VE::VRSQRTSvml_v:
    case VE::VRXORvm:
    case VE::VRXORvmL:
    case VE::VRXORvmL_v:
    case VE::VRXORvm_v:
    case VE::VRXORvml:
    case VE::VRXORvml_v:
    case VE::VSUMLvm:
    case VE::VSUMLvmL:
    case VE::VSUMLvmL_v:
    case VE::VSUMLvm_v:
    case VE::VSUMLvml:
    case VE::VSUMLvml_v:
    case VE::VSUMWSXvm:
    case VE::VSUMWSXvmL:
    case VE::VSUMWSXvmL_v:
    case VE::VSUMWSXvm_v:
    case VE::VSUMWSXvml:
    case VE::VSUMWSXvml_v:
    case VE::VSUMWZXvm:
    case VE::VSUMWZXvmL:
    case VE::VSUMWZXvmL_v:
    case VE::VSUMWZXvm_v:
    case VE::VSUMWZXvml:
    case VE::VSUMWZXvml_v: {
      switch (OpNum) {
      case 2:
        // op: m
        return 48;
      case 0:
        // op: vx
        return 24;
      case 1:
        // op: vy
        return 16;
      }
      break;
    }
    case VE::PVBRVLOvm:
    case VE::PVBRVLOvmL:
    case VE::PVBRVLOvmL_v:
    case VE::PVBRVLOvm_v:
    case VE::PVBRVLOvml:
    case VE::PVBRVLOvml_v:
    case VE::PVBRVUPvm:
    case VE::PVBRVUPvmL:
    case VE::PVBRVUPvmL_v:
    case VE::PVBRVUPvm_v:
    case VE::PVBRVUPvml:
    case VE::PVBRVUPvml_v:
    case VE::PVBRVvm:
    case VE::PVBRVvmL:
    case VE::PVBRVvmL_v:
    case VE::PVBRVvm_v:
    case VE::PVBRVvml:
    case VE::PVBRVvml_v:
    case VE::PVLDZLOvm:
    case VE::PVLDZLOvmL:
    case VE::PVLDZLOvmL_v:
    case VE::PVLDZLOvm_v:
    case VE::PVLDZLOvml:
    case VE::PVLDZLOvml_v:
    case VE::PVLDZUPvm:
    case VE::PVLDZUPvmL:
    case VE::PVLDZUPvmL_v:
    case VE::PVLDZUPvm_v:
    case VE::PVLDZUPvml:
    case VE::PVLDZUPvml_v:
    case VE::PVLDZvm:
    case VE::PVLDZvmL:
    case VE::PVLDZvmL_v:
    case VE::PVLDZvm_v:
    case VE::PVLDZvml:
    case VE::PVLDZvml_v:
    case VE::PVPCNTLOvm:
    case VE::PVPCNTLOvmL:
    case VE::PVPCNTLOvmL_v:
    case VE::PVPCNTLOvm_v:
    case VE::PVPCNTLOvml:
    case VE::PVPCNTLOvml_v:
    case VE::PVPCNTUPvm:
    case VE::PVPCNTUPvmL:
    case VE::PVPCNTUPvmL_v:
    case VE::PVPCNTUPvm_v:
    case VE::PVPCNTUPvml:
    case VE::PVPCNTUPvml_v:
    case VE::PVPCNTvm:
    case VE::PVPCNTvmL:
    case VE::PVPCNTvmL_v:
    case VE::PVPCNTvm_v:
    case VE::PVPCNTvml:
    case VE::PVPCNTvml_v:
    case VE::VBRVvm:
    case VE::VBRVvmL:
    case VE::VBRVvmL_v:
    case VE::VBRVvm_v:
    case VE::VBRVvml:
    case VE::VBRVvml_v:
    case VE::VCPvm:
    case VE::VCPvmL:
    case VE::VCPvmL_v:
    case VE::VCPvm_v:
    case VE::VCPvml:
    case VE::VCPvml_v:
    case VE::VEXvm:
    case VE::VEXvmL:
    case VE::VEXvmL_v:
    case VE::VEXvm_v:
    case VE::VEXvml:
    case VE::VEXvml_v:
    case VE::VLDZvm:
    case VE::VLDZvmL:
    case VE::VLDZvmL_v:
    case VE::VLDZvm_v:
    case VE::VLDZvml:
    case VE::VLDZvml_v:
    case VE::VPCNTvm:
    case VE::VPCNTvmL:
    case VE::VPCNTvmL_v:
    case VE::VPCNTvm_v:
    case VE::VPCNTvml:
    case VE::VPCNTvml_v: {
      switch (OpNum) {
      case 2:
        // op: m
        return 48;
      case 0:
        // op: vx
        return 24;
      case 1:
        // op: vz
        return 8;
      }
      break;
    }
    case VE::PVBRDim:
    case VE::PVBRDimL:
    case VE::PVBRDimL_v:
    case VE::PVBRDim_v:
    case VE::PVBRDiml:
    case VE::PVBRDiml_v:
    case VE::PVBRDrm:
    case VE::PVBRDrmL:
    case VE::PVBRDrmL_v:
    case VE::PVBRDrm_v:
    case VE::PVBRDrml:
    case VE::PVBRDrml_v:
    case VE::VBRDLim:
    case VE::VBRDLimL:
    case VE::VBRDLimL_v:
    case VE::VBRDLim_v:
    case VE::VBRDLiml:
    case VE::VBRDLiml_v:
    case VE::VBRDLrm:
    case VE::VBRDLrmL:
    case VE::VBRDLrmL_v:
    case VE::VBRDLrm_v:
    case VE::VBRDLrml:
    case VE::VBRDLrml_v:
    case VE::VBRDUim:
    case VE::VBRDUimL:
    case VE::VBRDUimL_v:
    case VE::VBRDUim_v:
    case VE::VBRDUiml:
    case VE::VBRDUiml_v:
    case VE::VBRDUrm:
    case VE::VBRDUrmL:
    case VE::VBRDUrmL_v:
    case VE::VBRDUrm_v:
    case VE::VBRDUrml:
    case VE::VBRDUrml_v:
    case VE::VBRDim:
    case VE::VBRDimL:
    case VE::VBRDimL_v:
    case VE::VBRDim_v:
    case VE::VBRDiml:
    case VE::VBRDiml_v:
    case VE::VBRDrm:
    case VE::VBRDrmL:
    case VE::VBRDrmL_v:
    case VE::VBRDrm_v:
    case VE::VBRDrml:
    case VE::VBRDrml_v: {
      switch (OpNum) {
      case 2:
        // op: m
        return 48;
      case 1:
        // op: sy
        return 40;
      case 0:
        // op: vx
        return 24;
      }
      break;
    }
    case VE::SCRirr:
    case VE::SCRizr:
    case VE::SCRrrr:
    case VE::SCRrzr: {
      switch (OpNum) {
      case 2:
        // op: sx
        return 48;
      case 0:
        // op: sy
        return 40;
      case 1:
        // op: sz
        return 32;
      }
      break;
    }
    case VE::SHMBri:
    case VE::SHMBzi:
    case VE::SHMHri:
    case VE::SHMHzi:
    case VE::SHMLri:
    case VE::SHMLzi:
    case VE::SHMWri:
    case VE::SHMWzi: {
      switch (OpNum) {
      case 2:
        // op: sx
        return 48;
      case 0:
        // op: sz
        return 32;
      case 1:
        // op: imm32
        return 0;
      }
      break;
    }
    case VE::PVFMADLOviv:
    case VE::PVFMADLOvivL:
    case VE::PVFMADLOvivL_v:
    case VE::PVFMADLOviv_v:
    case VE::PVFMADLOvivl:
    case VE::PVFMADLOvivl_v:
    case VE::PVFMADLOvrv:
    case VE::PVFMADLOvrvL:
    case VE::PVFMADLOvrvL_v:
    case VE::PVFMADLOvrv_v:
    case VE::PVFMADLOvrvl:
    case VE::PVFMADLOvrvl_v:
    case VE::PVFMADUPviv:
    case VE::PVFMADUPvivL:
    case VE::PVFMADUPvivL_v:
    case VE::PVFMADUPviv_v:
    case VE::PVFMADUPvivl:
    case VE::PVFMADUPvivl_v:
    case VE::PVFMADUPvrv:
    case VE::PVFMADUPvrvL:
    case VE::PVFMADUPvrvL_v:
    case VE::PVFMADUPvrv_v:
    case VE::PVFMADUPvrvl:
    case VE::PVFMADUPvrvl_v:
    case VE::PVFMADviv:
    case VE::PVFMADvivL:
    case VE::PVFMADvivL_v:
    case VE::PVFMADviv_v:
    case VE::PVFMADvivl:
    case VE::PVFMADvivl_v:
    case VE::PVFMADvrv:
    case VE::PVFMADvrvL:
    case VE::PVFMADvrvL_v:
    case VE::PVFMADvrv_v:
    case VE::PVFMADvrvl:
    case VE::PVFMADvrvl_v:
    case VE::PVFMSBLOviv:
    case VE::PVFMSBLOvivL:
    case VE::PVFMSBLOvivL_v:
    case VE::PVFMSBLOviv_v:
    case VE::PVFMSBLOvivl:
    case VE::PVFMSBLOvivl_v:
    case VE::PVFMSBLOvrv:
    case VE::PVFMSBLOvrvL:
    case VE::PVFMSBLOvrvL_v:
    case VE::PVFMSBLOvrv_v:
    case VE::PVFMSBLOvrvl:
    case VE::PVFMSBLOvrvl_v:
    case VE::PVFMSBUPviv:
    case VE::PVFMSBUPvivL:
    case VE::PVFMSBUPvivL_v:
    case VE::PVFMSBUPviv_v:
    case VE::PVFMSBUPvivl:
    case VE::PVFMSBUPvivl_v:
    case VE::PVFMSBUPvrv:
    case VE::PVFMSBUPvrvL:
    case VE::PVFMSBUPvrvL_v:
    case VE::PVFMSBUPvrv_v:
    case VE::PVFMSBUPvrvl:
    case VE::PVFMSBUPvrvl_v:
    case VE::PVFMSBviv:
    case VE::PVFMSBvivL:
    case VE::PVFMSBvivL_v:
    case VE::PVFMSBviv_v:
    case VE::PVFMSBvivl:
    case VE::PVFMSBvivl_v:
    case VE::PVFMSBvrv:
    case VE::PVFMSBvrvL:
    case VE::PVFMSBvrvL_v:
    case VE::PVFMSBvrv_v:
    case VE::PVFMSBvrvl:
    case VE::PVFMSBvrvl_v:
    case VE::PVFNMADLOviv:
    case VE::PVFNMADLOvivL:
    case VE::PVFNMADLOvivL_v:
    case VE::PVFNMADLOviv_v:
    case VE::PVFNMADLOvivl:
    case VE::PVFNMADLOvivl_v:
    case VE::PVFNMADLOvrv:
    case VE::PVFNMADLOvrvL:
    case VE::PVFNMADLOvrvL_v:
    case VE::PVFNMADLOvrv_v:
    case VE::PVFNMADLOvrvl:
    case VE::PVFNMADLOvrvl_v:
    case VE::PVFNMADUPviv:
    case VE::PVFNMADUPvivL:
    case VE::PVFNMADUPvivL_v:
    case VE::PVFNMADUPviv_v:
    case VE::PVFNMADUPvivl:
    case VE::PVFNMADUPvivl_v:
    case VE::PVFNMADUPvrv:
    case VE::PVFNMADUPvrvL:
    case VE::PVFNMADUPvrvL_v:
    case VE::PVFNMADUPvrv_v:
    case VE::PVFNMADUPvrvl:
    case VE::PVFNMADUPvrvl_v:
    case VE::PVFNMADviv:
    case VE::PVFNMADvivL:
    case VE::PVFNMADvivL_v:
    case VE::PVFNMADviv_v:
    case VE::PVFNMADvivl:
    case VE::PVFNMADvivl_v:
    case VE::PVFNMADvrv:
    case VE::PVFNMADvrvL:
    case VE::PVFNMADvrvL_v:
    case VE::PVFNMADvrv_v:
    case VE::PVFNMADvrvl:
    case VE::PVFNMADvrvl_v:
    case VE::PVFNMSBLOviv:
    case VE::PVFNMSBLOvivL:
    case VE::PVFNMSBLOvivL_v:
    case VE::PVFNMSBLOviv_v:
    case VE::PVFNMSBLOvivl:
    case VE::PVFNMSBLOvivl_v:
    case VE::PVFNMSBLOvrv:
    case VE::PVFNMSBLOvrvL:
    case VE::PVFNMSBLOvrvL_v:
    case VE::PVFNMSBLOvrv_v:
    case VE::PVFNMSBLOvrvl:
    case VE::PVFNMSBLOvrvl_v:
    case VE::PVFNMSBUPviv:
    case VE::PVFNMSBUPvivL:
    case VE::PVFNMSBUPvivL_v:
    case VE::PVFNMSBUPviv_v:
    case VE::PVFNMSBUPvivl:
    case VE::PVFNMSBUPvivl_v:
    case VE::PVFNMSBUPvrv:
    case VE::PVFNMSBUPvrvL:
    case VE::PVFNMSBUPvrvL_v:
    case VE::PVFNMSBUPvrv_v:
    case VE::PVFNMSBUPvrvl:
    case VE::PVFNMSBUPvrvl_v:
    case VE::PVFNMSBviv:
    case VE::PVFNMSBvivL:
    case VE::PVFNMSBvivL_v:
    case VE::PVFNMSBviv_v:
    case VE::PVFNMSBvivl:
    case VE::PVFNMSBvivl_v:
    case VE::PVFNMSBvrv:
    case VE::PVFNMSBvrvL:
    case VE::PVFNMSBvrvL_v:
    case VE::PVFNMSBvrv_v:
    case VE::PVFNMSBvrvl:
    case VE::PVFNMSBvrvl_v:
    case VE::VFMADDviv:
    case VE::VFMADDvivL:
    case VE::VFMADDvivL_v:
    case VE::VFMADDviv_v:
    case VE::VFMADDvivl:
    case VE::VFMADDvivl_v:
    case VE::VFMADDvrv:
    case VE::VFMADDvrvL:
    case VE::VFMADDvrvL_v:
    case VE::VFMADDvrv_v:
    case VE::VFMADDvrvl:
    case VE::VFMADDvrvl_v:
    case VE::VFMADSviv:
    case VE::VFMADSvivL:
    case VE::VFMADSvivL_v:
    case VE::VFMADSviv_v:
    case VE::VFMADSvivl:
    case VE::VFMADSvivl_v:
    case VE::VFMADSvrv:
    case VE::VFMADSvrvL:
    case VE::VFMADSvrvL_v:
    case VE::VFMADSvrv_v:
    case VE::VFMADSvrvl:
    case VE::VFMADSvrvl_v:
    case VE::VFMSBDviv:
    case VE::VFMSBDvivL:
    case VE::VFMSBDvivL_v:
    case VE::VFMSBDviv_v:
    case VE::VFMSBDvivl:
    case VE::VFMSBDvivl_v:
    case VE::VFMSBDvrv:
    case VE::VFMSBDvrvL:
    case VE::VFMSBDvrvL_v:
    case VE::VFMSBDvrv_v:
    case VE::VFMSBDvrvl:
    case VE::VFMSBDvrvl_v:
    case VE::VFMSBSviv:
    case VE::VFMSBSvivL:
    case VE::VFMSBSvivL_v:
    case VE::VFMSBSviv_v:
    case VE::VFMSBSvivl:
    case VE::VFMSBSvivl_v:
    case VE::VFMSBSvrv:
    case VE::VFMSBSvrvL:
    case VE::VFMSBSvrvL_v:
    case VE::VFMSBSvrv_v:
    case VE::VFMSBSvrvl:
    case VE::VFMSBSvrvl_v:
    case VE::VFNMADDviv:
    case VE::VFNMADDvivL:
    case VE::VFNMADDvivL_v:
    case VE::VFNMADDviv_v:
    case VE::VFNMADDvivl:
    case VE::VFNMADDvivl_v:
    case VE::VFNMADDvrv:
    case VE::VFNMADDvrvL:
    case VE::VFNMADDvrvL_v:
    case VE::VFNMADDvrv_v:
    case VE::VFNMADDvrvl:
    case VE::VFNMADDvrvl_v:
    case VE::VFNMADSviv:
    case VE::VFNMADSvivL:
    case VE::VFNMADSvivL_v:
    case VE::VFNMADSviv_v:
    case VE::VFNMADSvivl:
    case VE::VFNMADSvivl_v:
    case VE::VFNMADSvrv:
    case VE::VFNMADSvrvL:
    case VE::VFNMADSvrvL_v:
    case VE::VFNMADSvrv_v:
    case VE::VFNMADSvrvl:
    case VE::VFNMADSvrvl_v:
    case VE::VFNMSBDviv:
    case VE::VFNMSBDvivL:
    case VE::VFNMSBDvivL_v:
    case VE::VFNMSBDviv_v:
    case VE::VFNMSBDvivl:
    case VE::VFNMSBDvivl_v:
    case VE::VFNMSBDvrv:
    case VE::VFNMSBDvrvL:
    case VE::VFNMSBDvrvL_v:
    case VE::VFNMSBDvrv_v:
    case VE::VFNMSBDvrvl:
    case VE::VFNMSBDvrvl_v:
    case VE::VFNMSBSviv:
    case VE::VFNMSBSvivL:
    case VE::VFNMSBSvivL_v:
    case VE::VFNMSBSviv_v:
    case VE::VFNMSBSvivl:
    case VE::VFNMSBSvivl_v:
    case VE::VFNMSBSvrv:
    case VE::VFNMSBSvrvL:
    case VE::VFNMSBSvrvL_v:
    case VE::VFNMSBSvrv_v:
    case VE::VFNMSBSvrvl:
    case VE::VFNMSBSvrvl_v: {
      switch (OpNum) {
      case 2:
        // op: sy
        return 40;
      case 0:
        // op: vx
        return 24;
      case 1:
        // op: vy
        return 16;
      case 3:
        // op: vw
        return 0;
      }
      break;
    }
    case VE::VDIVSLvi:
    case VE::VDIVSLviL:
    case VE::VDIVSLviL_v:
    case VE::VDIVSLvi_v:
    case VE::VDIVSLvil:
    case VE::VDIVSLvil_v:
    case VE::VDIVSLvr:
    case VE::VDIVSLvrL:
    case VE::VDIVSLvrL_v:
    case VE::VDIVSLvr_v:
    case VE::VDIVSLvrl:
    case VE::VDIVSLvrl_v:
    case VE::VDIVSWSXvi:
    case VE::VDIVSWSXviL:
    case VE::VDIVSWSXviL_v:
    case VE::VDIVSWSXvi_v:
    case VE::VDIVSWSXvil:
    case VE::VDIVSWSXvil_v:
    case VE::VDIVSWSXvr:
    case VE::VDIVSWSXvrL:
    case VE::VDIVSWSXvrL_v:
    case VE::VDIVSWSXvr_v:
    case VE::VDIVSWSXvrl:
    case VE::VDIVSWSXvrl_v:
    case VE::VDIVSWZXvi:
    case VE::VDIVSWZXviL:
    case VE::VDIVSWZXviL_v:
    case VE::VDIVSWZXvi_v:
    case VE::VDIVSWZXvil:
    case VE::VDIVSWZXvil_v:
    case VE::VDIVSWZXvr:
    case VE::VDIVSWZXvrL:
    case VE::VDIVSWZXvrL_v:
    case VE::VDIVSWZXvr_v:
    case VE::VDIVSWZXvrl:
    case VE::VDIVSWZXvrl_v:
    case VE::VDIVULvi:
    case VE::VDIVULviL:
    case VE::VDIVULviL_v:
    case VE::VDIVULvi_v:
    case VE::VDIVULvil:
    case VE::VDIVULvil_v:
    case VE::VDIVULvr:
    case VE::VDIVULvrL:
    case VE::VDIVULvrL_v:
    case VE::VDIVULvr_v:
    case VE::VDIVULvrl:
    case VE::VDIVULvrl_v:
    case VE::VDIVUWvi:
    case VE::VDIVUWviL:
    case VE::VDIVUWviL_v:
    case VE::VDIVUWvi_v:
    case VE::VDIVUWvil:
    case VE::VDIVUWvil_v:
    case VE::VDIVUWvr:
    case VE::VDIVUWvrL:
    case VE::VDIVUWvrL_v:
    case VE::VDIVUWvr_v:
    case VE::VDIVUWvrl:
    case VE::VDIVUWvrl_v:
    case VE::VFDIVDvi:
    case VE::VFDIVDviL:
    case VE::VFDIVDviL_v:
    case VE::VFDIVDvi_v:
    case VE::VFDIVDvil:
    case VE::VFDIVDvil_v:
    case VE::VFDIVDvr:
    case VE::VFDIVDvrL:
    case VE::VFDIVDvrL_v:
    case VE::VFDIVDvr_v:
    case VE::VFDIVDvrl:
    case VE::VFDIVDvrl_v:
    case VE::VFDIVSvi:
    case VE::VFDIVSviL:
    case VE::VFDIVSviL_v:
    case VE::VFDIVSvi_v:
    case VE::VFDIVSvil:
    case VE::VFDIVSvil_v:
    case VE::VFDIVSvr:
    case VE::VFDIVSvrL:
    case VE::VFDIVSvrL_v:
    case VE::VFDIVSvr_v:
    case VE::VFDIVSvrl:
    case VE::VFDIVSvrl_v:
    case VE::VFIADvi:
    case VE::VFIADviL:
    case VE::VFIADviL_v:
    case VE::VFIADvi_v:
    case VE::VFIADvil:
    case VE::VFIADvil_v:
    case VE::VFIADvr:
    case VE::VFIADvrL:
    case VE::VFIADvrL_v:
    case VE::VFIADvr_v:
    case VE::VFIADvrl:
    case VE::VFIADvrl_v:
    case VE::VFIASvi:
    case VE::VFIASviL:
    case VE::VFIASviL_v:
    case VE::VFIASvi_v:
    case VE::VFIASvil:
    case VE::VFIASvil_v:
    case VE::VFIASvr:
    case VE::VFIASvrL:
    case VE::VFIASvrL_v:
    case VE::VFIASvr_v:
    case VE::VFIASvrl:
    case VE::VFIASvrl_v:
    case VE::VFIMDvi:
    case VE::VFIMDviL:
    case VE::VFIMDviL_v:
    case VE::VFIMDvi_v:
    case VE::VFIMDvil:
    case VE::VFIMDvil_v:
    case VE::VFIMDvr:
    case VE::VFIMDvrL:
    case VE::VFIMDvrL_v:
    case VE::VFIMDvr_v:
    case VE::VFIMDvrl:
    case VE::VFIMDvrl_v:
    case VE::VFIMSvi:
    case VE::VFIMSviL:
    case VE::VFIMSviL_v:
    case VE::VFIMSvi_v:
    case VE::VFIMSvil:
    case VE::VFIMSvil_v:
    case VE::VFIMSvr:
    case VE::VFIMSvrL:
    case VE::VFIMSvrL_v:
    case VE::VFIMSvr_v:
    case VE::VFIMSvrl:
    case VE::VFIMSvrl_v:
    case VE::VFISDvi:
    case VE::VFISDviL:
    case VE::VFISDviL_v:
    case VE::VFISDvi_v:
    case VE::VFISDvil:
    case VE::VFISDvil_v:
    case VE::VFISDvr:
    case VE::VFISDvrL:
    case VE::VFISDvrL_v:
    case VE::VFISDvr_v:
    case VE::VFISDvrl:
    case VE::VFISDvrl_v:
    case VE::VFISSvi:
    case VE::VFISSviL:
    case VE::VFISSviL_v:
    case VE::VFISSvi_v:
    case VE::VFISSvil:
    case VE::VFISSvil_v:
    case VE::VFISSvr:
    case VE::VFISSvrL:
    case VE::VFISSvrL_v:
    case VE::VFISSvr_v:
    case VE::VFISSvrl:
    case VE::VFISSvrl_v: {
      switch (OpNum) {
      case 2:
        // op: sy
        return 40;
      case 0:
        // op: vx
        return 24;
      case 1:
        // op: vy
        return 16;
      }
      break;
    }
    case VE::PVSLALOvi:
    case VE::PVSLALOviL:
    case VE::PVSLALOviL_v:
    case VE::PVSLALOvi_v:
    case VE::PVSLALOvil:
    case VE::PVSLALOvil_v:
    case VE::PVSLALOvr:
    case VE::PVSLALOvrL:
    case VE::PVSLALOvrL_v:
    case VE::PVSLALOvr_v:
    case VE::PVSLALOvrl:
    case VE::PVSLALOvrl_v:
    case VE::PVSLAUPvi:
    case VE::PVSLAUPviL:
    case VE::PVSLAUPviL_v:
    case VE::PVSLAUPvi_v:
    case VE::PVSLAUPvil:
    case VE::PVSLAUPvil_v:
    case VE::PVSLAUPvr:
    case VE::PVSLAUPvrL:
    case VE::PVSLAUPvrL_v:
    case VE::PVSLAUPvr_v:
    case VE::PVSLAUPvrl:
    case VE::PVSLAUPvrl_v:
    case VE::PVSLAvi:
    case VE::PVSLAviL:
    case VE::PVSLAviL_v:
    case VE::PVSLAvi_v:
    case VE::PVSLAvil:
    case VE::PVSLAvil_v:
    case VE::PVSLAvr:
    case VE::PVSLAvrL:
    case VE::PVSLAvrL_v:
    case VE::PVSLAvr_v:
    case VE::PVSLAvrl:
    case VE::PVSLAvrl_v:
    case VE::PVSLLLOvi:
    case VE::PVSLLLOviL:
    case VE::PVSLLLOviL_v:
    case VE::PVSLLLOvi_v:
    case VE::PVSLLLOvil:
    case VE::PVSLLLOvil_v:
    case VE::PVSLLLOvr:
    case VE::PVSLLLOvrL:
    case VE::PVSLLLOvrL_v:
    case VE::PVSLLLOvr_v:
    case VE::PVSLLLOvrl:
    case VE::PVSLLLOvrl_v:
    case VE::PVSLLUPvi:
    case VE::PVSLLUPviL:
    case VE::PVSLLUPviL_v:
    case VE::PVSLLUPvi_v:
    case VE::PVSLLUPvil:
    case VE::PVSLLUPvil_v:
    case VE::PVSLLUPvr:
    case VE::PVSLLUPvrL:
    case VE::PVSLLUPvrL_v:
    case VE::PVSLLUPvr_v:
    case VE::PVSLLUPvrl:
    case VE::PVSLLUPvrl_v:
    case VE::PVSLLvi:
    case VE::PVSLLviL:
    case VE::PVSLLviL_v:
    case VE::PVSLLvi_v:
    case VE::PVSLLvil:
    case VE::PVSLLvil_v:
    case VE::PVSLLvr:
    case VE::PVSLLvrL:
    case VE::PVSLLvrL_v:
    case VE::PVSLLvr_v:
    case VE::PVSLLvrl:
    case VE::PVSLLvrl_v:
    case VE::PVSRALOvi:
    case VE::PVSRALOviL:
    case VE::PVSRALOviL_v:
    case VE::PVSRALOvi_v:
    case VE::PVSRALOvil:
    case VE::PVSRALOvil_v:
    case VE::PVSRALOvr:
    case VE::PVSRALOvrL:
    case VE::PVSRALOvrL_v:
    case VE::PVSRALOvr_v:
    case VE::PVSRALOvrl:
    case VE::PVSRALOvrl_v:
    case VE::PVSRAUPvi:
    case VE::PVSRAUPviL:
    case VE::PVSRAUPviL_v:
    case VE::PVSRAUPvi_v:
    case VE::PVSRAUPvil:
    case VE::PVSRAUPvil_v:
    case VE::PVSRAUPvr:
    case VE::PVSRAUPvrL:
    case VE::PVSRAUPvrL_v:
    case VE::PVSRAUPvr_v:
    case VE::PVSRAUPvrl:
    case VE::PVSRAUPvrl_v:
    case VE::PVSRAvi:
    case VE::PVSRAviL:
    case VE::PVSRAviL_v:
    case VE::PVSRAvi_v:
    case VE::PVSRAvil:
    case VE::PVSRAvil_v:
    case VE::PVSRAvr:
    case VE::PVSRAvrL:
    case VE::PVSRAvrL_v:
    case VE::PVSRAvr_v:
    case VE::PVSRAvrl:
    case VE::PVSRAvrl_v:
    case VE::PVSRLLOvi:
    case VE::PVSRLLOviL:
    case VE::PVSRLLOviL_v:
    case VE::PVSRLLOvi_v:
    case VE::PVSRLLOvil:
    case VE::PVSRLLOvil_v:
    case VE::PVSRLLOvr:
    case VE::PVSRLLOvrL:
    case VE::PVSRLLOvrL_v:
    case VE::PVSRLLOvr_v:
    case VE::PVSRLLOvrl:
    case VE::PVSRLLOvrl_v:
    case VE::PVSRLUPvi:
    case VE::PVSRLUPviL:
    case VE::PVSRLUPviL_v:
    case VE::PVSRLUPvi_v:
    case VE::PVSRLUPvil:
    case VE::PVSRLUPvil_v:
    case VE::PVSRLUPvr:
    case VE::PVSRLUPvrL:
    case VE::PVSRLUPvrL_v:
    case VE::PVSRLUPvr_v:
    case VE::PVSRLUPvrl:
    case VE::PVSRLUPvrl_v:
    case VE::PVSRLvi:
    case VE::PVSRLviL:
    case VE::PVSRLviL_v:
    case VE::PVSRLvi_v:
    case VE::PVSRLvil:
    case VE::PVSRLvil_v:
    case VE::PVSRLvr:
    case VE::PVSRLvrL:
    case VE::PVSRLvrL_v:
    case VE::PVSRLvr_v:
    case VE::PVSRLvrl:
    case VE::PVSRLvrl_v:
    case VE::VSLALvi:
    case VE::VSLALviL:
    case VE::VSLALviL_v:
    case VE::VSLALvi_v:
    case VE::VSLALvil:
    case VE::VSLALvil_v:
    case VE::VSLALvr:
    case VE::VSLALvrL:
    case VE::VSLALvrL_v:
    case VE::VSLALvr_v:
    case VE::VSLALvrl:
    case VE::VSLALvrl_v:
    case VE::VSLAWSXvi:
    case VE::VSLAWSXviL:
    case VE::VSLAWSXviL_v:
    case VE::VSLAWSXvi_v:
    case VE::VSLAWSXvil:
    case VE::VSLAWSXvil_v:
    case VE::VSLAWSXvr:
    case VE::VSLAWSXvrL:
    case VE::VSLAWSXvrL_v:
    case VE::VSLAWSXvr_v:
    case VE::VSLAWSXvrl:
    case VE::VSLAWSXvrl_v:
    case VE::VSLAWZXvi:
    case VE::VSLAWZXviL:
    case VE::VSLAWZXviL_v:
    case VE::VSLAWZXvi_v:
    case VE::VSLAWZXvil:
    case VE::VSLAWZXvil_v:
    case VE::VSLAWZXvr:
    case VE::VSLAWZXvrL:
    case VE::VSLAWZXvrL_v:
    case VE::VSLAWZXvr_v:
    case VE::VSLAWZXvrl:
    case VE::VSLAWZXvrl_v:
    case VE::VSLLvi:
    case VE::VSLLviL:
    case VE::VSLLviL_v:
    case VE::VSLLvi_v:
    case VE::VSLLvil:
    case VE::VSLLvil_v:
    case VE::VSLLvr:
    case VE::VSLLvrL:
    case VE::VSLLvrL_v:
    case VE::VSLLvr_v:
    case VE::VSLLvrl:
    case VE::VSLLvrl_v:
    case VE::VSRALvi:
    case VE::VSRALviL:
    case VE::VSRALviL_v:
    case VE::VSRALvi_v:
    case VE::VSRALvil:
    case VE::VSRALvil_v:
    case VE::VSRALvr:
    case VE::VSRALvrL:
    case VE::VSRALvrL_v:
    case VE::VSRALvr_v:
    case VE::VSRALvrl:
    case VE::VSRALvrl_v:
    case VE::VSRAWSXvi:
    case VE::VSRAWSXviL:
    case VE::VSRAWSXviL_v:
    case VE::VSRAWSXvi_v:
    case VE::VSRAWSXvil:
    case VE::VSRAWSXvil_v:
    case VE::VSRAWSXvr:
    case VE::VSRAWSXvrL:
    case VE::VSRAWSXvrL_v:
    case VE::VSRAWSXvr_v:
    case VE::VSRAWSXvrl:
    case VE::VSRAWSXvrl_v:
    case VE::VSRAWZXvi:
    case VE::VSRAWZXviL:
    case VE::VSRAWZXviL_v:
    case VE::VSRAWZXvi_v:
    case VE::VSRAWZXvil:
    case VE::VSRAWZXvil_v:
    case VE::VSRAWZXvr:
    case VE::VSRAWZXvrL:
    case VE::VSRAWZXvrL_v:
    case VE::VSRAWZXvr_v:
    case VE::VSRAWZXvrl:
    case VE::VSRAWZXvrl_v:
    case VE::VSRLvi:
    case VE::VSRLviL:
    case VE::VSRLviL_v:
    case VE::VSRLvi_v:
    case VE::VSRLvil:
    case VE::VSRLvil_v:
    case VE::VSRLvr:
    case VE::VSRLvrL:
    case VE::VSRLvrL_v:
    case VE::VSRLvr_v:
    case VE::VSRLvrl:
    case VE::VSRLvrl_v: {
      switch (OpNum) {
      case 2:
        // op: sy
        return 40;
      case 0:
        // op: vx
        return 24;
      case 1:
        // op: vz
        return 8;
      }
      break;
    }
    case VE::VGTLSXNCsir:
    case VE::VGTLSXNCsirL:
    case VE::VGTLSXNCsirL_v:
    case VE::VGTLSXNCsir_v:
    case VE::VGTLSXNCsirl:
    case VE::VGTLSXNCsirl_v:
    case VE::VGTLSXNCsiz:
    case VE::VGTLSXNCsizL:
    case VE::VGTLSXNCsizL_v:
    case VE::VGTLSXNCsiz_v:
    case VE::VGTLSXNCsizl:
    case VE::VGTLSXNCsizl_v:
    case VE::VGTLSXNCsrr:
    case VE::VGTLSXNCsrrL:
    case VE::VGTLSXNCsrrL_v:
    case VE::VGTLSXNCsrr_v:
    case VE::VGTLSXNCsrrl:
    case VE::VGTLSXNCsrrl_v:
    case VE::VGTLSXNCsrz:
    case VE::VGTLSXNCsrzL:
    case VE::VGTLSXNCsrzL_v:
    case VE::VGTLSXNCsrz_v:
    case VE::VGTLSXNCsrzl:
    case VE::VGTLSXNCsrzl_v:
    case VE::VGTLSXsir:
    case VE::VGTLSXsirL:
    case VE::VGTLSXsirL_v:
    case VE::VGTLSXsir_v:
    case VE::VGTLSXsirl:
    case VE::VGTLSXsirl_v:
    case VE::VGTLSXsiz:
    case VE::VGTLSXsizL:
    case VE::VGTLSXsizL_v:
    case VE::VGTLSXsiz_v:
    case VE::VGTLSXsizl:
    case VE::VGTLSXsizl_v:
    case VE::VGTLSXsrr:
    case VE::VGTLSXsrrL:
    case VE::VGTLSXsrrL_v:
    case VE::VGTLSXsrr_v:
    case VE::VGTLSXsrrl:
    case VE::VGTLSXsrrl_v:
    case VE::VGTLSXsrz:
    case VE::VGTLSXsrzL:
    case VE::VGTLSXsrzL_v:
    case VE::VGTLSXsrz_v:
    case VE::VGTLSXsrzl:
    case VE::VGTLSXsrzl_v:
    case VE::VGTLZXNCsir:
    case VE::VGTLZXNCsirL:
    case VE::VGTLZXNCsirL_v:
    case VE::VGTLZXNCsir_v:
    case VE::VGTLZXNCsirl:
    case VE::VGTLZXNCsirl_v:
    case VE::VGTLZXNCsiz:
    case VE::VGTLZXNCsizL:
    case VE::VGTLZXNCsizL_v:
    case VE::VGTLZXNCsiz_v:
    case VE::VGTLZXNCsizl:
    case VE::VGTLZXNCsizl_v:
    case VE::VGTLZXNCsrr:
    case VE::VGTLZXNCsrrL:
    case VE::VGTLZXNCsrrL_v:
    case VE::VGTLZXNCsrr_v:
    case VE::VGTLZXNCsrrl:
    case VE::VGTLZXNCsrrl_v:
    case VE::VGTLZXNCsrz:
    case VE::VGTLZXNCsrzL:
    case VE::VGTLZXNCsrzL_v:
    case VE::VGTLZXNCsrz_v:
    case VE::VGTLZXNCsrzl:
    case VE::VGTLZXNCsrzl_v:
    case VE::VGTLZXsir:
    case VE::VGTLZXsirL:
    case VE::VGTLZXsirL_v:
    case VE::VGTLZXsir_v:
    case VE::VGTLZXsirl:
    case VE::VGTLZXsirl_v:
    case VE::VGTLZXsiz:
    case VE::VGTLZXsizL:
    case VE::VGTLZXsizL_v:
    case VE::VGTLZXsiz_v:
    case VE::VGTLZXsizl:
    case VE::VGTLZXsizl_v:
    case VE::VGTLZXsrr:
    case VE::VGTLZXsrrL:
    case VE::VGTLZXsrrL_v:
    case VE::VGTLZXsrr_v:
    case VE::VGTLZXsrrl:
    case VE::VGTLZXsrrl_v:
    case VE::VGTLZXsrz:
    case VE::VGTLZXsrzL:
    case VE::VGTLZXsrzL_v:
    case VE::VGTLZXsrz_v:
    case VE::VGTLZXsrzl:
    case VE::VGTLZXsrzl_v:
    case VE::VGTNCsir:
    case VE::VGTNCsirL:
    case VE::VGTNCsirL_v:
    case VE::VGTNCsir_v:
    case VE::VGTNCsirl:
    case VE::VGTNCsirl_v:
    case VE::VGTNCsiz:
    case VE::VGTNCsizL:
    case VE::VGTNCsizL_v:
    case VE::VGTNCsiz_v:
    case VE::VGTNCsizl:
    case VE::VGTNCsizl_v:
    case VE::VGTNCsrr:
    case VE::VGTNCsrrL:
    case VE::VGTNCsrrL_v:
    case VE::VGTNCsrr_v:
    case VE::VGTNCsrrl:
    case VE::VGTNCsrrl_v:
    case VE::VGTNCsrz:
    case VE::VGTNCsrzL:
    case VE::VGTNCsrzL_v:
    case VE::VGTNCsrz_v:
    case VE::VGTNCsrzl:
    case VE::VGTNCsrzl_v:
    case VE::VGTUNCsir:
    case VE::VGTUNCsirL:
    case VE::VGTUNCsirL_v:
    case VE::VGTUNCsir_v:
    case VE::VGTUNCsirl:
    case VE::VGTUNCsirl_v:
    case VE::VGTUNCsiz:
    case VE::VGTUNCsizL:
    case VE::VGTUNCsizL_v:
    case VE::VGTUNCsiz_v:
    case VE::VGTUNCsizl:
    case VE::VGTUNCsizl_v:
    case VE::VGTUNCsrr:
    case VE::VGTUNCsrrL:
    case VE::VGTUNCsrrL_v:
    case VE::VGTUNCsrr_v:
    case VE::VGTUNCsrrl:
    case VE::VGTUNCsrrl_v:
    case VE::VGTUNCsrz:
    case VE::VGTUNCsrzL:
    case VE::VGTUNCsrzL_v:
    case VE::VGTUNCsrz_v:
    case VE::VGTUNCsrzl:
    case VE::VGTUNCsrzl_v:
    case VE::VGTUsir:
    case VE::VGTUsirL:
    case VE::VGTUsirL_v:
    case VE::VGTUsir_v:
    case VE::VGTUsirl:
    case VE::VGTUsirl_v:
    case VE::VGTUsiz:
    case VE::VGTUsizL:
    case VE::VGTUsizL_v:
    case VE::VGTUsiz_v:
    case VE::VGTUsizl:
    case VE::VGTUsizl_v:
    case VE::VGTUsrr:
    case VE::VGTUsrrL:
    case VE::VGTUsrrL_v:
    case VE::VGTUsrr_v:
    case VE::VGTUsrrl:
    case VE::VGTUsrrl_v:
    case VE::VGTUsrz:
    case VE::VGTUsrzL:
    case VE::VGTUsrzL_v:
    case VE::VGTUsrz_v:
    case VE::VGTUsrzl:
    case VE::VGTUsrzl_v:
    case VE::VGTsir:
    case VE::VGTsirL:
    case VE::VGTsirL_v:
    case VE::VGTsir_v:
    case VE::VGTsirl:
    case VE::VGTsirl_v:
    case VE::VGTsiz:
    case VE::VGTsizL:
    case VE::VGTsizL_v:
    case VE::VGTsiz_v:
    case VE::VGTsizl:
    case VE::VGTsizl_v:
    case VE::VGTsrr:
    case VE::VGTsrrL:
    case VE::VGTsrrL_v:
    case VE::VGTsrr_v:
    case VE::VGTsrrl:
    case VE::VGTsrrl_v:
    case VE::VGTsrz:
    case VE::VGTsrzL:
    case VE::VGTsrzL_v:
    case VE::VGTsrz_v:
    case VE::VGTsrzl:
    case VE::VGTsrzl_v: {
      switch (OpNum) {
      case 2:
        // op: sy
        return 40;
      case 3:
        // op: sz
        return 32;
      case 0:
        // op: vx
        return 24;
      case 1:
        // op: sw
        return 0;
      }
      break;
    }
    case VE::VGTLSXNCvir:
    case VE::VGTLSXNCvirL:
    case VE::VGTLSXNCvirL_v:
    case VE::VGTLSXNCvir_v:
    case VE::VGTLSXNCvirl:
    case VE::VGTLSXNCvirl_v:
    case VE::VGTLSXNCviz:
    case VE::VGTLSXNCvizL:
    case VE::VGTLSXNCvizL_v:
    case VE::VGTLSXNCviz_v:
    case VE::VGTLSXNCvizl:
    case VE::VGTLSXNCvizl_v:
    case VE::VGTLSXNCvrr:
    case VE::VGTLSXNCvrrL:
    case VE::VGTLSXNCvrrL_v:
    case VE::VGTLSXNCvrr_v:
    case VE::VGTLSXNCvrrl:
    case VE::VGTLSXNCvrrl_v:
    case VE::VGTLSXNCvrz:
    case VE::VGTLSXNCvrzL:
    case VE::VGTLSXNCvrzL_v:
    case VE::VGTLSXNCvrz_v:
    case VE::VGTLSXNCvrzl:
    case VE::VGTLSXNCvrzl_v:
    case VE::VGTLSXvir:
    case VE::VGTLSXvirL:
    case VE::VGTLSXvirL_v:
    case VE::VGTLSXvir_v:
    case VE::VGTLSXvirl:
    case VE::VGTLSXvirl_v:
    case VE::VGTLSXviz:
    case VE::VGTLSXvizL:
    case VE::VGTLSXvizL_v:
    case VE::VGTLSXviz_v:
    case VE::VGTLSXvizl:
    case VE::VGTLSXvizl_v:
    case VE::VGTLSXvrr:
    case VE::VGTLSXvrrL:
    case VE::VGTLSXvrrL_v:
    case VE::VGTLSXvrr_v:
    case VE::VGTLSXvrrl:
    case VE::VGTLSXvrrl_v:
    case VE::VGTLSXvrz:
    case VE::VGTLSXvrzL:
    case VE::VGTLSXvrzL_v:
    case VE::VGTLSXvrz_v:
    case VE::VGTLSXvrzl:
    case VE::VGTLSXvrzl_v:
    case VE::VGTLZXNCvir:
    case VE::VGTLZXNCvirL:
    case VE::VGTLZXNCvirL_v:
    case VE::VGTLZXNCvir_v:
    case VE::VGTLZXNCvirl:
    case VE::VGTLZXNCvirl_v:
    case VE::VGTLZXNCviz:
    case VE::VGTLZXNCvizL:
    case VE::VGTLZXNCvizL_v:
    case VE::VGTLZXNCviz_v:
    case VE::VGTLZXNCvizl:
    case VE::VGTLZXNCvizl_v:
    case VE::VGTLZXNCvrr:
    case VE::VGTLZXNCvrrL:
    case VE::VGTLZXNCvrrL_v:
    case VE::VGTLZXNCvrr_v:
    case VE::VGTLZXNCvrrl:
    case VE::VGTLZXNCvrrl_v:
    case VE::VGTLZXNCvrz:
    case VE::VGTLZXNCvrzL:
    case VE::VGTLZXNCvrzL_v:
    case VE::VGTLZXNCvrz_v:
    case VE::VGTLZXNCvrzl:
    case VE::VGTLZXNCvrzl_v:
    case VE::VGTLZXvir:
    case VE::VGTLZXvirL:
    case VE::VGTLZXvirL_v:
    case VE::VGTLZXvir_v:
    case VE::VGTLZXvirl:
    case VE::VGTLZXvirl_v:
    case VE::VGTLZXviz:
    case VE::VGTLZXvizL:
    case VE::VGTLZXvizL_v:
    case VE::VGTLZXviz_v:
    case VE::VGTLZXvizl:
    case VE::VGTLZXvizl_v:
    case VE::VGTLZXvrr:
    case VE::VGTLZXvrrL:
    case VE::VGTLZXvrrL_v:
    case VE::VGTLZXvrr_v:
    case VE::VGTLZXvrrl:
    case VE::VGTLZXvrrl_v:
    case VE::VGTLZXvrz:
    case VE::VGTLZXvrzL:
    case VE::VGTLZXvrzL_v:
    case VE::VGTLZXvrz_v:
    case VE::VGTLZXvrzl:
    case VE::VGTLZXvrzl_v:
    case VE::VGTNCvir:
    case VE::VGTNCvirL:
    case VE::VGTNCvirL_v:
    case VE::VGTNCvir_v:
    case VE::VGTNCvirl:
    case VE::VGTNCvirl_v:
    case VE::VGTNCviz:
    case VE::VGTNCvizL:
    case VE::VGTNCvizL_v:
    case VE::VGTNCviz_v:
    case VE::VGTNCvizl:
    case VE::VGTNCvizl_v:
    case VE::VGTNCvrr:
    case VE::VGTNCvrrL:
    case VE::VGTNCvrrL_v:
    case VE::VGTNCvrr_v:
    case VE::VGTNCvrrl:
    case VE::VGTNCvrrl_v:
    case VE::VGTNCvrz:
    case VE::VGTNCvrzL:
    case VE::VGTNCvrzL_v:
    case VE::VGTNCvrz_v:
    case VE::VGTNCvrzl:
    case VE::VGTNCvrzl_v:
    case VE::VGTUNCvir:
    case VE::VGTUNCvirL:
    case VE::VGTUNCvirL_v:
    case VE::VGTUNCvir_v:
    case VE::VGTUNCvirl:
    case VE::VGTUNCvirl_v:
    case VE::VGTUNCviz:
    case VE::VGTUNCvizL:
    case VE::VGTUNCvizL_v:
    case VE::VGTUNCviz_v:
    case VE::VGTUNCvizl:
    case VE::VGTUNCvizl_v:
    case VE::VGTUNCvrr:
    case VE::VGTUNCvrrL:
    case VE::VGTUNCvrrL_v:
    case VE::VGTUNCvrr_v:
    case VE::VGTUNCvrrl:
    case VE::VGTUNCvrrl_v:
    case VE::VGTUNCvrz:
    case VE::VGTUNCvrzL:
    case VE::VGTUNCvrzL_v:
    case VE::VGTUNCvrz_v:
    case VE::VGTUNCvrzl:
    case VE::VGTUNCvrzl_v:
    case VE::VGTUvir:
    case VE::VGTUvirL:
    case VE::VGTUvirL_v:
    case VE::VGTUvir_v:
    case VE::VGTUvirl:
    case VE::VGTUvirl_v:
    case VE::VGTUviz:
    case VE::VGTUvizL:
    case VE::VGTUvizL_v:
    case VE::VGTUviz_v:
    case VE::VGTUvizl:
    case VE::VGTUvizl_v:
    case VE::VGTUvrr:
    case VE::VGTUvrrL:
    case VE::VGTUvrrL_v:
    case VE::VGTUvrr_v:
    case VE::VGTUvrrl:
    case VE::VGTUvrrl_v:
    case VE::VGTUvrz:
    case VE::VGTUvrzL:
    case VE::VGTUvrzL_v:
    case VE::VGTUvrz_v:
    case VE::VGTUvrzl:
    case VE::VGTUvrzl_v:
    case VE::VGTvir:
    case VE::VGTvirL:
    case VE::VGTvirL_v:
    case VE::VGTvir_v:
    case VE::VGTvirl:
    case VE::VGTvirl_v:
    case VE::VGTviz:
    case VE::VGTvizL:
    case VE::VGTvizL_v:
    case VE::VGTviz_v:
    case VE::VGTvizl:
    case VE::VGTvizl_v:
    case VE::VGTvrr:
    case VE::VGTvrrL:
    case VE::VGTvrrL_v:
    case VE::VGTvrr_v:
    case VE::VGTvrrl:
    case VE::VGTvrrl_v:
    case VE::VGTvrz:
    case VE::VGTvrzL:
    case VE::VGTvrzL_v:
    case VE::VGTvrz_v:
    case VE::VGTvrzl:
    case VE::VGTvrzl_v: {
      switch (OpNum) {
      case 2:
        // op: sy
        return 40;
      case 3:
        // op: sz
        return 32;
      case 0:
        // op: vx
        return 24;
      case 1:
        // op: vy
        return 16;
      }
      break;
    }
    case VE::VSFAvim:
    case VE::VSFAvimL:
    case VE::VSFAvimL_v:
    case VE::VSFAvim_v:
    case VE::VSFAviml:
    case VE::VSFAviml_v:
    case VE::VSFAvir:
    case VE::VSFAvirL:
    case VE::VSFAvirL_v:
    case VE::VSFAvir_v:
    case VE::VSFAvirl:
    case VE::VSFAvirl_v:
    case VE::VSFAvrm:
    case VE::VSFAvrmL:
    case VE::VSFAvrmL_v:
    case VE::VSFAvrm_v:
    case VE::VSFAvrml:
    case VE::VSFAvrml_v:
    case VE::VSFAvrr:
    case VE::VSFAvrrL:
    case VE::VSFAvrrL_v:
    case VE::VSFAvrr_v:
    case VE::VSFAvrrl:
    case VE::VSFAvrrl_v: {
      switch (OpNum) {
      case 2:
        // op: sy
        return 40;
      case 3:
        // op: sz
        return 32;
      case 0:
        // op: vx
        return 24;
      case 1:
        // op: vz
        return 8;
      }
      break;
    }
    case VE::VST2DNCOTirvm:
    case VE::VST2DNCOTirvmL:
    case VE::VST2DNCOTirvml:
    case VE::VST2DNCOTizvm:
    case VE::VST2DNCOTizvmL:
    case VE::VST2DNCOTizvml:
    case VE::VST2DNCOTrrvm:
    case VE::VST2DNCOTrrvmL:
    case VE::VST2DNCOTrrvml:
    case VE::VST2DNCOTrzvm:
    case VE::VST2DNCOTrzvmL:
    case VE::VST2DNCOTrzvml:
    case VE::VST2DNCirvm:
    case VE::VST2DNCirvmL:
    case VE::VST2DNCirvml:
    case VE::VST2DNCizvm:
    case VE::VST2DNCizvmL:
    case VE::VST2DNCizvml:
    case VE::VST2DNCrrvm:
    case VE::VST2DNCrrvmL:
    case VE::VST2DNCrrvml:
    case VE::VST2DNCrzvm:
    case VE::VST2DNCrzvmL:
    case VE::VST2DNCrzvml:
    case VE::VST2DOTirvm:
    case VE::VST2DOTirvmL:
    case VE::VST2DOTirvml:
    case VE::VST2DOTizvm:
    case VE::VST2DOTizvmL:
    case VE::VST2DOTizvml:
    case VE::VST2DOTrrvm:
    case VE::VST2DOTrrvmL:
    case VE::VST2DOTrrvml:
    case VE::VST2DOTrzvm:
    case VE::VST2DOTrzvmL:
    case VE::VST2DOTrzvml:
    case VE::VST2Dirvm:
    case VE::VST2DirvmL:
    case VE::VST2Dirvml:
    case VE::VST2Dizvm:
    case VE::VST2DizvmL:
    case VE::VST2Dizvml:
    case VE::VST2Drrvm:
    case VE::VST2DrrvmL:
    case VE::VST2Drrvml:
    case VE::VST2Drzvm:
    case VE::VST2DrzvmL:
    case VE::VST2Drzvml:
    case VE::VSTL2DNCOTirvm:
    case VE::VSTL2DNCOTirvmL:
    case VE::VSTL2DNCOTirvml:
    case VE::VSTL2DNCOTizvm:
    case VE::VSTL2DNCOTizvmL:
    case VE::VSTL2DNCOTizvml:
    case VE::VSTL2DNCOTrrvm:
    case VE::VSTL2DNCOTrrvmL:
    case VE::VSTL2DNCOTrrvml:
    case VE::VSTL2DNCOTrzvm:
    case VE::VSTL2DNCOTrzvmL:
    case VE::VSTL2DNCOTrzvml:
    case VE::VSTL2DNCirvm:
    case VE::VSTL2DNCirvmL:
    case VE::VSTL2DNCirvml:
    case VE::VSTL2DNCizvm:
    case VE::VSTL2DNCizvmL:
    case VE::VSTL2DNCizvml:
    case VE::VSTL2DNCrrvm:
    case VE::VSTL2DNCrrvmL:
    case VE::VSTL2DNCrrvml:
    case VE::VSTL2DNCrzvm:
    case VE::VSTL2DNCrzvmL:
    case VE::VSTL2DNCrzvml:
    case VE::VSTL2DOTirvm:
    case VE::VSTL2DOTirvmL:
    case VE::VSTL2DOTirvml:
    case VE::VSTL2DOTizvm:
    case VE::VSTL2DOTizvmL:
    case VE::VSTL2DOTizvml:
    case VE::VSTL2DOTrrvm:
    case VE::VSTL2DOTrrvmL:
    case VE::VSTL2DOTrrvml:
    case VE::VSTL2DOTrzvm:
    case VE::VSTL2DOTrzvmL:
    case VE::VSTL2DOTrzvml:
    case VE::VSTL2Dirvm:
    case VE::VSTL2DirvmL:
    case VE::VSTL2Dirvml:
    case VE::VSTL2Dizvm:
    case VE::VSTL2DizvmL:
    case VE::VSTL2Dizvml:
    case VE::VSTL2Drrvm:
    case VE::VSTL2DrrvmL:
    case VE::VSTL2Drrvml:
    case VE::VSTL2Drzvm:
    case VE::VSTL2DrzvmL:
    case VE::VSTL2Drzvml:
    case VE::VSTLNCOTirvm:
    case VE::VSTLNCOTirvmL:
    case VE::VSTLNCOTirvml:
    case VE::VSTLNCOTizvm:
    case VE::VSTLNCOTizvmL:
    case VE::VSTLNCOTizvml:
    case VE::VSTLNCOTrrvm:
    case VE::VSTLNCOTrrvmL:
    case VE::VSTLNCOTrrvml:
    case VE::VSTLNCOTrzvm:
    case VE::VSTLNCOTrzvmL:
    case VE::VSTLNCOTrzvml:
    case VE::VSTLNCirvm:
    case VE::VSTLNCirvmL:
    case VE::VSTLNCirvml:
    case VE::VSTLNCizvm:
    case VE::VSTLNCizvmL:
    case VE::VSTLNCizvml:
    case VE::VSTLNCrrvm:
    case VE::VSTLNCrrvmL:
    case VE::VSTLNCrrvml:
    case VE::VSTLNCrzvm:
    case VE::VSTLNCrzvmL:
    case VE::VSTLNCrzvml:
    case VE::VSTLOTirvm:
    case VE::VSTLOTirvmL:
    case VE::VSTLOTirvml:
    case VE::VSTLOTizvm:
    case VE::VSTLOTizvmL:
    case VE::VSTLOTizvml:
    case VE::VSTLOTrrvm:
    case VE::VSTLOTrrvmL:
    case VE::VSTLOTrrvml:
    case VE::VSTLOTrzvm:
    case VE::VSTLOTrzvmL:
    case VE::VSTLOTrzvml:
    case VE::VSTLirvm:
    case VE::VSTLirvmL:
    case VE::VSTLirvml:
    case VE::VSTLizvm:
    case VE::VSTLizvmL:
    case VE::VSTLizvml:
    case VE::VSTLrrvm:
    case VE::VSTLrrvmL:
    case VE::VSTLrrvml:
    case VE::VSTLrzvm:
    case VE::VSTLrzvmL:
    case VE::VSTLrzvml:
    case VE::VSTNCOTirvm:
    case VE::VSTNCOTirvmL:
    case VE::VSTNCOTirvml:
    case VE::VSTNCOTizvm:
    case VE::VSTNCOTizvmL:
    case VE::VSTNCOTizvml:
    case VE::VSTNCOTrrvm:
    case VE::VSTNCOTrrvmL:
    case VE::VSTNCOTrrvml:
    case VE::VSTNCOTrzvm:
    case VE::VSTNCOTrzvmL:
    case VE::VSTNCOTrzvml:
    case VE::VSTNCirvm:
    case VE::VSTNCirvmL:
    case VE::VSTNCirvml:
    case VE::VSTNCizvm:
    case VE::VSTNCizvmL:
    case VE::VSTNCizvml:
    case VE::VSTNCrrvm:
    case VE::VSTNCrrvmL:
    case VE::VSTNCrrvml:
    case VE::VSTNCrzvm:
    case VE::VSTNCrzvmL:
    case VE::VSTNCrzvml:
    case VE::VSTOTirvm:
    case VE::VSTOTirvmL:
    case VE::VSTOTirvml:
    case VE::VSTOTizvm:
    case VE::VSTOTizvmL:
    case VE::VSTOTizvml:
    case VE::VSTOTrrvm:
    case VE::VSTOTrrvmL:
    case VE::VSTOTrrvml:
    case VE::VSTOTrzvm:
    case VE::VSTOTrzvmL:
    case VE::VSTOTrzvml:
    case VE::VSTU2DNCOTirvm:
    case VE::VSTU2DNCOTirvmL:
    case VE::VSTU2DNCOTirvml:
    case VE::VSTU2DNCOTizvm:
    case VE::VSTU2DNCOTizvmL:
    case VE::VSTU2DNCOTizvml:
    case VE::VSTU2DNCOTrrvm:
    case VE::VSTU2DNCOTrrvmL:
    case VE::VSTU2DNCOTrrvml:
    case VE::VSTU2DNCOTrzvm:
    case VE::VSTU2DNCOTrzvmL:
    case VE::VSTU2DNCOTrzvml:
    case VE::VSTU2DNCirvm:
    case VE::VSTU2DNCirvmL:
    case VE::VSTU2DNCirvml:
    case VE::VSTU2DNCizvm:
    case VE::VSTU2DNCizvmL:
    case VE::VSTU2DNCizvml:
    case VE::VSTU2DNCrrvm:
    case VE::VSTU2DNCrrvmL:
    case VE::VSTU2DNCrrvml:
    case VE::VSTU2DNCrzvm:
    case VE::VSTU2DNCrzvmL:
    case VE::VSTU2DNCrzvml:
    case VE::VSTU2DOTirvm:
    case VE::VSTU2DOTirvmL:
    case VE::VSTU2DOTirvml:
    case VE::VSTU2DOTizvm:
    case VE::VSTU2DOTizvmL:
    case VE::VSTU2DOTizvml:
    case VE::VSTU2DOTrrvm:
    case VE::VSTU2DOTrrvmL:
    case VE::VSTU2DOTrrvml:
    case VE::VSTU2DOTrzvm:
    case VE::VSTU2DOTrzvmL:
    case VE::VSTU2DOTrzvml:
    case VE::VSTU2Dirvm:
    case VE::VSTU2DirvmL:
    case VE::VSTU2Dirvml:
    case VE::VSTU2Dizvm:
    case VE::VSTU2DizvmL:
    case VE::VSTU2Dizvml:
    case VE::VSTU2Drrvm:
    case VE::VSTU2DrrvmL:
    case VE::VSTU2Drrvml:
    case VE::VSTU2Drzvm:
    case VE::VSTU2DrzvmL:
    case VE::VSTU2Drzvml:
    case VE::VSTUNCOTirvm:
    case VE::VSTUNCOTirvmL:
    case VE::VSTUNCOTirvml:
    case VE::VSTUNCOTizvm:
    case VE::VSTUNCOTizvmL:
    case VE::VSTUNCOTizvml:
    case VE::VSTUNCOTrrvm:
    case VE::VSTUNCOTrrvmL:
    case VE::VSTUNCOTrrvml:
    case VE::VSTUNCOTrzvm:
    case VE::VSTUNCOTrzvmL:
    case VE::VSTUNCOTrzvml:
    case VE::VSTUNCirvm:
    case VE::VSTUNCirvmL:
    case VE::VSTUNCirvml:
    case VE::VSTUNCizvm:
    case VE::VSTUNCizvmL:
    case VE::VSTUNCizvml:
    case VE::VSTUNCrrvm:
    case VE::VSTUNCrrvmL:
    case VE::VSTUNCrrvml:
    case VE::VSTUNCrzvm:
    case VE::VSTUNCrzvmL:
    case VE::VSTUNCrzvml:
    case VE::VSTUOTirvm:
    case VE::VSTUOTirvmL:
    case VE::VSTUOTirvml:
    case VE::VSTUOTizvm:
    case VE::VSTUOTizvmL:
    case VE::VSTUOTizvml:
    case VE::VSTUOTrrvm:
    case VE::VSTUOTrrvmL:
    case VE::VSTUOTrrvml:
    case VE::VSTUOTrzvm:
    case VE::VSTUOTrzvmL:
    case VE::VSTUOTrzvml:
    case VE::VSTUirvm:
    case VE::VSTUirvmL:
    case VE::VSTUirvml:
    case VE::VSTUizvm:
    case VE::VSTUizvmL:
    case VE::VSTUizvml:
    case VE::VSTUrrvm:
    case VE::VSTUrrvmL:
    case VE::VSTUrrvml:
    case VE::VSTUrzvm:
    case VE::VSTUrzvmL:
    case VE::VSTUrzvml:
    case VE::VSTirvm:
    case VE::VSTirvmL:
    case VE::VSTirvml:
    case VE::VSTizvm:
    case VE::VSTizvmL:
    case VE::VSTizvml:
    case VE::VSTrrvm:
    case VE::VSTrrvmL:
    case VE::VSTrrvml:
    case VE::VSTrzvm:
    case VE::VSTrzvmL:
    case VE::VSTrzvml: {
      switch (OpNum) {
      case 3:
        // op: m
        return 48;
      case 0:
        // op: sy
        return 40;
      case 1:
        // op: sz
        return 32;
      case 2:
        // op: vx
        return 24;
      }
      break;
    }
    case VE::PVADDSLOvvm:
    case VE::PVADDSLOvvmL:
    case VE::PVADDSLOvvmL_v:
    case VE::PVADDSLOvvm_v:
    case VE::PVADDSLOvvml:
    case VE::PVADDSLOvvml_v:
    case VE::PVADDSUPvvm:
    case VE::PVADDSUPvvmL:
    case VE::PVADDSUPvvmL_v:
    case VE::PVADDSUPvvm_v:
    case VE::PVADDSUPvvml:
    case VE::PVADDSUPvvml_v:
    case VE::PVADDSvvm:
    case VE::PVADDSvvmL:
    case VE::PVADDSvvmL_v:
    case VE::PVADDSvvm_v:
    case VE::PVADDSvvml:
    case VE::PVADDSvvml_v:
    case VE::PVADDULOvvm:
    case VE::PVADDULOvvmL:
    case VE::PVADDULOvvmL_v:
    case VE::PVADDULOvvm_v:
    case VE::PVADDULOvvml:
    case VE::PVADDULOvvml_v:
    case VE::PVADDUUPvvm:
    case VE::PVADDUUPvvmL:
    case VE::PVADDUUPvvmL_v:
    case VE::PVADDUUPvvm_v:
    case VE::PVADDUUPvvml:
    case VE::PVADDUUPvvml_v:
    case VE::PVADDUvvm:
    case VE::PVADDUvvmL:
    case VE::PVADDUvvmL_v:
    case VE::PVADDUvvm_v:
    case VE::PVADDUvvml:
    case VE::PVADDUvvml_v:
    case VE::PVANDLOvvm:
    case VE::PVANDLOvvmL:
    case VE::PVANDLOvvmL_v:
    case VE::PVANDLOvvm_v:
    case VE::PVANDLOvvml:
    case VE::PVANDLOvvml_v:
    case VE::PVANDUPvvm:
    case VE::PVANDUPvvmL:
    case VE::PVANDUPvvmL_v:
    case VE::PVANDUPvvm_v:
    case VE::PVANDUPvvml:
    case VE::PVANDUPvvml_v:
    case VE::PVANDvvm:
    case VE::PVANDvvmL:
    case VE::PVANDvvmL_v:
    case VE::PVANDvvm_v:
    case VE::PVANDvvml:
    case VE::PVANDvvml_v:
    case VE::PVCMPSLOvvm:
    case VE::PVCMPSLOvvmL:
    case VE::PVCMPSLOvvmL_v:
    case VE::PVCMPSLOvvm_v:
    case VE::PVCMPSLOvvml:
    case VE::PVCMPSLOvvml_v:
    case VE::PVCMPSUPvvm:
    case VE::PVCMPSUPvvmL:
    case VE::PVCMPSUPvvmL_v:
    case VE::PVCMPSUPvvm_v:
    case VE::PVCMPSUPvvml:
    case VE::PVCMPSUPvvml_v:
    case VE::PVCMPSvvm:
    case VE::PVCMPSvvmL:
    case VE::PVCMPSvvmL_v:
    case VE::PVCMPSvvm_v:
    case VE::PVCMPSvvml:
    case VE::PVCMPSvvml_v:
    case VE::PVCMPULOvvm:
    case VE::PVCMPULOvvmL:
    case VE::PVCMPULOvvmL_v:
    case VE::PVCMPULOvvm_v:
    case VE::PVCMPULOvvml:
    case VE::PVCMPULOvvml_v:
    case VE::PVCMPUUPvvm:
    case VE::PVCMPUUPvvmL:
    case VE::PVCMPUUPvvmL_v:
    case VE::PVCMPUUPvvm_v:
    case VE::PVCMPUUPvvml:
    case VE::PVCMPUUPvvml_v:
    case VE::PVCMPUvvm:
    case VE::PVCMPUvvmL:
    case VE::PVCMPUvvmL_v:
    case VE::PVCMPUvvm_v:
    case VE::PVCMPUvvml:
    case VE::PVCMPUvvml_v:
    case VE::PVEQVLOvvm:
    case VE::PVEQVLOvvmL:
    case VE::PVEQVLOvvmL_v:
    case VE::PVEQVLOvvm_v:
    case VE::PVEQVLOvvml:
    case VE::PVEQVLOvvml_v:
    case VE::PVEQVUPvvm:
    case VE::PVEQVUPvvmL:
    case VE::PVEQVUPvvmL_v:
    case VE::PVEQVUPvvm_v:
    case VE::PVEQVUPvvml:
    case VE::PVEQVUPvvml_v:
    case VE::PVEQVvvm:
    case VE::PVEQVvvmL:
    case VE::PVEQVvvmL_v:
    case VE::PVEQVvvm_v:
    case VE::PVEQVvvml:
    case VE::PVEQVvvml_v:
    case VE::PVFADDLOvvm:
    case VE::PVFADDLOvvmL:
    case VE::PVFADDLOvvmL_v:
    case VE::PVFADDLOvvm_v:
    case VE::PVFADDLOvvml:
    case VE::PVFADDLOvvml_v:
    case VE::PVFADDUPvvm:
    case VE::PVFADDUPvvmL:
    case VE::PVFADDUPvvmL_v:
    case VE::PVFADDUPvvm_v:
    case VE::PVFADDUPvvml:
    case VE::PVFADDUPvvml_v:
    case VE::PVFADDvvm:
    case VE::PVFADDvvmL:
    case VE::PVFADDvvmL_v:
    case VE::PVFADDvvm_v:
    case VE::PVFADDvvml:
    case VE::PVFADDvvml_v:
    case VE::PVFCMPLOvvm:
    case VE::PVFCMPLOvvmL:
    case VE::PVFCMPLOvvmL_v:
    case VE::PVFCMPLOvvm_v:
    case VE::PVFCMPLOvvml:
    case VE::PVFCMPLOvvml_v:
    case VE::PVFCMPUPvvm:
    case VE::PVFCMPUPvvmL:
    case VE::PVFCMPUPvvmL_v:
    case VE::PVFCMPUPvvm_v:
    case VE::PVFCMPUPvvml:
    case VE::PVFCMPUPvvml_v:
    case VE::PVFCMPvvm:
    case VE::PVFCMPvvmL:
    case VE::PVFCMPvvmL_v:
    case VE::PVFCMPvvm_v:
    case VE::PVFCMPvvml:
    case VE::PVFCMPvvml_v:
    case VE::PVFMAXLOvvm:
    case VE::PVFMAXLOvvmL:
    case VE::PVFMAXLOvvmL_v:
    case VE::PVFMAXLOvvm_v:
    case VE::PVFMAXLOvvml:
    case VE::PVFMAXLOvvml_v:
    case VE::PVFMAXUPvvm:
    case VE::PVFMAXUPvvmL:
    case VE::PVFMAXUPvvmL_v:
    case VE::PVFMAXUPvvm_v:
    case VE::PVFMAXUPvvml:
    case VE::PVFMAXUPvvml_v:
    case VE::PVFMAXvvm:
    case VE::PVFMAXvvmL:
    case VE::PVFMAXvvmL_v:
    case VE::PVFMAXvvm_v:
    case VE::PVFMAXvvml:
    case VE::PVFMAXvvml_v:
    case VE::PVFMINLOvvm:
    case VE::PVFMINLOvvmL:
    case VE::PVFMINLOvvmL_v:
    case VE::PVFMINLOvvm_v:
    case VE::PVFMINLOvvml:
    case VE::PVFMINLOvvml_v:
    case VE::PVFMINUPvvm:
    case VE::PVFMINUPvvmL:
    case VE::PVFMINUPvvmL_v:
    case VE::PVFMINUPvvm_v:
    case VE::PVFMINUPvvml:
    case VE::PVFMINUPvvml_v:
    case VE::PVFMINvvm:
    case VE::PVFMINvvmL:
    case VE::PVFMINvvmL_v:
    case VE::PVFMINvvm_v:
    case VE::PVFMINvvml:
    case VE::PVFMINvvml_v:
    case VE::PVFMKSLOvm:
    case VE::PVFMKSLOvmL:
    case VE::PVFMKSLOvml:
    case VE::PVFMKSUPvm:
    case VE::PVFMKSUPvmL:
    case VE::PVFMKSUPvml:
    case VE::PVFMKWLOvm:
    case VE::PVFMKWLOvmL:
    case VE::PVFMKWLOvml:
    case VE::PVFMKWUPvm:
    case VE::PVFMKWUPvmL:
    case VE::PVFMKWUPvml:
    case VE::PVFMULLOvvm:
    case VE::PVFMULLOvvmL:
    case VE::PVFMULLOvvmL_v:
    case VE::PVFMULLOvvm_v:
    case VE::PVFMULLOvvml:
    case VE::PVFMULLOvvml_v:
    case VE::PVFMULUPvvm:
    case VE::PVFMULUPvvmL:
    case VE::PVFMULUPvvmL_v:
    case VE::PVFMULUPvvm_v:
    case VE::PVFMULUPvvml:
    case VE::PVFMULUPvvml_v:
    case VE::PVFMULvvm:
    case VE::PVFMULvvmL:
    case VE::PVFMULvvmL_v:
    case VE::PVFMULvvm_v:
    case VE::PVFMULvvml:
    case VE::PVFMULvvml_v:
    case VE::PVFSUBLOvvm:
    case VE::PVFSUBLOvvmL:
    case VE::PVFSUBLOvvmL_v:
    case VE::PVFSUBLOvvm_v:
    case VE::PVFSUBLOvvml:
    case VE::PVFSUBLOvvml_v:
    case VE::PVFSUBUPvvm:
    case VE::PVFSUBUPvvmL:
    case VE::PVFSUBUPvvmL_v:
    case VE::PVFSUBUPvvm_v:
    case VE::PVFSUBUPvvml:
    case VE::PVFSUBUPvvml_v:
    case VE::PVFSUBvvm:
    case VE::PVFSUBvvmL:
    case VE::PVFSUBvvmL_v:
    case VE::PVFSUBvvm_v:
    case VE::PVFSUBvvml:
    case VE::PVFSUBvvml_v:
    case VE::PVMAXSLOvvm:
    case VE::PVMAXSLOvvmL:
    case VE::PVMAXSLOvvmL_v:
    case VE::PVMAXSLOvvm_v:
    case VE::PVMAXSLOvvml:
    case VE::PVMAXSLOvvml_v:
    case VE::PVMAXSUPvvm:
    case VE::PVMAXSUPvvmL:
    case VE::PVMAXSUPvvmL_v:
    case VE::PVMAXSUPvvm_v:
    case VE::PVMAXSUPvvml:
    case VE::PVMAXSUPvvml_v:
    case VE::PVMAXSvvm:
    case VE::PVMAXSvvmL:
    case VE::PVMAXSvvmL_v:
    case VE::PVMAXSvvm_v:
    case VE::PVMAXSvvml:
    case VE::PVMAXSvvml_v:
    case VE::PVMINSLOvvm:
    case VE::PVMINSLOvvmL:
    case VE::PVMINSLOvvmL_v:
    case VE::PVMINSLOvvm_v:
    case VE::PVMINSLOvvml:
    case VE::PVMINSLOvvml_v:
    case VE::PVMINSUPvvm:
    case VE::PVMINSUPvvmL:
    case VE::PVMINSUPvvmL_v:
    case VE::PVMINSUPvvm_v:
    case VE::PVMINSUPvvml:
    case VE::PVMINSUPvvml_v:
    case VE::PVMINSvvm:
    case VE::PVMINSvvmL:
    case VE::PVMINSvvmL_v:
    case VE::PVMINSvvm_v:
    case VE::PVMINSvvml:
    case VE::PVMINSvvml_v:
    case VE::PVORLOvvm:
    case VE::PVORLOvvmL:
    case VE::PVORLOvvmL_v:
    case VE::PVORLOvvm_v:
    case VE::PVORLOvvml:
    case VE::PVORLOvvml_v:
    case VE::PVORUPvvm:
    case VE::PVORUPvvmL:
    case VE::PVORUPvvmL_v:
    case VE::PVORUPvvm_v:
    case VE::PVORUPvvml:
    case VE::PVORUPvvml_v:
    case VE::PVORvvm:
    case VE::PVORvvmL:
    case VE::PVORvvmL_v:
    case VE::PVORvvm_v:
    case VE::PVORvvml:
    case VE::PVORvvml_v:
    case VE::PVSUBSLOvvm:
    case VE::PVSUBSLOvvmL:
    case VE::PVSUBSLOvvmL_v:
    case VE::PVSUBSLOvvm_v:
    case VE::PVSUBSLOvvml:
    case VE::PVSUBSLOvvml_v:
    case VE::PVSUBSUPvvm:
    case VE::PVSUBSUPvvmL:
    case VE::PVSUBSUPvvmL_v:
    case VE::PVSUBSUPvvm_v:
    case VE::PVSUBSUPvvml:
    case VE::PVSUBSUPvvml_v:
    case VE::PVSUBSvvm:
    case VE::PVSUBSvvmL:
    case VE::PVSUBSvvmL_v:
    case VE::PVSUBSvvm_v:
    case VE::PVSUBSvvml:
    case VE::PVSUBSvvml_v:
    case VE::PVSUBULOvvm:
    case VE::PVSUBULOvvmL:
    case VE::PVSUBULOvvmL_v:
    case VE::PVSUBULOvvm_v:
    case VE::PVSUBULOvvml:
    case VE::PVSUBULOvvml_v:
    case VE::PVSUBUUPvvm:
    case VE::PVSUBUUPvvmL:
    case VE::PVSUBUUPvvmL_v:
    case VE::PVSUBUUPvvm_v:
    case VE::PVSUBUUPvvml:
    case VE::PVSUBUUPvvml_v:
    case VE::PVSUBUvvm:
    case VE::PVSUBUvvmL:
    case VE::PVSUBUvvmL_v:
    case VE::PVSUBUvvm_v:
    case VE::PVSUBUvvml:
    case VE::PVSUBUvvml_v:
    case VE::PVXORLOvvm:
    case VE::PVXORLOvvmL:
    case VE::PVXORLOvvmL_v:
    case VE::PVXORLOvvm_v:
    case VE::PVXORLOvvml:
    case VE::PVXORLOvvml_v:
    case VE::PVXORUPvvm:
    case VE::PVXORUPvvmL:
    case VE::PVXORUPvvmL_v:
    case VE::PVXORUPvvm_v:
    case VE::PVXORUPvvml:
    case VE::PVXORUPvvml_v:
    case VE::PVXORvvm:
    case VE::PVXORvvmL:
    case VE::PVXORvvmL_v:
    case VE::PVXORvvm_v:
    case VE::PVXORvvml:
    case VE::PVXORvvml_v:
    case VE::VADDSLvvm:
    case VE::VADDSLvvmL:
    case VE::VADDSLvvmL_v:
    case VE::VADDSLvvm_v:
    case VE::VADDSLvvml:
    case VE::VADDSLvvml_v:
    case VE::VADDSWSXvvm:
    case VE::VADDSWSXvvmL:
    case VE::VADDSWSXvvmL_v:
    case VE::VADDSWSXvvm_v:
    case VE::VADDSWSXvvml:
    case VE::VADDSWSXvvml_v:
    case VE::VADDSWZXvvm:
    case VE::VADDSWZXvvmL:
    case VE::VADDSWZXvvmL_v:
    case VE::VADDSWZXvvm_v:
    case VE::VADDSWZXvvml:
    case VE::VADDSWZXvvml_v:
    case VE::VADDULvvm:
    case VE::VADDULvvmL:
    case VE::VADDULvvmL_v:
    case VE::VADDULvvm_v:
    case VE::VADDULvvml:
    case VE::VADDULvvml_v:
    case VE::VADDUWvvm:
    case VE::VADDUWvvmL:
    case VE::VADDUWvvmL_v:
    case VE::VADDUWvvm_v:
    case VE::VADDUWvvml:
    case VE::VADDUWvvml_v:
    case VE::VANDvvm:
    case VE::VANDvvmL:
    case VE::VANDvvmL_v:
    case VE::VANDvvm_v:
    case VE::VANDvvml:
    case VE::VANDvvml_v:
    case VE::VCMPSLvvm:
    case VE::VCMPSLvvmL:
    case VE::VCMPSLvvmL_v:
    case VE::VCMPSLvvm_v:
    case VE::VCMPSLvvml:
    case VE::VCMPSLvvml_v:
    case VE::VCMPSWSXvvm:
    case VE::VCMPSWSXvvmL:
    case VE::VCMPSWSXvvmL_v:
    case VE::VCMPSWSXvvm_v:
    case VE::VCMPSWSXvvml:
    case VE::VCMPSWSXvvml_v:
    case VE::VCMPSWZXvvm:
    case VE::VCMPSWZXvvmL:
    case VE::VCMPSWZXvvmL_v:
    case VE::VCMPSWZXvvm_v:
    case VE::VCMPSWZXvvml:
    case VE::VCMPSWZXvvml_v:
    case VE::VCMPULvvm:
    case VE::VCMPULvvmL:
    case VE::VCMPULvvmL_v:
    case VE::VCMPULvvm_v:
    case VE::VCMPULvvml:
    case VE::VCMPULvvml_v:
    case VE::VCMPUWvvm:
    case VE::VCMPUWvvmL:
    case VE::VCMPUWvvmL_v:
    case VE::VCMPUWvvm_v:
    case VE::VCMPUWvvml:
    case VE::VCMPUWvvml_v:
    case VE::VDIVSLvvm:
    case VE::VDIVSLvvmL:
    case VE::VDIVSLvvmL_v:
    case VE::VDIVSLvvm_v:
    case VE::VDIVSLvvml:
    case VE::VDIVSLvvml_v:
    case VE::VDIVSWSXvvm:
    case VE::VDIVSWSXvvmL:
    case VE::VDIVSWSXvvmL_v:
    case VE::VDIVSWSXvvm_v:
    case VE::VDIVSWSXvvml:
    case VE::VDIVSWSXvvml_v:
    case VE::VDIVSWZXvvm:
    case VE::VDIVSWZXvvmL:
    case VE::VDIVSWZXvvmL_v:
    case VE::VDIVSWZXvvm_v:
    case VE::VDIVSWZXvvml:
    case VE::VDIVSWZXvvml_v:
    case VE::VDIVULvvm:
    case VE::VDIVULvvmL:
    case VE::VDIVULvvmL_v:
    case VE::VDIVULvvm_v:
    case VE::VDIVULvvml:
    case VE::VDIVULvvml_v:
    case VE::VDIVUWvvm:
    case VE::VDIVUWvvmL:
    case VE::VDIVUWvvmL_v:
    case VE::VDIVUWvvm_v:
    case VE::VDIVUWvvml:
    case VE::VDIVUWvvml_v:
    case VE::VEQVvvm:
    case VE::VEQVvvmL:
    case VE::VEQVvvmL_v:
    case VE::VEQVvvm_v:
    case VE::VEQVvvml:
    case VE::VEQVvvml_v:
    case VE::VFADDDvvm:
    case VE::VFADDDvvmL:
    case VE::VFADDDvvmL_v:
    case VE::VFADDDvvm_v:
    case VE::VFADDDvvml:
    case VE::VFADDDvvml_v:
    case VE::VFADDSvvm:
    case VE::VFADDSvvmL:
    case VE::VFADDSvvmL_v:
    case VE::VFADDSvvm_v:
    case VE::VFADDSvvml:
    case VE::VFADDSvvml_v:
    case VE::VFCMPDvvm:
    case VE::VFCMPDvvmL:
    case VE::VFCMPDvvmL_v:
    case VE::VFCMPDvvm_v:
    case VE::VFCMPDvvml:
    case VE::VFCMPDvvml_v:
    case VE::VFCMPSvvm:
    case VE::VFCMPSvvmL:
    case VE::VFCMPSvvmL_v:
    case VE::VFCMPSvvm_v:
    case VE::VFCMPSvvml:
    case VE::VFCMPSvvml_v:
    case VE::VFDIVDvvm:
    case VE::VFDIVDvvmL:
    case VE::VFDIVDvvmL_v:
    case VE::VFDIVDvvm_v:
    case VE::VFDIVDvvml:
    case VE::VFDIVDvvml_v:
    case VE::VFDIVSvvm:
    case VE::VFDIVSvvmL:
    case VE::VFDIVSvvmL_v:
    case VE::VFDIVSvvm_v:
    case VE::VFDIVSvvml:
    case VE::VFDIVSvvml_v:
    case VE::VFMAXDvvm:
    case VE::VFMAXDvvmL:
    case VE::VFMAXDvvmL_v:
    case VE::VFMAXDvvm_v:
    case VE::VFMAXDvvml:
    case VE::VFMAXDvvml_v:
    case VE::VFMAXSvvm:
    case VE::VFMAXSvvmL:
    case VE::VFMAXSvvmL_v:
    case VE::VFMAXSvvm_v:
    case VE::VFMAXSvvml:
    case VE::VFMAXSvvml_v:
    case VE::VFMINDvvm:
    case VE::VFMINDvvmL:
    case VE::VFMINDvvmL_v:
    case VE::VFMINDvvm_v:
    case VE::VFMINDvvml:
    case VE::VFMINDvvml_v:
    case VE::VFMINSvvm:
    case VE::VFMINSvvmL:
    case VE::VFMINSvvmL_v:
    case VE::VFMINSvvm_v:
    case VE::VFMINSvvml:
    case VE::VFMINSvvml_v:
    case VE::VFMKDvm:
    case VE::VFMKDvmL:
    case VE::VFMKDvml:
    case VE::VFMKLvm:
    case VE::VFMKLvmL:
    case VE::VFMKLvml:
    case VE::VFMKSvm:
    case VE::VFMKSvmL:
    case VE::VFMKSvml:
    case VE::VFMKWvm:
    case VE::VFMKWvmL:
    case VE::VFMKWvml:
    case VE::VFMULDvvm:
    case VE::VFMULDvvmL:
    case VE::VFMULDvvmL_v:
    case VE::VFMULDvvm_v:
    case VE::VFMULDvvml:
    case VE::VFMULDvvml_v:
    case VE::VFMULSvvm:
    case VE::VFMULSvvmL:
    case VE::VFMULSvvmL_v:
    case VE::VFMULSvvm_v:
    case VE::VFMULSvvml:
    case VE::VFMULSvvml_v:
    case VE::VFSUBDvvm:
    case VE::VFSUBDvvmL:
    case VE::VFSUBDvvmL_v:
    case VE::VFSUBDvvm_v:
    case VE::VFSUBDvvml:
    case VE::VFSUBDvvml_v:
    case VE::VFSUBSvvm:
    case VE::VFSUBSvvmL:
    case VE::VFSUBSvvmL_v:
    case VE::VFSUBSvvm_v:
    case VE::VFSUBSvvml:
    case VE::VFSUBSvvml_v:
    case VE::VMAXSLvvm:
    case VE::VMAXSLvvmL:
    case VE::VMAXSLvvmL_v:
    case VE::VMAXSLvvm_v:
    case VE::VMAXSLvvml:
    case VE::VMAXSLvvml_v:
    case VE::VMAXSWSXvvm:
    case VE::VMAXSWSXvvmL:
    case VE::VMAXSWSXvvmL_v:
    case VE::VMAXSWSXvvm_v:
    case VE::VMAXSWSXvvml:
    case VE::VMAXSWSXvvml_v:
    case VE::VMAXSWZXvvm:
    case VE::VMAXSWZXvvmL:
    case VE::VMAXSWZXvvmL_v:
    case VE::VMAXSWZXvvm_v:
    case VE::VMAXSWZXvvml:
    case VE::VMAXSWZXvvml_v:
    case VE::VMINSLvvm:
    case VE::VMINSLvvmL:
    case VE::VMINSLvvmL_v:
    case VE::VMINSLvvm_v:
    case VE::VMINSLvvml:
    case VE::VMINSLvvml_v:
    case VE::VMINSWSXvvm:
    case VE::VMINSWSXvvmL:
    case VE::VMINSWSXvvmL_v:
    case VE::VMINSWSXvvm_v:
    case VE::VMINSWSXvvml:
    case VE::VMINSWSXvvml_v:
    case VE::VMINSWZXvvm:
    case VE::VMINSWZXvvmL:
    case VE::VMINSWZXvvmL_v:
    case VE::VMINSWZXvvm_v:
    case VE::VMINSWZXvvml:
    case VE::VMINSWZXvvml_v:
    case VE::VMRGWvvm:
    case VE::VMRGWvvmL:
    case VE::VMRGWvvmL_v:
    case VE::VMRGWvvm_v:
    case VE::VMRGWvvml:
    case VE::VMRGWvvml_v:
    case VE::VMRGvvm:
    case VE::VMRGvvmL:
    case VE::VMRGvvmL_v:
    case VE::VMRGvvm_v:
    case VE::VMRGvvml:
    case VE::VMRGvvml_v:
    case VE::VMULSLWvvm:
    case VE::VMULSLWvvmL:
    case VE::VMULSLWvvmL_v:
    case VE::VMULSLWvvm_v:
    case VE::VMULSLWvvml:
    case VE::VMULSLWvvml_v:
    case VE::VMULSLvvm:
    case VE::VMULSLvvmL:
    case VE::VMULSLvvmL_v:
    case VE::VMULSLvvm_v:
    case VE::VMULSLvvml:
    case VE::VMULSLvvml_v:
    case VE::VMULSWSXvvm:
    case VE::VMULSWSXvvmL:
    case VE::VMULSWSXvvmL_v:
    case VE::VMULSWSXvvm_v:
    case VE::VMULSWSXvvml:
    case VE::VMULSWSXvvml_v:
    case VE::VMULSWZXvvm:
    case VE::VMULSWZXvvmL:
    case VE::VMULSWZXvvmL_v:
    case VE::VMULSWZXvvm_v:
    case VE::VMULSWZXvvml:
    case VE::VMULSWZXvvml_v:
    case VE::VMULULvvm:
    case VE::VMULULvvmL:
    case VE::VMULULvvmL_v:
    case VE::VMULULvvm_v:
    case VE::VMULULvvml:
    case VE::VMULULvvml_v:
    case VE::VMULUWvvm:
    case VE::VMULUWvvmL:
    case VE::VMULUWvvmL_v:
    case VE::VMULUWvvm_v:
    case VE::VMULUWvvml:
    case VE::VMULUWvvml_v:
    case VE::VORvvm:
    case VE::VORvvmL:
    case VE::VORvvmL_v:
    case VE::VORvvm_v:
    case VE::VORvvml:
    case VE::VORvvml_v:
    case VE::VSUBSLvvm:
    case VE::VSUBSLvvmL:
    case VE::VSUBSLvvmL_v:
    case VE::VSUBSLvvm_v:
    case VE::VSUBSLvvml:
    case VE::VSUBSLvvml_v:
    case VE::VSUBSWSXvvm:
    case VE::VSUBSWSXvvmL:
    case VE::VSUBSWSXvvmL_v:
    case VE::VSUBSWSXvvm_v:
    case VE::VSUBSWSXvvml:
    case VE::VSUBSWSXvvml_v:
    case VE::VSUBSWZXvvm:
    case VE::VSUBSWZXvvmL:
    case VE::VSUBSWZXvvmL_v:
    case VE::VSUBSWZXvvm_v:
    case VE::VSUBSWZXvvml:
    case VE::VSUBSWZXvvml_v:
    case VE::VSUBULvvm:
    case VE::VSUBULvvmL:
    case VE::VSUBULvvmL_v:
    case VE::VSUBULvvm_v:
    case VE::VSUBULvvml:
    case VE::VSUBULvvml_v:
    case VE::VSUBUWvvm:
    case VE::VSUBUWvvmL:
    case VE::VSUBUWvvmL_v:
    case VE::VSUBUWvvm_v:
    case VE::VSUBUWvvml:
    case VE::VSUBUWvvml_v:
    case VE::VXORvvm:
    case VE::VXORvvmL:
    case VE::VXORvvmL_v:
    case VE::VXORvvm_v:
    case VE::VXORvvml:
    case VE::VXORvvml_v: {
      switch (OpNum) {
      case 3:
        // op: m
        return 48;
      case 0:
        // op: vx
        return 24;
      case 1:
        // op: vy
        return 16;
      case 2:
        // op: vz
        return 8;
      }
      break;
    }
    case VE::PVCVTWSLOvm:
    case VE::PVCVTWSLOvmL:
    case VE::PVCVTWSLOvmL_v:
    case VE::PVCVTWSLOvm_v:
    case VE::PVCVTWSLOvml:
    case VE::PVCVTWSLOvml_v:
    case VE::PVCVTWSUPvm:
    case VE::PVCVTWSUPvmL:
    case VE::PVCVTWSUPvmL_v:
    case VE::PVCVTWSUPvm_v:
    case VE::PVCVTWSUPvml:
    case VE::PVCVTWSUPvml_v:
    case VE::PVCVTWSvm:
    case VE::PVCVTWSvmL:
    case VE::PVCVTWSvmL_v:
    case VE::PVCVTWSvm_v:
    case VE::PVCVTWSvml:
    case VE::PVCVTWSvml_v:
    case VE::PVSLALOvvm:
    case VE::PVSLALOvvmL:
    case VE::PVSLALOvvmL_v:
    case VE::PVSLALOvvm_v:
    case VE::PVSLALOvvml:
    case VE::PVSLALOvvml_v:
    case VE::PVSLAUPvvm:
    case VE::PVSLAUPvvmL:
    case VE::PVSLAUPvvmL_v:
    case VE::PVSLAUPvvm_v:
    case VE::PVSLAUPvvml:
    case VE::PVSLAUPvvml_v:
    case VE::PVSLAvvm:
    case VE::PVSLAvvmL:
    case VE::PVSLAvvmL_v:
    case VE::PVSLAvvm_v:
    case VE::PVSLAvvml:
    case VE::PVSLAvvml_v:
    case VE::PVSLLLOvvm:
    case VE::PVSLLLOvvmL:
    case VE::PVSLLLOvvmL_v:
    case VE::PVSLLLOvvm_v:
    case VE::PVSLLLOvvml:
    case VE::PVSLLLOvvml_v:
    case VE::PVSLLUPvvm:
    case VE::PVSLLUPvvmL:
    case VE::PVSLLUPvvmL_v:
    case VE::PVSLLUPvvm_v:
    case VE::PVSLLUPvvml:
    case VE::PVSLLUPvvml_v:
    case VE::PVSLLvvm:
    case VE::PVSLLvvmL:
    case VE::PVSLLvvmL_v:
    case VE::PVSLLvvm_v:
    case VE::PVSLLvvml:
    case VE::PVSLLvvml_v:
    case VE::PVSRALOvvm:
    case VE::PVSRALOvvmL:
    case VE::PVSRALOvvmL_v:
    case VE::PVSRALOvvm_v:
    case VE::PVSRALOvvml:
    case VE::PVSRALOvvml_v:
    case VE::PVSRAUPvvm:
    case VE::PVSRAUPvvmL:
    case VE::PVSRAUPvvmL_v:
    case VE::PVSRAUPvvm_v:
    case VE::PVSRAUPvvml:
    case VE::PVSRAUPvvml_v:
    case VE::PVSRAvvm:
    case VE::PVSRAvvmL:
    case VE::PVSRAvvmL_v:
    case VE::PVSRAvvm_v:
    case VE::PVSRAvvml:
    case VE::PVSRAvvml_v:
    case VE::PVSRLLOvvm:
    case VE::PVSRLLOvvmL:
    case VE::PVSRLLOvvmL_v:
    case VE::PVSRLLOvvm_v:
    case VE::PVSRLLOvvml:
    case VE::PVSRLLOvvml_v:
    case VE::PVSRLUPvvm:
    case VE::PVSRLUPvvmL:
    case VE::PVSRLUPvvmL_v:
    case VE::PVSRLUPvvm_v:
    case VE::PVSRLUPvvml:
    case VE::PVSRLUPvvml_v:
    case VE::PVSRLvvm:
    case VE::PVSRLvvmL:
    case VE::PVSRLvvmL_v:
    case VE::PVSRLvvm_v:
    case VE::PVSRLvvml:
    case VE::PVSRLvvml_v:
    case VE::VCVTLDvm:
    case VE::VCVTLDvmL:
    case VE::VCVTLDvmL_v:
    case VE::VCVTLDvm_v:
    case VE::VCVTLDvml:
    case VE::VCVTLDvml_v:
    case VE::VCVTWDSXvm:
    case VE::VCVTWDSXvmL:
    case VE::VCVTWDSXvmL_v:
    case VE::VCVTWDSXvm_v:
    case VE::VCVTWDSXvml:
    case VE::VCVTWDSXvml_v:
    case VE::VCVTWDZXvm:
    case VE::VCVTWDZXvmL:
    case VE::VCVTWDZXvmL_v:
    case VE::VCVTWDZXvm_v:
    case VE::VCVTWDZXvml:
    case VE::VCVTWDZXvml_v:
    case VE::VCVTWSSXvm:
    case VE::VCVTWSSXvmL:
    case VE::VCVTWSSXvmL_v:
    case VE::VCVTWSSXvm_v:
    case VE::VCVTWSSXvml:
    case VE::VCVTWSSXvml_v:
    case VE::VCVTWSZXvm:
    case VE::VCVTWSZXvmL:
    case VE::VCVTWSZXvmL_v:
    case VE::VCVTWSZXvm_v:
    case VE::VCVTWSZXvml:
    case VE::VCVTWSZXvml_v:
    case VE::VSLALvvm:
    case VE::VSLALvvmL:
    case VE::VSLALvvmL_v:
    case VE::VSLALvvm_v:
    case VE::VSLALvvml:
    case VE::VSLALvvml_v:
    case VE::VSLAWSXvvm:
    case VE::VSLAWSXvvmL:
    case VE::VSLAWSXvvmL_v:
    case VE::VSLAWSXvvm_v:
    case VE::VSLAWSXvvml:
    case VE::VSLAWSXvvml_v:
    case VE::VSLAWZXvvm:
    case VE::VSLAWZXvvmL:
    case VE::VSLAWZXvvmL_v:
    case VE::VSLAWZXvvm_v:
    case VE::VSLAWZXvvml:
    case VE::VSLAWZXvvml_v:
    case VE::VSLLvvm:
    case VE::VSLLvvmL:
    case VE::VSLLvvmL_v:
    case VE::VSLLvvm_v:
    case VE::VSLLvvml:
    case VE::VSLLvvml_v:
    case VE::VSRALvvm:
    case VE::VSRALvvmL:
    case VE::VSRALvvmL_v:
    case VE::VSRALvvm_v:
    case VE::VSRALvvml:
    case VE::VSRALvvml_v:
    case VE::VSRAWSXvvm:
    case VE::VSRAWSXvvmL:
    case VE::VSRAWSXvvmL_v:
    case VE::VSRAWSXvvm_v:
    case VE::VSRAWSXvvml:
    case VE::VSRAWSXvvml_v:
    case VE::VSRAWZXvvm:
    case VE::VSRAWZXvvmL:
    case VE::VSRAWZXvvmL_v:
    case VE::VSRAWZXvvm_v:
    case VE::VSRAWZXvvml:
    case VE::VSRAWZXvvml_v:
    case VE::VSRLvvm:
    case VE::VSRLvvmL:
    case VE::VSRLvvmL_v:
    case VE::VSRLvvm_v:
    case VE::VSRLvvml:
    case VE::VSRLvvml_v: {
      switch (OpNum) {
      case 3:
        // op: m
        return 48;
      case 0:
        // op: vx
        return 24;
      case 2:
        // op: vy
        return 16;
      case 1:
        // op: vz
        return 8;
      }
      break;
    }
    case VE::PVADDSLOivm:
    case VE::PVADDSLOivmL:
    case VE::PVADDSLOivmL_v:
    case VE::PVADDSLOivm_v:
    case VE::PVADDSLOivml:
    case VE::PVADDSLOivml_v:
    case VE::PVADDSLOrvm:
    case VE::PVADDSLOrvmL:
    case VE::PVADDSLOrvmL_v:
    case VE::PVADDSLOrvm_v:
    case VE::PVADDSLOrvml:
    case VE::PVADDSLOrvml_v:
    case VE::PVADDSUPivm:
    case VE::PVADDSUPivmL:
    case VE::PVADDSUPivmL_v:
    case VE::PVADDSUPivm_v:
    case VE::PVADDSUPivml:
    case VE::PVADDSUPivml_v:
    case VE::PVADDSUPrvm:
    case VE::PVADDSUPrvmL:
    case VE::PVADDSUPrvmL_v:
    case VE::PVADDSUPrvm_v:
    case VE::PVADDSUPrvml:
    case VE::PVADDSUPrvml_v:
    case VE::PVADDSivm:
    case VE::PVADDSivmL:
    case VE::PVADDSivmL_v:
    case VE::PVADDSivm_v:
    case VE::PVADDSivml:
    case VE::PVADDSivml_v:
    case VE::PVADDSrvm:
    case VE::PVADDSrvmL:
    case VE::PVADDSrvmL_v:
    case VE::PVADDSrvm_v:
    case VE::PVADDSrvml:
    case VE::PVADDSrvml_v:
    case VE::PVADDULOivm:
    case VE::PVADDULOivmL:
    case VE::PVADDULOivmL_v:
    case VE::PVADDULOivm_v:
    case VE::PVADDULOivml:
    case VE::PVADDULOivml_v:
    case VE::PVADDULOrvm:
    case VE::PVADDULOrvmL:
    case VE::PVADDULOrvmL_v:
    case VE::PVADDULOrvm_v:
    case VE::PVADDULOrvml:
    case VE::PVADDULOrvml_v:
    case VE::PVADDUUPivm:
    case VE::PVADDUUPivmL:
    case VE::PVADDUUPivmL_v:
    case VE::PVADDUUPivm_v:
    case VE::PVADDUUPivml:
    case VE::PVADDUUPivml_v:
    case VE::PVADDUUPrvm:
    case VE::PVADDUUPrvmL:
    case VE::PVADDUUPrvmL_v:
    case VE::PVADDUUPrvm_v:
    case VE::PVADDUUPrvml:
    case VE::PVADDUUPrvml_v:
    case VE::PVADDUivm:
    case VE::PVADDUivmL:
    case VE::PVADDUivmL_v:
    case VE::PVADDUivm_v:
    case VE::PVADDUivml:
    case VE::PVADDUivml_v:
    case VE::PVADDUrvm:
    case VE::PVADDUrvmL:
    case VE::PVADDUrvmL_v:
    case VE::PVADDUrvm_v:
    case VE::PVADDUrvml:
    case VE::PVADDUrvml_v:
    case VE::PVANDLOmvm:
    case VE::PVANDLOmvmL:
    case VE::PVANDLOmvmL_v:
    case VE::PVANDLOmvm_v:
    case VE::PVANDLOmvml:
    case VE::PVANDLOmvml_v:
    case VE::PVANDLOrvm:
    case VE::PVANDLOrvmL:
    case VE::PVANDLOrvmL_v:
    case VE::PVANDLOrvm_v:
    case VE::PVANDLOrvml:
    case VE::PVANDLOrvml_v:
    case VE::PVANDUPmvm:
    case VE::PVANDUPmvmL:
    case VE::PVANDUPmvmL_v:
    case VE::PVANDUPmvm_v:
    case VE::PVANDUPmvml:
    case VE::PVANDUPmvml_v:
    case VE::PVANDUPrvm:
    case VE::PVANDUPrvmL:
    case VE::PVANDUPrvmL_v:
    case VE::PVANDUPrvm_v:
    case VE::PVANDUPrvml:
    case VE::PVANDUPrvml_v:
    case VE::PVANDmvm:
    case VE::PVANDmvmL:
    case VE::PVANDmvmL_v:
    case VE::PVANDmvm_v:
    case VE::PVANDmvml:
    case VE::PVANDmvml_v:
    case VE::PVANDrvm:
    case VE::PVANDrvmL:
    case VE::PVANDrvmL_v:
    case VE::PVANDrvm_v:
    case VE::PVANDrvml:
    case VE::PVANDrvml_v:
    case VE::PVCMPSLOivm:
    case VE::PVCMPSLOivmL:
    case VE::PVCMPSLOivmL_v:
    case VE::PVCMPSLOivm_v:
    case VE::PVCMPSLOivml:
    case VE::PVCMPSLOivml_v:
    case VE::PVCMPSLOrvm:
    case VE::PVCMPSLOrvmL:
    case VE::PVCMPSLOrvmL_v:
    case VE::PVCMPSLOrvm_v:
    case VE::PVCMPSLOrvml:
    case VE::PVCMPSLOrvml_v:
    case VE::PVCMPSUPivm:
    case VE::PVCMPSUPivmL:
    case VE::PVCMPSUPivmL_v:
    case VE::PVCMPSUPivm_v:
    case VE::PVCMPSUPivml:
    case VE::PVCMPSUPivml_v:
    case VE::PVCMPSUPrvm:
    case VE::PVCMPSUPrvmL:
    case VE::PVCMPSUPrvmL_v:
    case VE::PVCMPSUPrvm_v:
    case VE::PVCMPSUPrvml:
    case VE::PVCMPSUPrvml_v:
    case VE::PVCMPSivm:
    case VE::PVCMPSivmL:
    case VE::PVCMPSivmL_v:
    case VE::PVCMPSivm_v:
    case VE::PVCMPSivml:
    case VE::PVCMPSivml_v:
    case VE::PVCMPSrvm:
    case VE::PVCMPSrvmL:
    case VE::PVCMPSrvmL_v:
    case VE::PVCMPSrvm_v:
    case VE::PVCMPSrvml:
    case VE::PVCMPSrvml_v:
    case VE::PVCMPULOivm:
    case VE::PVCMPULOivmL:
    case VE::PVCMPULOivmL_v:
    case VE::PVCMPULOivm_v:
    case VE::PVCMPULOivml:
    case VE::PVCMPULOivml_v:
    case VE::PVCMPULOrvm:
    case VE::PVCMPULOrvmL:
    case VE::PVCMPULOrvmL_v:
    case VE::PVCMPULOrvm_v:
    case VE::PVCMPULOrvml:
    case VE::PVCMPULOrvml_v:
    case VE::PVCMPUUPivm:
    case VE::PVCMPUUPivmL:
    case VE::PVCMPUUPivmL_v:
    case VE::PVCMPUUPivm_v:
    case VE::PVCMPUUPivml:
    case VE::PVCMPUUPivml_v:
    case VE::PVCMPUUPrvm:
    case VE::PVCMPUUPrvmL:
    case VE::PVCMPUUPrvmL_v:
    case VE::PVCMPUUPrvm_v:
    case VE::PVCMPUUPrvml:
    case VE::PVCMPUUPrvml_v:
    case VE::PVCMPUivm:
    case VE::PVCMPUivmL:
    case VE::PVCMPUivmL_v:
    case VE::PVCMPUivm_v:
    case VE::PVCMPUivml:
    case VE::PVCMPUivml_v:
    case VE::PVCMPUrvm:
    case VE::PVCMPUrvmL:
    case VE::PVCMPUrvmL_v:
    case VE::PVCMPUrvm_v:
    case VE::PVCMPUrvml:
    case VE::PVCMPUrvml_v:
    case VE::PVEQVLOmvm:
    case VE::PVEQVLOmvmL:
    case VE::PVEQVLOmvmL_v:
    case VE::PVEQVLOmvm_v:
    case VE::PVEQVLOmvml:
    case VE::PVEQVLOmvml_v:
    case VE::PVEQVLOrvm:
    case VE::PVEQVLOrvmL:
    case VE::PVEQVLOrvmL_v:
    case VE::PVEQVLOrvm_v:
    case VE::PVEQVLOrvml:
    case VE::PVEQVLOrvml_v:
    case VE::PVEQVUPmvm:
    case VE::PVEQVUPmvmL:
    case VE::PVEQVUPmvmL_v:
    case VE::PVEQVUPmvm_v:
    case VE::PVEQVUPmvml:
    case VE::PVEQVUPmvml_v:
    case VE::PVEQVUPrvm:
    case VE::PVEQVUPrvmL:
    case VE::PVEQVUPrvmL_v:
    case VE::PVEQVUPrvm_v:
    case VE::PVEQVUPrvml:
    case VE::PVEQVUPrvml_v:
    case VE::PVEQVmvm:
    case VE::PVEQVmvmL:
    case VE::PVEQVmvmL_v:
    case VE::PVEQVmvm_v:
    case VE::PVEQVmvml:
    case VE::PVEQVmvml_v:
    case VE::PVEQVrvm:
    case VE::PVEQVrvmL:
    case VE::PVEQVrvmL_v:
    case VE::PVEQVrvm_v:
    case VE::PVEQVrvml:
    case VE::PVEQVrvml_v:
    case VE::PVFADDLOivm:
    case VE::PVFADDLOivmL:
    case VE::PVFADDLOivmL_v:
    case VE::PVFADDLOivm_v:
    case VE::PVFADDLOivml:
    case VE::PVFADDLOivml_v:
    case VE::PVFADDLOrvm:
    case VE::PVFADDLOrvmL:
    case VE::PVFADDLOrvmL_v:
    case VE::PVFADDLOrvm_v:
    case VE::PVFADDLOrvml:
    case VE::PVFADDLOrvml_v:
    case VE::PVFADDUPivm:
    case VE::PVFADDUPivmL:
    case VE::PVFADDUPivmL_v:
    case VE::PVFADDUPivm_v:
    case VE::PVFADDUPivml:
    case VE::PVFADDUPivml_v:
    case VE::PVFADDUPrvm:
    case VE::PVFADDUPrvmL:
    case VE::PVFADDUPrvmL_v:
    case VE::PVFADDUPrvm_v:
    case VE::PVFADDUPrvml:
    case VE::PVFADDUPrvml_v:
    case VE::PVFADDivm:
    case VE::PVFADDivmL:
    case VE::PVFADDivmL_v:
    case VE::PVFADDivm_v:
    case VE::PVFADDivml:
    case VE::PVFADDivml_v:
    case VE::PVFADDrvm:
    case VE::PVFADDrvmL:
    case VE::PVFADDrvmL_v:
    case VE::PVFADDrvm_v:
    case VE::PVFADDrvml:
    case VE::PVFADDrvml_v:
    case VE::PVFCMPLOivm:
    case VE::PVFCMPLOivmL:
    case VE::PVFCMPLOivmL_v:
    case VE::PVFCMPLOivm_v:
    case VE::PVFCMPLOivml:
    case VE::PVFCMPLOivml_v:
    case VE::PVFCMPLOrvm:
    case VE::PVFCMPLOrvmL:
    case VE::PVFCMPLOrvmL_v:
    case VE::PVFCMPLOrvm_v:
    case VE::PVFCMPLOrvml:
    case VE::PVFCMPLOrvml_v:
    case VE::PVFCMPUPivm:
    case VE::PVFCMPUPivmL:
    case VE::PVFCMPUPivmL_v:
    case VE::PVFCMPUPivm_v:
    case VE::PVFCMPUPivml:
    case VE::PVFCMPUPivml_v:
    case VE::PVFCMPUPrvm:
    case VE::PVFCMPUPrvmL:
    case VE::PVFCMPUPrvmL_v:
    case VE::PVFCMPUPrvm_v:
    case VE::PVFCMPUPrvml:
    case VE::PVFCMPUPrvml_v:
    case VE::PVFCMPivm:
    case VE::PVFCMPivmL:
    case VE::PVFCMPivmL_v:
    case VE::PVFCMPivm_v:
    case VE::PVFCMPivml:
    case VE::PVFCMPivml_v:
    case VE::PVFCMPrvm:
    case VE::PVFCMPrvmL:
    case VE::PVFCMPrvmL_v:
    case VE::PVFCMPrvm_v:
    case VE::PVFCMPrvml:
    case VE::PVFCMPrvml_v:
    case VE::PVFMAXLOivm:
    case VE::PVFMAXLOivmL:
    case VE::PVFMAXLOivmL_v:
    case VE::PVFMAXLOivm_v:
    case VE::PVFMAXLOivml:
    case VE::PVFMAXLOivml_v:
    case VE::PVFMAXLOrvm:
    case VE::PVFMAXLOrvmL:
    case VE::PVFMAXLOrvmL_v:
    case VE::PVFMAXLOrvm_v:
    case VE::PVFMAXLOrvml:
    case VE::PVFMAXLOrvml_v:
    case VE::PVFMAXUPivm:
    case VE::PVFMAXUPivmL:
    case VE::PVFMAXUPivmL_v:
    case VE::PVFMAXUPivm_v:
    case VE::PVFMAXUPivml:
    case VE::PVFMAXUPivml_v:
    case VE::PVFMAXUPrvm:
    case VE::PVFMAXUPrvmL:
    case VE::PVFMAXUPrvmL_v:
    case VE::PVFMAXUPrvm_v:
    case VE::PVFMAXUPrvml:
    case VE::PVFMAXUPrvml_v:
    case VE::PVFMAXivm:
    case VE::PVFMAXivmL:
    case VE::PVFMAXivmL_v:
    case VE::PVFMAXivm_v:
    case VE::PVFMAXivml:
    case VE::PVFMAXivml_v:
    case VE::PVFMAXrvm:
    case VE::PVFMAXrvmL:
    case VE::PVFMAXrvmL_v:
    case VE::PVFMAXrvm_v:
    case VE::PVFMAXrvml:
    case VE::PVFMAXrvml_v:
    case VE::PVFMINLOivm:
    case VE::PVFMINLOivmL:
    case VE::PVFMINLOivmL_v:
    case VE::PVFMINLOivm_v:
    case VE::PVFMINLOivml:
    case VE::PVFMINLOivml_v:
    case VE::PVFMINLOrvm:
    case VE::PVFMINLOrvmL:
    case VE::PVFMINLOrvmL_v:
    case VE::PVFMINLOrvm_v:
    case VE::PVFMINLOrvml:
    case VE::PVFMINLOrvml_v:
    case VE::PVFMINUPivm:
    case VE::PVFMINUPivmL:
    case VE::PVFMINUPivmL_v:
    case VE::PVFMINUPivm_v:
    case VE::PVFMINUPivml:
    case VE::PVFMINUPivml_v:
    case VE::PVFMINUPrvm:
    case VE::PVFMINUPrvmL:
    case VE::PVFMINUPrvmL_v:
    case VE::PVFMINUPrvm_v:
    case VE::PVFMINUPrvml:
    case VE::PVFMINUPrvml_v:
    case VE::PVFMINivm:
    case VE::PVFMINivmL:
    case VE::PVFMINivmL_v:
    case VE::PVFMINivm_v:
    case VE::PVFMINivml:
    case VE::PVFMINivml_v:
    case VE::PVFMINrvm:
    case VE::PVFMINrvmL:
    case VE::PVFMINrvmL_v:
    case VE::PVFMINrvm_v:
    case VE::PVFMINrvml:
    case VE::PVFMINrvml_v:
    case VE::PVFMULLOivm:
    case VE::PVFMULLOivmL:
    case VE::PVFMULLOivmL_v:
    case VE::PVFMULLOivm_v:
    case VE::PVFMULLOivml:
    case VE::PVFMULLOivml_v:
    case VE::PVFMULLOrvm:
    case VE::PVFMULLOrvmL:
    case VE::PVFMULLOrvmL_v:
    case VE::PVFMULLOrvm_v:
    case VE::PVFMULLOrvml:
    case VE::PVFMULLOrvml_v:
    case VE::PVFMULUPivm:
    case VE::PVFMULUPivmL:
    case VE::PVFMULUPivmL_v:
    case VE::PVFMULUPivm_v:
    case VE::PVFMULUPivml:
    case VE::PVFMULUPivml_v:
    case VE::PVFMULUPrvm:
    case VE::PVFMULUPrvmL:
    case VE::PVFMULUPrvmL_v:
    case VE::PVFMULUPrvm_v:
    case VE::PVFMULUPrvml:
    case VE::PVFMULUPrvml_v:
    case VE::PVFMULivm:
    case VE::PVFMULivmL:
    case VE::PVFMULivmL_v:
    case VE::PVFMULivm_v:
    case VE::PVFMULivml:
    case VE::PVFMULivml_v:
    case VE::PVFMULrvm:
    case VE::PVFMULrvmL:
    case VE::PVFMULrvmL_v:
    case VE::PVFMULrvm_v:
    case VE::PVFMULrvml:
    case VE::PVFMULrvml_v:
    case VE::PVFSUBLOivm:
    case VE::PVFSUBLOivmL:
    case VE::PVFSUBLOivmL_v:
    case VE::PVFSUBLOivm_v:
    case VE::PVFSUBLOivml:
    case VE::PVFSUBLOivml_v:
    case VE::PVFSUBLOrvm:
    case VE::PVFSUBLOrvmL:
    case VE::PVFSUBLOrvmL_v:
    case VE::PVFSUBLOrvm_v:
    case VE::PVFSUBLOrvml:
    case VE::PVFSUBLOrvml_v:
    case VE::PVFSUBUPivm:
    case VE::PVFSUBUPivmL:
    case VE::PVFSUBUPivmL_v:
    case VE::PVFSUBUPivm_v:
    case VE::PVFSUBUPivml:
    case VE::PVFSUBUPivml_v:
    case VE::PVFSUBUPrvm:
    case VE::PVFSUBUPrvmL:
    case VE::PVFSUBUPrvmL_v:
    case VE::PVFSUBUPrvm_v:
    case VE::PVFSUBUPrvml:
    case VE::PVFSUBUPrvml_v:
    case VE::PVFSUBivm:
    case VE::PVFSUBivmL:
    case VE::PVFSUBivmL_v:
    case VE::PVFSUBivm_v:
    case VE::PVFSUBivml:
    case VE::PVFSUBivml_v:
    case VE::PVFSUBrvm:
    case VE::PVFSUBrvmL:
    case VE::PVFSUBrvmL_v:
    case VE::PVFSUBrvm_v:
    case VE::PVFSUBrvml:
    case VE::PVFSUBrvml_v:
    case VE::PVMAXSLOivm:
    case VE::PVMAXSLOivmL:
    case VE::PVMAXSLOivmL_v:
    case VE::PVMAXSLOivm_v:
    case VE::PVMAXSLOivml:
    case VE::PVMAXSLOivml_v:
    case VE::PVMAXSLOrvm:
    case VE::PVMAXSLOrvmL:
    case VE::PVMAXSLOrvmL_v:
    case VE::PVMAXSLOrvm_v:
    case VE::PVMAXSLOrvml:
    case VE::PVMAXSLOrvml_v:
    case VE::PVMAXSUPivm:
    case VE::PVMAXSUPivmL:
    case VE::PVMAXSUPivmL_v:
    case VE::PVMAXSUPivm_v:
    case VE::PVMAXSUPivml:
    case VE::PVMAXSUPivml_v:
    case VE::PVMAXSUPrvm:
    case VE::PVMAXSUPrvmL:
    case VE::PVMAXSUPrvmL_v:
    case VE::PVMAXSUPrvm_v:
    case VE::PVMAXSUPrvml:
    case VE::PVMAXSUPrvml_v:
    case VE::PVMAXSivm:
    case VE::PVMAXSivmL:
    case VE::PVMAXSivmL_v:
    case VE::PVMAXSivm_v:
    case VE::PVMAXSivml:
    case VE::PVMAXSivml_v:
    case VE::PVMAXSrvm:
    case VE::PVMAXSrvmL:
    case VE::PVMAXSrvmL_v:
    case VE::PVMAXSrvm_v:
    case VE::PVMAXSrvml:
    case VE::PVMAXSrvml_v:
    case VE::PVMINSLOivm:
    case VE::PVMINSLOivmL:
    case VE::PVMINSLOivmL_v:
    case VE::PVMINSLOivm_v:
    case VE::PVMINSLOivml:
    case VE::PVMINSLOivml_v:
    case VE::PVMINSLOrvm:
    case VE::PVMINSLOrvmL:
    case VE::PVMINSLOrvmL_v:
    case VE::PVMINSLOrvm_v:
    case VE::PVMINSLOrvml:
    case VE::PVMINSLOrvml_v:
    case VE::PVMINSUPivm:
    case VE::PVMINSUPivmL:
    case VE::PVMINSUPivmL_v:
    case VE::PVMINSUPivm_v:
    case VE::PVMINSUPivml:
    case VE::PVMINSUPivml_v:
    case VE::PVMINSUPrvm:
    case VE::PVMINSUPrvmL:
    case VE::PVMINSUPrvmL_v:
    case VE::PVMINSUPrvm_v:
    case VE::PVMINSUPrvml:
    case VE::PVMINSUPrvml_v:
    case VE::PVMINSivm:
    case VE::PVMINSivmL:
    case VE::PVMINSivmL_v:
    case VE::PVMINSivm_v:
    case VE::PVMINSivml:
    case VE::PVMINSivml_v:
    case VE::PVMINSrvm:
    case VE::PVMINSrvmL:
    case VE::PVMINSrvmL_v:
    case VE::PVMINSrvm_v:
    case VE::PVMINSrvml:
    case VE::PVMINSrvml_v:
    case VE::PVORLOmvm:
    case VE::PVORLOmvmL:
    case VE::PVORLOmvmL_v:
    case VE::PVORLOmvm_v:
    case VE::PVORLOmvml:
    case VE::PVORLOmvml_v:
    case VE::PVORLOrvm:
    case VE::PVORLOrvmL:
    case VE::PVORLOrvmL_v:
    case VE::PVORLOrvm_v:
    case VE::PVORLOrvml:
    case VE::PVORLOrvml_v:
    case VE::PVORUPmvm:
    case VE::PVORUPmvmL:
    case VE::PVORUPmvmL_v:
    case VE::PVORUPmvm_v:
    case VE::PVORUPmvml:
    case VE::PVORUPmvml_v:
    case VE::PVORUPrvm:
    case VE::PVORUPrvmL:
    case VE::PVORUPrvmL_v:
    case VE::PVORUPrvm_v:
    case VE::PVORUPrvml:
    case VE::PVORUPrvml_v:
    case VE::PVORmvm:
    case VE::PVORmvmL:
    case VE::PVORmvmL_v:
    case VE::PVORmvm_v:
    case VE::PVORmvml:
    case VE::PVORmvml_v:
    case VE::PVORrvm:
    case VE::PVORrvmL:
    case VE::PVORrvmL_v:
    case VE::PVORrvm_v:
    case VE::PVORrvml:
    case VE::PVORrvml_v:
    case VE::PVSUBSLOivm:
    case VE::PVSUBSLOivmL:
    case VE::PVSUBSLOivmL_v:
    case VE::PVSUBSLOivm_v:
    case VE::PVSUBSLOivml:
    case VE::PVSUBSLOivml_v:
    case VE::PVSUBSLOrvm:
    case VE::PVSUBSLOrvmL:
    case VE::PVSUBSLOrvmL_v:
    case VE::PVSUBSLOrvm_v:
    case VE::PVSUBSLOrvml:
    case VE::PVSUBSLOrvml_v:
    case VE::PVSUBSUPivm:
    case VE::PVSUBSUPivmL:
    case VE::PVSUBSUPivmL_v:
    case VE::PVSUBSUPivm_v:
    case VE::PVSUBSUPivml:
    case VE::PVSUBSUPivml_v:
    case VE::PVSUBSUPrvm:
    case VE::PVSUBSUPrvmL:
    case VE::PVSUBSUPrvmL_v:
    case VE::PVSUBSUPrvm_v:
    case VE::PVSUBSUPrvml:
    case VE::PVSUBSUPrvml_v:
    case VE::PVSUBSivm:
    case VE::PVSUBSivmL:
    case VE::PVSUBSivmL_v:
    case VE::PVSUBSivm_v:
    case VE::PVSUBSivml:
    case VE::PVSUBSivml_v:
    case VE::PVSUBSrvm:
    case VE::PVSUBSrvmL:
    case VE::PVSUBSrvmL_v:
    case VE::PVSUBSrvm_v:
    case VE::PVSUBSrvml:
    case VE::PVSUBSrvml_v:
    case VE::PVSUBULOivm:
    case VE::PVSUBULOivmL:
    case VE::PVSUBULOivmL_v:
    case VE::PVSUBULOivm_v:
    case VE::PVSUBULOivml:
    case VE::PVSUBULOivml_v:
    case VE::PVSUBULOrvm:
    case VE::PVSUBULOrvmL:
    case VE::PVSUBULOrvmL_v:
    case VE::PVSUBULOrvm_v:
    case VE::PVSUBULOrvml:
    case VE::PVSUBULOrvml_v:
    case VE::PVSUBUUPivm:
    case VE::PVSUBUUPivmL:
    case VE::PVSUBUUPivmL_v:
    case VE::PVSUBUUPivm_v:
    case VE::PVSUBUUPivml:
    case VE::PVSUBUUPivml_v:
    case VE::PVSUBUUPrvm:
    case VE::PVSUBUUPrvmL:
    case VE::PVSUBUUPrvmL_v:
    case VE::PVSUBUUPrvm_v:
    case VE::PVSUBUUPrvml:
    case VE::PVSUBUUPrvml_v:
    case VE::PVSUBUivm:
    case VE::PVSUBUivmL:
    case VE::PVSUBUivmL_v:
    case VE::PVSUBUivm_v:
    case VE::PVSUBUivml:
    case VE::PVSUBUivml_v:
    case VE::PVSUBUrvm:
    case VE::PVSUBUrvmL:
    case VE::PVSUBUrvmL_v:
    case VE::PVSUBUrvm_v:
    case VE::PVSUBUrvml:
    case VE::PVSUBUrvml_v:
    case VE::PVXORLOmvm:
    case VE::PVXORLOmvmL:
    case VE::PVXORLOmvmL_v:
    case VE::PVXORLOmvm_v:
    case VE::PVXORLOmvml:
    case VE::PVXORLOmvml_v:
    case VE::PVXORLOrvm:
    case VE::PVXORLOrvmL:
    case VE::PVXORLOrvmL_v:
    case VE::PVXORLOrvm_v:
    case VE::PVXORLOrvml:
    case VE::PVXORLOrvml_v:
    case VE::PVXORUPmvm:
    case VE::PVXORUPmvmL:
    case VE::PVXORUPmvmL_v:
    case VE::PVXORUPmvm_v:
    case VE::PVXORUPmvml:
    case VE::PVXORUPmvml_v:
    case VE::PVXORUPrvm:
    case VE::PVXORUPrvmL:
    case VE::PVXORUPrvmL_v:
    case VE::PVXORUPrvm_v:
    case VE::PVXORUPrvml:
    case VE::PVXORUPrvml_v:
    case VE::PVXORmvm:
    case VE::PVXORmvmL:
    case VE::PVXORmvmL_v:
    case VE::PVXORmvm_v:
    case VE::PVXORmvml:
    case VE::PVXORmvml_v:
    case VE::PVXORrvm:
    case VE::PVXORrvmL:
    case VE::PVXORrvmL_v:
    case VE::PVXORrvm_v:
    case VE::PVXORrvml:
    case VE::PVXORrvml_v:
    case VE::VADDSLivm:
    case VE::VADDSLivmL:
    case VE::VADDSLivmL_v:
    case VE::VADDSLivm_v:
    case VE::VADDSLivml:
    case VE::VADDSLivml_v:
    case VE::VADDSLrvm:
    case VE::VADDSLrvmL:
    case VE::VADDSLrvmL_v:
    case VE::VADDSLrvm_v:
    case VE::VADDSLrvml:
    case VE::VADDSLrvml_v:
    case VE::VADDSWSXivm:
    case VE::VADDSWSXivmL:
    case VE::VADDSWSXivmL_v:
    case VE::VADDSWSXivm_v:
    case VE::VADDSWSXivml:
    case VE::VADDSWSXivml_v:
    case VE::VADDSWSXrvm:
    case VE::VADDSWSXrvmL:
    case VE::VADDSWSXrvmL_v:
    case VE::VADDSWSXrvm_v:
    case VE::VADDSWSXrvml:
    case VE::VADDSWSXrvml_v:
    case VE::VADDSWZXivm:
    case VE::VADDSWZXivmL:
    case VE::VADDSWZXivmL_v:
    case VE::VADDSWZXivm_v:
    case VE::VADDSWZXivml:
    case VE::VADDSWZXivml_v:
    case VE::VADDSWZXrvm:
    case VE::VADDSWZXrvmL:
    case VE::VADDSWZXrvmL_v:
    case VE::VADDSWZXrvm_v:
    case VE::VADDSWZXrvml:
    case VE::VADDSWZXrvml_v:
    case VE::VADDULivm:
    case VE::VADDULivmL:
    case VE::VADDULivmL_v:
    case VE::VADDULivm_v:
    case VE::VADDULivml:
    case VE::VADDULivml_v:
    case VE::VADDULrvm:
    case VE::VADDULrvmL:
    case VE::VADDULrvmL_v:
    case VE::VADDULrvm_v:
    case VE::VADDULrvml:
    case VE::VADDULrvml_v:
    case VE::VADDUWivm:
    case VE::VADDUWivmL:
    case VE::VADDUWivmL_v:
    case VE::VADDUWivm_v:
    case VE::VADDUWivml:
    case VE::VADDUWivml_v:
    case VE::VADDUWrvm:
    case VE::VADDUWrvmL:
    case VE::VADDUWrvmL_v:
    case VE::VADDUWrvm_v:
    case VE::VADDUWrvml:
    case VE::VADDUWrvml_v:
    case VE::VANDmvm:
    case VE::VANDmvmL:
    case VE::VANDmvmL_v:
    case VE::VANDmvm_v:
    case VE::VANDmvml:
    case VE::VANDmvml_v:
    case VE::VANDrvm:
    case VE::VANDrvmL:
    case VE::VANDrvmL_v:
    case VE::VANDrvm_v:
    case VE::VANDrvml:
    case VE::VANDrvml_v:
    case VE::VCMPSLivm:
    case VE::VCMPSLivmL:
    case VE::VCMPSLivmL_v:
    case VE::VCMPSLivm_v:
    case VE::VCMPSLivml:
    case VE::VCMPSLivml_v:
    case VE::VCMPSLrvm:
    case VE::VCMPSLrvmL:
    case VE::VCMPSLrvmL_v:
    case VE::VCMPSLrvm_v:
    case VE::VCMPSLrvml:
    case VE::VCMPSLrvml_v:
    case VE::VCMPSWSXivm:
    case VE::VCMPSWSXivmL:
    case VE::VCMPSWSXivmL_v:
    case VE::VCMPSWSXivm_v:
    case VE::VCMPSWSXivml:
    case VE::VCMPSWSXivml_v:
    case VE::VCMPSWSXrvm:
    case VE::VCMPSWSXrvmL:
    case VE::VCMPSWSXrvmL_v:
    case VE::VCMPSWSXrvm_v:
    case VE::VCMPSWSXrvml:
    case VE::VCMPSWSXrvml_v:
    case VE::VCMPSWZXivm:
    case VE::VCMPSWZXivmL:
    case VE::VCMPSWZXivmL_v:
    case VE::VCMPSWZXivm_v:
    case VE::VCMPSWZXivml:
    case VE::VCMPSWZXivml_v:
    case VE::VCMPSWZXrvm:
    case VE::VCMPSWZXrvmL:
    case VE::VCMPSWZXrvmL_v:
    case VE::VCMPSWZXrvm_v:
    case VE::VCMPSWZXrvml:
    case VE::VCMPSWZXrvml_v:
    case VE::VCMPULivm:
    case VE::VCMPULivmL:
    case VE::VCMPULivmL_v:
    case VE::VCMPULivm_v:
    case VE::VCMPULivml:
    case VE::VCMPULivml_v:
    case VE::VCMPULrvm:
    case VE::VCMPULrvmL:
    case VE::VCMPULrvmL_v:
    case VE::VCMPULrvm_v:
    case VE::VCMPULrvml:
    case VE::VCMPULrvml_v:
    case VE::VCMPUWivm:
    case VE::VCMPUWivmL:
    case VE::VCMPUWivmL_v:
    case VE::VCMPUWivm_v:
    case VE::VCMPUWivml:
    case VE::VCMPUWivml_v:
    case VE::VCMPUWrvm:
    case VE::VCMPUWrvmL:
    case VE::VCMPUWrvmL_v:
    case VE::VCMPUWrvm_v:
    case VE::VCMPUWrvml:
    case VE::VCMPUWrvml_v:
    case VE::VDIVSLivm:
    case VE::VDIVSLivmL:
    case VE::VDIVSLivmL_v:
    case VE::VDIVSLivm_v:
    case VE::VDIVSLivml:
    case VE::VDIVSLivml_v:
    case VE::VDIVSLrvm:
    case VE::VDIVSLrvmL:
    case VE::VDIVSLrvmL_v:
    case VE::VDIVSLrvm_v:
    case VE::VDIVSLrvml:
    case VE::VDIVSLrvml_v:
    case VE::VDIVSWSXivm:
    case VE::VDIVSWSXivmL:
    case VE::VDIVSWSXivmL_v:
    case VE::VDIVSWSXivm_v:
    case VE::VDIVSWSXivml:
    case VE::VDIVSWSXivml_v:
    case VE::VDIVSWSXrvm:
    case VE::VDIVSWSXrvmL:
    case VE::VDIVSWSXrvmL_v:
    case VE::VDIVSWSXrvm_v:
    case VE::VDIVSWSXrvml:
    case VE::VDIVSWSXrvml_v:
    case VE::VDIVSWZXivm:
    case VE::VDIVSWZXivmL:
    case VE::VDIVSWZXivmL_v:
    case VE::VDIVSWZXivm_v:
    case VE::VDIVSWZXivml:
    case VE::VDIVSWZXivml_v:
    case VE::VDIVSWZXrvm:
    case VE::VDIVSWZXrvmL:
    case VE::VDIVSWZXrvmL_v:
    case VE::VDIVSWZXrvm_v:
    case VE::VDIVSWZXrvml:
    case VE::VDIVSWZXrvml_v:
    case VE::VDIVULivm:
    case VE::VDIVULivmL:
    case VE::VDIVULivmL_v:
    case VE::VDIVULivm_v:
    case VE::VDIVULivml:
    case VE::VDIVULivml_v:
    case VE::VDIVULrvm:
    case VE::VDIVULrvmL:
    case VE::VDIVULrvmL_v:
    case VE::VDIVULrvm_v:
    case VE::VDIVULrvml:
    case VE::VDIVULrvml_v:
    case VE::VDIVUWivm:
    case VE::VDIVUWivmL:
    case VE::VDIVUWivmL_v:
    case VE::VDIVUWivm_v:
    case VE::VDIVUWivml:
    case VE::VDIVUWivml_v:
    case VE::VDIVUWrvm:
    case VE::VDIVUWrvmL:
    case VE::VDIVUWrvmL_v:
    case VE::VDIVUWrvm_v:
    case VE::VDIVUWrvml:
    case VE::VDIVUWrvml_v:
    case VE::VEQVmvm:
    case VE::VEQVmvmL:
    case VE::VEQVmvmL_v:
    case VE::VEQVmvm_v:
    case VE::VEQVmvml:
    case VE::VEQVmvml_v:
    case VE::VEQVrvm:
    case VE::VEQVrvmL:
    case VE::VEQVrvmL_v:
    case VE::VEQVrvm_v:
    case VE::VEQVrvml:
    case VE::VEQVrvml_v:
    case VE::VFADDDivm:
    case VE::VFADDDivmL:
    case VE::VFADDDivmL_v:
    case VE::VFADDDivm_v:
    case VE::VFADDDivml:
    case VE::VFADDDivml_v:
    case VE::VFADDDrvm:
    case VE::VFADDDrvmL:
    case VE::VFADDDrvmL_v:
    case VE::VFADDDrvm_v:
    case VE::VFADDDrvml:
    case VE::VFADDDrvml_v:
    case VE::VFADDSivm:
    case VE::VFADDSivmL:
    case VE::VFADDSivmL_v:
    case VE::VFADDSivm_v:
    case VE::VFADDSivml:
    case VE::VFADDSivml_v:
    case VE::VFADDSrvm:
    case VE::VFADDSrvmL:
    case VE::VFADDSrvmL_v:
    case VE::VFADDSrvm_v:
    case VE::VFADDSrvml:
    case VE::VFADDSrvml_v:
    case VE::VFCMPDivm:
    case VE::VFCMPDivmL:
    case VE::VFCMPDivmL_v:
    case VE::VFCMPDivm_v:
    case VE::VFCMPDivml:
    case VE::VFCMPDivml_v:
    case VE::VFCMPDrvm:
    case VE::VFCMPDrvmL:
    case VE::VFCMPDrvmL_v:
    case VE::VFCMPDrvm_v:
    case VE::VFCMPDrvml:
    case VE::VFCMPDrvml_v:
    case VE::VFCMPSivm:
    case VE::VFCMPSivmL:
    case VE::VFCMPSivmL_v:
    case VE::VFCMPSivm_v:
    case VE::VFCMPSivml:
    case VE::VFCMPSivml_v:
    case VE::VFCMPSrvm:
    case VE::VFCMPSrvmL:
    case VE::VFCMPSrvmL_v:
    case VE::VFCMPSrvm_v:
    case VE::VFCMPSrvml:
    case VE::VFCMPSrvml_v:
    case VE::VFDIVDivm:
    case VE::VFDIVDivmL:
    case VE::VFDIVDivmL_v:
    case VE::VFDIVDivm_v:
    case VE::VFDIVDivml:
    case VE::VFDIVDivml_v:
    case VE::VFDIVDrvm:
    case VE::VFDIVDrvmL:
    case VE::VFDIVDrvmL_v:
    case VE::VFDIVDrvm_v:
    case VE::VFDIVDrvml:
    case VE::VFDIVDrvml_v:
    case VE::VFDIVSivm:
    case VE::VFDIVSivmL:
    case VE::VFDIVSivmL_v:
    case VE::VFDIVSivm_v:
    case VE::VFDIVSivml:
    case VE::VFDIVSivml_v:
    case VE::VFDIVSrvm:
    case VE::VFDIVSrvmL:
    case VE::VFDIVSrvmL_v:
    case VE::VFDIVSrvm_v:
    case VE::VFDIVSrvml:
    case VE::VFDIVSrvml_v:
    case VE::VFMAXDivm:
    case VE::VFMAXDivmL:
    case VE::VFMAXDivmL_v:
    case VE::VFMAXDivm_v:
    case VE::VFMAXDivml:
    case VE::VFMAXDivml_v:
    case VE::VFMAXDrvm:
    case VE::VFMAXDrvmL:
    case VE::VFMAXDrvmL_v:
    case VE::VFMAXDrvm_v:
    case VE::VFMAXDrvml:
    case VE::VFMAXDrvml_v:
    case VE::VFMAXSivm:
    case VE::VFMAXSivmL:
    case VE::VFMAXSivmL_v:
    case VE::VFMAXSivm_v:
    case VE::VFMAXSivml:
    case VE::VFMAXSivml_v:
    case VE::VFMAXSrvm:
    case VE::VFMAXSrvmL:
    case VE::VFMAXSrvmL_v:
    case VE::VFMAXSrvm_v:
    case VE::VFMAXSrvml:
    case VE::VFMAXSrvml_v:
    case VE::VFMINDivm:
    case VE::VFMINDivmL:
    case VE::VFMINDivmL_v:
    case VE::VFMINDivm_v:
    case VE::VFMINDivml:
    case VE::VFMINDivml_v:
    case VE::VFMINDrvm:
    case VE::VFMINDrvmL:
    case VE::VFMINDrvmL_v:
    case VE::VFMINDrvm_v:
    case VE::VFMINDrvml:
    case VE::VFMINDrvml_v:
    case VE::VFMINSivm:
    case VE::VFMINSivmL:
    case VE::VFMINSivmL_v:
    case VE::VFMINSivm_v:
    case VE::VFMINSivml:
    case VE::VFMINSivml_v:
    case VE::VFMINSrvm:
    case VE::VFMINSrvmL:
    case VE::VFMINSrvmL_v:
    case VE::VFMINSrvm_v:
    case VE::VFMINSrvml:
    case VE::VFMINSrvml_v:
    case VE::VFMULDivm:
    case VE::VFMULDivmL:
    case VE::VFMULDivmL_v:
    case VE::VFMULDivm_v:
    case VE::VFMULDivml:
    case VE::VFMULDivml_v:
    case VE::VFMULDrvm:
    case VE::VFMULDrvmL:
    case VE::VFMULDrvmL_v:
    case VE::VFMULDrvm_v:
    case VE::VFMULDrvml:
    case VE::VFMULDrvml_v:
    case VE::VFMULSivm:
    case VE::VFMULSivmL:
    case VE::VFMULSivmL_v:
    case VE::VFMULSivm_v:
    case VE::VFMULSivml:
    case VE::VFMULSivml_v:
    case VE::VFMULSrvm:
    case VE::VFMULSrvmL:
    case VE::VFMULSrvmL_v:
    case VE::VFMULSrvm_v:
    case VE::VFMULSrvml:
    case VE::VFMULSrvml_v:
    case VE::VFSUBDivm:
    case VE::VFSUBDivmL:
    case VE::VFSUBDivmL_v:
    case VE::VFSUBDivm_v:
    case VE::VFSUBDivml:
    case VE::VFSUBDivml_v:
    case VE::VFSUBDrvm:
    case VE::VFSUBDrvmL:
    case VE::VFSUBDrvmL_v:
    case VE::VFSUBDrvm_v:
    case VE::VFSUBDrvml:
    case VE::VFSUBDrvml_v:
    case VE::VFSUBSivm:
    case VE::VFSUBSivmL:
    case VE::VFSUBSivmL_v:
    case VE::VFSUBSivm_v:
    case VE::VFSUBSivml:
    case VE::VFSUBSivml_v:
    case VE::VFSUBSrvm:
    case VE::VFSUBSrvmL:
    case VE::VFSUBSrvmL_v:
    case VE::VFSUBSrvm_v:
    case VE::VFSUBSrvml:
    case VE::VFSUBSrvml_v:
    case VE::VMAXSLivm:
    case VE::VMAXSLivmL:
    case VE::VMAXSLivmL_v:
    case VE::VMAXSLivm_v:
    case VE::VMAXSLivml:
    case VE::VMAXSLivml_v:
    case VE::VMAXSLrvm:
    case VE::VMAXSLrvmL:
    case VE::VMAXSLrvmL_v:
    case VE::VMAXSLrvm_v:
    case VE::VMAXSLrvml:
    case VE::VMAXSLrvml_v:
    case VE::VMAXSWSXivm:
    case VE::VMAXSWSXivmL:
    case VE::VMAXSWSXivmL_v:
    case VE::VMAXSWSXivm_v:
    case VE::VMAXSWSXivml:
    case VE::VMAXSWSXivml_v:
    case VE::VMAXSWSXrvm:
    case VE::VMAXSWSXrvmL:
    case VE::VMAXSWSXrvmL_v:
    case VE::VMAXSWSXrvm_v:
    case VE::VMAXSWSXrvml:
    case VE::VMAXSWSXrvml_v:
    case VE::VMAXSWZXivm:
    case VE::VMAXSWZXivmL:
    case VE::VMAXSWZXivmL_v:
    case VE::VMAXSWZXivm_v:
    case VE::VMAXSWZXivml:
    case VE::VMAXSWZXivml_v:
    case VE::VMAXSWZXrvm:
    case VE::VMAXSWZXrvmL:
    case VE::VMAXSWZXrvmL_v:
    case VE::VMAXSWZXrvm_v:
    case VE::VMAXSWZXrvml:
    case VE::VMAXSWZXrvml_v:
    case VE::VMINSLivm:
    case VE::VMINSLivmL:
    case VE::VMINSLivmL_v:
    case VE::VMINSLivm_v:
    case VE::VMINSLivml:
    case VE::VMINSLivml_v:
    case VE::VMINSLrvm:
    case VE::VMINSLrvmL:
    case VE::VMINSLrvmL_v:
    case VE::VMINSLrvm_v:
    case VE::VMINSLrvml:
    case VE::VMINSLrvml_v:
    case VE::VMINSWSXivm:
    case VE::VMINSWSXivmL:
    case VE::VMINSWSXivmL_v:
    case VE::VMINSWSXivm_v:
    case VE::VMINSWSXivml:
    case VE::VMINSWSXivml_v:
    case VE::VMINSWSXrvm:
    case VE::VMINSWSXrvmL:
    case VE::VMINSWSXrvmL_v:
    case VE::VMINSWSXrvm_v:
    case VE::VMINSWSXrvml:
    case VE::VMINSWSXrvml_v:
    case VE::VMINSWZXivm:
    case VE::VMINSWZXivmL:
    case VE::VMINSWZXivmL_v:
    case VE::VMINSWZXivm_v:
    case VE::VMINSWZXivml:
    case VE::VMINSWZXivml_v:
    case VE::VMINSWZXrvm:
    case VE::VMINSWZXrvmL:
    case VE::VMINSWZXrvmL_v:
    case VE::VMINSWZXrvm_v:
    case VE::VMINSWZXrvml:
    case VE::VMINSWZXrvml_v:
    case VE::VMRGWivm:
    case VE::VMRGWivmL:
    case VE::VMRGWivmL_v:
    case VE::VMRGWivm_v:
    case VE::VMRGWivml:
    case VE::VMRGWivml_v:
    case VE::VMRGWrvm:
    case VE::VMRGWrvmL:
    case VE::VMRGWrvmL_v:
    case VE::VMRGWrvm_v:
    case VE::VMRGWrvml:
    case VE::VMRGWrvml_v:
    case VE::VMRGivm:
    case VE::VMRGivmL:
    case VE::VMRGivmL_v:
    case VE::VMRGivm_v:
    case VE::VMRGivml:
    case VE::VMRGivml_v:
    case VE::VMRGrvm:
    case VE::VMRGrvmL:
    case VE::VMRGrvmL_v:
    case VE::VMRGrvm_v:
    case VE::VMRGrvml:
    case VE::VMRGrvml_v:
    case VE::VMULSLWivm:
    case VE::VMULSLWivmL:
    case VE::VMULSLWivmL_v:
    case VE::VMULSLWivm_v:
    case VE::VMULSLWivml:
    case VE::VMULSLWivml_v:
    case VE::VMULSLWrvm:
    case VE::VMULSLWrvmL:
    case VE::VMULSLWrvmL_v:
    case VE::VMULSLWrvm_v:
    case VE::VMULSLWrvml:
    case VE::VMULSLWrvml_v:
    case VE::VMULSLivm:
    case VE::VMULSLivmL:
    case VE::VMULSLivmL_v:
    case VE::VMULSLivm_v:
    case VE::VMULSLivml:
    case VE::VMULSLivml_v:
    case VE::VMULSLrvm:
    case VE::VMULSLrvmL:
    case VE::VMULSLrvmL_v:
    case VE::VMULSLrvm_v:
    case VE::VMULSLrvml:
    case VE::VMULSLrvml_v:
    case VE::VMULSWSXivm:
    case VE::VMULSWSXivmL:
    case VE::VMULSWSXivmL_v:
    case VE::VMULSWSXivm_v:
    case VE::VMULSWSXivml:
    case VE::VMULSWSXivml_v:
    case VE::VMULSWSXrvm:
    case VE::VMULSWSXrvmL:
    case VE::VMULSWSXrvmL_v:
    case VE::VMULSWSXrvm_v:
    case VE::VMULSWSXrvml:
    case VE::VMULSWSXrvml_v:
    case VE::VMULSWZXivm:
    case VE::VMULSWZXivmL:
    case VE::VMULSWZXivmL_v:
    case VE::VMULSWZXivm_v:
    case VE::VMULSWZXivml:
    case VE::VMULSWZXivml_v:
    case VE::VMULSWZXrvm:
    case VE::VMULSWZXrvmL:
    case VE::VMULSWZXrvmL_v:
    case VE::VMULSWZXrvm_v:
    case VE::VMULSWZXrvml:
    case VE::VMULSWZXrvml_v:
    case VE::VMULULivm:
    case VE::VMULULivmL:
    case VE::VMULULivmL_v:
    case VE::VMULULivm_v:
    case VE::VMULULivml:
    case VE::VMULULivml_v:
    case VE::VMULULrvm:
    case VE::VMULULrvmL:
    case VE::VMULULrvmL_v:
    case VE::VMULULrvm_v:
    case VE::VMULULrvml:
    case VE::VMULULrvml_v:
    case VE::VMULUWivm:
    case VE::VMULUWivmL:
    case VE::VMULUWivmL_v:
    case VE::VMULUWivm_v:
    case VE::VMULUWivml:
    case VE::VMULUWivml_v:
    case VE::VMULUWrvm:
    case VE::VMULUWrvmL:
    case VE::VMULUWrvmL_v:
    case VE::VMULUWrvm_v:
    case VE::VMULUWrvml:
    case VE::VMULUWrvml_v:
    case VE::VMVivm:
    case VE::VMVivmL:
    case VE::VMVivmL_v:
    case VE::VMVivm_v:
    case VE::VMVivml:
    case VE::VMVivml_v:
    case VE::VMVrvm:
    case VE::VMVrvmL:
    case VE::VMVrvmL_v:
    case VE::VMVrvm_v:
    case VE::VMVrvml:
    case VE::VMVrvml_v:
    case VE::VORmvm:
    case VE::VORmvmL:
    case VE::VORmvmL_v:
    case VE::VORmvm_v:
    case VE::VORmvml:
    case VE::VORmvml_v:
    case VE::VORrvm:
    case VE::VORrvmL:
    case VE::VORrvmL_v:
    case VE::VORrvm_v:
    case VE::VORrvml:
    case VE::VORrvml_v:
    case VE::VSUBSLivm:
    case VE::VSUBSLivmL:
    case VE::VSUBSLivmL_v:
    case VE::VSUBSLivm_v:
    case VE::VSUBSLivml:
    case VE::VSUBSLivml_v:
    case VE::VSUBSLrvm:
    case VE::VSUBSLrvmL:
    case VE::VSUBSLrvmL_v:
    case VE::VSUBSLrvm_v:
    case VE::VSUBSLrvml:
    case VE::VSUBSLrvml_v:
    case VE::VSUBSWSXivm:
    case VE::VSUBSWSXivmL:
    case VE::VSUBSWSXivmL_v:
    case VE::VSUBSWSXivm_v:
    case VE::VSUBSWSXivml:
    case VE::VSUBSWSXivml_v:
    case VE::VSUBSWSXrvm:
    case VE::VSUBSWSXrvmL:
    case VE::VSUBSWSXrvmL_v:
    case VE::VSUBSWSXrvm_v:
    case VE::VSUBSWSXrvml:
    case VE::VSUBSWSXrvml_v:
    case VE::VSUBSWZXivm:
    case VE::VSUBSWZXivmL:
    case VE::VSUBSWZXivmL_v:
    case VE::VSUBSWZXivm_v:
    case VE::VSUBSWZXivml:
    case VE::VSUBSWZXivml_v:
    case VE::VSUBSWZXrvm:
    case VE::VSUBSWZXrvmL:
    case VE::VSUBSWZXrvmL_v:
    case VE::VSUBSWZXrvm_v:
    case VE::VSUBSWZXrvml:
    case VE::VSUBSWZXrvml_v:
    case VE::VSUBULivm:
    case VE::VSUBULivmL:
    case VE::VSUBULivmL_v:
    case VE::VSUBULivm_v:
    case VE::VSUBULivml:
    case VE::VSUBULivml_v:
    case VE::VSUBULrvm:
    case VE::VSUBULrvmL:
    case VE::VSUBULrvmL_v:
    case VE::VSUBULrvm_v:
    case VE::VSUBULrvml:
    case VE::VSUBULrvml_v:
    case VE::VSUBUWivm:
    case VE::VSUBUWivmL:
    case VE::VSUBUWivmL_v:
    case VE::VSUBUWivm_v:
    case VE::VSUBUWivml:
    case VE::VSUBUWivml_v:
    case VE::VSUBUWrvm:
    case VE::VSUBUWrvmL:
    case VE::VSUBUWrvmL_v:
    case VE::VSUBUWrvm_v:
    case VE::VSUBUWrvml:
    case VE::VSUBUWrvml_v:
    case VE::VXORmvm:
    case VE::VXORmvmL:
    case VE::VXORmvmL_v:
    case VE::VXORmvm_v:
    case VE::VXORmvml:
    case VE::VXORmvml_v:
    case VE::VXORrvm:
    case VE::VXORrvmL:
    case VE::VXORrvmL_v:
    case VE::VXORrvm_v:
    case VE::VXORrvml:
    case VE::VXORrvml_v: {
      switch (OpNum) {
      case 3:
        // op: m
        return 48;
      case 1:
        // op: sy
        return 40;
      case 0:
        // op: vx
        return 24;
      case 2:
        // op: vz
        return 8;
      }
      break;
    }
    case VE::VDIVSLvim:
    case VE::VDIVSLvimL:
    case VE::VDIVSLvimL_v:
    case VE::VDIVSLvim_v:
    case VE::VDIVSLviml:
    case VE::VDIVSLviml_v:
    case VE::VDIVSLvrm:
    case VE::VDIVSLvrmL:
    case VE::VDIVSLvrmL_v:
    case VE::VDIVSLvrm_v:
    case VE::VDIVSLvrml:
    case VE::VDIVSLvrml_v:
    case VE::VDIVSWSXvim:
    case VE::VDIVSWSXvimL:
    case VE::VDIVSWSXvimL_v:
    case VE::VDIVSWSXvim_v:
    case VE::VDIVSWSXviml:
    case VE::VDIVSWSXviml_v:
    case VE::VDIVSWSXvrm:
    case VE::VDIVSWSXvrmL:
    case VE::VDIVSWSXvrmL_v:
    case VE::VDIVSWSXvrm_v:
    case VE::VDIVSWSXvrml:
    case VE::VDIVSWSXvrml_v:
    case VE::VDIVSWZXvim:
    case VE::VDIVSWZXvimL:
    case VE::VDIVSWZXvimL_v:
    case VE::VDIVSWZXvim_v:
    case VE::VDIVSWZXviml:
    case VE::VDIVSWZXviml_v:
    case VE::VDIVSWZXvrm:
    case VE::VDIVSWZXvrmL:
    case VE::VDIVSWZXvrmL_v:
    case VE::VDIVSWZXvrm_v:
    case VE::VDIVSWZXvrml:
    case VE::VDIVSWZXvrml_v:
    case VE::VDIVULvim:
    case VE::VDIVULvimL:
    case VE::VDIVULvimL_v:
    case VE::VDIVULvim_v:
    case VE::VDIVULviml:
    case VE::VDIVULviml_v:
    case VE::VDIVULvrm:
    case VE::VDIVULvrmL:
    case VE::VDIVULvrmL_v:
    case VE::VDIVULvrm_v:
    case VE::VDIVULvrml:
    case VE::VDIVULvrml_v:
    case VE::VDIVUWvim:
    case VE::VDIVUWvimL:
    case VE::VDIVUWvimL_v:
    case VE::VDIVUWvim_v:
    case VE::VDIVUWviml:
    case VE::VDIVUWviml_v:
    case VE::VDIVUWvrm:
    case VE::VDIVUWvrmL:
    case VE::VDIVUWvrmL_v:
    case VE::VDIVUWvrm_v:
    case VE::VDIVUWvrml:
    case VE::VDIVUWvrml_v:
    case VE::VFDIVDvim:
    case VE::VFDIVDvimL:
    case VE::VFDIVDvimL_v:
    case VE::VFDIVDvim_v:
    case VE::VFDIVDviml:
    case VE::VFDIVDviml_v:
    case VE::VFDIVDvrm:
    case VE::VFDIVDvrmL:
    case VE::VFDIVDvrmL_v:
    case VE::VFDIVDvrm_v:
    case VE::VFDIVDvrml:
    case VE::VFDIVDvrml_v:
    case VE::VFDIVSvim:
    case VE::VFDIVSvimL:
    case VE::VFDIVSvimL_v:
    case VE::VFDIVSvim_v:
    case VE::VFDIVSviml:
    case VE::VFDIVSviml_v:
    case VE::VFDIVSvrm:
    case VE::VFDIVSvrmL:
    case VE::VFDIVSvrmL_v:
    case VE::VFDIVSvrm_v:
    case VE::VFDIVSvrml:
    case VE::VFDIVSvrml_v: {
      switch (OpNum) {
      case 3:
        // op: m
        return 48;
      case 2:
        // op: sy
        return 40;
      case 0:
        // op: vx
        return 24;
      case 1:
        // op: vy
        return 16;
      }
      break;
    }
    case VE::PVSLALOvim:
    case VE::PVSLALOvimL:
    case VE::PVSLALOvimL_v:
    case VE::PVSLALOvim_v:
    case VE::PVSLALOviml:
    case VE::PVSLALOviml_v:
    case VE::PVSLALOvrm:
    case VE::PVSLALOvrmL:
    case VE::PVSLALOvrmL_v:
    case VE::PVSLALOvrm_v:
    case VE::PVSLALOvrml:
    case VE::PVSLALOvrml_v:
    case VE::PVSLAUPvim:
    case VE::PVSLAUPvimL:
    case VE::PVSLAUPvimL_v:
    case VE::PVSLAUPvim_v:
    case VE::PVSLAUPviml:
    case VE::PVSLAUPviml_v:
    case VE::PVSLAUPvrm:
    case VE::PVSLAUPvrmL:
    case VE::PVSLAUPvrmL_v:
    case VE::PVSLAUPvrm_v:
    case VE::PVSLAUPvrml:
    case VE::PVSLAUPvrml_v:
    case VE::PVSLAvim:
    case VE::PVSLAvimL:
    case VE::PVSLAvimL_v:
    case VE::PVSLAvim_v:
    case VE::PVSLAviml:
    case VE::PVSLAviml_v:
    case VE::PVSLAvrm:
    case VE::PVSLAvrmL:
    case VE::PVSLAvrmL_v:
    case VE::PVSLAvrm_v:
    case VE::PVSLAvrml:
    case VE::PVSLAvrml_v:
    case VE::PVSLLLOvim:
    case VE::PVSLLLOvimL:
    case VE::PVSLLLOvimL_v:
    case VE::PVSLLLOvim_v:
    case VE::PVSLLLOviml:
    case VE::PVSLLLOviml_v:
    case VE::PVSLLLOvrm:
    case VE::PVSLLLOvrmL:
    case VE::PVSLLLOvrmL_v:
    case VE::PVSLLLOvrm_v:
    case VE::PVSLLLOvrml:
    case VE::PVSLLLOvrml_v:
    case VE::PVSLLUPvim:
    case VE::PVSLLUPvimL:
    case VE::PVSLLUPvimL_v:
    case VE::PVSLLUPvim_v:
    case VE::PVSLLUPviml:
    case VE::PVSLLUPviml_v:
    case VE::PVSLLUPvrm:
    case VE::PVSLLUPvrmL:
    case VE::PVSLLUPvrmL_v:
    case VE::PVSLLUPvrm_v:
    case VE::PVSLLUPvrml:
    case VE::PVSLLUPvrml_v:
    case VE::PVSLLvim:
    case VE::PVSLLvimL:
    case VE::PVSLLvimL_v:
    case VE::PVSLLvim_v:
    case VE::PVSLLviml:
    case VE::PVSLLviml_v:
    case VE::PVSLLvrm:
    case VE::PVSLLvrmL:
    case VE::PVSLLvrmL_v:
    case VE::PVSLLvrm_v:
    case VE::PVSLLvrml:
    case VE::PVSLLvrml_v:
    case VE::PVSRALOvim:
    case VE::PVSRALOvimL:
    case VE::PVSRALOvimL_v:
    case VE::PVSRALOvim_v:
    case VE::PVSRALOviml:
    case VE::PVSRALOviml_v:
    case VE::PVSRALOvrm:
    case VE::PVSRALOvrmL:
    case VE::PVSRALOvrmL_v:
    case VE::PVSRALOvrm_v:
    case VE::PVSRALOvrml:
    case VE::PVSRALOvrml_v:
    case VE::PVSRAUPvim:
    case VE::PVSRAUPvimL:
    case VE::PVSRAUPvimL_v:
    case VE::PVSRAUPvim_v:
    case VE::PVSRAUPviml:
    case VE::PVSRAUPviml_v:
    case VE::PVSRAUPvrm:
    case VE::PVSRAUPvrmL:
    case VE::PVSRAUPvrmL_v:
    case VE::PVSRAUPvrm_v:
    case VE::PVSRAUPvrml:
    case VE::PVSRAUPvrml_v:
    case VE::PVSRAvim:
    case VE::PVSRAvimL:
    case VE::PVSRAvimL_v:
    case VE::PVSRAvim_v:
    case VE::PVSRAviml:
    case VE::PVSRAviml_v:
    case VE::PVSRAvrm:
    case VE::PVSRAvrmL:
    case VE::PVSRAvrmL_v:
    case VE::PVSRAvrm_v:
    case VE::PVSRAvrml:
    case VE::PVSRAvrml_v:
    case VE::PVSRLLOvim:
    case VE::PVSRLLOvimL:
    case VE::PVSRLLOvimL_v:
    case VE::PVSRLLOvim_v:
    case VE::PVSRLLOviml:
    case VE::PVSRLLOviml_v:
    case VE::PVSRLLOvrm:
    case VE::PVSRLLOvrmL:
    case VE::PVSRLLOvrmL_v:
    case VE::PVSRLLOvrm_v:
    case VE::PVSRLLOvrml:
    case VE::PVSRLLOvrml_v:
    case VE::PVSRLUPvim:
    case VE::PVSRLUPvimL:
    case VE::PVSRLUPvimL_v:
    case VE::PVSRLUPvim_v:
    case VE::PVSRLUPviml:
    case VE::PVSRLUPviml_v:
    case VE::PVSRLUPvrm:
    case VE::PVSRLUPvrmL:
    case VE::PVSRLUPvrmL_v:
    case VE::PVSRLUPvrm_v:
    case VE::PVSRLUPvrml:
    case VE::PVSRLUPvrml_v:
    case VE::PVSRLvim:
    case VE::PVSRLvimL:
    case VE::PVSRLvimL_v:
    case VE::PVSRLvim_v:
    case VE::PVSRLviml:
    case VE::PVSRLviml_v:
    case VE::PVSRLvrm:
    case VE::PVSRLvrmL:
    case VE::PVSRLvrmL_v:
    case VE::PVSRLvrm_v:
    case VE::PVSRLvrml:
    case VE::PVSRLvrml_v:
    case VE::VSLALvim:
    case VE::VSLALvimL:
    case VE::VSLALvimL_v:
    case VE::VSLALvim_v:
    case VE::VSLALviml:
    case VE::VSLALviml_v:
    case VE::VSLALvrm:
    case VE::VSLALvrmL:
    case VE::VSLALvrmL_v:
    case VE::VSLALvrm_v:
    case VE::VSLALvrml:
    case VE::VSLALvrml_v:
    case VE::VSLAWSXvim:
    case VE::VSLAWSXvimL:
    case VE::VSLAWSXvimL_v:
    case VE::VSLAWSXvim_v:
    case VE::VSLAWSXviml:
    case VE::VSLAWSXviml_v:
    case VE::VSLAWSXvrm:
    case VE::VSLAWSXvrmL:
    case VE::VSLAWSXvrmL_v:
    case VE::VSLAWSXvrm_v:
    case VE::VSLAWSXvrml:
    case VE::VSLAWSXvrml_v:
    case VE::VSLAWZXvim:
    case VE::VSLAWZXvimL:
    case VE::VSLAWZXvimL_v:
    case VE::VSLAWZXvim_v:
    case VE::VSLAWZXviml:
    case VE::VSLAWZXviml_v:
    case VE::VSLAWZXvrm:
    case VE::VSLAWZXvrmL:
    case VE::VSLAWZXvrmL_v:
    case VE::VSLAWZXvrm_v:
    case VE::VSLAWZXvrml:
    case VE::VSLAWZXvrml_v:
    case VE::VSLLvim:
    case VE::VSLLvimL:
    case VE::VSLLvimL_v:
    case VE::VSLLvim_v:
    case VE::VSLLviml:
    case VE::VSLLviml_v:
    case VE::VSLLvrm:
    case VE::VSLLvrmL:
    case VE::VSLLvrmL_v:
    case VE::VSLLvrm_v:
    case VE::VSLLvrml:
    case VE::VSLLvrml_v:
    case VE::VSRALvim:
    case VE::VSRALvimL:
    case VE::VSRALvimL_v:
    case VE::VSRALvim_v:
    case VE::VSRALviml:
    case VE::VSRALviml_v:
    case VE::VSRALvrm:
    case VE::VSRALvrmL:
    case VE::VSRALvrmL_v:
    case VE::VSRALvrm_v:
    case VE::VSRALvrml:
    case VE::VSRALvrml_v:
    case VE::VSRAWSXvim:
    case VE::VSRAWSXvimL:
    case VE::VSRAWSXvimL_v:
    case VE::VSRAWSXvim_v:
    case VE::VSRAWSXviml:
    case VE::VSRAWSXviml_v:
    case VE::VSRAWSXvrm:
    case VE::VSRAWSXvrmL:
    case VE::VSRAWSXvrmL_v:
    case VE::VSRAWSXvrm_v:
    case VE::VSRAWSXvrml:
    case VE::VSRAWSXvrml_v:
    case VE::VSRAWZXvim:
    case VE::VSRAWZXvimL:
    case VE::VSRAWZXvimL_v:
    case VE::VSRAWZXvim_v:
    case VE::VSRAWZXviml:
    case VE::VSRAWZXviml_v:
    case VE::VSRAWZXvrm:
    case VE::VSRAWZXvrmL:
    case VE::VSRAWZXvrmL_v:
    case VE::VSRAWZXvrm_v:
    case VE::VSRAWZXvrml:
    case VE::VSRAWZXvrml_v:
    case VE::VSRLvim:
    case VE::VSRLvimL:
    case VE::VSRLvimL_v:
    case VE::VSRLvim_v:
    case VE::VSRLviml:
    case VE::VSRLviml_v:
    case VE::VSRLvrm:
    case VE::VSRLvrmL:
    case VE::VSRLvrmL_v:
    case VE::VSRLvrm_v:
    case VE::VSRLvrml:
    case VE::VSRLvrml_v: {
      switch (OpNum) {
      case 3:
        // op: m
        return 48;
      case 2:
        // op: sy
        return 40;
      case 0:
        // op: vx
        return 24;
      case 1:
        // op: vz
        return 8;
      }
      break;
    }
    case VE::ST1Brii:
    case VE::ST1Brri:
    case VE::ST1Bzii:
    case VE::ST1Bzri:
    case VE::ST2Brii:
    case VE::ST2Brri:
    case VE::ST2Bzii:
    case VE::ST2Bzri:
    case VE::STLrii:
    case VE::STLrri:
    case VE::STLzii:
    case VE::STLzri:
    case VE::STUrii:
    case VE::STUrri:
    case VE::STUzii:
    case VE::STUzri:
    case VE::STrii:
    case VE::STrri:
    case VE::STzii:
    case VE::STzri: {
      switch (OpNum) {
      case 3:
        // op: sx
        return 48;
      case 0:
        // op: sz
        return 32;
      case 1:
        // op: sy
        return 40;
      case 2:
        // op: imm32
        return 0;
      }
      break;
    }
    case VE::VFIAMDvvi:
    case VE::VFIAMDvviL:
    case VE::VFIAMDvviL_v:
    case VE::VFIAMDvvi_v:
    case VE::VFIAMDvvil:
    case VE::VFIAMDvvil_v:
    case VE::VFIAMDvvr:
    case VE::VFIAMDvvrL:
    case VE::VFIAMDvvrL_v:
    case VE::VFIAMDvvr_v:
    case VE::VFIAMDvvrl:
    case VE::VFIAMDvvrl_v:
    case VE::VFIAMSvvi:
    case VE::VFIAMSvviL:
    case VE::VFIAMSvviL_v:
    case VE::VFIAMSvvi_v:
    case VE::VFIAMSvvil:
    case VE::VFIAMSvvil_v:
    case VE::VFIAMSvvr:
    case VE::VFIAMSvvrL:
    case VE::VFIAMSvvrL_v:
    case VE::VFIAMSvvr_v:
    case VE::VFIAMSvvrl:
    case VE::VFIAMSvvrl_v:
    case VE::VFIMADvvi:
    case VE::VFIMADvviL:
    case VE::VFIMADvviL_v:
    case VE::VFIMADvvi_v:
    case VE::VFIMADvvil:
    case VE::VFIMADvvil_v:
    case VE::VFIMADvvr:
    case VE::VFIMADvvrL:
    case VE::VFIMADvvrL_v:
    case VE::VFIMADvvr_v:
    case VE::VFIMADvvrl:
    case VE::VFIMADvvrl_v:
    case VE::VFIMASvvi:
    case VE::VFIMASvviL:
    case VE::VFIMASvviL_v:
    case VE::VFIMASvvi_v:
    case VE::VFIMASvvil:
    case VE::VFIMASvvil_v:
    case VE::VFIMASvvr:
    case VE::VFIMASvvrL:
    case VE::VFIMASvvrL_v:
    case VE::VFIMASvvr_v:
    case VE::VFIMASvvrl:
    case VE::VFIMASvvrl_v:
    case VE::VFIMSDvvi:
    case VE::VFIMSDvviL:
    case VE::VFIMSDvviL_v:
    case VE::VFIMSDvvi_v:
    case VE::VFIMSDvvil:
    case VE::VFIMSDvvil_v:
    case VE::VFIMSDvvr:
    case VE::VFIMSDvvrL:
    case VE::VFIMSDvvrL_v:
    case VE::VFIMSDvvr_v:
    case VE::VFIMSDvvrl:
    case VE::VFIMSDvvrl_v:
    case VE::VFIMSSvvi:
    case VE::VFIMSSvviL:
    case VE::VFIMSSvviL_v:
    case VE::VFIMSSvvi_v:
    case VE::VFIMSSvvil:
    case VE::VFIMSSvvil_v:
    case VE::VFIMSSvvr:
    case VE::VFIMSSvvrL:
    case VE::VFIMSSvvrL_v:
    case VE::VFIMSSvvr_v:
    case VE::VFIMSSvvrl:
    case VE::VFIMSSvvrl_v:
    case VE::VFISMDvvi:
    case VE::VFISMDvviL:
    case VE::VFISMDvviL_v:
    case VE::VFISMDvvi_v:
    case VE::VFISMDvvil:
    case VE::VFISMDvvil_v:
    case VE::VFISMDvvr:
    case VE::VFISMDvvrL:
    case VE::VFISMDvvrL_v:
    case VE::VFISMDvvr_v:
    case VE::VFISMDvvrl:
    case VE::VFISMDvvrl_v:
    case VE::VFISMSvvi:
    case VE::VFISMSvviL:
    case VE::VFISMSvviL_v:
    case VE::VFISMSvvi_v:
    case VE::VFISMSvvil:
    case VE::VFISMSvvil_v:
    case VE::VFISMSvvr:
    case VE::VFISMSvvrL:
    case VE::VFISMSvvrL_v:
    case VE::VFISMSvvr_v:
    case VE::VFISMSvvrl:
    case VE::VFISMSvvrl_v:
    case VE::VSHFvvi:
    case VE::VSHFvviL:
    case VE::VSHFvviL_v:
    case VE::VSHFvvi_v:
    case VE::VSHFvvil:
    case VE::VSHFvvil_v:
    case VE::VSHFvvr:
    case VE::VSHFvvrL:
    case VE::VSHFvvrL_v:
    case VE::VSHFvvr_v:
    case VE::VSHFvvrl:
    case VE::VSHFvvrl_v:
    case VE::VSLDvvi:
    case VE::VSLDvviL:
    case VE::VSLDvviL_v:
    case VE::VSLDvvi_v:
    case VE::VSLDvvil:
    case VE::VSLDvvil_v:
    case VE::VSLDvvr:
    case VE::VSLDvvrL:
    case VE::VSLDvvrL_v:
    case VE::VSLDvvr_v:
    case VE::VSLDvvrl:
    case VE::VSLDvvrl_v:
    case VE::VSRDvvi:
    case VE::VSRDvviL:
    case VE::VSRDvviL_v:
    case VE::VSRDvvi_v:
    case VE::VSRDvvil:
    case VE::VSRDvvil_v:
    case VE::VSRDvvr:
    case VE::VSRDvvrL:
    case VE::VSRDvvrL_v:
    case VE::VSRDvvr_v:
    case VE::VSRDvvrl:
    case VE::VSRDvvrl_v: {
      switch (OpNum) {
      case 3:
        // op: sy
        return 40;
      case 0:
        // op: vx
        return 24;
      case 1:
        // op: vy
        return 16;
      case 2:
        // op: vz
        return 8;
      }
      break;
    }
    case VE::PVFMADLOvvvm:
    case VE::PVFMADLOvvvmL:
    case VE::PVFMADLOvvvmL_v:
    case VE::PVFMADLOvvvm_v:
    case VE::PVFMADLOvvvml:
    case VE::PVFMADLOvvvml_v:
    case VE::PVFMADUPvvvm:
    case VE::PVFMADUPvvvmL:
    case VE::PVFMADUPvvvmL_v:
    case VE::PVFMADUPvvvm_v:
    case VE::PVFMADUPvvvml:
    case VE::PVFMADUPvvvml_v:
    case VE::PVFMADvvvm:
    case VE::PVFMADvvvmL:
    case VE::PVFMADvvvmL_v:
    case VE::PVFMADvvvm_v:
    case VE::PVFMADvvvml:
    case VE::PVFMADvvvml_v:
    case VE::PVFMSBLOvvvm:
    case VE::PVFMSBLOvvvmL:
    case VE::PVFMSBLOvvvmL_v:
    case VE::PVFMSBLOvvvm_v:
    case VE::PVFMSBLOvvvml:
    case VE::PVFMSBLOvvvml_v:
    case VE::PVFMSBUPvvvm:
    case VE::PVFMSBUPvvvmL:
    case VE::PVFMSBUPvvvmL_v:
    case VE::PVFMSBUPvvvm_v:
    case VE::PVFMSBUPvvvml:
    case VE::PVFMSBUPvvvml_v:
    case VE::PVFMSBvvvm:
    case VE::PVFMSBvvvmL:
    case VE::PVFMSBvvvmL_v:
    case VE::PVFMSBvvvm_v:
    case VE::PVFMSBvvvml:
    case VE::PVFMSBvvvml_v:
    case VE::PVFNMADLOvvvm:
    case VE::PVFNMADLOvvvmL:
    case VE::PVFNMADLOvvvmL_v:
    case VE::PVFNMADLOvvvm_v:
    case VE::PVFNMADLOvvvml:
    case VE::PVFNMADLOvvvml_v:
    case VE::PVFNMADUPvvvm:
    case VE::PVFNMADUPvvvmL:
    case VE::PVFNMADUPvvvmL_v:
    case VE::PVFNMADUPvvvm_v:
    case VE::PVFNMADUPvvvml:
    case VE::PVFNMADUPvvvml_v:
    case VE::PVFNMADvvvm:
    case VE::PVFNMADvvvmL:
    case VE::PVFNMADvvvmL_v:
    case VE::PVFNMADvvvm_v:
    case VE::PVFNMADvvvml:
    case VE::PVFNMADvvvml_v:
    case VE::PVFNMSBLOvvvm:
    case VE::PVFNMSBLOvvvmL:
    case VE::PVFNMSBLOvvvmL_v:
    case VE::PVFNMSBLOvvvm_v:
    case VE::PVFNMSBLOvvvml:
    case VE::PVFNMSBLOvvvml_v:
    case VE::PVFNMSBUPvvvm:
    case VE::PVFNMSBUPvvvmL:
    case VE::PVFNMSBUPvvvmL_v:
    case VE::PVFNMSBUPvvvm_v:
    case VE::PVFNMSBUPvvvml:
    case VE::PVFNMSBUPvvvml_v:
    case VE::PVFNMSBvvvm:
    case VE::PVFNMSBvvvmL:
    case VE::PVFNMSBvvvmL_v:
    case VE::PVFNMSBvvvm_v:
    case VE::PVFNMSBvvvml:
    case VE::PVFNMSBvvvml_v:
    case VE::VFMADDvvvm:
    case VE::VFMADDvvvmL:
    case VE::VFMADDvvvmL_v:
    case VE::VFMADDvvvm_v:
    case VE::VFMADDvvvml:
    case VE::VFMADDvvvml_v:
    case VE::VFMADSvvvm:
    case VE::VFMADSvvvmL:
    case VE::VFMADSvvvmL_v:
    case VE::VFMADSvvvm_v:
    case VE::VFMADSvvvml:
    case VE::VFMADSvvvml_v:
    case VE::VFMSBDvvvm:
    case VE::VFMSBDvvvmL:
    case VE::VFMSBDvvvmL_v:
    case VE::VFMSBDvvvm_v:
    case VE::VFMSBDvvvml:
    case VE::VFMSBDvvvml_v:
    case VE::VFMSBSvvvm:
    case VE::VFMSBSvvvmL:
    case VE::VFMSBSvvvmL_v:
    case VE::VFMSBSvvvm_v:
    case VE::VFMSBSvvvml:
    case VE::VFMSBSvvvml_v:
    case VE::VFNMADDvvvm:
    case VE::VFNMADDvvvmL:
    case VE::VFNMADDvvvmL_v:
    case VE::VFNMADDvvvm_v:
    case VE::VFNMADDvvvml:
    case VE::VFNMADDvvvml_v:
    case VE::VFNMADSvvvm:
    case VE::VFNMADSvvvmL:
    case VE::VFNMADSvvvmL_v:
    case VE::VFNMADSvvvm_v:
    case VE::VFNMADSvvvml:
    case VE::VFNMADSvvvml_v:
    case VE::VFNMSBDvvvm:
    case VE::VFNMSBDvvvmL:
    case VE::VFNMSBDvvvmL_v:
    case VE::VFNMSBDvvvm_v:
    case VE::VFNMSBDvvvml:
    case VE::VFNMSBDvvvml_v:
    case VE::VFNMSBSvvvm:
    case VE::VFNMSBSvvvmL:
    case VE::VFNMSBSvvvmL_v:
    case VE::VFNMSBSvvvm_v:
    case VE::VFNMSBSvvvml:
    case VE::VFNMSBSvvvml_v: {
      switch (OpNum) {
      case 4:
        // op: m
        return 48;
      case 0:
        // op: vx
        return 24;
      case 1:
        // op: vy
        return 16;
      case 2:
        // op: vz
        return 8;
      case 3:
        // op: vw
        return 0;
      }
      break;
    }
    case VE::PVFMADLOivvm:
    case VE::PVFMADLOivvmL:
    case VE::PVFMADLOivvmL_v:
    case VE::PVFMADLOivvm_v:
    case VE::PVFMADLOivvml:
    case VE::PVFMADLOivvml_v:
    case VE::PVFMADLOrvvm:
    case VE::PVFMADLOrvvmL:
    case VE::PVFMADLOrvvmL_v:
    case VE::PVFMADLOrvvm_v:
    case VE::PVFMADLOrvvml:
    case VE::PVFMADLOrvvml_v:
    case VE::PVFMADUPivvm:
    case VE::PVFMADUPivvmL:
    case VE::PVFMADUPivvmL_v:
    case VE::PVFMADUPivvm_v:
    case VE::PVFMADUPivvml:
    case VE::PVFMADUPivvml_v:
    case VE::PVFMADUPrvvm:
    case VE::PVFMADUPrvvmL:
    case VE::PVFMADUPrvvmL_v:
    case VE::PVFMADUPrvvm_v:
    case VE::PVFMADUPrvvml:
    case VE::PVFMADUPrvvml_v:
    case VE::PVFMADivvm:
    case VE::PVFMADivvmL:
    case VE::PVFMADivvmL_v:
    case VE::PVFMADivvm_v:
    case VE::PVFMADivvml:
    case VE::PVFMADivvml_v:
    case VE::PVFMADrvvm:
    case VE::PVFMADrvvmL:
    case VE::PVFMADrvvmL_v:
    case VE::PVFMADrvvm_v:
    case VE::PVFMADrvvml:
    case VE::PVFMADrvvml_v:
    case VE::PVFMSBLOivvm:
    case VE::PVFMSBLOivvmL:
    case VE::PVFMSBLOivvmL_v:
    case VE::PVFMSBLOivvm_v:
    case VE::PVFMSBLOivvml:
    case VE::PVFMSBLOivvml_v:
    case VE::PVFMSBLOrvvm:
    case VE::PVFMSBLOrvvmL:
    case VE::PVFMSBLOrvvmL_v:
    case VE::PVFMSBLOrvvm_v:
    case VE::PVFMSBLOrvvml:
    case VE::PVFMSBLOrvvml_v:
    case VE::PVFMSBUPivvm:
    case VE::PVFMSBUPivvmL:
    case VE::PVFMSBUPivvmL_v:
    case VE::PVFMSBUPivvm_v:
    case VE::PVFMSBUPivvml:
    case VE::PVFMSBUPivvml_v:
    case VE::PVFMSBUPrvvm:
    case VE::PVFMSBUPrvvmL:
    case VE::PVFMSBUPrvvmL_v:
    case VE::PVFMSBUPrvvm_v:
    case VE::PVFMSBUPrvvml:
    case VE::PVFMSBUPrvvml_v:
    case VE::PVFMSBivvm:
    case VE::PVFMSBivvmL:
    case VE::PVFMSBivvmL_v:
    case VE::PVFMSBivvm_v:
    case VE::PVFMSBivvml:
    case VE::PVFMSBivvml_v:
    case VE::PVFMSBrvvm:
    case VE::PVFMSBrvvmL:
    case VE::PVFMSBrvvmL_v:
    case VE::PVFMSBrvvm_v:
    case VE::PVFMSBrvvml:
    case VE::PVFMSBrvvml_v:
    case VE::PVFNMADLOivvm:
    case VE::PVFNMADLOivvmL:
    case VE::PVFNMADLOivvmL_v:
    case VE::PVFNMADLOivvm_v:
    case VE::PVFNMADLOivvml:
    case VE::PVFNMADLOivvml_v:
    case VE::PVFNMADLOrvvm:
    case VE::PVFNMADLOrvvmL:
    case VE::PVFNMADLOrvvmL_v:
    case VE::PVFNMADLOrvvm_v:
    case VE::PVFNMADLOrvvml:
    case VE::PVFNMADLOrvvml_v:
    case VE::PVFNMADUPivvm:
    case VE::PVFNMADUPivvmL:
    case VE::PVFNMADUPivvmL_v:
    case VE::PVFNMADUPivvm_v:
    case VE::PVFNMADUPivvml:
    case VE::PVFNMADUPivvml_v:
    case VE::PVFNMADUPrvvm:
    case VE::PVFNMADUPrvvmL:
    case VE::PVFNMADUPrvvmL_v:
    case VE::PVFNMADUPrvvm_v:
    case VE::PVFNMADUPrvvml:
    case VE::PVFNMADUPrvvml_v:
    case VE::PVFNMADivvm:
    case VE::PVFNMADivvmL:
    case VE::PVFNMADivvmL_v:
    case VE::PVFNMADivvm_v:
    case VE::PVFNMADivvml:
    case VE::PVFNMADivvml_v:
    case VE::PVFNMADrvvm:
    case VE::PVFNMADrvvmL:
    case VE::PVFNMADrvvmL_v:
    case VE::PVFNMADrvvm_v:
    case VE::PVFNMADrvvml:
    case VE::PVFNMADrvvml_v:
    case VE::PVFNMSBLOivvm:
    case VE::PVFNMSBLOivvmL:
    case VE::PVFNMSBLOivvmL_v:
    case VE::PVFNMSBLOivvm_v:
    case VE::PVFNMSBLOivvml:
    case VE::PVFNMSBLOivvml_v:
    case VE::PVFNMSBLOrvvm:
    case VE::PVFNMSBLOrvvmL:
    case VE::PVFNMSBLOrvvmL_v:
    case VE::PVFNMSBLOrvvm_v:
    case VE::PVFNMSBLOrvvml:
    case VE::PVFNMSBLOrvvml_v:
    case VE::PVFNMSBUPivvm:
    case VE::PVFNMSBUPivvmL:
    case VE::PVFNMSBUPivvmL_v:
    case VE::PVFNMSBUPivvm_v:
    case VE::PVFNMSBUPivvml:
    case VE::PVFNMSBUPivvml_v:
    case VE::PVFNMSBUPrvvm:
    case VE::PVFNMSBUPrvvmL:
    case VE::PVFNMSBUPrvvmL_v:
    case VE::PVFNMSBUPrvvm_v:
    case VE::PVFNMSBUPrvvml:
    case VE::PVFNMSBUPrvvml_v:
    case VE::PVFNMSBivvm:
    case VE::PVFNMSBivvmL:
    case VE::PVFNMSBivvmL_v:
    case VE::PVFNMSBivvm_v:
    case VE::PVFNMSBivvml:
    case VE::PVFNMSBivvml_v:
    case VE::PVFNMSBrvvm:
    case VE::PVFNMSBrvvmL:
    case VE::PVFNMSBrvvmL_v:
    case VE::PVFNMSBrvvm_v:
    case VE::PVFNMSBrvvml:
    case VE::PVFNMSBrvvml_v:
    case VE::VFMADDivvm:
    case VE::VFMADDivvmL:
    case VE::VFMADDivvmL_v:
    case VE::VFMADDivvm_v:
    case VE::VFMADDivvml:
    case VE::VFMADDivvml_v:
    case VE::VFMADDrvvm:
    case VE::VFMADDrvvmL:
    case VE::VFMADDrvvmL_v:
    case VE::VFMADDrvvm_v:
    case VE::VFMADDrvvml:
    case VE::VFMADDrvvml_v:
    case VE::VFMADSivvm:
    case VE::VFMADSivvmL:
    case VE::VFMADSivvmL_v:
    case VE::VFMADSivvm_v:
    case VE::VFMADSivvml:
    case VE::VFMADSivvml_v:
    case VE::VFMADSrvvm:
    case VE::VFMADSrvvmL:
    case VE::VFMADSrvvmL_v:
    case VE::VFMADSrvvm_v:
    case VE::VFMADSrvvml:
    case VE::VFMADSrvvml_v:
    case VE::VFMSBDivvm:
    case VE::VFMSBDivvmL:
    case VE::VFMSBDivvmL_v:
    case VE::VFMSBDivvm_v:
    case VE::VFMSBDivvml:
    case VE::VFMSBDivvml_v:
    case VE::VFMSBDrvvm:
    case VE::VFMSBDrvvmL:
    case VE::VFMSBDrvvmL_v:
    case VE::VFMSBDrvvm_v:
    case VE::VFMSBDrvvml:
    case VE::VFMSBDrvvml_v:
    case VE::VFMSBSivvm:
    case VE::VFMSBSivvmL:
    case VE::VFMSBSivvmL_v:
    case VE::VFMSBSivvm_v:
    case VE::VFMSBSivvml:
    case VE::VFMSBSivvml_v:
    case VE::VFMSBSrvvm:
    case VE::VFMSBSrvvmL:
    case VE::VFMSBSrvvmL_v:
    case VE::VFMSBSrvvm_v:
    case VE::VFMSBSrvvml:
    case VE::VFMSBSrvvml_v:
    case VE::VFNMADDivvm:
    case VE::VFNMADDivvmL:
    case VE::VFNMADDivvmL_v:
    case VE::VFNMADDivvm_v:
    case VE::VFNMADDivvml:
    case VE::VFNMADDivvml_v:
    case VE::VFNMADDrvvm:
    case VE::VFNMADDrvvmL:
    case VE::VFNMADDrvvmL_v:
    case VE::VFNMADDrvvm_v:
    case VE::VFNMADDrvvml:
    case VE::VFNMADDrvvml_v:
    case VE::VFNMADSivvm:
    case VE::VFNMADSivvmL:
    case VE::VFNMADSivvmL_v:
    case VE::VFNMADSivvm_v:
    case VE::VFNMADSivvml:
    case VE::VFNMADSivvml_v:
    case VE::VFNMADSrvvm:
    case VE::VFNMADSrvvmL:
    case VE::VFNMADSrvvmL_v:
    case VE::VFNMADSrvvm_v:
    case VE::VFNMADSrvvml:
    case VE::VFNMADSrvvml_v:
    case VE::VFNMSBDivvm:
    case VE::VFNMSBDivvmL:
    case VE::VFNMSBDivvmL_v:
    case VE::VFNMSBDivvm_v:
    case VE::VFNMSBDivvml:
    case VE::VFNMSBDivvml_v:
    case VE::VFNMSBDrvvm:
    case VE::VFNMSBDrvvmL:
    case VE::VFNMSBDrvvmL_v:
    case VE::VFNMSBDrvvm_v:
    case VE::VFNMSBDrvvml:
    case VE::VFNMSBDrvvml_v:
    case VE::VFNMSBSivvm:
    case VE::VFNMSBSivvmL:
    case VE::VFNMSBSivvmL_v:
    case VE::VFNMSBSivvm_v:
    case VE::VFNMSBSivvml:
    case VE::VFNMSBSivvml_v:
    case VE::VFNMSBSrvvm:
    case VE::VFNMSBSrvvmL:
    case VE::VFNMSBSrvvmL_v:
    case VE::VFNMSBSrvvm_v:
    case VE::VFNMSBSrvvml:
    case VE::VFNMSBSrvvml_v: {
      switch (OpNum) {
      case 4:
        // op: m
        return 48;
      case 1:
        // op: sy
        return 40;
      case 0:
        // op: vx
        return 24;
      case 2:
        // op: vz
        return 8;
      case 3:
        // op: vw
        return 0;
      }
      break;
    }
    case VE::VSCLNCOTsirvm:
    case VE::VSCLNCOTsirvmL:
    case VE::VSCLNCOTsirvml:
    case VE::VSCLNCOTsizvm:
    case VE::VSCLNCOTsizvmL:
    case VE::VSCLNCOTsizvml:
    case VE::VSCLNCOTsrrvm:
    case VE::VSCLNCOTsrrvmL:
    case VE::VSCLNCOTsrrvml:
    case VE::VSCLNCOTsrzvm:
    case VE::VSCLNCOTsrzvmL:
    case VE::VSCLNCOTsrzvml:
    case VE::VSCLNCsirvm:
    case VE::VSCLNCsirvmL:
    case VE::VSCLNCsirvml:
    case VE::VSCLNCsizvm:
    case VE::VSCLNCsizvmL:
    case VE::VSCLNCsizvml:
    case VE::VSCLNCsrrvm:
    case VE::VSCLNCsrrvmL:
    case VE::VSCLNCsrrvml:
    case VE::VSCLNCsrzvm:
    case VE::VSCLNCsrzvmL:
    case VE::VSCLNCsrzvml:
    case VE::VSCLOTsirvm:
    case VE::VSCLOTsirvmL:
    case VE::VSCLOTsirvml:
    case VE::VSCLOTsizvm:
    case VE::VSCLOTsizvmL:
    case VE::VSCLOTsizvml:
    case VE::VSCLOTsrrvm:
    case VE::VSCLOTsrrvmL:
    case VE::VSCLOTsrrvml:
    case VE::VSCLOTsrzvm:
    case VE::VSCLOTsrzvmL:
    case VE::VSCLOTsrzvml:
    case VE::VSCLsirvm:
    case VE::VSCLsirvmL:
    case VE::VSCLsirvml:
    case VE::VSCLsizvm:
    case VE::VSCLsizvmL:
    case VE::VSCLsizvml:
    case VE::VSCLsrrvm:
    case VE::VSCLsrrvmL:
    case VE::VSCLsrrvml:
    case VE::VSCLsrzvm:
    case VE::VSCLsrzvmL:
    case VE::VSCLsrzvml:
    case VE::VSCNCOTsirvm:
    case VE::VSCNCOTsirvmL:
    case VE::VSCNCOTsirvml:
    case VE::VSCNCOTsizvm:
    case VE::VSCNCOTsizvmL:
    case VE::VSCNCOTsizvml:
    case VE::VSCNCOTsrrvm:
    case VE::VSCNCOTsrrvmL:
    case VE::VSCNCOTsrrvml:
    case VE::VSCNCOTsrzvm:
    case VE::VSCNCOTsrzvmL:
    case VE::VSCNCOTsrzvml:
    case VE::VSCNCsirvm:
    case VE::VSCNCsirvmL:
    case VE::VSCNCsirvml:
    case VE::VSCNCsizvm:
    case VE::VSCNCsizvmL:
    case VE::VSCNCsizvml:
    case VE::VSCNCsrrvm:
    case VE::VSCNCsrrvmL:
    case VE::VSCNCsrrvml:
    case VE::VSCNCsrzvm:
    case VE::VSCNCsrzvmL:
    case VE::VSCNCsrzvml:
    case VE::VSCOTsirvm:
    case VE::VSCOTsirvmL:
    case VE::VSCOTsirvml:
    case VE::VSCOTsizvm:
    case VE::VSCOTsizvmL:
    case VE::VSCOTsizvml:
    case VE::VSCOTsrrvm:
    case VE::VSCOTsrrvmL:
    case VE::VSCOTsrrvml:
    case VE::VSCOTsrzvm:
    case VE::VSCOTsrzvmL:
    case VE::VSCOTsrzvml:
    case VE::VSCUNCOTsirvm:
    case VE::VSCUNCOTsirvmL:
    case VE::VSCUNCOTsirvml:
    case VE::VSCUNCOTsizvm:
    case VE::VSCUNCOTsizvmL:
    case VE::VSCUNCOTsizvml:
    case VE::VSCUNCOTsrrvm:
    case VE::VSCUNCOTsrrvmL:
    case VE::VSCUNCOTsrrvml:
    case VE::VSCUNCOTsrzvm:
    case VE::VSCUNCOTsrzvmL:
    case VE::VSCUNCOTsrzvml:
    case VE::VSCUNCsirvm:
    case VE::VSCUNCsirvmL:
    case VE::VSCUNCsirvml:
    case VE::VSCUNCsizvm:
    case VE::VSCUNCsizvmL:
    case VE::VSCUNCsizvml:
    case VE::VSCUNCsrrvm:
    case VE::VSCUNCsrrvmL:
    case VE::VSCUNCsrrvml:
    case VE::VSCUNCsrzvm:
    case VE::VSCUNCsrzvmL:
    case VE::VSCUNCsrzvml:
    case VE::VSCUOTsirvm:
    case VE::VSCUOTsirvmL:
    case VE::VSCUOTsirvml:
    case VE::VSCUOTsizvm:
    case VE::VSCUOTsizvmL:
    case VE::VSCUOTsizvml:
    case VE::VSCUOTsrrvm:
    case VE::VSCUOTsrrvmL:
    case VE::VSCUOTsrrvml:
    case VE::VSCUOTsrzvm:
    case VE::VSCUOTsrzvmL:
    case VE::VSCUOTsrzvml:
    case VE::VSCUsirvm:
    case VE::VSCUsirvmL:
    case VE::VSCUsirvml:
    case VE::VSCUsizvm:
    case VE::VSCUsizvmL:
    case VE::VSCUsizvml:
    case VE::VSCUsrrvm:
    case VE::VSCUsrrvmL:
    case VE::VSCUsrrvml:
    case VE::VSCUsrzvm:
    case VE::VSCUsrzvmL:
    case VE::VSCUsrzvml:
    case VE::VSCsirvm:
    case VE::VSCsirvmL:
    case VE::VSCsirvml:
    case VE::VSCsizvm:
    case VE::VSCsizvmL:
    case VE::VSCsizvml:
    case VE::VSCsrrvm:
    case VE::VSCsrrvmL:
    case VE::VSCsrrvml:
    case VE::VSCsrzvm:
    case VE::VSCsrzvmL:
    case VE::VSCsrzvml: {
      switch (OpNum) {
      case 4:
        // op: m
        return 48;
      case 1:
        // op: sy
        return 40;
      case 2:
        // op: sz
        return 32;
      case 3:
        // op: vx
        return 24;
      case 0:
        // op: sw
        return 0;
      }
      break;
    }
    case VE::VSCLNCOTvirvm:
    case VE::VSCLNCOTvirvmL:
    case VE::VSCLNCOTvirvml:
    case VE::VSCLNCOTvizvm:
    case VE::VSCLNCOTvizvmL:
    case VE::VSCLNCOTvizvml:
    case VE::VSCLNCOTvrrvm:
    case VE::VSCLNCOTvrrvmL:
    case VE::VSCLNCOTvrrvml:
    case VE::VSCLNCOTvrzvm:
    case VE::VSCLNCOTvrzvmL:
    case VE::VSCLNCOTvrzvml:
    case VE::VSCLNCvirvm:
    case VE::VSCLNCvirvmL:
    case VE::VSCLNCvirvml:
    case VE::VSCLNCvizvm:
    case VE::VSCLNCvizvmL:
    case VE::VSCLNCvizvml:
    case VE::VSCLNCvrrvm:
    case VE::VSCLNCvrrvmL:
    case VE::VSCLNCvrrvml:
    case VE::VSCLNCvrzvm:
    case VE::VSCLNCvrzvmL:
    case VE::VSCLNCvrzvml:
    case VE::VSCLOTvirvm:
    case VE::VSCLOTvirvmL:
    case VE::VSCLOTvirvml:
    case VE::VSCLOTvizvm:
    case VE::VSCLOTvizvmL:
    case VE::VSCLOTvizvml:
    case VE::VSCLOTvrrvm:
    case VE::VSCLOTvrrvmL:
    case VE::VSCLOTvrrvml:
    case VE::VSCLOTvrzvm:
    case VE::VSCLOTvrzvmL:
    case VE::VSCLOTvrzvml:
    case VE::VSCLvirvm:
    case VE::VSCLvirvmL:
    case VE::VSCLvirvml:
    case VE::VSCLvizvm:
    case VE::VSCLvizvmL:
    case VE::VSCLvizvml:
    case VE::VSCLvrrvm:
    case VE::VSCLvrrvmL:
    case VE::VSCLvrrvml:
    case VE::VSCLvrzvm:
    case VE::VSCLvrzvmL:
    case VE::VSCLvrzvml:
    case VE::VSCNCOTvirvm:
    case VE::VSCNCOTvirvmL:
    case VE::VSCNCOTvirvml:
    case VE::VSCNCOTvizvm:
    case VE::VSCNCOTvizvmL:
    case VE::VSCNCOTvizvml:
    case VE::VSCNCOTvrrvm:
    case VE::VSCNCOTvrrvmL:
    case VE::VSCNCOTvrrvml:
    case VE::VSCNCOTvrzvm:
    case VE::VSCNCOTvrzvmL:
    case VE::VSCNCOTvrzvml:
    case VE::VSCNCvirvm:
    case VE::VSCNCvirvmL:
    case VE::VSCNCvirvml:
    case VE::VSCNCvizvm:
    case VE::VSCNCvizvmL:
    case VE::VSCNCvizvml:
    case VE::VSCNCvrrvm:
    case VE::VSCNCvrrvmL:
    case VE::VSCNCvrrvml:
    case VE::VSCNCvrzvm:
    case VE::VSCNCvrzvmL:
    case VE::VSCNCvrzvml:
    case VE::VSCOTvirvm:
    case VE::VSCOTvirvmL:
    case VE::VSCOTvirvml:
    case VE::VSCOTvizvm:
    case VE::VSCOTvizvmL:
    case VE::VSCOTvizvml:
    case VE::VSCOTvrrvm:
    case VE::VSCOTvrrvmL:
    case VE::VSCOTvrrvml:
    case VE::VSCOTvrzvm:
    case VE::VSCOTvrzvmL:
    case VE::VSCOTvrzvml:
    case VE::VSCUNCOTvirvm:
    case VE::VSCUNCOTvirvmL:
    case VE::VSCUNCOTvirvml:
    case VE::VSCUNCOTvizvm:
    case VE::VSCUNCOTvizvmL:
    case VE::VSCUNCOTvizvml:
    case VE::VSCUNCOTvrrvm:
    case VE::VSCUNCOTvrrvmL:
    case VE::VSCUNCOTvrrvml:
    case VE::VSCUNCOTvrzvm:
    case VE::VSCUNCOTvrzvmL:
    case VE::VSCUNCOTvrzvml:
    case VE::VSCUNCvirvm:
    case VE::VSCUNCvirvmL:
    case VE::VSCUNCvirvml:
    case VE::VSCUNCvizvm:
    case VE::VSCUNCvizvmL:
    case VE::VSCUNCvizvml:
    case VE::VSCUNCvrrvm:
    case VE::VSCUNCvrrvmL:
    case VE::VSCUNCvrrvml:
    case VE::VSCUNCvrzvm:
    case VE::VSCUNCvrzvmL:
    case VE::VSCUNCvrzvml:
    case VE::VSCUOTvirvm:
    case VE::VSCUOTvirvmL:
    case VE::VSCUOTvirvml:
    case VE::VSCUOTvizvm:
    case VE::VSCUOTvizvmL:
    case VE::VSCUOTvizvml:
    case VE::VSCUOTvrrvm:
    case VE::VSCUOTvrrvmL:
    case VE::VSCUOTvrrvml:
    case VE::VSCUOTvrzvm:
    case VE::VSCUOTvrzvmL:
    case VE::VSCUOTvrzvml:
    case VE::VSCUvirvm:
    case VE::VSCUvirvmL:
    case VE::VSCUvirvml:
    case VE::VSCUvizvm:
    case VE::VSCUvizvmL:
    case VE::VSCUvizvml:
    case VE::VSCUvrrvm:
    case VE::VSCUvrrvmL:
    case VE::VSCUvrrvml:
    case VE::VSCUvrzvm:
    case VE::VSCUvrzvmL:
    case VE::VSCUvrzvml:
    case VE::VSCvirvm:
    case VE::VSCvirvmL:
    case VE::VSCvirvml:
    case VE::VSCvizvm:
    case VE::VSCvizvmL:
    case VE::VSCvizvml:
    case VE::VSCvrrvm:
    case VE::VSCvrrvmL:
    case VE::VSCvrrvml:
    case VE::VSCvrzvm:
    case VE::VSCvrzvmL:
    case VE::VSCvrzvml: {
      switch (OpNum) {
      case 4:
        // op: m
        return 48;
      case 1:
        // op: sy
        return 40;
      case 2:
        // op: sz
        return 32;
      case 3:
        // op: vx
        return 24;
      case 0:
        // op: vy
        return 16;
      }
      break;
    }
    case VE::PVFMADLOvivm:
    case VE::PVFMADLOvivmL:
    case VE::PVFMADLOvivmL_v:
    case VE::PVFMADLOvivm_v:
    case VE::PVFMADLOvivml:
    case VE::PVFMADLOvivml_v:
    case VE::PVFMADLOvrvm:
    case VE::PVFMADLOvrvmL:
    case VE::PVFMADLOvrvmL_v:
    case VE::PVFMADLOvrvm_v:
    case VE::PVFMADLOvrvml:
    case VE::PVFMADLOvrvml_v:
    case VE::PVFMADUPvivm:
    case VE::PVFMADUPvivmL:
    case VE::PVFMADUPvivmL_v:
    case VE::PVFMADUPvivm_v:
    case VE::PVFMADUPvivml:
    case VE::PVFMADUPvivml_v:
    case VE::PVFMADUPvrvm:
    case VE::PVFMADUPvrvmL:
    case VE::PVFMADUPvrvmL_v:
    case VE::PVFMADUPvrvm_v:
    case VE::PVFMADUPvrvml:
    case VE::PVFMADUPvrvml_v:
    case VE::PVFMADvivm:
    case VE::PVFMADvivmL:
    case VE::PVFMADvivmL_v:
    case VE::PVFMADvivm_v:
    case VE::PVFMADvivml:
    case VE::PVFMADvivml_v:
    case VE::PVFMADvrvm:
    case VE::PVFMADvrvmL:
    case VE::PVFMADvrvmL_v:
    case VE::PVFMADvrvm_v:
    case VE::PVFMADvrvml:
    case VE::PVFMADvrvml_v:
    case VE::PVFMSBLOvivm:
    case VE::PVFMSBLOvivmL:
    case VE::PVFMSBLOvivmL_v:
    case VE::PVFMSBLOvivm_v:
    case VE::PVFMSBLOvivml:
    case VE::PVFMSBLOvivml_v:
    case VE::PVFMSBLOvrvm:
    case VE::PVFMSBLOvrvmL:
    case VE::PVFMSBLOvrvmL_v:
    case VE::PVFMSBLOvrvm_v:
    case VE::PVFMSBLOvrvml:
    case VE::PVFMSBLOvrvml_v:
    case VE::PVFMSBUPvivm:
    case VE::PVFMSBUPvivmL:
    case VE::PVFMSBUPvivmL_v:
    case VE::PVFMSBUPvivm_v:
    case VE::PVFMSBUPvivml:
    case VE::PVFMSBUPvivml_v:
    case VE::PVFMSBUPvrvm:
    case VE::PVFMSBUPvrvmL:
    case VE::PVFMSBUPvrvmL_v:
    case VE::PVFMSBUPvrvm_v:
    case VE::PVFMSBUPvrvml:
    case VE::PVFMSBUPvrvml_v:
    case VE::PVFMSBvivm:
    case VE::PVFMSBvivmL:
    case VE::PVFMSBvivmL_v:
    case VE::PVFMSBvivm_v:
    case VE::PVFMSBvivml:
    case VE::PVFMSBvivml_v:
    case VE::PVFMSBvrvm:
    case VE::PVFMSBvrvmL:
    case VE::PVFMSBvrvmL_v:
    case VE::PVFMSBvrvm_v:
    case VE::PVFMSBvrvml:
    case VE::PVFMSBvrvml_v:
    case VE::PVFNMADLOvivm:
    case VE::PVFNMADLOvivmL:
    case VE::PVFNMADLOvivmL_v:
    case VE::PVFNMADLOvivm_v:
    case VE::PVFNMADLOvivml:
    case VE::PVFNMADLOvivml_v:
    case VE::PVFNMADLOvrvm:
    case VE::PVFNMADLOvrvmL:
    case VE::PVFNMADLOvrvmL_v:
    case VE::PVFNMADLOvrvm_v:
    case VE::PVFNMADLOvrvml:
    case VE::PVFNMADLOvrvml_v:
    case VE::PVFNMADUPvivm:
    case VE::PVFNMADUPvivmL:
    case VE::PVFNMADUPvivmL_v:
    case VE::PVFNMADUPvivm_v:
    case VE::PVFNMADUPvivml:
    case VE::PVFNMADUPvivml_v:
    case VE::PVFNMADUPvrvm:
    case VE::PVFNMADUPvrvmL:
    case VE::PVFNMADUPvrvmL_v:
    case VE::PVFNMADUPvrvm_v:
    case VE::PVFNMADUPvrvml:
    case VE::PVFNMADUPvrvml_v:
    case VE::PVFNMADvivm:
    case VE::PVFNMADvivmL:
    case VE::PVFNMADvivmL_v:
    case VE::PVFNMADvivm_v:
    case VE::PVFNMADvivml:
    case VE::PVFNMADvivml_v:
    case VE::PVFNMADvrvm:
    case VE::PVFNMADvrvmL:
    case VE::PVFNMADvrvmL_v:
    case VE::PVFNMADvrvm_v:
    case VE::PVFNMADvrvml:
    case VE::PVFNMADvrvml_v:
    case VE::PVFNMSBLOvivm:
    case VE::PVFNMSBLOvivmL:
    case VE::PVFNMSBLOvivmL_v:
    case VE::PVFNMSBLOvivm_v:
    case VE::PVFNMSBLOvivml:
    case VE::PVFNMSBLOvivml_v:
    case VE::PVFNMSBLOvrvm:
    case VE::PVFNMSBLOvrvmL:
    case VE::PVFNMSBLOvrvmL_v:
    case VE::PVFNMSBLOvrvm_v:
    case VE::PVFNMSBLOvrvml:
    case VE::PVFNMSBLOvrvml_v:
    case VE::PVFNMSBUPvivm:
    case VE::PVFNMSBUPvivmL:
    case VE::PVFNMSBUPvivmL_v:
    case VE::PVFNMSBUPvivm_v:
    case VE::PVFNMSBUPvivml:
    case VE::PVFNMSBUPvivml_v:
    case VE::PVFNMSBUPvrvm:
    case VE::PVFNMSBUPvrvmL:
    case VE::PVFNMSBUPvrvmL_v:
    case VE::PVFNMSBUPvrvm_v:
    case VE::PVFNMSBUPvrvml:
    case VE::PVFNMSBUPvrvml_v:
    case VE::PVFNMSBvivm:
    case VE::PVFNMSBvivmL:
    case VE::PVFNMSBvivmL_v:
    case VE::PVFNMSBvivm_v:
    case VE::PVFNMSBvivml:
    case VE::PVFNMSBvivml_v:
    case VE::PVFNMSBvrvm:
    case VE::PVFNMSBvrvmL:
    case VE::PVFNMSBvrvmL_v:
    case VE::PVFNMSBvrvm_v:
    case VE::PVFNMSBvrvml:
    case VE::PVFNMSBvrvml_v:
    case VE::VFMADDvivm:
    case VE::VFMADDvivmL:
    case VE::VFMADDvivmL_v:
    case VE::VFMADDvivm_v:
    case VE::VFMADDvivml:
    case VE::VFMADDvivml_v:
    case VE::VFMADDvrvm:
    case VE::VFMADDvrvmL:
    case VE::VFMADDvrvmL_v:
    case VE::VFMADDvrvm_v:
    case VE::VFMADDvrvml:
    case VE::VFMADDvrvml_v:
    case VE::VFMADSvivm:
    case VE::VFMADSvivmL:
    case VE::VFMADSvivmL_v:
    case VE::VFMADSvivm_v:
    case VE::VFMADSvivml:
    case VE::VFMADSvivml_v:
    case VE::VFMADSvrvm:
    case VE::VFMADSvrvmL:
    case VE::VFMADSvrvmL_v:
    case VE::VFMADSvrvm_v:
    case VE::VFMADSvrvml:
    case VE::VFMADSvrvml_v:
    case VE::VFMSBDvivm:
    case VE::VFMSBDvivmL:
    case VE::VFMSBDvivmL_v:
    case VE::VFMSBDvivm_v:
    case VE::VFMSBDvivml:
    case VE::VFMSBDvivml_v:
    case VE::VFMSBDvrvm:
    case VE::VFMSBDvrvmL:
    case VE::VFMSBDvrvmL_v:
    case VE::VFMSBDvrvm_v:
    case VE::VFMSBDvrvml:
    case VE::VFMSBDvrvml_v:
    case VE::VFMSBSvivm:
    case VE::VFMSBSvivmL:
    case VE::VFMSBSvivmL_v:
    case VE::VFMSBSvivm_v:
    case VE::VFMSBSvivml:
    case VE::VFMSBSvivml_v:
    case VE::VFMSBSvrvm:
    case VE::VFMSBSvrvmL:
    case VE::VFMSBSvrvmL_v:
    case VE::VFMSBSvrvm_v:
    case VE::VFMSBSvrvml:
    case VE::VFMSBSvrvml_v:
    case VE::VFNMADDvivm:
    case VE::VFNMADDvivmL:
    case VE::VFNMADDvivmL_v:
    case VE::VFNMADDvivm_v:
    case VE::VFNMADDvivml:
    case VE::VFNMADDvivml_v:
    case VE::VFNMADDvrvm:
    case VE::VFNMADDvrvmL:
    case VE::VFNMADDvrvmL_v:
    case VE::VFNMADDvrvm_v:
    case VE::VFNMADDvrvml:
    case VE::VFNMADDvrvml_v:
    case VE::VFNMADSvivm:
    case VE::VFNMADSvivmL:
    case VE::VFNMADSvivmL_v:
    case VE::VFNMADSvivm_v:
    case VE::VFNMADSvivml:
    case VE::VFNMADSvivml_v:
    case VE::VFNMADSvrvm:
    case VE::VFNMADSvrvmL:
    case VE::VFNMADSvrvmL_v:
    case VE::VFNMADSvrvm_v:
    case VE::VFNMADSvrvml:
    case VE::VFNMADSvrvml_v:
    case VE::VFNMSBDvivm:
    case VE::VFNMSBDvivmL:
    case VE::VFNMSBDvivmL_v:
    case VE::VFNMSBDvivm_v:
    case VE::VFNMSBDvivml:
    case VE::VFNMSBDvivml_v:
    case VE::VFNMSBDvrvm:
    case VE::VFNMSBDvrvmL:
    case VE::VFNMSBDvrvmL_v:
    case VE::VFNMSBDvrvm_v:
    case VE::VFNMSBDvrvml:
    case VE::VFNMSBDvrvml_v:
    case VE::VFNMSBSvivm:
    case VE::VFNMSBSvivmL:
    case VE::VFNMSBSvivmL_v:
    case VE::VFNMSBSvivm_v:
    case VE::VFNMSBSvivml:
    case VE::VFNMSBSvivml_v:
    case VE::VFNMSBSvrvm:
    case VE::VFNMSBSvrvmL:
    case VE::VFNMSBSvrvmL_v:
    case VE::VFNMSBSvrvm_v:
    case VE::VFNMSBSvrvml:
    case VE::VFNMSBSvrvml_v: {
      switch (OpNum) {
      case 4:
        // op: m
        return 48;
      case 2:
        // op: sy
        return 40;
      case 0:
        // op: vx
        return 24;
      case 1:
        // op: vy
        return 16;
      case 3:
        // op: vw
        return 0;
      }
      break;
    }
    case VE::VGTLSXNCsirm:
    case VE::VGTLSXNCsirmL:
    case VE::VGTLSXNCsirmL_v:
    case VE::VGTLSXNCsirm_v:
    case VE::VGTLSXNCsirml:
    case VE::VGTLSXNCsirml_v:
    case VE::VGTLSXNCsizm:
    case VE::VGTLSXNCsizmL:
    case VE::VGTLSXNCsizmL_v:
    case VE::VGTLSXNCsizm_v:
    case VE::VGTLSXNCsizml:
    case VE::VGTLSXNCsizml_v:
    case VE::VGTLSXNCsrrm:
    case VE::VGTLSXNCsrrmL:
    case VE::VGTLSXNCsrrmL_v:
    case VE::VGTLSXNCsrrm_v:
    case VE::VGTLSXNCsrrml:
    case VE::VGTLSXNCsrrml_v:
    case VE::VGTLSXNCsrzm:
    case VE::VGTLSXNCsrzmL:
    case VE::VGTLSXNCsrzmL_v:
    case VE::VGTLSXNCsrzm_v:
    case VE::VGTLSXNCsrzml:
    case VE::VGTLSXNCsrzml_v:
    case VE::VGTLSXsirm:
    case VE::VGTLSXsirmL:
    case VE::VGTLSXsirmL_v:
    case VE::VGTLSXsirm_v:
    case VE::VGTLSXsirml:
    case VE::VGTLSXsirml_v:
    case VE::VGTLSXsizm:
    case VE::VGTLSXsizmL:
    case VE::VGTLSXsizmL_v:
    case VE::VGTLSXsizm_v:
    case VE::VGTLSXsizml:
    case VE::VGTLSXsizml_v:
    case VE::VGTLSXsrrm:
    case VE::VGTLSXsrrmL:
    case VE::VGTLSXsrrmL_v:
    case VE::VGTLSXsrrm_v:
    case VE::VGTLSXsrrml:
    case VE::VGTLSXsrrml_v:
    case VE::VGTLSXsrzm:
    case VE::VGTLSXsrzmL:
    case VE::VGTLSXsrzmL_v:
    case VE::VGTLSXsrzm_v:
    case VE::VGTLSXsrzml:
    case VE::VGTLSXsrzml_v:
    case VE::VGTLZXNCsirm:
    case VE::VGTLZXNCsirmL:
    case VE::VGTLZXNCsirmL_v:
    case VE::VGTLZXNCsirm_v:
    case VE::VGTLZXNCsirml:
    case VE::VGTLZXNCsirml_v:
    case VE::VGTLZXNCsizm:
    case VE::VGTLZXNCsizmL:
    case VE::VGTLZXNCsizmL_v:
    case VE::VGTLZXNCsizm_v:
    case VE::VGTLZXNCsizml:
    case VE::VGTLZXNCsizml_v:
    case VE::VGTLZXNCsrrm:
    case VE::VGTLZXNCsrrmL:
    case VE::VGTLZXNCsrrmL_v:
    case VE::VGTLZXNCsrrm_v:
    case VE::VGTLZXNCsrrml:
    case VE::VGTLZXNCsrrml_v:
    case VE::VGTLZXNCsrzm:
    case VE::VGTLZXNCsrzmL:
    case VE::VGTLZXNCsrzmL_v:
    case VE::VGTLZXNCsrzm_v:
    case VE::VGTLZXNCsrzml:
    case VE::VGTLZXNCsrzml_v:
    case VE::VGTLZXsirm:
    case VE::VGTLZXsirmL:
    case VE::VGTLZXsirmL_v:
    case VE::VGTLZXsirm_v:
    case VE::VGTLZXsirml:
    case VE::VGTLZXsirml_v:
    case VE::VGTLZXsizm:
    case VE::VGTLZXsizmL:
    case VE::VGTLZXsizmL_v:
    case VE::VGTLZXsizm_v:
    case VE::VGTLZXsizml:
    case VE::VGTLZXsizml_v:
    case VE::VGTLZXsrrm:
    case VE::VGTLZXsrrmL:
    case VE::VGTLZXsrrmL_v:
    case VE::VGTLZXsrrm_v:
    case VE::VGTLZXsrrml:
    case VE::VGTLZXsrrml_v:
    case VE::VGTLZXsrzm:
    case VE::VGTLZXsrzmL:
    case VE::VGTLZXsrzmL_v:
    case VE::VGTLZXsrzm_v:
    case VE::VGTLZXsrzml:
    case VE::VGTLZXsrzml_v:
    case VE::VGTNCsirm:
    case VE::VGTNCsirmL:
    case VE::VGTNCsirmL_v:
    case VE::VGTNCsirm_v:
    case VE::VGTNCsirml:
    case VE::VGTNCsirml_v:
    case VE::VGTNCsizm:
    case VE::VGTNCsizmL:
    case VE::VGTNCsizmL_v:
    case VE::VGTNCsizm_v:
    case VE::VGTNCsizml:
    case VE::VGTNCsizml_v:
    case VE::VGTNCsrrm:
    case VE::VGTNCsrrmL:
    case VE::VGTNCsrrmL_v:
    case VE::VGTNCsrrm_v:
    case VE::VGTNCsrrml:
    case VE::VGTNCsrrml_v:
    case VE::VGTNCsrzm:
    case VE::VGTNCsrzmL:
    case VE::VGTNCsrzmL_v:
    case VE::VGTNCsrzm_v:
    case VE::VGTNCsrzml:
    case VE::VGTNCsrzml_v:
    case VE::VGTUNCsirm:
    case VE::VGTUNCsirmL:
    case VE::VGTUNCsirmL_v:
    case VE::VGTUNCsirm_v:
    case VE::VGTUNCsirml:
    case VE::VGTUNCsirml_v:
    case VE::VGTUNCsizm:
    case VE::VGTUNCsizmL:
    case VE::VGTUNCsizmL_v:
    case VE::VGTUNCsizm_v:
    case VE::VGTUNCsizml:
    case VE::VGTUNCsizml_v:
    case VE::VGTUNCsrrm:
    case VE::VGTUNCsrrmL:
    case VE::VGTUNCsrrmL_v:
    case VE::VGTUNCsrrm_v:
    case VE::VGTUNCsrrml:
    case VE::VGTUNCsrrml_v:
    case VE::VGTUNCsrzm:
    case VE::VGTUNCsrzmL:
    case VE::VGTUNCsrzmL_v:
    case VE::VGTUNCsrzm_v:
    case VE::VGTUNCsrzml:
    case VE::VGTUNCsrzml_v:
    case VE::VGTUsirm:
    case VE::VGTUsirmL:
    case VE::VGTUsirmL_v:
    case VE::VGTUsirm_v:
    case VE::VGTUsirml:
    case VE::VGTUsirml_v:
    case VE::VGTUsizm:
    case VE::VGTUsizmL:
    case VE::VGTUsizmL_v:
    case VE::VGTUsizm_v:
    case VE::VGTUsizml:
    case VE::VGTUsizml_v:
    case VE::VGTUsrrm:
    case VE::VGTUsrrmL:
    case VE::VGTUsrrmL_v:
    case VE::VGTUsrrm_v:
    case VE::VGTUsrrml:
    case VE::VGTUsrrml_v:
    case VE::VGTUsrzm:
    case VE::VGTUsrzmL:
    case VE::VGTUsrzmL_v:
    case VE::VGTUsrzm_v:
    case VE::VGTUsrzml:
    case VE::VGTUsrzml_v:
    case VE::VGTsirm:
    case VE::VGTsirmL:
    case VE::VGTsirmL_v:
    case VE::VGTsirm_v:
    case VE::VGTsirml:
    case VE::VGTsirml_v:
    case VE::VGTsizm:
    case VE::VGTsizmL:
    case VE::VGTsizmL_v:
    case VE::VGTsizm_v:
    case VE::VGTsizml:
    case VE::VGTsizml_v:
    case VE::VGTsrrm:
    case VE::VGTsrrmL:
    case VE::VGTsrrmL_v:
    case VE::VGTsrrm_v:
    case VE::VGTsrrml:
    case VE::VGTsrrml_v:
    case VE::VGTsrzm:
    case VE::VGTsrzmL:
    case VE::VGTsrzmL_v:
    case VE::VGTsrzm_v:
    case VE::VGTsrzml:
    case VE::VGTsrzml_v: {
      switch (OpNum) {
      case 4:
        // op: m
        return 48;
      case 2:
        // op: sy
        return 40;
      case 3:
        // op: sz
        return 32;
      case 0:
        // op: vx
        return 24;
      case 1:
        // op: sw
        return 0;
      }
      break;
    }
    case VE::VGTLSXNCvirm:
    case VE::VGTLSXNCvirmL:
    case VE::VGTLSXNCvirmL_v:
    case VE::VGTLSXNCvirm_v:
    case VE::VGTLSXNCvirml:
    case VE::VGTLSXNCvirml_v:
    case VE::VGTLSXNCvizm:
    case VE::VGTLSXNCvizmL:
    case VE::VGTLSXNCvizmL_v:
    case VE::VGTLSXNCvizm_v:
    case VE::VGTLSXNCvizml:
    case VE::VGTLSXNCvizml_v:
    case VE::VGTLSXNCvrrm:
    case VE::VGTLSXNCvrrmL:
    case VE::VGTLSXNCvrrmL_v:
    case VE::VGTLSXNCvrrm_v:
    case VE::VGTLSXNCvrrml:
    case VE::VGTLSXNCvrrml_v:
    case VE::VGTLSXNCvrzm:
    case VE::VGTLSXNCvrzmL:
    case VE::VGTLSXNCvrzmL_v:
    case VE::VGTLSXNCvrzm_v:
    case VE::VGTLSXNCvrzml:
    case VE::VGTLSXNCvrzml_v:
    case VE::VGTLSXvirm:
    case VE::VGTLSXvirmL:
    case VE::VGTLSXvirmL_v:
    case VE::VGTLSXvirm_v:
    case VE::VGTLSXvirml:
    case VE::VGTLSXvirml_v:
    case VE::VGTLSXvizm:
    case VE::VGTLSXvizmL:
    case VE::VGTLSXvizmL_v:
    case VE::VGTLSXvizm_v:
    case VE::VGTLSXvizml:
    case VE::VGTLSXvizml_v:
    case VE::VGTLSXvrrm:
    case VE::VGTLSXvrrmL:
    case VE::VGTLSXvrrmL_v:
    case VE::VGTLSXvrrm_v:
    case VE::VGTLSXvrrml:
    case VE::VGTLSXvrrml_v:
    case VE::VGTLSXvrzm:
    case VE::VGTLSXvrzmL:
    case VE::VGTLSXvrzmL_v:
    case VE::VGTLSXvrzm_v:
    case VE::VGTLSXvrzml:
    case VE::VGTLSXvrzml_v:
    case VE::VGTLZXNCvirm:
    case VE::VGTLZXNCvirmL:
    case VE::VGTLZXNCvirmL_v:
    case VE::VGTLZXNCvirm_v:
    case VE::VGTLZXNCvirml:
    case VE::VGTLZXNCvirml_v:
    case VE::VGTLZXNCvizm:
    case VE::VGTLZXNCvizmL:
    case VE::VGTLZXNCvizmL_v:
    case VE::VGTLZXNCvizm_v:
    case VE::VGTLZXNCvizml:
    case VE::VGTLZXNCvizml_v:
    case VE::VGTLZXNCvrrm:
    case VE::VGTLZXNCvrrmL:
    case VE::VGTLZXNCvrrmL_v:
    case VE::VGTLZXNCvrrm_v:
    case VE::VGTLZXNCvrrml:
    case VE::VGTLZXNCvrrml_v:
    case VE::VGTLZXNCvrzm:
    case VE::VGTLZXNCvrzmL:
    case VE::VGTLZXNCvrzmL_v:
    case VE::VGTLZXNCvrzm_v:
    case VE::VGTLZXNCvrzml:
    case VE::VGTLZXNCvrzml_v:
    case VE::VGTLZXvirm:
    case VE::VGTLZXvirmL:
    case VE::VGTLZXvirmL_v:
    case VE::VGTLZXvirm_v:
    case VE::VGTLZXvirml:
    case VE::VGTLZXvirml_v:
    case VE::VGTLZXvizm:
    case VE::VGTLZXvizmL:
    case VE::VGTLZXvizmL_v:
    case VE::VGTLZXvizm_v:
    case VE::VGTLZXvizml:
    case VE::VGTLZXvizml_v:
    case VE::VGTLZXvrrm:
    case VE::VGTLZXvrrmL:
    case VE::VGTLZXvrrmL_v:
    case VE::VGTLZXvrrm_v:
    case VE::VGTLZXvrrml:
    case VE::VGTLZXvrrml_v:
    case VE::VGTLZXvrzm:
    case VE::VGTLZXvrzmL:
    case VE::VGTLZXvrzmL_v:
    case VE::VGTLZXvrzm_v:
    case VE::VGTLZXvrzml:
    case VE::VGTLZXvrzml_v:
    case VE::VGTNCvirm:
    case VE::VGTNCvirmL:
    case VE::VGTNCvirmL_v:
    case VE::VGTNCvirm_v:
    case VE::VGTNCvirml:
    case VE::VGTNCvirml_v:
    case VE::VGTNCvizm:
    case VE::VGTNCvizmL:
    case VE::VGTNCvizmL_v:
    case VE::VGTNCvizm_v:
    case VE::VGTNCvizml:
    case VE::VGTNCvizml_v:
    case VE::VGTNCvrrm:
    case VE::VGTNCvrrmL:
    case VE::VGTNCvrrmL_v:
    case VE::VGTNCvrrm_v:
    case VE::VGTNCvrrml:
    case VE::VGTNCvrrml_v:
    case VE::VGTNCvrzm:
    case VE::VGTNCvrzmL:
    case VE::VGTNCvrzmL_v:
    case VE::VGTNCvrzm_v:
    case VE::VGTNCvrzml:
    case VE::VGTNCvrzml_v:
    case VE::VGTUNCvirm:
    case VE::VGTUNCvirmL:
    case VE::VGTUNCvirmL_v:
    case VE::VGTUNCvirm_v:
    case VE::VGTUNCvirml:
    case VE::VGTUNCvirml_v:
    case VE::VGTUNCvizm:
    case VE::VGTUNCvizmL:
    case VE::VGTUNCvizmL_v:
    case VE::VGTUNCvizm_v:
    case VE::VGTUNCvizml:
    case VE::VGTUNCvizml_v:
    case VE::VGTUNCvrrm:
    case VE::VGTUNCvrrmL:
    case VE::VGTUNCvrrmL_v:
    case VE::VGTUNCvrrm_v:
    case VE::VGTUNCvrrml:
    case VE::VGTUNCvrrml_v:
    case VE::VGTUNCvrzm:
    case VE::VGTUNCvrzmL:
    case VE::VGTUNCvrzmL_v:
    case VE::VGTUNCvrzm_v:
    case VE::VGTUNCvrzml:
    case VE::VGTUNCvrzml_v:
    case VE::VGTUvirm:
    case VE::VGTUvirmL:
    case VE::VGTUvirmL_v:
    case VE::VGTUvirm_v:
    case VE::VGTUvirml:
    case VE::VGTUvirml_v:
    case VE::VGTUvizm:
    case VE::VGTUvizmL:
    case VE::VGTUvizmL_v:
    case VE::VGTUvizm_v:
    case VE::VGTUvizml:
    case VE::VGTUvizml_v:
    case VE::VGTUvrrm:
    case VE::VGTUvrrmL:
    case VE::VGTUvrrmL_v:
    case VE::VGTUvrrm_v:
    case VE::VGTUvrrml:
    case VE::VGTUvrrml_v:
    case VE::VGTUvrzm:
    case VE::VGTUvrzmL:
    case VE::VGTUvrzmL_v:
    case VE::VGTUvrzm_v:
    case VE::VGTUvrzml:
    case VE::VGTUvrzml_v:
    case VE::VGTvirm:
    case VE::VGTvirmL:
    case VE::VGTvirmL_v:
    case VE::VGTvirm_v:
    case VE::VGTvirml:
    case VE::VGTvirml_v:
    case VE::VGTvizm:
    case VE::VGTvizmL:
    case VE::VGTvizmL_v:
    case VE::VGTvizm_v:
    case VE::VGTvizml:
    case VE::VGTvizml_v:
    case VE::VGTvrrm:
    case VE::VGTvrrmL:
    case VE::VGTvrrmL_v:
    case VE::VGTvrrm_v:
    case VE::VGTvrrml:
    case VE::VGTvrrml_v:
    case VE::VGTvrzm:
    case VE::VGTvrzmL:
    case VE::VGTvrzmL_v:
    case VE::VGTvrzm_v:
    case VE::VGTvrzml:
    case VE::VGTvrzml_v: {
      switch (OpNum) {
      case 4:
        // op: m
        return 48;
      case 2:
        // op: sy
        return 40;
      case 3:
        // op: sz
        return 32;
      case 0:
        // op: vx
        return 24;
      case 1:
        // op: vy
        return 16;
      }
      break;
    }
    case VE::VSFAvimm:
    case VE::VSFAvimmL:
    case VE::VSFAvimmL_v:
    case VE::VSFAvimm_v:
    case VE::VSFAvimml:
    case VE::VSFAvimml_v:
    case VE::VSFAvirm:
    case VE::VSFAvirmL:
    case VE::VSFAvirmL_v:
    case VE::VSFAvirm_v:
    case VE::VSFAvirml:
    case VE::VSFAvirml_v:
    case VE::VSFAvrmm:
    case VE::VSFAvrmmL:
    case VE::VSFAvrmmL_v:
    case VE::VSFAvrmm_v:
    case VE::VSFAvrmml:
    case VE::VSFAvrmml_v:
    case VE::VSFAvrrm:
    case VE::VSFAvrrmL:
    case VE::VSFAvrrmL_v:
    case VE::VSFAvrrm_v:
    case VE::VSFAvrrml:
    case VE::VSFAvrrml_v: {
      switch (OpNum) {
      case 4:
        // op: m
        return 48;
      case 2:
        // op: sy
        return 40;
      case 3:
        // op: sz
        return 32;
      case 0:
        // op: vx
        return 24;
      case 1:
        // op: vz
        return 8;
      }
      break;
    }
    case VE::VSLDvvim:
    case VE::VSLDvvimL:
    case VE::VSLDvvimL_v:
    case VE::VSLDvvim_v:
    case VE::VSLDvviml:
    case VE::VSLDvviml_v:
    case VE::VSLDvvrm:
    case VE::VSLDvvrmL:
    case VE::VSLDvvrmL_v:
    case VE::VSLDvvrm_v:
    case VE::VSLDvvrml:
    case VE::VSLDvvrml_v:
    case VE::VSRDvvim:
    case VE::VSRDvvimL:
    case VE::VSRDvvimL_v:
    case VE::VSRDvvim_v:
    case VE::VSRDvviml:
    case VE::VSRDvviml_v:
    case VE::VSRDvvrm:
    case VE::VSRDvvrmL:
    case VE::VSRDvvrmL_v:
    case VE::VSRDvvrm_v:
    case VE::VSRDvvrml:
    case VE::VSRDvvrml_v: {
      switch (OpNum) {
      case 4:
        // op: m
        return 48;
      case 3:
        // op: sy
        return 40;
      case 0:
        // op: vx
        return 24;
      case 1:
        // op: vy
        return 16;
      case 2:
        // op: vz
        return 8;
      }
      break;
    }
  }
  std::string msg;
  raw_string_ostream Msg(msg);
  Msg << "Not supported instr[opcode]: " << MI << "[" << OpNum << "]";
  report_fatal_error(Msg.str().c_str());
}

#endif // GET_OPERAND_BIT_OFFSET