/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |* *| |* Target Instruction Enum Values and Descriptors *| |* *| |* Automatically generated file, do not edit! *| |* *| \*===----------------------------------------------------------------------===*/ #ifdef GET_INSTRINFO_ENUM #undef GET_INSTRINFO_ENUM namespace llvm { namespace WebAssembly { enum { … }; } // end namespace WebAssembly } // end namespace llvm #endif // GET_INSTRINFO_ENUM #ifdef GET_INSTRINFO_SCHED_ENUM #undef GET_INSTRINFO_SCHED_ENUM namespace llvm { namespace WebAssembly { namespace Sched { enum { NoInstrModel = 0, SCHED_LIST_END = 1 }; } // end namespace Sched } // end namespace WebAssembly } // end namespace llvm #endif // GET_INSTRINFO_SCHED_ENUM #if defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR) namespace llvm { struct WebAssemblyInstrTable { MCInstrDesc Insts[1898]; static_assert(alignof(MCInstrDesc) >= alignof(MCOperandInfo), "Unwanted padding between Insts and OperandInfo"); MCOperandInfo OperandInfo[808]; static_assert(alignof(MCOperandInfo) >= alignof(MCPhysReg), "Unwanted padding between OperandInfo and ImplicitOps"); MCPhysReg ImplicitOps[10]; }; } // end namespace llvm #endif // defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR) #ifdef GET_INSTRINFO_MC_DESC #undef GET_INSTRINFO_MC_DESC namespace llvm { static_assert(sizeof(MCOperandInfo) % sizeof(MCPhysReg) == 0); static constexpr unsigned WebAssemblyImpOpBase = sizeof WebAssemblyInstrTable::OperandInfo / (sizeof(MCPhysReg)); extern const WebAssemblyInstrTable WebAssemblyDescs = { { { 1897, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1897 = uint_to_fp_F32x4_S { 1896, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1896 = uint_to_fp_F32x4 { 1895, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1895 = uint_to_fp_F16x8_S { 1894, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1894 = uint_to_fp_F16x8 { 1893, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1893 = trunc_sat_zero_u_I32x4_S { 1892, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1892 = trunc_sat_zero_u_I32x4 { 1891, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1891 = trunc_sat_zero_s_I32x4_S { 1890, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1890 = trunc_sat_zero_s_I32x4 { 1889, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1889 = sint_to_fp_F32x4_S { 1888, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1888 = sint_to_fp_F32x4 { 1887, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1887 = sint_to_fp_F16x8_S { 1886, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1886 = sint_to_fp_F16x8 { 1885, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1885 = promote_low_F64x2_S { 1884, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1884 = promote_low_F64x2 { 1883, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1883 = int_wasm_relaxed_trunc_unsigned_zero_I32x4_S { 1882, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1882 = int_wasm_relaxed_trunc_unsigned_zero_I32x4 { 1881, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1881 = int_wasm_relaxed_trunc_unsigned_I32x4_S { 1880, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1880 = int_wasm_relaxed_trunc_unsigned_I32x4 { 1879, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1879 = int_wasm_relaxed_trunc_signed_zero_I32x4_S { 1878, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1878 = int_wasm_relaxed_trunc_signed_zero_I32x4 { 1877, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1877 = int_wasm_relaxed_trunc_signed_I32x4_S { 1876, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1876 = int_wasm_relaxed_trunc_signed_I32x4 { 1875, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1875 = int_wasm_extadd_pairwise_unsigned_I32x4_S { 1874, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1874 = int_wasm_extadd_pairwise_unsigned_I32x4 { 1873, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1873 = int_wasm_extadd_pairwise_unsigned_I16x8_S { 1872, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1872 = int_wasm_extadd_pairwise_unsigned_I16x8 { 1871, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1871 = int_wasm_extadd_pairwise_signed_I32x4_S { 1870, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1870 = int_wasm_extadd_pairwise_signed_I32x4 { 1869, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1869 = int_wasm_extadd_pairwise_signed_I16x8_S { 1868, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1868 = int_wasm_extadd_pairwise_signed_I16x8 { 1867, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1867 = fp_to_uint_I32x4_S { 1866, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1866 = fp_to_uint_I32x4 { 1865, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1865 = fp_to_uint_I16x8_S { 1864, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1864 = fp_to_uint_I16x8 { 1863, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1863 = fp_to_sint_I32x4_S { 1862, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1862 = fp_to_sint_I32x4 { 1861, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1861 = fp_to_sint_I16x8_S { 1860, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1860 = fp_to_sint_I16x8 { 1859, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1859 = extend_low_u_I64x2_S { 1858, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1858 = extend_low_u_I64x2 { 1857, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1857 = extend_low_u_I32x4_S { 1856, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1856 = extend_low_u_I32x4 { 1855, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1855 = extend_low_u_I16x8_S { 1854, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1854 = extend_low_u_I16x8 { 1853, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1853 = extend_low_s_I64x2_S { 1852, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1852 = extend_low_s_I64x2 { 1851, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1851 = extend_low_s_I32x4_S { 1850, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1850 = extend_low_s_I32x4 { 1849, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1849 = extend_low_s_I16x8_S { 1848, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1848 = extend_low_s_I16x8 { 1847, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1847 = extend_high_u_I64x2_S { 1846, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1846 = extend_high_u_I64x2 { 1845, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1845 = extend_high_u_I32x4_S { 1844, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1844 = extend_high_u_I32x4 { 1843, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1843 = extend_high_u_I16x8_S { 1842, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1842 = extend_high_u_I16x8 { 1841, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1841 = extend_high_s_I64x2_S { 1840, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1840 = extend_high_s_I64x2 { 1839, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1839 = extend_high_s_I32x4_S { 1838, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1838 = extend_high_s_I32x4 { 1837, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1837 = extend_high_s_I16x8_S { 1836, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1836 = extend_high_s_I16x8 { 1835, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1835 = demote_zero_F32x4_S { 1834, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1834 = demote_zero_F32x4 { 1833, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1833 = convert_low_u_F64x2_S { 1832, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1832 = convert_low_u_F64x2 { 1831, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1831 = convert_low_s_F64x2_S { 1830, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1830 = convert_low_s_F64x2 { 1829, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 788, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1829 = anonymous_8884MEMORY_INIT_A64_S { 1828, 5, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 803, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1828 = anonymous_8884MEMORY_INIT_A64 { 1827, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 300, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1827 = anonymous_8884MEMORY_FILL_A64_S { 1826, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 799, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1826 = anonymous_8884MEMORY_FILL_A64 { 1825, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 788, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1825 = anonymous_8884MEMORY_COPY_A64_S { 1824, 5, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 794, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1824 = anonymous_8884MEMORY_COPY_A64 { 1823, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 300, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1823 = anonymous_8884DATA_DROP_S { 1822, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 300, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1822 = anonymous_8884DATA_DROP { 1821, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 788, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1821 = anonymous_8883MEMORY_INIT_A32_S { 1820, 5, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 783, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1820 = anonymous_8883MEMORY_INIT_A32 { 1819, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 300, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1819 = anonymous_8883MEMORY_FILL_A32_S { 1818, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 790, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1818 = anonymous_8883MEMORY_FILL_A32 { 1817, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 788, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1817 = anonymous_8883MEMORY_COPY_A32_S { 1816, 5, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 783, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1816 = anonymous_8883MEMORY_COPY_A32 { 1815, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 300, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1815 = anonymous_8883DATA_DROP_S { 1814, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 300, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1814 = anonymous_8883DATA_DROP { 1813, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1813 = anonymous_8167MEMORY_SIZE_A64_S { 1812, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 190, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1812 = anonymous_8167MEMORY_SIZE_A64 { 1811, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1811 = anonymous_8167MEMORY_GROW_A64_S { 1810, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 780, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1810 = anonymous_8167MEMORY_GROW_A64 { 1809, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1809 = anonymous_8166MEMORY_SIZE_A32_S { 1808, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 188, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1808 = anonymous_8166MEMORY_SIZE_A32 { 1807, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1807 = anonymous_8166MEMORY_GROW_A32_S { 1806, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 777, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1806 = anonymous_8166MEMORY_GROW_A32 { 1805, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1805 = XOR_S { 1804, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1804 = XOR_I64_S { 1803, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 173, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1803 = XOR_I64 { 1802, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1802 = XOR_I32_S { 1801, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 170, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1801 = XOR_I32 { 1800, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1800 = XOR { 1799, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Trap)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1799 = UNREACHABLE_S { 1798, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Trap)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1798 = UNREACHABLE { 1797, 1, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 8, 278, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1797 = TRY_S { 1796, 1, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 8, 278, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1796 = TRY { 1795, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1795 = TRUNC_F64x2_S { 1794, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1794 = TRUNC_F64x2 { 1793, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1793 = TRUNC_F64_S { 1792, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 159, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1792 = TRUNC_F64 { 1791, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1791 = TRUNC_F32x4_S { 1790, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1790 = TRUNC_F32x4 { 1789, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1789 = TRUNC_F32_S { 1788, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 157, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1788 = TRUNC_F32 { 1787, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1787 = TRUNC_F16x8_S { 1786, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1786 = TRUNC_F16x8 { 1785, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 287, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1785 = THROW_S { 1784, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 287, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1784 = THROW { 1783, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1783 = TEE_V128_S { 1782, 3, 2, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1782 = TEE_V128 { 1781, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1781 = TEE_I64_S { 1780, 3, 2, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 173, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1780 = TEE_I64 { 1779, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1779 = TEE_I32_S { 1778, 3, 2, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 170, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1778 = TEE_I32 { 1777, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1777 = TEE_FUNCREF_S { 1776, 3, 2, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 774, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1776 = TEE_FUNCREF { 1775, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1775 = TEE_F64_S { 1774, 3, 2, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 167, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1774 = TEE_F64 { 1773, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1773 = TEE_F32_S { 1772, 3, 2, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 164, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1772 = TEE_F32 { 1771, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1771 = TEE_EXTERNREF_S { 1770, 3, 2, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 771, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1770 = TEE_EXTERNREF { 1769, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1769 = TEE_EXNREF_S { 1768, 3, 2, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 768, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1768 = TEE_EXNREF { 1767, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 727, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1767 = TABLE_SIZE_S { 1766, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 766, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1766 = TABLE_SIZE { 1765, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 727, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1765 = TABLE_SET_FUNCREF_S { 1764, 3, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 763, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1764 = TABLE_SET_FUNCREF { 1763, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 727, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1763 = TABLE_SET_EXTERNREF_S { 1762, 3, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 760, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1762 = TABLE_SET_EXTERNREF { 1761, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 727, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1761 = TABLE_SET_EXNREF_S { 1760, 3, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 757, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1760 = TABLE_SET_EXNREF { 1759, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 727, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1759 = TABLE_GROW_FUNCREF_S { 1758, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 753, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1758 = TABLE_GROW_FUNCREF { 1757, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 727, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1757 = TABLE_GROW_EXTERNREF_S { 1756, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 749, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1756 = TABLE_GROW_EXTERNREF { 1755, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 727, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1755 = TABLE_GROW_EXNREF_S { 1754, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 745, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1754 = TABLE_GROW_EXNREF { 1753, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 727, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1753 = TABLE_GET_FUNCREF_S { 1752, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 742, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1752 = TABLE_GET_FUNCREF { 1751, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 727, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1751 = TABLE_GET_EXTERNREF_S { 1750, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 739, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1750 = TABLE_GET_EXTERNREF { 1749, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 727, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1749 = TABLE_GET_EXNREF_S { 1748, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 736, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1748 = TABLE_GET_EXNREF { 1747, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 727, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1747 = TABLE_FILL_FUNCREF_S { 1746, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 732, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1746 = TABLE_FILL_FUNCREF { 1745, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 727, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1745 = TABLE_FILL_EXTERNREF_S { 1744, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 728, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1744 = TABLE_FILL_EXTERNREF { 1743, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 727, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1743 = TABLE_FILL_EXNREF_S { 1742, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 723, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1742 = TABLE_FILL_EXNREF { 1741, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 721, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1741 = TABLE_COPY_S { 1740, 5, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 716, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1740 = TABLE_COPY { 1739, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1739 = SWIZZLE_S { 1738, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1738 = SWIZZLE { 1737, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1737 = SUB_SAT_U_I8x16_S { 1736, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1736 = SUB_SAT_U_I8x16 { 1735, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1735 = SUB_SAT_U_I16x8_S { 1734, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1734 = SUB_SAT_U_I16x8 { 1733, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1733 = SUB_SAT_S_I8x16_S { 1732, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1732 = SUB_SAT_S_I8x16 { 1731, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1731 = SUB_SAT_S_I16x8_S { 1730, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1730 = SUB_SAT_S_I16x8 { 1729, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1729 = SUB_I8x16_S { 1728, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1728 = SUB_I8x16 { 1727, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1727 = SUB_I64x2_S { 1726, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1726 = SUB_I64x2 { 1725, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1725 = SUB_I64_S { 1724, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 173, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1724 = SUB_I64 { 1723, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1723 = SUB_I32x4_S { 1722, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1722 = SUB_I32x4 { 1721, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1721 = SUB_I32_S { 1720, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 170, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1720 = SUB_I32 { 1719, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1719 = SUB_I16x8_S { 1718, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1718 = SUB_I16x8 { 1717, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1717 = SUB_F64x2_S { 1716, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1716 = SUB_F64x2 { 1715, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1715 = SUB_F64_S { 1714, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 167, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1714 = SUB_F64 { 1713, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1713 = SUB_F32x4_S { 1712, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1712 = SUB_F32x4 { 1711, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1711 = SUB_F32_S { 1710, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 164, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1710 = SUB_F32 { 1709, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1709 = SUB_F16x8_S { 1708, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1708 = SUB_F16x8 { 1707, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1707 = STORE_V128_A64_S { 1706, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 712, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1706 = STORE_V128_A64 { 1705, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1705 = STORE_V128_A32_S { 1704, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 708, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1704 = STORE_V128_A32 { 1703, 3, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 514, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1703 = STORE_LANE_I8x16_A64_S { 1702, 5, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 703, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1702 = STORE_LANE_I8x16_A64 { 1701, 3, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 505, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1701 = STORE_LANE_I8x16_A32_S { 1700, 5, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 698, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1700 = STORE_LANE_I8x16_A32 { 1699, 3, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 514, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1699 = STORE_LANE_I64x2_A64_S { 1698, 5, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 703, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1698 = STORE_LANE_I64x2_A64 { 1697, 3, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 505, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1697 = STORE_LANE_I64x2_A32_S { 1696, 5, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 698, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1696 = STORE_LANE_I64x2_A32 { 1695, 3, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 514, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1695 = STORE_LANE_I32x4_A64_S { 1694, 5, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 703, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1694 = STORE_LANE_I32x4_A64 { 1693, 3, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 505, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1693 = STORE_LANE_I32x4_A32_S { 1692, 5, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 698, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1692 = STORE_LANE_I32x4_A32 { 1691, 3, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 514, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1691 = STORE_LANE_I16x8_A64_S { 1690, 5, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 703, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1690 = STORE_LANE_I16x8_A64 { 1689, 3, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 505, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1689 = STORE_LANE_I16x8_A32_S { 1688, 5, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 698, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1688 = STORE_LANE_I16x8_A32 { 1687, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1687 = STORE_I64_A64_S { 1686, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 270, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1686 = STORE_I64_A64 { 1685, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1685 = STORE_I64_A32_S { 1684, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 266, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1684 = STORE_I64_A32 { 1683, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1683 = STORE_I32_A64_S { 1682, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 262, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1682 = STORE_I32_A64 { 1681, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1681 = STORE_I32_A32_S { 1680, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 258, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1680 = STORE_I32_A32 { 1679, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1679 = STORE_F64_A64_S { 1678, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 694, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1678 = STORE_F64_A64 { 1677, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1677 = STORE_F64_A32_S { 1676, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 690, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1676 = STORE_F64_A32 { 1675, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1675 = STORE_F32_A64_S { 1674, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 686, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1674 = STORE_F32_A64 { 1673, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1673 = STORE_F32_A32_S { 1672, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 682, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1672 = STORE_F32_A32 { 1671, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1671 = STORE_F16_F32_A64_S { 1670, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 686, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1670 = STORE_F16_F32_A64 { 1669, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1669 = STORE_F16_F32_A32_S { 1668, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 682, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1668 = STORE_F16_F32_A32 { 1667, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1667 = STORE8_I64_A64_S { 1666, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 270, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1666 = STORE8_I64_A64 { 1665, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1665 = STORE8_I64_A32_S { 1664, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 266, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1664 = STORE8_I64_A32 { 1663, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1663 = STORE8_I32_A64_S { 1662, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 262, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1662 = STORE8_I32_A64 { 1661, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1661 = STORE8_I32_A32_S { 1660, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 258, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1660 = STORE8_I32_A32 { 1659, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1659 = STORE32_I64_A64_S { 1658, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 270, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1658 = STORE32_I64_A64 { 1657, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1657 = STORE32_I64_A32_S { 1656, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 266, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1656 = STORE32_I64_A32 { 1655, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1655 = STORE16_I64_A64_S { 1654, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 270, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1654 = STORE16_I64_A64 { 1653, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1653 = STORE16_I64_A32_S { 1652, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 266, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1652 = STORE16_I64_A32 { 1651, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1651 = STORE16_I32_A64_S { 1650, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 262, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1650 = STORE16_I32_A64 { 1649, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1649 = STORE16_I32_A32_S { 1648, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 258, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1648 = STORE16_I32_A32 { 1647, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1647 = SQRT_F64x2_S { 1646, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1646 = SQRT_F64x2 { 1645, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1645 = SQRT_F64_S { 1644, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 159, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1644 = SQRT_F64 { 1643, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1643 = SQRT_F32x4_S { 1642, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1642 = SQRT_F32x4 { 1641, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1641 = SQRT_F32_S { 1640, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 157, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1640 = SQRT_F32 { 1639, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1639 = SQRT_F16x8_S { 1638, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1638 = SQRT_F16x8 { 1637, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1637 = SPLAT_I8x16_S { 1636, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 678, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1636 = SPLAT_I8x16 { 1635, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1635 = SPLAT_I64x2_S { 1634, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 680, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1634 = SPLAT_I64x2 { 1633, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1633 = SPLAT_I32x4_S { 1632, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 678, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1632 = SPLAT_I32x4 { 1631, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1631 = SPLAT_I16x8_S { 1630, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 678, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1630 = SPLAT_I16x8 { 1629, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1629 = SPLAT_F64x2_S { 1628, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 676, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1628 = SPLAT_F64x2 { 1627, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1627 = SPLAT_F32x4_S { 1626, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 674, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1626 = SPLAT_F32x4 { 1625, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1625 = SPLAT_F16x8_S { 1624, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 674, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1624 = SPLAT_F16x8 { 1623, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1623 = SIMD_RELAXED_FMIN_F64x2_S { 1622, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1622 = SIMD_RELAXED_FMIN_F64x2 { 1621, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1621 = SIMD_RELAXED_FMIN_F32x4_S { 1620, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1620 = SIMD_RELAXED_FMIN_F32x4 { 1619, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1619 = SIMD_RELAXED_FMAX_F64x2_S { 1618, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1618 = SIMD_RELAXED_FMAX_F64x2 { 1617, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1617 = SIMD_RELAXED_FMAX_F32x4_S { 1616, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1616 = SIMD_RELAXED_FMAX_F32x4 { 1615, 16, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 366, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1615 = SHUFFLE_S { 1614, 19, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 655, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1614 = SHUFFLE { 1613, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1613 = SHR_U_I8x16_S { 1612, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 652, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1612 = SHR_U_I8x16 { 1611, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1611 = SHR_U_I64x2_S { 1610, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 652, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1610 = SHR_U_I64x2 { 1609, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1609 = SHR_U_I64_S { 1608, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 173, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1608 = SHR_U_I64 { 1607, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1607 = SHR_U_I32x4_S { 1606, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 652, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1606 = SHR_U_I32x4 { 1605, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1605 = SHR_U_I32_S { 1604, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 170, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1604 = SHR_U_I32 { 1603, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1603 = SHR_U_I16x8_S { 1602, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 652, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1602 = SHR_U_I16x8 { 1601, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1601 = SHR_S_I8x16_S { 1600, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 652, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1600 = SHR_S_I8x16 { 1599, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1599 = SHR_S_I64x2_S { 1598, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 652, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1598 = SHR_S_I64x2 { 1597, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1597 = SHR_S_I64_S { 1596, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 173, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1596 = SHR_S_I64 { 1595, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1595 = SHR_S_I32x4_S { 1594, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 652, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1594 = SHR_S_I32x4 { 1593, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1593 = SHR_S_I32_S { 1592, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 170, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1592 = SHR_S_I32 { 1591, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1591 = SHR_S_I16x8_S { 1590, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 652, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1590 = SHR_S_I16x8 { 1589, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1589 = SHL_I8x16_S { 1588, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 652, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1588 = SHL_I8x16 { 1587, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1587 = SHL_I64x2_S { 1586, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 652, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1586 = SHL_I64x2 { 1585, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1585 = SHL_I64_S { 1584, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 173, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1584 = SHL_I64 { 1583, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1583 = SHL_I32x4_S { 1582, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 652, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1582 = SHL_I32x4 { 1581, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1581 = SHL_I32_S { 1580, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 170, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1580 = SHL_I32 { 1579, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1579 = SHL_I16x8_S { 1578, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 652, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1578 = SHL_I16x8 { 1577, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1577 = SELECT_V128_S { 1576, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 648, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1576 = SELECT_V128 { 1575, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1575 = SELECT_I64_S { 1574, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 644, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1574 = SELECT_I64 { 1573, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1573 = SELECT_I32_S { 1572, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 640, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1572 = SELECT_I32 { 1571, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1571 = SELECT_FUNCREF_S { 1570, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 636, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1570 = SELECT_FUNCREF { 1569, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1569 = SELECT_F64_S { 1568, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 632, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1568 = SELECT_F64 { 1567, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1567 = SELECT_F32_S { 1566, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 628, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1566 = SELECT_F32 { 1565, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1565 = SELECT_EXTERNREF_S { 1564, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 624, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1564 = SELECT_EXTERNREF { 1563, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1563 = SELECT_EXNREF_S { 1562, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 620, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1562 = SELECT_EXNREF { 1561, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1561 = ROTR_I64_S { 1560, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 173, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1560 = ROTR_I64 { 1559, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1559 = ROTR_I32_S { 1558, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 170, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1558 = ROTR_I32 { 1557, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1557 = ROTL_I64_S { 1556, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 173, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1556 = ROTL_I64 { 1555, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1555 = ROTL_I32_S { 1554, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 170, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1554 = ROTL_I32 { 1553, 1, 0, 0, 0, 2, 1, WebAssemblyImpOpBase + 0, 152, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1553 = RET_CALL_S { 1552, 2, 0, 0, 0, 2, 1, WebAssemblyImpOpBase + 0, 285, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1552 = RET_CALL_INDIRECT_S { 1551, 2, 0, 0, 0, 2, 1, WebAssemblyImpOpBase + 0, 285, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1551 = RET_CALL_INDIRECT { 1550, 1, 0, 0, 0, 2, 1, WebAssemblyImpOpBase + 0, 152, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1550 = RET_CALL { 1549, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1549 = RETURN_S { 1548, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1548 = RETURN { 1547, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1547 = RETHROW_S { 1546, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1546 = RETHROW { 1545, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 408, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1545 = REPLACE_LANE_I8x16_S { 1544, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 612, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1544 = REPLACE_LANE_I8x16 { 1543, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 408, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1543 = REPLACE_LANE_I64x2_S { 1542, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 616, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1542 = REPLACE_LANE_I64x2 { 1541, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 408, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1541 = REPLACE_LANE_I32x4_S { 1540, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 612, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1540 = REPLACE_LANE_I32x4 { 1539, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 408, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1539 = REPLACE_LANE_I16x8_S { 1538, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 612, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1538 = REPLACE_LANE_I16x8 { 1537, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 408, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1537 = REPLACE_LANE_F64x2_S { 1536, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 608, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1536 = REPLACE_LANE_F64x2 { 1535, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 408, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1535 = REPLACE_LANE_F32x4_S { 1534, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 604, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1534 = REPLACE_LANE_F32x4 { 1533, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 408, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1533 = REPLACE_LANE_F16x8_S { 1532, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 604, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1532 = REPLACE_LANE_F16x8 { 1531, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1531 = REM_U_I64_S { 1530, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 173, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1530 = REM_U_I64 { 1529, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1529 = REM_U_I32_S { 1528, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 170, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1528 = REM_U_I32 { 1527, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1527 = REM_S_I64_S { 1526, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 173, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1526 = REM_S_I64 { 1525, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1525 = REM_S_I32_S { 1524, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 170, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1524 = REM_S_I32 { 1523, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1523 = RELAXED_SWIZZLE_S { 1522, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1522 = RELAXED_SWIZZLE { 1521, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1521 = RELAXED_Q15MULR_S_I16x8_S { 1520, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1520 = RELAXED_Q15MULR_S_I16x8 { 1519, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1519 = RELAXED_DOT_S { 1518, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1518 = RELAXED_DOT_BFLOAT_S { 1517, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 274, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1517 = RELAXED_DOT_BFLOAT { 1516, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1516 = RELAXED_DOT_ADD_S { 1515, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 274, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1515 = RELAXED_DOT_ADD { 1514, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1514 = RELAXED_DOT { 1513, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1513 = REF_NULL_FUNCREF_S { 1512, 1, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 392, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1512 = REF_NULL_FUNCREF { 1511, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1511 = REF_NULL_EXTERNREF_S { 1510, 1, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 389, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1510 = REF_NULL_EXTERNREF { 1509, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1509 = REF_NULL_EXNREF_S { 1508, 1, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 388, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1508 = REF_NULL_EXNREF { 1507, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1507 = REF_IS_NULL_FUNCREF_S { 1506, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 602, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1506 = REF_IS_NULL_FUNCREF { 1505, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1505 = REF_IS_NULL_EXTERNREF_S { 1504, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 600, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1504 = REF_IS_NULL_EXTERNREF { 1503, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1503 = REF_IS_NULL_EXNREF_S { 1502, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 598, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1502 = REF_IS_NULL_EXNREF { 1501, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1501 = Q15MULR_SAT_S_I16x8_S { 1500, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1500 = Q15MULR_SAT_S_I16x8 { 1499, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1499 = POPCNT_I8x16_S { 1498, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1498 = POPCNT_I8x16 { 1497, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1497 = POPCNT_I64_S { 1496, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 290, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1496 = POPCNT_I64 { 1495, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1495 = POPCNT_I32_S { 1494, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 288, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1494 = POPCNT_I32 { 1493, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1493 = PMIN_F64x2_S { 1492, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1492 = PMIN_F64x2 { 1491, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1491 = PMIN_F32x4_S { 1490, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1490 = PMIN_F32x4 { 1489, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1489 = PMIN_F16x8_S { 1488, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1488 = PMIN_F16x8 { 1487, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1487 = PMAX_F64x2_S { 1486, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1486 = PMAX_F64x2 { 1485, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1485 = PMAX_F32x4_S { 1484, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1484 = PMAX_F32x4 { 1483, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1483 = PMAX_F16x8_S { 1482, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1482 = PMAX_F16x8 { 1481, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1481 = OR_S { 1480, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1480 = OR_I64_S { 1479, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 173, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1479 = OR_I64 { 1478, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1478 = OR_I32_S { 1477, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 170, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1477 = OR_I32 { 1476, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1476 = OR { 1475, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1475 = NOT_S { 1474, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1474 = NOT { 1473, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1473 = NOP_S { 1472, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1472 = NOP { 1471, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1471 = NMADD_F64x2_S { 1470, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 274, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1470 = NMADD_F64x2 { 1469, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1469 = NMADD_F32x4_S { 1468, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 274, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1468 = NMADD_F32x4 { 1467, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1467 = NMADD_F16x8_S { 1466, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 274, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1466 = NMADD_F16x8 { 1465, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1465 = NE_I8x16_S { 1464, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1464 = NE_I8x16 { 1463, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1463 = NE_I64x2_S { 1462, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1462 = NE_I64x2 { 1461, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1461 = NE_I64_S { 1460, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 402, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1460 = NE_I64 { 1459, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1459 = NE_I32x4_S { 1458, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1458 = NE_I32x4 { 1457, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1457 = NE_I32_S { 1456, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 170, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1456 = NE_I32 { 1455, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1455 = NE_I16x8_S { 1454, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1454 = NE_I16x8 { 1453, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1453 = NE_F64x2_S { 1452, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1452 = NE_F64x2 { 1451, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1451 = NE_F64_S { 1450, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 399, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1450 = NE_F64 { 1449, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1449 = NE_F32x4_S { 1448, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1448 = NE_F32x4 { 1447, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1447 = NE_F32_S { 1446, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 396, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1446 = NE_F32 { 1445, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1445 = NE_F16x8_S { 1444, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1444 = NE_F16x8 { 1443, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1443 = NEG_I8x16_S { 1442, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1442 = NEG_I8x16 { 1441, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1441 = NEG_I64x2_S { 1440, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1440 = NEG_I64x2 { 1439, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1439 = NEG_I32x4_S { 1438, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1438 = NEG_I32x4 { 1437, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1437 = NEG_I16x8_S { 1436, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1436 = NEG_I16x8 { 1435, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1435 = NEG_F64x2_S { 1434, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1434 = NEG_F64x2 { 1433, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1433 = NEG_F64_S { 1432, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 159, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1432 = NEG_F64 { 1431, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1431 = NEG_F32x4_S { 1430, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1430 = NEG_F32x4 { 1429, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1429 = NEG_F32_S { 1428, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 157, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1428 = NEG_F32 { 1427, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1427 = NEG_F16x8_S { 1426, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1426 = NEG_F16x8 { 1425, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1425 = NEAREST_F64x2_S { 1424, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1424 = NEAREST_F64x2 { 1423, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1423 = NEAREST_F64_S { 1422, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 159, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1422 = NEAREST_F64 { 1421, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1421 = NEAREST_F32x4_S { 1420, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1420 = NEAREST_F32x4 { 1419, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1419 = NEAREST_F32_S { 1418, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 157, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1418 = NEAREST_F32 { 1417, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1417 = NEAREST_F16x8_S { 1416, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1416 = NEAREST_F16x8 { 1415, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1415 = NARROW_U_I8x16_S { 1414, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1414 = NARROW_U_I8x16 { 1413, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1413 = NARROW_U_I16x8_S { 1412, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1412 = NARROW_U_I16x8 { 1411, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1411 = NARROW_S_I8x16_S { 1410, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1410 = NARROW_S_I8x16 { 1409, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1409 = NARROW_S_I16x8_S { 1408, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1408 = NARROW_S_I16x8 { 1407, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1407 = MUL_I64x2_S { 1406, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1406 = MUL_I64x2 { 1405, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1405 = MUL_I64_S { 1404, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 173, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1404 = MUL_I64 { 1403, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1403 = MUL_I32x4_S { 1402, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1402 = MUL_I32x4 { 1401, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1401 = MUL_I32_S { 1400, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 170, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1400 = MUL_I32 { 1399, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1399 = MUL_I16x8_S { 1398, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1398 = MUL_I16x8 { 1397, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1397 = MUL_F64x2_S { 1396, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1396 = MUL_F64x2 { 1395, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1395 = MUL_F64_S { 1394, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 167, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1394 = MUL_F64 { 1393, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1393 = MUL_F32x4_S { 1392, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1392 = MUL_F32x4 { 1391, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1391 = MUL_F32_S { 1390, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 164, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1390 = MUL_F32 { 1389, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1389 = MUL_F16x8_S { 1388, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1388 = MUL_F16x8 { 1387, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1387 = MIN_U_I8x16_S { 1386, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1386 = MIN_U_I8x16 { 1385, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1385 = MIN_U_I32x4_S { 1384, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1384 = MIN_U_I32x4 { 1383, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1383 = MIN_U_I16x8_S { 1382, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1382 = MIN_U_I16x8 { 1381, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1381 = MIN_S_I8x16_S { 1380, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1380 = MIN_S_I8x16 { 1379, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1379 = MIN_S_I32x4_S { 1378, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1378 = MIN_S_I32x4 { 1377, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1377 = MIN_S_I16x8_S { 1376, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1376 = MIN_S_I16x8 { 1375, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1375 = MIN_F64x2_S { 1374, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1374 = MIN_F64x2 { 1373, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1373 = MIN_F64_S { 1372, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 167, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1372 = MIN_F64 { 1371, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1371 = MIN_F32x4_S { 1370, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1370 = MIN_F32x4 { 1369, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1369 = MIN_F32_S { 1368, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 164, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1368 = MIN_F32 { 1367, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1367 = MIN_F16x8_S { 1366, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1366 = MIN_F16x8 { 1365, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1365 = MEMORY_ATOMIC_WAIT64_A64_S { 1364, 6, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 592, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1364 = MEMORY_ATOMIC_WAIT64_A64 { 1363, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1363 = MEMORY_ATOMIC_WAIT64_A32_S { 1362, 6, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 586, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1362 = MEMORY_ATOMIC_WAIT64_A32 { 1361, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1361 = MEMORY_ATOMIC_WAIT32_A64_S { 1360, 6, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 580, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1360 = MEMORY_ATOMIC_WAIT32_A64 { 1359, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1359 = MEMORY_ATOMIC_WAIT32_A32_S { 1358, 6, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 574, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1358 = MEMORY_ATOMIC_WAIT32_A32 { 1357, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1357 = MEMORY_ATOMIC_NOTIFY_A64_S { 1356, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 219, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1356 = MEMORY_ATOMIC_NOTIFY_A64 { 1355, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1355 = MEMORY_ATOMIC_NOTIFY_A32_S { 1354, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 214, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1354 = MEMORY_ATOMIC_NOTIFY_A32 { 1353, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1353 = MAX_U_I8x16_S { 1352, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1352 = MAX_U_I8x16 { 1351, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1351 = MAX_U_I32x4_S { 1350, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1350 = MAX_U_I32x4 { 1349, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1349 = MAX_U_I16x8_S { 1348, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1348 = MAX_U_I16x8 { 1347, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1347 = MAX_S_I8x16_S { 1346, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1346 = MAX_S_I8x16 { 1345, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1345 = MAX_S_I32x4_S { 1344, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1344 = MAX_S_I32x4 { 1343, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1343 = MAX_S_I16x8_S { 1342, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1342 = MAX_S_I16x8 { 1341, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1341 = MAX_F64x2_S { 1340, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1340 = MAX_F64x2 { 1339, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1339 = MAX_F64_S { 1338, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 167, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1338 = MAX_F64 { 1337, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1337 = MAX_F32x4_S { 1336, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1336 = MAX_F32x4 { 1335, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1335 = MAX_F32_S { 1334, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 164, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1334 = MAX_F32 { 1333, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1333 = MAX_F16x8_S { 1332, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1332 = MAX_F16x8 { 1331, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1331 = MADD_F64x2_S { 1330, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 274, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1330 = MADD_F64x2 { 1329, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1329 = MADD_F32x4_S { 1328, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 274, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1328 = MADD_F32x4 { 1327, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1327 = MADD_F16x8_S { 1326, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 274, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1326 = MADD_F16x8 { 1325, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1325 = LT_U_I8x16_S { 1324, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1324 = LT_U_I8x16 { 1323, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1323 = LT_U_I64_S { 1322, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 402, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1322 = LT_U_I64 { 1321, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1321 = LT_U_I32x4_S { 1320, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1320 = LT_U_I32x4 { 1319, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1319 = LT_U_I32_S { 1318, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 170, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1318 = LT_U_I32 { 1317, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1317 = LT_U_I16x8_S { 1316, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1316 = LT_U_I16x8 { 1315, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1315 = LT_S_I8x16_S { 1314, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1314 = LT_S_I8x16 { 1313, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1313 = LT_S_I64x2_S { 1312, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1312 = LT_S_I64x2 { 1311, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1311 = LT_S_I64_S { 1310, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 402, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1310 = LT_S_I64 { 1309, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1309 = LT_S_I32x4_S { 1308, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1308 = LT_S_I32x4 { 1307, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1307 = LT_S_I32_S { 1306, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 170, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1306 = LT_S_I32 { 1305, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1305 = LT_S_I16x8_S { 1304, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1304 = LT_S_I16x8 { 1303, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1303 = LT_F64x2_S { 1302, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1302 = LT_F64x2 { 1301, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1301 = LT_F64_S { 1300, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 399, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1300 = LT_F64 { 1299, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1299 = LT_F32x4_S { 1298, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1298 = LT_F32x4 { 1297, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1297 = LT_F32_S { 1296, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 396, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1296 = LT_F32 { 1295, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1295 = LT_F16x8_S { 1294, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1294 = LT_F16x8 { 1293, 1, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 8, 278, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1293 = LOOP_S { 1292, 1, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 8, 278, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1292 = LOOP { 1291, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 519, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1291 = LOCAL_TEE_V128_S { 1290, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 571, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1290 = LOCAL_TEE_V128 { 1289, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 519, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1289 = LOCAL_TEE_I64_S { 1288, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 568, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1288 = LOCAL_TEE_I64 { 1287, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 519, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1287 = LOCAL_TEE_I32_S { 1286, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 565, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1286 = LOCAL_TEE_I32 { 1285, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 519, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1285 = LOCAL_TEE_FUNCREF_S { 1284, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 562, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1284 = LOCAL_TEE_FUNCREF { 1283, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 519, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1283 = LOCAL_TEE_F64_S { 1282, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 559, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1282 = LOCAL_TEE_F64 { 1281, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 519, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1281 = LOCAL_TEE_F32_S { 1280, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 556, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1280 = LOCAL_TEE_F32 { 1279, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 519, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1279 = LOCAL_TEE_EXTERNREF_S { 1278, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 553, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1278 = LOCAL_TEE_EXTERNREF { 1277, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 519, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1277 = LOCAL_TEE_EXNREF_S { 1276, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 550, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1276 = LOCAL_TEE_EXNREF { 1275, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 519, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1275 = LOCAL_SET_V128_S { 1274, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 548, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1274 = LOCAL_SET_V128 { 1273, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 519, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1273 = LOCAL_SET_I64_S { 1272, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 546, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1272 = LOCAL_SET_I64 { 1271, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 519, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1271 = LOCAL_SET_I32_S { 1270, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 544, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1270 = LOCAL_SET_I32 { 1269, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 519, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1269 = LOCAL_SET_FUNCREF_S { 1268, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 542, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1268 = LOCAL_SET_FUNCREF { 1267, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 519, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1267 = LOCAL_SET_F64_S { 1266, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 540, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1266 = LOCAL_SET_F64 { 1265, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 519, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1265 = LOCAL_SET_F32_S { 1264, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 538, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1264 = LOCAL_SET_F32 { 1263, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 519, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1263 = LOCAL_SET_EXTERNREF_S { 1262, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 536, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1262 = LOCAL_SET_EXTERNREF { 1261, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 519, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1261 = LOCAL_SET_EXNREF_S { 1260, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 534, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1260 = LOCAL_SET_EXNREF { 1259, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 519, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1259 = LOCAL_GET_V128_S { 1258, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 532, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1258 = LOCAL_GET_V128 { 1257, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 519, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1257 = LOCAL_GET_I64_S { 1256, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 530, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1256 = LOCAL_GET_I64 { 1255, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 519, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1255 = LOCAL_GET_I32_S { 1254, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 528, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1254 = LOCAL_GET_I32 { 1253, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 519, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1253 = LOCAL_GET_FUNCREF_S { 1252, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 526, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1252 = LOCAL_GET_FUNCREF { 1251, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 519, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1251 = LOCAL_GET_F64_S { 1250, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 524, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1250 = LOCAL_GET_F64 { 1249, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 519, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1249 = LOCAL_GET_F32_S { 1248, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 522, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1248 = LOCAL_GET_F32 { 1247, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 519, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1247 = LOCAL_GET_EXTERNREF_S { 1246, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 520, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1246 = LOCAL_GET_EXTERNREF { 1245, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 519, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1245 = LOCAL_GET_EXNREF_S { 1244, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 517, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1244 = LOCAL_GET_EXNREF { 1243, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1243 = LOAD_ZERO_64_A64_S { 1242, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 479, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1242 = LOAD_ZERO_64_A64 { 1241, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1241 = LOAD_ZERO_64_A32_S { 1240, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 475, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1240 = LOAD_ZERO_64_A32 { 1239, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1239 = LOAD_ZERO_32_A64_S { 1238, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 479, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1238 = LOAD_ZERO_32_A64 { 1237, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1237 = LOAD_ZERO_32_A32_S { 1236, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 475, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1236 = LOAD_ZERO_32_A32 { 1235, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1235 = LOAD_V128_A64_S { 1234, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 479, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1234 = LOAD_V128_A64 { 1233, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1233 = LOAD_V128_A32_S { 1232, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 475, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1232 = LOAD_V128_A32 { 1231, 3, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 514, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1231 = LOAD_LANE_8_A64_S { 1230, 6, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 508, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1230 = LOAD_LANE_8_A64 { 1229, 3, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 505, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1229 = LOAD_LANE_8_A32_S { 1228, 6, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 499, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1228 = LOAD_LANE_8_A32 { 1227, 3, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 514, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1227 = LOAD_LANE_64_A64_S { 1226, 6, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 508, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1226 = LOAD_LANE_64_A64 { 1225, 3, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 505, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1225 = LOAD_LANE_64_A32_S { 1224, 6, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 499, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1224 = LOAD_LANE_64_A32 { 1223, 3, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 514, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1223 = LOAD_LANE_32_A64_S { 1222, 6, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 508, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1222 = LOAD_LANE_32_A64 { 1221, 3, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 505, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1221 = LOAD_LANE_32_A32_S { 1220, 6, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 499, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1220 = LOAD_LANE_32_A32 { 1219, 3, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 514, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1219 = LOAD_LANE_16_A64_S { 1218, 6, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 508, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1218 = LOAD_LANE_16_A64 { 1217, 3, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 505, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1217 = LOAD_LANE_16_A32_S { 1216, 6, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 499, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1216 = LOAD_LANE_16_A32 { 1215, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1215 = LOAD_I64_A64_S { 1214, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 210, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1214 = LOAD_I64_A64 { 1213, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1213 = LOAD_I64_A32_S { 1212, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 206, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1212 = LOAD_I64_A32 { 1211, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1211 = LOAD_I32_A64_S { 1210, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 200, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1210 = LOAD_I32_A64 { 1209, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1209 = LOAD_I32_A32_S { 1208, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 194, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1208 = LOAD_I32_A32 { 1207, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1207 = LOAD_F64_A64_S { 1206, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 495, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1206 = LOAD_F64_A64 { 1205, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1205 = LOAD_F64_A32_S { 1204, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 491, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1204 = LOAD_F64_A32 { 1203, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1203 = LOAD_F32_A64_S { 1202, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 487, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1202 = LOAD_F32_A64 { 1201, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1201 = LOAD_F32_A32_S { 1200, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 483, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1200 = LOAD_F32_A32 { 1199, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1199 = LOAD_F16_F32_A64_S { 1198, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 487, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1198 = LOAD_F16_F32_A64 { 1197, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1197 = LOAD_F16_F32_A32_S { 1196, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 483, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1196 = LOAD_F16_F32_A32 { 1195, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1195 = LOAD_EXTEND_U_I64x2_A64_S { 1194, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 479, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1194 = LOAD_EXTEND_U_I64x2_A64 { 1193, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1193 = LOAD_EXTEND_U_I64x2_A32_S { 1192, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 475, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1192 = LOAD_EXTEND_U_I64x2_A32 { 1191, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1191 = LOAD_EXTEND_U_I32x4_A64_S { 1190, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 479, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1190 = LOAD_EXTEND_U_I32x4_A64 { 1189, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1189 = LOAD_EXTEND_U_I32x4_A32_S { 1188, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 475, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1188 = LOAD_EXTEND_U_I32x4_A32 { 1187, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1187 = LOAD_EXTEND_U_I16x8_A64_S { 1186, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 479, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1186 = LOAD_EXTEND_U_I16x8_A64 { 1185, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1185 = LOAD_EXTEND_U_I16x8_A32_S { 1184, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 475, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1184 = LOAD_EXTEND_U_I16x8_A32 { 1183, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1183 = LOAD_EXTEND_S_I64x2_A64_S { 1182, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 479, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1182 = LOAD_EXTEND_S_I64x2_A64 { 1181, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1181 = LOAD_EXTEND_S_I64x2_A32_S { 1180, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 475, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1180 = LOAD_EXTEND_S_I64x2_A32 { 1179, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1179 = LOAD_EXTEND_S_I32x4_A64_S { 1178, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 479, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1178 = LOAD_EXTEND_S_I32x4_A64 { 1177, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1177 = LOAD_EXTEND_S_I32x4_A32_S { 1176, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 475, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1176 = LOAD_EXTEND_S_I32x4_A32 { 1175, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1175 = LOAD_EXTEND_S_I16x8_A64_S { 1174, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 479, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1174 = LOAD_EXTEND_S_I16x8_A64 { 1173, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1173 = LOAD_EXTEND_S_I16x8_A32_S { 1172, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 475, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1172 = LOAD_EXTEND_S_I16x8_A32 { 1171, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1171 = LOAD8_U_I64_A64_S { 1170, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 210, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1170 = LOAD8_U_I64_A64 { 1169, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1169 = LOAD8_U_I64_A32_S { 1168, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 206, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1168 = LOAD8_U_I64_A32 { 1167, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1167 = LOAD8_U_I32_A64_S { 1166, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 200, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1166 = LOAD8_U_I32_A64 { 1165, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1165 = LOAD8_U_I32_A32_S { 1164, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 194, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1164 = LOAD8_U_I32_A32 { 1163, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1163 = LOAD8_S_I64_A64_S { 1162, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 210, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1162 = LOAD8_S_I64_A64 { 1161, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1161 = LOAD8_S_I64_A32_S { 1160, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 206, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1160 = LOAD8_S_I64_A32 { 1159, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1159 = LOAD8_S_I32_A64_S { 1158, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 200, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1158 = LOAD8_S_I32_A64 { 1157, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1157 = LOAD8_S_I32_A32_S { 1156, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 194, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1156 = LOAD8_S_I32_A32 { 1155, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1155 = LOAD8_SPLAT_A64_S { 1154, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 479, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1154 = LOAD8_SPLAT_A64 { 1153, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1153 = LOAD8_SPLAT_A32_S { 1152, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 475, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1152 = LOAD8_SPLAT_A32 { 1151, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1151 = LOAD64_SPLAT_A64_S { 1150, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 479, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1150 = LOAD64_SPLAT_A64 { 1149, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1149 = LOAD64_SPLAT_A32_S { 1148, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 475, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1148 = LOAD64_SPLAT_A32 { 1147, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1147 = LOAD32_U_I64_A64_S { 1146, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 210, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1146 = LOAD32_U_I64_A64 { 1145, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1145 = LOAD32_U_I64_A32_S { 1144, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 206, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1144 = LOAD32_U_I64_A32 { 1143, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1143 = LOAD32_S_I64_A64_S { 1142, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 210, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1142 = LOAD32_S_I64_A64 { 1141, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1141 = LOAD32_S_I64_A32_S { 1140, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 206, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1140 = LOAD32_S_I64_A32 { 1139, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1139 = LOAD32_SPLAT_A64_S { 1138, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 479, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1138 = LOAD32_SPLAT_A64 { 1137, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1137 = LOAD32_SPLAT_A32_S { 1136, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 475, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1136 = LOAD32_SPLAT_A32 { 1135, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1135 = LOAD16_U_I64_A64_S { 1134, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 210, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1134 = LOAD16_U_I64_A64 { 1133, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1133 = LOAD16_U_I64_A32_S { 1132, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 206, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1132 = LOAD16_U_I64_A32 { 1131, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1131 = LOAD16_U_I32_A64_S { 1130, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 200, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1130 = LOAD16_U_I32_A64 { 1129, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1129 = LOAD16_U_I32_A32_S { 1128, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 194, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1128 = LOAD16_U_I32_A32 { 1127, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1127 = LOAD16_S_I64_A64_S { 1126, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 210, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1126 = LOAD16_S_I64_A64 { 1125, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1125 = LOAD16_S_I64_A32_S { 1124, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 206, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1124 = LOAD16_S_I64_A32 { 1123, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1123 = LOAD16_S_I32_A64_S { 1122, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 200, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1122 = LOAD16_S_I32_A64 { 1121, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1121 = LOAD16_S_I32_A32_S { 1120, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 194, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1120 = LOAD16_S_I32_A32 { 1119, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1119 = LOAD16_SPLAT_A64_S { 1118, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 479, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1118 = LOAD16_SPLAT_A64 { 1117, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1117 = LOAD16_SPLAT_A32_S { 1116, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 475, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1116 = LOAD16_SPLAT_A32 { 1115, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1115 = LE_U_I8x16_S { 1114, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1114 = LE_U_I8x16 { 1113, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1113 = LE_U_I64_S { 1112, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 402, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1112 = LE_U_I64 { 1111, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1111 = LE_U_I32x4_S { 1110, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1110 = LE_U_I32x4 { 1109, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1109 = LE_U_I32_S { 1108, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 170, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1108 = LE_U_I32 { 1107, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1107 = LE_U_I16x8_S { 1106, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1106 = LE_U_I16x8 { 1105, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1105 = LE_S_I8x16_S { 1104, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1104 = LE_S_I8x16 { 1103, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1103 = LE_S_I64x2_S { 1102, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1102 = LE_S_I64x2 { 1101, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1101 = LE_S_I64_S { 1100, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 402, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1100 = LE_S_I64 { 1099, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1099 = LE_S_I32x4_S { 1098, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1098 = LE_S_I32x4 { 1097, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1097 = LE_S_I32_S { 1096, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 170, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1096 = LE_S_I32 { 1095, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1095 = LE_S_I16x8_S { 1094, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1094 = LE_S_I16x8 { 1093, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1093 = LE_F64x2_S { 1092, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1092 = LE_F64x2 { 1091, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1091 = LE_F64_S { 1090, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 399, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1090 = LE_F64 { 1089, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1089 = LE_F32x4_S { 1088, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1088 = LE_F32x4 { 1087, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1087 = LE_F32_S { 1086, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 396, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1086 = LE_F32 { 1085, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1085 = LE_F16x8_S { 1084, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1084 = LE_F16x8 { 1083, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1083 = LANESELECT_I8x16_S { 1082, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 274, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1082 = LANESELECT_I8x16 { 1081, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1081 = LANESELECT_I64x2_S { 1080, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 274, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1080 = LANESELECT_I64x2 { 1079, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1079 = LANESELECT_I32x4_S { 1078, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 274, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1078 = LANESELECT_I32x4 { 1077, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1077 = LANESELECT_I16x8_S { 1076, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 274, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1076 = LANESELECT_I16x8 { 1075, 1, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 8, 278, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1075 = IF_S { 1074, 2, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 8, 473, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1074 = IF { 1073, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1073 = I64_TRUNC_U_SAT_F64_S { 1072, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 436, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1072 = I64_TRUNC_U_SAT_F64 { 1071, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1071 = I64_TRUNC_U_SAT_F32_S { 1070, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 434, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1070 = I64_TRUNC_U_SAT_F32 { 1069, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1069 = I64_TRUNC_U_F64_S { 1068, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 436, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1068 = I64_TRUNC_U_F64 { 1067, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1067 = I64_TRUNC_U_F32_S { 1066, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 434, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1066 = I64_TRUNC_U_F32 { 1065, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1065 = I64_TRUNC_S_SAT_F64_S { 1064, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 436, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1064 = I64_TRUNC_S_SAT_F64 { 1063, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1063 = I64_TRUNC_S_SAT_F32_S { 1062, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 434, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1062 = I64_TRUNC_S_SAT_F32 { 1061, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1061 = I64_TRUNC_S_F64_S { 1060, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 436, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1060 = I64_TRUNC_S_F64 { 1059, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1059 = I64_TRUNC_S_F32_S { 1058, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 434, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1058 = I64_TRUNC_S_F32 { 1057, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1057 = I64_REINTERPRET_F64_S { 1056, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 436, 0|(1ULL<<MCID::Bitcast)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1056 = I64_REINTERPRET_F64 { 1055, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1055 = I64_EXTEND_U_I32_S { 1054, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 471, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1054 = I64_EXTEND_U_I32 { 1053, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1053 = I64_EXTEND_S_I32_S { 1052, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 471, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1052 = I64_EXTEND_S_I32 { 1051, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1051 = I64_EXTEND8_S_I64_S { 1050, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 290, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1050 = I64_EXTEND8_S_I64 { 1049, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1049 = I64_EXTEND32_S_I64_S { 1048, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 290, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1048 = I64_EXTEND32_S_I64 { 1047, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1047 = I64_EXTEND16_S_I64_S { 1046, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 290, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1046 = I64_EXTEND16_S_I64 { 1045, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1045 = I32_WRAP_I64_S { 1044, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 394, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1044 = I32_WRAP_I64 { 1043, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1043 = I32_TRUNC_U_SAT_F64_S { 1042, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 432, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1042 = I32_TRUNC_U_SAT_F64 { 1041, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1041 = I32_TRUNC_U_SAT_F32_S { 1040, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 430, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1040 = I32_TRUNC_U_SAT_F32 { 1039, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1039 = I32_TRUNC_U_F64_S { 1038, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 432, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1038 = I32_TRUNC_U_F64 { 1037, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1037 = I32_TRUNC_U_F32_S { 1036, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 430, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1036 = I32_TRUNC_U_F32 { 1035, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1035 = I32_TRUNC_S_SAT_F64_S { 1034, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 432, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1034 = I32_TRUNC_S_SAT_F64 { 1033, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1033 = I32_TRUNC_S_SAT_F32_S { 1032, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 430, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1032 = I32_TRUNC_S_SAT_F32 { 1031, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1031 = I32_TRUNC_S_F64_S { 1030, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 432, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1030 = I32_TRUNC_S_F64 { 1029, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1029 = I32_TRUNC_S_F32_S { 1028, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 430, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1028 = I32_TRUNC_S_F32 { 1027, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1027 = I32_REINTERPRET_F32_S { 1026, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 430, 0|(1ULL<<MCID::Bitcast)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1026 = I32_REINTERPRET_F32 { 1025, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1025 = I32_EXTEND8_S_I32_S { 1024, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 288, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1024 = I32_EXTEND8_S_I32 { 1023, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1023 = I32_EXTEND16_S_I32_S { 1022, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 288, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1022 = I32_EXTEND16_S_I32 { 1021, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1021 = GT_U_I8x16_S { 1020, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1020 = GT_U_I8x16 { 1019, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1019 = GT_U_I64_S { 1018, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 402, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1018 = GT_U_I64 { 1017, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1017 = GT_U_I32x4_S { 1016, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1016 = GT_U_I32x4 { 1015, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1015 = GT_U_I32_S { 1014, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 170, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1014 = GT_U_I32 { 1013, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1013 = GT_U_I16x8_S { 1012, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1012 = GT_U_I16x8 { 1011, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1011 = GT_S_I8x16_S { 1010, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1010 = GT_S_I8x16 { 1009, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1009 = GT_S_I64x2_S { 1008, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1008 = GT_S_I64x2 { 1007, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1007 = GT_S_I64_S { 1006, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 402, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1006 = GT_S_I64 { 1005, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1005 = GT_S_I32x4_S { 1004, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1004 = GT_S_I32x4 { 1003, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1003 = GT_S_I32_S { 1002, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 170, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1002 = GT_S_I32 { 1001, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1001 = GT_S_I16x8_S { 1000, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1000 = GT_S_I16x8 { 999, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #999 = GT_F64x2_S { 998, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #998 = GT_F64x2 { 997, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #997 = GT_F64_S { 996, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 399, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #996 = GT_F64 { 995, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #995 = GT_F32x4_S { 994, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #994 = GT_F32x4 { 993, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #993 = GT_F32_S { 992, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 396, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #992 = GT_F32 { 991, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #991 = GT_F16x8_S { 990, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #990 = GT_F16x8 { 989, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 440, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #989 = GLOBAL_SET_V128_S { 988, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 469, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #988 = GLOBAL_SET_V128 { 987, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 440, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #987 = GLOBAL_SET_I64_S { 986, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 467, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #986 = GLOBAL_SET_I64 { 985, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 440, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #985 = GLOBAL_SET_I32_S { 984, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 465, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #984 = GLOBAL_SET_I32 { 983, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 440, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #983 = GLOBAL_SET_FUNCREF_S { 982, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 463, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #982 = GLOBAL_SET_FUNCREF { 981, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 440, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #981 = GLOBAL_SET_F64_S { 980, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 461, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #980 = GLOBAL_SET_F64 { 979, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 440, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #979 = GLOBAL_SET_F32_S { 978, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 459, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #978 = GLOBAL_SET_F32 { 977, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 440, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #977 = GLOBAL_SET_EXTERNREF_S { 976, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 457, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #976 = GLOBAL_SET_EXTERNREF { 975, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 440, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #975 = GLOBAL_SET_EXNREF_S { 974, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 455, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #974 = GLOBAL_SET_EXNREF { 973, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 440, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #973 = GLOBAL_GET_V128_S { 972, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 453, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #972 = GLOBAL_GET_V128 { 971, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 440, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #971 = GLOBAL_GET_I64_S { 970, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 451, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #970 = GLOBAL_GET_I64 { 969, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 440, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #969 = GLOBAL_GET_I32_S { 968, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 449, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #968 = GLOBAL_GET_I32 { 967, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 440, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #967 = GLOBAL_GET_FUNCREF_S { 966, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 447, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #966 = GLOBAL_GET_FUNCREF { 965, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 440, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #965 = GLOBAL_GET_F64_S { 964, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 445, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #964 = GLOBAL_GET_F64 { 963, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 440, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #963 = GLOBAL_GET_F32_S { 962, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 443, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #962 = GLOBAL_GET_F32 { 961, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 440, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #961 = GLOBAL_GET_EXTERNREF_S { 960, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 441, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #960 = GLOBAL_GET_EXTERNREF { 959, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 440, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #959 = GLOBAL_GET_EXNREF_S { 958, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 438, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #958 = GLOBAL_GET_EXNREF { 957, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #957 = GE_U_I8x16_S { 956, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #956 = GE_U_I8x16 { 955, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #955 = GE_U_I64_S { 954, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 402, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #954 = GE_U_I64 { 953, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #953 = GE_U_I32x4_S { 952, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #952 = GE_U_I32x4 { 951, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #951 = GE_U_I32_S { 950, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 170, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #950 = GE_U_I32 { 949, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #949 = GE_U_I16x8_S { 948, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #948 = GE_U_I16x8 { 947, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #947 = GE_S_I8x16_S { 946, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #946 = GE_S_I8x16 { 945, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #945 = GE_S_I64x2_S { 944, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #944 = GE_S_I64x2 { 943, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #943 = GE_S_I64_S { 942, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 402, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #942 = GE_S_I64 { 941, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #941 = GE_S_I32x4_S { 940, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #940 = GE_S_I32x4 { 939, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #939 = GE_S_I32_S { 938, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 170, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #938 = GE_S_I32 { 937, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #937 = GE_S_I16x8_S { 936, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #936 = GE_S_I16x8 { 935, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #935 = GE_F64x2_S { 934, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #934 = GE_F64x2 { 933, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #933 = GE_F64_S { 932, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 399, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #932 = GE_F64 { 931, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #931 = GE_F32x4_S { 930, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #930 = GE_F32x4 { 929, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #929 = GE_F32_S { 928, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 396, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #928 = GE_F32 { 927, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #927 = GE_F16x8_S { 926, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #926 = GE_F16x8 { 925, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #925 = FP_TO_UINT_I64_F64_S { 924, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 436, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #924 = FP_TO_UINT_I64_F64 { 923, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #923 = FP_TO_UINT_I64_F32_S { 922, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 434, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #922 = FP_TO_UINT_I64_F32 { 921, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #921 = FP_TO_UINT_I32_F64_S { 920, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 432, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #920 = FP_TO_UINT_I32_F64 { 919, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #919 = FP_TO_UINT_I32_F32_S { 918, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 430, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #918 = FP_TO_UINT_I32_F32 { 917, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #917 = FP_TO_SINT_I64_F64_S { 916, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 436, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #916 = FP_TO_SINT_I64_F64 { 915, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #915 = FP_TO_SINT_I64_F32_S { 914, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 434, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #914 = FP_TO_SINT_I64_F32 { 913, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #913 = FP_TO_SINT_I32_F64_S { 912, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 432, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #912 = FP_TO_SINT_I32_F64 { 911, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #911 = FP_TO_SINT_I32_F32_S { 910, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 430, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #910 = FP_TO_SINT_I32_F32 { 909, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #909 = FLOOR_F64x2_S { 908, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #908 = FLOOR_F64x2 { 907, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #907 = FLOOR_F64_S { 906, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 159, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #906 = FLOOR_F64 { 905, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #905 = FLOOR_F32x4_S { 904, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #904 = FLOOR_F32x4 { 903, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #903 = FLOOR_F32_S { 902, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 157, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #902 = FLOOR_F32 { 901, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #901 = FLOOR_F16x8_S { 900, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #900 = FLOOR_F16x8 { 899, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #899 = FALLTHROUGH_RETURN_S { 898, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #898 = FALLTHROUGH_RETURN { 897, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #897 = F64_REINTERPRET_I64_S { 896, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 426, 0|(1ULL<<MCID::Bitcast)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #896 = F64_REINTERPRET_I64 { 895, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #895 = F64_PROMOTE_F32_S { 894, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 428, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #894 = F64_PROMOTE_F32 { 893, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #893 = F64_CONVERT_U_I64_S { 892, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 426, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #892 = F64_CONVERT_U_I64 { 891, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #891 = F64_CONVERT_U_I32_S { 890, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 424, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #890 = F64_CONVERT_U_I32 { 889, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #889 = F64_CONVERT_S_I64_S { 888, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 426, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #888 = F64_CONVERT_S_I64 { 887, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #887 = F64_CONVERT_S_I32_S { 886, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 424, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #886 = F64_CONVERT_S_I32 { 885, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #885 = F32_REINTERPRET_I32_S { 884, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 418, 0|(1ULL<<MCID::Bitcast)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #884 = F32_REINTERPRET_I32 { 883, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #883 = F32_DEMOTE_F64_S { 882, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 422, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #882 = F32_DEMOTE_F64 { 881, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #881 = F32_CONVERT_U_I64_S { 880, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 420, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #880 = F32_CONVERT_U_I64 { 879, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #879 = F32_CONVERT_U_I32_S { 878, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 418, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #878 = F32_CONVERT_U_I32 { 877, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #877 = F32_CONVERT_S_I64_S { 876, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 420, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #876 = F32_CONVERT_S_I64 { 875, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #875 = F32_CONVERT_S_I32_S { 874, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 418, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #874 = F32_CONVERT_S_I32 { 873, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 408, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #873 = EXTRACT_LANE_I8x16_u_S { 872, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 412, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #872 = EXTRACT_LANE_I8x16_u { 871, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 408, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #871 = EXTRACT_LANE_I8x16_s_S { 870, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 412, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #870 = EXTRACT_LANE_I8x16_s { 869, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 408, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #869 = EXTRACT_LANE_I64x2_S { 868, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 415, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #868 = EXTRACT_LANE_I64x2 { 867, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 408, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #867 = EXTRACT_LANE_I32x4_S { 866, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 412, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #866 = EXTRACT_LANE_I32x4 { 865, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 408, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #865 = EXTRACT_LANE_I16x8_u_S { 864, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 412, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #864 = EXTRACT_LANE_I16x8_u { 863, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 408, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #863 = EXTRACT_LANE_I16x8_s_S { 862, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 412, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #862 = EXTRACT_LANE_I16x8_s { 861, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 408, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #861 = EXTRACT_LANE_F64x2_S { 860, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 409, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #860 = EXTRACT_LANE_F64x2 { 859, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 408, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #859 = EXTRACT_LANE_F32x4_S { 858, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 405, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #858 = EXTRACT_LANE_F32x4 { 857, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 408, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #857 = EXTRACT_LANE_F16x8_S { 856, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 405, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #856 = EXTRACT_LANE_F16x8 { 855, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #855 = EXTMUL_LOW_U_I64x2_S { 854, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #854 = EXTMUL_LOW_U_I64x2 { 853, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #853 = EXTMUL_LOW_U_I32x4_S { 852, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #852 = EXTMUL_LOW_U_I32x4 { 851, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #851 = EXTMUL_LOW_U_I16x8_S { 850, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #850 = EXTMUL_LOW_U_I16x8 { 849, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #849 = EXTMUL_LOW_S_I64x2_S { 848, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #848 = EXTMUL_LOW_S_I64x2 { 847, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #847 = EXTMUL_LOW_S_I32x4_S { 846, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #846 = EXTMUL_LOW_S_I32x4 { 845, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #845 = EXTMUL_LOW_S_I16x8_S { 844, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #844 = EXTMUL_LOW_S_I16x8 { 843, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #843 = EXTMUL_HIGH_U_I64x2_S { 842, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #842 = EXTMUL_HIGH_U_I64x2 { 841, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #841 = EXTMUL_HIGH_U_I32x4_S { 840, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #840 = EXTMUL_HIGH_U_I32x4 { 839, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #839 = EXTMUL_HIGH_U_I16x8_S { 838, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #838 = EXTMUL_HIGH_U_I16x8 { 837, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #837 = EXTMUL_HIGH_S_I64x2_S { 836, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #836 = EXTMUL_HIGH_S_I64x2 { 835, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #835 = EXTMUL_HIGH_S_I32x4_S { 834, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #834 = EXTMUL_HIGH_S_I32x4 { 833, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #833 = EXTMUL_HIGH_S_I16x8_S { 832, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #832 = EXTMUL_HIGH_S_I16x8 { 831, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #831 = EQ_I8x16_S { 830, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #830 = EQ_I8x16 { 829, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #829 = EQ_I64x2_S { 828, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #828 = EQ_I64x2 { 827, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #827 = EQ_I64_S { 826, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 402, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #826 = EQ_I64 { 825, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #825 = EQ_I32x4_S { 824, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #824 = EQ_I32x4 { 823, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #823 = EQ_I32_S { 822, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 170, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #822 = EQ_I32 { 821, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #821 = EQ_I16x8_S { 820, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #820 = EQ_I16x8 { 819, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #819 = EQ_F64x2_S { 818, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #818 = EQ_F64x2 { 817, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #817 = EQ_F64_S { 816, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 399, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #816 = EQ_F64 { 815, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #815 = EQ_F32x4_S { 814, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #814 = EQ_F32x4 { 813, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #813 = EQ_F32_S { 812, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 396, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #812 = EQ_F32 { 811, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #811 = EQ_F16x8_S { 810, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #810 = EQ_F16x8 { 809, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #809 = EQZ_I64_S { 808, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 394, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #808 = EQZ_I64 { 807, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #807 = EQZ_I32_S { 806, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 288, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #806 = EQZ_I32 { 805, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 8, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #805 = END_TRY_S { 804, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 8, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #804 = END_TRY { 803, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 8, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #803 = END_S { 802, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 8, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #802 = END_LOOP_S { 801, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 8, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #801 = END_LOOP { 800, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 8, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #800 = END_IF_S { 799, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 8, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #799 = END_IF { 798, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 8, 1, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #798 = END_FUNCTION_S { 797, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 8, 1, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #797 = END_FUNCTION { 796, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 8, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #796 = END_BLOCK_S { 795, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 8, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #795 = END_BLOCK { 794, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 8, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #794 = END { 793, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 8, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #793 = ELSE_S { 792, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 8, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #792 = ELSE { 791, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #791 = DROP_V128_S { 790, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 393, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #790 = DROP_V128 { 789, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #789 = DROP_I64_S { 788, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 284, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #788 = DROP_I64 { 787, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #787 = DROP_I32_S { 786, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 282, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #786 = DROP_I32 { 785, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #785 = DROP_FUNCREF_S { 784, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 392, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #784 = DROP_FUNCREF { 783, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #783 = DROP_F64_S { 782, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 391, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #782 = DROP_F64 { 781, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #781 = DROP_F32_S { 780, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 390, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #780 = DROP_F32 { 779, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #779 = DROP_EXTERNREF_S { 778, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 389, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #778 = DROP_EXTERNREF { 777, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #777 = DROP_EXNREF_S { 776, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 388, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #776 = DROP_EXNREF { 775, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #775 = DOT_S { 774, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #774 = DOT { 773, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #773 = DIV_U_I64_S { 772, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 173, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #772 = DIV_U_I64 { 771, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #771 = DIV_U_I32_S { 770, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 170, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #770 = DIV_U_I32 { 769, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #769 = DIV_S_I64_S { 768, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 173, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #768 = DIV_S_I64 { 767, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #767 = DIV_S_I32_S { 766, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 170, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #766 = DIV_S_I32 { 765, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #765 = DIV_F64x2_S { 764, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #764 = DIV_F64x2 { 763, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #763 = DIV_F64_S { 762, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 167, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #762 = DIV_F64 { 761, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #761 = DIV_F32x4_S { 760, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #760 = DIV_F32x4 { 759, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #759 = DIV_F32_S { 758, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 164, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #758 = DIV_F32 { 757, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #757 = DIV_F16x8_S { 756, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #756 = DIV_F16x8 { 755, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 279, 0|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #755 = DELEGATE_S { 754, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 279, 0|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #754 = DELEGATE { 753, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Trap)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #753 = DEBUG_UNREACHABLE_S { 752, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Trap)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #752 = DEBUG_UNREACHABLE { 751, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #751 = CTZ_I64_S { 750, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 290, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #750 = CTZ_I64 { 749, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #749 = CTZ_I32_S { 748, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 288, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #748 = CTZ_I32 { 747, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #747 = COPY_V128_S { 746, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #746 = COPY_V128 { 745, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #745 = COPY_I64_S { 744, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 290, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #744 = COPY_I64 { 743, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #743 = COPY_I32_S { 742, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 288, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #742 = COPY_I32 { 741, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #741 = COPY_FUNCREF_S { 740, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 386, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #740 = COPY_FUNCREF { 739, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #739 = COPY_F64_S { 738, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 159, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #738 = COPY_F64 { 737, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #737 = COPY_F32_S { 736, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 157, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #736 = COPY_F32 { 735, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #735 = COPY_EXTERNREF_S { 734, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 384, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #734 = COPY_EXTERNREF { 733, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #733 = COPY_EXNREF_S { 732, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 382, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #732 = COPY_EXNREF { 731, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #731 = COPYSIGN_F64_S { 730, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 167, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #730 = COPYSIGN_F64 { 729, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #729 = COPYSIGN_F32_S { 728, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 164, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #728 = COPYSIGN_F32 { 727, 16, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 366, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #727 = CONST_V128_I8x16_S { 726, 17, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 349, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #726 = CONST_V128_I8x16 { 725, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 347, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #725 = CONST_V128_I64x2_S { 724, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 344, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #724 = CONST_V128_I64x2 { 723, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 340, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #723 = CONST_V128_I32x4_S { 722, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 335, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #722 = CONST_V128_I32x4 { 721, 8, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 327, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #721 = CONST_V128_I16x8_S { 720, 9, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 318, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #720 = CONST_V128_I16x8 { 719, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 316, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #719 = CONST_V128_F64x2_S { 718, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 313, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #718 = CONST_V128_F64x2 { 717, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 309, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #717 = CONST_V128_F32x4_S { 716, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 304, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #716 = CONST_V128_F32x4 { 715, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 303, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #715 = CONST_I64_S { 714, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 301, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #714 = CONST_I64 { 713, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 300, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #713 = CONST_I32_S { 712, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 298, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #712 = CONST_I32 { 711, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 297, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #711 = CONST_F64_S { 710, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 295, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #710 = CONST_F64 { 709, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 294, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #709 = CONST_F32_S { 708, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 292, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #708 = CONST_F32 { 707, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #707 = CLZ_I64_S { 706, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 290, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #706 = CLZ_I64 { 705, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #705 = CLZ_I32_S { 704, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 288, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #704 = CLZ_I32 { 703, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #703 = CEIL_F64x2_S { 702, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #702 = CEIL_F64x2 { 701, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #701 = CEIL_F64_S { 700, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 159, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #700 = CEIL_F64 { 699, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #699 = CEIL_F32x4_S { 698, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #698 = CEIL_F32x4 { 697, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #697 = CEIL_F32_S { 696, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 157, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #696 = CEIL_F32 { 695, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #695 = CEIL_F16x8_S { 694, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #694 = CEIL_F16x8 { 693, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 287, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x0ULL }, // Inst #693 = CATCH_S { 692, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #692 = CATCH_ALL_S { 691, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #691 = CATCH_ALL { 690, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 287, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x0ULL }, // Inst #690 = CATCH { 689, 1, 0, 0, 0, 2, 1, WebAssemblyImpOpBase + 0, 152, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x0ULL }, // Inst #689 = CALL_S { 688, 2, 0, 0, 0, 2, 1, WebAssemblyImpOpBase + 0, 285, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x0ULL }, // Inst #688 = CALL_INDIRECT_S { 687, 2, 0, 0, 0, 2, 1, WebAssemblyImpOpBase + 0, 285, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x0ULL }, // Inst #687 = CALL_INDIRECT { 686, 1, 0, 0, 0, 2, 1, WebAssemblyImpOpBase + 0, 152, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x0ULL }, // Inst #686 = CALL { 685, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 279, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #685 = BR_UNLESS_S { 684, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 280, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #684 = BR_UNLESS { 683, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 283, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #683 = BR_TABLE_I64_S { 682, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 284, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #682 = BR_TABLE_I64 { 681, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 283, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #681 = BR_TABLE_I32_S { 680, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 282, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #680 = BR_TABLE_I32 { 679, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 279, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #679 = BR_S { 678, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 279, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #678 = BR_IF_S { 677, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 280, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #677 = BR_IF { 676, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 279, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #676 = BR { 675, 1, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 8, 278, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #675 = BLOCK_S { 674, 1, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 8, 278, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #674 = BLOCK { 673, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #673 = BITSELECT_S { 672, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 274, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #672 = BITSELECT { 671, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #671 = BITMASK_I8x16_S { 670, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 176, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #670 = BITMASK_I8x16 { 669, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #669 = BITMASK_I64x2_S { 668, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 176, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #668 = BITMASK_I64x2 { 667, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #667 = BITMASK_I32x4_S { 666, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 176, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #666 = BITMASK_I32x4 { 665, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #665 = BITMASK_I16x8_S { 664, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 176, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #664 = BITMASK_I16x8 { 663, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #663 = AVGR_U_I8x16_S { 662, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #662 = AVGR_U_I8x16 { 661, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #661 = AVGR_U_I16x8_S { 660, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #660 = AVGR_U_I16x8 { 659, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #659 = ATOMIC_STORE_I64_A64_S { 658, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 270, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #658 = ATOMIC_STORE_I64_A64 { 657, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #657 = ATOMIC_STORE_I64_A32_S { 656, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 266, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #656 = ATOMIC_STORE_I64_A32 { 655, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #655 = ATOMIC_STORE_I32_A64_S { 654, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 262, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #654 = ATOMIC_STORE_I32_A64 { 653, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #653 = ATOMIC_STORE_I32_A32_S { 652, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 258, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #652 = ATOMIC_STORE_I32_A32 { 651, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #651 = ATOMIC_STORE8_I64_A64_S { 650, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 270, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #650 = ATOMIC_STORE8_I64_A64 { 649, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #649 = ATOMIC_STORE8_I64_A32_S { 648, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 266, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #648 = ATOMIC_STORE8_I64_A32 { 647, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #647 = ATOMIC_STORE8_I32_A64_S { 646, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 262, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #646 = ATOMIC_STORE8_I32_A64 { 645, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #645 = ATOMIC_STORE8_I32_A32_S { 644, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 258, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #644 = ATOMIC_STORE8_I32_A32 { 643, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #643 = ATOMIC_STORE32_I64_A64_S { 642, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 270, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #642 = ATOMIC_STORE32_I64_A64 { 641, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #641 = ATOMIC_STORE32_I64_A32_S { 640, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 266, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #640 = ATOMIC_STORE32_I64_A32 { 639, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #639 = ATOMIC_STORE16_I64_A64_S { 638, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 270, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #638 = ATOMIC_STORE16_I64_A64 { 637, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #637 = ATOMIC_STORE16_I64_A32_S { 636, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 266, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #636 = ATOMIC_STORE16_I64_A32 { 635, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #635 = ATOMIC_STORE16_I32_A64_S { 634, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 262, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #634 = ATOMIC_STORE16_I32_A64 { 633, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #633 = ATOMIC_STORE16_I32_A32_S { 632, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 258, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #632 = ATOMIC_STORE16_I32_A32 { 631, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #631 = ATOMIC_RMW_XOR_I64_A64_S { 630, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 229, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #630 = ATOMIC_RMW_XOR_I64_A64 { 629, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #629 = ATOMIC_RMW_XOR_I64_A32_S { 628, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 224, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #628 = ATOMIC_RMW_XOR_I64_A32 { 627, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #627 = ATOMIC_RMW_XOR_I32_A64_S { 626, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 219, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #626 = ATOMIC_RMW_XOR_I32_A64 { 625, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #625 = ATOMIC_RMW_XOR_I32_A32_S { 624, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 214, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #624 = ATOMIC_RMW_XOR_I32_A32 { 623, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #623 = ATOMIC_RMW_XCHG_I64_A64_S { 622, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 229, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #622 = ATOMIC_RMW_XCHG_I64_A64 { 621, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #621 = ATOMIC_RMW_XCHG_I64_A32_S { 620, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 224, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #620 = ATOMIC_RMW_XCHG_I64_A32 { 619, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #619 = ATOMIC_RMW_XCHG_I32_A64_S { 618, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 219, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #618 = ATOMIC_RMW_XCHG_I32_A64 { 617, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #617 = ATOMIC_RMW_XCHG_I32_A32_S { 616, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 214, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #616 = ATOMIC_RMW_XCHG_I32_A32 { 615, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #615 = ATOMIC_RMW_SUB_I64_A64_S { 614, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 229, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #614 = ATOMIC_RMW_SUB_I64_A64 { 613, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #613 = ATOMIC_RMW_SUB_I64_A32_S { 612, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 224, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #612 = ATOMIC_RMW_SUB_I64_A32 { 611, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #611 = ATOMIC_RMW_SUB_I32_A64_S { 610, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 219, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #610 = ATOMIC_RMW_SUB_I32_A64 { 609, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #609 = ATOMIC_RMW_SUB_I32_A32_S { 608, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 214, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #608 = ATOMIC_RMW_SUB_I32_A32 { 607, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #607 = ATOMIC_RMW_OR_I64_A64_S { 606, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 229, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #606 = ATOMIC_RMW_OR_I64_A64 { 605, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #605 = ATOMIC_RMW_OR_I64_A32_S { 604, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 224, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #604 = ATOMIC_RMW_OR_I64_A32 { 603, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #603 = ATOMIC_RMW_OR_I32_A64_S { 602, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 219, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #602 = ATOMIC_RMW_OR_I32_A64 { 601, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #601 = ATOMIC_RMW_OR_I32_A32_S { 600, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 214, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #600 = ATOMIC_RMW_OR_I32_A32 { 599, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #599 = ATOMIC_RMW_CMPXCHG_I64_A64_S { 598, 6, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 252, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #598 = ATOMIC_RMW_CMPXCHG_I64_A64 { 597, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #597 = ATOMIC_RMW_CMPXCHG_I64_A32_S { 596, 6, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 246, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #596 = ATOMIC_RMW_CMPXCHG_I64_A32 { 595, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #595 = ATOMIC_RMW_CMPXCHG_I32_A64_S { 594, 6, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 240, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #594 = ATOMIC_RMW_CMPXCHG_I32_A64 { 593, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #593 = ATOMIC_RMW_CMPXCHG_I32_A32_S { 592, 6, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 234, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #592 = ATOMIC_RMW_CMPXCHG_I32_A32 { 591, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #591 = ATOMIC_RMW_AND_I64_A64_S { 590, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 229, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #590 = ATOMIC_RMW_AND_I64_A64 { 589, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #589 = ATOMIC_RMW_AND_I64_A32_S { 588, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 224, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #588 = ATOMIC_RMW_AND_I64_A32 { 587, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #587 = ATOMIC_RMW_AND_I32_A64_S { 586, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 219, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #586 = ATOMIC_RMW_AND_I32_A64 { 585, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #585 = ATOMIC_RMW_AND_I32_A32_S { 584, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 214, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #584 = ATOMIC_RMW_AND_I32_A32 { 583, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #583 = ATOMIC_RMW_ADD_I64_A64_S { 582, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 229, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #582 = ATOMIC_RMW_ADD_I64_A64 { 581, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #581 = ATOMIC_RMW_ADD_I64_A32_S { 580, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 224, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #580 = ATOMIC_RMW_ADD_I64_A32 { 579, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #579 = ATOMIC_RMW_ADD_I32_A64_S { 578, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 219, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #578 = ATOMIC_RMW_ADD_I32_A64 { 577, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #577 = ATOMIC_RMW_ADD_I32_A32_S { 576, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 214, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #576 = ATOMIC_RMW_ADD_I32_A32 { 575, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #575 = ATOMIC_RMW8_U_XOR_I64_A64_S { 574, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 229, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #574 = ATOMIC_RMW8_U_XOR_I64_A64 { 573, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #573 = ATOMIC_RMW8_U_XOR_I64_A32_S { 572, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 224, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #572 = ATOMIC_RMW8_U_XOR_I64_A32 { 571, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #571 = ATOMIC_RMW8_U_XOR_I32_A64_S { 570, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 219, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #570 = ATOMIC_RMW8_U_XOR_I32_A64 { 569, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #569 = ATOMIC_RMW8_U_XOR_I32_A32_S { 568, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 214, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #568 = ATOMIC_RMW8_U_XOR_I32_A32 { 567, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #567 = ATOMIC_RMW8_U_XCHG_I64_A64_S { 566, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 229, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #566 = ATOMIC_RMW8_U_XCHG_I64_A64 { 565, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #565 = ATOMIC_RMW8_U_XCHG_I64_A32_S { 564, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 224, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #564 = ATOMIC_RMW8_U_XCHG_I64_A32 { 563, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #563 = ATOMIC_RMW8_U_XCHG_I32_A64_S { 562, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 219, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #562 = ATOMIC_RMW8_U_XCHG_I32_A64 { 561, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #561 = ATOMIC_RMW8_U_XCHG_I32_A32_S { 560, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 214, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #560 = ATOMIC_RMW8_U_XCHG_I32_A32 { 559, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #559 = ATOMIC_RMW8_U_SUB_I64_A64_S { 558, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 229, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #558 = ATOMIC_RMW8_U_SUB_I64_A64 { 557, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #557 = ATOMIC_RMW8_U_SUB_I64_A32_S { 556, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 224, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #556 = ATOMIC_RMW8_U_SUB_I64_A32 { 555, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #555 = ATOMIC_RMW8_U_SUB_I32_A64_S { 554, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 219, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #554 = ATOMIC_RMW8_U_SUB_I32_A64 { 553, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #553 = ATOMIC_RMW8_U_SUB_I32_A32_S { 552, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 214, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #552 = ATOMIC_RMW8_U_SUB_I32_A32 { 551, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #551 = ATOMIC_RMW8_U_OR_I64_A64_S { 550, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 229, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #550 = ATOMIC_RMW8_U_OR_I64_A64 { 549, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #549 = ATOMIC_RMW8_U_OR_I64_A32_S { 548, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 224, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #548 = ATOMIC_RMW8_U_OR_I64_A32 { 547, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #547 = ATOMIC_RMW8_U_OR_I32_A64_S { 546, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 219, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #546 = ATOMIC_RMW8_U_OR_I32_A64 { 545, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #545 = ATOMIC_RMW8_U_OR_I32_A32_S { 544, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 214, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #544 = ATOMIC_RMW8_U_OR_I32_A32 { 543, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #543 = ATOMIC_RMW8_U_CMPXCHG_I64_A64_S { 542, 6, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 252, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #542 = ATOMIC_RMW8_U_CMPXCHG_I64_A64 { 541, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #541 = ATOMIC_RMW8_U_CMPXCHG_I64_A32_S { 540, 6, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 246, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #540 = ATOMIC_RMW8_U_CMPXCHG_I64_A32 { 539, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #539 = ATOMIC_RMW8_U_CMPXCHG_I32_A64_S { 538, 6, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 240, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #538 = ATOMIC_RMW8_U_CMPXCHG_I32_A64 { 537, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #537 = ATOMIC_RMW8_U_CMPXCHG_I32_A32_S { 536, 6, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 234, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #536 = ATOMIC_RMW8_U_CMPXCHG_I32_A32 { 535, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #535 = ATOMIC_RMW8_U_AND_I64_A64_S { 534, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 229, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #534 = ATOMIC_RMW8_U_AND_I64_A64 { 533, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #533 = ATOMIC_RMW8_U_AND_I64_A32_S { 532, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 224, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #532 = ATOMIC_RMW8_U_AND_I64_A32 { 531, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #531 = ATOMIC_RMW8_U_AND_I32_A64_S { 530, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 219, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #530 = ATOMIC_RMW8_U_AND_I32_A64 { 529, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #529 = ATOMIC_RMW8_U_AND_I32_A32_S { 528, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 214, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #528 = ATOMIC_RMW8_U_AND_I32_A32 { 527, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #527 = ATOMIC_RMW8_U_ADD_I64_A64_S { 526, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 229, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #526 = ATOMIC_RMW8_U_ADD_I64_A64 { 525, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #525 = ATOMIC_RMW8_U_ADD_I64_A32_S { 524, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 224, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #524 = ATOMIC_RMW8_U_ADD_I64_A32 { 523, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #523 = ATOMIC_RMW8_U_ADD_I32_A64_S { 522, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 219, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #522 = ATOMIC_RMW8_U_ADD_I32_A64 { 521, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #521 = ATOMIC_RMW8_U_ADD_I32_A32_S { 520, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 214, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #520 = ATOMIC_RMW8_U_ADD_I32_A32 { 519, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #519 = ATOMIC_RMW32_U_XOR_I64_A64_S { 518, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 229, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #518 = ATOMIC_RMW32_U_XOR_I64_A64 { 517, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #517 = ATOMIC_RMW32_U_XOR_I64_A32_S { 516, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 224, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #516 = ATOMIC_RMW32_U_XOR_I64_A32 { 515, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #515 = ATOMIC_RMW32_U_XCHG_I64_A64_S { 514, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 229, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #514 = ATOMIC_RMW32_U_XCHG_I64_A64 { 513, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #513 = ATOMIC_RMW32_U_XCHG_I64_A32_S { 512, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 224, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #512 = ATOMIC_RMW32_U_XCHG_I64_A32 { 511, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #511 = ATOMIC_RMW32_U_SUB_I64_A64_S { 510, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 229, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #510 = ATOMIC_RMW32_U_SUB_I64_A64 { 509, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #509 = ATOMIC_RMW32_U_SUB_I64_A32_S { 508, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 224, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #508 = ATOMIC_RMW32_U_SUB_I64_A32 { 507, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #507 = ATOMIC_RMW32_U_OR_I64_A64_S { 506, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 229, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #506 = ATOMIC_RMW32_U_OR_I64_A64 { 505, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #505 = ATOMIC_RMW32_U_OR_I64_A32_S { 504, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 224, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #504 = ATOMIC_RMW32_U_OR_I64_A32 { 503, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #503 = ATOMIC_RMW32_U_CMPXCHG_I64_A64_S { 502, 6, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 252, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #502 = ATOMIC_RMW32_U_CMPXCHG_I64_A64 { 501, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #501 = ATOMIC_RMW32_U_CMPXCHG_I64_A32_S { 500, 6, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 246, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #500 = ATOMIC_RMW32_U_CMPXCHG_I64_A32 { 499, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #499 = ATOMIC_RMW32_U_AND_I64_A64_S { 498, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 229, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #498 = ATOMIC_RMW32_U_AND_I64_A64 { 497, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #497 = ATOMIC_RMW32_U_AND_I64_A32_S { 496, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 224, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #496 = ATOMIC_RMW32_U_AND_I64_A32 { 495, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #495 = ATOMIC_RMW32_U_ADD_I64_A64_S { 494, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 229, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #494 = ATOMIC_RMW32_U_ADD_I64_A64 { 493, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #493 = ATOMIC_RMW32_U_ADD_I64_A32_S { 492, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 224, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #492 = ATOMIC_RMW32_U_ADD_I64_A32 { 491, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #491 = ATOMIC_RMW16_U_XOR_I64_A64_S { 490, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 229, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #490 = ATOMIC_RMW16_U_XOR_I64_A64 { 489, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #489 = ATOMIC_RMW16_U_XOR_I64_A32_S { 488, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 224, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #488 = ATOMIC_RMW16_U_XOR_I64_A32 { 487, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #487 = ATOMIC_RMW16_U_XOR_I32_A64_S { 486, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 219, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #486 = ATOMIC_RMW16_U_XOR_I32_A64 { 485, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #485 = ATOMIC_RMW16_U_XOR_I32_A32_S { 484, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 214, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #484 = ATOMIC_RMW16_U_XOR_I32_A32 { 483, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #483 = ATOMIC_RMW16_U_XCHG_I64_A64_S { 482, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 229, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #482 = ATOMIC_RMW16_U_XCHG_I64_A64 { 481, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #481 = ATOMIC_RMW16_U_XCHG_I64_A32_S { 480, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 224, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #480 = ATOMIC_RMW16_U_XCHG_I64_A32 { 479, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #479 = ATOMIC_RMW16_U_XCHG_I32_A64_S { 478, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 219, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #478 = ATOMIC_RMW16_U_XCHG_I32_A64 { 477, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #477 = ATOMIC_RMW16_U_XCHG_I32_A32_S { 476, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 214, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #476 = ATOMIC_RMW16_U_XCHG_I32_A32 { 475, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #475 = ATOMIC_RMW16_U_SUB_I64_A64_S { 474, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 229, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #474 = ATOMIC_RMW16_U_SUB_I64_A64 { 473, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #473 = ATOMIC_RMW16_U_SUB_I64_A32_S { 472, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 224, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #472 = ATOMIC_RMW16_U_SUB_I64_A32 { 471, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #471 = ATOMIC_RMW16_U_SUB_I32_A64_S { 470, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 219, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #470 = ATOMIC_RMW16_U_SUB_I32_A64 { 469, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #469 = ATOMIC_RMW16_U_SUB_I32_A32_S { 468, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 214, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #468 = ATOMIC_RMW16_U_SUB_I32_A32 { 467, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #467 = ATOMIC_RMW16_U_OR_I64_A64_S { 466, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 229, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #466 = ATOMIC_RMW16_U_OR_I64_A64 { 465, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #465 = ATOMIC_RMW16_U_OR_I64_A32_S { 464, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 224, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #464 = ATOMIC_RMW16_U_OR_I64_A32 { 463, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #463 = ATOMIC_RMW16_U_OR_I32_A64_S { 462, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 219, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #462 = ATOMIC_RMW16_U_OR_I32_A64 { 461, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #461 = ATOMIC_RMW16_U_OR_I32_A32_S { 460, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 214, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #460 = ATOMIC_RMW16_U_OR_I32_A32 { 459, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #459 = ATOMIC_RMW16_U_CMPXCHG_I64_A64_S { 458, 6, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 252, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #458 = ATOMIC_RMW16_U_CMPXCHG_I64_A64 { 457, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #457 = ATOMIC_RMW16_U_CMPXCHG_I64_A32_S { 456, 6, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 246, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #456 = ATOMIC_RMW16_U_CMPXCHG_I64_A32 { 455, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #455 = ATOMIC_RMW16_U_CMPXCHG_I32_A64_S { 454, 6, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 240, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #454 = ATOMIC_RMW16_U_CMPXCHG_I32_A64 { 453, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #453 = ATOMIC_RMW16_U_CMPXCHG_I32_A32_S { 452, 6, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 234, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #452 = ATOMIC_RMW16_U_CMPXCHG_I32_A32 { 451, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #451 = ATOMIC_RMW16_U_AND_I64_A64_S { 450, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 229, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #450 = ATOMIC_RMW16_U_AND_I64_A64 { 449, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #449 = ATOMIC_RMW16_U_AND_I64_A32_S { 448, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 224, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #448 = ATOMIC_RMW16_U_AND_I64_A32 { 447, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #447 = ATOMIC_RMW16_U_AND_I32_A64_S { 446, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 219, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #446 = ATOMIC_RMW16_U_AND_I32_A64 { 445, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #445 = ATOMIC_RMW16_U_AND_I32_A32_S { 444, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 214, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #444 = ATOMIC_RMW16_U_AND_I32_A32 { 443, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #443 = ATOMIC_RMW16_U_ADD_I64_A64_S { 442, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 229, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #442 = ATOMIC_RMW16_U_ADD_I64_A64 { 441, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #441 = ATOMIC_RMW16_U_ADD_I64_A32_S { 440, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 224, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #440 = ATOMIC_RMW16_U_ADD_I64_A32 { 439, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #439 = ATOMIC_RMW16_U_ADD_I32_A64_S { 438, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 219, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #438 = ATOMIC_RMW16_U_ADD_I32_A64 { 437, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #437 = ATOMIC_RMW16_U_ADD_I32_A32_S { 436, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 214, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #436 = ATOMIC_RMW16_U_ADD_I32_A32 { 435, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #435 = ATOMIC_LOAD_I64_A64_S { 434, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 210, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #434 = ATOMIC_LOAD_I64_A64 { 433, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #433 = ATOMIC_LOAD_I64_A32_S { 432, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 206, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #432 = ATOMIC_LOAD_I64_A32 { 431, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #431 = ATOMIC_LOAD_I32_A64_S { 430, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 200, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #430 = ATOMIC_LOAD_I32_A64 { 429, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #429 = ATOMIC_LOAD_I32_A32_S { 428, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 194, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #428 = ATOMIC_LOAD_I32_A32 { 427, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #427 = ATOMIC_LOAD8_U_I64_A64_S { 426, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 210, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #426 = ATOMIC_LOAD8_U_I64_A64 { 425, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #425 = ATOMIC_LOAD8_U_I64_A32_S { 424, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 206, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #424 = ATOMIC_LOAD8_U_I64_A32 { 423, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #423 = ATOMIC_LOAD8_U_I32_A64_S { 422, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 200, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #422 = ATOMIC_LOAD8_U_I32_A64 { 421, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #421 = ATOMIC_LOAD8_U_I32_A32_S { 420, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 194, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #420 = ATOMIC_LOAD8_U_I32_A32 { 419, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #419 = ATOMIC_LOAD32_U_I64_A64_S { 418, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 210, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #418 = ATOMIC_LOAD32_U_I64_A64 { 417, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #417 = ATOMIC_LOAD32_U_I64_A32_S { 416, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 206, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #416 = ATOMIC_LOAD32_U_I64_A32 { 415, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #415 = ATOMIC_LOAD16_U_I64_A64_S { 414, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 210, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #414 = ATOMIC_LOAD16_U_I64_A64 { 413, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #413 = ATOMIC_LOAD16_U_I64_A32_S { 412, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 206, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #412 = ATOMIC_LOAD16_U_I64_A32 { 411, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #411 = ATOMIC_LOAD16_U_I32_A64_S { 410, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 200, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #410 = ATOMIC_LOAD16_U_I32_A64 { 409, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #409 = ATOMIC_LOAD16_U_I32_A32_S { 408, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 194, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #408 = ATOMIC_LOAD16_U_I32_A32 { 407, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #407 = ATOMIC_FENCE_S { 406, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #406 = ATOMIC_FENCE { 405, 1, 0, 0, 0, 1, 0, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #405 = ARGUMENT_v8i16_S { 404, 2, 1, 0, 0, 1, 0, WebAssemblyImpOpBase + 3, 192, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #404 = ARGUMENT_v8i16 { 403, 1, 0, 0, 0, 1, 0, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #403 = ARGUMENT_v8f16_S { 402, 2, 1, 0, 0, 1, 0, WebAssemblyImpOpBase + 3, 192, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #402 = ARGUMENT_v8f16 { 401, 1, 0, 0, 0, 1, 0, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #401 = ARGUMENT_v4i32_S { 400, 2, 1, 0, 0, 1, 0, WebAssemblyImpOpBase + 3, 192, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #400 = ARGUMENT_v4i32 { 399, 1, 0, 0, 0, 1, 0, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #399 = ARGUMENT_v4f32_S { 398, 2, 1, 0, 0, 1, 0, WebAssemblyImpOpBase + 3, 192, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #398 = ARGUMENT_v4f32 { 397, 1, 0, 0, 0, 1, 0, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #397 = ARGUMENT_v2i64_S { 396, 2, 1, 0, 0, 1, 0, WebAssemblyImpOpBase + 3, 192, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #396 = ARGUMENT_v2i64 { 395, 1, 0, 0, 0, 1, 0, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #395 = ARGUMENT_v2f64_S { 394, 2, 1, 0, 0, 1, 0, WebAssemblyImpOpBase + 3, 192, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #394 = ARGUMENT_v2f64 { 393, 1, 0, 0, 0, 1, 0, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #393 = ARGUMENT_v16i8_S { 392, 2, 1, 0, 0, 1, 0, WebAssemblyImpOpBase + 3, 192, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #392 = ARGUMENT_v16i8 { 391, 1, 0, 0, 0, 1, 0, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #391 = ARGUMENT_i64_S { 390, 2, 1, 0, 0, 1, 0, WebAssemblyImpOpBase + 3, 190, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #390 = ARGUMENT_i64 { 389, 1, 0, 0, 0, 1, 0, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #389 = ARGUMENT_i32_S { 388, 2, 1, 0, 0, 1, 0, WebAssemblyImpOpBase + 3, 188, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #388 = ARGUMENT_i32 { 387, 1, 0, 0, 0, 1, 0, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #387 = ARGUMENT_funcref_S { 386, 2, 1, 0, 0, 1, 0, WebAssemblyImpOpBase + 3, 186, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #386 = ARGUMENT_funcref { 385, 1, 0, 0, 0, 1, 0, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #385 = ARGUMENT_f64_S { 384, 2, 1, 0, 0, 1, 0, WebAssemblyImpOpBase + 3, 184, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #384 = ARGUMENT_f64 { 383, 1, 0, 0, 0, 1, 0, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #383 = ARGUMENT_f32_S { 382, 2, 1, 0, 0, 1, 0, WebAssemblyImpOpBase + 3, 182, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #382 = ARGUMENT_f32 { 381, 1, 0, 0, 0, 1, 0, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #381 = ARGUMENT_externref_S { 380, 2, 1, 0, 0, 1, 0, WebAssemblyImpOpBase + 3, 180, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #380 = ARGUMENT_externref { 379, 1, 0, 0, 0, 1, 0, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #379 = ARGUMENT_exnref_S { 378, 2, 1, 0, 0, 1, 0, WebAssemblyImpOpBase + 3, 178, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #378 = ARGUMENT_exnref { 377, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #377 = ANYTRUE_S { 376, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 176, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #376 = ANYTRUE { 375, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #375 = AND_S { 374, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #374 = AND_I64_S { 373, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 173, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #373 = AND_I64 { 372, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #372 = AND_I32_S { 371, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 170, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #371 = AND_I32 { 370, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #370 = ANDNOT_S { 369, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #369 = ANDNOT { 368, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #368 = AND { 367, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #367 = ALLTRUE_I8x16_S { 366, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 176, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #366 = ALLTRUE_I8x16 { 365, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #365 = ALLTRUE_I64x2_S { 364, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 176, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #364 = ALLTRUE_I64x2 { 363, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #363 = ALLTRUE_I32x4_S { 362, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 176, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #362 = ALLTRUE_I32x4 { 361, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #361 = ALLTRUE_I16x8_S { 360, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 176, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #360 = ALLTRUE_I16x8 { 359, 2, 0, 0, 0, 2, 2, WebAssemblyImpOpBase + 4, 21, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #359 = ADJCALLSTACKUP_S { 358, 2, 0, 0, 0, 2, 2, WebAssemblyImpOpBase + 4, 21, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #358 = ADJCALLSTACKUP { 357, 2, 0, 0, 0, 2, 2, WebAssemblyImpOpBase + 4, 21, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #357 = ADJCALLSTACKDOWN_S { 356, 2, 0, 0, 0, 2, 2, WebAssemblyImpOpBase + 4, 21, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #356 = ADJCALLSTACKDOWN { 355, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #355 = ADD_SAT_U_I8x16_S { 354, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #354 = ADD_SAT_U_I8x16 { 353, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #353 = ADD_SAT_U_I16x8_S { 352, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #352 = ADD_SAT_U_I16x8 { 351, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #351 = ADD_SAT_S_I8x16_S { 350, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #350 = ADD_SAT_S_I8x16 { 349, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #349 = ADD_SAT_S_I16x8_S { 348, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #348 = ADD_SAT_S_I16x8 { 347, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #347 = ADD_I8x16_S { 346, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #346 = ADD_I8x16 { 345, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #345 = ADD_I64x2_S { 344, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #344 = ADD_I64x2 { 343, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #343 = ADD_I64_S { 342, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 173, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #342 = ADD_I64 { 341, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #341 = ADD_I32x4_S { 340, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #340 = ADD_I32x4 { 339, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #339 = ADD_I32_S { 338, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 170, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #338 = ADD_I32 { 337, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #337 = ADD_I16x8_S { 336, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #336 = ADD_I16x8 { 335, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #335 = ADD_F64x2_S { 334, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #334 = ADD_F64x2 { 333, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #333 = ADD_F64_S { 332, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 167, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #332 = ADD_F64 { 331, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #331 = ADD_F32x4_S { 330, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #330 = ADD_F32x4 { 329, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #329 = ADD_F32_S { 328, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 164, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #328 = ADD_F32 { 327, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #327 = ADD_F16x8_S { 326, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #326 = ADD_F16x8 { 325, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #325 = ABS_I8x16_S { 324, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #324 = ABS_I8x16 { 323, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #323 = ABS_I64x2_S { 322, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #322 = ABS_I64x2 { 321, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #321 = ABS_I32x4_S { 320, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #320 = ABS_I32x4 { 319, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #319 = ABS_I16x8_S { 318, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #318 = ABS_I16x8 { 317, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #317 = ABS_F64x2_S { 316, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #316 = ABS_F64x2 { 315, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #315 = ABS_F64_S { 314, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 159, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #314 = ABS_F64 { 313, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #313 = ABS_F32x4_S { 312, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #312 = ABS_F32x4 { 311, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #311 = ABS_F32_S { 310, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 157, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #310 = ABS_F32 { 309, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #309 = ABS_F16x8_S { 308, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #308 = ABS_F16x8 { 307, 0, 0, 0, 0, 2, 1, WebAssemblyImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x0ULL }, // Inst #307 = RET_CALL_RESULTS_S { 306, 0, 0, 0, 0, 2, 1, WebAssemblyImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x0ULL }, // Inst #306 = RET_CALL_RESULTS { 305, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #305 = COMPILER_FENCE_S { 304, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #304 = COMPILER_FENCE { 303, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::EHScopeReturn)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #303 = CLEANUPRET_S { 302, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::EHScopeReturn)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #302 = CLEANUPRET { 301, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 153, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::EHScopeReturn)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #301 = CATCHRET_S { 300, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 153, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::EHScopeReturn)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #300 = CATCHRET { 299, 0, 0, 0, 0, 2, 1, WebAssemblyImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x0ULL }, // Inst #299 = CALL_RESULTS_S { 298, 0, 0, 0, 0, 2, 1, WebAssemblyImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x0ULL }, // Inst #298 = CALL_RESULTS { 297, 1, 0, 0, 0, 2, 1, WebAssemblyImpOpBase + 0, 152, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #297 = CALL_PARAMS_S { 296, 1, 0, 0, 0, 2, 1, WebAssemblyImpOpBase + 0, 152, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #296 = CALL_PARAMS { 295, 4, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 148, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #295 = G_UBFX { 294, 4, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 148, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #294 = G_SBFX { 293, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #293 = G_VECREDUCE_UMIN { 292, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #292 = G_VECREDUCE_UMAX { 291, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #291 = G_VECREDUCE_SMIN { 290, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #290 = G_VECREDUCE_SMAX { 289, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #289 = G_VECREDUCE_XOR { 288, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #288 = G_VECREDUCE_OR { 287, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #287 = G_VECREDUCE_AND { 286, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #286 = G_VECREDUCE_MUL { 285, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #285 = G_VECREDUCE_ADD { 284, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #284 = G_VECREDUCE_FMINIMUM { 283, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #283 = G_VECREDUCE_FMAXIMUM { 282, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #282 = G_VECREDUCE_FMIN { 281, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #281 = G_VECREDUCE_FMAX { 280, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #280 = G_VECREDUCE_FMUL { 279, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #279 = G_VECREDUCE_FADD { 278, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 131, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #278 = G_VECREDUCE_SEQ_FMUL { 277, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 131, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #277 = G_VECREDUCE_SEQ_FADD { 276, 1, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 1, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #276 = G_UBSANTRAP { 275, 0, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 1, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #275 = G_DEBUGTRAP { 274, 0, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 1, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #274 = G_TRAP { 273, 3, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 58, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #273 = G_BZERO { 272, 4, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 144, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #272 = G_MEMSET { 271, 4, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 144, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #271 = G_MEMMOVE { 270, 3, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 131, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #270 = G_MEMCPY_INLINE { 269, 4, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 144, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #269 = G_MEMCPY { 268, 2, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 142, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #268 = G_WRITE_REGISTER { 267, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #267 = G_READ_REGISTER { 266, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #266 = G_STRICT_FLDEXP { 265, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #265 = G_STRICT_FSQRT { 264, 4, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 46, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #264 = G_STRICT_FMA { 263, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #263 = G_STRICT_FREM { 262, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #262 = G_STRICT_FDIV { 261, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #261 = G_STRICT_FMUL { 260, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #260 = G_STRICT_FSUB { 259, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #259 = G_STRICT_FADD { 258, 1, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #258 = G_STACKRESTORE { 257, 1, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #257 = G_STACKSAVE { 256, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 69, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #256 = G_DYN_STACKALLOC { 255, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #255 = G_JUMP_TABLE { 254, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #254 = G_BLOCK_ADDR { 253, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #253 = G_ADDRSPACE_CAST { 252, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #252 = G_FNEARBYINT { 251, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #251 = G_FRINT { 250, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #250 = G_FFLOOR { 249, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #249 = G_FSQRT { 248, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #248 = G_FTANH { 247, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #247 = G_FSINH { 246, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #246 = G_FCOSH { 245, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #245 = G_FATAN { 244, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #244 = G_FASIN { 243, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #243 = G_FACOS { 242, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #242 = G_FTAN { 241, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #241 = G_FSIN { 240, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #240 = G_FCOS { 239, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #239 = G_FCEIL { 238, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #238 = G_BITREVERSE { 237, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #237 = G_BSWAP { 236, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #236 = G_CTPOP { 235, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #235 = G_CTLZ_ZERO_UNDEF { 234, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #234 = G_CTLZ { 233, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #233 = G_CTTZ_ZERO_UNDEF { 232, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #232 = G_CTTZ { 231, 4, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 138, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #231 = G_VECTOR_COMPRESS { 230, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #230 = G_SPLAT_VECTOR { 229, 4, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 134, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #229 = G_SHUFFLE_VECTOR { 228, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 131, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #228 = G_EXTRACT_VECTOR_ELT { 227, 4, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 127, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #227 = G_INSERT_VECTOR_ELT { 226, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 40, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #226 = G_EXTRACT_SUBVECTOR { 225, 4, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 63, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #225 = G_INSERT_SUBVECTOR { 224, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #224 = G_VSCALE { 223, 3, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 124, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #223 = G_BRJT { 222, 1, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #222 = G_BR { 221, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #221 = G_LLROUND { 220, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #220 = G_LROUND { 219, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #219 = G_ABS { 218, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #218 = G_UMAX { 217, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #217 = G_UMIN { 216, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #216 = G_SMAX { 215, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #215 = G_SMIN { 214, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #214 = G_PTRMASK { 213, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #213 = G_PTR_ADD { 212, 0, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 1, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #212 = G_RESET_FPMODE { 211, 1, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #211 = G_SET_FPMODE { 210, 1, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #210 = G_GET_FPMODE { 209, 0, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 1, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #209 = G_RESET_FPENV { 208, 1, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #208 = G_SET_FPENV { 207, 1, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #207 = G_GET_FPENV { 206, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #206 = G_FMAXIMUM { 205, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #205 = G_FMINIMUM { 204, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #204 = G_FMAXNUM_IEEE { 203, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #203 = G_FMINNUM_IEEE { 202, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #202 = G_FMAXNUM { 201, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #201 = G_FMINNUM { 200, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #200 = G_FCANONICALIZE { 199, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 98, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #199 = G_IS_FPCLASS { 198, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #198 = G_FCOPYSIGN { 197, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #197 = G_FABS { 196, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #196 = G_UITOFP { 195, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #195 = G_SITOFP { 194, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #194 = G_FPTOUI { 193, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #193 = G_FPTOSI { 192, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #192 = G_FPTRUNC { 191, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #191 = G_FPEXT { 190, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #190 = G_FNEG { 189, 3, 2, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #189 = G_FFREXP { 188, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #188 = G_FLDEXP { 187, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #187 = G_FLOG10 { 186, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #186 = G_FLOG2 { 185, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #185 = G_FLOG { 184, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #184 = G_FEXP10 { 183, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #183 = G_FEXP2 { 182, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #182 = G_FEXP { 181, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #181 = G_FPOWI { 180, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #180 = G_FPOW { 179, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #179 = G_FREM { 178, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #178 = G_FDIV { 177, 4, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 46, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #177 = G_FMAD { 176, 4, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 46, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #176 = G_FMA { 175, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #175 = G_FMUL { 174, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #174 = G_FSUB { 173, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #173 = G_FADD { 172, 4, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #172 = G_UDIVFIXSAT { 171, 4, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #171 = G_SDIVFIXSAT { 170, 4, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #170 = G_UDIVFIX { 169, 4, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #169 = G_SDIVFIX { 168, 4, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #168 = G_UMULFIXSAT { 167, 4, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #167 = G_SMULFIXSAT { 166, 4, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #166 = G_UMULFIX { 165, 4, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #165 = G_SMULFIX { 164, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #164 = G_SSHLSAT { 163, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #163 = G_USHLSAT { 162, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #162 = G_SSUBSAT { 161, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #161 = G_USUBSAT { 160, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #160 = G_SADDSAT { 159, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #159 = G_UADDSAT { 158, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #158 = G_SMULH { 157, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #157 = G_UMULH { 156, 4, 2, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #156 = G_SMULO { 155, 4, 2, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #155 = G_UMULO { 154, 5, 2, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 115, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #154 = G_SSUBE { 153, 4, 2, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #153 = G_SSUBO { 152, 5, 2, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 115, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #152 = G_SADDE { 151, 4, 2, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #151 = G_SADDO { 150, 5, 2, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 115, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #150 = G_USUBE { 149, 4, 2, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #149 = G_USUBO { 148, 5, 2, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 115, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #148 = G_UADDE { 147, 4, 2, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #147 = G_UADDO { 146, 4, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #146 = G_SELECT { 145, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 112, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #145 = G_UCMP { 144, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 112, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #144 = G_SCMP { 143, 4, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 108, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #143 = G_FCMP { 142, 4, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 108, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #142 = G_ICMP { 141, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #141 = G_ROTL { 140, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #140 = G_ROTR { 139, 4, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 104, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #139 = G_FSHR { 138, 4, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 104, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #138 = G_FSHL { 137, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #137 = G_ASHR { 136, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #136 = G_LSHR { 135, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #135 = G_SHL { 134, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #134 = G_ZEXT { 133, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 40, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #133 = G_SEXT_INREG { 132, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #132 = G_SEXT { 131, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 98, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #131 = G_VAARG { 130, 1, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #130 = G_VASTART { 129, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #129 = G_FCONSTANT { 128, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #128 = G_CONSTANT { 127, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #127 = G_TRUNC { 126, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #126 = G_ANYEXT { 125, 1, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #125 = G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS { 124, 1, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #124 = G_INTRINSIC_CONVERGENT { 123, 1, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #123 = G_INTRINSIC_W_SIDE_EFFECTS { 122, 1, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #122 = G_INTRINSIC { 121, 0, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 1, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #121 = G_INVOKE_REGION_START { 120, 1, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #120 = G_BRINDIRECT { 119, 2, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #119 = G_BRCOND { 118, 4, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 94, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #118 = G_PREFETCH { 117, 2, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 21, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #117 = G_FENCE { 116, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #116 = G_ATOMICRMW_UDEC_WRAP { 115, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #115 = G_ATOMICRMW_UINC_WRAP { 114, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #114 = G_ATOMICRMW_FMIN { 113, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #113 = G_ATOMICRMW_FMAX { 112, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #112 = G_ATOMICRMW_FSUB { 111, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #111 = G_ATOMICRMW_FADD { 110, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #110 = G_ATOMICRMW_UMIN { 109, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #109 = G_ATOMICRMW_UMAX { 108, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #108 = G_ATOMICRMW_MIN { 107, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #107 = G_ATOMICRMW_MAX { 106, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #106 = G_ATOMICRMW_XOR { 105, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #105 = G_ATOMICRMW_OR { 104, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #104 = G_ATOMICRMW_NAND { 103, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #103 = G_ATOMICRMW_AND { 102, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #102 = G_ATOMICRMW_SUB { 101, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #101 = G_ATOMICRMW_ADD { 100, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #100 = G_ATOMICRMW_XCHG { 99, 4, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #99 = G_ATOMIC_CMPXCHG { 98, 5, 2, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 82, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #98 = G_ATOMIC_CMPXCHG_WITH_SUCCESS { 97, 5, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 77, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #97 = G_INDEXED_STORE { 96, 2, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #96 = G_STORE { 95, 5, 2, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 72, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #95 = G_INDEXED_ZEXTLOAD { 94, 5, 2, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 72, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #94 = G_INDEXED_SEXTLOAD { 93, 5, 2, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 72, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #93 = G_INDEXED_LOAD { 92, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #92 = G_ZEXTLOAD { 91, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #91 = G_SEXTLOAD { 90, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #90 = G_LOAD { 89, 1, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #89 = G_READSTEADYCOUNTER { 88, 1, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #88 = G_READCYCLECOUNTER { 87, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #87 = G_INTRINSIC_ROUNDEVEN { 86, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #86 = G_INTRINSIC_LLRINT { 85, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #85 = G_INTRINSIC_LRINT { 84, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #84 = G_INTRINSIC_ROUND { 83, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #83 = G_INTRINSIC_TRUNC { 82, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 69, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #82 = G_INTRINSIC_FPTRUNC_ROUND { 81, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #81 = G_CONSTANT_FOLD_BARRIER { 80, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #80 = G_FREEZE { 79, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #79 = G_BITCAST { 78, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #78 = G_INTTOPTR { 77, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #77 = G_PTRTOINT { 76, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #76 = G_CONCAT_VECTORS { 75, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #75 = G_BUILD_VECTOR_TRUNC { 74, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #74 = G_BUILD_VECTOR { 73, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #73 = G_MERGE_VALUES { 72, 4, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 63, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #72 = G_INSERT { 71, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #71 = G_UNMERGE_VALUES { 70, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 58, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #70 = G_EXTRACT { 69, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #69 = G_CONSTANT_POOL { 68, 5, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 53, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #68 = G_PTRAUTH_GLOBAL_VALUE { 67, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #67 = G_GLOBAL_VALUE { 66, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #66 = G_FRAME_INDEX { 65, 1, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #65 = G_PHI { 64, 1, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #64 = G_IMPLICIT_DEF { 63, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #63 = G_XOR { 62, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #62 = G_OR { 61, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #61 = G_AND { 60, 4, 2, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 46, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #60 = G_UDIVREM { 59, 4, 2, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 46, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #59 = G_SDIVREM { 58, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #58 = G_UREM { 57, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #57 = G_SREM { 56, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #56 = G_UDIV { 55, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #55 = G_SDIV { 54, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #54 = G_MUL { 53, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #53 = G_SUB { 52, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #52 = G_ADD { 51, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 40, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #51 = G_ASSERT_ALIGN { 50, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 40, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #50 = G_ASSERT_ZEXT { 49, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 40, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #49 = G_ASSERT_SEXT { 48, 1, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #48 = CONVERGENCECTRL_GLUE { 47, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 13, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #47 = CONVERGENCECTRL_LOOP { 46, 1, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #46 = CONVERGENCECTRL_ANCHOR { 45, 1, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #45 = CONVERGENCECTRL_ENTRY { 44, 1, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #44 = JUMP_TABLE_DEBUG_INFO { 43, 0, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #43 = MEMBARRIER { 42, 0, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #42 = FAKE_USE { 41, 0, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #41 = ICALL_BRANCH_FUNNEL { 40, 3, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 37, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #40 = PATCHABLE_TYPED_EVENT_CALL { 39, 2, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 35, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #39 = PATCHABLE_EVENT_CALL { 38, 0, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #38 = PATCHABLE_TAIL_CALL { 37, 0, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #37 = PATCHABLE_FUNCTION_EXIT { 36, 0, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #36 = PATCHABLE_RET { 35, 0, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #35 = PATCHABLE_FUNCTION_ENTER { 34, 0, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #34 = PATCHABLE_OP { 33, 1, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #33 = FAULTING_OP { 32, 2, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 33, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #32 = LOCAL_ESCAPE { 31, 0, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #31 = STATEPOINT { 30, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 30, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #30 = PREALLOCATED_ARG { 29, 1, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #29 = PREALLOCATED_SETUP { 28, 1, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 29, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #28 = LOAD_STACK_GUARD { 27, 6, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 23, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #27 = PATCHPOINT { 26, 0, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #26 = FENTRY_CALL { 25, 2, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 21, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #25 = STACKMAP { 24, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 19, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #24 = ARITH_FENCE { 23, 4, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 15, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #23 = PSEUDO_PROBE { 22, 1, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #22 = LIFETIME_END { 21, 1, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #21 = LIFETIME_START { 20, 0, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #20 = BUNDLE { 19, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 13, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #19 = COPY { 18, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 13, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #18 = REG_SEQUENCE { 17, 1, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #17 = DBG_LABEL { 16, 0, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #16 = DBG_PHI { 15, 0, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #15 = DBG_INSTR_REF { 14, 0, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #14 = DBG_VALUE_LIST { 13, 0, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #13 = DBG_VALUE { 12, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #12 = COPY_TO_REGCLASS { 11, 4, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 9, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #11 = SUBREG_TO_REG { 10, 1, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #10 = IMPLICIT_DEF { 9, 4, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 5, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #9 = INSERT_SUBREG { 8, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #8 = EXTRACT_SUBREG { 7, 0, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #7 = KILL { 6, 1, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #6 = ANNOTATION_LABEL { 5, 1, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #5 = GC_LABEL { 4, 1, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #4 = EH_LABEL { 3, 1, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #3 = CFI_INSTRUCTION { 2, 0, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #2 = INLINEASM_BR { 1, 0, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1 = INLINEASM { 0, 1, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #0 = PHI }, { /* 0 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 1 */ /* 1 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, /* 2 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, /* 5 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, /* 9 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, /* 13 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 15 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, /* 19 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) }, /* 21 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, /* 23 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, /* 29 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, /* 30 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, /* 33 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, /* 35 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 37 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 40 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 }, /* 43 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, /* 46 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, /* 50 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, /* 51 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 53 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, /* 58 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 }, /* 61 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, /* 63 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 }, /* 67 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, /* 69 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, /* 72 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 77 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 82 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, /* 87 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, /* 91 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, /* 94 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, /* 98 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 101 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, /* 104 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, /* 108 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, /* 112 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, /* 115 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, /* 120 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 }, /* 124 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, /* 127 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, /* 131 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, /* 134 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, /* 138 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, /* 142 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, /* 144 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 }, /* 148 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, /* 152 */ { -1, 0, WebAssembly::OPERAND_FUNCTION32, 0 }, /* 153 */ { -1, 0, WebAssembly::OPERAND_BASIC_BLOCK, 0 }, { -1, 0, WebAssembly::OPERAND_BASIC_BLOCK, 0 }, /* 155 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 157 */ { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 159 */ { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 161 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 164 */ { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 167 */ { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 170 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 173 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 176 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 178 */ { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, /* 180 */ { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, /* 182 */ { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, /* 184 */ { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, /* 186 */ { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, /* 188 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, /* 190 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, /* 192 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, /* 194 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 198 */ { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, /* 200 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 204 */ { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, /* 206 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 210 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 214 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 219 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 224 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 229 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 234 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 240 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 246 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 252 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 258 */ { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 262 */ { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 266 */ { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 270 */ { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 274 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 278 */ { -1, 0, WebAssembly::OPERAND_SIGNATURE, 0 }, /* 279 */ { -1, 0, WebAssembly::OPERAND_BASIC_BLOCK, 0 }, /* 280 */ { -1, 0, WebAssembly::OPERAND_BASIC_BLOCK, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 282 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 283 */ { -1, 0, WebAssembly::OPERAND_BRLIST, 0 }, /* 284 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 285 */ { -1, 0, WebAssembly::OPERAND_TYPEINDEX, 0 }, { -1, 0, WebAssembly::OPERAND_TABLE, 0 }, /* 287 */ { -1, 0, WebAssembly::OPERAND_TAG, 0 }, /* 288 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 290 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 292 */ { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_F32IMM, 0 }, /* 294 */ { -1, 0, WebAssembly::OPERAND_F32IMM, 0 }, /* 295 */ { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_F64IMM, 0 }, /* 297 */ { -1, 0, WebAssembly::OPERAND_F64IMM, 0 }, /* 298 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_I32IMM, 0 }, /* 300 */ { -1, 0, WebAssembly::OPERAND_I32IMM, 0 }, /* 301 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_I64IMM, 0 }, /* 303 */ { -1, 0, WebAssembly::OPERAND_I64IMM, 0 }, /* 304 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_F32IMM, 0 }, { -1, 0, WebAssembly::OPERAND_F32IMM, 0 }, { -1, 0, WebAssembly::OPERAND_F32IMM, 0 }, { -1, 0, WebAssembly::OPERAND_F32IMM, 0 }, /* 309 */ { -1, 0, WebAssembly::OPERAND_F32IMM, 0 }, { -1, 0, WebAssembly::OPERAND_F32IMM, 0 }, { -1, 0, WebAssembly::OPERAND_F32IMM, 0 }, { -1, 0, WebAssembly::OPERAND_F32IMM, 0 }, /* 313 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_F64IMM, 0 }, { -1, 0, WebAssembly::OPERAND_F64IMM, 0 }, /* 316 */ { -1, 0, WebAssembly::OPERAND_F64IMM, 0 }, { -1, 0, WebAssembly::OPERAND_F64IMM, 0 }, /* 318 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I16IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I16IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I16IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I16IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I16IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I16IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I16IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I16IMM, 0 }, /* 327 */ { -1, 0, WebAssembly::OPERAND_VEC_I16IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I16IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I16IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I16IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I16IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I16IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I16IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I16IMM, 0 }, /* 335 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I32IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I32IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I32IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I32IMM, 0 }, /* 340 */ { -1, 0, WebAssembly::OPERAND_VEC_I32IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I32IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I32IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I32IMM, 0 }, /* 344 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I64IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I64IMM, 0 }, /* 347 */ { -1, 0, WebAssembly::OPERAND_VEC_I64IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I64IMM, 0 }, /* 349 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, /* 366 */ { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, /* 382 */ { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 384 */ { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 386 */ { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 388 */ { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 389 */ { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 390 */ { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 391 */ { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 392 */ { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 393 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 394 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 396 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 399 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 402 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 405 */ { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, /* 408 */ { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, /* 409 */ { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, /* 412 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, /* 415 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, /* 418 */ { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 420 */ { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 422 */ { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 424 */ { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 426 */ { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 428 */ { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 430 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 432 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 434 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 436 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 438 */ { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 }, /* 440 */ { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 }, /* 441 */ { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 }, /* 443 */ { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 }, /* 445 */ { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 }, /* 447 */ { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 }, /* 449 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 }, /* 451 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 }, /* 453 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 }, /* 455 */ { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 }, { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 457 */ { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 }, { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 459 */ { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 461 */ { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 463 */ { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 }, { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 465 */ { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 467 */ { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 469 */ { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 471 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 473 */ { -1, 0, WebAssembly::OPERAND_SIGNATURE, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 475 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 479 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 483 */ { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 487 */ { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 491 */ { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 495 */ { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 499 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 505 */ { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, /* 508 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 514 */ { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, /* 517 */ { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, /* 519 */ { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, /* 520 */ { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, /* 522 */ { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, /* 524 */ { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, /* 526 */ { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, /* 528 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, /* 530 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, /* 532 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, /* 534 */ { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 536 */ { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 538 */ { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 540 */ { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 542 */ { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 544 */ { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 546 */ { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 548 */ { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 550 */ { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 553 */ { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 556 */ { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 559 */ { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 562 */ { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 565 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 568 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 571 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 574 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 580 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 586 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 592 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 598 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 600 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 602 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 604 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 608 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 612 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 616 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 620 */ { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 624 */ { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 628 */ { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 632 */ { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 636 */ { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 640 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 644 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 648 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 652 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 655 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, /* 674 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 676 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 678 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 680 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 682 */ { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 686 */ { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 690 */ { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 694 */ { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 698 */ { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 703 */ { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 708 */ { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 712 */ { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 716 */ { -1, 0, WebAssembly::OPERAND_TABLE, 0 }, { -1, 0, WebAssembly::OPERAND_TABLE, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 721 */ { -1, 0, WebAssembly::OPERAND_TABLE, 0 }, { -1, 0, WebAssembly::OPERAND_TABLE, 0 }, /* 723 */ { -1, 0, WebAssembly::OPERAND_TABLE, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 727 */ { -1, 0, WebAssembly::OPERAND_TABLE, 0 }, /* 728 */ { -1, 0, WebAssembly::OPERAND_TABLE, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 732 */ { -1, 0, WebAssembly::OPERAND_TABLE, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 736 */ { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_TABLE, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 739 */ { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_TABLE, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 742 */ { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_TABLE, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 745 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_TABLE, 0 }, { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 749 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_TABLE, 0 }, { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 753 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_TABLE, 0 }, { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 757 */ { -1, 0, WebAssembly::OPERAND_TABLE, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 760 */ { -1, 0, WebAssembly::OPERAND_TABLE, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 763 */ { -1, 0, WebAssembly::OPERAND_TABLE, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 766 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_TABLE, 0 }, /* 768 */ { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 771 */ { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 774 */ { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 777 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 780 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 783 */ { -1, 0, WebAssembly::OPERAND_I32IMM, 0 }, { -1, 0, WebAssembly::OPERAND_I32IMM, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 788 */ { -1, 0, WebAssembly::OPERAND_I32IMM, 0 }, { -1, 0, WebAssembly::OPERAND_I32IMM, 0 }, /* 790 */ { -1, 0, WebAssembly::OPERAND_I32IMM, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 794 */ { -1, 0, WebAssembly::OPERAND_I32IMM, 0 }, { -1, 0, WebAssembly::OPERAND_I32IMM, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 799 */ { -1, 0, WebAssembly::OPERAND_I32IMM, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, /* 803 */ { -1, 0, WebAssembly::OPERAND_I32IMM, 0 }, { -1, 0, WebAssembly::OPERAND_I32IMM, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }, { /* 0 */ /* 0 */ WebAssembly::SP32, WebAssembly::SP64, WebAssembly::ARGUMENTS, /* 3 */ WebAssembly::ARGUMENTS, /* 4 */ WebAssembly::SP32, WebAssembly::SP64, WebAssembly::SP32, WebAssembly::SP64, /* 8 */ WebAssembly::VALUE_STACK, WebAssembly::VALUE_STACK, } }; #ifdef __GNUC__ #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Woverlength-strings" #endif extern const char WebAssemblyInstrNameData[] = { /* 0 */ "G_FLOG10\0" /* 9 */ "G_FEXP10\0" /* 18 */ "LOAD_F16_F32_A32\0" /* 35 */ "STORE_F16_F32_A32\0" /* 53 */ "LOAD_F32_A32\0" /* 66 */ "STORE_F32_A32\0" /* 80 */ "ATOMIC_STORE16_I32_A32\0" /* 103 */ "ATOMIC_STORE8_I32_A32\0" /* 125 */ "ATOMIC_RMW16_U_SUB_I32_A32\0" /* 152 */ "ATOMIC_RMW8_U_SUB_I32_A32\0" /* 178 */ "ATOMIC_RMW_SUB_I32_A32\0" /* 201 */ "ATOMIC_LOAD_I32_A32\0" /* 221 */ "ATOMIC_RMW16_U_ADD_I32_A32\0" /* 248 */ "ATOMIC_RMW8_U_ADD_I32_A32\0" /* 274 */ "ATOMIC_RMW_ADD_I32_A32\0" /* 297 */ "ATOMIC_RMW16_U_AND_I32_A32\0" /* 324 */ "ATOMIC_RMW8_U_AND_I32_A32\0" /* 350 */ "ATOMIC_RMW_AND_I32_A32\0" /* 373 */ "ATOMIC_STORE_I32_A32\0" /* 394 */ "ATOMIC_RMW16_U_CMPXCHG_I32_A32\0" /* 425 */ "ATOMIC_RMW8_U_CMPXCHG_I32_A32\0" /* 455 */ "ATOMIC_RMW_CMPXCHG_I32_A32\0" /* 482 */ "ATOMIC_RMW16_U_XCHG_I32_A32\0" /* 510 */ "ATOMIC_RMW8_U_XCHG_I32_A32\0" /* 537 */ "ATOMIC_RMW_XCHG_I32_A32\0" /* 561 */ "ATOMIC_RMW16_U_XOR_I32_A32\0" /* 588 */ "ATOMIC_RMW8_U_XOR_I32_A32\0" /* 614 */ "ATOMIC_RMW_XOR_I32_A32\0" /* 637 */ "ATOMIC_RMW16_U_OR_I32_A32\0" /* 663 */ "ATOMIC_RMW8_U_OR_I32_A32\0" /* 688 */ "ATOMIC_RMW_OR_I32_A32\0" /* 710 */ "LOAD16_S_I32_A32\0" /* 727 */ "LOAD8_S_I32_A32\0" /* 743 */ "ATOMIC_LOAD16_U_I32_A32\0" /* 767 */ "ATOMIC_LOAD8_U_I32_A32\0" /* 790 */ "MEMORY_ATOMIC_WAIT32_A32\0" /* 815 */ "LOAD_LANE_32_A32\0" /* 832 */ "LOAD_ZERO_32_A32\0" /* 849 */ "STORE_LANE_I64x2_A32\0" /* 870 */ "LOAD_EXTEND_S_I64x2_A32\0" /* 894 */ "LOAD_EXTEND_U_I64x2_A32\0" /* 918 */ "LOAD_F64_A32\0" /* 931 */ "STORE_F64_A32\0" /* 945 */ "ATOMIC_STORE32_I64_A32\0" /* 968 */ "ATOMIC_STORE16_I64_A32\0" /* 991 */ "ATOMIC_STORE8_I64_A32\0" /* 1013 */ "ATOMIC_RMW32_U_SUB_I64_A32\0" /* 1040 */ "ATOMIC_RMW16_U_SUB_I64_A32\0" /* 1067 */ "ATOMIC_RMW8_U_SUB_I64_A32\0" /* 1093 */ "ATOMIC_RMW_SUB_I64_A32\0" /* 1116 */ "ATOMIC_LOAD_I64_A32\0" /* 1136 */ "ATOMIC_RMW32_U_ADD_I64_A32\0" /* 1163 */ "ATOMIC_RMW16_U_ADD_I64_A32\0" /* 1190 */ "ATOMIC_RMW8_U_ADD_I64_A32\0" /* 1216 */ "ATOMIC_RMW_ADD_I64_A32\0" /* 1239 */ "ATOMIC_RMW32_U_AND_I64_A32\0" /* 1266 */ "ATOMIC_RMW16_U_AND_I64_A32\0" /* 1293 */ "ATOMIC_RMW8_U_AND_I64_A32\0" /* 1319 */ "ATOMIC_RMW_AND_I64_A32\0" /* 1342 */ "ATOMIC_STORE_I64_A32\0" /* 1363 */ "ATOMIC_RMW32_U_CMPXCHG_I64_A32\0" /* 1394 */ "ATOMIC_RMW16_U_CMPXCHG_I64_A32\0" /* 1425 */ "ATOMIC_RMW8_U_CMPXCHG_I64_A32\0" /* 1455 */ "ATOMIC_RMW_CMPXCHG_I64_A32\0" /* 1482 */ "ATOMIC_RMW32_U_XCHG_I64_A32\0" /* 1510 */ "ATOMIC_RMW16_U_XCHG_I64_A32\0" /* 1538 */ "ATOMIC_RMW8_U_XCHG_I64_A32\0" /* 1565 */ "ATOMIC_RMW_XCHG_I64_A32\0" /* 1589 */ "ATOMIC_RMW32_U_XOR_I64_A32\0" /* 1616 */ "ATOMIC_RMW16_U_XOR_I64_A32\0" /* 1643 */ "ATOMIC_RMW8_U_XOR_I64_A32\0" /* 1669 */ "ATOMIC_RMW_XOR_I64_A32\0" /* 1692 */ "ATOMIC_RMW32_U_OR_I64_A32\0" /* 1718 */ "ATOMIC_RMW16_U_OR_I64_A32\0" /* 1744 */ "ATOMIC_RMW8_U_OR_I64_A32\0" /* 1769 */ "ATOMIC_RMW_OR_I64_A32\0" /* 1791 */ "LOAD32_S_I64_A32\0" /* 1808 */ "LOAD16_S_I64_A32\0" /* 1825 */ "LOAD8_S_I64_A32\0" /* 1841 */ "ATOMIC_LOAD32_U_I64_A32\0" /* 1865 */ "ATOMIC_LOAD16_U_I64_A32\0" /* 1889 */ "ATOMIC_LOAD8_U_I64_A32\0" /* 1912 */ "MEMORY_ATOMIC_WAIT64_A32\0" /* 1937 */ "LOAD_LANE_64_A32\0" /* 1954 */ "LOAD_ZERO_64_A32\0" /* 1971 */ "STORE_LANE_I32x4_A32\0" /* 1992 */ "LOAD_EXTEND_S_I32x4_A32\0" /* 2016 */ "LOAD_EXTEND_U_I32x4_A32\0" /* 2040 */ "LOAD_LANE_16_A32\0" /* 2057 */ "STORE_LANE_I8x16_A32\0" /* 2078 */ "LOAD_V128_A32\0" /* 2092 */ "STORE_V128_A32\0" /* 2107 */ "LOAD_LANE_8_A32\0" /* 2123 */ "STORE_LANE_I16x8_A32\0" /* 2144 */ "LOAD_EXTEND_S_I16x8_A32\0" /* 2168 */ "LOAD_EXTEND_U_I16x8_A32\0" /* 2192 */ "anonymous_8166MEMORY_SIZE_A32\0" /* 2222 */ "anonymous_8883MEMORY_FILL_A32\0" /* 2252 */ "LOAD32_SPLAT_A32\0" /* 2269 */ "LOAD64_SPLAT_A32\0" /* 2286 */ "LOAD16_SPLAT_A32\0" /* 2303 */ "LOAD8_SPLAT_A32\0" /* 2319 */ "anonymous_8883MEMORY_INIT_A32\0" /* 2349 */ "anonymous_8166MEMORY_GROW_A32\0" /* 2379 */ "MEMORY_ATOMIC_NOTIFY_A32\0" /* 2404 */ "anonymous_8883MEMORY_COPY_A32\0" /* 2434 */ "FP_TO_SINT_I32_F32\0" /* 2453 */ "FP_TO_UINT_I32_F32\0" /* 2472 */ "FP_TO_SINT_I64_F32\0" /* 2491 */ "FP_TO_UINT_I64_F32\0" /* 2510 */ "SUB_F32\0" /* 2518 */ "TRUNC_F32\0" /* 2528 */ "ADD_F32\0" /* 2536 */ "LOCAL_TEE_F32\0" /* 2550 */ "GE_F32\0" /* 2557 */ "LE_F32\0" /* 2564 */ "NE_F32\0" /* 2571 */ "F64_PROMOTE_F32\0" /* 2587 */ "NEG_F32\0" /* 2595 */ "CEIL_F32\0" /* 2604 */ "MUL_F32\0" /* 2612 */ "COPYSIGN_F32\0" /* 2625 */ "MIN_F32\0" /* 2633 */ "DROP_F32\0" /* 2642 */ "EQ_F32\0" /* 2649 */ "FLOOR_F32\0" /* 2659 */ "ABS_F32\0" /* 2667 */ "I32_TRUNC_S_F32\0" /* 2683 */ "I64_TRUNC_S_F32\0" /* 2699 */ "I32_TRUNC_S_SAT_F32\0" /* 2719 */ "I64_TRUNC_S_SAT_F32\0" /* 2739 */ "I32_TRUNC_U_SAT_F32\0" /* 2759 */ "I64_TRUNC_U_SAT_F32\0" /* 2779 */ "SELECT_F32\0" /* 2790 */ "GLOBAL_GET_F32\0" /* 2805 */ "LOCAL_GET_F32\0" /* 2819 */ "I32_REINTERPRET_F32\0" /* 2839 */ "GLOBAL_SET_F32\0" /* 2854 */ "LOCAL_SET_F32\0" /* 2868 */ "GT_F32\0" /* 2875 */ "LT_F32\0" /* 2882 */ "SQRT_F32\0" /* 2891 */ "NEAREST_F32\0" /* 2903 */ "CONST_F32\0" /* 2913 */ "I32_TRUNC_U_F32\0" /* 2929 */ "I64_TRUNC_U_F32\0" /* 2945 */ "DIV_F32\0" /* 2953 */ "MAX_F32\0" /* 2961 */ "COPY_F32\0" /* 2970 */ "SUB_I32\0" /* 2978 */ "ADD_I32\0" /* 2986 */ "AND_I32\0" /* 2994 */ "LOCAL_TEE_I32\0" /* 3008 */ "BR_TABLE_I32\0" /* 3021 */ "NE_I32\0" /* 3028 */ "SHL_I32\0" /* 3036 */ "ROTL_I32\0" /* 3045 */ "MUL_I32\0" /* 3053 */ "DROP_I32\0" /* 3062 */ "EQ_I32\0" /* 3069 */ "XOR_I32\0" /* 3077 */ "ROTR_I32\0" /* 3086 */ "I32_EXTEND16_S_I32\0" /* 3105 */ "I32_EXTEND8_S_I32\0" /* 3123 */ "I64_EXTEND_S_I32\0" /* 3140 */ "GE_S_I32\0" /* 3149 */ "LE_S_I32\0" /* 3158 */ "REM_S_I32\0" /* 3168 */ "SHR_S_I32\0" /* 3178 */ "GT_S_I32\0" /* 3187 */ "LT_S_I32\0" /* 3196 */ "F32_CONVERT_S_I32\0" /* 3214 */ "F64_CONVERT_S_I32\0" /* 3232 */ "DIV_S_I32\0" /* 3242 */ "SELECT_I32\0" /* 3253 */ "GLOBAL_GET_I32\0" /* 3268 */ "LOCAL_GET_I32\0" /* 3282 */ "F32_REINTERPRET_I32\0" /* 3302 */ "GLOBAL_SET_I32\0" /* 3317 */ "LOCAL_SET_I32\0" /* 3331 */ "POPCNT_I32\0" /* 3342 */ "CONST_I32\0" /* 3352 */ "I64_EXTEND_U_I32\0" /* 3369 */ "GE_U_I32\0" /* 3378 */ "LE_U_I32\0" /* 3387 */ "REM_U_I32\0" /* 3397 */ "SHR_U_I32\0" /* 3407 */ "GT_U_I32\0" /* 3416 */ "LT_U_I32\0" /* 3425 */ "F32_CONVERT_U_I32\0" /* 3443 */ "F64_CONVERT_U_I32\0" /* 3461 */ "DIV_U_I32\0" /* 3471 */ "COPY_I32\0" /* 3480 */ "CLZ_I32\0" /* 3488 */ "EQZ_I32\0" /* 3496 */ "CTZ_I32\0" /* 3504 */ "ARGUMENT_v4f32\0" /* 3519 */ "ARGUMENT_f32\0" /* 3532 */ "ARGUMENT_v4i32\0" /* 3547 */ "ARGUMENT_i32\0" /* 3560 */ "G_FLOG2\0" /* 3568 */ "G_FEXP2\0" /* 3576 */ "CONST_V128_F64x2\0" /* 3593 */ "SUB_F64x2\0" /* 3603 */ "TRUNC_F64x2\0" /* 3615 */ "NMADD_F64x2\0" /* 3627 */ "GE_F64x2\0" /* 3636 */ "LE_F64x2\0" /* 3645 */ "REPLACE_LANE_F64x2\0" /* 3664 */ "EXTRACT_LANE_F64x2\0" /* 3683 */ "NEG_F64x2\0" /* 3693 */ "CEIL_F64x2\0" /* 3704 */ "MUL_F64x2\0" /* 3714 */ "SIMD_RELAXED_FMIN_F64x2\0" /* 3738 */ "PMIN_F64x2\0" /* 3749 */ "EQ_F64x2\0" /* 3758 */ "FLOOR_F64x2\0" /* 3770 */ "ABS_F64x2\0" /* 3780 */ "SPLAT_F64x2\0" /* 3792 */ "GT_F64x2\0" /* 3801 */ "LT_F64x2\0" /* 3810 */ "SQRT_F64x2\0" /* 3821 */ "NEAREST_F64x2\0" /* 3835 */ "DIV_F64x2\0" /* 3845 */ "SIMD_RELAXED_FMAX_F64x2\0" /* 3869 */ "PMAX_F64x2\0" /* 3880 */ "convert_low_s_F64x2\0" /* 3900 */ "convert_low_u_F64x2\0" /* 3920 */ "promote_low_F64x2\0" /* 3938 */ "CONST_V128_I64x2\0" /* 3955 */ "SUB_I64x2\0" /* 3965 */ "ADD_I64x2\0" /* 3975 */ "REPLACE_LANE_I64x2\0" /* 3994 */ "EXTRACT_LANE_I64x2\0" /* 4013 */ "ALLTRUE_I64x2\0" /* 4027 */ "NEG_I64x2\0" /* 4037 */ "BITMASK_I64x2\0" /* 4051 */ "SHL_I64x2\0" /* 4061 */ "MUL_I64x2\0" /* 4071 */ "EQ_I64x2\0" /* 4080 */ "ABS_I64x2\0" /* 4090 */ "GE_S_I64x2\0" /* 4101 */ "LE_S_I64x2\0" /* 4112 */ "EXTMUL_HIGH_S_I64x2\0" /* 4132 */ "SHR_S_I64x2\0" /* 4144 */ "GT_S_I64x2\0" /* 4155 */ "LT_S_I64x2\0" /* 4166 */ "EXTMUL_LOW_S_I64x2\0" /* 4185 */ "SPLAT_I64x2\0" /* 4197 */ "LANESELECT_I64x2\0" /* 4214 */ "EXTMUL_HIGH_U_I64x2\0" /* 4234 */ "SHR_U_I64x2\0" /* 4246 */ "EXTMUL_LOW_U_I64x2\0" /* 4265 */ "extend_high_s_I64x2\0" /* 4285 */ "extend_low_s_I64x2\0" /* 4304 */ "extend_high_u_I64x2\0" /* 4324 */ "extend_low_u_I64x2\0" /* 4343 */ "LOAD_F16_F32_A64\0" /* 4360 */ "STORE_F16_F32_A64\0" /* 4378 */ "LOAD_F32_A64\0" /* 4391 */ "STORE_F32_A64\0" /* 4405 */ "ATOMIC_STORE16_I32_A64\0" /* 4428 */ "ATOMIC_STORE8_I32_A64\0" /* 4450 */ "ATOMIC_RMW16_U_SUB_I32_A64\0" /* 4477 */ "ATOMIC_RMW8_U_SUB_I32_A64\0" /* 4503 */ "ATOMIC_RMW_SUB_I32_A64\0" /* 4526 */ "ATOMIC_LOAD_I32_A64\0" /* 4546 */ "ATOMIC_RMW16_U_ADD_I32_A64\0" /* 4573 */ "ATOMIC_RMW8_U_ADD_I32_A64\0" /* 4599 */ "ATOMIC_RMW_ADD_I32_A64\0" /* 4622 */ "ATOMIC_RMW16_U_AND_I32_A64\0" /* 4649 */ "ATOMIC_RMW8_U_AND_I32_A64\0" /* 4675 */ "ATOMIC_RMW_AND_I32_A64\0" /* 4698 */ "ATOMIC_STORE_I32_A64\0" /* 4719 */ "ATOMIC_RMW16_U_CMPXCHG_I32_A64\0" /* 4750 */ "ATOMIC_RMW8_U_CMPXCHG_I32_A64\0" /* 4780 */ "ATOMIC_RMW_CMPXCHG_I32_A64\0" /* 4807 */ "ATOMIC_RMW16_U_XCHG_I32_A64\0" /* 4835 */ "ATOMIC_RMW8_U_XCHG_I32_A64\0" /* 4862 */ "ATOMIC_RMW_XCHG_I32_A64\0" /* 4886 */ "ATOMIC_RMW16_U_XOR_I32_A64\0" /* 4913 */ "ATOMIC_RMW8_U_XOR_I32_A64\0" /* 4939 */ "ATOMIC_RMW_XOR_I32_A64\0" /* 4962 */ "ATOMIC_RMW16_U_OR_I32_A64\0" /* 4988 */ "ATOMIC_RMW8_U_OR_I32_A64\0" /* 5013 */ "ATOMIC_RMW_OR_I32_A64\0" /* 5035 */ "LOAD16_S_I32_A64\0" /* 5052 */ "LOAD8_S_I32_A64\0" /* 5068 */ "ATOMIC_LOAD16_U_I32_A64\0" /* 5092 */ "ATOMIC_LOAD8_U_I32_A64\0" /* 5115 */ "MEMORY_ATOMIC_WAIT32_A64\0" /* 5140 */ "LOAD_LANE_32_A64\0" /* 5157 */ "LOAD_ZERO_32_A64\0" /* 5174 */ "STORE_LANE_I64x2_A64\0" /* 5195 */ "LOAD_EXTEND_S_I64x2_A64\0" /* 5219 */ "LOAD_EXTEND_U_I64x2_A64\0" /* 5243 */ "LOAD_F64_A64\0" /* 5256 */ "STORE_F64_A64\0" /* 5270 */ "ATOMIC_STORE32_I64_A64\0" /* 5293 */ "ATOMIC_STORE16_I64_A64\0" /* 5316 */ "ATOMIC_STORE8_I64_A64\0" /* 5338 */ "ATOMIC_RMW32_U_SUB_I64_A64\0" /* 5365 */ "ATOMIC_RMW16_U_SUB_I64_A64\0" /* 5392 */ "ATOMIC_RMW8_U_SUB_I64_A64\0" /* 5418 */ "ATOMIC_RMW_SUB_I64_A64\0" /* 5441 */ "ATOMIC_LOAD_I64_A64\0" /* 5461 */ "ATOMIC_RMW32_U_ADD_I64_A64\0" /* 5488 */ "ATOMIC_RMW16_U_ADD_I64_A64\0" /* 5515 */ "ATOMIC_RMW8_U_ADD_I64_A64\0" /* 5541 */ "ATOMIC_RMW_ADD_I64_A64\0" /* 5564 */ "ATOMIC_RMW32_U_AND_I64_A64\0" /* 5591 */ "ATOMIC_RMW16_U_AND_I64_A64\0" /* 5618 */ "ATOMIC_RMW8_U_AND_I64_A64\0" /* 5644 */ "ATOMIC_RMW_AND_I64_A64\0" /* 5667 */ "ATOMIC_STORE_I64_A64\0" /* 5688 */ "ATOMIC_RMW32_U_CMPXCHG_I64_A64\0" /* 5719 */ "ATOMIC_RMW16_U_CMPXCHG_I64_A64\0" /* 5750 */ "ATOMIC_RMW8_U_CMPXCHG_I64_A64\0" /* 5780 */ "ATOMIC_RMW_CMPXCHG_I64_A64\0" /* 5807 */ "ATOMIC_RMW32_U_XCHG_I64_A64\0" /* 5835 */ "ATOMIC_RMW16_U_XCHG_I64_A64\0" /* 5863 */ "ATOMIC_RMW8_U_XCHG_I64_A64\0" /* 5890 */ "ATOMIC_RMW_XCHG_I64_A64\0" /* 5914 */ "ATOMIC_RMW32_U_XOR_I64_A64\0" /* 5941 */ "ATOMIC_RMW16_U_XOR_I64_A64\0" /* 5968 */ "ATOMIC_RMW8_U_XOR_I64_A64\0" /* 5994 */ "ATOMIC_RMW_XOR_I64_A64\0" /* 6017 */ "ATOMIC_RMW32_U_OR_I64_A64\0" /* 6043 */ "ATOMIC_RMW16_U_OR_I64_A64\0" /* 6069 */ "ATOMIC_RMW8_U_OR_I64_A64\0" /* 6094 */ "ATOMIC_RMW_OR_I64_A64\0" /* 6116 */ "LOAD32_S_I64_A64\0" /* 6133 */ "LOAD16_S_I64_A64\0" /* 6150 */ "LOAD8_S_I64_A64\0" /* 6166 */ "ATOMIC_LOAD32_U_I64_A64\0" /* 6190 */ "ATOMIC_LOAD16_U_I64_A64\0" /* 6214 */ "ATOMIC_LOAD8_U_I64_A64\0" /* 6237 */ "MEMORY_ATOMIC_WAIT64_A64\0" /* 6262 */ "LOAD_LANE_64_A64\0" /* 6279 */ "LOAD_ZERO_64_A64\0" /* 6296 */ "STORE_LANE_I32x4_A64\0" /* 6317 */ "LOAD_EXTEND_S_I32x4_A64\0" /* 6341 */ "LOAD_EXTEND_U_I32x4_A64\0" /* 6365 */ "LOAD_LANE_16_A64\0" /* 6382 */ "STORE_LANE_I8x16_A64\0" /* 6403 */ "LOAD_V128_A64\0" /* 6417 */ "STORE_V128_A64\0" /* 6432 */ "LOAD_LANE_8_A64\0" /* 6448 */ "STORE_LANE_I16x8_A64\0" /* 6469 */ "LOAD_EXTEND_S_I16x8_A64\0" /* 6493 */ "LOAD_EXTEND_U_I16x8_A64\0" /* 6517 */ "anonymous_8167MEMORY_SIZE_A64\0" /* 6547 */ "anonymous_8884MEMORY_FILL_A64\0" /* 6577 */ "LOAD32_SPLAT_A64\0" /* 6594 */ "LOAD64_SPLAT_A64\0" /* 6611 */ "LOAD16_SPLAT_A64\0" /* 6628 */ "LOAD8_SPLAT_A64\0" /* 6644 */ "anonymous_8884MEMORY_INIT_A64\0" /* 6674 */ "anonymous_8167MEMORY_GROW_A64\0" /* 6704 */ "MEMORY_ATOMIC_NOTIFY_A64\0" /* 6729 */ "anonymous_8884MEMORY_COPY_A64\0" /* 6759 */ "FP_TO_SINT_I32_F64\0" /* 6778 */ "FP_TO_UINT_I32_F64\0" /* 6797 */ "FP_TO_SINT_I64_F64\0" /* 6816 */ "FP_TO_UINT_I64_F64\0" /* 6835 */ "SUB_F64\0" /* 6843 */ "TRUNC_F64\0" /* 6853 */ "ADD_F64\0" /* 6861 */ "LOCAL_TEE_F64\0" /* 6875 */ "GE_F64\0" /* 6882 */ "LE_F64\0" /* 6889 */ "NE_F64\0" /* 6896 */ "F32_DEMOTE_F64\0" /* 6911 */ "NEG_F64\0" /* 6919 */ "CEIL_F64\0" /* 6928 */ "MUL_F64\0" /* 6936 */ "COPYSIGN_F64\0" /* 6949 */ "MIN_F64\0" /* 6957 */ "DROP_F64\0" /* 6966 */ "EQ_F64\0" /* 6973 */ "FLOOR_F64\0" /* 6983 */ "ABS_F64\0" /* 6991 */ "I32_TRUNC_S_F64\0" /* 7007 */ "I64_TRUNC_S_F64\0" /* 7023 */ "I32_TRUNC_S_SAT_F64\0" /* 7043 */ "I64_TRUNC_S_SAT_F64\0" /* 7063 */ "I32_TRUNC_U_SAT_F64\0" /* 7083 */ "I64_TRUNC_U_SAT_F64\0" /* 7103 */ "SELECT_F64\0" /* 7114 */ "GLOBAL_GET_F64\0" /* 7129 */ "LOCAL_GET_F64\0" /* 7143 */ "I64_REINTERPRET_F64\0" /* 7163 */ "GLOBAL_SET_F64\0" /* 7178 */ "LOCAL_SET_F64\0" /* 7192 */ "GT_F64\0" /* 7199 */ "LT_F64\0" /* 7206 */ "SQRT_F64\0" /* 7215 */ "NEAREST_F64\0" /* 7227 */ "CONST_F64\0" /* 7237 */ "I32_TRUNC_U_F64\0" /* 7253 */ "I64_TRUNC_U_F64\0" /* 7269 */ "DIV_F64\0" /* 7277 */ "MAX_F64\0" /* 7285 */ "COPY_F64\0" /* 7294 */ "SUB_I64\0" /* 7302 */ "ADD_I64\0" /* 7310 */ "AND_I64\0" /* 7318 */ "LOCAL_TEE_I64\0" /* 7332 */ "BR_TABLE_I64\0" /* 7345 */ "NE_I64\0" /* 7352 */ "SHL_I64\0" /* 7360 */ "ROTL_I64\0" /* 7369 */ "MUL_I64\0" /* 7377 */ "I32_WRAP_I64\0" /* 7390 */ "DROP_I64\0" /* 7399 */ "EQ_I64\0" /* 7406 */ "XOR_I64\0" /* 7414 */ "ROTR_I64\0" /* 7423 */ "I64_EXTEND32_S_I64\0" /* 7442 */ "I64_EXTEND16_S_I64\0" /* 7461 */ "I64_EXTEND8_S_I64\0" /* 7479 */ "GE_S_I64\0" /* 7488 */ "LE_S_I64\0" /* 7497 */ "REM_S_I64\0" /* 7507 */ "SHR_S_I64\0" /* 7517 */ "GT_S_I64\0" /* 7526 */ "LT_S_I64\0" /* 7535 */ "F32_CONVERT_S_I64\0" /* 7553 */ "F64_CONVERT_S_I64\0" /* 7571 */ "DIV_S_I64\0" /* 7581 */ "SELECT_I64\0" /* 7592 */ "GLOBAL_GET_I64\0" /* 7607 */ "LOCAL_GET_I64\0" /* 7621 */ "F64_REINTERPRET_I64\0" /* 7641 */ "GLOBAL_SET_I64\0" /* 7656 */ "LOCAL_SET_I64\0" /* 7670 */ "POPCNT_I64\0" /* 7681 */ "CONST_I64\0" /* 7691 */ "GE_U_I64\0" /* 7700 */ "LE_U_I64\0" /* 7709 */ "REM_U_I64\0" /* 7719 */ "SHR_U_I64\0" /* 7729 */ "GT_U_I64\0" /* 7738 */ "LT_U_I64\0" /* 7747 */ "F32_CONVERT_U_I64\0" /* 7765 */ "F64_CONVERT_U_I64\0" /* 7783 */ "DIV_U_I64\0" /* 7793 */ "COPY_I64\0" /* 7802 */ "CLZ_I64\0" /* 7810 */ "EQZ_I64\0" /* 7818 */ "CTZ_I64\0" /* 7826 */ "ARGUMENT_v2f64\0" /* 7841 */ "ARGUMENT_f64\0" /* 7854 */ "ARGUMENT_v2i64\0" /* 7869 */ "ARGUMENT_i64\0" /* 7882 */ "CONST_V128_F32x4\0" /* 7899 */ "SUB_F32x4\0" /* 7909 */ "TRUNC_F32x4\0" /* 7921 */ "NMADD_F32x4\0" /* 7933 */ "GE_F32x4\0" /* 7942 */ "LE_F32x4\0" /* 7951 */ "REPLACE_LANE_F32x4\0" /* 7970 */ "EXTRACT_LANE_F32x4\0" /* 7989 */ "NEG_F32x4\0" /* 7999 */ "CEIL_F32x4\0" /* 8010 */ "MUL_F32x4\0" /* 8020 */ "SIMD_RELAXED_FMIN_F32x4\0" /* 8044 */ "PMIN_F32x4\0" /* 8055 */ "EQ_F32x4\0" /* 8064 */ "FLOOR_F32x4\0" /* 8076 */ "ABS_F32x4\0" /* 8086 */ "SPLAT_F32x4\0" /* 8098 */ "GT_F32x4\0" /* 8107 */ "LT_F32x4\0" /* 8116 */ "SQRT_F32x4\0" /* 8127 */ "NEAREST_F32x4\0" /* 8141 */ "DIV_F32x4\0" /* 8151 */ "SIMD_RELAXED_FMAX_F32x4\0" /* 8175 */ "PMAX_F32x4\0" /* 8186 */ "demote_zero_F32x4\0" /* 8204 */ "sint_to_fp_F32x4\0" /* 8221 */ "uint_to_fp_F32x4\0" /* 8238 */ "CONST_V128_I32x4\0" /* 8255 */ "SUB_I32x4\0" /* 8265 */ "ADD_I32x4\0" /* 8275 */ "REPLACE_LANE_I32x4\0" /* 8294 */ "EXTRACT_LANE_I32x4\0" /* 8313 */ "ALLTRUE_I32x4\0" /* 8327 */ "NEG_I32x4\0" /* 8337 */ "BITMASK_I32x4\0" /* 8351 */ "SHL_I32x4\0" /* 8361 */ "MUL_I32x4\0" /* 8371 */ "EQ_I32x4\0" /* 8380 */ "ABS_I32x4\0" /* 8390 */ "GE_S_I32x4\0" /* 8401 */ "LE_S_I32x4\0" /* 8412 */ "EXTMUL_HIGH_S_I32x4\0" /* 8432 */ "MIN_S_I32x4\0" /* 8444 */ "SHR_S_I32x4\0" /* 8456 */ "GT_S_I32x4\0" /* 8467 */ "LT_S_I32x4\0" /* 8478 */ "EXTMUL_LOW_S_I32x4\0" /* 8497 */ "MAX_S_I32x4\0" /* 8509 */ "SPLAT_I32x4\0" /* 8521 */ "LANESELECT_I32x4\0" /* 8538 */ "GE_U_I32x4\0" /* 8549 */ "LE_U_I32x4\0" /* 8560 */ "EXTMUL_HIGH_U_I32x4\0" /* 8580 */ "MIN_U_I32x4\0" /* 8592 */ "SHR_U_I32x4\0" /* 8604 */ "GT_U_I32x4\0" /* 8615 */ "LT_U_I32x4\0" /* 8626 */ "EXTMUL_LOW_U_I32x4\0" /* 8645 */ "MAX_U_I32x4\0" /* 8657 */ "int_wasm_relaxed_trunc_signed_I32x4\0" /* 8693 */ "int_wasm_extadd_pairwise_signed_I32x4\0" /* 8731 */ "int_wasm_relaxed_trunc_unsigned_I32x4\0" /* 8769 */ "int_wasm_extadd_pairwise_unsigned_I32x4\0" /* 8809 */ "int_wasm_relaxed_trunc_signed_zero_I32x4\0" /* 8850 */ "int_wasm_relaxed_trunc_unsigned_zero_I32x4\0" /* 8893 */ "extend_high_s_I32x4\0" /* 8913 */ "trunc_sat_zero_s_I32x4\0" /* 8936 */ "extend_low_s_I32x4\0" /* 8955 */ "fp_to_sint_I32x4\0" /* 8972 */ "fp_to_uint_I32x4\0" /* 8989 */ "extend_high_u_I32x4\0" /* 9009 */ "trunc_sat_zero_u_I32x4\0" /* 9032 */ "extend_low_u_I32x4\0" /* 9051 */ "ARGUMENT_v8f16\0" /* 9066 */ "ARGUMENT_v8i16\0" /* 9081 */ "CONST_V128_I8x16\0" /* 9098 */ "SUB_I8x16\0" /* 9108 */ "ADD_I8x16\0" /* 9118 */ "REPLACE_LANE_I8x16\0" /* 9137 */ "ALLTRUE_I8x16\0" /* 9151 */ "NEG_I8x16\0" /* 9161 */ "BITMASK_I8x16\0" /* 9175 */ "SHL_I8x16\0" /* 9185 */ "EQ_I8x16\0" /* 9194 */ "ABS_I8x16\0" /* 9204 */ "GE_S_I8x16\0" /* 9215 */ "LE_S_I8x16\0" /* 9226 */ "MIN_S_I8x16\0" /* 9238 */ "SHR_S_I8x16\0" /* 9250 */ "SUB_SAT_S_I8x16\0" /* 9266 */ "ADD_SAT_S_I8x16\0" /* 9282 */ "GT_S_I8x16\0" /* 9293 */ "LT_S_I8x16\0" /* 9304 */ "NARROW_S_I8x16\0" /* 9319 */ "MAX_S_I8x16\0" /* 9331 */ "SPLAT_I8x16\0" /* 9343 */ "LANESELECT_I8x16\0" /* 9360 */ "POPCNT_I8x16\0" /* 9373 */ "GE_U_I8x16\0" /* 9384 */ "LE_U_I8x16\0" /* 9395 */ "MIN_U_I8x16\0" /* 9407 */ "AVGR_U_I8x16\0" /* 9420 */ "SHR_U_I8x16\0" /* 9432 */ "SUB_SAT_U_I8x16\0" /* 9448 */ "ADD_SAT_U_I8x16\0" /* 9464 */ "GT_U_I8x16\0" /* 9475 */ "LT_U_I8x16\0" /* 9486 */ "NARROW_U_I8x16\0" /* 9501 */ "MAX_U_I8x16\0" /* 9513 */ "LOCAL_TEE_V128\0" /* 9528 */ "DROP_V128\0" /* 9538 */ "SELECT_V128\0" /* 9550 */ "GLOBAL_GET_V128\0" /* 9566 */ "LOCAL_GET_V128\0" /* 9581 */ "GLOBAL_SET_V128\0" /* 9597 */ "LOCAL_SET_V128\0" /* 9612 */ "COPY_V128\0" /* 9622 */ "ARGUMENT_v16i8\0" /* 9637 */ "SUB_F16x8\0" /* 9647 */ "TRUNC_F16x8\0" /* 9659 */ "NMADD_F16x8\0" /* 9671 */ "GE_F16x8\0" /* 9680 */ "LE_F16x8\0" /* 9689 */ "REPLACE_LANE_F16x8\0" /* 9708 */ "EXTRACT_LANE_F16x8\0" /* 9727 */ "NEG_F16x8\0" /* 9737 */ "CEIL_F16x8\0" /* 9748 */ "MUL_F16x8\0" /* 9758 */ "PMIN_F16x8\0" /* 9769 */ "EQ_F16x8\0" /* 9778 */ "FLOOR_F16x8\0" /* 9790 */ "ABS_F16x8\0" /* 9800 */ "SPLAT_F16x8\0" /* 9812 */ "GT_F16x8\0" /* 9821 */ "LT_F16x8\0" /* 9830 */ "SQRT_F16x8\0" /* 9841 */ "NEAREST_F16x8\0" /* 9855 */ "DIV_F16x8\0" /* 9865 */ "PMAX_F16x8\0" /* 9876 */ "sint_to_fp_F16x8\0" /* 9893 */ "uint_to_fp_F16x8\0" /* 9910 */ "CONST_V128_I16x8\0" /* 9927 */ "SUB_I16x8\0" /* 9937 */ "ADD_I16x8\0" /* 9947 */ "REPLACE_LANE_I16x8\0" /* 9966 */ "ALLTRUE_I16x8\0" /* 9980 */ "NEG_I16x8\0" /* 9990 */ "BITMASK_I16x8\0" /* 10004 */ "SHL_I16x8\0" /* 10014 */ "MUL_I16x8\0" /* 10024 */ "EQ_I16x8\0" /* 10033 */ "ABS_I16x8\0" /* 10043 */ "GE_S_I16x8\0" /* 10054 */ "LE_S_I16x8\0" /* 10065 */ "EXTMUL_HIGH_S_I16x8\0" /* 10085 */ "MIN_S_I16x8\0" /* 10097 */ "SHR_S_I16x8\0" /* 10109 */ "RELAXED_Q15MULR_S_I16x8\0" /* 10133 */ "SUB_SAT_S_I16x8\0" /* 10149 */ "ADD_SAT_S_I16x8\0" /* 10165 */ "Q15MULR_SAT_S_I16x8\0" /* 10185 */ "GT_S_I16x8\0" /* 10196 */ "LT_S_I16x8\0" /* 10207 */ "EXTMUL_LOW_S_I16x8\0" /* 10226 */ "NARROW_S_I16x8\0" /* 10241 */ "MAX_S_I16x8\0" /* 10253 */ "SPLAT_I16x8\0" /* 10265 */ "LANESELECT_I16x8\0" /* 10282 */ "GE_U_I16x8\0" /* 10293 */ "LE_U_I16x8\0" /* 10304 */ "EXTMUL_HIGH_U_I16x8\0" /* 10324 */ "MIN_U_I16x8\0" /* 10336 */ "AVGR_U_I16x8\0" /* 10349 */ "SHR_U_I16x8\0" /* 10361 */ "SUB_SAT_U_I16x8\0" /* 10377 */ "ADD_SAT_U_I16x8\0" /* 10393 */ "GT_U_I16x8\0" /* 10404 */ "LT_U_I16x8\0" /* 10415 */ "EXTMUL_LOW_U_I16x8\0" /* 10434 */ "NARROW_U_I16x8\0" /* 10449 */ "MAX_U_I16x8\0" /* 10461 */ "int_wasm_extadd_pairwise_signed_I16x8\0" /* 10499 */ "int_wasm_extadd_pairwise_unsigned_I16x8\0" /* 10539 */ "extend_high_s_I16x8\0" /* 10559 */ "extend_low_s_I16x8\0" /* 10578 */ "fp_to_sint_I16x8\0" /* 10595 */ "fp_to_uint_I16x8\0" /* 10612 */ "extend_high_u_I16x8\0" /* 10632 */ "extend_low_u_I16x8\0" /* 10651 */ "G_FMA\0" /* 10657 */ "G_STRICT_FMA\0" /* 10670 */ "G_FSUB\0" /* 10677 */ "G_STRICT_FSUB\0" /* 10691 */ "G_ATOMICRMW_FSUB\0" /* 10708 */ "G_SUB\0" /* 10714 */ "G_ATOMICRMW_SUB\0" /* 10730 */ "G_INTRINSIC\0" /* 10742 */ "G_FPTRUNC\0" /* 10752 */ "G_INTRINSIC_TRUNC\0" /* 10770 */ "G_TRUNC\0" /* 10778 */ "G_BUILD_VECTOR_TRUNC\0" /* 10799 */ "G_DYN_STACKALLOC\0" /* 10816 */ "G_FMAD\0" /* 10823 */ "G_INDEXED_SEXTLOAD\0" /* 10842 */ "G_SEXTLOAD\0" /* 10853 */ "G_INDEXED_ZEXTLOAD\0" /* 10872 */ "G_ZEXTLOAD\0" /* 10883 */ "G_INDEXED_LOAD\0" /* 10898 */ "G_LOAD\0" /* 10905 */ "G_VECREDUCE_FADD\0" /* 10922 */ "G_FADD\0" /* 10929 */ "G_VECREDUCE_SEQ_FADD\0" /* 10950 */ "G_STRICT_FADD\0" /* 10964 */ "G_ATOMICRMW_FADD\0" /* 10981 */ "G_VECREDUCE_ADD\0" /* 10997 */ "G_ADD\0" /* 11003 */ "G_PTR_ADD\0" /* 11013 */ "RELAXED_DOT_ADD\0" /* 11029 */ "G_ATOMICRMW_ADD\0" /* 11045 */ "G_ATOMICRMW_NAND\0" /* 11062 */ "G_VECREDUCE_AND\0" /* 11078 */ "G_AND\0" /* 11084 */ "G_ATOMICRMW_AND\0" /* 11100 */ "LIFETIME_END\0" /* 11113 */ "G_BRCOND\0" /* 11122 */ "G_LLROUND\0" /* 11132 */ "G_LROUND\0" /* 11141 */ "G_INTRINSIC_ROUND\0" /* 11159 */ "G_INTRINSIC_FPTRUNC_ROUND\0" /* 11185 */ "LOAD_STACK_GUARD\0" /* 11202 */ "PSEUDO_PROBE\0" /* 11215 */ "G_SSUBE\0" /* 11223 */ "G_USUBE\0" /* 11231 */ "ATOMIC_FENCE\0" /* 11244 */ "G_FENCE\0" /* 11252 */ "ARITH_FENCE\0" /* 11264 */ "COMPILER_FENCE\0" /* 11279 */ "REG_SEQUENCE\0" /* 11292 */ "G_SADDE\0" /* 11300 */ "G_UADDE\0" /* 11308 */ "G_GET_FPMODE\0" /* 11321 */ "G_RESET_FPMODE\0" /* 11336 */ "G_SET_FPMODE\0" /* 11349 */ "G_FMINNUM_IEEE\0" /* 11364 */ "G_FMAXNUM_IEEE\0" /* 11379 */ "G_VSCALE\0" /* 11388 */ "DEBUG_UNREACHABLE\0" /* 11406 */ "G_JUMP_TABLE\0" /* 11419 */ "BUNDLE\0" /* 11426 */ "SHUFFLE\0" /* 11434 */ "RELAXED_SWIZZLE\0" /* 11450 */ "G_MEMCPY_INLINE\0" /* 11466 */ "LOCAL_ESCAPE\0" /* 11479 */ "G_STACKRESTORE\0" /* 11494 */ "G_INDEXED_STORE\0" /* 11510 */ "G_STORE\0" /* 11518 */ "ELSE\0" /* 11523 */ "G_BITREVERSE\0" /* 11536 */ "FAKE_USE\0" /* 11545 */ "DELEGATE\0" /* 11554 */ "DBG_VALUE\0" /* 11564 */ "G_GLOBAL_VALUE\0" /* 11579 */ "G_PTRAUTH_GLOBAL_VALUE\0" /* 11602 */ "CONVERGENCECTRL_GLUE\0" /* 11623 */ "ANYTRUE\0" /* 11631 */ "G_STACKSAVE\0" /* 11643 */ "G_MEMMOVE\0" /* 11653 */ "G_FREEZE\0" /* 11662 */ "G_FCANONICALIZE\0" /* 11678 */ "TABLE_SIZE\0" /* 11689 */ "G_CTLZ_ZERO_UNDEF\0" /* 11707 */ "G_CTTZ_ZERO_UNDEF\0" /* 11725 */ "G_IMPLICIT_DEF\0" /* 11740 */ "LOCAL_TEE_FUNCREF\0" /* 11758 */ "TABLE_FILL_FUNCREF\0" /* 11777 */ "REF_NULL_FUNCREF\0" /* 11794 */ "REF_IS_NULL_FUNCREF\0" /* 11814 */ "DROP_FUNCREF\0" /* 11827 */ "SELECT_FUNCREF\0" /* 11842 */ "TABLE_GET_FUNCREF\0" /* 11860 */ "GLOBAL_GET_FUNCREF\0" /* 11879 */ "LOCAL_GET_FUNCREF\0" /* 11897 */ "TABLE_SET_FUNCREF\0" /* 11915 */ "GLOBAL_SET_FUNCREF\0" /* 11934 */ "LOCAL_SET_FUNCREF\0" /* 11952 */ "TABLE_GROW_FUNCREF\0" /* 11971 */ "COPY_FUNCREF\0" /* 11984 */ "LOCAL_TEE_EXTERNREF\0" /* 12004 */ "TABLE_FILL_EXTERNREF\0" /* 12025 */ "REF_NULL_EXTERNREF\0" /* 12044 */ "REF_IS_NULL_EXTERNREF\0" /* 12066 */ "DROP_EXTERNREF\0" /* 12081 */ "SELECT_EXTERNREF\0" /* 12098 */ "TABLE_GET_EXTERNREF\0" /* 12118 */ "GLOBAL_GET_EXTERNREF\0" /* 12139 */ "LOCAL_GET_EXTERNREF\0" /* 12159 */ "TABLE_SET_EXTERNREF\0" /* 12179 */ "GLOBAL_SET_EXTERNREF\0" /* 12200 */ "LOCAL_SET_EXTERNREF\0" /* 12220 */ "TABLE_GROW_EXTERNREF\0" /* 12241 */ "COPY_EXTERNREF\0" /* 12256 */ "LOCAL_TEE_EXNREF\0" /* 12273 */ "TABLE_FILL_EXNREF\0" /* 12291 */ "REF_NULL_EXNREF\0" /* 12307 */ "REF_IS_NULL_EXNREF\0" /* 12326 */ "DROP_EXNREF\0" /* 12338 */ "SELECT_EXNREF\0" /* 12352 */ "TABLE_GET_EXNREF\0" /* 12369 */ "GLOBAL_GET_EXNREF\0" /* 12387 */ "LOCAL_GET_EXNREF\0" /* 12404 */ "TABLE_SET_EXNREF\0" /* 12421 */ "GLOBAL_SET_EXNREF\0" /* 12439 */ "LOCAL_SET_EXNREF\0" /* 12456 */ "TABLE_GROW_EXNREF\0" /* 12474 */ "COPY_EXNREF\0" /* 12486 */ "DBG_INSTR_REF\0" /* 12500 */ "END_IF\0" /* 12507 */ "BR_IF\0" /* 12513 */ "G_FNEG\0" /* 12520 */ "EXTRACT_SUBREG\0" /* 12535 */ "INSERT_SUBREG\0" /* 12549 */ "G_SEXT_INREG\0" /* 12562 */ "SUBREG_TO_REG\0" /* 12576 */ "G_ATOMIC_CMPXCHG\0" /* 12593 */ "G_ATOMICRMW_XCHG\0" /* 12610 */ "G_FLOG\0" /* 12617 */ "G_VAARG\0" /* 12625 */ "PREALLOCATED_ARG\0" /* 12642 */ "CATCH\0" /* 12648 */ "G_PREFETCH\0" /* 12659 */ "G_SMULH\0" /* 12667 */ "G_UMULH\0" /* 12675 */ "G_FTANH\0" /* 12683 */ "G_FSINH\0" /* 12691 */ "G_FCOSH\0" /* 12699 */ "DBG_PHI\0" /* 12707 */ "G_FPTOSI\0" /* 12716 */ "G_FPTOUI\0" /* 12725 */ "G_FPOWI\0" /* 12733 */ "END_BLOCK\0" /* 12743 */ "G_PTRMASK\0" /* 12753 */ "GC_LABEL\0" /* 12762 */ "DBG_LABEL\0" /* 12772 */ "EH_LABEL\0" /* 12781 */ "ANNOTATION_LABEL\0" /* 12798 */ "ICALL_BRANCH_FUNNEL\0" /* 12818 */ "G_FSHL\0" /* 12825 */ "G_SHL\0" /* 12831 */ "G_FCEIL\0" /* 12839 */ "PATCHABLE_TAIL_CALL\0" /* 12859 */ "RET_CALL\0" /* 12868 */ "PATCHABLE_TYPED_EVENT_CALL\0" /* 12895 */ "PATCHABLE_EVENT_CALL\0" /* 12916 */ "FENTRY_CALL\0" /* 12928 */ "CATCH_ALL\0" /* 12938 */ "KILL\0" /* 12943 */ "G_CONSTANT_POOL\0" /* 12959 */ "G_ROTL\0" /* 12966 */ "G_VECREDUCE_FMUL\0" /* 12983 */ "G_FMUL\0" /* 12990 */ "G_VECREDUCE_SEQ_FMUL\0" /* 13011 */ "G_STRICT_FMUL\0" /* 13025 */ "G_VECREDUCE_MUL\0" /* 13041 */ "G_MUL\0" /* 13047 */ "G_FREM\0" /* 13054 */ "G_STRICT_FREM\0" /* 13068 */ "G_SREM\0" /* 13075 */ "G_UREM\0" /* 13082 */ "G_SDIVREM\0" /* 13092 */ "G_UDIVREM\0" /* 13102 */ "INLINEASM\0" /* 13112 */ "G_VECREDUCE_FMINIMUM\0" /* 13133 */ "G_FMINIMUM\0" /* 13144 */ "G_VECREDUCE_FMAXIMUM\0" /* 13165 */ "G_FMAXIMUM\0" /* 13176 */ "G_FMINNUM\0" /* 13186 */ "G_FMAXNUM\0" /* 13196 */ "G_FATAN\0" /* 13204 */ "G_FTAN\0" /* 13211 */ "G_INTRINSIC_ROUNDEVEN\0" /* 13233 */ "G_ASSERT_ALIGN\0" /* 13248 */ "G_FCOPYSIGN\0" /* 13260 */ "G_VECREDUCE_FMIN\0" /* 13277 */ "G_ATOMICRMW_FMIN\0" /* 13294 */ "G_VECREDUCE_SMIN\0" /* 13311 */ "G_SMIN\0" /* 13318 */ "G_VECREDUCE_UMIN\0" /* 13335 */ "G_UMIN\0" /* 13342 */ "G_ATOMICRMW_UMIN\0" /* 13359 */ "G_ATOMICRMW_MIN\0" /* 13375 */ "G_FASIN\0" /* 13383 */ "G_FSIN\0" /* 13390 */ "END_FUNCTION\0" /* 13403 */ "CFI_INSTRUCTION\0" /* 13419 */ "FALLTHROUGH_RETURN\0" /* 13438 */ "ADJCALLSTACKDOWN\0" /* 13455 */ "G_SSUBO\0" /* 13463 */ "G_USUBO\0" /* 13471 */ "G_SADDO\0" /* 13479 */ "G_UADDO\0" /* 13487 */ "JUMP_TABLE_DEBUG_INFO\0" /* 13509 */ "G_SMULO\0" /* 13517 */ "G_UMULO\0" /* 13525 */ "G_BZERO\0" /* 13533 */ "STACKMAP\0" /* 13542 */ "G_DEBUGTRAP\0" /* 13554 */ "G_UBSANTRAP\0" /* 13566 */ "G_TRAP\0" /* 13573 */ "G_ATOMICRMW_UDEC_WRAP\0" /* 13595 */ "G_ATOMICRMW_UINC_WRAP\0" /* 13617 */ "G_BSWAP\0" /* 13625 */ "G_SITOFP\0" /* 13634 */ "G_UITOFP\0" /* 13643 */ "G_FCMP\0" /* 13650 */ "G_ICMP\0" /* 13657 */ "G_SCMP\0" /* 13664 */ "G_UCMP\0" /* 13671 */ "NOP\0" /* 13675 */ "END_LOOP\0" /* 13684 */ "CONVERGENCECTRL_LOOP\0" /* 13705 */ "G_CTPOP\0" /* 13713 */ "anonymous_8883DATA_DROP\0" /* 13737 */ "anonymous_8884DATA_DROP\0" /* 13761 */ "PATCHABLE_OP\0" /* 13774 */ "FAULTING_OP\0" /* 13786 */ "ADJCALLSTACKUP\0" /* 13801 */ "PREALLOCATED_SETUP\0" /* 13820 */ "G_FLDEXP\0" /* 13829 */ "G_STRICT_FLDEXP\0" /* 13845 */ "G_FEXP\0" /* 13852 */ "G_FFREXP\0" /* 13861 */ "G_BR\0" /* 13866 */ "INLINEASM_BR\0" /* 13879 */ "G_BLOCK_ADDR\0" /* 13892 */ "MEMBARRIER\0" /* 13903 */ "G_CONSTANT_FOLD_BARRIER\0" /* 13927 */ "PATCHABLE_FUNCTION_ENTER\0" /* 13952 */ "G_READCYCLECOUNTER\0" /* 13971 */ "G_READSTEADYCOUNTER\0" /* 13991 */ "G_READ_REGISTER\0" /* 14007 */ "G_WRITE_REGISTER\0" /* 14024 */ "G_ASHR\0" /* 14031 */ "G_FSHR\0" /* 14038 */ "G_LSHR\0" /* 14045 */ "CONVERGENCECTRL_ANCHOR\0" /* 14068 */ "G_FFLOOR\0" /* 14077 */ "G_EXTRACT_SUBVECTOR\0" /* 14097 */ "G_INSERT_SUBVECTOR\0" /* 14116 */ "G_BUILD_VECTOR\0" /* 14131 */ "G_SHUFFLE_VECTOR\0" /* 14148 */ "G_SPLAT_VECTOR\0" /* 14163 */ "G_VECREDUCE_XOR\0" /* 14179 */ "G_XOR\0" /* 14185 */ "G_ATOMICRMW_XOR\0" /* 14201 */ "G_VECREDUCE_OR\0" /* 14216 */ "G_OR\0" /* 14221 */ "G_ATOMICRMW_OR\0" /* 14236 */ "G_ROTR\0" /* 14243 */ "G_INTTOPTR\0" /* 14254 */ "G_FABS\0" /* 14261 */ "G_ABS\0" /* 14267 */ "G_UNMERGE_VALUES\0" /* 14284 */ "G_MERGE_VALUES\0" /* 14299 */ "CALL_PARAMS\0" /* 14311 */ "G_FACOS\0" /* 14319 */ "G_FCOS\0" /* 14326 */ "G_CONCAT_VECTORS\0" /* 14343 */ "COPY_TO_REGCLASS\0" /* 14360 */ "G_IS_FPCLASS\0" /* 14373 */ "G_ATOMIC_CMPXCHG_WITH_SUCCESS\0" /* 14403 */ "BR_UNLESS\0" /* 14413 */ "G_VECTOR_COMPRESS\0" /* 14431 */ "G_INTRINSIC_W_SIDE_EFFECTS\0" /* 14458 */ "G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS\0" /* 14496 */ "RET_CALL_RESULTS\0" /* 14513 */ "LOAD_F16_F32_A32_S\0" /* 14532 */ "STORE_F16_F32_A32_S\0" /* 14552 */ "LOAD_F32_A32_S\0" /* 14567 */ "STORE_F32_A32_S\0" /* 14583 */ "ATOMIC_STORE16_I32_A32_S\0" /* 14608 */ "ATOMIC_STORE8_I32_A32_S\0" /* 14632 */ "ATOMIC_RMW16_U_SUB_I32_A32_S\0" /* 14661 */ "ATOMIC_RMW8_U_SUB_I32_A32_S\0" /* 14689 */ "ATOMIC_RMW_SUB_I32_A32_S\0" /* 14714 */ "ATOMIC_LOAD_I32_A32_S\0" /* 14736 */ "ATOMIC_RMW16_U_ADD_I32_A32_S\0" /* 14765 */ "ATOMIC_RMW8_U_ADD_I32_A32_S\0" /* 14793 */ "ATOMIC_RMW_ADD_I32_A32_S\0" /* 14818 */ "ATOMIC_RMW16_U_AND_I32_A32_S\0" /* 14847 */ "ATOMIC_RMW8_U_AND_I32_A32_S\0" /* 14875 */ "ATOMIC_RMW_AND_I32_A32_S\0" /* 14900 */ "ATOMIC_STORE_I32_A32_S\0" /* 14923 */ "ATOMIC_RMW16_U_CMPXCHG_I32_A32_S\0" /* 14956 */ "ATOMIC_RMW8_U_CMPXCHG_I32_A32_S\0" /* 14988 */ "ATOMIC_RMW_CMPXCHG_I32_A32_S\0" /* 15017 */ "ATOMIC_RMW16_U_XCHG_I32_A32_S\0" /* 15047 */ "ATOMIC_RMW8_U_XCHG_I32_A32_S\0" /* 15076 */ "ATOMIC_RMW_XCHG_I32_A32_S\0" /* 15102 */ "ATOMIC_RMW16_U_XOR_I32_A32_S\0" /* 15131 */ "ATOMIC_RMW8_U_XOR_I32_A32_S\0" /* 15159 */ "ATOMIC_RMW_XOR_I32_A32_S\0" /* 15184 */ "ATOMIC_RMW16_U_OR_I32_A32_S\0" /* 15212 */ "ATOMIC_RMW8_U_OR_I32_A32_S\0" /* 15239 */ "ATOMIC_RMW_OR_I32_A32_S\0" /* 15263 */ "LOAD16_S_I32_A32_S\0" /* 15282 */ "LOAD8_S_I32_A32_S\0" /* 15300 */ "ATOMIC_LOAD16_U_I32_A32_S\0" /* 15326 */ "ATOMIC_LOAD8_U_I32_A32_S\0" /* 15351 */ "MEMORY_ATOMIC_WAIT32_A32_S\0" /* 15378 */ "LOAD_LANE_32_A32_S\0" /* 15397 */ "LOAD_ZERO_32_A32_S\0" /* 15416 */ "STORE_LANE_I64x2_A32_S\0" /* 15439 */ "LOAD_EXTEND_S_I64x2_A32_S\0" /* 15465 */ "LOAD_EXTEND_U_I64x2_A32_S\0" /* 15491 */ "LOAD_F64_A32_S\0" /* 15506 */ "STORE_F64_A32_S\0" /* 15522 */ "ATOMIC_STORE32_I64_A32_S\0" /* 15547 */ "ATOMIC_STORE16_I64_A32_S\0" /* 15572 */ "ATOMIC_STORE8_I64_A32_S\0" /* 15596 */ "ATOMIC_RMW32_U_SUB_I64_A32_S\0" /* 15625 */ "ATOMIC_RMW16_U_SUB_I64_A32_S\0" /* 15654 */ "ATOMIC_RMW8_U_SUB_I64_A32_S\0" /* 15682 */ "ATOMIC_RMW_SUB_I64_A32_S\0" /* 15707 */ "ATOMIC_LOAD_I64_A32_S\0" /* 15729 */ "ATOMIC_RMW32_U_ADD_I64_A32_S\0" /* 15758 */ "ATOMIC_RMW16_U_ADD_I64_A32_S\0" /* 15787 */ "ATOMIC_RMW8_U_ADD_I64_A32_S\0" /* 15815 */ "ATOMIC_RMW_ADD_I64_A32_S\0" /* 15840 */ "ATOMIC_RMW32_U_AND_I64_A32_S\0" /* 15869 */ "ATOMIC_RMW16_U_AND_I64_A32_S\0" /* 15898 */ "ATOMIC_RMW8_U_AND_I64_A32_S\0" /* 15926 */ "ATOMIC_RMW_AND_I64_A32_S\0" /* 15951 */ "ATOMIC_STORE_I64_A32_S\0" /* 15974 */ "ATOMIC_RMW32_U_CMPXCHG_I64_A32_S\0" /* 16007 */ "ATOMIC_RMW16_U_CMPXCHG_I64_A32_S\0" /* 16040 */ "ATOMIC_RMW8_U_CMPXCHG_I64_A32_S\0" /* 16072 */ "ATOMIC_RMW_CMPXCHG_I64_A32_S\0" /* 16101 */ "ATOMIC_RMW32_U_XCHG_I64_A32_S\0" /* 16131 */ "ATOMIC_RMW16_U_XCHG_I64_A32_S\0" /* 16161 */ "ATOMIC_RMW8_U_XCHG_I64_A32_S\0" /* 16190 */ "ATOMIC_RMW_XCHG_I64_A32_S\0" /* 16216 */ "ATOMIC_RMW32_U_XOR_I64_A32_S\0" /* 16245 */ "ATOMIC_RMW16_U_XOR_I64_A32_S\0" /* 16274 */ "ATOMIC_RMW8_U_XOR_I64_A32_S\0" /* 16302 */ "ATOMIC_RMW_XOR_I64_A32_S\0" /* 16327 */ "ATOMIC_RMW32_U_OR_I64_A32_S\0" /* 16355 */ "ATOMIC_RMW16_U_OR_I64_A32_S\0" /* 16383 */ "ATOMIC_RMW8_U_OR_I64_A32_S\0" /* 16410 */ "ATOMIC_RMW_OR_I64_A32_S\0" /* 16434 */ "LOAD32_S_I64_A32_S\0" /* 16453 */ "LOAD16_S_I64_A32_S\0" /* 16472 */ "LOAD8_S_I64_A32_S\0" /* 16490 */ "ATOMIC_LOAD32_U_I64_A32_S\0" /* 16516 */ "ATOMIC_LOAD16_U_I64_A32_S\0" /* 16542 */ "ATOMIC_LOAD8_U_I64_A32_S\0" /* 16567 */ "MEMORY_ATOMIC_WAIT64_A32_S\0" /* 16594 */ "LOAD_LANE_64_A32_S\0" /* 16613 */ "LOAD_ZERO_64_A32_S\0" /* 16632 */ "STORE_LANE_I32x4_A32_S\0" /* 16655 */ "LOAD_EXTEND_S_I32x4_A32_S\0" /* 16681 */ "LOAD_EXTEND_U_I32x4_A32_S\0" /* 16707 */ "LOAD_LANE_16_A32_S\0" /* 16726 */ "STORE_LANE_I8x16_A32_S\0" /* 16749 */ "LOAD_V128_A32_S\0" /* 16765 */ "STORE_V128_A32_S\0" /* 16782 */ "LOAD_LANE_8_A32_S\0" /* 16800 */ "STORE_LANE_I16x8_A32_S\0" /* 16823 */ "LOAD_EXTEND_S_I16x8_A32_S\0" /* 16849 */ "LOAD_EXTEND_U_I16x8_A32_S\0" /* 16875 */ "anonymous_8166MEMORY_SIZE_A32_S\0" /* 16907 */ "anonymous_8883MEMORY_FILL_A32_S\0" /* 16939 */ "LOAD32_SPLAT_A32_S\0" /* 16958 */ "LOAD64_SPLAT_A32_S\0" /* 16977 */ "LOAD16_SPLAT_A32_S\0" /* 16996 */ "LOAD8_SPLAT_A32_S\0" /* 17014 */ "anonymous_8883MEMORY_INIT_A32_S\0" /* 17046 */ "anonymous_8166MEMORY_GROW_A32_S\0" /* 17078 */ "MEMORY_ATOMIC_NOTIFY_A32_S\0" /* 17105 */ "anonymous_8883MEMORY_COPY_A32_S\0" /* 17137 */ "FP_TO_SINT_I32_F32_S\0" /* 17158 */ "FP_TO_UINT_I32_F32_S\0" /* 17179 */ "FP_TO_SINT_I64_F32_S\0" /* 17200 */ "FP_TO_UINT_I64_F32_S\0" /* 17221 */ "SUB_F32_S\0" /* 17231 */ "TRUNC_F32_S\0" /* 17243 */ "ADD_F32_S\0" /* 17253 */ "LOCAL_TEE_F32_S\0" /* 17269 */ "GE_F32_S\0" /* 17278 */ "LE_F32_S\0" /* 17287 */ "NE_F32_S\0" /* 17296 */ "F64_PROMOTE_F32_S\0" /* 17314 */ "NEG_F32_S\0" /* 17324 */ "CEIL_F32_S\0" /* 17335 */ "MUL_F32_S\0" /* 17345 */ "COPYSIGN_F32_S\0" /* 17360 */ "MIN_F32_S\0" /* 17370 */ "DROP_F32_S\0" /* 17381 */ "EQ_F32_S\0" /* 17390 */ "FLOOR_F32_S\0" /* 17402 */ "ABS_F32_S\0" /* 17412 */ "I32_TRUNC_S_F32_S\0" /* 17430 */ "I64_TRUNC_S_F32_S\0" /* 17448 */ "I32_TRUNC_S_SAT_F32_S\0" /* 17470 */ "I64_TRUNC_S_SAT_F32_S\0" /* 17492 */ "I32_TRUNC_U_SAT_F32_S\0" /* 17514 */ "I64_TRUNC_U_SAT_F32_S\0" /* 17536 */ "SELECT_F32_S\0" /* 17549 */ "GLOBAL_GET_F32_S\0" /* 17566 */ "LOCAL_GET_F32_S\0" /* 17582 */ "I32_REINTERPRET_F32_S\0" /* 17604 */ "GLOBAL_SET_F32_S\0" /* 17621 */ "LOCAL_SET_F32_S\0" /* 17637 */ "GT_F32_S\0" /* 17646 */ "LT_F32_S\0" /* 17655 */ "SQRT_F32_S\0" /* 17666 */ "NEAREST_F32_S\0" /* 17680 */ "CONST_F32_S\0" /* 17692 */ "I32_TRUNC_U_F32_S\0" /* 17710 */ "I64_TRUNC_U_F32_S\0" /* 17728 */ "DIV_F32_S\0" /* 17738 */ "MAX_F32_S\0" /* 17748 */ "COPY_F32_S\0" /* 17759 */ "SUB_I32_S\0" /* 17769 */ "ADD_I32_S\0" /* 17779 */ "AND_I32_S\0" /* 17789 */ "LOCAL_TEE_I32_S\0" /* 17805 */ "BR_TABLE_I32_S\0" /* 17820 */ "NE_I32_S\0" /* 17829 */ "SHL_I32_S\0" /* 17839 */ "ROTL_I32_S\0" /* 17850 */ "MUL_I32_S\0" /* 17860 */ "DROP_I32_S\0" /* 17871 */ "EQ_I32_S\0" /* 17880 */ "XOR_I32_S\0" /* 17890 */ "ROTR_I32_S\0" /* 17901 */ "I32_EXTEND16_S_I32_S\0" /* 17922 */ "I32_EXTEND8_S_I32_S\0" /* 17942 */ "I64_EXTEND_S_I32_S\0" /* 17961 */ "GE_S_I32_S\0" /* 17972 */ "LE_S_I32_S\0" /* 17983 */ "REM_S_I32_S\0" /* 17995 */ "SHR_S_I32_S\0" /* 18007 */ "GT_S_I32_S\0" /* 18018 */ "LT_S_I32_S\0" /* 18029 */ "F32_CONVERT_S_I32_S\0" /* 18049 */ "F64_CONVERT_S_I32_S\0" /* 18069 */ "DIV_S_I32_S\0" /* 18081 */ "SELECT_I32_S\0" /* 18094 */ "GLOBAL_GET_I32_S\0" /* 18111 */ "LOCAL_GET_I32_S\0" /* 18127 */ "F32_REINTERPRET_I32_S\0" /* 18149 */ "GLOBAL_SET_I32_S\0" /* 18166 */ "LOCAL_SET_I32_S\0" /* 18182 */ "POPCNT_I32_S\0" /* 18195 */ "CONST_I32_S\0" /* 18207 */ "I64_EXTEND_U_I32_S\0" /* 18226 */ "GE_U_I32_S\0" /* 18237 */ "LE_U_I32_S\0" /* 18248 */ "REM_U_I32_S\0" /* 18260 */ "SHR_U_I32_S\0" /* 18272 */ "GT_U_I32_S\0" /* 18283 */ "LT_U_I32_S\0" /* 18294 */ "F32_CONVERT_U_I32_S\0" /* 18314 */ "F64_CONVERT_U_I32_S\0" /* 18334 */ "DIV_U_I32_S\0" /* 18346 */ "COPY_I32_S\0" /* 18357 */ "CLZ_I32_S\0" /* 18367 */ "EQZ_I32_S\0" /* 18377 */ "CTZ_I32_S\0" /* 18387 */ "ARGUMENT_v4f32_S\0" /* 18404 */ "ARGUMENT_f32_S\0" /* 18419 */ "ARGUMENT_v4i32_S\0" /* 18436 */ "ARGUMENT_i32_S\0" /* 18451 */ "CONST_V128_F64x2_S\0" /* 18470 */ "SUB_F64x2_S\0" /* 18482 */ "TRUNC_F64x2_S\0" /* 18496 */ "NMADD_F64x2_S\0" /* 18510 */ "GE_F64x2_S\0" /* 18521 */ "LE_F64x2_S\0" /* 18532 */ "REPLACE_LANE_F64x2_S\0" /* 18553 */ "EXTRACT_LANE_F64x2_S\0" /* 18574 */ "NEG_F64x2_S\0" /* 18586 */ "CEIL_F64x2_S\0" /* 18599 */ "MUL_F64x2_S\0" /* 18611 */ "SIMD_RELAXED_FMIN_F64x2_S\0" /* 18637 */ "PMIN_F64x2_S\0" /* 18650 */ "EQ_F64x2_S\0" /* 18661 */ "FLOOR_F64x2_S\0" /* 18675 */ "ABS_F64x2_S\0" /* 18687 */ "SPLAT_F64x2_S\0" /* 18701 */ "GT_F64x2_S\0" /* 18712 */ "LT_F64x2_S\0" /* 18723 */ "SQRT_F64x2_S\0" /* 18736 */ "NEAREST_F64x2_S\0" /* 18752 */ "DIV_F64x2_S\0" /* 18764 */ "SIMD_RELAXED_FMAX_F64x2_S\0" /* 18790 */ "PMAX_F64x2_S\0" /* 18803 */ "convert_low_s_F64x2_S\0" /* 18825 */ "convert_low_u_F64x2_S\0" /* 18847 */ "promote_low_F64x2_S\0" /* 18867 */ "CONST_V128_I64x2_S\0" /* 18886 */ "SUB_I64x2_S\0" /* 18898 */ "ADD_I64x2_S\0" /* 18910 */ "REPLACE_LANE_I64x2_S\0" /* 18931 */ "EXTRACT_LANE_I64x2_S\0" /* 18952 */ "ALLTRUE_I64x2_S\0" /* 18968 */ "NEG_I64x2_S\0" /* 18980 */ "BITMASK_I64x2_S\0" /* 18996 */ "SHL_I64x2_S\0" /* 19008 */ "MUL_I64x2_S\0" /* 19020 */ "EQ_I64x2_S\0" /* 19031 */ "ABS_I64x2_S\0" /* 19043 */ "GE_S_I64x2_S\0" /* 19056 */ "LE_S_I64x2_S\0" /* 19069 */ "EXTMUL_HIGH_S_I64x2_S\0" /* 19091 */ "SHR_S_I64x2_S\0" /* 19105 */ "GT_S_I64x2_S\0" /* 19118 */ "LT_S_I64x2_S\0" /* 19131 */ "EXTMUL_LOW_S_I64x2_S\0" /* 19152 */ "SPLAT_I64x2_S\0" /* 19166 */ "LANESELECT_I64x2_S\0" /* 19185 */ "EXTMUL_HIGH_U_I64x2_S\0" /* 19207 */ "SHR_U_I64x2_S\0" /* 19221 */ "EXTMUL_LOW_U_I64x2_S\0" /* 19242 */ "extend_high_s_I64x2_S\0" /* 19264 */ "extend_low_s_I64x2_S\0" /* 19285 */ "extend_high_u_I64x2_S\0" /* 19307 */ "extend_low_u_I64x2_S\0" /* 19328 */ "LOAD_F16_F32_A64_S\0" /* 19347 */ "STORE_F16_F32_A64_S\0" /* 19367 */ "LOAD_F32_A64_S\0" /* 19382 */ "STORE_F32_A64_S\0" /* 19398 */ "ATOMIC_STORE16_I32_A64_S\0" /* 19423 */ "ATOMIC_STORE8_I32_A64_S\0" /* 19447 */ "ATOMIC_RMW16_U_SUB_I32_A64_S\0" /* 19476 */ "ATOMIC_RMW8_U_SUB_I32_A64_S\0" /* 19504 */ "ATOMIC_RMW_SUB_I32_A64_S\0" /* 19529 */ "ATOMIC_LOAD_I32_A64_S\0" /* 19551 */ "ATOMIC_RMW16_U_ADD_I32_A64_S\0" /* 19580 */ "ATOMIC_RMW8_U_ADD_I32_A64_S\0" /* 19608 */ "ATOMIC_RMW_ADD_I32_A64_S\0" /* 19633 */ "ATOMIC_RMW16_U_AND_I32_A64_S\0" /* 19662 */ "ATOMIC_RMW8_U_AND_I32_A64_S\0" /* 19690 */ "ATOMIC_RMW_AND_I32_A64_S\0" /* 19715 */ "ATOMIC_STORE_I32_A64_S\0" /* 19738 */ "ATOMIC_RMW16_U_CMPXCHG_I32_A64_S\0" /* 19771 */ "ATOMIC_RMW8_U_CMPXCHG_I32_A64_S\0" /* 19803 */ "ATOMIC_RMW_CMPXCHG_I32_A64_S\0" /* 19832 */ "ATOMIC_RMW16_U_XCHG_I32_A64_S\0" /* 19862 */ "ATOMIC_RMW8_U_XCHG_I32_A64_S\0" /* 19891 */ "ATOMIC_RMW_XCHG_I32_A64_S\0" /* 19917 */ "ATOMIC_RMW16_U_XOR_I32_A64_S\0" /* 19946 */ "ATOMIC_RMW8_U_XOR_I32_A64_S\0" /* 19974 */ "ATOMIC_RMW_XOR_I32_A64_S\0" /* 19999 */ "ATOMIC_RMW16_U_OR_I32_A64_S\0" /* 20027 */ "ATOMIC_RMW8_U_OR_I32_A64_S\0" /* 20054 */ "ATOMIC_RMW_OR_I32_A64_S\0" /* 20078 */ "LOAD16_S_I32_A64_S\0" /* 20097 */ "LOAD8_S_I32_A64_S\0" /* 20115 */ "ATOMIC_LOAD16_U_I32_A64_S\0" /* 20141 */ "ATOMIC_LOAD8_U_I32_A64_S\0" /* 20166 */ "MEMORY_ATOMIC_WAIT32_A64_S\0" /* 20193 */ "LOAD_LANE_32_A64_S\0" /* 20212 */ "LOAD_ZERO_32_A64_S\0" /* 20231 */ "STORE_LANE_I64x2_A64_S\0" /* 20254 */ "LOAD_EXTEND_S_I64x2_A64_S\0" /* 20280 */ "LOAD_EXTEND_U_I64x2_A64_S\0" /* 20306 */ "LOAD_F64_A64_S\0" /* 20321 */ "STORE_F64_A64_S\0" /* 20337 */ "ATOMIC_STORE32_I64_A64_S\0" /* 20362 */ "ATOMIC_STORE16_I64_A64_S\0" /* 20387 */ "ATOMIC_STORE8_I64_A64_S\0" /* 20411 */ "ATOMIC_RMW32_U_SUB_I64_A64_S\0" /* 20440 */ "ATOMIC_RMW16_U_SUB_I64_A64_S\0" /* 20469 */ "ATOMIC_RMW8_U_SUB_I64_A64_S\0" /* 20497 */ "ATOMIC_RMW_SUB_I64_A64_S\0" /* 20522 */ "ATOMIC_LOAD_I64_A64_S\0" /* 20544 */ "ATOMIC_RMW32_U_ADD_I64_A64_S\0" /* 20573 */ "ATOMIC_RMW16_U_ADD_I64_A64_S\0" /* 20602 */ "ATOMIC_RMW8_U_ADD_I64_A64_S\0" /* 20630 */ "ATOMIC_RMW_ADD_I64_A64_S\0" /* 20655 */ "ATOMIC_RMW32_U_AND_I64_A64_S\0" /* 20684 */ "ATOMIC_RMW16_U_AND_I64_A64_S\0" /* 20713 */ "ATOMIC_RMW8_U_AND_I64_A64_S\0" /* 20741 */ "ATOMIC_RMW_AND_I64_A64_S\0" /* 20766 */ "ATOMIC_STORE_I64_A64_S\0" /* 20789 */ "ATOMIC_RMW32_U_CMPXCHG_I64_A64_S\0" /* 20822 */ "ATOMIC_RMW16_U_CMPXCHG_I64_A64_S\0" /* 20855 */ "ATOMIC_RMW8_U_CMPXCHG_I64_A64_S\0" /* 20887 */ "ATOMIC_RMW_CMPXCHG_I64_A64_S\0" /* 20916 */ "ATOMIC_RMW32_U_XCHG_I64_A64_S\0" /* 20946 */ "ATOMIC_RMW16_U_XCHG_I64_A64_S\0" /* 20976 */ "ATOMIC_RMW8_U_XCHG_I64_A64_S\0" /* 21005 */ "ATOMIC_RMW_XCHG_I64_A64_S\0" /* 21031 */ "ATOMIC_RMW32_U_XOR_I64_A64_S\0" /* 21060 */ "ATOMIC_RMW16_U_XOR_I64_A64_S\0" /* 21089 */ "ATOMIC_RMW8_U_XOR_I64_A64_S\0" /* 21117 */ "ATOMIC_RMW_XOR_I64_A64_S\0" /* 21142 */ "ATOMIC_RMW32_U_OR_I64_A64_S\0" /* 21170 */ "ATOMIC_RMW16_U_OR_I64_A64_S\0" /* 21198 */ "ATOMIC_RMW8_U_OR_I64_A64_S\0" /* 21225 */ "ATOMIC_RMW_OR_I64_A64_S\0" /* 21249 */ "LOAD32_S_I64_A64_S\0" /* 21268 */ "LOAD16_S_I64_A64_S\0" /* 21287 */ "LOAD8_S_I64_A64_S\0" /* 21305 */ "ATOMIC_LOAD32_U_I64_A64_S\0" /* 21331 */ "ATOMIC_LOAD16_U_I64_A64_S\0" /* 21357 */ "ATOMIC_LOAD8_U_I64_A64_S\0" /* 21382 */ "MEMORY_ATOMIC_WAIT64_A64_S\0" /* 21409 */ "LOAD_LANE_64_A64_S\0" /* 21428 */ "LOAD_ZERO_64_A64_S\0" /* 21447 */ "STORE_LANE_I32x4_A64_S\0" /* 21470 */ "LOAD_EXTEND_S_I32x4_A64_S\0" /* 21496 */ "LOAD_EXTEND_U_I32x4_A64_S\0" /* 21522 */ "LOAD_LANE_16_A64_S\0" /* 21541 */ "STORE_LANE_I8x16_A64_S\0" /* 21564 */ "LOAD_V128_A64_S\0" /* 21580 */ "STORE_V128_A64_S\0" /* 21597 */ "LOAD_LANE_8_A64_S\0" /* 21615 */ "STORE_LANE_I16x8_A64_S\0" /* 21638 */ "LOAD_EXTEND_S_I16x8_A64_S\0" /* 21664 */ "LOAD_EXTEND_U_I16x8_A64_S\0" /* 21690 */ "anonymous_8167MEMORY_SIZE_A64_S\0" /* 21722 */ "anonymous_8884MEMORY_FILL_A64_S\0" /* 21754 */ "LOAD32_SPLAT_A64_S\0" /* 21773 */ "LOAD64_SPLAT_A64_S\0" /* 21792 */ "LOAD16_SPLAT_A64_S\0" /* 21811 */ "LOAD8_SPLAT_A64_S\0" /* 21829 */ "anonymous_8884MEMORY_INIT_A64_S\0" /* 21861 */ "anonymous_8167MEMORY_GROW_A64_S\0" /* 21893 */ "MEMORY_ATOMIC_NOTIFY_A64_S\0" /* 21920 */ "anonymous_8884MEMORY_COPY_A64_S\0" /* 21952 */ "FP_TO_SINT_I32_F64_S\0" /* 21973 */ "FP_TO_UINT_I32_F64_S\0" /* 21994 */ "FP_TO_SINT_I64_F64_S\0" /* 22015 */ "FP_TO_UINT_I64_F64_S\0" /* 22036 */ "SUB_F64_S\0" /* 22046 */ "TRUNC_F64_S\0" /* 22058 */ "ADD_F64_S\0" /* 22068 */ "LOCAL_TEE_F64_S\0" /* 22084 */ "GE_F64_S\0" /* 22093 */ "LE_F64_S\0" /* 22102 */ "NE_F64_S\0" /* 22111 */ "F32_DEMOTE_F64_S\0" /* 22128 */ "NEG_F64_S\0" /* 22138 */ "CEIL_F64_S\0" /* 22149 */ "MUL_F64_S\0" /* 22159 */ "COPYSIGN_F64_S\0" /* 22174 */ "MIN_F64_S\0" /* 22184 */ "DROP_F64_S\0" /* 22195 */ "EQ_F64_S\0" /* 22204 */ "FLOOR_F64_S\0" /* 22216 */ "ABS_F64_S\0" /* 22226 */ "I32_TRUNC_S_F64_S\0" /* 22244 */ "I64_TRUNC_S_F64_S\0" /* 22262 */ "I32_TRUNC_S_SAT_F64_S\0" /* 22284 */ "I64_TRUNC_S_SAT_F64_S\0" /* 22306 */ "I32_TRUNC_U_SAT_F64_S\0" /* 22328 */ "I64_TRUNC_U_SAT_F64_S\0" /* 22350 */ "SELECT_F64_S\0" /* 22363 */ "GLOBAL_GET_F64_S\0" /* 22380 */ "LOCAL_GET_F64_S\0" /* 22396 */ "I64_REINTERPRET_F64_S\0" /* 22418 */ "GLOBAL_SET_F64_S\0" /* 22435 */ "LOCAL_SET_F64_S\0" /* 22451 */ "GT_F64_S\0" /* 22460 */ "LT_F64_S\0" /* 22469 */ "SQRT_F64_S\0" /* 22480 */ "NEAREST_F64_S\0" /* 22494 */ "CONST_F64_S\0" /* 22506 */ "I32_TRUNC_U_F64_S\0" /* 22524 */ "I64_TRUNC_U_F64_S\0" /* 22542 */ "DIV_F64_S\0" /* 22552 */ "MAX_F64_S\0" /* 22562 */ "COPY_F64_S\0" /* 22573 */ "SUB_I64_S\0" /* 22583 */ "ADD_I64_S\0" /* 22593 */ "AND_I64_S\0" /* 22603 */ "LOCAL_TEE_I64_S\0" /* 22619 */ "BR_TABLE_I64_S\0" /* 22634 */ "NE_I64_S\0" /* 22643 */ "SHL_I64_S\0" /* 22653 */ "ROTL_I64_S\0" /* 22664 */ "MUL_I64_S\0" /* 22674 */ "I32_WRAP_I64_S\0" /* 22689 */ "DROP_I64_S\0" /* 22700 */ "EQ_I64_S\0" /* 22709 */ "XOR_I64_S\0" /* 22719 */ "ROTR_I64_S\0" /* 22730 */ "I64_EXTEND32_S_I64_S\0" /* 22751 */ "I64_EXTEND16_S_I64_S\0" /* 22772 */ "I64_EXTEND8_S_I64_S\0" /* 22792 */ "GE_S_I64_S\0" /* 22803 */ "LE_S_I64_S\0" /* 22814 */ "REM_S_I64_S\0" /* 22826 */ "SHR_S_I64_S\0" /* 22838 */ "GT_S_I64_S\0" /* 22849 */ "LT_S_I64_S\0" /* 22860 */ "F32_CONVERT_S_I64_S\0" /* 22880 */ "F64_CONVERT_S_I64_S\0" /* 22900 */ "DIV_S_I64_S\0" /* 22912 */ "SELECT_I64_S\0" /* 22925 */ "GLOBAL_GET_I64_S\0" /* 22942 */ "LOCAL_GET_I64_S\0" /* 22958 */ "F64_REINTERPRET_I64_S\0" /* 22980 */ "GLOBAL_SET_I64_S\0" /* 22997 */ "LOCAL_SET_I64_S\0" /* 23013 */ "POPCNT_I64_S\0" /* 23026 */ "CONST_I64_S\0" /* 23038 */ "GE_U_I64_S\0" /* 23049 */ "LE_U_I64_S\0" /* 23060 */ "REM_U_I64_S\0" /* 23072 */ "SHR_U_I64_S\0" /* 23084 */ "GT_U_I64_S\0" /* 23095 */ "LT_U_I64_S\0" /* 23106 */ "F32_CONVERT_U_I64_S\0" /* 23126 */ "F64_CONVERT_U_I64_S\0" /* 23146 */ "DIV_U_I64_S\0" /* 23158 */ "COPY_I64_S\0" /* 23169 */ "CLZ_I64_S\0" /* 23179 */ "EQZ_I64_S\0" /* 23189 */ "CTZ_I64_S\0" /* 23199 */ "ARGUMENT_v2f64_S\0" /* 23216 */ "ARGUMENT_f64_S\0" /* 23231 */ "ARGUMENT_v2i64_S\0" /* 23248 */ "ARGUMENT_i64_S\0" /* 23263 */ "CONST_V128_F32x4_S\0" /* 23282 */ "SUB_F32x4_S\0" /* 23294 */ "TRUNC_F32x4_S\0" /* 23308 */ "NMADD_F32x4_S\0" /* 23322 */ "GE_F32x4_S\0" /* 23333 */ "LE_F32x4_S\0" /* 23344 */ "REPLACE_LANE_F32x4_S\0" /* 23365 */ "EXTRACT_LANE_F32x4_S\0" /* 23386 */ "NEG_F32x4_S\0" /* 23398 */ "CEIL_F32x4_S\0" /* 23411 */ "MUL_F32x4_S\0" /* 23423 */ "SIMD_RELAXED_FMIN_F32x4_S\0" /* 23449 */ "PMIN_F32x4_S\0" /* 23462 */ "EQ_F32x4_S\0" /* 23473 */ "FLOOR_F32x4_S\0" /* 23487 */ "ABS_F32x4_S\0" /* 23499 */ "SPLAT_F32x4_S\0" /* 23513 */ "GT_F32x4_S\0" /* 23524 */ "LT_F32x4_S\0" /* 23535 */ "SQRT_F32x4_S\0" /* 23548 */ "NEAREST_F32x4_S\0" /* 23564 */ "DIV_F32x4_S\0" /* 23576 */ "SIMD_RELAXED_FMAX_F32x4_S\0" /* 23602 */ "PMAX_F32x4_S\0" /* 23615 */ "demote_zero_F32x4_S\0" /* 23635 */ "sint_to_fp_F32x4_S\0" /* 23654 */ "uint_to_fp_F32x4_S\0" /* 23673 */ "CONST_V128_I32x4_S\0" /* 23692 */ "SUB_I32x4_S\0" /* 23704 */ "ADD_I32x4_S\0" /* 23716 */ "REPLACE_LANE_I32x4_S\0" /* 23737 */ "EXTRACT_LANE_I32x4_S\0" /* 23758 */ "ALLTRUE_I32x4_S\0" /* 23774 */ "NEG_I32x4_S\0" /* 23786 */ "BITMASK_I32x4_S\0" /* 23802 */ "SHL_I32x4_S\0" /* 23814 */ "MUL_I32x4_S\0" /* 23826 */ "EQ_I32x4_S\0" /* 23837 */ "ABS_I32x4_S\0" /* 23849 */ "GE_S_I32x4_S\0" /* 23862 */ "LE_S_I32x4_S\0" /* 23875 */ "EXTMUL_HIGH_S_I32x4_S\0" /* 23897 */ "MIN_S_I32x4_S\0" /* 23911 */ "SHR_S_I32x4_S\0" /* 23925 */ "GT_S_I32x4_S\0" /* 23938 */ "LT_S_I32x4_S\0" /* 23951 */ "EXTMUL_LOW_S_I32x4_S\0" /* 23972 */ "MAX_S_I32x4_S\0" /* 23986 */ "SPLAT_I32x4_S\0" /* 24000 */ "LANESELECT_I32x4_S\0" /* 24019 */ "GE_U_I32x4_S\0" /* 24032 */ "LE_U_I32x4_S\0" /* 24045 */ "EXTMUL_HIGH_U_I32x4_S\0" /* 24067 */ "MIN_U_I32x4_S\0" /* 24081 */ "SHR_U_I32x4_S\0" /* 24095 */ "GT_U_I32x4_S\0" /* 24108 */ "LT_U_I32x4_S\0" /* 24121 */ "EXTMUL_LOW_U_I32x4_S\0" /* 24142 */ "MAX_U_I32x4_S\0" /* 24156 */ "int_wasm_relaxed_trunc_signed_I32x4_S\0" /* 24194 */ "int_wasm_extadd_pairwise_signed_I32x4_S\0" /* 24234 */ "int_wasm_relaxed_trunc_unsigned_I32x4_S\0" /* 24274 */ "int_wasm_extadd_pairwise_unsigned_I32x4_S\0" /* 24316 */ "int_wasm_relaxed_trunc_signed_zero_I32x4_S\0" /* 24359 */ "int_wasm_relaxed_trunc_unsigned_zero_I32x4_S\0" /* 24404 */ "extend_high_s_I32x4_S\0" /* 24426 */ "trunc_sat_zero_s_I32x4_S\0" /* 24451 */ "extend_low_s_I32x4_S\0" /* 24472 */ "fp_to_sint_I32x4_S\0" /* 24491 */ "fp_to_uint_I32x4_S\0" /* 24510 */ "extend_high_u_I32x4_S\0" /* 24532 */ "trunc_sat_zero_u_I32x4_S\0" /* 24557 */ "extend_low_u_I32x4_S\0" /* 24578 */ "ARGUMENT_v8f16_S\0" /* 24595 */ "ARGUMENT_v8i16_S\0" /* 24612 */ "CONST_V128_I8x16_S\0" /* 24631 */ "SUB_I8x16_S\0" /* 24643 */ "ADD_I8x16_S\0" /* 24655 */ "REPLACE_LANE_I8x16_S\0" /* 24676 */ "ALLTRUE_I8x16_S\0" /* 24692 */ "NEG_I8x16_S\0" /* 24704 */ "BITMASK_I8x16_S\0" /* 24720 */ "SHL_I8x16_S\0" /* 24732 */ "EQ_I8x16_S\0" /* 24743 */ "ABS_I8x16_S\0" /* 24755 */ "GE_S_I8x16_S\0" /* 24768 */ "LE_S_I8x16_S\0" /* 24781 */ "MIN_S_I8x16_S\0" /* 24795 */ "SHR_S_I8x16_S\0" /* 24809 */ "SUB_SAT_S_I8x16_S\0" /* 24827 */ "ADD_SAT_S_I8x16_S\0" /* 24845 */ "GT_S_I8x16_S\0" /* 24858 */ "LT_S_I8x16_S\0" /* 24871 */ "NARROW_S_I8x16_S\0" /* 24888 */ "MAX_S_I8x16_S\0" /* 24902 */ "SPLAT_I8x16_S\0" /* 24916 */ "LANESELECT_I8x16_S\0" /* 24935 */ "POPCNT_I8x16_S\0" /* 24950 */ "GE_U_I8x16_S\0" /* 24963 */ "LE_U_I8x16_S\0" /* 24976 */ "MIN_U_I8x16_S\0" /* 24990 */ "AVGR_U_I8x16_S\0" /* 25005 */ "SHR_U_I8x16_S\0" /* 25019 */ "SUB_SAT_U_I8x16_S\0" /* 25037 */ "ADD_SAT_U_I8x16_S\0" /* 25055 */ "GT_U_I8x16_S\0" /* 25068 */ "LT_U_I8x16_S\0" /* 25081 */ "NARROW_U_I8x16_S\0" /* 25098 */ "MAX_U_I8x16_S\0" /* 25112 */ "LOCAL_TEE_V128_S\0" /* 25129 */ "DROP_V128_S\0" /* 25141 */ "SELECT_V128_S\0" /* 25155 */ "GLOBAL_GET_V128_S\0" /* 25173 */ "LOCAL_GET_V128_S\0" /* 25190 */ "GLOBAL_SET_V128_S\0" /* 25208 */ "LOCAL_SET_V128_S\0" /* 25225 */ "COPY_V128_S\0" /* 25237 */ "ARGUMENT_v16i8_S\0" /* 25254 */ "SUB_F16x8_S\0" /* 25266 */ "TRUNC_F16x8_S\0" /* 25280 */ "NMADD_F16x8_S\0" /* 25294 */ "GE_F16x8_S\0" /* 25305 */ "LE_F16x8_S\0" /* 25316 */ "REPLACE_LANE_F16x8_S\0" /* 25337 */ "EXTRACT_LANE_F16x8_S\0" /* 25358 */ "NEG_F16x8_S\0" /* 25370 */ "CEIL_F16x8_S\0" /* 25383 */ "MUL_F16x8_S\0" /* 25395 */ "PMIN_F16x8_S\0" /* 25408 */ "EQ_F16x8_S\0" /* 25419 */ "FLOOR_F16x8_S\0" /* 25433 */ "ABS_F16x8_S\0" /* 25445 */ "SPLAT_F16x8_S\0" /* 25459 */ "GT_F16x8_S\0" /* 25470 */ "LT_F16x8_S\0" /* 25481 */ "SQRT_F16x8_S\0" /* 25494 */ "NEAREST_F16x8_S\0" /* 25510 */ "DIV_F16x8_S\0" /* 25522 */ "PMAX_F16x8_S\0" /* 25535 */ "sint_to_fp_F16x8_S\0" /* 25554 */ "uint_to_fp_F16x8_S\0" /* 25573 */ "CONST_V128_I16x8_S\0" /* 25592 */ "SUB_I16x8_S\0" /* 25604 */ "ADD_I16x8_S\0" /* 25616 */ "REPLACE_LANE_I16x8_S\0" /* 25637 */ "ALLTRUE_I16x8_S\0" /* 25653 */ "NEG_I16x8_S\0" /* 25665 */ "BITMASK_I16x8_S\0" /* 25681 */ "SHL_I16x8_S\0" /* 25693 */ "MUL_I16x8_S\0" /* 25705 */ "EQ_I16x8_S\0" /* 25716 */ "ABS_I16x8_S\0" /* 25728 */ "GE_S_I16x8_S\0" /* 25741 */ "LE_S_I16x8_S\0" /* 25754 */ "EXTMUL_HIGH_S_I16x8_S\0" /* 25776 */ "MIN_S_I16x8_S\0" /* 25790 */ "SHR_S_I16x8_S\0" /* 25804 */ "RELAXED_Q15MULR_S_I16x8_S\0" /* 25830 */ "SUB_SAT_S_I16x8_S\0" /* 25848 */ "ADD_SAT_S_I16x8_S\0" /* 25866 */ "Q15MULR_SAT_S_I16x8_S\0" /* 25888 */ "GT_S_I16x8_S\0" /* 25901 */ "LT_S_I16x8_S\0" /* 25914 */ "EXTMUL_LOW_S_I16x8_S\0" /* 25935 */ "NARROW_S_I16x8_S\0" /* 25952 */ "MAX_S_I16x8_S\0" /* 25966 */ "SPLAT_I16x8_S\0" /* 25980 */ "LANESELECT_I16x8_S\0" /* 25999 */ "GE_U_I16x8_S\0" /* 26012 */ "LE_U_I16x8_S\0" /* 26025 */ "EXTMUL_HIGH_U_I16x8_S\0" /* 26047 */ "MIN_U_I16x8_S\0" /* 26061 */ "AVGR_U_I16x8_S\0" /* 26076 */ "SHR_U_I16x8_S\0" /* 26090 */ "SUB_SAT_U_I16x8_S\0" /* 26108 */ "ADD_SAT_U_I16x8_S\0" /* 26126 */ "GT_U_I16x8_S\0" /* 26139 */ "LT_U_I16x8_S\0" /* 26152 */ "EXTMUL_LOW_U_I16x8_S\0" /* 26173 */ "NARROW_U_I16x8_S\0" /* 26190 */ "MAX_U_I16x8_S\0" /* 26204 */ "int_wasm_extadd_pairwise_signed_I16x8_S\0" /* 26244 */ "int_wasm_extadd_pairwise_unsigned_I16x8_S\0" /* 26286 */ "extend_high_s_I16x8_S\0" /* 26308 */ "extend_low_s_I16x8_S\0" /* 26329 */ "fp_to_sint_I16x8_S\0" /* 26348 */ "fp_to_uint_I16x8_S\0" /* 26367 */ "extend_high_u_I16x8_S\0" /* 26389 */ "extend_low_u_I16x8_S\0" /* 26410 */ "RELAXED_DOT_ADD_S\0" /* 26428 */ "AND_S\0" /* 26434 */ "END_S\0" /* 26440 */ "ATOMIC_FENCE_S\0" /* 26455 */ "COMPILER_FENCE_S\0" /* 26472 */ "DEBUG_UNREACHABLE_S\0" /* 26492 */ "SHUFFLE_S\0" /* 26502 */ "RELAXED_SWIZZLE_S\0" /* 26520 */ "ELSE_S\0" /* 26527 */ "DELEGATE_S\0" /* 26538 */ "ANYTRUE_S\0" /* 26548 */ "TABLE_SIZE_S\0" /* 26561 */ "LOCAL_TEE_FUNCREF_S\0" /* 26581 */ "TABLE_FILL_FUNCREF_S\0" /* 26602 */ "REF_NULL_FUNCREF_S\0" /* 26621 */ "REF_IS_NULL_FUNCREF_S\0" /* 26643 */ "DROP_FUNCREF_S\0" /* 26658 */ "SELECT_FUNCREF_S\0" /* 26675 */ "TABLE_GET_FUNCREF_S\0" /* 26695 */ "GLOBAL_GET_FUNCREF_S\0" /* 26716 */ "LOCAL_GET_FUNCREF_S\0" /* 26736 */ "TABLE_SET_FUNCREF_S\0" /* 26756 */ "GLOBAL_SET_FUNCREF_S\0" /* 26777 */ "LOCAL_SET_FUNCREF_S\0" /* 26797 */ "TABLE_GROW_FUNCREF_S\0" /* 26818 */ "COPY_FUNCREF_S\0" /* 26833 */ "LOCAL_TEE_EXTERNREF_S\0" /* 26855 */ "TABLE_FILL_EXTERNREF_S\0" /* 26878 */ "REF_NULL_EXTERNREF_S\0" /* 26899 */ "REF_IS_NULL_EXTERNREF_S\0" /* 26923 */ "DROP_EXTERNREF_S\0" /* 26940 */ "SELECT_EXTERNREF_S\0" /* 26959 */ "TABLE_GET_EXTERNREF_S\0" /* 26981 */ "GLOBAL_GET_EXTERNREF_S\0" /* 27004 */ "LOCAL_GET_EXTERNREF_S\0" /* 27026 */ "TABLE_SET_EXTERNREF_S\0" /* 27048 */ "GLOBAL_SET_EXTERNREF_S\0" /* 27071 */ "LOCAL_SET_EXTERNREF_S\0" /* 27093 */ "TABLE_GROW_EXTERNREF_S\0" /* 27116 */ "COPY_EXTERNREF_S\0" /* 27133 */ "LOCAL_TEE_EXNREF_S\0" /* 27152 */ "TABLE_FILL_EXNREF_S\0" /* 27172 */ "REF_NULL_EXNREF_S\0" /* 27190 */ "REF_IS_NULL_EXNREF_S\0" /* 27211 */ "DROP_EXNREF_S\0" /* 27225 */ "SELECT_EXNREF_S\0" /* 27241 */ "TABLE_GET_EXNREF_S\0" /* 27260 */ "GLOBAL_GET_EXNREF_S\0" /* 27280 */ "LOCAL_GET_EXNREF_S\0" /* 27299 */ "TABLE_SET_EXNREF_S\0" /* 27318 */ "GLOBAL_SET_EXNREF_S\0" /* 27338 */ "LOCAL_SET_EXNREF_S\0" /* 27357 */ "TABLE_GROW_EXNREF_S\0" /* 27377 */ "COPY_EXNREF_S\0" /* 27391 */ "END_IF_S\0" /* 27400 */ "BR_IF_S\0" /* 27408 */ "CATCH_S\0" /* 27416 */ "END_BLOCK_S\0" /* 27428 */ "RET_CALL_S\0" /* 27439 */ "CATCH_ALL_S\0" /* 27451 */ "END_FUNCTION_S\0" /* 27466 */ "FALLTHROUGH_RETURN_S\0" /* 27487 */ "ADJCALLSTACKDOWN_S\0" /* 27506 */ "NOP_S\0" /* 27512 */ "END_LOOP_S\0" /* 27523 */ "anonymous_8883DATA_DROP_S\0" /* 27549 */ "anonymous_8884DATA_DROP_S\0" /* 27575 */ "ADJCALLSTACKUP_S\0" /* 27592 */ "BR_S\0" /* 27597 */ "XOR_S\0" /* 27603 */ "CALL_PARAMS_S\0" /* 27617 */ "BR_UNLESS_S\0" /* 27629 */ "RET_CALL_RESULTS_S\0" /* 27648 */ "RELAXED_DOT_BFLOAT_S\0" /* 27669 */ "BITSELECT_S\0" /* 27681 */ "RET_CALL_INDIRECT_S\0" /* 27701 */ "CATCHRET_S\0" /* 27712 */ "CLEANUPRET_S\0" /* 27725 */ "RELAXED_DOT_S\0" /* 27739 */ "ANDNOT_S\0" /* 27748 */ "RETHROW_S\0" /* 27758 */ "TABLE_COPY_S\0" /* 27771 */ "END_TRY_S\0" /* 27781 */ "ARGUMENT_funcref_S\0" /* 27800 */ "ARGUMENT_externref_S\0" /* 27821 */ "ARGUMENT_exnref_S\0" /* 27839 */ "EXTRACT_LANE_I8x16_s_S\0" /* 27862 */ "EXTRACT_LANE_I16x8_s_S\0" /* 27885 */ "EXTRACT_LANE_I8x16_u_S\0" /* 27908 */ "EXTRACT_LANE_I16x8_u_S\0" /* 27931 */ "RELAXED_DOT_BFLOAT\0" /* 27950 */ "G_SSUBSAT\0" /* 27960 */ "G_USUBSAT\0" /* 27970 */ "G_SADDSAT\0" /* 27980 */ "G_UADDSAT\0" /* 27990 */ "G_SSHLSAT\0" /* 28000 */ "G_USHLSAT\0" /* 28010 */ "G_SMULFIXSAT\0" /* 28023 */ "G_UMULFIXSAT\0" /* 28036 */ "G_SDIVFIXSAT\0" /* 28049 */ "G_UDIVFIXSAT\0" /* 28062 */ "G_EXTRACT\0" /* 28072 */ "BITSELECT\0" /* 28082 */ "G_SELECT\0" /* 28091 */ "G_BRINDIRECT\0" /* 28104 */ "RET_CALL_INDIRECT\0" /* 28122 */ "CATCHRET\0" /* 28131 */ "CLEANUPRET\0" /* 28142 */ "PATCHABLE_RET\0" /* 28156 */ "G_MEMSET\0" /* 28165 */ "PATCHABLE_FUNCTION_EXIT\0" /* 28189 */ "G_BRJT\0" /* 28196 */ "G_EXTRACT_VECTOR_ELT\0" /* 28217 */ "G_INSERT_VECTOR_ELT\0" /* 28237 */ "G_FCONSTANT\0" /* 28249 */ "G_CONSTANT\0" /* 28260 */ "G_INTRINSIC_CONVERGENT\0" /* 28283 */ "STATEPOINT\0" /* 28294 */ "PATCHPOINT\0" /* 28305 */ "G_PTRTOINT\0" /* 28316 */ "G_FRINT\0" /* 28324 */ "G_INTRINSIC_LLRINT\0" /* 28343 */ "G_INTRINSIC_LRINT\0" /* 28361 */ "G_FNEARBYINT\0" /* 28374 */ "RELAXED_DOT\0" /* 28386 */ "ANDNOT\0" /* 28393 */ "G_VASTART\0" /* 28403 */ "LIFETIME_START\0" /* 28418 */ "G_INVOKE_REGION_START\0" /* 28440 */ "G_INSERT\0" /* 28449 */ "G_FSQRT\0" /* 28457 */ "G_STRICT_FSQRT\0" /* 28472 */ "G_BITCAST\0" /* 28482 */ "G_ADDRSPACE_CAST\0" /* 28499 */ "DBG_VALUE_LIST\0" /* 28514 */ "G_FPEXT\0" /* 28522 */ "G_SEXT\0" /* 28529 */ "G_ASSERT_SEXT\0" /* 28543 */ "G_ANYEXT\0" /* 28552 */ "G_ZEXT\0" /* 28559 */ "G_ASSERT_ZEXT\0" /* 28573 */ "G_FDIV\0" /* 28580 */ "G_STRICT_FDIV\0" /* 28594 */ "G_SDIV\0" /* 28601 */ "G_UDIV\0" /* 28608 */ "G_GET_FPENV\0" /* 28620 */ "G_RESET_FPENV\0" /* 28634 */ "G_SET_FPENV\0" /* 28646 */ "G_FPOW\0" /* 28653 */ "RETHROW\0" /* 28661 */ "G_VECREDUCE_FMAX\0" /* 28678 */ "G_ATOMICRMW_FMAX\0" /* 28695 */ "G_VECREDUCE_SMAX\0" /* 28712 */ "G_SMAX\0" /* 28719 */ "G_VECREDUCE_UMAX\0" /* 28736 */ "G_UMAX\0" /* 28743 */ "G_ATOMICRMW_UMAX\0" /* 28760 */ "G_ATOMICRMW_MAX\0" /* 28776 */ "G_FRAME_INDEX\0" /* 28790 */ "G_SBFX\0" /* 28797 */ "G_UBFX\0" /* 28804 */ "G_SMULFIX\0" /* 28814 */ "G_UMULFIX\0" /* 28824 */ "G_SDIVFIX\0" /* 28834 */ "G_UDIVFIX\0" /* 28844 */ "G_MEMCPY\0" /* 28853 */ "TABLE_COPY\0" /* 28864 */ "CONVERGENCECTRL_ENTRY\0" /* 28886 */ "END_TRY\0" /* 28894 */ "G_CTLZ\0" /* 28901 */ "G_CTTZ\0" /* 28908 */ "ARGUMENT_funcref\0" /* 28925 */ "ARGUMENT_externref\0" /* 28944 */ "ARGUMENT_exnref\0" /* 28960 */ "EXTRACT_LANE_I8x16_s\0" /* 28981 */ "EXTRACT_LANE_I16x8_s\0" /* 29002 */ "EXTRACT_LANE_I8x16_u\0" /* 29023 */ "EXTRACT_LANE_I16x8_u\0" }; #ifdef __GNUC__ #pragma GCC diagnostic pop #endif extern const unsigned WebAssemblyInstrNameIndices[] = { 12703U, 13102U, 13866U, 13403U, 12772U, 12753U, 12781U, 12938U, 12520U, 12535U, 11727U, 12562U, 14343U, 11554U, 28499U, 12486U, 12699U, 12762U, 11279U, 28859U, 11419U, 28403U, 11100U, 11202U, 11252U, 13533U, 12916U, 28294U, 11185U, 13801U, 12625U, 28283U, 11466U, 13774U, 13761U, 13927U, 28142U, 28165U, 12839U, 12895U, 12868U, 12798U, 11536U, 13892U, 13487U, 28864U, 14045U, 13684U, 11602U, 28529U, 28559U, 13233U, 10997U, 10708U, 13041U, 28594U, 28601U, 13068U, 13075U, 13082U, 13092U, 11078U, 14216U, 14179U, 11725U, 12701U, 28776U, 11564U, 11579U, 12943U, 28062U, 14267U, 28440U, 14284U, 14116U, 10778U, 14326U, 28305U, 14243U, 28472U, 11653U, 13903U, 11159U, 10752U, 11141U, 28343U, 28324U, 13211U, 13952U, 13971U, 10898U, 10842U, 10872U, 10883U, 10823U, 10853U, 11510U, 11494U, 14373U, 12576U, 12593U, 11029U, 10714U, 11084U, 11045U, 14221U, 14185U, 28760U, 13359U, 28743U, 13342U, 10964U, 10691U, 28678U, 13277U, 13595U, 13573U, 11244U, 12648U, 11113U, 28091U, 28418U, 10730U, 14431U, 28260U, 14458U, 28543U, 10770U, 28249U, 28237U, 28393U, 12617U, 28522U, 12549U, 28552U, 12825U, 14038U, 14024U, 12818U, 14031U, 14236U, 12959U, 13650U, 13643U, 13657U, 13664U, 28082U, 13479U, 11300U, 13463U, 11223U, 13471U, 11292U, 13455U, 11215U, 13517U, 13509U, 12667U, 12659U, 27980U, 27970U, 27960U, 27950U, 28000U, 27990U, 28804U, 28814U, 28010U, 28023U, 28824U, 28834U, 28036U, 28049U, 10922U, 10670U, 12983U, 10651U, 10816U, 28573U, 13047U, 28646U, 12725U, 13845U, 3568U, 9U, 12610U, 3560U, 0U, 13820U, 13852U, 12513U, 28514U, 10742U, 12707U, 12716U, 13625U, 13634U, 14254U, 13248U, 14360U, 11662U, 13176U, 13186U, 11349U, 11364U, 13133U, 13165U, 28608U, 28634U, 28620U, 11308U, 11336U, 11321U, 11003U, 12743U, 13311U, 28712U, 13335U, 28736U, 14261U, 11132U, 11122U, 13861U, 28189U, 11379U, 14097U, 14077U, 28217U, 28196U, 14131U, 14148U, 14413U, 28901U, 11707U, 28894U, 11689U, 13705U, 13617U, 11523U, 12831U, 14319U, 13383U, 13204U, 14311U, 13375U, 13196U, 12691U, 12683U, 12675U, 28449U, 14068U, 28316U, 28361U, 28482U, 13879U, 11406U, 10799U, 11631U, 11479U, 10950U, 10677U, 13011U, 28580U, 13054U, 10657U, 28457U, 13829U, 13991U, 14007U, 28844U, 11450U, 11643U, 28156U, 13525U, 13566U, 13542U, 13554U, 10929U, 12990U, 10905U, 12966U, 28661U, 13260U, 13144U, 13112U, 10981U, 13025U, 11062U, 14201U, 14163U, 28695U, 13294U, 28719U, 13318U, 28790U, 28797U, 14299U, 27603U, 14500U, 27633U, 28122U, 27701U, 28131U, 27712U, 11264U, 26455U, 14496U, 27629U, 9790U, 25433U, 2659U, 17402U, 8076U, 23487U, 6983U, 22216U, 3770U, 18675U, 10033U, 25716U, 8380U, 23837U, 4080U, 19031U, 9194U, 24743U, 9661U, 25282U, 2528U, 17243U, 7923U, 23310U, 6853U, 22058U, 3617U, 18498U, 9937U, 25604U, 2978U, 17769U, 8265U, 23704U, 7302U, 22583U, 3965U, 18898U, 9108U, 24643U, 10149U, 25848U, 9266U, 24827U, 10377U, 26108U, 9448U, 25037U, 13438U, 27487U, 13786U, 27575U, 9966U, 25637U, 8313U, 23758U, 4013U, 18952U, 9137U, 24676U, 11058U, 28386U, 27739U, 2986U, 17779U, 7310U, 22593U, 26428U, 11623U, 26538U, 28944U, 27821U, 28925U, 27800U, 3519U, 18404U, 7841U, 23216U, 28908U, 27781U, 3547U, 18436U, 7869U, 23248U, 9622U, 25237U, 7826U, 23199U, 7854U, 23231U, 3504U, 18387U, 3532U, 18419U, 9051U, 24578U, 9066U, 24595U, 11231U, 26440U, 743U, 15300U, 5068U, 20115U, 1865U, 16516U, 6190U, 21331U, 1841U, 16490U, 6166U, 21305U, 767U, 15326U, 5092U, 20141U, 1889U, 16542U, 6214U, 21357U, 201U, 14714U, 4526U, 19529U, 1116U, 15707U, 5441U, 20522U, 221U, 14736U, 4546U, 19551U, 1163U, 15758U, 5488U, 20573U, 297U, 14818U, 4622U, 19633U, 1266U, 15869U, 5591U, 20684U, 394U, 14923U, 4719U, 19738U, 1394U, 16007U, 5719U, 20822U, 637U, 15184U, 4962U, 19999U, 1718U, 16355U, 6043U, 21170U, 125U, 14632U, 4450U, 19447U, 1040U, 15625U, 5365U, 20440U, 482U, 15017U, 4807U, 19832U, 1510U, 16131U, 5835U, 20946U, 561U, 15102U, 4886U, 19917U, 1616U, 16245U, 5941U, 21060U, 1136U, 15729U, 5461U, 20544U, 1239U, 15840U, 5564U, 20655U, 1363U, 15974U, 5688U, 20789U, 1692U, 16327U, 6017U, 21142U, 1013U, 15596U, 5338U, 20411U, 1482U, 16101U, 5807U, 20916U, 1589U, 16216U, 5914U, 21031U, 248U, 14765U, 4573U, 19580U, 1190U, 15787U, 5515U, 20602U, 324U, 14847U, 4649U, 19662U, 1293U, 15898U, 5618U, 20713U, 425U, 14956U, 4750U, 19771U, 1425U, 16040U, 5750U, 20855U, 663U, 15212U, 4988U, 20027U, 1744U, 16383U, 6069U, 21198U, 152U, 14661U, 4477U, 19476U, 1067U, 15654U, 5392U, 20469U, 510U, 15047U, 4835U, 19862U, 1538U, 16161U, 5863U, 20976U, 588U, 15131U, 4913U, 19946U, 1643U, 16274U, 5968U, 21089U, 274U, 14793U, 4599U, 19608U, 1216U, 15815U, 5541U, 20630U, 350U, 14875U, 4675U, 19690U, 1319U, 15926U, 5644U, 20741U, 455U, 14988U, 4780U, 19803U, 1455U, 16072U, 5780U, 20887U, 688U, 15239U, 5013U, 20054U, 1769U, 16410U, 6094U, 21225U, 178U, 14689U, 4503U, 19504U, 1093U, 15682U, 5418U, 20497U, 537U, 15076U, 4862U, 19891U, 1565U, 16190U, 5890U, 21005U, 614U, 15159U, 4939U, 19974U, 1669U, 16302U, 5994U, 21117U, 80U, 14583U, 4405U, 19398U, 968U, 15547U, 5293U, 20362U, 945U, 15522U, 5270U, 20337U, 103U, 14608U, 4428U, 19423U, 991U, 15572U, 5316U, 20387U, 373U, 14900U, 4698U, 19715U, 1342U, 15951U, 5667U, 20766U, 10336U, 26061U, 9407U, 24990U, 9990U, 25665U, 8337U, 23786U, 4037U, 18980U, 9161U, 24704U, 28072U, 27669U, 12737U, 27420U, 13863U, 12507U, 27400U, 27592U, 3008U, 17805U, 7332U, 22619U, 14403U, 27617U, 12854U, 28108U, 27685U, 27432U, 12642U, 12928U, 27439U, 27408U, 9737U, 25370U, 2595U, 17324U, 7999U, 23398U, 6919U, 22138U, 3693U, 18586U, 3480U, 18357U, 7802U, 23169U, 2903U, 17680U, 7227U, 22494U, 3342U, 18195U, 7681U, 23026U, 7882U, 23263U, 3576U, 18451U, 9910U, 25573U, 8238U, 23673U, 3938U, 18867U, 9081U, 24612U, 2612U, 17345U, 6936U, 22159U, 12474U, 27377U, 12241U, 27116U, 2961U, 17748U, 7285U, 22562U, 11971U, 26818U, 3471U, 18346U, 7793U, 23158U, 9612U, 25225U, 3496U, 18377U, 7818U, 23189U, 11388U, 26472U, 11545U, 26527U, 9855U, 25510U, 2945U, 17728U, 8141U, 23564U, 7269U, 22542U, 3835U, 18752U, 3232U, 18069U, 7571U, 22900U, 3461U, 18334U, 7783U, 23146U, 28382U, 27733U, 12326U, 27211U, 12066U, 26923U, 2633U, 17370U, 6957U, 22184U, 11814U, 26643U, 3053U, 17860U, 7390U, 22689U, 9528U, 25129U, 11518U, 26520U, 11109U, 12733U, 27416U, 13390U, 27451U, 12500U, 27391U, 13675U, 27512U, 26434U, 28886U, 27771U, 3488U, 18367U, 7810U, 23179U, 9769U, 25408U, 2642U, 17381U, 8055U, 23462U, 6966U, 22195U, 3749U, 18650U, 10024U, 25705U, 3062U, 17871U, 8371U, 23826U, 7399U, 22700U, 4071U, 19020U, 9185U, 24732U, 10065U, 25754U, 8412U, 23875U, 4112U, 19069U, 10304U, 26025U, 8560U, 24045U, 4214U, 19185U, 10207U, 25914U, 8478U, 23951U, 4166U, 19131U, 10415U, 26152U, 8626U, 24121U, 4246U, 19221U, 9708U, 25337U, 7970U, 23365U, 3664U, 18553U, 28981U, 27862U, 29023U, 27908U, 8294U, 23737U, 3994U, 18931U, 28960U, 27839U, 29002U, 27885U, 3196U, 18029U, 7535U, 22860U, 3425U, 18294U, 7747U, 23106U, 6896U, 22111U, 3282U, 18127U, 3214U, 18049U, 7553U, 22880U, 3443U, 18314U, 7765U, 23126U, 2571U, 17296U, 7621U, 22958U, 13419U, 27466U, 9778U, 25419U, 2649U, 17390U, 8064U, 23473U, 6973U, 22204U, 3758U, 18661U, 2434U, 17137U, 6759U, 21952U, 2472U, 17179U, 6797U, 21994U, 2453U, 17158U, 6778U, 21973U, 2491U, 17200U, 6816U, 22015U, 9671U, 25294U, 2550U, 17269U, 7933U, 23322U, 6875U, 22084U, 3627U, 18510U, 10043U, 25728U, 3140U, 17961U, 8390U, 23849U, 7479U, 22792U, 4090U, 19043U, 9204U, 24755U, 10282U, 25999U, 3369U, 18226U, 8538U, 24019U, 7691U, 23038U, 9373U, 24950U, 12369U, 27260U, 12118U, 26981U, 2790U, 17549U, 7114U, 22363U, 11860U, 26695U, 3253U, 18094U, 7592U, 22925U, 9550U, 25155U, 12421U, 27318U, 12179U, 27048U, 2839U, 17604U, 7163U, 22418U, 11915U, 26756U, 3302U, 18149U, 7641U, 22980U, 9581U, 25190U, 9812U, 25459U, 2868U, 17637U, 8098U, 23513U, 7192U, 22451U, 3792U, 18701U, 10185U, 25888U, 3178U, 18007U, 8456U, 23925U, 7517U, 22838U, 4144U, 19105U, 9282U, 24845U, 10393U, 26126U, 3407U, 18272U, 8604U, 24095U, 7729U, 23084U, 9464U, 25055U, 3086U, 17901U, 3105U, 17922U, 2819U, 17582U, 2667U, 17412U, 6991U, 22226U, 2699U, 17448U, 7023U, 22262U, 2913U, 17692U, 7237U, 22506U, 2739U, 17492U, 7063U, 22306U, 7377U, 22674U, 7442U, 22751U, 7423U, 22730U, 7461U, 22772U, 3123U, 17942U, 3352U, 18207U, 7143U, 22396U, 2683U, 17430U, 7007U, 22244U, 2719U, 17470U, 7043U, 22284U, 2929U, 17710U, 7253U, 22524U, 2759U, 17514U, 7083U, 22328U, 12504U, 27395U, 10265U, 25980U, 8521U, 24000U, 4197U, 19166U, 9343U, 24916U, 9680U, 25305U, 2557U, 17278U, 7942U, 23333U, 6882U, 22093U, 3636U, 18521U, 10054U, 25741U, 3149U, 17972U, 8401U, 23862U, 7488U, 22803U, 4101U, 19056U, 9215U, 24768U, 10293U, 26012U, 3378U, 18237U, 8549U, 24032U, 7700U, 23049U, 9384U, 24963U, 2286U, 16977U, 6611U, 21792U, 710U, 15263U, 5035U, 20078U, 1808U, 16453U, 6133U, 21268U, 750U, 15307U, 5075U, 20122U, 1872U, 16523U, 6197U, 21338U, 2252U, 16939U, 6577U, 21754U, 1791U, 16434U, 6116U, 21249U, 1848U, 16497U, 6173U, 21312U, 2269U, 16958U, 6594U, 21773U, 2303U, 16996U, 6628U, 21811U, 727U, 15282U, 5052U, 20097U, 1825U, 16472U, 6150U, 21287U, 774U, 15333U, 5099U, 20148U, 1896U, 16549U, 6221U, 21364U, 2144U, 16823U, 6469U, 21638U, 1992U, 16655U, 6317U, 21470U, 870U, 15439U, 5195U, 20254U, 2168U, 16849U, 6493U, 21664U, 2016U, 16681U, 6341U, 21496U, 894U, 15465U, 5219U, 20280U, 18U, 14513U, 4343U, 19328U, 53U, 14552U, 4378U, 19367U, 918U, 15491U, 5243U, 20306U, 208U, 14721U, 4533U, 19536U, 1123U, 15714U, 5448U, 20529U, 2040U, 16707U, 6365U, 21522U, 815U, 15378U, 5140U, 20193U, 1937U, 16594U, 6262U, 21409U, 2107U, 16782U, 6432U, 21597U, 2078U, 16749U, 6403U, 21564U, 832U, 15397U, 5157U, 20212U, 1954U, 16613U, 6279U, 21428U, 12387U, 27280U, 12139U, 27004U, 2805U, 17566U, 7129U, 22380U, 11879U, 26716U, 3268U, 18111U, 7607U, 22942U, 9566U, 25173U, 12439U, 27338U, 12200U, 27071U, 2854U, 17621U, 7178U, 22435U, 11934U, 26777U, 3317U, 18166U, 7656U, 22997U, 9597U, 25208U, 12256U, 27133U, 11984U, 26833U, 2536U, 17253U, 6861U, 22068U, 11740U, 26561U, 2994U, 17789U, 7318U, 22603U, 9513U, 25112U, 13679U, 27516U, 9821U, 25470U, 2875U, 17646U, 8107U, 23524U, 7199U, 22460U, 3801U, 18712U, 10196U, 25901U, 3187U, 18018U, 8467U, 23938U, 7526U, 22849U, 4155U, 19118U, 9293U, 24858U, 10404U, 26139U, 3416U, 18283U, 8615U, 24108U, 7738U, 23095U, 9475U, 25068U, 9660U, 25281U, 7922U, 23309U, 3616U, 18497U, 9866U, 25523U, 2953U, 17738U, 8165U, 23590U, 7277U, 22552U, 3859U, 18778U, 10241U, 25952U, 8497U, 23972U, 9319U, 24888U, 10449U, 26190U, 8645U, 24142U, 9501U, 25098U, 2379U, 17078U, 6704U, 21893U, 790U, 15351U, 5115U, 20166U, 1912U, 16567U, 6237U, 21382U, 9759U, 25396U, 2625U, 17360U, 8034U, 23437U, 6949U, 22174U, 3728U, 18625U, 10085U, 25776U, 8432U, 23897U, 9226U, 24781U, 10324U, 26047U, 8580U, 24067U, 9395U, 24976U, 9748U, 25383U, 2604U, 17335U, 8010U, 23411U, 6928U, 22149U, 3704U, 18599U, 10014U, 25693U, 3045U, 17850U, 8361U, 23814U, 7369U, 22664U, 4061U, 19008U, 10226U, 25935U, 9304U, 24871U, 10434U, 26173U, 9486U, 25081U, 9841U, 25494U, 2891U, 17666U, 8127U, 23548U, 7215U, 22480U, 3821U, 18736U, 9727U, 25358U, 2587U, 17314U, 7989U, 23386U, 6911U, 22128U, 3683U, 18574U, 9980U, 25653U, 8327U, 23774U, 4027U, 18968U, 9151U, 24692U, 9699U, 25326U, 2564U, 17287U, 7961U, 23354U, 6889U, 22102U, 3655U, 18542U, 9957U, 25626U, 3021U, 17820U, 8285U, 23726U, 7345U, 22634U, 3985U, 18920U, 9128U, 24665U, 9659U, 25280U, 7921U, 23308U, 3615U, 18496U, 13671U, 27506U, 28389U, 27742U, 14065U, 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24081U, 7719U, 23072U, 4234U, 19207U, 9420U, 25005U, 11426U, 26492U, 8151U, 23576U, 3845U, 18764U, 8020U, 23423U, 3714U, 18611U, 9800U, 25445U, 8086U, 23499U, 3780U, 18687U, 10253U, 25966U, 8509U, 23986U, 4185U, 19152U, 9331U, 24902U, 9830U, 25481U, 2882U, 17655U, 8116U, 23535U, 7206U, 22469U, 3810U, 18723U, 87U, 14590U, 4412U, 19405U, 975U, 15554U, 5300U, 20369U, 952U, 15529U, 5277U, 20344U, 110U, 14615U, 4435U, 19430U, 998U, 15579U, 5323U, 20394U, 35U, 14532U, 4360U, 19347U, 66U, 14567U, 4391U, 19382U, 931U, 15506U, 5256U, 20321U, 380U, 14907U, 4705U, 19722U, 1349U, 15958U, 5674U, 20773U, 2123U, 16800U, 6448U, 21615U, 1971U, 16632U, 6296U, 21447U, 849U, 15416U, 5174U, 20231U, 2057U, 16726U, 6382U, 21541U, 2092U, 16765U, 6417U, 21580U, 9637U, 25254U, 2510U, 17221U, 7899U, 23282U, 6835U, 22036U, 3593U, 18470U, 9927U, 25592U, 2970U, 17759U, 8255U, 23692U, 7294U, 22573U, 3955U, 18886U, 9098U, 24631U, 10133U, 25830U, 9250U, 24809U, 10361U, 26090U, 9432U, 25019U, 11442U, 26510U, 28853U, 27758U, 12273U, 27152U, 12004U, 26855U, 11758U, 26581U, 12352U, 27241U, 12098U, 26959U, 11842U, 26675U, 12456U, 27357U, 12220U, 27093U, 11952U, 26797U, 12404U, 27299U, 12159U, 27026U, 11897U, 26736U, 11678U, 26548U, 12262U, 27139U, 11990U, 26839U, 2542U, 17259U, 6867U, 22074U, 11746U, 26567U, 3000U, 17795U, 7324U, 22609U, 9519U, 25118U, 28655U, 27750U, 9647U, 25266U, 2518U, 17231U, 7909U, 23294U, 6843U, 22046U, 3603U, 18482U, 28882U, 27775U, 11394U, 26478U, 14175U, 3069U, 17880U, 7406U, 22709U, 27597U, 2349U, 17046U, 2192U, 16875U, 6674U, 21861U, 6517U, 21690U, 13713U, 27523U, 2404U, 17105U, 2222U, 16907U, 2319U, 17014U, 13737U, 27549U, 6729U, 21920U, 6547U, 21722U, 6644U, 21829U, 3880U, 18803U, 3900U, 18825U, 8186U, 23615U, 10539U, 26286U, 8893U, 24404U, 4265U, 19242U, 10612U, 26367U, 8989U, 24510U, 4304U, 19285U, 10559U, 26308U, 8936U, 24451U, 4285U, 19264U, 10632U, 26389U, 9032U, 24557U, 4324U, 19307U, 10578U, 26329U, 8955U, 24472U, 10595U, 26348U, 8972U, 24491U, 10461U, 26204U, 8693U, 24194U, 10499U, 26244U, 8769U, 24274U, 8657U, 24156U, 8809U, 24316U, 8731U, 24234U, 8850U, 24359U, 3920U, 18847U, 9876U, 25535U, 8204U, 23635U, 8913U, 24426U, 9009U, 24532U, 9893U, 25554U, 8221U, 23654U, }; static inline void InitWebAssemblyMCInstrInfo(MCInstrInfo *II) { II->InitMCInstrInfo(WebAssemblyDescs.Insts, WebAssemblyInstrNameIndices, WebAssemblyInstrNameData, nullptr, nullptr, 1898); } } // end namespace llvm #endif // GET_INSTRINFO_MC_DESC #ifdef GET_INSTRINFO_HEADER #undef GET_INSTRINFO_HEADER namespace llvm { struct WebAssemblyGenInstrInfo : public TargetInstrInfo { explicit WebAssemblyGenInstrInfo(unsigned CFSetupOpcode = ~0u, unsigned CFDestroyOpcode = ~0u, unsigned CatchRetOpcode = ~0u, unsigned ReturnOpcode = ~0u); ~WebAssemblyGenInstrInfo() override = default; }; } // end namespace llvm #endif // GET_INSTRINFO_HEADER #ifdef GET_INSTRINFO_HELPER_DECLS #undef GET_INSTRINFO_HELPER_DECLS #endif // GET_INSTRINFO_HELPER_DECLS #ifdef GET_INSTRINFO_HELPERS #undef GET_INSTRINFO_HELPERS #endif // GET_INSTRINFO_HELPERS #ifdef GET_INSTRINFO_CTOR_DTOR #undef GET_INSTRINFO_CTOR_DTOR namespace llvm { extern const WebAssemblyInstrTable WebAssemblyDescs; extern const unsigned WebAssemblyInstrNameIndices[]; extern const char WebAssemblyInstrNameData[]; WebAssemblyGenInstrInfo::WebAssemblyGenInstrInfo(unsigned CFSetupOpcode, unsigned CFDestroyOpcode, unsigned CatchRetOpcode, unsigned ReturnOpcode) : TargetInstrInfo(CFSetupOpcode, CFDestroyOpcode, CatchRetOpcode, ReturnOpcode) { InitMCInstrInfo(WebAssemblyDescs.Insts, WebAssemblyInstrNameIndices, WebAssemblyInstrNameData, nullptr, nullptr, 1898); } } // end namespace llvm #endif // GET_INSTRINFO_CTOR_DTOR #ifdef GET_INSTRINFO_OPERAND_ENUM #undef GET_INSTRINFO_OPERAND_ENUM namespace llvm { namespace WebAssembly { namespace OpName { enum { addr = 3, count = 9, dst = 0, exp = 5, idx = 7, new_ = 6, off = 2, p2align = 1, timeout = 10, val = 4, vec = 8, OPERAND_LAST }; } // end namespace OpName } // end namespace WebAssembly } // end namespace llvm #endif //GET_INSTRINFO_OPERAND_ENUM #ifdef GET_INSTRINFO_NAMED_OPS #undef GET_INSTRINFO_NAMED_OPS namespace llvm { namespace WebAssembly { LLVM_READONLY int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx) { static const int16_t OperandMap [][11] = { {0, 1, 2, 3, -1, -1, -1, -1, -1, -1, -1, }, {0, 1, 2, 3, 4, -1, -1, -1, -1, -1, -1, }, {0, 1, 2, 3, -1, 4, 5, -1, -1, -1, -1, }, {0, 1, 2, 3, -1, 4, -1, -1, -1, -1, 5, }, {0, 1, 2, 3, -1, -1, -1, -1, -1, 4, -1, }, {0, 1, 2, 4, -1, -1, -1, 3, 5, -1, -1, }, {-1, 0, 1, -1, -1, -1, -1, -1, -1, -1, -1, }, {-1, 0, 1, 2, 3, -1, -1, -1, -1, -1, -1, }, {-1, 0, 1, 2, -1, -1, -1, -1, 3, -1, -1, }, {-1, 0, 1, 3, -1, -1, -1, 2, 4, -1, -1, }, {-1, 0, 1, -1, -1, -1, -1, 2, -1, -1, -1, }, }; switch(Opcode) { case WebAssembly::ATOMIC_LOAD16_U_I32_A32: case WebAssembly::ATOMIC_LOAD16_U_I32_A64: case WebAssembly::ATOMIC_LOAD16_U_I64_A32: case WebAssembly::ATOMIC_LOAD16_U_I64_A64: case WebAssembly::ATOMIC_LOAD32_U_I64_A32: case WebAssembly::ATOMIC_LOAD32_U_I64_A64: case WebAssembly::ATOMIC_LOAD8_U_I32_A32: case WebAssembly::ATOMIC_LOAD8_U_I32_A64: case WebAssembly::ATOMIC_LOAD8_U_I64_A32: case WebAssembly::ATOMIC_LOAD8_U_I64_A64: case WebAssembly::ATOMIC_LOAD_I32_A32: case WebAssembly::ATOMIC_LOAD_I32_A64: case WebAssembly::ATOMIC_LOAD_I64_A32: case WebAssembly::ATOMIC_LOAD_I64_A64: case WebAssembly::LOAD16_SPLAT_A32: case WebAssembly::LOAD16_SPLAT_A64: case WebAssembly::LOAD16_S_I32_A32: case WebAssembly::LOAD16_S_I32_A64: case WebAssembly::LOAD16_S_I64_A32: case WebAssembly::LOAD16_S_I64_A64: case WebAssembly::LOAD16_U_I32_A32: case WebAssembly::LOAD16_U_I32_A64: case WebAssembly::LOAD16_U_I64_A32: case WebAssembly::LOAD16_U_I64_A64: case WebAssembly::LOAD32_SPLAT_A32: case WebAssembly::LOAD32_SPLAT_A64: case WebAssembly::LOAD32_S_I64_A32: case WebAssembly::LOAD32_S_I64_A64: case WebAssembly::LOAD32_U_I64_A32: case WebAssembly::LOAD32_U_I64_A64: case WebAssembly::LOAD64_SPLAT_A32: case WebAssembly::LOAD64_SPLAT_A64: case WebAssembly::LOAD8_SPLAT_A32: case WebAssembly::LOAD8_SPLAT_A64: case WebAssembly::LOAD8_S_I32_A32: case WebAssembly::LOAD8_S_I32_A64: case WebAssembly::LOAD8_S_I64_A32: case WebAssembly::LOAD8_S_I64_A64: case WebAssembly::LOAD8_U_I32_A32: case WebAssembly::LOAD8_U_I32_A64: case WebAssembly::LOAD8_U_I64_A32: case WebAssembly::LOAD8_U_I64_A64: case WebAssembly::LOAD_EXTEND_S_I16x8_A32: case WebAssembly::LOAD_EXTEND_S_I16x8_A64: case WebAssembly::LOAD_EXTEND_S_I32x4_A32: case WebAssembly::LOAD_EXTEND_S_I32x4_A64: case WebAssembly::LOAD_EXTEND_S_I64x2_A32: case WebAssembly::LOAD_EXTEND_S_I64x2_A64: case WebAssembly::LOAD_EXTEND_U_I16x8_A32: case WebAssembly::LOAD_EXTEND_U_I16x8_A64: case WebAssembly::LOAD_EXTEND_U_I32x4_A32: case WebAssembly::LOAD_EXTEND_U_I32x4_A64: case WebAssembly::LOAD_EXTEND_U_I64x2_A32: case WebAssembly::LOAD_EXTEND_U_I64x2_A64: case WebAssembly::LOAD_F16_F32_A32: case WebAssembly::LOAD_F16_F32_A64: case WebAssembly::LOAD_F32_A32: case WebAssembly::LOAD_F32_A64: case WebAssembly::LOAD_F64_A32: case WebAssembly::LOAD_F64_A64: case WebAssembly::LOAD_I32_A32: case WebAssembly::LOAD_I32_A64: case WebAssembly::LOAD_I64_A32: case WebAssembly::LOAD_I64_A64: case WebAssembly::LOAD_V128_A32: case WebAssembly::LOAD_V128_A64: case WebAssembly::LOAD_ZERO_32_A32: case WebAssembly::LOAD_ZERO_32_A64: case WebAssembly::LOAD_ZERO_64_A32: case WebAssembly::LOAD_ZERO_64_A64: return OperandMap[0][NamedIdx]; case WebAssembly::ATOMIC_RMW16_U_ADD_I32_A32: case WebAssembly::ATOMIC_RMW16_U_ADD_I32_A64: case WebAssembly::ATOMIC_RMW16_U_ADD_I64_A32: case WebAssembly::ATOMIC_RMW16_U_ADD_I64_A64: case WebAssembly::ATOMIC_RMW16_U_AND_I32_A32: case WebAssembly::ATOMIC_RMW16_U_AND_I32_A64: case WebAssembly::ATOMIC_RMW16_U_AND_I64_A32: case WebAssembly::ATOMIC_RMW16_U_AND_I64_A64: case WebAssembly::ATOMIC_RMW16_U_OR_I32_A32: case WebAssembly::ATOMIC_RMW16_U_OR_I32_A64: case WebAssembly::ATOMIC_RMW16_U_OR_I64_A32: case WebAssembly::ATOMIC_RMW16_U_OR_I64_A64: case WebAssembly::ATOMIC_RMW16_U_SUB_I32_A32: case WebAssembly::ATOMIC_RMW16_U_SUB_I32_A64: case WebAssembly::ATOMIC_RMW16_U_SUB_I64_A32: case WebAssembly::ATOMIC_RMW16_U_SUB_I64_A64: case WebAssembly::ATOMIC_RMW16_U_XCHG_I32_A32: case WebAssembly::ATOMIC_RMW16_U_XCHG_I32_A64: case WebAssembly::ATOMIC_RMW16_U_XCHG_I64_A32: case WebAssembly::ATOMIC_RMW16_U_XCHG_I64_A64: case WebAssembly::ATOMIC_RMW16_U_XOR_I32_A32: case WebAssembly::ATOMIC_RMW16_U_XOR_I32_A64: case WebAssembly::ATOMIC_RMW16_U_XOR_I64_A32: case WebAssembly::ATOMIC_RMW16_U_XOR_I64_A64: case WebAssembly::ATOMIC_RMW32_U_ADD_I64_A32: case WebAssembly::ATOMIC_RMW32_U_ADD_I64_A64: case WebAssembly::ATOMIC_RMW32_U_AND_I64_A32: case WebAssembly::ATOMIC_RMW32_U_AND_I64_A64: case WebAssembly::ATOMIC_RMW32_U_OR_I64_A32: case WebAssembly::ATOMIC_RMW32_U_OR_I64_A64: case WebAssembly::ATOMIC_RMW32_U_SUB_I64_A32: case WebAssembly::ATOMIC_RMW32_U_SUB_I64_A64: case WebAssembly::ATOMIC_RMW32_U_XCHG_I64_A32: case WebAssembly::ATOMIC_RMW32_U_XCHG_I64_A64: case WebAssembly::ATOMIC_RMW32_U_XOR_I64_A32: case WebAssembly::ATOMIC_RMW32_U_XOR_I64_A64: case WebAssembly::ATOMIC_RMW8_U_ADD_I32_A32: case WebAssembly::ATOMIC_RMW8_U_ADD_I32_A64: case WebAssembly::ATOMIC_RMW8_U_ADD_I64_A32: case WebAssembly::ATOMIC_RMW8_U_ADD_I64_A64: case WebAssembly::ATOMIC_RMW8_U_AND_I32_A32: case WebAssembly::ATOMIC_RMW8_U_AND_I32_A64: case WebAssembly::ATOMIC_RMW8_U_AND_I64_A32: case WebAssembly::ATOMIC_RMW8_U_AND_I64_A64: case WebAssembly::ATOMIC_RMW8_U_OR_I32_A32: case WebAssembly::ATOMIC_RMW8_U_OR_I32_A64: case WebAssembly::ATOMIC_RMW8_U_OR_I64_A32: case WebAssembly::ATOMIC_RMW8_U_OR_I64_A64: case WebAssembly::ATOMIC_RMW8_U_SUB_I32_A32: case WebAssembly::ATOMIC_RMW8_U_SUB_I32_A64: case WebAssembly::ATOMIC_RMW8_U_SUB_I64_A32: case WebAssembly::ATOMIC_RMW8_U_SUB_I64_A64: case WebAssembly::ATOMIC_RMW8_U_XCHG_I32_A32: case WebAssembly::ATOMIC_RMW8_U_XCHG_I32_A64: case WebAssembly::ATOMIC_RMW8_U_XCHG_I64_A32: case WebAssembly::ATOMIC_RMW8_U_XCHG_I64_A64: case WebAssembly::ATOMIC_RMW8_U_XOR_I32_A32: case WebAssembly::ATOMIC_RMW8_U_XOR_I32_A64: case WebAssembly::ATOMIC_RMW8_U_XOR_I64_A32: case WebAssembly::ATOMIC_RMW8_U_XOR_I64_A64: case WebAssembly::ATOMIC_RMW_ADD_I32_A32: case WebAssembly::ATOMIC_RMW_ADD_I32_A64: case WebAssembly::ATOMIC_RMW_ADD_I64_A32: case WebAssembly::ATOMIC_RMW_ADD_I64_A64: case WebAssembly::ATOMIC_RMW_AND_I32_A32: case WebAssembly::ATOMIC_RMW_AND_I32_A64: case WebAssembly::ATOMIC_RMW_AND_I64_A32: case WebAssembly::ATOMIC_RMW_AND_I64_A64: case WebAssembly::ATOMIC_RMW_OR_I32_A32: case WebAssembly::ATOMIC_RMW_OR_I32_A64: case WebAssembly::ATOMIC_RMW_OR_I64_A32: case WebAssembly::ATOMIC_RMW_OR_I64_A64: case WebAssembly::ATOMIC_RMW_SUB_I32_A32: case WebAssembly::ATOMIC_RMW_SUB_I32_A64: case WebAssembly::ATOMIC_RMW_SUB_I64_A32: case WebAssembly::ATOMIC_RMW_SUB_I64_A64: case WebAssembly::ATOMIC_RMW_XCHG_I32_A32: case WebAssembly::ATOMIC_RMW_XCHG_I32_A64: case WebAssembly::ATOMIC_RMW_XCHG_I64_A32: case WebAssembly::ATOMIC_RMW_XCHG_I64_A64: case WebAssembly::ATOMIC_RMW_XOR_I32_A32: case WebAssembly::ATOMIC_RMW_XOR_I32_A64: case WebAssembly::ATOMIC_RMW_XOR_I64_A32: case WebAssembly::ATOMIC_RMW_XOR_I64_A64: return OperandMap[1][NamedIdx]; case WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I32_A32: case WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I32_A64: case WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I64_A32: case WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I64_A64: case WebAssembly::ATOMIC_RMW32_U_CMPXCHG_I64_A32: case WebAssembly::ATOMIC_RMW32_U_CMPXCHG_I64_A64: case WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I32_A32: case WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I32_A64: case WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I64_A32: case WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I64_A64: case WebAssembly::ATOMIC_RMW_CMPXCHG_I32_A32: case WebAssembly::ATOMIC_RMW_CMPXCHG_I32_A64: case WebAssembly::ATOMIC_RMW_CMPXCHG_I64_A32: case WebAssembly::ATOMIC_RMW_CMPXCHG_I64_A64: return OperandMap[2][NamedIdx]; case WebAssembly::MEMORY_ATOMIC_WAIT32_A32: case WebAssembly::MEMORY_ATOMIC_WAIT32_A64: case WebAssembly::MEMORY_ATOMIC_WAIT64_A32: case WebAssembly::MEMORY_ATOMIC_WAIT64_A64: return OperandMap[3][NamedIdx]; case WebAssembly::MEMORY_ATOMIC_NOTIFY_A32: case WebAssembly::MEMORY_ATOMIC_NOTIFY_A64: return OperandMap[4][NamedIdx]; case WebAssembly::LOAD_LANE_16_A32: case WebAssembly::LOAD_LANE_16_A64: case WebAssembly::LOAD_LANE_32_A32: case WebAssembly::LOAD_LANE_32_A64: case WebAssembly::LOAD_LANE_64_A32: case WebAssembly::LOAD_LANE_64_A64: case WebAssembly::LOAD_LANE_8_A32: case WebAssembly::LOAD_LANE_8_A64: return OperandMap[5][NamedIdx]; case WebAssembly::ATOMIC_LOAD16_U_I32_A32_S: case WebAssembly::ATOMIC_LOAD16_U_I32_A64_S: case WebAssembly::ATOMIC_LOAD16_U_I64_A32_S: case WebAssembly::ATOMIC_LOAD16_U_I64_A64_S: case WebAssembly::ATOMIC_LOAD32_U_I64_A32_S: case WebAssembly::ATOMIC_LOAD32_U_I64_A64_S: case WebAssembly::ATOMIC_LOAD8_U_I32_A32_S: case WebAssembly::ATOMIC_LOAD8_U_I32_A64_S: case WebAssembly::ATOMIC_LOAD8_U_I64_A32_S: case WebAssembly::ATOMIC_LOAD8_U_I64_A64_S: case WebAssembly::ATOMIC_LOAD_I32_A32_S: case WebAssembly::ATOMIC_LOAD_I32_A64_S: case WebAssembly::ATOMIC_LOAD_I64_A32_S: case WebAssembly::ATOMIC_LOAD_I64_A64_S: case WebAssembly::ATOMIC_RMW16_U_ADD_I32_A32_S: case WebAssembly::ATOMIC_RMW16_U_ADD_I32_A64_S: case WebAssembly::ATOMIC_RMW16_U_ADD_I64_A32_S: case WebAssembly::ATOMIC_RMW16_U_ADD_I64_A64_S: case WebAssembly::ATOMIC_RMW16_U_AND_I32_A32_S: case WebAssembly::ATOMIC_RMW16_U_AND_I32_A64_S: case WebAssembly::ATOMIC_RMW16_U_AND_I64_A32_S: case WebAssembly::ATOMIC_RMW16_U_AND_I64_A64_S: case WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I32_A32_S: case WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I32_A64_S: case WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I64_A32_S: case WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I64_A64_S: case WebAssembly::ATOMIC_RMW16_U_OR_I32_A32_S: case WebAssembly::ATOMIC_RMW16_U_OR_I32_A64_S: case WebAssembly::ATOMIC_RMW16_U_OR_I64_A32_S: case WebAssembly::ATOMIC_RMW16_U_OR_I64_A64_S: case WebAssembly::ATOMIC_RMW16_U_SUB_I32_A32_S: case WebAssembly::ATOMIC_RMW16_U_SUB_I32_A64_S: case WebAssembly::ATOMIC_RMW16_U_SUB_I64_A32_S: case WebAssembly::ATOMIC_RMW16_U_SUB_I64_A64_S: case WebAssembly::ATOMIC_RMW16_U_XCHG_I32_A32_S: case WebAssembly::ATOMIC_RMW16_U_XCHG_I32_A64_S: case WebAssembly::ATOMIC_RMW16_U_XCHG_I64_A32_S: case WebAssembly::ATOMIC_RMW16_U_XCHG_I64_A64_S: case WebAssembly::ATOMIC_RMW16_U_XOR_I32_A32_S: case WebAssembly::ATOMIC_RMW16_U_XOR_I32_A64_S: case WebAssembly::ATOMIC_RMW16_U_XOR_I64_A32_S: case WebAssembly::ATOMIC_RMW16_U_XOR_I64_A64_S: case WebAssembly::ATOMIC_RMW32_U_ADD_I64_A32_S: case WebAssembly::ATOMIC_RMW32_U_ADD_I64_A64_S: case WebAssembly::ATOMIC_RMW32_U_AND_I64_A32_S: case WebAssembly::ATOMIC_RMW32_U_AND_I64_A64_S: case WebAssembly::ATOMIC_RMW32_U_CMPXCHG_I64_A32_S: case WebAssembly::ATOMIC_RMW32_U_CMPXCHG_I64_A64_S: case WebAssembly::ATOMIC_RMW32_U_OR_I64_A32_S: case WebAssembly::ATOMIC_RMW32_U_OR_I64_A64_S: case WebAssembly::ATOMIC_RMW32_U_SUB_I64_A32_S: case WebAssembly::ATOMIC_RMW32_U_SUB_I64_A64_S: case WebAssembly::ATOMIC_RMW32_U_XCHG_I64_A32_S: case WebAssembly::ATOMIC_RMW32_U_XCHG_I64_A64_S: case WebAssembly::ATOMIC_RMW32_U_XOR_I64_A32_S: case WebAssembly::ATOMIC_RMW32_U_XOR_I64_A64_S: case WebAssembly::ATOMIC_RMW8_U_ADD_I32_A32_S: case WebAssembly::ATOMIC_RMW8_U_ADD_I32_A64_S: case WebAssembly::ATOMIC_RMW8_U_ADD_I64_A32_S: case WebAssembly::ATOMIC_RMW8_U_ADD_I64_A64_S: case WebAssembly::ATOMIC_RMW8_U_AND_I32_A32_S: case WebAssembly::ATOMIC_RMW8_U_AND_I32_A64_S: case WebAssembly::ATOMIC_RMW8_U_AND_I64_A32_S: case WebAssembly::ATOMIC_RMW8_U_AND_I64_A64_S: case WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I32_A32_S: case WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I32_A64_S: case WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I64_A32_S: case WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I64_A64_S: case WebAssembly::ATOMIC_RMW8_U_OR_I32_A32_S: case WebAssembly::ATOMIC_RMW8_U_OR_I32_A64_S: case WebAssembly::ATOMIC_RMW8_U_OR_I64_A32_S: case WebAssembly::ATOMIC_RMW8_U_OR_I64_A64_S: case WebAssembly::ATOMIC_RMW8_U_SUB_I32_A32_S: case WebAssembly::ATOMIC_RMW8_U_SUB_I32_A64_S: case WebAssembly::ATOMIC_RMW8_U_SUB_I64_A32_S: case WebAssembly::ATOMIC_RMW8_U_SUB_I64_A64_S: case WebAssembly::ATOMIC_RMW8_U_XCHG_I32_A32_S: case WebAssembly::ATOMIC_RMW8_U_XCHG_I32_A64_S: case WebAssembly::ATOMIC_RMW8_U_XCHG_I64_A32_S: case WebAssembly::ATOMIC_RMW8_U_XCHG_I64_A64_S: case WebAssembly::ATOMIC_RMW8_U_XOR_I32_A32_S: case WebAssembly::ATOMIC_RMW8_U_XOR_I32_A64_S: case WebAssembly::ATOMIC_RMW8_U_XOR_I64_A32_S: case WebAssembly::ATOMIC_RMW8_U_XOR_I64_A64_S: case WebAssembly::ATOMIC_RMW_ADD_I32_A32_S: case WebAssembly::ATOMIC_RMW_ADD_I32_A64_S: case WebAssembly::ATOMIC_RMW_ADD_I64_A32_S: case WebAssembly::ATOMIC_RMW_ADD_I64_A64_S: case WebAssembly::ATOMIC_RMW_AND_I32_A32_S: case WebAssembly::ATOMIC_RMW_AND_I32_A64_S: case WebAssembly::ATOMIC_RMW_AND_I64_A32_S: case WebAssembly::ATOMIC_RMW_AND_I64_A64_S: case WebAssembly::ATOMIC_RMW_CMPXCHG_I32_A32_S: case WebAssembly::ATOMIC_RMW_CMPXCHG_I32_A64_S: case WebAssembly::ATOMIC_RMW_CMPXCHG_I64_A32_S: case WebAssembly::ATOMIC_RMW_CMPXCHG_I64_A64_S: case WebAssembly::ATOMIC_RMW_OR_I32_A32_S: case WebAssembly::ATOMIC_RMW_OR_I32_A64_S: case WebAssembly::ATOMIC_RMW_OR_I64_A32_S: case WebAssembly::ATOMIC_RMW_OR_I64_A64_S: case WebAssembly::ATOMIC_RMW_SUB_I32_A32_S: case WebAssembly::ATOMIC_RMW_SUB_I32_A64_S: case WebAssembly::ATOMIC_RMW_SUB_I64_A32_S: case WebAssembly::ATOMIC_RMW_SUB_I64_A64_S: case WebAssembly::ATOMIC_RMW_XCHG_I32_A32_S: case WebAssembly::ATOMIC_RMW_XCHG_I32_A64_S: case WebAssembly::ATOMIC_RMW_XCHG_I64_A32_S: case WebAssembly::ATOMIC_RMW_XCHG_I64_A64_S: case WebAssembly::ATOMIC_RMW_XOR_I32_A32_S: case WebAssembly::ATOMIC_RMW_XOR_I32_A64_S: case WebAssembly::ATOMIC_RMW_XOR_I64_A32_S: case WebAssembly::ATOMIC_RMW_XOR_I64_A64_S: case WebAssembly::ATOMIC_STORE16_I32_A32_S: case WebAssembly::ATOMIC_STORE16_I32_A64_S: case WebAssembly::ATOMIC_STORE16_I64_A32_S: case WebAssembly::ATOMIC_STORE16_I64_A64_S: case WebAssembly::ATOMIC_STORE32_I64_A32_S: case WebAssembly::ATOMIC_STORE32_I64_A64_S: case WebAssembly::ATOMIC_STORE8_I32_A32_S: case WebAssembly::ATOMIC_STORE8_I32_A64_S: case WebAssembly::ATOMIC_STORE8_I64_A32_S: case WebAssembly::ATOMIC_STORE8_I64_A64_S: case WebAssembly::ATOMIC_STORE_I32_A32_S: case WebAssembly::ATOMIC_STORE_I32_A64_S: case WebAssembly::ATOMIC_STORE_I64_A32_S: case WebAssembly::ATOMIC_STORE_I64_A64_S: case WebAssembly::LOAD16_SPLAT_A32_S: case WebAssembly::LOAD16_SPLAT_A64_S: case WebAssembly::LOAD16_S_I32_A32_S: case WebAssembly::LOAD16_S_I32_A64_S: case WebAssembly::LOAD16_S_I64_A32_S: case WebAssembly::LOAD16_S_I64_A64_S: case WebAssembly::LOAD16_U_I32_A32_S: case WebAssembly::LOAD16_U_I32_A64_S: case WebAssembly::LOAD16_U_I64_A32_S: case WebAssembly::LOAD16_U_I64_A64_S: case WebAssembly::LOAD32_SPLAT_A32_S: case WebAssembly::LOAD32_SPLAT_A64_S: case WebAssembly::LOAD32_S_I64_A32_S: case WebAssembly::LOAD32_S_I64_A64_S: case WebAssembly::LOAD32_U_I64_A32_S: case WebAssembly::LOAD32_U_I64_A64_S: case WebAssembly::LOAD64_SPLAT_A32_S: case WebAssembly::LOAD64_SPLAT_A64_S: case WebAssembly::LOAD8_SPLAT_A32_S: case WebAssembly::LOAD8_SPLAT_A64_S: case WebAssembly::LOAD8_S_I32_A32_S: case WebAssembly::LOAD8_S_I32_A64_S: case WebAssembly::LOAD8_S_I64_A32_S: case WebAssembly::LOAD8_S_I64_A64_S: case WebAssembly::LOAD8_U_I32_A32_S: case WebAssembly::LOAD8_U_I32_A64_S: case WebAssembly::LOAD8_U_I64_A32_S: case WebAssembly::LOAD8_U_I64_A64_S: case WebAssembly::LOAD_EXTEND_S_I16x8_A32_S: case WebAssembly::LOAD_EXTEND_S_I16x8_A64_S: case WebAssembly::LOAD_EXTEND_S_I32x4_A32_S: case WebAssembly::LOAD_EXTEND_S_I32x4_A64_S: case WebAssembly::LOAD_EXTEND_S_I64x2_A32_S: case WebAssembly::LOAD_EXTEND_S_I64x2_A64_S: case WebAssembly::LOAD_EXTEND_U_I16x8_A32_S: case WebAssembly::LOAD_EXTEND_U_I16x8_A64_S: case WebAssembly::LOAD_EXTEND_U_I32x4_A32_S: case WebAssembly::LOAD_EXTEND_U_I32x4_A64_S: case WebAssembly::LOAD_EXTEND_U_I64x2_A32_S: case WebAssembly::LOAD_EXTEND_U_I64x2_A64_S: case WebAssembly::LOAD_F16_F32_A32_S: case WebAssembly::LOAD_F16_F32_A64_S: case WebAssembly::LOAD_F32_A32_S: case WebAssembly::LOAD_F32_A64_S: case WebAssembly::LOAD_F64_A32_S: case WebAssembly::LOAD_F64_A64_S: case WebAssembly::LOAD_I32_A32_S: case WebAssembly::LOAD_I32_A64_S: case WebAssembly::LOAD_I64_A32_S: case WebAssembly::LOAD_I64_A64_S: case WebAssembly::LOAD_V128_A32_S: case WebAssembly::LOAD_V128_A64_S: case WebAssembly::LOAD_ZERO_32_A32_S: case WebAssembly::LOAD_ZERO_32_A64_S: case WebAssembly::LOAD_ZERO_64_A32_S: case WebAssembly::LOAD_ZERO_64_A64_S: case WebAssembly::MEMORY_ATOMIC_NOTIFY_A32_S: case WebAssembly::MEMORY_ATOMIC_NOTIFY_A64_S: case WebAssembly::MEMORY_ATOMIC_WAIT32_A32_S: case WebAssembly::MEMORY_ATOMIC_WAIT32_A64_S: case WebAssembly::MEMORY_ATOMIC_WAIT64_A32_S: case WebAssembly::MEMORY_ATOMIC_WAIT64_A64_S: case WebAssembly::STORE16_I32_A32_S: case WebAssembly::STORE16_I32_A64_S: case WebAssembly::STORE16_I64_A32_S: case WebAssembly::STORE16_I64_A64_S: case WebAssembly::STORE32_I64_A32_S: case WebAssembly::STORE32_I64_A64_S: case WebAssembly::STORE8_I32_A32_S: case WebAssembly::STORE8_I32_A64_S: case WebAssembly::STORE8_I64_A32_S: case WebAssembly::STORE8_I64_A64_S: case WebAssembly::STORE_F16_F32_A32_S: case WebAssembly::STORE_F16_F32_A64_S: case WebAssembly::STORE_F32_A32_S: case WebAssembly::STORE_F32_A64_S: case WebAssembly::STORE_F64_A32_S: case WebAssembly::STORE_F64_A64_S: case WebAssembly::STORE_I32_A32_S: case WebAssembly::STORE_I32_A64_S: case WebAssembly::STORE_I64_A32_S: case WebAssembly::STORE_I64_A64_S: case WebAssembly::STORE_V128_A32_S: case WebAssembly::STORE_V128_A64_S: return OperandMap[6][NamedIdx]; case WebAssembly::ATOMIC_STORE16_I32_A32: case WebAssembly::ATOMIC_STORE16_I32_A64: case WebAssembly::ATOMIC_STORE16_I64_A32: case WebAssembly::ATOMIC_STORE16_I64_A64: case WebAssembly::ATOMIC_STORE32_I64_A32: case WebAssembly::ATOMIC_STORE32_I64_A64: case WebAssembly::ATOMIC_STORE8_I32_A32: case WebAssembly::ATOMIC_STORE8_I32_A64: case WebAssembly::ATOMIC_STORE8_I64_A32: case WebAssembly::ATOMIC_STORE8_I64_A64: case WebAssembly::ATOMIC_STORE_I32_A32: case WebAssembly::ATOMIC_STORE_I32_A64: case WebAssembly::ATOMIC_STORE_I64_A32: case WebAssembly::ATOMIC_STORE_I64_A64: case WebAssembly::STORE16_I32_A32: case WebAssembly::STORE16_I32_A64: case WebAssembly::STORE16_I64_A32: case WebAssembly::STORE16_I64_A64: case WebAssembly::STORE32_I64_A32: case WebAssembly::STORE32_I64_A64: case WebAssembly::STORE8_I32_A32: case WebAssembly::STORE8_I32_A64: case WebAssembly::STORE8_I64_A32: case WebAssembly::STORE8_I64_A64: case WebAssembly::STORE_F16_F32_A32: case WebAssembly::STORE_F16_F32_A64: case WebAssembly::STORE_F32_A32: case WebAssembly::STORE_F32_A64: case WebAssembly::STORE_F64_A32: case WebAssembly::STORE_F64_A64: case WebAssembly::STORE_I32_A32: case WebAssembly::STORE_I32_A64: case WebAssembly::STORE_I64_A32: case WebAssembly::STORE_I64_A64: return OperandMap[7][NamedIdx]; case WebAssembly::STORE_V128_A32: case WebAssembly::STORE_V128_A64: return OperandMap[8][NamedIdx]; case WebAssembly::STORE_LANE_I16x8_A32: case WebAssembly::STORE_LANE_I16x8_A64: case WebAssembly::STORE_LANE_I32x4_A32: case WebAssembly::STORE_LANE_I32x4_A64: case WebAssembly::STORE_LANE_I64x2_A32: case WebAssembly::STORE_LANE_I64x2_A64: case WebAssembly::STORE_LANE_I8x16_A32: case WebAssembly::STORE_LANE_I8x16_A64: return OperandMap[9][NamedIdx]; case WebAssembly::LOAD_LANE_16_A32_S: case WebAssembly::LOAD_LANE_16_A64_S: case WebAssembly::LOAD_LANE_32_A32_S: case WebAssembly::LOAD_LANE_32_A64_S: case WebAssembly::LOAD_LANE_64_A32_S: case WebAssembly::LOAD_LANE_64_A64_S: case WebAssembly::LOAD_LANE_8_A32_S: case WebAssembly::LOAD_LANE_8_A64_S: case WebAssembly::STORE_LANE_I16x8_A32_S: case WebAssembly::STORE_LANE_I16x8_A64_S: case WebAssembly::STORE_LANE_I32x4_A32_S: case WebAssembly::STORE_LANE_I32x4_A64_S: case WebAssembly::STORE_LANE_I64x2_A32_S: case WebAssembly::STORE_LANE_I64x2_A64_S: case WebAssembly::STORE_LANE_I8x16_A32_S: case WebAssembly::STORE_LANE_I8x16_A64_S: return OperandMap[10][NamedIdx]; default: return -1; } } } // end namespace WebAssembly } // end namespace llvm #endif //GET_INSTRINFO_NAMED_OPS #ifdef GET_INSTRINFO_OPERAND_TYPES_ENUM #undef GET_INSTRINFO_OPERAND_TYPES_ENUM namespace llvm { namespace WebAssembly { namespace OpTypes { enum OperandType { P2Align = 0, Signature = 1, TypeIndex = 2, bb_op = 3, brlist = 4, f32imm = 5, f32imm_op = 6, f64imm = 7, f64imm_op = 8, function32_op = 9, global_op32 = 10, global_op64 = 11, i1imm = 12, i8imm = 13, i16imm = 14, i32imm = 15, i32imm_op = 16, i64imm = 17, i64imm_op = 18, local_op = 19, offset32_op = 20, offset64_op = 21, ptype0 = 22, ptype1 = 23, ptype2 = 24, ptype3 = 25, ptype4 = 26, ptype5 = 27, table32_op = 28, tag_op = 29, type0 = 30, type1 = 31, type2 = 32, type3 = 33, type4 = 34, type5 = 35, untyped_imm_0 = 36, vec_i8imm_op = 37, vec_i16imm_op = 38, vec_i32imm_op = 39, vec_i64imm_op = 40, EXNREF = 41, EXTERNREF = 42, F32 = 43, F64 = 44, FUNCREF = 45, I32 = 46, I64 = 47, V128 = 48, OPERAND_TYPE_LIST_END }; } // end namespace OpTypes } // end namespace WebAssembly } // end namespace llvm #endif // GET_INSTRINFO_OPERAND_TYPES_ENUM #ifdef GET_INSTRINFO_OPERAND_TYPE #undef GET_INSTRINFO_OPERAND_TYPE namespace llvm { namespace WebAssembly { LLVM_READONLY static int getOperandType(uint16_t Opcode, uint16_t OpIdx) { static const uint16_t Offsets[] = { /* PHI */ 0, /* INLINEASM */ 1, /* INLINEASM_BR */ 1, /* CFI_INSTRUCTION */ 1, /* EH_LABEL */ 2, /* GC_LABEL */ 3, /* ANNOTATION_LABEL */ 4, /* KILL */ 5, /* EXTRACT_SUBREG */ 5, /* INSERT_SUBREG */ 8, /* IMPLICIT_DEF */ 12, /* SUBREG_TO_REG */ 13, /* COPY_TO_REGCLASS */ 17, /* DBG_VALUE */ 20, /* DBG_VALUE_LIST */ 20, /* DBG_INSTR_REF */ 20, /* DBG_PHI */ 20, /* DBG_LABEL */ 20, /* REG_SEQUENCE */ 21, /* COPY */ 23, /* BUNDLE */ 25, /* LIFETIME_START */ 25, /* LIFETIME_END */ 26, /* PSEUDO_PROBE */ 27, /* ARITH_FENCE */ 31, /* STACKMAP */ 33, /* FENTRY_CALL */ 35, /* PATCHPOINT */ 35, /* LOAD_STACK_GUARD */ 41, /* PREALLOCATED_SETUP */ 42, /* PREALLOCATED_ARG */ 43, /* STATEPOINT */ 46, /* LOCAL_ESCAPE */ 46, /* FAULTING_OP */ 48, /* PATCHABLE_OP */ 49, /* PATCHABLE_FUNCTION_ENTER */ 49, /* PATCHABLE_RET */ 49, /* PATCHABLE_FUNCTION_EXIT */ 49, /* PATCHABLE_TAIL_CALL */ 49, /* PATCHABLE_EVENT_CALL */ 49, /* PATCHABLE_TYPED_EVENT_CALL */ 51, /* ICALL_BRANCH_FUNNEL */ 54, /* FAKE_USE */ 54, /* MEMBARRIER */ 54, /* JUMP_TABLE_DEBUG_INFO */ 54, /* CONVERGENCECTRL_ENTRY */ 55, /* CONVERGENCECTRL_ANCHOR */ 56, /* CONVERGENCECTRL_LOOP */ 57, /* CONVERGENCECTRL_GLUE */ 59, /* G_ASSERT_SEXT */ 60, /* G_ASSERT_ZEXT */ 63, /* G_ASSERT_ALIGN */ 66, /* G_ADD */ 69, /* G_SUB */ 72, /* G_MUL */ 75, /* G_SDIV */ 78, /* G_UDIV */ 81, /* G_SREM */ 84, /* G_UREM */ 87, /* G_SDIVREM */ 90, /* G_UDIVREM */ 94, /* G_AND */ 98, /* G_OR */ 101, /* G_XOR */ 104, /* G_IMPLICIT_DEF */ 107, /* G_PHI */ 108, /* G_FRAME_INDEX */ 109, /* G_GLOBAL_VALUE */ 111, /* G_PTRAUTH_GLOBAL_VALUE */ 113, /* G_CONSTANT_POOL */ 118, /* G_EXTRACT */ 120, /* G_UNMERGE_VALUES */ 123, /* G_INSERT */ 125, /* G_MERGE_VALUES */ 129, /* G_BUILD_VECTOR */ 131, /* G_BUILD_VECTOR_TRUNC */ 133, /* G_CONCAT_VECTORS */ 135, /* G_PTRTOINT */ 137, /* G_INTTOPTR */ 139, /* G_BITCAST */ 141, /* G_FREEZE */ 143, /* G_CONSTANT_FOLD_BARRIER */ 145, /* G_INTRINSIC_FPTRUNC_ROUND */ 147, /* G_INTRINSIC_TRUNC */ 150, /* G_INTRINSIC_ROUND */ 152, /* G_INTRINSIC_LRINT */ 154, /* G_INTRINSIC_LLRINT */ 156, /* G_INTRINSIC_ROUNDEVEN */ 158, /* G_READCYCLECOUNTER */ 160, /* G_READSTEADYCOUNTER */ 161, /* G_LOAD */ 162, /* G_SEXTLOAD */ 164, /* G_ZEXTLOAD */ 166, /* G_INDEXED_LOAD */ 168, /* G_INDEXED_SEXTLOAD */ 173, /* G_INDEXED_ZEXTLOAD */ 178, /* G_STORE */ 183, /* G_INDEXED_STORE */ 185, /* G_ATOMIC_CMPXCHG_WITH_SUCCESS */ 190, /* G_ATOMIC_CMPXCHG */ 195, /* G_ATOMICRMW_XCHG */ 199, /* G_ATOMICRMW_ADD */ 202, /* G_ATOMICRMW_SUB */ 205, /* G_ATOMICRMW_AND */ 208, /* G_ATOMICRMW_NAND */ 211, /* G_ATOMICRMW_OR */ 214, /* G_ATOMICRMW_XOR */ 217, /* G_ATOMICRMW_MAX */ 220, /* G_ATOMICRMW_MIN */ 223, /* G_ATOMICRMW_UMAX */ 226, /* G_ATOMICRMW_UMIN */ 229, /* G_ATOMICRMW_FADD */ 232, /* G_ATOMICRMW_FSUB */ 235, /* G_ATOMICRMW_FMAX */ 238, /* G_ATOMICRMW_FMIN */ 241, /* G_ATOMICRMW_UINC_WRAP */ 244, /* G_ATOMICRMW_UDEC_WRAP */ 247, /* G_FENCE */ 250, /* G_PREFETCH */ 252, /* G_BRCOND */ 256, /* G_BRINDIRECT */ 258, /* G_INVOKE_REGION_START */ 259, /* G_INTRINSIC */ 259, /* G_INTRINSIC_W_SIDE_EFFECTS */ 260, /* G_INTRINSIC_CONVERGENT */ 261, /* G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS */ 262, /* G_ANYEXT */ 263, /* G_TRUNC */ 265, /* G_CONSTANT */ 267, /* G_FCONSTANT */ 269, /* G_VASTART */ 271, /* G_VAARG */ 272, /* G_SEXT */ 275, /* G_SEXT_INREG */ 277, /* G_ZEXT */ 280, /* G_SHL */ 282, /* G_LSHR */ 285, /* G_ASHR */ 288, /* G_FSHL */ 291, /* G_FSHR */ 295, /* G_ROTR */ 299, /* G_ROTL */ 302, /* G_ICMP */ 305, /* G_FCMP */ 309, /* G_SCMP */ 313, /* G_UCMP */ 316, /* G_SELECT */ 319, /* G_UADDO */ 323, /* G_UADDE */ 327, /* G_USUBO */ 332, /* G_USUBE */ 336, /* G_SADDO */ 341, /* G_SADDE */ 345, /* G_SSUBO */ 350, /* G_SSUBE */ 354, /* G_UMULO */ 359, /* G_SMULO */ 363, /* G_UMULH */ 367, /* G_SMULH */ 370, /* G_UADDSAT */ 373, /* G_SADDSAT */ 376, /* G_USUBSAT */ 379, /* G_SSUBSAT */ 382, /* G_USHLSAT */ 385, /* G_SSHLSAT */ 388, /* G_SMULFIX */ 391, /* G_UMULFIX */ 395, /* G_SMULFIXSAT */ 399, /* G_UMULFIXSAT */ 403, /* G_SDIVFIX */ 407, /* G_UDIVFIX */ 411, /* G_SDIVFIXSAT */ 415, /* G_UDIVFIXSAT */ 419, /* G_FADD */ 423, /* G_FSUB */ 426, /* G_FMUL */ 429, /* G_FMA */ 432, /* G_FMAD */ 436, /* G_FDIV */ 440, /* G_FREM */ 443, /* G_FPOW */ 446, /* G_FPOWI */ 449, /* G_FEXP */ 452, /* G_FEXP2 */ 454, /* G_FEXP10 */ 456, /* G_FLOG */ 458, /* G_FLOG2 */ 460, /* G_FLOG10 */ 462, /* G_FLDEXP */ 464, /* G_FFREXP */ 467, /* G_FNEG */ 470, /* G_FPEXT */ 472, /* G_FPTRUNC */ 474, /* G_FPTOSI */ 476, /* G_FPTOUI */ 478, /* G_SITOFP */ 480, /* G_UITOFP */ 482, /* G_FABS */ 484, /* G_FCOPYSIGN */ 486, /* G_IS_FPCLASS */ 489, /* G_FCANONICALIZE */ 492, /* G_FMINNUM */ 494, /* G_FMAXNUM */ 497, /* G_FMINNUM_IEEE */ 500, /* G_FMAXNUM_IEEE */ 503, /* G_FMINIMUM */ 506, /* G_FMAXIMUM */ 509, /* G_GET_FPENV */ 512, /* G_SET_FPENV */ 513, /* G_RESET_FPENV */ 514, /* G_GET_FPMODE */ 514, /* G_SET_FPMODE */ 515, /* G_RESET_FPMODE */ 516, /* G_PTR_ADD */ 516, /* G_PTRMASK */ 519, /* G_SMIN */ 522, /* G_SMAX */ 525, /* G_UMIN */ 528, /* G_UMAX */ 531, /* G_ABS */ 534, /* G_LROUND */ 536, /* G_LLROUND */ 538, /* G_BR */ 540, /* G_BRJT */ 541, /* G_VSCALE */ 544, /* G_INSERT_SUBVECTOR */ 546, /* G_EXTRACT_SUBVECTOR */ 550, /* G_INSERT_VECTOR_ELT */ 553, /* G_EXTRACT_VECTOR_ELT */ 557, /* G_SHUFFLE_VECTOR */ 560, /* G_SPLAT_VECTOR */ 564, /* G_VECTOR_COMPRESS */ 566, /* G_CTTZ */ 570, /* G_CTTZ_ZERO_UNDEF */ 572, /* G_CTLZ */ 574, /* G_CTLZ_ZERO_UNDEF */ 576, /* G_CTPOP */ 578, /* G_BSWAP */ 580, /* G_BITREVERSE */ 582, /* G_FCEIL */ 584, /* G_FCOS */ 586, /* G_FSIN */ 588, /* G_FTAN */ 590, /* G_FACOS */ 592, /* G_FASIN */ 594, /* G_FATAN */ 596, /* G_FCOSH */ 598, /* G_FSINH */ 600, /* G_FTANH */ 602, /* G_FSQRT */ 604, /* G_FFLOOR */ 606, /* G_FRINT */ 608, /* G_FNEARBYINT */ 610, /* G_ADDRSPACE_CAST */ 612, /* G_BLOCK_ADDR */ 614, /* G_JUMP_TABLE */ 616, /* G_DYN_STACKALLOC */ 618, /* G_STACKSAVE */ 621, /* G_STACKRESTORE */ 622, /* G_STRICT_FADD */ 623, /* G_STRICT_FSUB */ 626, /* G_STRICT_FMUL */ 629, /* G_STRICT_FDIV */ 632, /* G_STRICT_FREM */ 635, /* G_STRICT_FMA */ 638, /* G_STRICT_FSQRT */ 642, /* G_STRICT_FLDEXP */ 644, /* G_READ_REGISTER */ 647, /* G_WRITE_REGISTER */ 649, /* G_MEMCPY */ 651, /* G_MEMCPY_INLINE */ 655, /* G_MEMMOVE */ 658, /* G_MEMSET */ 662, /* G_BZERO */ 666, /* G_TRAP */ 669, /* G_DEBUGTRAP */ 669, /* G_UBSANTRAP */ 669, /* G_VECREDUCE_SEQ_FADD */ 670, /* G_VECREDUCE_SEQ_FMUL */ 673, /* G_VECREDUCE_FADD */ 676, /* G_VECREDUCE_FMUL */ 678, /* G_VECREDUCE_FMAX */ 680, /* G_VECREDUCE_FMIN */ 682, /* G_VECREDUCE_FMAXIMUM */ 684, /* G_VECREDUCE_FMINIMUM */ 686, /* G_VECREDUCE_ADD */ 688, /* G_VECREDUCE_MUL */ 690, /* G_VECREDUCE_AND */ 692, /* G_VECREDUCE_OR */ 694, /* G_VECREDUCE_XOR */ 696, /* G_VECREDUCE_SMAX */ 698, /* G_VECREDUCE_SMIN */ 700, /* G_VECREDUCE_UMAX */ 702, /* G_VECREDUCE_UMIN */ 704, /* G_SBFX */ 706, /* G_UBFX */ 710, /* CALL_PARAMS */ 714, /* CALL_PARAMS_S */ 715, /* CALL_RESULTS */ 716, /* CALL_RESULTS_S */ 716, /* CATCHRET */ 716, /* CATCHRET_S */ 718, /* CLEANUPRET */ 720, /* CLEANUPRET_S */ 720, /* COMPILER_FENCE */ 720, /* COMPILER_FENCE_S */ 720, /* RET_CALL_RESULTS */ 720, /* RET_CALL_RESULTS_S */ 720, /* ABS_F16x8 */ 720, /* ABS_F16x8_S */ 722, /* ABS_F32 */ 722, /* ABS_F32_S */ 724, /* ABS_F32x4 */ 724, /* ABS_F32x4_S */ 726, /* ABS_F64 */ 726, /* ABS_F64_S */ 728, /* ABS_F64x2 */ 728, /* ABS_F64x2_S */ 730, /* ABS_I16x8 */ 730, /* ABS_I16x8_S */ 732, /* ABS_I32x4 */ 732, /* ABS_I32x4_S */ 734, /* ABS_I64x2 */ 734, /* ABS_I64x2_S */ 736, /* ABS_I8x16 */ 736, /* ABS_I8x16_S */ 738, /* ADD_F16x8 */ 738, /* ADD_F16x8_S */ 741, /* ADD_F32 */ 741, /* ADD_F32_S */ 744, /* ADD_F32x4 */ 744, /* ADD_F32x4_S */ 747, /* ADD_F64 */ 747, /* ADD_F64_S */ 750, /* ADD_F64x2 */ 750, /* ADD_F64x2_S */ 753, /* ADD_I16x8 */ 753, /* ADD_I16x8_S */ 756, /* ADD_I32 */ 756, /* ADD_I32_S */ 759, /* ADD_I32x4 */ 759, /* ADD_I32x4_S */ 762, /* ADD_I64 */ 762, /* ADD_I64_S */ 765, /* ADD_I64x2 */ 765, /* ADD_I64x2_S */ 768, /* ADD_I8x16 */ 768, /* ADD_I8x16_S */ 771, /* ADD_SAT_S_I16x8 */ 771, /* ADD_SAT_S_I16x8_S */ 774, /* ADD_SAT_S_I8x16 */ 774, /* ADD_SAT_S_I8x16_S */ 777, /* ADD_SAT_U_I16x8 */ 777, /* ADD_SAT_U_I16x8_S */ 780, /* ADD_SAT_U_I8x16 */ 780, /* ADD_SAT_U_I8x16_S */ 783, /* ADJCALLSTACKDOWN */ 783, /* ADJCALLSTACKDOWN_S */ 785, /* ADJCALLSTACKUP */ 787, /* ADJCALLSTACKUP_S */ 789, /* ALLTRUE_I16x8 */ 791, /* ALLTRUE_I16x8_S */ 793, /* ALLTRUE_I32x4 */ 793, /* ALLTRUE_I32x4_S */ 795, /* ALLTRUE_I64x2 */ 795, /* ALLTRUE_I64x2_S */ 797, /* ALLTRUE_I8x16 */ 797, /* ALLTRUE_I8x16_S */ 799, /* AND */ 799, /* ANDNOT */ 802, /* ANDNOT_S */ 805, /* AND_I32 */ 805, /* AND_I32_S */ 808, /* AND_I64 */ 808, /* AND_I64_S */ 811, /* AND_S */ 811, /* ANYTRUE */ 811, /* ANYTRUE_S */ 813, /* ARGUMENT_exnref */ 813, /* ARGUMENT_exnref_S */ 815, /* ARGUMENT_externref */ 816, /* ARGUMENT_externref_S */ 818, /* ARGUMENT_f32 */ 819, /* ARGUMENT_f32_S */ 821, /* ARGUMENT_f64 */ 822, /* ARGUMENT_f64_S */ 824, /* ARGUMENT_funcref */ 825, /* ARGUMENT_funcref_S */ 827, /* ARGUMENT_i32 */ 828, /* ARGUMENT_i32_S */ 830, /* ARGUMENT_i64 */ 831, /* ARGUMENT_i64_S */ 833, /* ARGUMENT_v16i8 */ 834, /* ARGUMENT_v16i8_S */ 836, /* ARGUMENT_v2f64 */ 837, /* ARGUMENT_v2f64_S */ 839, /* ARGUMENT_v2i64 */ 840, /* ARGUMENT_v2i64_S */ 842, /* ARGUMENT_v4f32 */ 843, /* ARGUMENT_v4f32_S */ 845, /* ARGUMENT_v4i32 */ 846, /* ARGUMENT_v4i32_S */ 848, /* ARGUMENT_v8f16 */ 849, /* ARGUMENT_v8f16_S */ 851, /* ARGUMENT_v8i16 */ 852, /* ARGUMENT_v8i16_S */ 854, /* ATOMIC_FENCE */ 855, /* ATOMIC_FENCE_S */ 856, /* ATOMIC_LOAD16_U_I32_A32 */ 857, /* ATOMIC_LOAD16_U_I32_A32_S */ 861, /* ATOMIC_LOAD16_U_I32_A64 */ 863, /* ATOMIC_LOAD16_U_I32_A64_S */ 867, /* ATOMIC_LOAD16_U_I64_A32 */ 869, /* ATOMIC_LOAD16_U_I64_A32_S */ 873, /* ATOMIC_LOAD16_U_I64_A64 */ 875, /* ATOMIC_LOAD16_U_I64_A64_S */ 879, /* ATOMIC_LOAD32_U_I64_A32 */ 881, /* ATOMIC_LOAD32_U_I64_A32_S */ 885, /* ATOMIC_LOAD32_U_I64_A64 */ 887, /* ATOMIC_LOAD32_U_I64_A64_S */ 891, /* ATOMIC_LOAD8_U_I32_A32 */ 893, /* ATOMIC_LOAD8_U_I32_A32_S */ 897, /* ATOMIC_LOAD8_U_I32_A64 */ 899, /* ATOMIC_LOAD8_U_I32_A64_S */ 903, /* ATOMIC_LOAD8_U_I64_A32 */ 905, /* ATOMIC_LOAD8_U_I64_A32_S */ 909, /* ATOMIC_LOAD8_U_I64_A64 */ 911, /* ATOMIC_LOAD8_U_I64_A64_S */ 915, /* ATOMIC_LOAD_I32_A32 */ 917, /* ATOMIC_LOAD_I32_A32_S */ 921, /* ATOMIC_LOAD_I32_A64 */ 923, /* ATOMIC_LOAD_I32_A64_S */ 927, /* ATOMIC_LOAD_I64_A32 */ 929, /* ATOMIC_LOAD_I64_A32_S */ 933, /* ATOMIC_LOAD_I64_A64 */ 935, /* ATOMIC_LOAD_I64_A64_S */ 939, /* ATOMIC_RMW16_U_ADD_I32_A32 */ 941, /* ATOMIC_RMW16_U_ADD_I32_A32_S */ 946, /* ATOMIC_RMW16_U_ADD_I32_A64 */ 948, /* ATOMIC_RMW16_U_ADD_I32_A64_S */ 953, /* ATOMIC_RMW16_U_ADD_I64_A32 */ 955, /* ATOMIC_RMW16_U_ADD_I64_A32_S */ 960, /* ATOMIC_RMW16_U_ADD_I64_A64 */ 962, /* ATOMIC_RMW16_U_ADD_I64_A64_S */ 967, /* ATOMIC_RMW16_U_AND_I32_A32 */ 969, /* ATOMIC_RMW16_U_AND_I32_A32_S */ 974, /* ATOMIC_RMW16_U_AND_I32_A64 */ 976, /* ATOMIC_RMW16_U_AND_I32_A64_S */ 981, /* ATOMIC_RMW16_U_AND_I64_A32 */ 983, /* ATOMIC_RMW16_U_AND_I64_A32_S */ 988, /* ATOMIC_RMW16_U_AND_I64_A64 */ 990, /* ATOMIC_RMW16_U_AND_I64_A64_S */ 995, /* ATOMIC_RMW16_U_CMPXCHG_I32_A32 */ 997, /* ATOMIC_RMW16_U_CMPXCHG_I32_A32_S */ 1003, /* ATOMIC_RMW16_U_CMPXCHG_I32_A64 */ 1005, /* ATOMIC_RMW16_U_CMPXCHG_I32_A64_S */ 1011, /* ATOMIC_RMW16_U_CMPXCHG_I64_A32 */ 1013, /* ATOMIC_RMW16_U_CMPXCHG_I64_A32_S */ 1019, /* ATOMIC_RMW16_U_CMPXCHG_I64_A64 */ 1021, /* ATOMIC_RMW16_U_CMPXCHG_I64_A64_S */ 1027, /* ATOMIC_RMW16_U_OR_I32_A32 */ 1029, /* ATOMIC_RMW16_U_OR_I32_A32_S */ 1034, /* ATOMIC_RMW16_U_OR_I32_A64 */ 1036, /* ATOMIC_RMW16_U_OR_I32_A64_S */ 1041, /* ATOMIC_RMW16_U_OR_I64_A32 */ 1043, /* ATOMIC_RMW16_U_OR_I64_A32_S */ 1048, /* ATOMIC_RMW16_U_OR_I64_A64 */ 1050, /* ATOMIC_RMW16_U_OR_I64_A64_S */ 1055, /* ATOMIC_RMW16_U_SUB_I32_A32 */ 1057, /* ATOMIC_RMW16_U_SUB_I32_A32_S */ 1062, /* ATOMIC_RMW16_U_SUB_I32_A64 */ 1064, /* ATOMIC_RMW16_U_SUB_I32_A64_S */ 1069, /* ATOMIC_RMW16_U_SUB_I64_A32 */ 1071, /* ATOMIC_RMW16_U_SUB_I64_A32_S */ 1076, /* ATOMIC_RMW16_U_SUB_I64_A64 */ 1078, /* ATOMIC_RMW16_U_SUB_I64_A64_S */ 1083, /* ATOMIC_RMW16_U_XCHG_I32_A32 */ 1085, /* ATOMIC_RMW16_U_XCHG_I32_A32_S */ 1090, /* ATOMIC_RMW16_U_XCHG_I32_A64 */ 1092, /* ATOMIC_RMW16_U_XCHG_I32_A64_S */ 1097, /* ATOMIC_RMW16_U_XCHG_I64_A32 */ 1099, /* ATOMIC_RMW16_U_XCHG_I64_A32_S */ 1104, /* ATOMIC_RMW16_U_XCHG_I64_A64 */ 1106, /* ATOMIC_RMW16_U_XCHG_I64_A64_S */ 1111, /* ATOMIC_RMW16_U_XOR_I32_A32 */ 1113, /* ATOMIC_RMW16_U_XOR_I32_A32_S */ 1118, /* ATOMIC_RMW16_U_XOR_I32_A64 */ 1120, /* ATOMIC_RMW16_U_XOR_I32_A64_S */ 1125, /* ATOMIC_RMW16_U_XOR_I64_A32 */ 1127, /* ATOMIC_RMW16_U_XOR_I64_A32_S */ 1132, /* ATOMIC_RMW16_U_XOR_I64_A64 */ 1134, /* ATOMIC_RMW16_U_XOR_I64_A64_S */ 1139, /* ATOMIC_RMW32_U_ADD_I64_A32 */ 1141, /* ATOMIC_RMW32_U_ADD_I64_A32_S */ 1146, /* ATOMIC_RMW32_U_ADD_I64_A64 */ 1148, /* ATOMIC_RMW32_U_ADD_I64_A64_S */ 1153, /* ATOMIC_RMW32_U_AND_I64_A32 */ 1155, /* ATOMIC_RMW32_U_AND_I64_A32_S */ 1160, /* ATOMIC_RMW32_U_AND_I64_A64 */ 1162, /* ATOMIC_RMW32_U_AND_I64_A64_S */ 1167, /* ATOMIC_RMW32_U_CMPXCHG_I64_A32 */ 1169, /* ATOMIC_RMW32_U_CMPXCHG_I64_A32_S */ 1175, /* ATOMIC_RMW32_U_CMPXCHG_I64_A64 */ 1177, /* ATOMIC_RMW32_U_CMPXCHG_I64_A64_S */ 1183, /* ATOMIC_RMW32_U_OR_I64_A32 */ 1185, /* ATOMIC_RMW32_U_OR_I64_A32_S */ 1190, /* ATOMIC_RMW32_U_OR_I64_A64 */ 1192, /* ATOMIC_RMW32_U_OR_I64_A64_S */ 1197, /* ATOMIC_RMW32_U_SUB_I64_A32 */ 1199, /* ATOMIC_RMW32_U_SUB_I64_A32_S */ 1204, /* ATOMIC_RMW32_U_SUB_I64_A64 */ 1206, /* ATOMIC_RMW32_U_SUB_I64_A64_S */ 1211, /* ATOMIC_RMW32_U_XCHG_I64_A32 */ 1213, /* ATOMIC_RMW32_U_XCHG_I64_A32_S */ 1218, /* ATOMIC_RMW32_U_XCHG_I64_A64 */ 1220, /* ATOMIC_RMW32_U_XCHG_I64_A64_S */ 1225, /* ATOMIC_RMW32_U_XOR_I64_A32 */ 1227, /* ATOMIC_RMW32_U_XOR_I64_A32_S */ 1232, /* ATOMIC_RMW32_U_XOR_I64_A64 */ 1234, /* ATOMIC_RMW32_U_XOR_I64_A64_S */ 1239, /* ATOMIC_RMW8_U_ADD_I32_A32 */ 1241, /* ATOMIC_RMW8_U_ADD_I32_A32_S */ 1246, /* ATOMIC_RMW8_U_ADD_I32_A64 */ 1248, /* ATOMIC_RMW8_U_ADD_I32_A64_S */ 1253, /* ATOMIC_RMW8_U_ADD_I64_A32 */ 1255, /* ATOMIC_RMW8_U_ADD_I64_A32_S */ 1260, /* ATOMIC_RMW8_U_ADD_I64_A64 */ 1262, /* ATOMIC_RMW8_U_ADD_I64_A64_S */ 1267, /* ATOMIC_RMW8_U_AND_I32_A32 */ 1269, /* ATOMIC_RMW8_U_AND_I32_A32_S */ 1274, /* ATOMIC_RMW8_U_AND_I32_A64 */ 1276, /* ATOMIC_RMW8_U_AND_I32_A64_S */ 1281, /* ATOMIC_RMW8_U_AND_I64_A32 */ 1283, /* ATOMIC_RMW8_U_AND_I64_A32_S */ 1288, /* ATOMIC_RMW8_U_AND_I64_A64 */ 1290, /* ATOMIC_RMW8_U_AND_I64_A64_S */ 1295, /* ATOMIC_RMW8_U_CMPXCHG_I32_A32 */ 1297, /* ATOMIC_RMW8_U_CMPXCHG_I32_A32_S */ 1303, /* ATOMIC_RMW8_U_CMPXCHG_I32_A64 */ 1305, /* ATOMIC_RMW8_U_CMPXCHG_I32_A64_S */ 1311, /* ATOMIC_RMW8_U_CMPXCHG_I64_A32 */ 1313, /* ATOMIC_RMW8_U_CMPXCHG_I64_A32_S */ 1319, /* ATOMIC_RMW8_U_CMPXCHG_I64_A64 */ 1321, /* ATOMIC_RMW8_U_CMPXCHG_I64_A64_S */ 1327, /* ATOMIC_RMW8_U_OR_I32_A32 */ 1329, /* ATOMIC_RMW8_U_OR_I32_A32_S */ 1334, /* ATOMIC_RMW8_U_OR_I32_A64 */ 1336, /* ATOMIC_RMW8_U_OR_I32_A64_S */ 1341, /* ATOMIC_RMW8_U_OR_I64_A32 */ 1343, /* ATOMIC_RMW8_U_OR_I64_A32_S */ 1348, /* ATOMIC_RMW8_U_OR_I64_A64 */ 1350, /* ATOMIC_RMW8_U_OR_I64_A64_S */ 1355, /* ATOMIC_RMW8_U_SUB_I32_A32 */ 1357, /* ATOMIC_RMW8_U_SUB_I32_A32_S */ 1362, /* ATOMIC_RMW8_U_SUB_I32_A64 */ 1364, /* ATOMIC_RMW8_U_SUB_I32_A64_S */ 1369, /* ATOMIC_RMW8_U_SUB_I64_A32 */ 1371, /* ATOMIC_RMW8_U_SUB_I64_A32_S */ 1376, /* ATOMIC_RMW8_U_SUB_I64_A64 */ 1378, /* ATOMIC_RMW8_U_SUB_I64_A64_S */ 1383, /* ATOMIC_RMW8_U_XCHG_I32_A32 */ 1385, /* ATOMIC_RMW8_U_XCHG_I32_A32_S */ 1390, /* ATOMIC_RMW8_U_XCHG_I32_A64 */ 1392, /* ATOMIC_RMW8_U_XCHG_I32_A64_S */ 1397, /* ATOMIC_RMW8_U_XCHG_I64_A32 */ 1399, /* ATOMIC_RMW8_U_XCHG_I64_A32_S */ 1404, /* ATOMIC_RMW8_U_XCHG_I64_A64 */ 1406, /* ATOMIC_RMW8_U_XCHG_I64_A64_S */ 1411, /* ATOMIC_RMW8_U_XOR_I32_A32 */ 1413, /* ATOMIC_RMW8_U_XOR_I32_A32_S */ 1418, /* ATOMIC_RMW8_U_XOR_I32_A64 */ 1420, /* ATOMIC_RMW8_U_XOR_I32_A64_S */ 1425, /* ATOMIC_RMW8_U_XOR_I64_A32 */ 1427, /* ATOMIC_RMW8_U_XOR_I64_A32_S */ 1432, /* ATOMIC_RMW8_U_XOR_I64_A64 */ 1434, /* ATOMIC_RMW8_U_XOR_I64_A64_S */ 1439, /* ATOMIC_RMW_ADD_I32_A32 */ 1441, /* ATOMIC_RMW_ADD_I32_A32_S */ 1446, /* ATOMIC_RMW_ADD_I32_A64 */ 1448, /* ATOMIC_RMW_ADD_I32_A64_S */ 1453, /* ATOMIC_RMW_ADD_I64_A32 */ 1455, /* ATOMIC_RMW_ADD_I64_A32_S */ 1460, /* ATOMIC_RMW_ADD_I64_A64 */ 1462, /* ATOMIC_RMW_ADD_I64_A64_S */ 1467, /* ATOMIC_RMW_AND_I32_A32 */ 1469, /* ATOMIC_RMW_AND_I32_A32_S */ 1474, /* ATOMIC_RMW_AND_I32_A64 */ 1476, /* ATOMIC_RMW_AND_I32_A64_S */ 1481, /* ATOMIC_RMW_AND_I64_A32 */ 1483, /* ATOMIC_RMW_AND_I64_A32_S */ 1488, /* ATOMIC_RMW_AND_I64_A64 */ 1490, /* ATOMIC_RMW_AND_I64_A64_S */ 1495, /* ATOMIC_RMW_CMPXCHG_I32_A32 */ 1497, /* ATOMIC_RMW_CMPXCHG_I32_A32_S */ 1503, /* ATOMIC_RMW_CMPXCHG_I32_A64 */ 1505, /* ATOMIC_RMW_CMPXCHG_I32_A64_S */ 1511, /* ATOMIC_RMW_CMPXCHG_I64_A32 */ 1513, /* ATOMIC_RMW_CMPXCHG_I64_A32_S */ 1519, /* ATOMIC_RMW_CMPXCHG_I64_A64 */ 1521, /* ATOMIC_RMW_CMPXCHG_I64_A64_S */ 1527, /* ATOMIC_RMW_OR_I32_A32 */ 1529, /* ATOMIC_RMW_OR_I32_A32_S */ 1534, /* ATOMIC_RMW_OR_I32_A64 */ 1536, /* ATOMIC_RMW_OR_I32_A64_S */ 1541, /* ATOMIC_RMW_OR_I64_A32 */ 1543, /* ATOMIC_RMW_OR_I64_A32_S */ 1548, /* ATOMIC_RMW_OR_I64_A64 */ 1550, /* ATOMIC_RMW_OR_I64_A64_S */ 1555, /* ATOMIC_RMW_SUB_I32_A32 */ 1557, /* ATOMIC_RMW_SUB_I32_A32_S */ 1562, /* ATOMIC_RMW_SUB_I32_A64 */ 1564, /* ATOMIC_RMW_SUB_I32_A64_S */ 1569, /* ATOMIC_RMW_SUB_I64_A32 */ 1571, /* ATOMIC_RMW_SUB_I64_A32_S */ 1576, /* ATOMIC_RMW_SUB_I64_A64 */ 1578, /* ATOMIC_RMW_SUB_I64_A64_S */ 1583, /* ATOMIC_RMW_XCHG_I32_A32 */ 1585, /* ATOMIC_RMW_XCHG_I32_A32_S */ 1590, /* ATOMIC_RMW_XCHG_I32_A64 */ 1592, /* ATOMIC_RMW_XCHG_I32_A64_S */ 1597, /* ATOMIC_RMW_XCHG_I64_A32 */ 1599, /* ATOMIC_RMW_XCHG_I64_A32_S */ 1604, /* ATOMIC_RMW_XCHG_I64_A64 */ 1606, /* ATOMIC_RMW_XCHG_I64_A64_S */ 1611, /* ATOMIC_RMW_XOR_I32_A32 */ 1613, /* ATOMIC_RMW_XOR_I32_A32_S */ 1618, /* ATOMIC_RMW_XOR_I32_A64 */ 1620, /* ATOMIC_RMW_XOR_I32_A64_S */ 1625, /* ATOMIC_RMW_XOR_I64_A32 */ 1627, /* ATOMIC_RMW_XOR_I64_A32_S */ 1632, /* ATOMIC_RMW_XOR_I64_A64 */ 1634, /* ATOMIC_RMW_XOR_I64_A64_S */ 1639, /* ATOMIC_STORE16_I32_A32 */ 1641, /* ATOMIC_STORE16_I32_A32_S */ 1645, /* ATOMIC_STORE16_I32_A64 */ 1647, /* ATOMIC_STORE16_I32_A64_S */ 1651, /* ATOMIC_STORE16_I64_A32 */ 1653, /* ATOMIC_STORE16_I64_A32_S */ 1657, /* ATOMIC_STORE16_I64_A64 */ 1659, /* ATOMIC_STORE16_I64_A64_S */ 1663, /* ATOMIC_STORE32_I64_A32 */ 1665, /* ATOMIC_STORE32_I64_A32_S */ 1669, /* ATOMIC_STORE32_I64_A64 */ 1671, /* ATOMIC_STORE32_I64_A64_S */ 1675, /* ATOMIC_STORE8_I32_A32 */ 1677, /* ATOMIC_STORE8_I32_A32_S */ 1681, /* ATOMIC_STORE8_I32_A64 */ 1683, /* ATOMIC_STORE8_I32_A64_S */ 1687, /* ATOMIC_STORE8_I64_A32 */ 1689, /* ATOMIC_STORE8_I64_A32_S */ 1693, /* ATOMIC_STORE8_I64_A64 */ 1695, /* ATOMIC_STORE8_I64_A64_S */ 1699, /* ATOMIC_STORE_I32_A32 */ 1701, /* ATOMIC_STORE_I32_A32_S */ 1705, /* ATOMIC_STORE_I32_A64 */ 1707, /* ATOMIC_STORE_I32_A64_S */ 1711, /* ATOMIC_STORE_I64_A32 */ 1713, /* ATOMIC_STORE_I64_A32_S */ 1717, /* ATOMIC_STORE_I64_A64 */ 1719, /* ATOMIC_STORE_I64_A64_S */ 1723, /* AVGR_U_I16x8 */ 1725, /* AVGR_U_I16x8_S */ 1728, /* AVGR_U_I8x16 */ 1728, /* AVGR_U_I8x16_S */ 1731, /* BITMASK_I16x8 */ 1731, /* BITMASK_I16x8_S */ 1733, /* BITMASK_I32x4 */ 1733, /* BITMASK_I32x4_S */ 1735, /* BITMASK_I64x2 */ 1735, /* BITMASK_I64x2_S */ 1737, /* BITMASK_I8x16 */ 1737, /* BITMASK_I8x16_S */ 1739, /* BITSELECT */ 1739, /* BITSELECT_S */ 1743, /* BLOCK */ 1743, /* BLOCK_S */ 1744, /* BR */ 1745, /* BR_IF */ 1746, /* BR_IF_S */ 1748, /* BR_S */ 1749, /* BR_TABLE_I32 */ 1750, /* BR_TABLE_I32_S */ 1751, /* BR_TABLE_I64 */ 1752, /* BR_TABLE_I64_S */ 1753, /* BR_UNLESS */ 1754, /* BR_UNLESS_S */ 1756, /* CALL */ 1757, /* CALL_INDIRECT */ 1758, /* CALL_INDIRECT_S */ 1760, /* CALL_S */ 1762, /* CATCH */ 1763, /* CATCH_ALL */ 1764, /* CATCH_ALL_S */ 1764, /* CATCH_S */ 1764, /* CEIL_F16x8 */ 1765, /* CEIL_F16x8_S */ 1767, /* CEIL_F32 */ 1767, /* CEIL_F32_S */ 1769, /* CEIL_F32x4 */ 1769, /* CEIL_F32x4_S */ 1771, /* CEIL_F64 */ 1771, /* CEIL_F64_S */ 1773, /* CEIL_F64x2 */ 1773, /* CEIL_F64x2_S */ 1775, /* CLZ_I32 */ 1775, /* CLZ_I32_S */ 1777, /* CLZ_I64 */ 1777, /* CLZ_I64_S */ 1779, /* CONST_F32 */ 1779, /* CONST_F32_S */ 1781, /* CONST_F64 */ 1782, /* CONST_F64_S */ 1784, /* CONST_I32 */ 1785, /* CONST_I32_S */ 1787, /* CONST_I64 */ 1788, /* CONST_I64_S */ 1790, /* CONST_V128_F32x4 */ 1791, /* CONST_V128_F32x4_S */ 1796, /* CONST_V128_F64x2 */ 1800, /* CONST_V128_F64x2_S */ 1803, /* CONST_V128_I16x8 */ 1805, /* CONST_V128_I16x8_S */ 1814, /* CONST_V128_I32x4 */ 1822, /* CONST_V128_I32x4_S */ 1827, /* CONST_V128_I64x2 */ 1831, /* CONST_V128_I64x2_S */ 1834, /* CONST_V128_I8x16 */ 1836, /* CONST_V128_I8x16_S */ 1853, /* COPYSIGN_F32 */ 1869, /* COPYSIGN_F32_S */ 1872, /* COPYSIGN_F64 */ 1872, /* COPYSIGN_F64_S */ 1875, /* COPY_EXNREF */ 1875, /* COPY_EXNREF_S */ 1877, /* COPY_EXTERNREF */ 1877, /* COPY_EXTERNREF_S */ 1879, /* COPY_F32 */ 1879, /* COPY_F32_S */ 1881, /* COPY_F64 */ 1881, /* COPY_F64_S */ 1883, /* COPY_FUNCREF */ 1883, /* COPY_FUNCREF_S */ 1885, /* COPY_I32 */ 1885, /* COPY_I32_S */ 1887, /* COPY_I64 */ 1887, /* COPY_I64_S */ 1889, /* COPY_V128 */ 1889, /* COPY_V128_S */ 1891, /* CTZ_I32 */ 1891, /* CTZ_I32_S */ 1893, /* CTZ_I64 */ 1893, /* CTZ_I64_S */ 1895, /* DEBUG_UNREACHABLE */ 1895, /* DEBUG_UNREACHABLE_S */ 1895, /* DELEGATE */ 1895, /* DELEGATE_S */ 1896, /* DIV_F16x8 */ 1897, /* DIV_F16x8_S */ 1900, /* DIV_F32 */ 1900, /* DIV_F32_S */ 1903, /* DIV_F32x4 */ 1903, /* DIV_F32x4_S */ 1906, /* DIV_F64 */ 1906, /* DIV_F64_S */ 1909, /* DIV_F64x2 */ 1909, /* DIV_F64x2_S */ 1912, /* DIV_S_I32 */ 1912, /* DIV_S_I32_S */ 1915, /* DIV_S_I64 */ 1915, /* DIV_S_I64_S */ 1918, /* DIV_U_I32 */ 1918, /* DIV_U_I32_S */ 1921, /* DIV_U_I64 */ 1921, /* DIV_U_I64_S */ 1924, /* DOT */ 1924, /* DOT_S */ 1927, /* DROP_EXNREF */ 1927, /* DROP_EXNREF_S */ 1928, /* DROP_EXTERNREF */ 1928, /* DROP_EXTERNREF_S */ 1929, /* DROP_F32 */ 1929, /* DROP_F32_S */ 1930, /* DROP_F64 */ 1930, /* DROP_F64_S */ 1931, /* DROP_FUNCREF */ 1931, /* DROP_FUNCREF_S */ 1932, /* DROP_I32 */ 1932, /* DROP_I32_S */ 1933, /* DROP_I64 */ 1933, /* DROP_I64_S */ 1934, /* DROP_V128 */ 1934, /* DROP_V128_S */ 1935, /* ELSE */ 1935, /* ELSE_S */ 1935, /* END */ 1935, /* END_BLOCK */ 1935, /* END_BLOCK_S */ 1935, /* END_FUNCTION */ 1935, /* END_FUNCTION_S */ 1935, /* END_IF */ 1935, /* END_IF_S */ 1935, /* END_LOOP */ 1935, /* END_LOOP_S */ 1935, /* END_S */ 1935, /* END_TRY */ 1935, /* END_TRY_S */ 1935, /* EQZ_I32 */ 1935, /* EQZ_I32_S */ 1937, /* EQZ_I64 */ 1937, /* EQZ_I64_S */ 1939, /* EQ_F16x8 */ 1939, /* EQ_F16x8_S */ 1942, /* EQ_F32 */ 1942, /* EQ_F32_S */ 1945, /* EQ_F32x4 */ 1945, /* EQ_F32x4_S */ 1948, /* EQ_F64 */ 1948, /* EQ_F64_S */ 1951, /* EQ_F64x2 */ 1951, /* EQ_F64x2_S */ 1954, /* EQ_I16x8 */ 1954, /* EQ_I16x8_S */ 1957, /* EQ_I32 */ 1957, /* EQ_I32_S */ 1960, /* EQ_I32x4 */ 1960, /* EQ_I32x4_S */ 1963, /* EQ_I64 */ 1963, /* EQ_I64_S */ 1966, /* EQ_I64x2 */ 1966, /* EQ_I64x2_S */ 1969, /* EQ_I8x16 */ 1969, /* EQ_I8x16_S */ 1972, /* EXTMUL_HIGH_S_I16x8 */ 1972, /* EXTMUL_HIGH_S_I16x8_S */ 1975, /* EXTMUL_HIGH_S_I32x4 */ 1975, /* EXTMUL_HIGH_S_I32x4_S */ 1978, /* EXTMUL_HIGH_S_I64x2 */ 1978, /* EXTMUL_HIGH_S_I64x2_S */ 1981, /* EXTMUL_HIGH_U_I16x8 */ 1981, /* EXTMUL_HIGH_U_I16x8_S */ 1984, /* EXTMUL_HIGH_U_I32x4 */ 1984, /* EXTMUL_HIGH_U_I32x4_S */ 1987, /* EXTMUL_HIGH_U_I64x2 */ 1987, /* EXTMUL_HIGH_U_I64x2_S */ 1990, /* EXTMUL_LOW_S_I16x8 */ 1990, /* EXTMUL_LOW_S_I16x8_S */ 1993, /* EXTMUL_LOW_S_I32x4 */ 1993, /* EXTMUL_LOW_S_I32x4_S */ 1996, /* EXTMUL_LOW_S_I64x2 */ 1996, /* EXTMUL_LOW_S_I64x2_S */ 1999, /* EXTMUL_LOW_U_I16x8 */ 1999, /* EXTMUL_LOW_U_I16x8_S */ 2002, /* EXTMUL_LOW_U_I32x4 */ 2002, /* EXTMUL_LOW_U_I32x4_S */ 2005, /* EXTMUL_LOW_U_I64x2 */ 2005, /* EXTMUL_LOW_U_I64x2_S */ 2008, /* EXTRACT_LANE_F16x8 */ 2008, /* EXTRACT_LANE_F16x8_S */ 2011, /* EXTRACT_LANE_F32x4 */ 2012, /* EXTRACT_LANE_F32x4_S */ 2015, /* EXTRACT_LANE_F64x2 */ 2016, /* EXTRACT_LANE_F64x2_S */ 2019, /* EXTRACT_LANE_I16x8_s */ 2020, /* EXTRACT_LANE_I16x8_s_S */ 2023, /* EXTRACT_LANE_I16x8_u */ 2024, /* EXTRACT_LANE_I16x8_u_S */ 2027, /* EXTRACT_LANE_I32x4 */ 2028, /* EXTRACT_LANE_I32x4_S */ 2031, /* EXTRACT_LANE_I64x2 */ 2032, /* EXTRACT_LANE_I64x2_S */ 2035, /* EXTRACT_LANE_I8x16_s */ 2036, /* EXTRACT_LANE_I8x16_s_S */ 2039, /* EXTRACT_LANE_I8x16_u */ 2040, /* EXTRACT_LANE_I8x16_u_S */ 2043, /* F32_CONVERT_S_I32 */ 2044, /* F32_CONVERT_S_I32_S */ 2046, /* F32_CONVERT_S_I64 */ 2046, /* F32_CONVERT_S_I64_S */ 2048, /* F32_CONVERT_U_I32 */ 2048, /* F32_CONVERT_U_I32_S */ 2050, /* F32_CONVERT_U_I64 */ 2050, /* F32_CONVERT_U_I64_S */ 2052, /* F32_DEMOTE_F64 */ 2052, /* F32_DEMOTE_F64_S */ 2054, /* F32_REINTERPRET_I32 */ 2054, /* F32_REINTERPRET_I32_S */ 2056, /* F64_CONVERT_S_I32 */ 2056, /* F64_CONVERT_S_I32_S */ 2058, /* F64_CONVERT_S_I64 */ 2058, /* F64_CONVERT_S_I64_S */ 2060, /* F64_CONVERT_U_I32 */ 2060, /* F64_CONVERT_U_I32_S */ 2062, /* F64_CONVERT_U_I64 */ 2062, /* F64_CONVERT_U_I64_S */ 2064, /* F64_PROMOTE_F32 */ 2064, /* F64_PROMOTE_F32_S */ 2066, /* F64_REINTERPRET_I64 */ 2066, /* F64_REINTERPRET_I64_S */ 2068, /* FALLTHROUGH_RETURN */ 2068, /* FALLTHROUGH_RETURN_S */ 2068, /* FLOOR_F16x8 */ 2068, /* FLOOR_F16x8_S */ 2070, /* FLOOR_F32 */ 2070, /* FLOOR_F32_S */ 2072, /* FLOOR_F32x4 */ 2072, /* FLOOR_F32x4_S */ 2074, /* FLOOR_F64 */ 2074, /* FLOOR_F64_S */ 2076, /* FLOOR_F64x2 */ 2076, /* FLOOR_F64x2_S */ 2078, /* FP_TO_SINT_I32_F32 */ 2078, /* FP_TO_SINT_I32_F32_S */ 2080, /* FP_TO_SINT_I32_F64 */ 2080, /* FP_TO_SINT_I32_F64_S */ 2082, /* FP_TO_SINT_I64_F32 */ 2082, /* FP_TO_SINT_I64_F32_S */ 2084, /* FP_TO_SINT_I64_F64 */ 2084, /* FP_TO_SINT_I64_F64_S */ 2086, /* FP_TO_UINT_I32_F32 */ 2086, /* FP_TO_UINT_I32_F32_S */ 2088, /* FP_TO_UINT_I32_F64 */ 2088, /* FP_TO_UINT_I32_F64_S */ 2090, /* FP_TO_UINT_I64_F32 */ 2090, /* FP_TO_UINT_I64_F32_S */ 2092, /* FP_TO_UINT_I64_F64 */ 2092, /* FP_TO_UINT_I64_F64_S */ 2094, /* GE_F16x8 */ 2094, /* GE_F16x8_S */ 2097, /* GE_F32 */ 2097, /* GE_F32_S */ 2100, /* GE_F32x4 */ 2100, /* GE_F32x4_S */ 2103, /* GE_F64 */ 2103, /* GE_F64_S */ 2106, /* GE_F64x2 */ 2106, /* GE_F64x2_S */ 2109, /* GE_S_I16x8 */ 2109, /* GE_S_I16x8_S */ 2112, /* GE_S_I32 */ 2112, /* GE_S_I32_S */ 2115, /* GE_S_I32x4 */ 2115, /* GE_S_I32x4_S */ 2118, /* GE_S_I64 */ 2118, /* GE_S_I64_S */ 2121, /* GE_S_I64x2 */ 2121, /* GE_S_I64x2_S */ 2124, /* GE_S_I8x16 */ 2124, /* GE_S_I8x16_S */ 2127, /* GE_U_I16x8 */ 2127, /* GE_U_I16x8_S */ 2130, /* GE_U_I32 */ 2130, /* GE_U_I32_S */ 2133, /* GE_U_I32x4 */ 2133, /* GE_U_I32x4_S */ 2136, /* GE_U_I64 */ 2136, /* GE_U_I64_S */ 2139, /* GE_U_I8x16 */ 2139, /* GE_U_I8x16_S */ 2142, /* GLOBAL_GET_EXNREF */ 2142, /* GLOBAL_GET_EXNREF_S */ 2144, /* GLOBAL_GET_EXTERNREF */ 2145, /* GLOBAL_GET_EXTERNREF_S */ 2147, /* GLOBAL_GET_F32 */ 2148, /* GLOBAL_GET_F32_S */ 2150, /* GLOBAL_GET_F64 */ 2151, /* GLOBAL_GET_F64_S */ 2153, /* GLOBAL_GET_FUNCREF */ 2154, /* GLOBAL_GET_FUNCREF_S */ 2156, /* GLOBAL_GET_I32 */ 2157, /* GLOBAL_GET_I32_S */ 2159, /* GLOBAL_GET_I64 */ 2160, /* GLOBAL_GET_I64_S */ 2162, /* GLOBAL_GET_V128 */ 2163, /* GLOBAL_GET_V128_S */ 2165, /* GLOBAL_SET_EXNREF */ 2166, /* GLOBAL_SET_EXNREF_S */ 2168, /* GLOBAL_SET_EXTERNREF */ 2169, /* GLOBAL_SET_EXTERNREF_S */ 2171, /* GLOBAL_SET_F32 */ 2172, /* GLOBAL_SET_F32_S */ 2174, /* GLOBAL_SET_F64 */ 2175, /* GLOBAL_SET_F64_S */ 2177, /* GLOBAL_SET_FUNCREF */ 2178, /* GLOBAL_SET_FUNCREF_S */ 2180, /* GLOBAL_SET_I32 */ 2181, /* GLOBAL_SET_I32_S */ 2183, /* GLOBAL_SET_I64 */ 2184, /* GLOBAL_SET_I64_S */ 2186, /* GLOBAL_SET_V128 */ 2187, /* GLOBAL_SET_V128_S */ 2189, /* GT_F16x8 */ 2190, /* GT_F16x8_S */ 2193, /* GT_F32 */ 2193, /* GT_F32_S */ 2196, /* GT_F32x4 */ 2196, /* GT_F32x4_S */ 2199, /* GT_F64 */ 2199, /* GT_F64_S */ 2202, /* GT_F64x2 */ 2202, /* GT_F64x2_S */ 2205, /* GT_S_I16x8 */ 2205, /* GT_S_I16x8_S */ 2208, /* GT_S_I32 */ 2208, /* GT_S_I32_S */ 2211, /* GT_S_I32x4 */ 2211, /* GT_S_I32x4_S */ 2214, /* GT_S_I64 */ 2214, /* GT_S_I64_S */ 2217, /* GT_S_I64x2 */ 2217, /* GT_S_I64x2_S */ 2220, /* GT_S_I8x16 */ 2220, /* GT_S_I8x16_S */ 2223, /* GT_U_I16x8 */ 2223, /* GT_U_I16x8_S */ 2226, /* GT_U_I32 */ 2226, /* GT_U_I32_S */ 2229, /* GT_U_I32x4 */ 2229, /* GT_U_I32x4_S */ 2232, /* GT_U_I64 */ 2232, /* GT_U_I64_S */ 2235, /* GT_U_I8x16 */ 2235, /* GT_U_I8x16_S */ 2238, /* I32_EXTEND16_S_I32 */ 2238, /* I32_EXTEND16_S_I32_S */ 2240, /* I32_EXTEND8_S_I32 */ 2240, /* I32_EXTEND8_S_I32_S */ 2242, /* I32_REINTERPRET_F32 */ 2242, /* I32_REINTERPRET_F32_S */ 2244, /* I32_TRUNC_S_F32 */ 2244, /* I32_TRUNC_S_F32_S */ 2246, /* I32_TRUNC_S_F64 */ 2246, /* I32_TRUNC_S_F64_S */ 2248, /* I32_TRUNC_S_SAT_F32 */ 2248, /* I32_TRUNC_S_SAT_F32_S */ 2250, /* I32_TRUNC_S_SAT_F64 */ 2250, /* I32_TRUNC_S_SAT_F64_S */ 2252, /* I32_TRUNC_U_F32 */ 2252, /* I32_TRUNC_U_F32_S */ 2254, /* I32_TRUNC_U_F64 */ 2254, /* I32_TRUNC_U_F64_S */ 2256, /* I32_TRUNC_U_SAT_F32 */ 2256, /* I32_TRUNC_U_SAT_F32_S */ 2258, /* I32_TRUNC_U_SAT_F64 */ 2258, /* I32_TRUNC_U_SAT_F64_S */ 2260, /* I32_WRAP_I64 */ 2260, /* I32_WRAP_I64_S */ 2262, /* I64_EXTEND16_S_I64 */ 2262, /* I64_EXTEND16_S_I64_S */ 2264, /* I64_EXTEND32_S_I64 */ 2264, /* I64_EXTEND32_S_I64_S */ 2266, /* I64_EXTEND8_S_I64 */ 2266, /* I64_EXTEND8_S_I64_S */ 2268, /* I64_EXTEND_S_I32 */ 2268, /* I64_EXTEND_S_I32_S */ 2270, /* I64_EXTEND_U_I32 */ 2270, /* I64_EXTEND_U_I32_S */ 2272, /* I64_REINTERPRET_F64 */ 2272, /* I64_REINTERPRET_F64_S */ 2274, /* I64_TRUNC_S_F32 */ 2274, /* I64_TRUNC_S_F32_S */ 2276, /* I64_TRUNC_S_F64 */ 2276, /* I64_TRUNC_S_F64_S */ 2278, /* I64_TRUNC_S_SAT_F32 */ 2278, /* I64_TRUNC_S_SAT_F32_S */ 2280, /* I64_TRUNC_S_SAT_F64 */ 2280, /* I64_TRUNC_S_SAT_F64_S */ 2282, /* I64_TRUNC_U_F32 */ 2282, /* I64_TRUNC_U_F32_S */ 2284, /* I64_TRUNC_U_F64 */ 2284, /* I64_TRUNC_U_F64_S */ 2286, /* I64_TRUNC_U_SAT_F32 */ 2286, /* I64_TRUNC_U_SAT_F32_S */ 2288, /* I64_TRUNC_U_SAT_F64 */ 2288, /* I64_TRUNC_U_SAT_F64_S */ 2290, /* IF */ 2290, /* IF_S */ 2292, /* LANESELECT_I16x8 */ 2293, /* LANESELECT_I16x8_S */ 2297, /* LANESELECT_I32x4 */ 2297, /* LANESELECT_I32x4_S */ 2301, /* LANESELECT_I64x2 */ 2301, /* LANESELECT_I64x2_S */ 2305, /* LANESELECT_I8x16 */ 2305, /* LANESELECT_I8x16_S */ 2309, /* LE_F16x8 */ 2309, /* LE_F16x8_S */ 2312, /* LE_F32 */ 2312, /* LE_F32_S */ 2315, /* LE_F32x4 */ 2315, /* LE_F32x4_S */ 2318, /* LE_F64 */ 2318, /* LE_F64_S */ 2321, /* LE_F64x2 */ 2321, /* LE_F64x2_S */ 2324, /* LE_S_I16x8 */ 2324, /* LE_S_I16x8_S */ 2327, /* LE_S_I32 */ 2327, /* LE_S_I32_S */ 2330, /* LE_S_I32x4 */ 2330, /* LE_S_I32x4_S */ 2333, /* LE_S_I64 */ 2333, /* LE_S_I64_S */ 2336, /* LE_S_I64x2 */ 2336, /* LE_S_I64x2_S */ 2339, /* LE_S_I8x16 */ 2339, /* LE_S_I8x16_S */ 2342, /* LE_U_I16x8 */ 2342, /* LE_U_I16x8_S */ 2345, /* LE_U_I32 */ 2345, /* LE_U_I32_S */ 2348, /* LE_U_I32x4 */ 2348, /* LE_U_I32x4_S */ 2351, /* LE_U_I64 */ 2351, /* LE_U_I64_S */ 2354, /* LE_U_I8x16 */ 2354, /* LE_U_I8x16_S */ 2357, /* LOAD16_SPLAT_A32 */ 2357, /* LOAD16_SPLAT_A32_S */ 2361, /* LOAD16_SPLAT_A64 */ 2363, /* LOAD16_SPLAT_A64_S */ 2367, /* LOAD16_S_I32_A32 */ 2369, /* LOAD16_S_I32_A32_S */ 2373, /* LOAD16_S_I32_A64 */ 2375, /* LOAD16_S_I32_A64_S */ 2379, /* LOAD16_S_I64_A32 */ 2381, /* LOAD16_S_I64_A32_S */ 2385, /* LOAD16_S_I64_A64 */ 2387, /* LOAD16_S_I64_A64_S */ 2391, /* LOAD16_U_I32_A32 */ 2393, /* LOAD16_U_I32_A32_S */ 2397, /* LOAD16_U_I32_A64 */ 2399, /* LOAD16_U_I32_A64_S */ 2403, /* LOAD16_U_I64_A32 */ 2405, /* LOAD16_U_I64_A32_S */ 2409, /* LOAD16_U_I64_A64 */ 2411, /* LOAD16_U_I64_A64_S */ 2415, /* LOAD32_SPLAT_A32 */ 2417, /* LOAD32_SPLAT_A32_S */ 2421, /* LOAD32_SPLAT_A64 */ 2423, /* LOAD32_SPLAT_A64_S */ 2427, /* LOAD32_S_I64_A32 */ 2429, /* LOAD32_S_I64_A32_S */ 2433, /* LOAD32_S_I64_A64 */ 2435, /* LOAD32_S_I64_A64_S */ 2439, /* LOAD32_U_I64_A32 */ 2441, /* LOAD32_U_I64_A32_S */ 2445, /* LOAD32_U_I64_A64 */ 2447, /* LOAD32_U_I64_A64_S */ 2451, /* LOAD64_SPLAT_A32 */ 2453, /* LOAD64_SPLAT_A32_S */ 2457, /* LOAD64_SPLAT_A64 */ 2459, /* LOAD64_SPLAT_A64_S */ 2463, /* LOAD8_SPLAT_A32 */ 2465, /* LOAD8_SPLAT_A32_S */ 2469, /* LOAD8_SPLAT_A64 */ 2471, /* LOAD8_SPLAT_A64_S */ 2475, /* LOAD8_S_I32_A32 */ 2477, /* LOAD8_S_I32_A32_S */ 2481, /* LOAD8_S_I32_A64 */ 2483, /* LOAD8_S_I32_A64_S */ 2487, /* LOAD8_S_I64_A32 */ 2489, /* LOAD8_S_I64_A32_S */ 2493, /* LOAD8_S_I64_A64 */ 2495, /* LOAD8_S_I64_A64_S */ 2499, /* LOAD8_U_I32_A32 */ 2501, /* LOAD8_U_I32_A32_S */ 2505, /* LOAD8_U_I32_A64 */ 2507, /* LOAD8_U_I32_A64_S */ 2511, /* LOAD8_U_I64_A32 */ 2513, /* LOAD8_U_I64_A32_S */ 2517, /* LOAD8_U_I64_A64 */ 2519, /* LOAD8_U_I64_A64_S */ 2523, /* LOAD_EXTEND_S_I16x8_A32 */ 2525, /* LOAD_EXTEND_S_I16x8_A32_S */ 2529, /* LOAD_EXTEND_S_I16x8_A64 */ 2531, /* LOAD_EXTEND_S_I16x8_A64_S */ 2535, /* LOAD_EXTEND_S_I32x4_A32 */ 2537, /* LOAD_EXTEND_S_I32x4_A32_S */ 2541, /* LOAD_EXTEND_S_I32x4_A64 */ 2543, /* LOAD_EXTEND_S_I32x4_A64_S */ 2547, /* LOAD_EXTEND_S_I64x2_A32 */ 2549, /* LOAD_EXTEND_S_I64x2_A32_S */ 2553, /* LOAD_EXTEND_S_I64x2_A64 */ 2555, /* LOAD_EXTEND_S_I64x2_A64_S */ 2559, /* LOAD_EXTEND_U_I16x8_A32 */ 2561, /* LOAD_EXTEND_U_I16x8_A32_S */ 2565, /* LOAD_EXTEND_U_I16x8_A64 */ 2567, /* LOAD_EXTEND_U_I16x8_A64_S */ 2571, /* LOAD_EXTEND_U_I32x4_A32 */ 2573, /* LOAD_EXTEND_U_I32x4_A32_S */ 2577, /* LOAD_EXTEND_U_I32x4_A64 */ 2579, /* LOAD_EXTEND_U_I32x4_A64_S */ 2583, /* LOAD_EXTEND_U_I64x2_A32 */ 2585, /* LOAD_EXTEND_U_I64x2_A32_S */ 2589, /* LOAD_EXTEND_U_I64x2_A64 */ 2591, /* LOAD_EXTEND_U_I64x2_A64_S */ 2595, /* LOAD_F16_F32_A32 */ 2597, /* LOAD_F16_F32_A32_S */ 2601, /* LOAD_F16_F32_A64 */ 2603, /* LOAD_F16_F32_A64_S */ 2607, /* LOAD_F32_A32 */ 2609, /* LOAD_F32_A32_S */ 2613, /* LOAD_F32_A64 */ 2615, /* LOAD_F32_A64_S */ 2619, /* LOAD_F64_A32 */ 2621, /* LOAD_F64_A32_S */ 2625, /* LOAD_F64_A64 */ 2627, /* LOAD_F64_A64_S */ 2631, /* LOAD_I32_A32 */ 2633, /* LOAD_I32_A32_S */ 2637, /* LOAD_I32_A64 */ 2639, /* LOAD_I32_A64_S */ 2643, /* LOAD_I64_A32 */ 2645, /* LOAD_I64_A32_S */ 2649, /* LOAD_I64_A64 */ 2651, /* LOAD_I64_A64_S */ 2655, /* LOAD_LANE_16_A32 */ 2657, /* LOAD_LANE_16_A32_S */ 2663, /* LOAD_LANE_16_A64 */ 2666, /* LOAD_LANE_16_A64_S */ 2672, /* LOAD_LANE_32_A32 */ 2675, /* LOAD_LANE_32_A32_S */ 2681, /* LOAD_LANE_32_A64 */ 2684, /* LOAD_LANE_32_A64_S */ 2690, /* LOAD_LANE_64_A32 */ 2693, /* LOAD_LANE_64_A32_S */ 2699, /* LOAD_LANE_64_A64 */ 2702, /* LOAD_LANE_64_A64_S */ 2708, /* LOAD_LANE_8_A32 */ 2711, /* LOAD_LANE_8_A32_S */ 2717, /* LOAD_LANE_8_A64 */ 2720, /* LOAD_LANE_8_A64_S */ 2726, /* LOAD_V128_A32 */ 2729, /* LOAD_V128_A32_S */ 2733, /* LOAD_V128_A64 */ 2735, /* LOAD_V128_A64_S */ 2739, /* LOAD_ZERO_32_A32 */ 2741, /* LOAD_ZERO_32_A32_S */ 2745, /* LOAD_ZERO_32_A64 */ 2747, /* LOAD_ZERO_32_A64_S */ 2751, /* LOAD_ZERO_64_A32 */ 2753, /* LOAD_ZERO_64_A32_S */ 2757, /* LOAD_ZERO_64_A64 */ 2759, /* LOAD_ZERO_64_A64_S */ 2763, /* LOCAL_GET_EXNREF */ 2765, /* LOCAL_GET_EXNREF_S */ 2767, /* LOCAL_GET_EXTERNREF */ 2768, /* LOCAL_GET_EXTERNREF_S */ 2770, /* LOCAL_GET_F32 */ 2771, /* LOCAL_GET_F32_S */ 2773, /* LOCAL_GET_F64 */ 2774, /* LOCAL_GET_F64_S */ 2776, /* LOCAL_GET_FUNCREF */ 2777, /* LOCAL_GET_FUNCREF_S */ 2779, /* LOCAL_GET_I32 */ 2780, /* LOCAL_GET_I32_S */ 2782, /* LOCAL_GET_I64 */ 2783, /* LOCAL_GET_I64_S */ 2785, /* LOCAL_GET_V128 */ 2786, /* LOCAL_GET_V128_S */ 2788, /* LOCAL_SET_EXNREF */ 2789, /* LOCAL_SET_EXNREF_S */ 2791, /* LOCAL_SET_EXTERNREF */ 2792, /* LOCAL_SET_EXTERNREF_S */ 2794, /* LOCAL_SET_F32 */ 2795, /* LOCAL_SET_F32_S */ 2797, /* LOCAL_SET_F64 */ 2798, /* LOCAL_SET_F64_S */ 2800, /* LOCAL_SET_FUNCREF */ 2801, /* LOCAL_SET_FUNCREF_S */ 2803, /* LOCAL_SET_I32 */ 2804, /* LOCAL_SET_I32_S */ 2806, /* LOCAL_SET_I64 */ 2807, /* LOCAL_SET_I64_S */ 2809, /* LOCAL_SET_V128 */ 2810, /* LOCAL_SET_V128_S */ 2812, /* LOCAL_TEE_EXNREF */ 2813, /* LOCAL_TEE_EXNREF_S */ 2816, /* LOCAL_TEE_EXTERNREF */ 2817, /* LOCAL_TEE_EXTERNREF_S */ 2820, /* LOCAL_TEE_F32 */ 2821, /* LOCAL_TEE_F32_S */ 2824, /* LOCAL_TEE_F64 */ 2825, /* LOCAL_TEE_F64_S */ 2828, /* LOCAL_TEE_FUNCREF */ 2829, /* LOCAL_TEE_FUNCREF_S */ 2832, /* LOCAL_TEE_I32 */ 2833, /* LOCAL_TEE_I32_S */ 2836, /* LOCAL_TEE_I64 */ 2837, /* LOCAL_TEE_I64_S */ 2840, /* LOCAL_TEE_V128 */ 2841, /* LOCAL_TEE_V128_S */ 2844, /* LOOP */ 2845, /* LOOP_S */ 2846, /* LT_F16x8 */ 2847, /* LT_F16x8_S */ 2850, /* LT_F32 */ 2850, /* LT_F32_S */ 2853, /* LT_F32x4 */ 2853, /* LT_F32x4_S */ 2856, /* LT_F64 */ 2856, /* LT_F64_S */ 2859, /* LT_F64x2 */ 2859, /* LT_F64x2_S */ 2862, /* LT_S_I16x8 */ 2862, /* LT_S_I16x8_S */ 2865, /* LT_S_I32 */ 2865, /* LT_S_I32_S */ 2868, /* LT_S_I32x4 */ 2868, /* LT_S_I32x4_S */ 2871, /* LT_S_I64 */ 2871, /* LT_S_I64_S */ 2874, /* LT_S_I64x2 */ 2874, /* LT_S_I64x2_S */ 2877, /* LT_S_I8x16 */ 2877, /* LT_S_I8x16_S */ 2880, /* LT_U_I16x8 */ 2880, /* LT_U_I16x8_S */ 2883, /* LT_U_I32 */ 2883, /* LT_U_I32_S */ 2886, /* LT_U_I32x4 */ 2886, /* LT_U_I32x4_S */ 2889, /* LT_U_I64 */ 2889, /* LT_U_I64_S */ 2892, /* LT_U_I8x16 */ 2892, /* LT_U_I8x16_S */ 2895, /* MADD_F16x8 */ 2895, /* MADD_F16x8_S */ 2899, /* MADD_F32x4 */ 2899, /* MADD_F32x4_S */ 2903, /* MADD_F64x2 */ 2903, /* MADD_F64x2_S */ 2907, /* MAX_F16x8 */ 2907, /* MAX_F16x8_S */ 2910, /* MAX_F32 */ 2910, /* MAX_F32_S */ 2913, /* MAX_F32x4 */ 2913, /* MAX_F32x4_S */ 2916, /* MAX_F64 */ 2916, /* MAX_F64_S */ 2919, /* MAX_F64x2 */ 2919, /* MAX_F64x2_S */ 2922, /* MAX_S_I16x8 */ 2922, /* MAX_S_I16x8_S */ 2925, /* MAX_S_I32x4 */ 2925, /* MAX_S_I32x4_S */ 2928, /* MAX_S_I8x16 */ 2928, /* MAX_S_I8x16_S */ 2931, /* MAX_U_I16x8 */ 2931, /* MAX_U_I16x8_S */ 2934, /* MAX_U_I32x4 */ 2934, /* MAX_U_I32x4_S */ 2937, /* MAX_U_I8x16 */ 2937, /* MAX_U_I8x16_S */ 2940, /* MEMORY_ATOMIC_NOTIFY_A32 */ 2940, /* MEMORY_ATOMIC_NOTIFY_A32_S */ 2945, /* MEMORY_ATOMIC_NOTIFY_A64 */ 2947, /* MEMORY_ATOMIC_NOTIFY_A64_S */ 2952, /* MEMORY_ATOMIC_WAIT32_A32 */ 2954, /* MEMORY_ATOMIC_WAIT32_A32_S */ 2960, /* MEMORY_ATOMIC_WAIT32_A64 */ 2962, /* MEMORY_ATOMIC_WAIT32_A64_S */ 2968, /* MEMORY_ATOMIC_WAIT64_A32 */ 2970, /* MEMORY_ATOMIC_WAIT64_A32_S */ 2976, /* MEMORY_ATOMIC_WAIT64_A64 */ 2978, /* MEMORY_ATOMIC_WAIT64_A64_S */ 2984, /* MIN_F16x8 */ 2986, /* MIN_F16x8_S */ 2989, /* MIN_F32 */ 2989, /* MIN_F32_S */ 2992, /* MIN_F32x4 */ 2992, /* MIN_F32x4_S */ 2995, /* MIN_F64 */ 2995, /* MIN_F64_S */ 2998, /* MIN_F64x2 */ 2998, /* MIN_F64x2_S */ 3001, /* MIN_S_I16x8 */ 3001, /* MIN_S_I16x8_S */ 3004, /* MIN_S_I32x4 */ 3004, /* MIN_S_I32x4_S */ 3007, /* MIN_S_I8x16 */ 3007, /* MIN_S_I8x16_S */ 3010, /* MIN_U_I16x8 */ 3010, /* MIN_U_I16x8_S */ 3013, /* MIN_U_I32x4 */ 3013, /* MIN_U_I32x4_S */ 3016, /* MIN_U_I8x16 */ 3016, /* MIN_U_I8x16_S */ 3019, /* MUL_F16x8 */ 3019, /* MUL_F16x8_S */ 3022, /* MUL_F32 */ 3022, /* MUL_F32_S */ 3025, /* MUL_F32x4 */ 3025, /* MUL_F32x4_S */ 3028, /* MUL_F64 */ 3028, /* MUL_F64_S */ 3031, /* MUL_F64x2 */ 3031, /* MUL_F64x2_S */ 3034, /* MUL_I16x8 */ 3034, /* MUL_I16x8_S */ 3037, /* MUL_I32 */ 3037, /* MUL_I32_S */ 3040, /* MUL_I32x4 */ 3040, /* MUL_I32x4_S */ 3043, /* MUL_I64 */ 3043, /* MUL_I64_S */ 3046, /* MUL_I64x2 */ 3046, /* MUL_I64x2_S */ 3049, /* NARROW_S_I16x8 */ 3049, /* NARROW_S_I16x8_S */ 3052, /* NARROW_S_I8x16 */ 3052, /* NARROW_S_I8x16_S */ 3055, /* NARROW_U_I16x8 */ 3055, /* NARROW_U_I16x8_S */ 3058, /* NARROW_U_I8x16 */ 3058, /* NARROW_U_I8x16_S */ 3061, /* NEAREST_F16x8 */ 3061, /* NEAREST_F16x8_S */ 3063, /* NEAREST_F32 */ 3063, /* NEAREST_F32_S */ 3065, /* NEAREST_F32x4 */ 3065, /* NEAREST_F32x4_S */ 3067, /* NEAREST_F64 */ 3067, /* NEAREST_F64_S */ 3069, /* NEAREST_F64x2 */ 3069, /* NEAREST_F64x2_S */ 3071, /* NEG_F16x8 */ 3071, /* NEG_F16x8_S */ 3073, /* NEG_F32 */ 3073, /* NEG_F32_S */ 3075, /* NEG_F32x4 */ 3075, /* NEG_F32x4_S */ 3077, /* NEG_F64 */ 3077, /* NEG_F64_S */ 3079, /* NEG_F64x2 */ 3079, /* NEG_F64x2_S */ 3081, /* NEG_I16x8 */ 3081, /* NEG_I16x8_S */ 3083, /* NEG_I32x4 */ 3083, /* NEG_I32x4_S */ 3085, /* NEG_I64x2 */ 3085, /* NEG_I64x2_S */ 3087, /* NEG_I8x16 */ 3087, /* NEG_I8x16_S */ 3089, /* NE_F16x8 */ 3089, /* NE_F16x8_S */ 3092, /* NE_F32 */ 3092, /* NE_F32_S */ 3095, /* NE_F32x4 */ 3095, /* NE_F32x4_S */ 3098, /* NE_F64 */ 3098, /* NE_F64_S */ 3101, /* NE_F64x2 */ 3101, /* NE_F64x2_S */ 3104, /* NE_I16x8 */ 3104, /* NE_I16x8_S */ 3107, /* NE_I32 */ 3107, /* NE_I32_S */ 3110, /* NE_I32x4 */ 3110, /* NE_I32x4_S */ 3113, /* NE_I64 */ 3113, /* NE_I64_S */ 3116, /* NE_I64x2 */ 3116, /* NE_I64x2_S */ 3119, /* NE_I8x16 */ 3119, /* NE_I8x16_S */ 3122, /* NMADD_F16x8 */ 3122, /* NMADD_F16x8_S */ 3126, /* NMADD_F32x4 */ 3126, /* NMADD_F32x4_S */ 3130, /* NMADD_F64x2 */ 3130, /* NMADD_F64x2_S */ 3134, /* NOP */ 3134, /* NOP_S */ 3134, /* NOT */ 3134, /* NOT_S */ 3136, /* OR */ 3136, /* OR_I32 */ 3139, /* OR_I32_S */ 3142, /* OR_I64 */ 3142, /* OR_I64_S */ 3145, /* OR_S */ 3145, /* PMAX_F16x8 */ 3145, /* PMAX_F16x8_S */ 3148, /* PMAX_F32x4 */ 3148, /* PMAX_F32x4_S */ 3151, /* PMAX_F64x2 */ 3151, /* PMAX_F64x2_S */ 3154, /* PMIN_F16x8 */ 3154, /* PMIN_F16x8_S */ 3157, /* PMIN_F32x4 */ 3157, /* PMIN_F32x4_S */ 3160, /* PMIN_F64x2 */ 3160, /* PMIN_F64x2_S */ 3163, /* POPCNT_I32 */ 3163, /* POPCNT_I32_S */ 3165, /* POPCNT_I64 */ 3165, /* POPCNT_I64_S */ 3167, /* POPCNT_I8x16 */ 3167, /* POPCNT_I8x16_S */ 3169, /* Q15MULR_SAT_S_I16x8 */ 3169, /* Q15MULR_SAT_S_I16x8_S */ 3172, /* REF_IS_NULL_EXNREF */ 3172, /* REF_IS_NULL_EXNREF_S */ 3174, /* REF_IS_NULL_EXTERNREF */ 3174, /* REF_IS_NULL_EXTERNREF_S */ 3176, /* REF_IS_NULL_FUNCREF */ 3176, /* REF_IS_NULL_FUNCREF_S */ 3178, /* REF_NULL_EXNREF */ 3178, /* REF_NULL_EXNREF_S */ 3179, /* REF_NULL_EXTERNREF */ 3179, /* REF_NULL_EXTERNREF_S */ 3180, /* REF_NULL_FUNCREF */ 3180, /* REF_NULL_FUNCREF_S */ 3181, /* RELAXED_DOT */ 3181, /* RELAXED_DOT_ADD */ 3184, /* RELAXED_DOT_ADD_S */ 3188, /* RELAXED_DOT_BFLOAT */ 3188, /* RELAXED_DOT_BFLOAT_S */ 3192, /* RELAXED_DOT_S */ 3192, /* RELAXED_Q15MULR_S_I16x8 */ 3192, /* RELAXED_Q15MULR_S_I16x8_S */ 3195, /* RELAXED_SWIZZLE */ 3195, /* RELAXED_SWIZZLE_S */ 3198, /* REM_S_I32 */ 3198, /* REM_S_I32_S */ 3201, /* REM_S_I64 */ 3201, /* REM_S_I64_S */ 3204, /* REM_U_I32 */ 3204, /* REM_U_I32_S */ 3207, /* REM_U_I64 */ 3207, /* REM_U_I64_S */ 3210, /* REPLACE_LANE_F16x8 */ 3210, /* REPLACE_LANE_F16x8_S */ 3214, /* REPLACE_LANE_F32x4 */ 3215, /* REPLACE_LANE_F32x4_S */ 3219, /* REPLACE_LANE_F64x2 */ 3220, /* REPLACE_LANE_F64x2_S */ 3224, /* REPLACE_LANE_I16x8 */ 3225, /* REPLACE_LANE_I16x8_S */ 3229, /* REPLACE_LANE_I32x4 */ 3230, /* REPLACE_LANE_I32x4_S */ 3234, /* REPLACE_LANE_I64x2 */ 3235, /* REPLACE_LANE_I64x2_S */ 3239, /* REPLACE_LANE_I8x16 */ 3240, /* REPLACE_LANE_I8x16_S */ 3244, /* RETHROW */ 3245, /* RETHROW_S */ 3246, /* RETURN */ 3247, /* RETURN_S */ 3247, /* RET_CALL */ 3247, /* RET_CALL_INDIRECT */ 3248, /* RET_CALL_INDIRECT_S */ 3250, /* RET_CALL_S */ 3252, /* ROTL_I32 */ 3253, /* ROTL_I32_S */ 3256, /* ROTL_I64 */ 3256, /* ROTL_I64_S */ 3259, /* ROTR_I32 */ 3259, /* ROTR_I32_S */ 3262, /* ROTR_I64 */ 3262, /* ROTR_I64_S */ 3265, /* SELECT_EXNREF */ 3265, /* SELECT_EXNREF_S */ 3269, /* SELECT_EXTERNREF */ 3269, /* SELECT_EXTERNREF_S */ 3273, /* SELECT_F32 */ 3273, /* SELECT_F32_S */ 3277, /* SELECT_F64 */ 3277, /* SELECT_F64_S */ 3281, /* SELECT_FUNCREF */ 3281, /* SELECT_FUNCREF_S */ 3285, /* SELECT_I32 */ 3285, /* SELECT_I32_S */ 3289, /* SELECT_I64 */ 3289, /* SELECT_I64_S */ 3293, /* SELECT_V128 */ 3293, /* SELECT_V128_S */ 3297, /* SHL_I16x8 */ 3297, /* SHL_I16x8_S */ 3300, /* SHL_I32 */ 3300, /* SHL_I32_S */ 3303, /* SHL_I32x4 */ 3303, /* SHL_I32x4_S */ 3306, /* SHL_I64 */ 3306, /* SHL_I64_S */ 3309, /* SHL_I64x2 */ 3309, /* SHL_I64x2_S */ 3312, /* SHL_I8x16 */ 3312, /* SHL_I8x16_S */ 3315, /* SHR_S_I16x8 */ 3315, /* SHR_S_I16x8_S */ 3318, /* SHR_S_I32 */ 3318, /* SHR_S_I32_S */ 3321, /* SHR_S_I32x4 */ 3321, /* SHR_S_I32x4_S */ 3324, /* SHR_S_I64 */ 3324, /* SHR_S_I64_S */ 3327, /* SHR_S_I64x2 */ 3327, /* SHR_S_I64x2_S */ 3330, /* SHR_S_I8x16 */ 3330, /* SHR_S_I8x16_S */ 3333, /* SHR_U_I16x8 */ 3333, /* SHR_U_I16x8_S */ 3336, /* SHR_U_I32 */ 3336, /* SHR_U_I32_S */ 3339, /* SHR_U_I32x4 */ 3339, /* SHR_U_I32x4_S */ 3342, /* SHR_U_I64 */ 3342, /* SHR_U_I64_S */ 3345, /* SHR_U_I64x2 */ 3345, /* SHR_U_I64x2_S */ 3348, /* SHR_U_I8x16 */ 3348, /* SHR_U_I8x16_S */ 3351, /* SHUFFLE */ 3351, /* SHUFFLE_S */ 3370, /* SIMD_RELAXED_FMAX_F32x4 */ 3386, /* SIMD_RELAXED_FMAX_F32x4_S */ 3389, /* SIMD_RELAXED_FMAX_F64x2 */ 3389, /* SIMD_RELAXED_FMAX_F64x2_S */ 3392, /* SIMD_RELAXED_FMIN_F32x4 */ 3392, /* SIMD_RELAXED_FMIN_F32x4_S */ 3395, /* SIMD_RELAXED_FMIN_F64x2 */ 3395, /* SIMD_RELAXED_FMIN_F64x2_S */ 3398, /* SPLAT_F16x8 */ 3398, /* SPLAT_F16x8_S */ 3400, /* SPLAT_F32x4 */ 3400, /* SPLAT_F32x4_S */ 3402, /* SPLAT_F64x2 */ 3402, /* SPLAT_F64x2_S */ 3404, /* SPLAT_I16x8 */ 3404, /* SPLAT_I16x8_S */ 3406, /* SPLAT_I32x4 */ 3406, /* SPLAT_I32x4_S */ 3408, /* SPLAT_I64x2 */ 3408, /* SPLAT_I64x2_S */ 3410, /* SPLAT_I8x16 */ 3410, /* SPLAT_I8x16_S */ 3412, /* SQRT_F16x8 */ 3412, /* SQRT_F16x8_S */ 3414, /* SQRT_F32 */ 3414, /* SQRT_F32_S */ 3416, /* SQRT_F32x4 */ 3416, /* SQRT_F32x4_S */ 3418, /* SQRT_F64 */ 3418, /* SQRT_F64_S */ 3420, /* SQRT_F64x2 */ 3420, /* SQRT_F64x2_S */ 3422, /* STORE16_I32_A32 */ 3422, /* STORE16_I32_A32_S */ 3426, /* STORE16_I32_A64 */ 3428, /* STORE16_I32_A64_S */ 3432, /* STORE16_I64_A32 */ 3434, /* STORE16_I64_A32_S */ 3438, /* STORE16_I64_A64 */ 3440, /* STORE16_I64_A64_S */ 3444, /* STORE32_I64_A32 */ 3446, /* STORE32_I64_A32_S */ 3450, /* STORE32_I64_A64 */ 3452, /* STORE32_I64_A64_S */ 3456, /* STORE8_I32_A32 */ 3458, /* STORE8_I32_A32_S */ 3462, /* STORE8_I32_A64 */ 3464, /* STORE8_I32_A64_S */ 3468, /* STORE8_I64_A32 */ 3470, /* STORE8_I64_A32_S */ 3474, /* STORE8_I64_A64 */ 3476, /* STORE8_I64_A64_S */ 3480, /* STORE_F16_F32_A32 */ 3482, /* STORE_F16_F32_A32_S */ 3486, /* STORE_F16_F32_A64 */ 3488, /* STORE_F16_F32_A64_S */ 3492, /* STORE_F32_A32 */ 3494, /* STORE_F32_A32_S */ 3498, /* STORE_F32_A64 */ 3500, /* STORE_F32_A64_S */ 3504, /* STORE_F64_A32 */ 3506, /* STORE_F64_A32_S */ 3510, /* STORE_F64_A64 */ 3512, /* STORE_F64_A64_S */ 3516, /* STORE_I32_A32 */ 3518, /* STORE_I32_A32_S */ 3522, /* STORE_I32_A64 */ 3524, /* STORE_I32_A64_S */ 3528, /* STORE_I64_A32 */ 3530, /* STORE_I64_A32_S */ 3534, /* STORE_I64_A64 */ 3536, /* STORE_I64_A64_S */ 3540, /* STORE_LANE_I16x8_A32 */ 3542, /* STORE_LANE_I16x8_A32_S */ 3547, /* STORE_LANE_I16x8_A64 */ 3550, /* STORE_LANE_I16x8_A64_S */ 3555, /* STORE_LANE_I32x4_A32 */ 3558, /* STORE_LANE_I32x4_A32_S */ 3563, /* STORE_LANE_I32x4_A64 */ 3566, /* STORE_LANE_I32x4_A64_S */ 3571, /* STORE_LANE_I64x2_A32 */ 3574, /* STORE_LANE_I64x2_A32_S */ 3579, /* STORE_LANE_I64x2_A64 */ 3582, /* STORE_LANE_I64x2_A64_S */ 3587, /* STORE_LANE_I8x16_A32 */ 3590, /* STORE_LANE_I8x16_A32_S */ 3595, /* STORE_LANE_I8x16_A64 */ 3598, /* STORE_LANE_I8x16_A64_S */ 3603, /* STORE_V128_A32 */ 3606, /* STORE_V128_A32_S */ 3610, /* STORE_V128_A64 */ 3612, /* STORE_V128_A64_S */ 3616, /* SUB_F16x8 */ 3618, /* SUB_F16x8_S */ 3621, /* SUB_F32 */ 3621, /* SUB_F32_S */ 3624, /* SUB_F32x4 */ 3624, /* SUB_F32x4_S */ 3627, /* SUB_F64 */ 3627, /* SUB_F64_S */ 3630, /* SUB_F64x2 */ 3630, /* SUB_F64x2_S */ 3633, /* SUB_I16x8 */ 3633, /* SUB_I16x8_S */ 3636, /* SUB_I32 */ 3636, /* SUB_I32_S */ 3639, /* SUB_I32x4 */ 3639, /* SUB_I32x4_S */ 3642, /* SUB_I64 */ 3642, /* SUB_I64_S */ 3645, /* SUB_I64x2 */ 3645, /* SUB_I64x2_S */ 3648, /* SUB_I8x16 */ 3648, /* SUB_I8x16_S */ 3651, /* SUB_SAT_S_I16x8 */ 3651, /* SUB_SAT_S_I16x8_S */ 3654, /* SUB_SAT_S_I8x16 */ 3654, /* SUB_SAT_S_I8x16_S */ 3657, /* SUB_SAT_U_I16x8 */ 3657, /* SUB_SAT_U_I16x8_S */ 3660, /* SUB_SAT_U_I8x16 */ 3660, /* SUB_SAT_U_I8x16_S */ 3663, /* SWIZZLE */ 3663, /* SWIZZLE_S */ 3666, /* TABLE_COPY */ 3666, /* TABLE_COPY_S */ 3671, /* TABLE_FILL_EXNREF */ 3673, /* TABLE_FILL_EXNREF_S */ 3677, /* TABLE_FILL_EXTERNREF */ 3678, /* TABLE_FILL_EXTERNREF_S */ 3682, /* TABLE_FILL_FUNCREF */ 3683, /* TABLE_FILL_FUNCREF_S */ 3687, /* TABLE_GET_EXNREF */ 3688, /* TABLE_GET_EXNREF_S */ 3691, /* TABLE_GET_EXTERNREF */ 3692, /* TABLE_GET_EXTERNREF_S */ 3695, /* TABLE_GET_FUNCREF */ 3696, /* TABLE_GET_FUNCREF_S */ 3699, /* TABLE_GROW_EXNREF */ 3700, /* TABLE_GROW_EXNREF_S */ 3704, /* TABLE_GROW_EXTERNREF */ 3705, /* TABLE_GROW_EXTERNREF_S */ 3709, /* TABLE_GROW_FUNCREF */ 3710, /* TABLE_GROW_FUNCREF_S */ 3714, /* TABLE_SET_EXNREF */ 3715, /* TABLE_SET_EXNREF_S */ 3718, /* TABLE_SET_EXTERNREF */ 3719, /* TABLE_SET_EXTERNREF_S */ 3722, /* TABLE_SET_FUNCREF */ 3723, /* TABLE_SET_FUNCREF_S */ 3726, /* TABLE_SIZE */ 3727, /* TABLE_SIZE_S */ 3729, /* TEE_EXNREF */ 3730, /* TEE_EXNREF_S */ 3733, /* TEE_EXTERNREF */ 3733, /* TEE_EXTERNREF_S */ 3736, /* TEE_F32 */ 3736, /* TEE_F32_S */ 3739, /* TEE_F64 */ 3739, /* TEE_F64_S */ 3742, /* TEE_FUNCREF */ 3742, /* TEE_FUNCREF_S */ 3745, /* TEE_I32 */ 3745, /* TEE_I32_S */ 3748, /* TEE_I64 */ 3748, /* TEE_I64_S */ 3751, /* TEE_V128 */ 3751, /* TEE_V128_S */ 3754, /* THROW */ 3754, /* THROW_S */ 3755, /* TRUNC_F16x8 */ 3756, /* TRUNC_F16x8_S */ 3758, /* TRUNC_F32 */ 3758, /* TRUNC_F32_S */ 3760, /* TRUNC_F32x4 */ 3760, /* TRUNC_F32x4_S */ 3762, /* TRUNC_F64 */ 3762, /* TRUNC_F64_S */ 3764, /* TRUNC_F64x2 */ 3764, /* TRUNC_F64x2_S */ 3766, /* TRY */ 3766, /* TRY_S */ 3767, /* UNREACHABLE */ 3768, /* UNREACHABLE_S */ 3768, /* XOR */ 3768, /* XOR_I32 */ 3771, /* XOR_I32_S */ 3774, /* XOR_I64 */ 3774, /* XOR_I64_S */ 3777, /* XOR_S */ 3777, /* anonymous_8166MEMORY_GROW_A32 */ 3777, /* anonymous_8166MEMORY_GROW_A32_S */ 3780, /* anonymous_8166MEMORY_SIZE_A32 */ 3781, /* anonymous_8166MEMORY_SIZE_A32_S */ 3783, /* anonymous_8167MEMORY_GROW_A64 */ 3784, /* anonymous_8167MEMORY_GROW_A64_S */ 3787, /* anonymous_8167MEMORY_SIZE_A64 */ 3788, /* anonymous_8167MEMORY_SIZE_A64_S */ 3790, /* anonymous_8883DATA_DROP */ 3791, /* anonymous_8883DATA_DROP_S */ 3792, /* anonymous_8883MEMORY_COPY_A32 */ 3793, /* anonymous_8883MEMORY_COPY_A32_S */ 3798, /* anonymous_8883MEMORY_FILL_A32 */ 3800, /* anonymous_8883MEMORY_FILL_A32_S */ 3804, /* anonymous_8883MEMORY_INIT_A32 */ 3805, /* anonymous_8883MEMORY_INIT_A32_S */ 3810, /* anonymous_8884DATA_DROP */ 3812, /* anonymous_8884DATA_DROP_S */ 3813, /* anonymous_8884MEMORY_COPY_A64 */ 3814, /* anonymous_8884MEMORY_COPY_A64_S */ 3819, /* anonymous_8884MEMORY_FILL_A64 */ 3821, /* anonymous_8884MEMORY_FILL_A64_S */ 3825, /* anonymous_8884MEMORY_INIT_A64 */ 3826, /* anonymous_8884MEMORY_INIT_A64_S */ 3831, /* convert_low_s_F64x2 */ 3833, /* convert_low_s_F64x2_S */ 3835, /* convert_low_u_F64x2 */ 3835, /* convert_low_u_F64x2_S */ 3837, /* demote_zero_F32x4 */ 3837, /* demote_zero_F32x4_S */ 3839, /* extend_high_s_I16x8 */ 3839, /* extend_high_s_I16x8_S */ 3841, /* extend_high_s_I32x4 */ 3841, /* extend_high_s_I32x4_S */ 3843, /* extend_high_s_I64x2 */ 3843, /* extend_high_s_I64x2_S */ 3845, /* extend_high_u_I16x8 */ 3845, /* extend_high_u_I16x8_S */ 3847, /* extend_high_u_I32x4 */ 3847, /* extend_high_u_I32x4_S */ 3849, /* extend_high_u_I64x2 */ 3849, /* extend_high_u_I64x2_S */ 3851, /* extend_low_s_I16x8 */ 3851, /* extend_low_s_I16x8_S */ 3853, /* extend_low_s_I32x4 */ 3853, /* extend_low_s_I32x4_S */ 3855, /* extend_low_s_I64x2 */ 3855, /* extend_low_s_I64x2_S */ 3857, /* extend_low_u_I16x8 */ 3857, /* extend_low_u_I16x8_S */ 3859, /* extend_low_u_I32x4 */ 3859, /* extend_low_u_I32x4_S */ 3861, /* extend_low_u_I64x2 */ 3861, /* extend_low_u_I64x2_S */ 3863, /* fp_to_sint_I16x8 */ 3863, /* fp_to_sint_I16x8_S */ 3865, /* fp_to_sint_I32x4 */ 3865, /* fp_to_sint_I32x4_S */ 3867, /* fp_to_uint_I16x8 */ 3867, /* fp_to_uint_I16x8_S */ 3869, /* fp_to_uint_I32x4 */ 3869, /* fp_to_uint_I32x4_S */ 3871, /* int_wasm_extadd_pairwise_signed_I16x8 */ 3871, /* int_wasm_extadd_pairwise_signed_I16x8_S */ 3873, /* int_wasm_extadd_pairwise_signed_I32x4 */ 3873, /* int_wasm_extadd_pairwise_signed_I32x4_S */ 3875, /* int_wasm_extadd_pairwise_unsigned_I16x8 */ 3875, /* int_wasm_extadd_pairwise_unsigned_I16x8_S */ 3877, /* int_wasm_extadd_pairwise_unsigned_I32x4 */ 3877, /* int_wasm_extadd_pairwise_unsigned_I32x4_S */ 3879, /* int_wasm_relaxed_trunc_signed_I32x4 */ 3879, /* int_wasm_relaxed_trunc_signed_I32x4_S */ 3881, /* int_wasm_relaxed_trunc_signed_zero_I32x4 */ 3881, /* int_wasm_relaxed_trunc_signed_zero_I32x4_S */ 3883, /* int_wasm_relaxed_trunc_unsigned_I32x4 */ 3883, /* int_wasm_relaxed_trunc_unsigned_I32x4_S */ 3885, /* int_wasm_relaxed_trunc_unsigned_zero_I32x4 */ 3885, /* int_wasm_relaxed_trunc_unsigned_zero_I32x4_S */ 3887, /* promote_low_F64x2 */ 3887, /* promote_low_F64x2_S */ 3889, /* sint_to_fp_F16x8 */ 3889, /* sint_to_fp_F16x8_S */ 3891, /* sint_to_fp_F32x4 */ 3891, /* sint_to_fp_F32x4_S */ 3893, /* trunc_sat_zero_s_I32x4 */ 3893, /* trunc_sat_zero_s_I32x4_S */ 3895, /* trunc_sat_zero_u_I32x4 */ 3895, /* trunc_sat_zero_u_I32x4_S */ 3897, /* uint_to_fp_F16x8 */ 3897, /* uint_to_fp_F16x8_S */ 3899, /* uint_to_fp_F32x4 */ 3899, /* uint_to_fp_F32x4_S */ 3901, }; using namespace OpTypes; static const int8_t OpcodeOperandTypes[] = { /* PHI */ -1, /* INLINEASM */ /* INLINEASM_BR */ /* CFI_INSTRUCTION */ i32imm, /* EH_LABEL */ i32imm, /* GC_LABEL */ i32imm, /* ANNOTATION_LABEL */ i32imm, /* KILL */ /* EXTRACT_SUBREG */ -1, -1, i32imm, /* INSERT_SUBREG */ -1, -1, -1, i32imm, /* IMPLICIT_DEF */ -1, /* SUBREG_TO_REG */ -1, -1, -1, i32imm, /* COPY_TO_REGCLASS */ -1, -1, i32imm, /* DBG_VALUE */ /* DBG_VALUE_LIST */ /* DBG_INSTR_REF */ /* DBG_PHI */ /* DBG_LABEL */ -1, /* REG_SEQUENCE */ -1, -1, /* COPY */ -1, -1, /* BUNDLE */ /* LIFETIME_START */ i32imm, /* LIFETIME_END */ i32imm, /* PSEUDO_PROBE */ i64imm, i64imm, i8imm, i32imm, /* ARITH_FENCE */ -1, -1, /* STACKMAP */ i64imm, i32imm, /* FENTRY_CALL */ /* PATCHPOINT */ -1, i64imm, i32imm, -1, i32imm, i32imm, /* LOAD_STACK_GUARD */ -1, /* PREALLOCATED_SETUP */ i32imm, /* PREALLOCATED_ARG */ -1, i32imm, i32imm, /* STATEPOINT */ /* LOCAL_ESCAPE */ -1, i32imm, /* FAULTING_OP */ -1, /* PATCHABLE_OP */ /* PATCHABLE_FUNCTION_ENTER */ /* PATCHABLE_RET */ /* PATCHABLE_FUNCTION_EXIT */ /* PATCHABLE_TAIL_CALL */ /* PATCHABLE_EVENT_CALL */ -1, -1, /* PATCHABLE_TYPED_EVENT_CALL */ -1, -1, -1, /* ICALL_BRANCH_FUNNEL */ /* FAKE_USE */ /* MEMBARRIER */ /* JUMP_TABLE_DEBUG_INFO */ i64imm, /* CONVERGENCECTRL_ENTRY */ -1, /* CONVERGENCECTRL_ANCHOR */ -1, /* CONVERGENCECTRL_LOOP */ -1, -1, /* CONVERGENCECTRL_GLUE */ -1, /* G_ASSERT_SEXT */ type0, type0, untyped_imm_0, /* G_ASSERT_ZEXT */ type0, type0, untyped_imm_0, /* G_ASSERT_ALIGN */ type0, type0, untyped_imm_0, /* G_ADD */ type0, type0, type0, /* G_SUB */ type0, type0, type0, /* G_MUL */ type0, type0, type0, /* G_SDIV */ type0, type0, type0, /* G_UDIV */ type0, type0, type0, /* G_SREM */ type0, type0, type0, /* G_UREM */ type0, type0, type0, /* G_SDIVREM */ type0, type0, type0, type0, /* G_UDIVREM */ type0, type0, type0, type0, /* G_AND */ type0, type0, type0, /* G_OR */ type0, type0, type0, /* G_XOR */ type0, type0, type0, /* G_IMPLICIT_DEF */ type0, /* G_PHI */ type0, /* G_FRAME_INDEX */ type0, -1, /* G_GLOBAL_VALUE */ type0, -1, /* G_PTRAUTH_GLOBAL_VALUE */ type0, -1, i32imm, type1, i64imm, /* G_CONSTANT_POOL */ type0, -1, /* G_EXTRACT */ type0, type1, untyped_imm_0, /* G_UNMERGE_VALUES */ type0, type1, /* G_INSERT */ type0, type0, type1, untyped_imm_0, /* G_MERGE_VALUES */ type0, type1, /* G_BUILD_VECTOR */ type0, type1, /* G_BUILD_VECTOR_TRUNC */ type0, type1, /* G_CONCAT_VECTORS */ type0, type1, /* G_PTRTOINT */ type0, type1, /* G_INTTOPTR */ type0, type1, /* G_BITCAST */ type0, type1, /* G_FREEZE */ type0, type0, /* G_CONSTANT_FOLD_BARRIER */ type0, type0, /* G_INTRINSIC_FPTRUNC_ROUND */ type0, type1, i32imm, /* G_INTRINSIC_TRUNC */ type0, type0, /* G_INTRINSIC_ROUND */ type0, type0, /* G_INTRINSIC_LRINT */ type0, type1, /* G_INTRINSIC_LLRINT */ type0, type1, /* G_INTRINSIC_ROUNDEVEN */ type0, type0, /* G_READCYCLECOUNTER */ type0, /* G_READSTEADYCOUNTER */ type0, /* G_LOAD */ type0, ptype1, /* G_SEXTLOAD */ type0, ptype1, /* G_ZEXTLOAD */ type0, ptype1, /* G_INDEXED_LOAD */ type0, ptype1, ptype1, type2, -1, /* G_INDEXED_SEXTLOAD */ type0, ptype1, ptype1, type2, -1, /* G_INDEXED_ZEXTLOAD */ type0, ptype1, ptype1, type2, -1, /* G_STORE */ type0, ptype1, /* G_INDEXED_STORE */ ptype0, type1, ptype0, ptype2, -1, /* G_ATOMIC_CMPXCHG_WITH_SUCCESS */ type0, type1, type2, type0, type0, /* G_ATOMIC_CMPXCHG */ type0, ptype1, type0, type0, /* G_ATOMICRMW_XCHG */ type0, ptype1, type0, /* G_ATOMICRMW_ADD */ type0, ptype1, type0, /* G_ATOMICRMW_SUB */ type0, ptype1, type0, /* G_ATOMICRMW_AND */ type0, ptype1, type0, /* G_ATOMICRMW_NAND */ type0, ptype1, type0, /* G_ATOMICRMW_OR */ type0, ptype1, type0, /* G_ATOMICRMW_XOR */ type0, ptype1, type0, /* G_ATOMICRMW_MAX */ type0, ptype1, type0, /* G_ATOMICRMW_MIN */ type0, ptype1, type0, /* G_ATOMICRMW_UMAX */ type0, ptype1, type0, /* G_ATOMICRMW_UMIN */ type0, ptype1, type0, /* G_ATOMICRMW_FADD */ type0, ptype1, type0, /* G_ATOMICRMW_FSUB */ type0, ptype1, type0, /* G_ATOMICRMW_FMAX */ type0, ptype1, type0, /* G_ATOMICRMW_FMIN */ type0, ptype1, type0, /* G_ATOMICRMW_UINC_WRAP */ type0, ptype1, type0, /* G_ATOMICRMW_UDEC_WRAP */ type0, ptype1, type0, /* G_FENCE */ i32imm, i32imm, /* G_PREFETCH */ ptype0, i32imm, i32imm, i32imm, /* G_BRCOND */ type0, -1, /* G_BRINDIRECT */ type0, /* G_INVOKE_REGION_START */ /* G_INTRINSIC */ -1, /* G_INTRINSIC_W_SIDE_EFFECTS */ -1, /* G_INTRINSIC_CONVERGENT */ -1, /* G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS */ -1, /* G_ANYEXT */ type0, type1, /* G_TRUNC */ type0, type1, /* G_CONSTANT */ type0, -1, /* G_FCONSTANT */ type0, -1, /* G_VASTART */ type0, /* G_VAARG */ type0, type1, -1, /* G_SEXT */ type0, type1, /* G_SEXT_INREG */ type0, type0, untyped_imm_0, /* G_ZEXT */ type0, type1, /* G_SHL */ type0, type0, type1, /* G_LSHR */ type0, type0, type1, /* G_ASHR */ type0, type0, type1, /* G_FSHL */ type0, type0, type0, type1, /* G_FSHR */ type0, type0, type0, type1, /* G_ROTR */ type0, type0, type1, /* G_ROTL */ type0, type0, type1, /* G_ICMP */ type0, -1, type1, type1, /* G_FCMP */ type0, -1, type1, type1, /* G_SCMP */ type0, type1, type1, /* G_UCMP */ type0, type1, type1, /* G_SELECT */ type0, type1, type0, type0, /* G_UADDO */ type0, type1, type0, type0, /* G_UADDE */ type0, type1, type0, type0, type1, /* G_USUBO */ type0, type1, type0, type0, /* G_USUBE */ type0, type1, type0, type0, type1, /* G_SADDO */ type0, type1, type0, type0, /* G_SADDE */ type0, type1, type0, type0, type1, /* G_SSUBO */ type0, type1, type0, type0, /* G_SSUBE */ type0, type1, type0, type0, type1, /* G_UMULO */ type0, type1, type0, type0, /* G_SMULO */ type0, type1, type0, type0, /* G_UMULH */ type0, type0, type0, /* G_SMULH */ type0, type0, type0, /* G_UADDSAT */ type0, type0, type0, /* G_SADDSAT */ type0, type0, type0, /* G_USUBSAT */ type0, type0, type0, /* G_SSUBSAT */ type0, type0, type0, /* G_USHLSAT */ type0, type0, type1, /* G_SSHLSAT */ type0, type0, type1, /* G_SMULFIX */ type0, type0, type0, untyped_imm_0, /* G_UMULFIX */ type0, type0, type0, untyped_imm_0, /* G_SMULFIXSAT */ type0, type0, type0, untyped_imm_0, /* G_UMULFIXSAT */ type0, type0, type0, untyped_imm_0, /* G_SDIVFIX */ type0, type0, type0, untyped_imm_0, /* G_UDIVFIX */ type0, type0, type0, untyped_imm_0, /* G_SDIVFIXSAT */ type0, type0, type0, untyped_imm_0, /* G_UDIVFIXSAT */ type0, type0, type0, untyped_imm_0, /* G_FADD */ type0, type0, type0, /* G_FSUB */ type0, type0, type0, /* G_FMUL */ type0, type0, type0, /* G_FMA */ type0, type0, type0, type0, /* G_FMAD */ type0, type0, type0, type0, /* G_FDIV */ type0, type0, type0, /* G_FREM */ type0, type0, type0, /* G_FPOW */ type0, type0, type0, /* G_FPOWI */ type0, type0, type1, /* G_FEXP */ type0, type0, /* G_FEXP2 */ type0, type0, /* G_FEXP10 */ type0, type0, /* G_FLOG */ type0, type0, /* G_FLOG2 */ type0, type0, /* G_FLOG10 */ type0, type0, /* G_FLDEXP */ type0, type0, type1, /* G_FFREXP */ type0, type1, type0, /* G_FNEG */ type0, type0, /* G_FPEXT */ type0, type1, /* G_FPTRUNC */ type0, type1, /* G_FPTOSI */ type0, type1, /* G_FPTOUI */ type0, type1, /* G_SITOFP */ type0, type1, /* G_UITOFP */ type0, type1, /* G_FABS */ type0, type0, /* G_FCOPYSIGN */ type0, type0, type1, /* G_IS_FPCLASS */ type0, type1, -1, /* G_FCANONICALIZE */ type0, type0, /* G_FMINNUM */ type0, type0, type0, /* G_FMAXNUM */ type0, type0, type0, /* G_FMINNUM_IEEE */ type0, type0, type0, /* G_FMAXNUM_IEEE */ type0, type0, type0, /* G_FMINIMUM */ type0, type0, type0, /* G_FMAXIMUM */ type0, type0, type0, /* G_GET_FPENV */ type0, /* G_SET_FPENV */ type0, /* G_RESET_FPENV */ /* G_GET_FPMODE */ type0, /* G_SET_FPMODE */ type0, /* G_RESET_FPMODE */ /* G_PTR_ADD */ ptype0, ptype0, type1, /* G_PTRMASK */ ptype0, ptype0, type1, /* G_SMIN */ type0, type0, type0, /* G_SMAX */ type0, type0, type0, /* G_UMIN */ type0, type0, type0, /* G_UMAX */ type0, type0, type0, /* G_ABS */ type0, type0, /* G_LROUND */ type0, type1, /* G_LLROUND */ type0, type1, /* G_BR */ -1, /* G_BRJT */ ptype0, -1, type1, /* G_VSCALE */ type0, -1, /* G_INSERT_SUBVECTOR */ type0, type0, type1, untyped_imm_0, /* G_EXTRACT_SUBVECTOR */ type0, type0, untyped_imm_0, /* G_INSERT_VECTOR_ELT */ type0, type0, type1, type2, /* G_EXTRACT_VECTOR_ELT */ type0, type1, type2, /* G_SHUFFLE_VECTOR */ type0, type1, type1, -1, /* G_SPLAT_VECTOR */ type0, type1, /* G_VECTOR_COMPRESS */ type0, type0, type1, type0, /* G_CTTZ */ type0, type1, /* G_CTTZ_ZERO_UNDEF */ type0, type1, /* G_CTLZ */ type0, type1, /* G_CTLZ_ZERO_UNDEF */ type0, type1, /* G_CTPOP */ type0, type1, /* G_BSWAP */ type0, type0, /* G_BITREVERSE */ type0, type0, /* G_FCEIL */ type0, type0, /* G_FCOS */ type0, type0, /* G_FSIN */ type0, type0, /* G_FTAN */ type0, type0, /* G_FACOS */ type0, type0, /* G_FASIN */ type0, type0, /* G_FATAN */ type0, type0, /* G_FCOSH */ type0, type0, /* G_FSINH */ type0, type0, /* G_FTANH */ type0, type0, /* G_FSQRT */ type0, type0, /* G_FFLOOR */ type0, type0, /* G_FRINT */ type0, type0, /* G_FNEARBYINT */ type0, type0, /* G_ADDRSPACE_CAST */ type0, type1, /* G_BLOCK_ADDR */ type0, -1, /* G_JUMP_TABLE */ type0, -1, /* G_DYN_STACKALLOC */ ptype0, type1, i32imm, /* G_STACKSAVE */ ptype0, /* G_STACKRESTORE */ ptype0, /* G_STRICT_FADD */ type0, type0, type0, /* G_STRICT_FSUB */ type0, type0, type0, /* G_STRICT_FMUL */ type0, type0, type0, /* G_STRICT_FDIV */ type0, type0, type0, /* G_STRICT_FREM */ type0, type0, type0, /* G_STRICT_FMA */ type0, type0, type0, type0, /* G_STRICT_FSQRT */ type0, type0, /* G_STRICT_FLDEXP */ type0, type0, type1, /* G_READ_REGISTER */ type0, -1, /* G_WRITE_REGISTER */ -1, type0, /* G_MEMCPY */ ptype0, ptype1, type2, untyped_imm_0, /* G_MEMCPY_INLINE */ ptype0, ptype1, type2, /* G_MEMMOVE */ ptype0, ptype1, type2, untyped_imm_0, /* G_MEMSET */ ptype0, type1, type2, untyped_imm_0, /* G_BZERO */ ptype0, type1, untyped_imm_0, /* G_TRAP */ /* G_DEBUGTRAP */ /* G_UBSANTRAP */ i8imm, /* G_VECREDUCE_SEQ_FADD */ type0, type1, type2, /* G_VECREDUCE_SEQ_FMUL */ type0, type1, type2, /* G_VECREDUCE_FADD */ type0, type1, /* G_VECREDUCE_FMUL */ type0, type1, /* G_VECREDUCE_FMAX */ type0, type1, /* G_VECREDUCE_FMIN */ type0, type1, /* G_VECREDUCE_FMAXIMUM */ type0, type1, /* G_VECREDUCE_FMINIMUM */ type0, type1, /* G_VECREDUCE_ADD */ type0, type1, /* G_VECREDUCE_MUL */ type0, type1, /* G_VECREDUCE_AND */ type0, type1, /* G_VECREDUCE_OR */ type0, type1, /* G_VECREDUCE_XOR */ type0, type1, /* G_VECREDUCE_SMAX */ type0, type1, /* G_VECREDUCE_SMIN */ type0, type1, /* G_VECREDUCE_UMAX */ type0, type1, /* G_VECREDUCE_UMIN */ type0, type1, /* G_SBFX */ type0, type0, type1, type1, /* G_UBFX */ type0, type0, type1, type1, /* CALL_PARAMS */ function32_op, /* CALL_PARAMS_S */ function32_op, /* CALL_RESULTS */ /* CALL_RESULTS_S */ /* CATCHRET */ bb_op, bb_op, /* CATCHRET_S */ bb_op, bb_op, /* CLEANUPRET */ /* CLEANUPRET_S */ /* COMPILER_FENCE */ /* COMPILER_FENCE_S */ /* RET_CALL_RESULTS */ /* RET_CALL_RESULTS_S */ /* ABS_F16x8 */ V128, V128, /* ABS_F16x8_S */ /* ABS_F32 */ F32, F32, /* ABS_F32_S */ /* ABS_F32x4 */ V128, V128, /* ABS_F32x4_S */ /* ABS_F64 */ F64, F64, /* ABS_F64_S */ /* ABS_F64x2 */ V128, V128, /* ABS_F64x2_S */ /* ABS_I16x8 */ V128, V128, /* ABS_I16x8_S */ /* ABS_I32x4 */ V128, V128, /* ABS_I32x4_S */ /* ABS_I64x2 */ V128, V128, /* ABS_I64x2_S */ /* ABS_I8x16 */ V128, V128, /* ABS_I8x16_S */ /* ADD_F16x8 */ V128, V128, V128, /* ADD_F16x8_S */ /* ADD_F32 */ F32, F32, F32, /* ADD_F32_S */ /* ADD_F32x4 */ V128, V128, V128, /* ADD_F32x4_S */ /* ADD_F64 */ F64, F64, F64, /* ADD_F64_S */ /* ADD_F64x2 */ V128, V128, V128, /* ADD_F64x2_S */ /* ADD_I16x8 */ V128, V128, V128, /* ADD_I16x8_S */ /* ADD_I32 */ I32, I32, I32, /* ADD_I32_S */ /* ADD_I32x4 */ V128, V128, V128, /* ADD_I32x4_S */ /* ADD_I64 */ I64, I64, I64, /* ADD_I64_S */ /* ADD_I64x2 */ V128, V128, V128, /* ADD_I64x2_S */ /* ADD_I8x16 */ V128, V128, V128, /* ADD_I8x16_S */ /* ADD_SAT_S_I16x8 */ V128, V128, V128, /* ADD_SAT_S_I16x8_S */ /* ADD_SAT_S_I8x16 */ V128, V128, V128, /* ADD_SAT_S_I8x16_S */ /* ADD_SAT_U_I16x8 */ V128, V128, V128, /* ADD_SAT_U_I16x8_S */ /* ADD_SAT_U_I8x16 */ V128, V128, V128, /* ADD_SAT_U_I8x16_S */ /* ADJCALLSTACKDOWN */ i32imm, i32imm, /* ADJCALLSTACKDOWN_S */ i32imm, i32imm, /* ADJCALLSTACKUP */ i32imm, i32imm, /* ADJCALLSTACKUP_S */ i32imm, i32imm, /* ALLTRUE_I16x8 */ I32, V128, /* ALLTRUE_I16x8_S */ /* ALLTRUE_I32x4 */ I32, V128, /* ALLTRUE_I32x4_S */ /* ALLTRUE_I64x2 */ I32, V128, /* ALLTRUE_I64x2_S */ /* ALLTRUE_I8x16 */ I32, V128, /* ALLTRUE_I8x16_S */ /* AND */ V128, V128, V128, /* ANDNOT */ V128, V128, V128, /* ANDNOT_S */ /* AND_I32 */ I32, I32, I32, /* AND_I32_S */ /* AND_I64 */ I64, I64, I64, /* AND_I64_S */ /* AND_S */ /* ANYTRUE */ I32, V128, /* ANYTRUE_S */ /* ARGUMENT_exnref */ EXNREF, i32imm, /* ARGUMENT_exnref_S */ i32imm, /* ARGUMENT_externref */ EXTERNREF, i32imm, /* ARGUMENT_externref_S */ i32imm, /* ARGUMENT_f32 */ F32, i32imm, /* ARGUMENT_f32_S */ i32imm, /* ARGUMENT_f64 */ F64, i32imm, /* ARGUMENT_f64_S */ i32imm, /* ARGUMENT_funcref */ FUNCREF, i32imm, /* ARGUMENT_funcref_S */ i32imm, /* ARGUMENT_i32 */ I32, i32imm, /* ARGUMENT_i32_S */ i32imm, /* ARGUMENT_i64 */ I64, i32imm, /* ARGUMENT_i64_S */ i32imm, /* ARGUMENT_v16i8 */ V128, i32imm, /* ARGUMENT_v16i8_S */ i32imm, /* ARGUMENT_v2f64 */ V128, i32imm, /* ARGUMENT_v2f64_S */ i32imm, /* ARGUMENT_v2i64 */ V128, i32imm, /* ARGUMENT_v2i64_S */ i32imm, /* ARGUMENT_v4f32 */ V128, i32imm, /* ARGUMENT_v4f32_S */ i32imm, /* ARGUMENT_v4i32 */ V128, i32imm, /* ARGUMENT_v4i32_S */ i32imm, /* ARGUMENT_v8f16 */ V128, i32imm, /* ARGUMENT_v8f16_S */ i32imm, /* ARGUMENT_v8i16 */ V128, i32imm, /* ARGUMENT_v8i16_S */ i32imm, /* ATOMIC_FENCE */ i8imm, /* ATOMIC_FENCE_S */ i8imm, /* ATOMIC_LOAD16_U_I32_A32 */ I32, P2Align, offset32_op, I32, /* ATOMIC_LOAD16_U_I32_A32_S */ P2Align, offset32_op, /* ATOMIC_LOAD16_U_I32_A64 */ I32, P2Align, offset64_op, I64, /* ATOMIC_LOAD16_U_I32_A64_S */ P2Align, offset64_op, /* ATOMIC_LOAD16_U_I64_A32 */ I64, P2Align, offset32_op, I32, /* ATOMIC_LOAD16_U_I64_A32_S */ P2Align, offset32_op, /* ATOMIC_LOAD16_U_I64_A64 */ I64, P2Align, offset64_op, I64, /* ATOMIC_LOAD16_U_I64_A64_S */ P2Align, offset64_op, /* ATOMIC_LOAD32_U_I64_A32 */ I64, P2Align, offset32_op, I32, /* ATOMIC_LOAD32_U_I64_A32_S */ P2Align, offset32_op, /* ATOMIC_LOAD32_U_I64_A64 */ I64, P2Align, offset64_op, I64, /* ATOMIC_LOAD32_U_I64_A64_S */ P2Align, offset64_op, /* ATOMIC_LOAD8_U_I32_A32 */ I32, P2Align, offset32_op, I32, /* ATOMIC_LOAD8_U_I32_A32_S */ P2Align, offset32_op, /* ATOMIC_LOAD8_U_I32_A64 */ I32, P2Align, offset64_op, I64, /* ATOMIC_LOAD8_U_I32_A64_S */ P2Align, offset64_op, /* ATOMIC_LOAD8_U_I64_A32 */ I64, P2Align, offset32_op, I32, /* ATOMIC_LOAD8_U_I64_A32_S */ P2Align, offset32_op, /* ATOMIC_LOAD8_U_I64_A64 */ I64, P2Align, offset64_op, I64, /* ATOMIC_LOAD8_U_I64_A64_S */ P2Align, offset64_op, /* ATOMIC_LOAD_I32_A32 */ I32, P2Align, offset32_op, I32, /* ATOMIC_LOAD_I32_A32_S */ P2Align, offset32_op, /* ATOMIC_LOAD_I32_A64 */ I32, P2Align, offset64_op, I64, /* ATOMIC_LOAD_I32_A64_S */ P2Align, offset64_op, /* ATOMIC_LOAD_I64_A32 */ I64, P2Align, offset32_op, I32, /* ATOMIC_LOAD_I64_A32_S */ P2Align, offset32_op, /* ATOMIC_LOAD_I64_A64 */ I64, P2Align, offset64_op, I64, /* ATOMIC_LOAD_I64_A64_S */ P2Align, offset64_op, /* ATOMIC_RMW16_U_ADD_I32_A32 */ I32, P2Align, offset32_op, I32, I32, /* ATOMIC_RMW16_U_ADD_I32_A32_S */ P2Align, offset32_op, /* ATOMIC_RMW16_U_ADD_I32_A64 */ I32, P2Align, offset64_op, I64, I32, /* ATOMIC_RMW16_U_ADD_I32_A64_S */ P2Align, offset64_op, /* ATOMIC_RMW16_U_ADD_I64_A32 */ I64, P2Align, offset32_op, I32, I64, /* ATOMIC_RMW16_U_ADD_I64_A32_S */ P2Align, offset32_op, /* ATOMIC_RMW16_U_ADD_I64_A64 */ I64, P2Align, offset64_op, I64, I64, /* ATOMIC_RMW16_U_ADD_I64_A64_S */ P2Align, offset64_op, /* ATOMIC_RMW16_U_AND_I32_A32 */ I32, P2Align, offset32_op, I32, I32, /* ATOMIC_RMW16_U_AND_I32_A32_S */ P2Align, offset32_op, /* ATOMIC_RMW16_U_AND_I32_A64 */ I32, P2Align, offset64_op, I64, I32, /* ATOMIC_RMW16_U_AND_I32_A64_S */ P2Align, offset64_op, /* ATOMIC_RMW16_U_AND_I64_A32 */ I64, P2Align, offset32_op, I32, I64, /* ATOMIC_RMW16_U_AND_I64_A32_S */ P2Align, offset32_op, /* ATOMIC_RMW16_U_AND_I64_A64 */ I64, P2Align, offset64_op, I64, I64, /* ATOMIC_RMW16_U_AND_I64_A64_S */ P2Align, offset64_op, /* ATOMIC_RMW16_U_CMPXCHG_I32_A32 */ I32, P2Align, offset32_op, I32, I32, I32, /* ATOMIC_RMW16_U_CMPXCHG_I32_A32_S */ P2Align, offset32_op, /* ATOMIC_RMW16_U_CMPXCHG_I32_A64 */ I32, P2Align, offset64_op, I64, I32, I32, /* ATOMIC_RMW16_U_CMPXCHG_I32_A64_S */ P2Align, offset64_op, /* ATOMIC_RMW16_U_CMPXCHG_I64_A32 */ I64, P2Align, offset32_op, I32, I64, I64, /* ATOMIC_RMW16_U_CMPXCHG_I64_A32_S */ P2Align, offset32_op, /* ATOMIC_RMW16_U_CMPXCHG_I64_A64 */ I64, P2Align, offset64_op, I64, I64, I64, /* ATOMIC_RMW16_U_CMPXCHG_I64_A64_S */ P2Align, offset64_op, /* ATOMIC_RMW16_U_OR_I32_A32 */ I32, P2Align, offset32_op, I32, I32, /* ATOMIC_RMW16_U_OR_I32_A32_S */ P2Align, offset32_op, /* ATOMIC_RMW16_U_OR_I32_A64 */ I32, P2Align, offset64_op, I64, I32, /* ATOMIC_RMW16_U_OR_I32_A64_S */ P2Align, offset64_op, /* ATOMIC_RMW16_U_OR_I64_A32 */ I64, P2Align, offset32_op, I32, I64, /* ATOMIC_RMW16_U_OR_I64_A32_S */ P2Align, offset32_op, /* ATOMIC_RMW16_U_OR_I64_A64 */ I64, P2Align, offset64_op, I64, I64, /* ATOMIC_RMW16_U_OR_I64_A64_S */ P2Align, offset64_op, /* ATOMIC_RMW16_U_SUB_I32_A32 */ I32, P2Align, offset32_op, I32, I32, /* ATOMIC_RMW16_U_SUB_I32_A32_S */ P2Align, offset32_op, /* ATOMIC_RMW16_U_SUB_I32_A64 */ I32, P2Align, offset64_op, I64, I32, /* ATOMIC_RMW16_U_SUB_I32_A64_S */ P2Align, offset64_op, /* ATOMIC_RMW16_U_SUB_I64_A32 */ I64, P2Align, offset32_op, I32, I64, /* ATOMIC_RMW16_U_SUB_I64_A32_S */ P2Align, offset32_op, /* ATOMIC_RMW16_U_SUB_I64_A64 */ I64, P2Align, offset64_op, I64, I64, /* ATOMIC_RMW16_U_SUB_I64_A64_S */ P2Align, offset64_op, /* ATOMIC_RMW16_U_XCHG_I32_A32 */ I32, P2Align, offset32_op, I32, I32, /* ATOMIC_RMW16_U_XCHG_I32_A32_S */ P2Align, offset32_op, /* ATOMIC_RMW16_U_XCHG_I32_A64 */ I32, P2Align, offset64_op, I64, I32, /* ATOMIC_RMW16_U_XCHG_I32_A64_S */ P2Align, offset64_op, /* ATOMIC_RMW16_U_XCHG_I64_A32 */ I64, P2Align, offset32_op, I32, I64, /* ATOMIC_RMW16_U_XCHG_I64_A32_S */ P2Align, offset32_op, /* ATOMIC_RMW16_U_XCHG_I64_A64 */ I64, P2Align, offset64_op, I64, I64, /* ATOMIC_RMW16_U_XCHG_I64_A64_S */ P2Align, offset64_op, /* ATOMIC_RMW16_U_XOR_I32_A32 */ I32, P2Align, offset32_op, I32, I32, /* ATOMIC_RMW16_U_XOR_I32_A32_S */ P2Align, offset32_op, /* ATOMIC_RMW16_U_XOR_I32_A64 */ I32, P2Align, offset64_op, I64, I32, /* ATOMIC_RMW16_U_XOR_I32_A64_S */ P2Align, offset64_op, /* ATOMIC_RMW16_U_XOR_I64_A32 */ I64, P2Align, offset32_op, I32, I64, /* ATOMIC_RMW16_U_XOR_I64_A32_S */ P2Align, offset32_op, /* ATOMIC_RMW16_U_XOR_I64_A64 */ I64, P2Align, offset64_op, I64, I64, /* ATOMIC_RMW16_U_XOR_I64_A64_S */ P2Align, offset64_op, /* ATOMIC_RMW32_U_ADD_I64_A32 */ I64, P2Align, offset32_op, I32, I64, /* ATOMIC_RMW32_U_ADD_I64_A32_S */ P2Align, offset32_op, /* ATOMIC_RMW32_U_ADD_I64_A64 */ I64, P2Align, offset64_op, I64, I64, /* ATOMIC_RMW32_U_ADD_I64_A64_S */ P2Align, offset64_op, /* ATOMIC_RMW32_U_AND_I64_A32 */ I64, P2Align, offset32_op, I32, I64, /* ATOMIC_RMW32_U_AND_I64_A32_S */ P2Align, offset32_op, /* ATOMIC_RMW32_U_AND_I64_A64 */ I64, P2Align, offset64_op, I64, I64, /* ATOMIC_RMW32_U_AND_I64_A64_S */ P2Align, offset64_op, /* ATOMIC_RMW32_U_CMPXCHG_I64_A32 */ I64, P2Align, offset32_op, I32, I64, I64, /* ATOMIC_RMW32_U_CMPXCHG_I64_A32_S */ P2Align, offset32_op, /* ATOMIC_RMW32_U_CMPXCHG_I64_A64 */ I64, P2Align, offset64_op, I64, I64, I64, /* ATOMIC_RMW32_U_CMPXCHG_I64_A64_S */ P2Align, offset64_op, /* ATOMIC_RMW32_U_OR_I64_A32 */ I64, P2Align, offset32_op, I32, I64, /* ATOMIC_RMW32_U_OR_I64_A32_S */ P2Align, offset32_op, /* ATOMIC_RMW32_U_OR_I64_A64 */ I64, P2Align, offset64_op, I64, I64, /* ATOMIC_RMW32_U_OR_I64_A64_S */ P2Align, offset64_op, /* ATOMIC_RMW32_U_SUB_I64_A32 */ I64, P2Align, offset32_op, I32, I64, /* ATOMIC_RMW32_U_SUB_I64_A32_S */ P2Align, offset32_op, /* ATOMIC_RMW32_U_SUB_I64_A64 */ I64, P2Align, offset64_op, I64, I64, /* ATOMIC_RMW32_U_SUB_I64_A64_S */ P2Align, offset64_op, /* ATOMIC_RMW32_U_XCHG_I64_A32 */ I64, P2Align, offset32_op, I32, I64, /* ATOMIC_RMW32_U_XCHG_I64_A32_S */ P2Align, offset32_op, /* ATOMIC_RMW32_U_XCHG_I64_A64 */ I64, P2Align, offset64_op, I64, I64, /* ATOMIC_RMW32_U_XCHG_I64_A64_S */ P2Align, offset64_op, /* ATOMIC_RMW32_U_XOR_I64_A32 */ I64, P2Align, offset32_op, I32, I64, /* ATOMIC_RMW32_U_XOR_I64_A32_S */ P2Align, offset32_op, /* ATOMIC_RMW32_U_XOR_I64_A64 */ I64, P2Align, offset64_op, I64, I64, /* ATOMIC_RMW32_U_XOR_I64_A64_S */ P2Align, offset64_op, /* ATOMIC_RMW8_U_ADD_I32_A32 */ I32, P2Align, offset32_op, I32, I32, /* ATOMIC_RMW8_U_ADD_I32_A32_S */ P2Align, offset32_op, /* ATOMIC_RMW8_U_ADD_I32_A64 */ I32, P2Align, offset64_op, I64, I32, /* ATOMIC_RMW8_U_ADD_I32_A64_S */ P2Align, offset64_op, /* ATOMIC_RMW8_U_ADD_I64_A32 */ I64, P2Align, offset32_op, I32, I64, /* ATOMIC_RMW8_U_ADD_I64_A32_S */ P2Align, offset32_op, /* ATOMIC_RMW8_U_ADD_I64_A64 */ I64, P2Align, offset64_op, I64, I64, /* ATOMIC_RMW8_U_ADD_I64_A64_S */ P2Align, offset64_op, /* ATOMIC_RMW8_U_AND_I32_A32 */ I32, P2Align, offset32_op, I32, I32, /* ATOMIC_RMW8_U_AND_I32_A32_S */ P2Align, offset32_op, /* ATOMIC_RMW8_U_AND_I32_A64 */ I32, P2Align, offset64_op, I64, I32, /* ATOMIC_RMW8_U_AND_I32_A64_S */ P2Align, offset64_op, /* ATOMIC_RMW8_U_AND_I64_A32 */ I64, P2Align, offset32_op, I32, I64, /* ATOMIC_RMW8_U_AND_I64_A32_S */ P2Align, offset32_op, /* ATOMIC_RMW8_U_AND_I64_A64 */ I64, P2Align, offset64_op, I64, I64, /* ATOMIC_RMW8_U_AND_I64_A64_S */ P2Align, offset64_op, /* ATOMIC_RMW8_U_CMPXCHG_I32_A32 */ I32, P2Align, offset32_op, I32, I32, I32, /* ATOMIC_RMW8_U_CMPXCHG_I32_A32_S */ P2Align, offset32_op, /* ATOMIC_RMW8_U_CMPXCHG_I32_A64 */ I32, P2Align, offset64_op, I64, I32, I32, /* ATOMIC_RMW8_U_CMPXCHG_I32_A64_S */ P2Align, offset64_op, /* ATOMIC_RMW8_U_CMPXCHG_I64_A32 */ I64, P2Align, offset32_op, I32, I64, I64, /* ATOMIC_RMW8_U_CMPXCHG_I64_A32_S */ P2Align, offset32_op, /* ATOMIC_RMW8_U_CMPXCHG_I64_A64 */ I64, P2Align, offset64_op, I64, I64, I64, /* ATOMIC_RMW8_U_CMPXCHG_I64_A64_S */ P2Align, offset64_op, /* ATOMIC_RMW8_U_OR_I32_A32 */ I32, P2Align, offset32_op, I32, I32, /* ATOMIC_RMW8_U_OR_I32_A32_S */ P2Align, offset32_op, /* ATOMIC_RMW8_U_OR_I32_A64 */ I32, P2Align, offset64_op, I64, I32, /* ATOMIC_RMW8_U_OR_I32_A64_S */ P2Align, offset64_op, /* ATOMIC_RMW8_U_OR_I64_A32 */ I64, P2Align, offset32_op, I32, I64, /* ATOMIC_RMW8_U_OR_I64_A32_S */ P2Align, offset32_op, /* ATOMIC_RMW8_U_OR_I64_A64 */ I64, P2Align, offset64_op, I64, I64, /* ATOMIC_RMW8_U_OR_I64_A64_S */ P2Align, offset64_op, /* ATOMIC_RMW8_U_SUB_I32_A32 */ I32, P2Align, offset32_op, I32, I32, /* ATOMIC_RMW8_U_SUB_I32_A32_S */ P2Align, offset32_op, /* ATOMIC_RMW8_U_SUB_I32_A64 */ I32, P2Align, offset64_op, I64, I32, /* ATOMIC_RMW8_U_SUB_I32_A64_S */ P2Align, offset64_op, /* ATOMIC_RMW8_U_SUB_I64_A32 */ I64, P2Align, offset32_op, I32, I64, /* ATOMIC_RMW8_U_SUB_I64_A32_S */ P2Align, offset32_op, /* ATOMIC_RMW8_U_SUB_I64_A64 */ I64, P2Align, offset64_op, I64, I64, /* ATOMIC_RMW8_U_SUB_I64_A64_S */ P2Align, offset64_op, /* ATOMIC_RMW8_U_XCHG_I32_A32 */ I32, P2Align, offset32_op, I32, I32, /* ATOMIC_RMW8_U_XCHG_I32_A32_S */ P2Align, offset32_op, /* ATOMIC_RMW8_U_XCHG_I32_A64 */ I32, P2Align, offset64_op, I64, I32, /* ATOMIC_RMW8_U_XCHG_I32_A64_S */ P2Align, offset64_op, /* ATOMIC_RMW8_U_XCHG_I64_A32 */ I64, P2Align, offset32_op, I32, I64, /* ATOMIC_RMW8_U_XCHG_I64_A32_S */ P2Align, offset32_op, /* ATOMIC_RMW8_U_XCHG_I64_A64 */ I64, P2Align, offset64_op, I64, I64, /* ATOMIC_RMW8_U_XCHG_I64_A64_S */ P2Align, offset64_op, /* ATOMIC_RMW8_U_XOR_I32_A32 */ I32, P2Align, offset32_op, I32, I32, /* ATOMIC_RMW8_U_XOR_I32_A32_S */ P2Align, offset32_op, /* ATOMIC_RMW8_U_XOR_I32_A64 */ I32, P2Align, offset64_op, I64, I32, /* ATOMIC_RMW8_U_XOR_I32_A64_S */ P2Align, offset64_op, /* ATOMIC_RMW8_U_XOR_I64_A32 */ I64, P2Align, offset32_op, I32, I64, /* ATOMIC_RMW8_U_XOR_I64_A32_S */ P2Align, offset32_op, /* ATOMIC_RMW8_U_XOR_I64_A64 */ I64, P2Align, offset64_op, I64, I64, /* ATOMIC_RMW8_U_XOR_I64_A64_S */ P2Align, offset64_op, /* ATOMIC_RMW_ADD_I32_A32 */ I32, P2Align, offset32_op, I32, I32, /* ATOMIC_RMW_ADD_I32_A32_S */ P2Align, offset32_op, /* ATOMIC_RMW_ADD_I32_A64 */ I32, P2Align, offset64_op, I64, I32, /* ATOMIC_RMW_ADD_I32_A64_S */ P2Align, offset64_op, /* ATOMIC_RMW_ADD_I64_A32 */ I64, P2Align, offset32_op, I32, I64, /* ATOMIC_RMW_ADD_I64_A32_S */ P2Align, offset32_op, /* ATOMIC_RMW_ADD_I64_A64 */ I64, P2Align, offset64_op, I64, I64, /* ATOMIC_RMW_ADD_I64_A64_S */ P2Align, offset64_op, /* ATOMIC_RMW_AND_I32_A32 */ I32, P2Align, offset32_op, I32, I32, /* ATOMIC_RMW_AND_I32_A32_S */ P2Align, offset32_op, /* ATOMIC_RMW_AND_I32_A64 */ I32, P2Align, offset64_op, I64, I32, /* ATOMIC_RMW_AND_I32_A64_S */ P2Align, offset64_op, /* ATOMIC_RMW_AND_I64_A32 */ I64, P2Align, offset32_op, I32, I64, /* ATOMIC_RMW_AND_I64_A32_S */ P2Align, offset32_op, /* ATOMIC_RMW_AND_I64_A64 */ I64, P2Align, offset64_op, I64, I64, /* ATOMIC_RMW_AND_I64_A64_S */ P2Align, offset64_op, /* ATOMIC_RMW_CMPXCHG_I32_A32 */ I32, P2Align, offset32_op, I32, I32, I32, /* ATOMIC_RMW_CMPXCHG_I32_A32_S */ P2Align, offset32_op, /* ATOMIC_RMW_CMPXCHG_I32_A64 */ I32, P2Align, offset64_op, I64, I32, I32, /* ATOMIC_RMW_CMPXCHG_I32_A64_S */ P2Align, offset64_op, /* ATOMIC_RMW_CMPXCHG_I64_A32 */ I64, P2Align, offset32_op, I32, I64, I64, /* ATOMIC_RMW_CMPXCHG_I64_A32_S */ P2Align, offset32_op, /* ATOMIC_RMW_CMPXCHG_I64_A64 */ I64, P2Align, offset64_op, I64, I64, I64, /* ATOMIC_RMW_CMPXCHG_I64_A64_S */ P2Align, offset64_op, /* ATOMIC_RMW_OR_I32_A32 */ I32, P2Align, offset32_op, I32, I32, /* ATOMIC_RMW_OR_I32_A32_S */ P2Align, offset32_op, /* ATOMIC_RMW_OR_I32_A64 */ I32, P2Align, offset64_op, I64, I32, /* ATOMIC_RMW_OR_I32_A64_S */ P2Align, offset64_op, /* ATOMIC_RMW_OR_I64_A32 */ I64, P2Align, offset32_op, I32, I64, /* ATOMIC_RMW_OR_I64_A32_S */ P2Align, offset32_op, /* ATOMIC_RMW_OR_I64_A64 */ I64, P2Align, offset64_op, I64, I64, /* ATOMIC_RMW_OR_I64_A64_S */ P2Align, offset64_op, /* ATOMIC_RMW_SUB_I32_A32 */ I32, P2Align, offset32_op, I32, I32, /* ATOMIC_RMW_SUB_I32_A32_S */ P2Align, offset32_op, /* ATOMIC_RMW_SUB_I32_A64 */ I32, P2Align, offset64_op, I64, I32, /* ATOMIC_RMW_SUB_I32_A64_S */ P2Align, offset64_op, /* ATOMIC_RMW_SUB_I64_A32 */ I64, P2Align, offset32_op, I32, I64, /* ATOMIC_RMW_SUB_I64_A32_S */ P2Align, offset32_op, /* ATOMIC_RMW_SUB_I64_A64 */ I64, P2Align, offset64_op, I64, I64, /* ATOMIC_RMW_SUB_I64_A64_S */ P2Align, offset64_op, /* ATOMIC_RMW_XCHG_I32_A32 */ I32, P2Align, offset32_op, I32, I32, /* ATOMIC_RMW_XCHG_I32_A32_S */ P2Align, offset32_op, /* ATOMIC_RMW_XCHG_I32_A64 */ I32, P2Align, offset64_op, I64, I32, /* ATOMIC_RMW_XCHG_I32_A64_S */ P2Align, offset64_op, /* ATOMIC_RMW_XCHG_I64_A32 */ I64, P2Align, offset32_op, I32, I64, /* ATOMIC_RMW_XCHG_I64_A32_S */ P2Align, offset32_op, /* ATOMIC_RMW_XCHG_I64_A64 */ I64, P2Align, offset64_op, I64, I64, /* ATOMIC_RMW_XCHG_I64_A64_S */ P2Align, offset64_op, /* ATOMIC_RMW_XOR_I32_A32 */ I32, P2Align, offset32_op, I32, I32, /* ATOMIC_RMW_XOR_I32_A32_S */ P2Align, offset32_op, /* ATOMIC_RMW_XOR_I32_A64 */ I32, P2Align, offset64_op, I64, I32, /* ATOMIC_RMW_XOR_I32_A64_S */ P2Align, offset64_op, /* ATOMIC_RMW_XOR_I64_A32 */ I64, P2Align, offset32_op, I32, I64, /* ATOMIC_RMW_XOR_I64_A32_S */ P2Align, offset32_op, /* ATOMIC_RMW_XOR_I64_A64 */ I64, P2Align, offset64_op, I64, I64, /* ATOMIC_RMW_XOR_I64_A64_S */ P2Align, offset64_op, /* ATOMIC_STORE16_I32_A32 */ P2Align, offset32_op, I32, I32, /* ATOMIC_STORE16_I32_A32_S */ P2Align, offset32_op, /* ATOMIC_STORE16_I32_A64 */ P2Align, offset64_op, I64, I32, /* ATOMIC_STORE16_I32_A64_S */ P2Align, offset64_op, /* ATOMIC_STORE16_I64_A32 */ P2Align, offset32_op, I32, I64, /* ATOMIC_STORE16_I64_A32_S */ P2Align, offset32_op, /* ATOMIC_STORE16_I64_A64 */ P2Align, offset64_op, I64, I64, /* ATOMIC_STORE16_I64_A64_S */ P2Align, offset64_op, /* ATOMIC_STORE32_I64_A32 */ P2Align, offset32_op, I32, I64, /* ATOMIC_STORE32_I64_A32_S */ P2Align, offset32_op, /* ATOMIC_STORE32_I64_A64 */ P2Align, offset64_op, I64, I64, /* ATOMIC_STORE32_I64_A64_S */ P2Align, offset64_op, /* ATOMIC_STORE8_I32_A32 */ P2Align, offset32_op, I32, I32, /* ATOMIC_STORE8_I32_A32_S */ P2Align, offset32_op, /* ATOMIC_STORE8_I32_A64 */ P2Align, offset64_op, I64, I32, /* ATOMIC_STORE8_I32_A64_S */ P2Align, offset64_op, /* ATOMIC_STORE8_I64_A32 */ P2Align, offset32_op, I32, I64, /* ATOMIC_STORE8_I64_A32_S */ P2Align, offset32_op, /* ATOMIC_STORE8_I64_A64 */ P2Align, offset64_op, I64, I64, /* ATOMIC_STORE8_I64_A64_S */ P2Align, offset64_op, /* ATOMIC_STORE_I32_A32 */ P2Align, offset32_op, I32, I32, /* ATOMIC_STORE_I32_A32_S */ P2Align, offset32_op, /* ATOMIC_STORE_I32_A64 */ P2Align, offset64_op, I64, I32, /* ATOMIC_STORE_I32_A64_S */ P2Align, offset64_op, /* ATOMIC_STORE_I64_A32 */ P2Align, offset32_op, I32, I64, /* ATOMIC_STORE_I64_A32_S */ P2Align, offset32_op, /* ATOMIC_STORE_I64_A64 */ P2Align, offset64_op, I64, I64, /* ATOMIC_STORE_I64_A64_S */ P2Align, offset64_op, /* AVGR_U_I16x8 */ V128, V128, V128, /* AVGR_U_I16x8_S */ /* AVGR_U_I8x16 */ V128, V128, V128, /* AVGR_U_I8x16_S */ /* BITMASK_I16x8 */ I32, V128, /* BITMASK_I16x8_S */ /* BITMASK_I32x4 */ I32, V128, /* BITMASK_I32x4_S */ /* BITMASK_I64x2 */ I32, V128, /* BITMASK_I64x2_S */ /* BITMASK_I8x16 */ I32, V128, /* BITMASK_I8x16_S */ /* BITSELECT */ V128, V128, V128, V128, /* BITSELECT_S */ /* BLOCK */ Signature, /* BLOCK_S */ Signature, /* BR */ bb_op, /* BR_IF */ bb_op, I32, /* BR_IF_S */ bb_op, /* BR_S */ bb_op, /* BR_TABLE_I32 */ I32, /* BR_TABLE_I32_S */ brlist, /* BR_TABLE_I64 */ I64, /* BR_TABLE_I64_S */ brlist, /* BR_UNLESS */ bb_op, I32, /* BR_UNLESS_S */ bb_op, /* CALL */ function32_op, /* CALL_INDIRECT */ TypeIndex, table32_op, /* CALL_INDIRECT_S */ TypeIndex, table32_op, /* CALL_S */ function32_op, /* CATCH */ tag_op, /* CATCH_ALL */ /* CATCH_ALL_S */ /* CATCH_S */ tag_op, /* CEIL_F16x8 */ V128, V128, /* CEIL_F16x8_S */ /* CEIL_F32 */ F32, F32, /* CEIL_F32_S */ /* CEIL_F32x4 */ V128, V128, /* CEIL_F32x4_S */ /* CEIL_F64 */ F64, F64, /* CEIL_F64_S */ /* CEIL_F64x2 */ V128, V128, /* CEIL_F64x2_S */ /* CLZ_I32 */ I32, I32, /* CLZ_I32_S */ /* CLZ_I64 */ I64, I64, /* CLZ_I64_S */ /* CONST_F32 */ F32, f32imm_op, /* CONST_F32_S */ f32imm_op, /* CONST_F64 */ F64, f64imm_op, /* CONST_F64_S */ f64imm_op, /* CONST_I32 */ I32, i32imm_op, /* CONST_I32_S */ i32imm_op, /* CONST_I64 */ I64, i64imm_op, /* CONST_I64_S */ i64imm_op, /* CONST_V128_F32x4 */ V128, f32imm_op, f32imm_op, f32imm_op, f32imm_op, /* CONST_V128_F32x4_S */ f32imm_op, f32imm_op, f32imm_op, f32imm_op, /* CONST_V128_F64x2 */ V128, f64imm_op, f64imm_op, /* CONST_V128_F64x2_S */ f64imm_op, f64imm_op, /* CONST_V128_I16x8 */ V128, vec_i16imm_op, vec_i16imm_op, vec_i16imm_op, vec_i16imm_op, vec_i16imm_op, vec_i16imm_op, vec_i16imm_op, vec_i16imm_op, /* CONST_V128_I16x8_S */ vec_i16imm_op, vec_i16imm_op, vec_i16imm_op, vec_i16imm_op, vec_i16imm_op, vec_i16imm_op, vec_i16imm_op, vec_i16imm_op, /* CONST_V128_I32x4 */ V128, vec_i32imm_op, vec_i32imm_op, vec_i32imm_op, vec_i32imm_op, /* CONST_V128_I32x4_S */ vec_i32imm_op, vec_i32imm_op, vec_i32imm_op, vec_i32imm_op, /* CONST_V128_I64x2 */ V128, vec_i64imm_op, vec_i64imm_op, /* CONST_V128_I64x2_S */ vec_i64imm_op, vec_i64imm_op, /* CONST_V128_I8x16 */ V128, vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, /* CONST_V128_I8x16_S */ vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, /* COPYSIGN_F32 */ F32, F32, F32, /* COPYSIGN_F32_S */ /* COPYSIGN_F64 */ F64, F64, F64, /* COPYSIGN_F64_S */ /* COPY_EXNREF */ EXNREF, EXNREF, /* COPY_EXNREF_S */ /* COPY_EXTERNREF */ EXTERNREF, EXTERNREF, /* COPY_EXTERNREF_S */ /* COPY_F32 */ F32, F32, /* COPY_F32_S */ /* COPY_F64 */ F64, F64, /* COPY_F64_S */ /* COPY_FUNCREF */ FUNCREF, FUNCREF, /* COPY_FUNCREF_S */ /* COPY_I32 */ I32, I32, /* COPY_I32_S */ /* COPY_I64 */ I64, I64, /* COPY_I64_S */ /* COPY_V128 */ V128, V128, /* COPY_V128_S */ /* CTZ_I32 */ I32, I32, /* CTZ_I32_S */ /* CTZ_I64 */ I64, I64, /* CTZ_I64_S */ /* DEBUG_UNREACHABLE */ /* DEBUG_UNREACHABLE_S */ /* DELEGATE */ bb_op, /* DELEGATE_S */ bb_op, /* DIV_F16x8 */ V128, V128, V128, /* DIV_F16x8_S */ /* DIV_F32 */ F32, F32, F32, /* DIV_F32_S */ /* DIV_F32x4 */ V128, V128, V128, /* DIV_F32x4_S */ /* DIV_F64 */ F64, F64, F64, /* DIV_F64_S */ /* DIV_F64x2 */ V128, V128, V128, /* DIV_F64x2_S */ /* DIV_S_I32 */ I32, I32, I32, /* DIV_S_I32_S */ /* DIV_S_I64 */ I64, I64, I64, /* DIV_S_I64_S */ /* DIV_U_I32 */ I32, I32, I32, /* DIV_U_I32_S */ /* DIV_U_I64 */ I64, I64, I64, /* DIV_U_I64_S */ /* DOT */ V128, V128, V128, /* DOT_S */ /* DROP_EXNREF */ EXNREF, /* DROP_EXNREF_S */ /* DROP_EXTERNREF */ EXTERNREF, /* DROP_EXTERNREF_S */ /* DROP_F32 */ F32, /* DROP_F32_S */ /* DROP_F64 */ F64, /* DROP_F64_S */ /* DROP_FUNCREF */ FUNCREF, /* DROP_FUNCREF_S */ /* DROP_I32 */ I32, /* DROP_I32_S */ /* DROP_I64 */ I64, /* DROP_I64_S */ /* DROP_V128 */ V128, /* DROP_V128_S */ /* ELSE */ /* ELSE_S */ /* END */ /* END_BLOCK */ /* END_BLOCK_S */ /* END_FUNCTION */ /* END_FUNCTION_S */ /* END_IF */ /* END_IF_S */ /* END_LOOP */ /* END_LOOP_S */ /* END_S */ /* END_TRY */ /* END_TRY_S */ /* EQZ_I32 */ I32, I32, /* EQZ_I32_S */ /* EQZ_I64 */ I32, I64, /* EQZ_I64_S */ /* EQ_F16x8 */ V128, V128, V128, /* EQ_F16x8_S */ /* EQ_F32 */ I32, F32, F32, /* EQ_F32_S */ /* EQ_F32x4 */ V128, V128, V128, /* EQ_F32x4_S */ /* EQ_F64 */ I32, F64, F64, /* EQ_F64_S */ /* EQ_F64x2 */ V128, V128, V128, /* EQ_F64x2_S */ /* EQ_I16x8 */ V128, V128, V128, /* EQ_I16x8_S */ /* EQ_I32 */ I32, I32, I32, /* EQ_I32_S */ /* EQ_I32x4 */ V128, V128, V128, /* EQ_I32x4_S */ /* EQ_I64 */ I32, I64, I64, /* EQ_I64_S */ /* EQ_I64x2 */ V128, V128, V128, /* EQ_I64x2_S */ /* EQ_I8x16 */ V128, V128, V128, /* EQ_I8x16_S */ /* EXTMUL_HIGH_S_I16x8 */ V128, V128, V128, /* EXTMUL_HIGH_S_I16x8_S */ /* EXTMUL_HIGH_S_I32x4 */ V128, V128, V128, /* EXTMUL_HIGH_S_I32x4_S */ /* EXTMUL_HIGH_S_I64x2 */ V128, V128, V128, /* EXTMUL_HIGH_S_I64x2_S */ /* EXTMUL_HIGH_U_I16x8 */ V128, V128, V128, /* EXTMUL_HIGH_U_I16x8_S */ /* EXTMUL_HIGH_U_I32x4 */ V128, V128, V128, /* EXTMUL_HIGH_U_I32x4_S */ /* EXTMUL_HIGH_U_I64x2 */ V128, V128, V128, /* EXTMUL_HIGH_U_I64x2_S */ /* EXTMUL_LOW_S_I16x8 */ V128, V128, V128, /* EXTMUL_LOW_S_I16x8_S */ /* EXTMUL_LOW_S_I32x4 */ V128, V128, V128, /* EXTMUL_LOW_S_I32x4_S */ /* EXTMUL_LOW_S_I64x2 */ V128, V128, V128, /* EXTMUL_LOW_S_I64x2_S */ /* EXTMUL_LOW_U_I16x8 */ V128, V128, V128, /* EXTMUL_LOW_U_I16x8_S */ /* EXTMUL_LOW_U_I32x4 */ V128, V128, V128, /* EXTMUL_LOW_U_I32x4_S */ /* EXTMUL_LOW_U_I64x2 */ V128, V128, V128, /* EXTMUL_LOW_U_I64x2_S */ /* EXTRACT_LANE_F16x8 */ F32, V128, vec_i8imm_op, /* EXTRACT_LANE_F16x8_S */ vec_i8imm_op, /* EXTRACT_LANE_F32x4 */ F32, V128, vec_i8imm_op, /* EXTRACT_LANE_F32x4_S */ vec_i8imm_op, /* EXTRACT_LANE_F64x2 */ F64, V128, vec_i8imm_op, /* EXTRACT_LANE_F64x2_S */ vec_i8imm_op, /* EXTRACT_LANE_I16x8_s */ I32, V128, vec_i8imm_op, /* EXTRACT_LANE_I16x8_s_S */ vec_i8imm_op, /* EXTRACT_LANE_I16x8_u */ I32, V128, vec_i8imm_op, /* EXTRACT_LANE_I16x8_u_S */ vec_i8imm_op, /* EXTRACT_LANE_I32x4 */ I32, V128, vec_i8imm_op, /* EXTRACT_LANE_I32x4_S */ vec_i8imm_op, /* EXTRACT_LANE_I64x2 */ I64, V128, vec_i8imm_op, /* EXTRACT_LANE_I64x2_S */ vec_i8imm_op, /* EXTRACT_LANE_I8x16_s */ I32, V128, vec_i8imm_op, /* EXTRACT_LANE_I8x16_s_S */ vec_i8imm_op, /* EXTRACT_LANE_I8x16_u */ I32, V128, vec_i8imm_op, /* EXTRACT_LANE_I8x16_u_S */ vec_i8imm_op, /* F32_CONVERT_S_I32 */ F32, I32, /* F32_CONVERT_S_I32_S */ /* F32_CONVERT_S_I64 */ F32, I64, /* F32_CONVERT_S_I64_S */ /* F32_CONVERT_U_I32 */ F32, I32, /* F32_CONVERT_U_I32_S */ /* F32_CONVERT_U_I64 */ F32, I64, /* F32_CONVERT_U_I64_S */ /* F32_DEMOTE_F64 */ F32, F64, /* F32_DEMOTE_F64_S */ /* F32_REINTERPRET_I32 */ F32, I32, /* F32_REINTERPRET_I32_S */ /* F64_CONVERT_S_I32 */ F64, I32, /* F64_CONVERT_S_I32_S */ /* F64_CONVERT_S_I64 */ F64, I64, /* F64_CONVERT_S_I64_S */ /* F64_CONVERT_U_I32 */ F64, I32, /* F64_CONVERT_U_I32_S */ /* F64_CONVERT_U_I64 */ F64, I64, /* F64_CONVERT_U_I64_S */ /* F64_PROMOTE_F32 */ F64, F32, /* F64_PROMOTE_F32_S */ /* F64_REINTERPRET_I64 */ F64, I64, /* F64_REINTERPRET_I64_S */ /* FALLTHROUGH_RETURN */ /* FALLTHROUGH_RETURN_S */ /* FLOOR_F16x8 */ V128, V128, /* FLOOR_F16x8_S */ /* FLOOR_F32 */ F32, F32, /* FLOOR_F32_S */ /* FLOOR_F32x4 */ V128, V128, /* FLOOR_F32x4_S */ /* FLOOR_F64 */ F64, F64, /* FLOOR_F64_S */ /* FLOOR_F64x2 */ V128, V128, /* FLOOR_F64x2_S */ /* FP_TO_SINT_I32_F32 */ I32, F32, /* FP_TO_SINT_I32_F32_S */ /* FP_TO_SINT_I32_F64 */ I32, F64, /* FP_TO_SINT_I32_F64_S */ /* FP_TO_SINT_I64_F32 */ I64, F32, /* FP_TO_SINT_I64_F32_S */ /* FP_TO_SINT_I64_F64 */ I64, F64, /* FP_TO_SINT_I64_F64_S */ /* FP_TO_UINT_I32_F32 */ I32, F32, /* FP_TO_UINT_I32_F32_S */ /* FP_TO_UINT_I32_F64 */ I32, F64, /* FP_TO_UINT_I32_F64_S */ /* FP_TO_UINT_I64_F32 */ I64, F32, /* FP_TO_UINT_I64_F32_S */ /* FP_TO_UINT_I64_F64 */ I64, F64, /* FP_TO_UINT_I64_F64_S */ /* GE_F16x8 */ V128, V128, V128, /* GE_F16x8_S */ /* GE_F32 */ I32, F32, F32, /* GE_F32_S */ /* GE_F32x4 */ V128, V128, V128, /* GE_F32x4_S */ /* GE_F64 */ I32, F64, F64, /* GE_F64_S */ /* GE_F64x2 */ V128, V128, V128, /* GE_F64x2_S */ /* GE_S_I16x8 */ V128, V128, V128, /* GE_S_I16x8_S */ /* GE_S_I32 */ I32, I32, I32, /* GE_S_I32_S */ /* GE_S_I32x4 */ V128, V128, V128, /* GE_S_I32x4_S */ /* GE_S_I64 */ I32, I64, I64, /* GE_S_I64_S */ /* GE_S_I64x2 */ V128, V128, V128, /* GE_S_I64x2_S */ /* GE_S_I8x16 */ V128, V128, V128, /* GE_S_I8x16_S */ /* GE_U_I16x8 */ V128, V128, V128, /* GE_U_I16x8_S */ /* GE_U_I32 */ I32, I32, I32, /* GE_U_I32_S */ /* GE_U_I32x4 */ V128, V128, V128, /* GE_U_I32x4_S */ /* GE_U_I64 */ I32, I64, I64, /* GE_U_I64_S */ /* GE_U_I8x16 */ V128, V128, V128, /* GE_U_I8x16_S */ /* GLOBAL_GET_EXNREF */ EXNREF, global_op32, /* GLOBAL_GET_EXNREF_S */ global_op32, /* GLOBAL_GET_EXTERNREF */ EXTERNREF, global_op32, /* GLOBAL_GET_EXTERNREF_S */ global_op32, /* GLOBAL_GET_F32 */ F32, global_op32, /* GLOBAL_GET_F32_S */ global_op32, /* GLOBAL_GET_F64 */ F64, global_op32, /* GLOBAL_GET_F64_S */ global_op32, /* GLOBAL_GET_FUNCREF */ FUNCREF, global_op32, /* GLOBAL_GET_FUNCREF_S */ global_op32, /* GLOBAL_GET_I32 */ I32, global_op32, /* GLOBAL_GET_I32_S */ global_op32, /* GLOBAL_GET_I64 */ I64, global_op64, /* GLOBAL_GET_I64_S */ global_op64, /* GLOBAL_GET_V128 */ V128, global_op32, /* GLOBAL_GET_V128_S */ global_op32, /* GLOBAL_SET_EXNREF */ global_op32, EXNREF, /* GLOBAL_SET_EXNREF_S */ global_op32, /* GLOBAL_SET_EXTERNREF */ global_op32, EXTERNREF, /* GLOBAL_SET_EXTERNREF_S */ global_op32, /* GLOBAL_SET_F32 */ global_op32, F32, /* GLOBAL_SET_F32_S */ global_op32, /* GLOBAL_SET_F64 */ global_op32, F64, /* GLOBAL_SET_F64_S */ global_op32, /* GLOBAL_SET_FUNCREF */ global_op32, FUNCREF, /* GLOBAL_SET_FUNCREF_S */ global_op32, /* GLOBAL_SET_I32 */ global_op32, I32, /* GLOBAL_SET_I32_S */ global_op32, /* GLOBAL_SET_I64 */ global_op64, I64, /* GLOBAL_SET_I64_S */ global_op64, /* GLOBAL_SET_V128 */ global_op32, V128, /* GLOBAL_SET_V128_S */ global_op32, /* GT_F16x8 */ V128, V128, V128, /* GT_F16x8_S */ /* GT_F32 */ I32, F32, F32, /* GT_F32_S */ /* GT_F32x4 */ V128, V128, V128, /* GT_F32x4_S */ /* GT_F64 */ I32, F64, F64, /* GT_F64_S */ /* GT_F64x2 */ V128, V128, V128, /* GT_F64x2_S */ /* GT_S_I16x8 */ V128, V128, V128, /* GT_S_I16x8_S */ /* GT_S_I32 */ I32, I32, I32, /* GT_S_I32_S */ /* GT_S_I32x4 */ V128, V128, V128, /* GT_S_I32x4_S */ /* GT_S_I64 */ I32, I64, I64, /* GT_S_I64_S */ /* GT_S_I64x2 */ V128, V128, V128, /* GT_S_I64x2_S */ /* GT_S_I8x16 */ V128, V128, V128, /* GT_S_I8x16_S */ /* GT_U_I16x8 */ V128, V128, V128, /* GT_U_I16x8_S */ /* GT_U_I32 */ I32, I32, I32, /* GT_U_I32_S */ /* GT_U_I32x4 */ V128, V128, V128, /* GT_U_I32x4_S */ /* GT_U_I64 */ I32, I64, I64, /* GT_U_I64_S */ /* GT_U_I8x16 */ V128, V128, V128, /* GT_U_I8x16_S */ /* I32_EXTEND16_S_I32 */ I32, I32, /* I32_EXTEND16_S_I32_S */ /* I32_EXTEND8_S_I32 */ I32, I32, /* I32_EXTEND8_S_I32_S */ /* I32_REINTERPRET_F32 */ I32, F32, /* I32_REINTERPRET_F32_S */ /* I32_TRUNC_S_F32 */ I32, F32, /* I32_TRUNC_S_F32_S */ /* I32_TRUNC_S_F64 */ I32, F64, /* I32_TRUNC_S_F64_S */ /* I32_TRUNC_S_SAT_F32 */ I32, F32, /* I32_TRUNC_S_SAT_F32_S */ /* I32_TRUNC_S_SAT_F64 */ I32, F64, /* I32_TRUNC_S_SAT_F64_S */ /* I32_TRUNC_U_F32 */ I32, F32, /* I32_TRUNC_U_F32_S */ /* I32_TRUNC_U_F64 */ I32, F64, /* I32_TRUNC_U_F64_S */ /* I32_TRUNC_U_SAT_F32 */ I32, F32, /* I32_TRUNC_U_SAT_F32_S */ /* I32_TRUNC_U_SAT_F64 */ I32, F64, /* I32_TRUNC_U_SAT_F64_S */ /* I32_WRAP_I64 */ I32, I64, /* I32_WRAP_I64_S */ /* I64_EXTEND16_S_I64 */ I64, I64, /* I64_EXTEND16_S_I64_S */ /* I64_EXTEND32_S_I64 */ I64, I64, /* I64_EXTEND32_S_I64_S */ /* I64_EXTEND8_S_I64 */ I64, I64, /* I64_EXTEND8_S_I64_S */ /* I64_EXTEND_S_I32 */ I64, I32, /* I64_EXTEND_S_I32_S */ /* I64_EXTEND_U_I32 */ I64, I32, /* I64_EXTEND_U_I32_S */ /* I64_REINTERPRET_F64 */ I64, F64, /* I64_REINTERPRET_F64_S */ /* I64_TRUNC_S_F32 */ I64, F32, /* I64_TRUNC_S_F32_S */ /* I64_TRUNC_S_F64 */ I64, F64, /* I64_TRUNC_S_F64_S */ /* I64_TRUNC_S_SAT_F32 */ I64, F32, /* I64_TRUNC_S_SAT_F32_S */ /* I64_TRUNC_S_SAT_F64 */ I64, F64, /* I64_TRUNC_S_SAT_F64_S */ /* I64_TRUNC_U_F32 */ I64, F32, /* I64_TRUNC_U_F32_S */ /* I64_TRUNC_U_F64 */ I64, F64, /* I64_TRUNC_U_F64_S */ /* I64_TRUNC_U_SAT_F32 */ I64, F32, /* I64_TRUNC_U_SAT_F32_S */ /* I64_TRUNC_U_SAT_F64 */ I64, F64, /* I64_TRUNC_U_SAT_F64_S */ /* IF */ Signature, I32, /* IF_S */ Signature, /* LANESELECT_I16x8 */ V128, V128, V128, V128, /* LANESELECT_I16x8_S */ /* LANESELECT_I32x4 */ V128, V128, V128, V128, /* LANESELECT_I32x4_S */ /* LANESELECT_I64x2 */ V128, V128, V128, V128, /* LANESELECT_I64x2_S */ /* LANESELECT_I8x16 */ V128, V128, V128, V128, /* LANESELECT_I8x16_S */ /* LE_F16x8 */ V128, V128, V128, /* LE_F16x8_S */ /* LE_F32 */ I32, F32, F32, /* LE_F32_S */ /* LE_F32x4 */ V128, V128, V128, /* LE_F32x4_S */ /* LE_F64 */ I32, F64, F64, /* LE_F64_S */ /* LE_F64x2 */ V128, V128, V128, /* LE_F64x2_S */ /* LE_S_I16x8 */ V128, V128, V128, /* LE_S_I16x8_S */ /* LE_S_I32 */ I32, I32, I32, /* LE_S_I32_S */ /* LE_S_I32x4 */ V128, V128, V128, /* LE_S_I32x4_S */ /* LE_S_I64 */ I32, I64, I64, /* LE_S_I64_S */ /* LE_S_I64x2 */ V128, V128, V128, /* LE_S_I64x2_S */ /* LE_S_I8x16 */ V128, V128, V128, /* LE_S_I8x16_S */ /* LE_U_I16x8 */ V128, V128, V128, /* LE_U_I16x8_S */ /* LE_U_I32 */ I32, I32, I32, /* LE_U_I32_S */ /* LE_U_I32x4 */ V128, V128, V128, /* LE_U_I32x4_S */ /* LE_U_I64 */ I32, I64, I64, /* LE_U_I64_S */ /* LE_U_I8x16 */ V128, V128, V128, /* LE_U_I8x16_S */ /* LOAD16_SPLAT_A32 */ V128, P2Align, offset32_op, I32, /* LOAD16_SPLAT_A32_S */ P2Align, offset32_op, /* LOAD16_SPLAT_A64 */ V128, P2Align, offset64_op, I64, /* LOAD16_SPLAT_A64_S */ P2Align, offset64_op, /* LOAD16_S_I32_A32 */ I32, P2Align, offset32_op, I32, /* LOAD16_S_I32_A32_S */ P2Align, offset32_op, /* LOAD16_S_I32_A64 */ I32, P2Align, offset64_op, I64, /* LOAD16_S_I32_A64_S */ P2Align, offset64_op, /* LOAD16_S_I64_A32 */ I64, P2Align, offset32_op, I32, /* LOAD16_S_I64_A32_S */ P2Align, offset32_op, /* LOAD16_S_I64_A64 */ I64, P2Align, offset64_op, I64, /* LOAD16_S_I64_A64_S */ P2Align, offset64_op, /* LOAD16_U_I32_A32 */ I32, P2Align, offset32_op, I32, /* LOAD16_U_I32_A32_S */ P2Align, offset32_op, /* LOAD16_U_I32_A64 */ I32, P2Align, offset64_op, I64, /* LOAD16_U_I32_A64_S */ P2Align, offset64_op, /* LOAD16_U_I64_A32 */ I64, P2Align, offset32_op, I32, /* LOAD16_U_I64_A32_S */ P2Align, offset32_op, /* LOAD16_U_I64_A64 */ I64, P2Align, offset64_op, I64, /* LOAD16_U_I64_A64_S */ P2Align, offset64_op, /* LOAD32_SPLAT_A32 */ V128, P2Align, offset32_op, I32, /* LOAD32_SPLAT_A32_S */ P2Align, offset32_op, /* LOAD32_SPLAT_A64 */ V128, P2Align, offset64_op, I64, /* LOAD32_SPLAT_A64_S */ P2Align, offset64_op, /* LOAD32_S_I64_A32 */ I64, P2Align, offset32_op, I32, /* LOAD32_S_I64_A32_S */ P2Align, offset32_op, /* LOAD32_S_I64_A64 */ I64, P2Align, offset64_op, I64, /* LOAD32_S_I64_A64_S */ P2Align, offset64_op, /* LOAD32_U_I64_A32 */ I64, P2Align, offset32_op, I32, /* LOAD32_U_I64_A32_S */ P2Align, offset32_op, /* LOAD32_U_I64_A64 */ I64, P2Align, offset64_op, I64, /* LOAD32_U_I64_A64_S */ P2Align, offset64_op, /* LOAD64_SPLAT_A32 */ V128, P2Align, offset32_op, I32, /* LOAD64_SPLAT_A32_S */ P2Align, offset32_op, /* LOAD64_SPLAT_A64 */ V128, P2Align, offset64_op, I64, /* LOAD64_SPLAT_A64_S */ P2Align, offset64_op, /* LOAD8_SPLAT_A32 */ V128, P2Align, offset32_op, I32, /* LOAD8_SPLAT_A32_S */ P2Align, offset32_op, /* LOAD8_SPLAT_A64 */ V128, P2Align, offset64_op, I64, /* LOAD8_SPLAT_A64_S */ P2Align, offset64_op, /* LOAD8_S_I32_A32 */ I32, P2Align, offset32_op, I32, /* LOAD8_S_I32_A32_S */ P2Align, offset32_op, /* LOAD8_S_I32_A64 */ I32, P2Align, offset64_op, I64, /* LOAD8_S_I32_A64_S */ P2Align, offset64_op, /* LOAD8_S_I64_A32 */ I64, P2Align, offset32_op, I32, /* LOAD8_S_I64_A32_S */ P2Align, offset32_op, /* LOAD8_S_I64_A64 */ I64, P2Align, offset64_op, I64, /* LOAD8_S_I64_A64_S */ P2Align, offset64_op, /* LOAD8_U_I32_A32 */ I32, P2Align, offset32_op, I32, /* LOAD8_U_I32_A32_S */ P2Align, offset32_op, /* LOAD8_U_I32_A64 */ I32, P2Align, offset64_op, I64, /* LOAD8_U_I32_A64_S */ P2Align, offset64_op, /* LOAD8_U_I64_A32 */ I64, P2Align, offset32_op, I32, /* LOAD8_U_I64_A32_S */ P2Align, offset32_op, /* LOAD8_U_I64_A64 */ I64, P2Align, offset64_op, I64, /* LOAD8_U_I64_A64_S */ P2Align, offset64_op, /* LOAD_EXTEND_S_I16x8_A32 */ V128, P2Align, offset32_op, I32, /* LOAD_EXTEND_S_I16x8_A32_S */ P2Align, offset32_op, /* LOAD_EXTEND_S_I16x8_A64 */ V128, P2Align, offset64_op, I64, /* LOAD_EXTEND_S_I16x8_A64_S */ P2Align, offset64_op, /* LOAD_EXTEND_S_I32x4_A32 */ V128, P2Align, offset32_op, I32, /* LOAD_EXTEND_S_I32x4_A32_S */ P2Align, offset32_op, /* LOAD_EXTEND_S_I32x4_A64 */ V128, P2Align, offset64_op, I64, /* LOAD_EXTEND_S_I32x4_A64_S */ P2Align, offset64_op, /* LOAD_EXTEND_S_I64x2_A32 */ V128, P2Align, offset32_op, I32, /* LOAD_EXTEND_S_I64x2_A32_S */ P2Align, offset32_op, /* LOAD_EXTEND_S_I64x2_A64 */ V128, P2Align, offset64_op, I64, /* LOAD_EXTEND_S_I64x2_A64_S */ P2Align, offset64_op, /* LOAD_EXTEND_U_I16x8_A32 */ V128, P2Align, offset32_op, I32, /* LOAD_EXTEND_U_I16x8_A32_S */ P2Align, offset32_op, /* LOAD_EXTEND_U_I16x8_A64 */ V128, P2Align, offset64_op, I64, /* LOAD_EXTEND_U_I16x8_A64_S */ P2Align, offset64_op, /* LOAD_EXTEND_U_I32x4_A32 */ V128, P2Align, offset32_op, I32, /* LOAD_EXTEND_U_I32x4_A32_S */ P2Align, offset32_op, /* LOAD_EXTEND_U_I32x4_A64 */ V128, P2Align, offset64_op, I64, /* LOAD_EXTEND_U_I32x4_A64_S */ P2Align, offset64_op, /* LOAD_EXTEND_U_I64x2_A32 */ V128, P2Align, offset32_op, I32, /* LOAD_EXTEND_U_I64x2_A32_S */ P2Align, offset32_op, /* LOAD_EXTEND_U_I64x2_A64 */ V128, P2Align, offset64_op, I64, /* LOAD_EXTEND_U_I64x2_A64_S */ P2Align, offset64_op, /* LOAD_F16_F32_A32 */ F32, P2Align, offset32_op, I32, /* LOAD_F16_F32_A32_S */ P2Align, offset32_op, /* LOAD_F16_F32_A64 */ F32, P2Align, offset64_op, I64, /* LOAD_F16_F32_A64_S */ P2Align, offset64_op, /* LOAD_F32_A32 */ F32, P2Align, offset32_op, I32, /* LOAD_F32_A32_S */ P2Align, offset32_op, /* LOAD_F32_A64 */ F32, P2Align, offset64_op, I64, /* LOAD_F32_A64_S */ P2Align, offset64_op, /* LOAD_F64_A32 */ F64, P2Align, offset32_op, I32, /* LOAD_F64_A32_S */ P2Align, offset32_op, /* LOAD_F64_A64 */ F64, P2Align, offset64_op, I64, /* LOAD_F64_A64_S */ P2Align, offset64_op, /* LOAD_I32_A32 */ I32, P2Align, offset32_op, I32, /* LOAD_I32_A32_S */ P2Align, offset32_op, /* LOAD_I32_A64 */ I32, P2Align, offset64_op, I64, /* LOAD_I32_A64_S */ P2Align, offset64_op, /* LOAD_I64_A32 */ I64, P2Align, offset32_op, I32, /* LOAD_I64_A32_S */ P2Align, offset32_op, /* LOAD_I64_A64 */ I64, P2Align, offset64_op, I64, /* LOAD_I64_A64_S */ P2Align, offset64_op, /* LOAD_LANE_16_A32 */ V128, P2Align, offset32_op, vec_i8imm_op, I32, V128, /* LOAD_LANE_16_A32_S */ P2Align, offset32_op, vec_i8imm_op, /* LOAD_LANE_16_A64 */ V128, P2Align, offset64_op, vec_i8imm_op, I64, V128, /* LOAD_LANE_16_A64_S */ P2Align, offset64_op, vec_i8imm_op, /* LOAD_LANE_32_A32 */ V128, P2Align, offset32_op, vec_i8imm_op, I32, V128, /* LOAD_LANE_32_A32_S */ P2Align, offset32_op, vec_i8imm_op, /* LOAD_LANE_32_A64 */ V128, P2Align, offset64_op, vec_i8imm_op, I64, V128, /* LOAD_LANE_32_A64_S */ P2Align, offset64_op, vec_i8imm_op, /* LOAD_LANE_64_A32 */ V128, P2Align, offset32_op, vec_i8imm_op, I32, V128, /* LOAD_LANE_64_A32_S */ P2Align, offset32_op, vec_i8imm_op, /* LOAD_LANE_64_A64 */ V128, P2Align, offset64_op, vec_i8imm_op, I64, V128, /* LOAD_LANE_64_A64_S */ P2Align, offset64_op, vec_i8imm_op, /* LOAD_LANE_8_A32 */ V128, P2Align, offset32_op, vec_i8imm_op, I32, V128, /* LOAD_LANE_8_A32_S */ P2Align, offset32_op, vec_i8imm_op, /* LOAD_LANE_8_A64 */ V128, P2Align, offset64_op, vec_i8imm_op, I64, V128, /* LOAD_LANE_8_A64_S */ P2Align, offset64_op, vec_i8imm_op, /* LOAD_V128_A32 */ V128, P2Align, offset32_op, I32, /* LOAD_V128_A32_S */ P2Align, offset32_op, /* LOAD_V128_A64 */ V128, P2Align, offset64_op, I64, /* LOAD_V128_A64_S */ P2Align, offset64_op, /* LOAD_ZERO_32_A32 */ V128, P2Align, offset32_op, I32, /* LOAD_ZERO_32_A32_S */ P2Align, offset32_op, /* LOAD_ZERO_32_A64 */ V128, P2Align, offset64_op, I64, /* LOAD_ZERO_32_A64_S */ P2Align, offset64_op, /* LOAD_ZERO_64_A32 */ V128, P2Align, offset32_op, I32, /* LOAD_ZERO_64_A32_S */ P2Align, offset32_op, /* LOAD_ZERO_64_A64 */ V128, P2Align, offset64_op, I64, /* LOAD_ZERO_64_A64_S */ P2Align, offset64_op, /* LOCAL_GET_EXNREF */ EXNREF, local_op, /* LOCAL_GET_EXNREF_S */ local_op, /* LOCAL_GET_EXTERNREF */ EXTERNREF, local_op, /* LOCAL_GET_EXTERNREF_S */ local_op, /* LOCAL_GET_F32 */ F32, local_op, /* LOCAL_GET_F32_S */ local_op, /* LOCAL_GET_F64 */ F64, local_op, /* LOCAL_GET_F64_S */ local_op, /* LOCAL_GET_FUNCREF */ FUNCREF, local_op, /* LOCAL_GET_FUNCREF_S */ local_op, /* LOCAL_GET_I32 */ I32, local_op, /* LOCAL_GET_I32_S */ local_op, /* LOCAL_GET_I64 */ I64, local_op, /* LOCAL_GET_I64_S */ local_op, /* LOCAL_GET_V128 */ V128, local_op, /* LOCAL_GET_V128_S */ local_op, /* LOCAL_SET_EXNREF */ local_op, EXNREF, /* LOCAL_SET_EXNREF_S */ local_op, /* LOCAL_SET_EXTERNREF */ local_op, EXTERNREF, /* LOCAL_SET_EXTERNREF_S */ local_op, /* LOCAL_SET_F32 */ local_op, F32, /* LOCAL_SET_F32_S */ local_op, /* LOCAL_SET_F64 */ local_op, F64, /* LOCAL_SET_F64_S */ local_op, /* LOCAL_SET_FUNCREF */ local_op, FUNCREF, /* LOCAL_SET_FUNCREF_S */ local_op, /* LOCAL_SET_I32 */ local_op, I32, /* LOCAL_SET_I32_S */ local_op, /* LOCAL_SET_I64 */ local_op, I64, /* LOCAL_SET_I64_S */ local_op, /* LOCAL_SET_V128 */ local_op, V128, /* LOCAL_SET_V128_S */ local_op, /* LOCAL_TEE_EXNREF */ EXNREF, local_op, EXNREF, /* LOCAL_TEE_EXNREF_S */ local_op, /* LOCAL_TEE_EXTERNREF */ EXTERNREF, local_op, EXTERNREF, /* LOCAL_TEE_EXTERNREF_S */ local_op, /* LOCAL_TEE_F32 */ F32, local_op, F32, /* LOCAL_TEE_F32_S */ local_op, /* LOCAL_TEE_F64 */ F64, local_op, F64, /* LOCAL_TEE_F64_S */ local_op, /* LOCAL_TEE_FUNCREF */ FUNCREF, local_op, FUNCREF, /* LOCAL_TEE_FUNCREF_S */ local_op, /* LOCAL_TEE_I32 */ I32, local_op, I32, /* LOCAL_TEE_I32_S */ local_op, /* LOCAL_TEE_I64 */ I64, local_op, I64, /* LOCAL_TEE_I64_S */ local_op, /* LOCAL_TEE_V128 */ V128, local_op, V128, /* LOCAL_TEE_V128_S */ local_op, /* LOOP */ Signature, /* LOOP_S */ Signature, /* LT_F16x8 */ V128, V128, V128, /* LT_F16x8_S */ /* LT_F32 */ I32, F32, F32, /* LT_F32_S */ /* LT_F32x4 */ V128, V128, V128, /* LT_F32x4_S */ /* LT_F64 */ I32, F64, F64, /* LT_F64_S */ /* LT_F64x2 */ V128, V128, V128, /* LT_F64x2_S */ /* LT_S_I16x8 */ V128, V128, V128, /* LT_S_I16x8_S */ /* LT_S_I32 */ I32, I32, I32, /* LT_S_I32_S */ /* LT_S_I32x4 */ V128, V128, V128, /* LT_S_I32x4_S */ /* LT_S_I64 */ I32, I64, I64, /* LT_S_I64_S */ /* LT_S_I64x2 */ V128, V128, V128, /* LT_S_I64x2_S */ /* LT_S_I8x16 */ V128, V128, V128, /* LT_S_I8x16_S */ /* LT_U_I16x8 */ V128, V128, V128, /* LT_U_I16x8_S */ /* LT_U_I32 */ I32, I32, I32, /* LT_U_I32_S */ /* LT_U_I32x4 */ V128, V128, V128, /* LT_U_I32x4_S */ /* LT_U_I64 */ I32, I64, I64, /* LT_U_I64_S */ /* LT_U_I8x16 */ V128, V128, V128, /* LT_U_I8x16_S */ /* MADD_F16x8 */ V128, V128, V128, V128, /* MADD_F16x8_S */ /* MADD_F32x4 */ V128, V128, V128, V128, /* MADD_F32x4_S */ /* MADD_F64x2 */ V128, V128, V128, V128, /* MADD_F64x2_S */ /* MAX_F16x8 */ V128, V128, V128, /* MAX_F16x8_S */ /* MAX_F32 */ F32, F32, F32, /* MAX_F32_S */ /* MAX_F32x4 */ V128, V128, V128, /* MAX_F32x4_S */ /* MAX_F64 */ F64, F64, F64, /* MAX_F64_S */ /* MAX_F64x2 */ V128, V128, V128, /* MAX_F64x2_S */ /* MAX_S_I16x8 */ V128, V128, V128, /* MAX_S_I16x8_S */ /* MAX_S_I32x4 */ V128, V128, V128, /* MAX_S_I32x4_S */ /* MAX_S_I8x16 */ V128, V128, V128, /* MAX_S_I8x16_S */ /* MAX_U_I16x8 */ V128, V128, V128, /* MAX_U_I16x8_S */ /* MAX_U_I32x4 */ V128, V128, V128, /* MAX_U_I32x4_S */ /* MAX_U_I8x16 */ V128, V128, V128, /* MAX_U_I8x16_S */ /* MEMORY_ATOMIC_NOTIFY_A32 */ I32, P2Align, offset32_op, I32, I32, /* MEMORY_ATOMIC_NOTIFY_A32_S */ P2Align, offset32_op, /* MEMORY_ATOMIC_NOTIFY_A64 */ I32, P2Align, offset64_op, I64, I32, /* MEMORY_ATOMIC_NOTIFY_A64_S */ P2Align, offset64_op, /* MEMORY_ATOMIC_WAIT32_A32 */ I32, P2Align, offset32_op, I32, I32, I64, /* MEMORY_ATOMIC_WAIT32_A32_S */ P2Align, offset32_op, /* MEMORY_ATOMIC_WAIT32_A64 */ I32, P2Align, offset64_op, I64, I32, I64, /* MEMORY_ATOMIC_WAIT32_A64_S */ P2Align, offset64_op, /* MEMORY_ATOMIC_WAIT64_A32 */ I32, P2Align, offset32_op, I32, I64, I64, /* MEMORY_ATOMIC_WAIT64_A32_S */ P2Align, offset32_op, /* MEMORY_ATOMIC_WAIT64_A64 */ I32, P2Align, offset64_op, I64, I64, I64, /* MEMORY_ATOMIC_WAIT64_A64_S */ P2Align, offset64_op, /* MIN_F16x8 */ V128, V128, V128, /* MIN_F16x8_S */ /* MIN_F32 */ F32, F32, F32, /* MIN_F32_S */ /* MIN_F32x4 */ V128, V128, V128, /* MIN_F32x4_S */ /* MIN_F64 */ F64, F64, F64, /* MIN_F64_S */ /* MIN_F64x2 */ V128, V128, V128, /* MIN_F64x2_S */ /* MIN_S_I16x8 */ V128, V128, V128, /* MIN_S_I16x8_S */ /* MIN_S_I32x4 */ V128, V128, V128, /* MIN_S_I32x4_S */ /* MIN_S_I8x16 */ V128, V128, V128, /* MIN_S_I8x16_S */ /* MIN_U_I16x8 */ V128, V128, V128, /* MIN_U_I16x8_S */ /* MIN_U_I32x4 */ V128, V128, V128, /* MIN_U_I32x4_S */ /* MIN_U_I8x16 */ V128, V128, V128, /* MIN_U_I8x16_S */ /* MUL_F16x8 */ V128, V128, V128, /* MUL_F16x8_S */ /* MUL_F32 */ F32, F32, F32, /* MUL_F32_S */ /* MUL_F32x4 */ V128, V128, V128, /* MUL_F32x4_S */ /* MUL_F64 */ F64, F64, F64, /* MUL_F64_S */ /* MUL_F64x2 */ V128, V128, V128, /* MUL_F64x2_S */ /* MUL_I16x8 */ V128, V128, V128, /* MUL_I16x8_S */ /* MUL_I32 */ I32, I32, I32, /* MUL_I32_S */ /* MUL_I32x4 */ V128, V128, V128, /* MUL_I32x4_S */ /* MUL_I64 */ I64, I64, I64, /* MUL_I64_S */ /* MUL_I64x2 */ V128, V128, V128, /* MUL_I64x2_S */ /* NARROW_S_I16x8 */ V128, V128, V128, /* NARROW_S_I16x8_S */ /* NARROW_S_I8x16 */ V128, V128, V128, /* NARROW_S_I8x16_S */ /* NARROW_U_I16x8 */ V128, V128, V128, /* NARROW_U_I16x8_S */ /* NARROW_U_I8x16 */ V128, V128, V128, /* NARROW_U_I8x16_S */ /* NEAREST_F16x8 */ V128, V128, /* NEAREST_F16x8_S */ /* NEAREST_F32 */ F32, F32, /* NEAREST_F32_S */ /* NEAREST_F32x4 */ V128, V128, /* NEAREST_F32x4_S */ /* NEAREST_F64 */ F64, F64, /* NEAREST_F64_S */ /* NEAREST_F64x2 */ V128, V128, /* NEAREST_F64x2_S */ /* NEG_F16x8 */ V128, V128, /* NEG_F16x8_S */ /* NEG_F32 */ F32, F32, /* NEG_F32_S */ /* NEG_F32x4 */ V128, V128, /* NEG_F32x4_S */ /* NEG_F64 */ F64, F64, /* NEG_F64_S */ /* NEG_F64x2 */ V128, V128, /* NEG_F64x2_S */ /* NEG_I16x8 */ V128, V128, /* NEG_I16x8_S */ /* NEG_I32x4 */ V128, V128, /* NEG_I32x4_S */ /* NEG_I64x2 */ V128, V128, /* NEG_I64x2_S */ /* NEG_I8x16 */ V128, V128, /* NEG_I8x16_S */ /* NE_F16x8 */ V128, V128, V128, /* NE_F16x8_S */ /* NE_F32 */ I32, F32, F32, /* NE_F32_S */ /* NE_F32x4 */ V128, V128, V128, /* NE_F32x4_S */ /* NE_F64 */ I32, F64, F64, /* NE_F64_S */ /* NE_F64x2 */ V128, V128, V128, /* NE_F64x2_S */ /* NE_I16x8 */ V128, V128, V128, /* NE_I16x8_S */ /* NE_I32 */ I32, I32, I32, /* NE_I32_S */ /* NE_I32x4 */ V128, V128, V128, /* NE_I32x4_S */ /* NE_I64 */ I32, I64, I64, /* NE_I64_S */ /* NE_I64x2 */ V128, V128, V128, /* NE_I64x2_S */ /* NE_I8x16 */ V128, V128, V128, /* NE_I8x16_S */ /* NMADD_F16x8 */ V128, V128, V128, V128, /* NMADD_F16x8_S */ /* NMADD_F32x4 */ V128, V128, V128, V128, /* NMADD_F32x4_S */ /* NMADD_F64x2 */ V128, V128, V128, V128, /* NMADD_F64x2_S */ /* NOP */ /* NOP_S */ /* NOT */ V128, V128, /* NOT_S */ /* OR */ V128, V128, V128, /* OR_I32 */ I32, I32, I32, /* OR_I32_S */ /* OR_I64 */ I64, I64, I64, /* OR_I64_S */ /* OR_S */ /* PMAX_F16x8 */ V128, V128, V128, /* PMAX_F16x8_S */ /* PMAX_F32x4 */ V128, V128, V128, /* PMAX_F32x4_S */ /* PMAX_F64x2 */ V128, V128, V128, /* PMAX_F64x2_S */ /* PMIN_F16x8 */ V128, V128, V128, /* PMIN_F16x8_S */ /* PMIN_F32x4 */ V128, V128, V128, /* PMIN_F32x4_S */ /* PMIN_F64x2 */ V128, V128, V128, /* PMIN_F64x2_S */ /* POPCNT_I32 */ I32, I32, /* POPCNT_I32_S */ /* POPCNT_I64 */ I64, I64, /* POPCNT_I64_S */ /* POPCNT_I8x16 */ V128, V128, /* POPCNT_I8x16_S */ /* Q15MULR_SAT_S_I16x8 */ V128, V128, V128, /* Q15MULR_SAT_S_I16x8_S */ /* REF_IS_NULL_EXNREF */ I32, EXNREF, /* REF_IS_NULL_EXNREF_S */ /* REF_IS_NULL_EXTERNREF */ I32, EXTERNREF, /* REF_IS_NULL_EXTERNREF_S */ /* REF_IS_NULL_FUNCREF */ I32, FUNCREF, /* REF_IS_NULL_FUNCREF_S */ /* REF_NULL_EXNREF */ EXNREF, /* REF_NULL_EXNREF_S */ /* REF_NULL_EXTERNREF */ EXTERNREF, /* REF_NULL_EXTERNREF_S */ /* REF_NULL_FUNCREF */ FUNCREF, /* REF_NULL_FUNCREF_S */ /* RELAXED_DOT */ V128, V128, V128, /* RELAXED_DOT_ADD */ V128, V128, V128, V128, /* RELAXED_DOT_ADD_S */ /* RELAXED_DOT_BFLOAT */ V128, V128, V128, V128, /* RELAXED_DOT_BFLOAT_S */ /* RELAXED_DOT_S */ /* RELAXED_Q15MULR_S_I16x8 */ V128, V128, V128, /* RELAXED_Q15MULR_S_I16x8_S */ /* RELAXED_SWIZZLE */ V128, V128, V128, /* RELAXED_SWIZZLE_S */ /* REM_S_I32 */ I32, I32, I32, /* REM_S_I32_S */ /* REM_S_I64 */ I64, I64, I64, /* REM_S_I64_S */ /* REM_U_I32 */ I32, I32, I32, /* REM_U_I32_S */ /* REM_U_I64 */ I64, I64, I64, /* REM_U_I64_S */ /* REPLACE_LANE_F16x8 */ V128, V128, vec_i8imm_op, F32, /* REPLACE_LANE_F16x8_S */ vec_i8imm_op, /* REPLACE_LANE_F32x4 */ V128, V128, vec_i8imm_op, F32, /* REPLACE_LANE_F32x4_S */ vec_i8imm_op, /* REPLACE_LANE_F64x2 */ V128, V128, vec_i8imm_op, F64, /* REPLACE_LANE_F64x2_S */ vec_i8imm_op, /* REPLACE_LANE_I16x8 */ V128, V128, vec_i8imm_op, I32, /* REPLACE_LANE_I16x8_S */ vec_i8imm_op, /* REPLACE_LANE_I32x4 */ V128, V128, vec_i8imm_op, I32, /* REPLACE_LANE_I32x4_S */ vec_i8imm_op, /* REPLACE_LANE_I64x2 */ V128, V128, vec_i8imm_op, I64, /* REPLACE_LANE_I64x2_S */ vec_i8imm_op, /* REPLACE_LANE_I8x16 */ V128, V128, vec_i8imm_op, I32, /* REPLACE_LANE_I8x16_S */ vec_i8imm_op, /* RETHROW */ i32imm, /* RETHROW_S */ i32imm, /* RETURN */ /* RETURN_S */ /* RET_CALL */ function32_op, /* RET_CALL_INDIRECT */ TypeIndex, table32_op, /* RET_CALL_INDIRECT_S */ TypeIndex, table32_op, /* RET_CALL_S */ function32_op, /* ROTL_I32 */ I32, I32, I32, /* ROTL_I32_S */ /* ROTL_I64 */ I64, I64, I64, /* ROTL_I64_S */ /* ROTR_I32 */ I32, I32, I32, /* ROTR_I32_S */ /* ROTR_I64 */ I64, I64, I64, /* ROTR_I64_S */ /* SELECT_EXNREF */ EXNREF, EXNREF, EXNREF, I32, /* SELECT_EXNREF_S */ /* SELECT_EXTERNREF */ EXTERNREF, EXTERNREF, EXTERNREF, I32, /* SELECT_EXTERNREF_S */ /* SELECT_F32 */ F32, F32, F32, I32, /* SELECT_F32_S */ /* SELECT_F64 */ F64, F64, F64, I32, /* SELECT_F64_S */ /* SELECT_FUNCREF */ FUNCREF, FUNCREF, FUNCREF, I32, /* SELECT_FUNCREF_S */ /* SELECT_I32 */ I32, I32, I32, I32, /* SELECT_I32_S */ /* SELECT_I64 */ I64, I64, I64, I32, /* SELECT_I64_S */ /* SELECT_V128 */ V128, V128, V128, I32, /* SELECT_V128_S */ /* SHL_I16x8 */ V128, V128, I32, /* SHL_I16x8_S */ /* SHL_I32 */ I32, I32, I32, /* SHL_I32_S */ /* SHL_I32x4 */ V128, V128, I32, /* SHL_I32x4_S */ /* SHL_I64 */ I64, I64, I64, /* SHL_I64_S */ /* SHL_I64x2 */ V128, V128, I32, /* SHL_I64x2_S */ /* SHL_I8x16 */ V128, V128, I32, /* SHL_I8x16_S */ /* SHR_S_I16x8 */ V128, V128, I32, /* SHR_S_I16x8_S */ /* SHR_S_I32 */ I32, I32, I32, /* SHR_S_I32_S */ /* SHR_S_I32x4 */ V128, V128, I32, /* SHR_S_I32x4_S */ /* SHR_S_I64 */ I64, I64, I64, /* SHR_S_I64_S */ /* SHR_S_I64x2 */ V128, V128, I32, /* SHR_S_I64x2_S */ /* SHR_S_I8x16 */ V128, V128, I32, /* SHR_S_I8x16_S */ /* SHR_U_I16x8 */ V128, V128, I32, /* SHR_U_I16x8_S */ /* SHR_U_I32 */ I32, I32, I32, /* SHR_U_I32_S */ /* SHR_U_I32x4 */ V128, V128, I32, /* SHR_U_I32x4_S */ /* SHR_U_I64 */ I64, I64, I64, /* SHR_U_I64_S */ /* SHR_U_I64x2 */ V128, V128, I32, /* SHR_U_I64x2_S */ /* SHR_U_I8x16 */ V128, V128, I32, /* SHR_U_I8x16_S */ /* SHUFFLE */ V128, V128, V128, vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, /* SHUFFLE_S */ vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, /* SIMD_RELAXED_FMAX_F32x4 */ V128, V128, V128, /* SIMD_RELAXED_FMAX_F32x4_S */ /* SIMD_RELAXED_FMAX_F64x2 */ V128, V128, V128, /* SIMD_RELAXED_FMAX_F64x2_S */ /* SIMD_RELAXED_FMIN_F32x4 */ V128, V128, V128, /* SIMD_RELAXED_FMIN_F32x4_S */ /* SIMD_RELAXED_FMIN_F64x2 */ V128, V128, V128, /* SIMD_RELAXED_FMIN_F64x2_S */ /* SPLAT_F16x8 */ V128, F32, /* SPLAT_F16x8_S */ /* SPLAT_F32x4 */ V128, F32, /* SPLAT_F32x4_S */ /* SPLAT_F64x2 */ V128, F64, /* SPLAT_F64x2_S */ /* SPLAT_I16x8 */ V128, I32, /* SPLAT_I16x8_S */ /* SPLAT_I32x4 */ V128, I32, /* SPLAT_I32x4_S */ /* SPLAT_I64x2 */ V128, I64, /* SPLAT_I64x2_S */ /* SPLAT_I8x16 */ V128, I32, /* SPLAT_I8x16_S */ /* SQRT_F16x8 */ V128, V128, /* SQRT_F16x8_S */ /* SQRT_F32 */ F32, F32, /* SQRT_F32_S */ /* SQRT_F32x4 */ V128, V128, /* SQRT_F32x4_S */ /* SQRT_F64 */ F64, F64, /* SQRT_F64_S */ /* SQRT_F64x2 */ V128, V128, /* SQRT_F64x2_S */ /* STORE16_I32_A32 */ P2Align, offset32_op, I32, I32, /* STORE16_I32_A32_S */ P2Align, offset32_op, /* STORE16_I32_A64 */ P2Align, offset64_op, I64, I32, /* STORE16_I32_A64_S */ P2Align, offset64_op, /* STORE16_I64_A32 */ P2Align, offset32_op, I32, I64, /* STORE16_I64_A32_S */ P2Align, offset32_op, /* STORE16_I64_A64 */ P2Align, offset64_op, I64, I64, /* STORE16_I64_A64_S */ P2Align, offset64_op, /* STORE32_I64_A32 */ P2Align, offset32_op, I32, I64, /* STORE32_I64_A32_S */ P2Align, offset32_op, /* STORE32_I64_A64 */ P2Align, offset64_op, I64, I64, /* STORE32_I64_A64_S */ P2Align, offset64_op, /* STORE8_I32_A32 */ P2Align, offset32_op, I32, I32, /* STORE8_I32_A32_S */ P2Align, offset32_op, /* STORE8_I32_A64 */ P2Align, offset64_op, I64, I32, /* STORE8_I32_A64_S */ P2Align, offset64_op, /* STORE8_I64_A32 */ P2Align, offset32_op, I32, I64, /* STORE8_I64_A32_S */ P2Align, offset32_op, /* STORE8_I64_A64 */ P2Align, offset64_op, I64, I64, /* STORE8_I64_A64_S */ P2Align, offset64_op, /* STORE_F16_F32_A32 */ P2Align, offset32_op, I32, F32, /* STORE_F16_F32_A32_S */ P2Align, offset32_op, /* STORE_F16_F32_A64 */ P2Align, offset64_op, I64, F32, /* STORE_F16_F32_A64_S */ P2Align, offset64_op, /* STORE_F32_A32 */ P2Align, offset32_op, I32, F32, /* STORE_F32_A32_S */ P2Align, offset32_op, /* STORE_F32_A64 */ P2Align, offset64_op, I64, F32, /* STORE_F32_A64_S */ P2Align, offset64_op, /* STORE_F64_A32 */ P2Align, offset32_op, I32, F64, /* STORE_F64_A32_S */ P2Align, offset32_op, /* STORE_F64_A64 */ P2Align, offset64_op, I64, F64, /* STORE_F64_A64_S */ P2Align, offset64_op, /* STORE_I32_A32 */ P2Align, offset32_op, I32, I32, /* STORE_I32_A32_S */ P2Align, offset32_op, /* STORE_I32_A64 */ P2Align, offset64_op, I64, I32, /* STORE_I32_A64_S */ P2Align, offset64_op, /* STORE_I64_A32 */ P2Align, offset32_op, I32, I64, /* STORE_I64_A32_S */ P2Align, offset32_op, /* STORE_I64_A64 */ P2Align, offset64_op, I64, I64, /* STORE_I64_A64_S */ P2Align, offset64_op, /* STORE_LANE_I16x8_A32 */ P2Align, offset32_op, vec_i8imm_op, I32, V128, /* STORE_LANE_I16x8_A32_S */ P2Align, offset32_op, vec_i8imm_op, /* STORE_LANE_I16x8_A64 */ P2Align, offset64_op, vec_i8imm_op, I64, V128, /* STORE_LANE_I16x8_A64_S */ P2Align, offset64_op, vec_i8imm_op, /* STORE_LANE_I32x4_A32 */ P2Align, offset32_op, vec_i8imm_op, I32, V128, /* STORE_LANE_I32x4_A32_S */ P2Align, offset32_op, vec_i8imm_op, /* STORE_LANE_I32x4_A64 */ P2Align, offset64_op, vec_i8imm_op, I64, V128, /* STORE_LANE_I32x4_A64_S */ P2Align, offset64_op, vec_i8imm_op, /* STORE_LANE_I64x2_A32 */ P2Align, offset32_op, vec_i8imm_op, I32, V128, /* STORE_LANE_I64x2_A32_S */ P2Align, offset32_op, vec_i8imm_op, /* STORE_LANE_I64x2_A64 */ P2Align, offset64_op, vec_i8imm_op, I64, V128, /* STORE_LANE_I64x2_A64_S */ P2Align, offset64_op, vec_i8imm_op, /* STORE_LANE_I8x16_A32 */ P2Align, offset32_op, vec_i8imm_op, I32, V128, /* STORE_LANE_I8x16_A32_S */ P2Align, offset32_op, vec_i8imm_op, /* STORE_LANE_I8x16_A64 */ P2Align, offset64_op, vec_i8imm_op, I64, V128, /* STORE_LANE_I8x16_A64_S */ P2Align, offset64_op, vec_i8imm_op, /* STORE_V128_A32 */ P2Align, offset32_op, I32, V128, /* STORE_V128_A32_S */ P2Align, offset32_op, /* STORE_V128_A64 */ P2Align, offset64_op, I64, V128, /* STORE_V128_A64_S */ P2Align, offset64_op, /* SUB_F16x8 */ V128, V128, V128, /* SUB_F16x8_S */ /* SUB_F32 */ F32, F32, F32, /* SUB_F32_S */ /* SUB_F32x4 */ V128, V128, V128, /* SUB_F32x4_S */ /* SUB_F64 */ F64, F64, F64, /* SUB_F64_S */ /* SUB_F64x2 */ V128, V128, V128, /* SUB_F64x2_S */ /* SUB_I16x8 */ V128, V128, V128, /* SUB_I16x8_S */ /* SUB_I32 */ I32, I32, I32, /* SUB_I32_S */ /* SUB_I32x4 */ V128, V128, V128, /* SUB_I32x4_S */ /* SUB_I64 */ I64, I64, I64, /* SUB_I64_S */ /* SUB_I64x2 */ V128, V128, V128, /* SUB_I64x2_S */ /* SUB_I8x16 */ V128, V128, V128, /* SUB_I8x16_S */ /* SUB_SAT_S_I16x8 */ V128, V128, V128, /* SUB_SAT_S_I16x8_S */ /* SUB_SAT_S_I8x16 */ V128, V128, V128, /* SUB_SAT_S_I8x16_S */ /* SUB_SAT_U_I16x8 */ V128, V128, V128, /* SUB_SAT_U_I16x8_S */ /* SUB_SAT_U_I8x16 */ V128, V128, V128, /* SUB_SAT_U_I8x16_S */ /* SWIZZLE */ V128, V128, V128, /* SWIZZLE_S */ /* TABLE_COPY */ table32_op, table32_op, I32, I32, I32, /* TABLE_COPY_S */ table32_op, table32_op, /* TABLE_FILL_EXNREF */ table32_op, I32, EXNREF, I32, /* TABLE_FILL_EXNREF_S */ table32_op, /* TABLE_FILL_EXTERNREF */ table32_op, I32, EXTERNREF, I32, /* TABLE_FILL_EXTERNREF_S */ table32_op, /* TABLE_FILL_FUNCREF */ table32_op, I32, FUNCREF, I32, /* TABLE_FILL_FUNCREF_S */ table32_op, /* TABLE_GET_EXNREF */ EXNREF, table32_op, I32, /* TABLE_GET_EXNREF_S */ table32_op, /* TABLE_GET_EXTERNREF */ EXTERNREF, table32_op, I32, /* TABLE_GET_EXTERNREF_S */ table32_op, /* TABLE_GET_FUNCREF */ FUNCREF, table32_op, I32, /* TABLE_GET_FUNCREF_S */ table32_op, /* TABLE_GROW_EXNREF */ I32, table32_op, EXNREF, I32, /* TABLE_GROW_EXNREF_S */ table32_op, /* TABLE_GROW_EXTERNREF */ I32, table32_op, EXTERNREF, I32, /* TABLE_GROW_EXTERNREF_S */ table32_op, /* TABLE_GROW_FUNCREF */ I32, table32_op, FUNCREF, I32, /* TABLE_GROW_FUNCREF_S */ table32_op, /* TABLE_SET_EXNREF */ table32_op, I32, EXNREF, /* TABLE_SET_EXNREF_S */ table32_op, /* TABLE_SET_EXTERNREF */ table32_op, I32, EXTERNREF, /* TABLE_SET_EXTERNREF_S */ table32_op, /* TABLE_SET_FUNCREF */ table32_op, I32, FUNCREF, /* TABLE_SET_FUNCREF_S */ table32_op, /* TABLE_SIZE */ I32, table32_op, /* TABLE_SIZE_S */ table32_op, /* TEE_EXNREF */ EXNREF, EXNREF, EXNREF, /* TEE_EXNREF_S */ /* TEE_EXTERNREF */ EXTERNREF, EXTERNREF, EXTERNREF, /* TEE_EXTERNREF_S */ /* TEE_F32 */ F32, F32, F32, /* TEE_F32_S */ /* TEE_F64 */ F64, F64, F64, /* TEE_F64_S */ /* TEE_FUNCREF */ FUNCREF, FUNCREF, FUNCREF, /* TEE_FUNCREF_S */ /* TEE_I32 */ I32, I32, I32, /* TEE_I32_S */ /* TEE_I64 */ I64, I64, I64, /* TEE_I64_S */ /* TEE_V128 */ V128, V128, V128, /* TEE_V128_S */ /* THROW */ tag_op, /* THROW_S */ tag_op, /* TRUNC_F16x8 */ V128, V128, /* TRUNC_F16x8_S */ /* TRUNC_F32 */ F32, F32, /* TRUNC_F32_S */ /* TRUNC_F32x4 */ V128, V128, /* TRUNC_F32x4_S */ /* TRUNC_F64 */ F64, F64, /* TRUNC_F64_S */ /* TRUNC_F64x2 */ V128, V128, /* TRUNC_F64x2_S */ /* TRY */ Signature, /* TRY_S */ Signature, /* UNREACHABLE */ /* UNREACHABLE_S */ /* XOR */ V128, V128, V128, /* XOR_I32 */ I32, I32, I32, /* XOR_I32_S */ /* XOR_I64 */ I64, I64, I64, /* XOR_I64_S */ /* XOR_S */ /* anonymous_8166MEMORY_GROW_A32 */ I32, i32imm, I32, /* anonymous_8166MEMORY_GROW_A32_S */ i32imm, /* anonymous_8166MEMORY_SIZE_A32 */ I32, i32imm, /* anonymous_8166MEMORY_SIZE_A32_S */ i32imm, /* anonymous_8167MEMORY_GROW_A64 */ I64, i32imm, I64, /* anonymous_8167MEMORY_GROW_A64_S */ i32imm, /* anonymous_8167MEMORY_SIZE_A64 */ I64, i32imm, /* anonymous_8167MEMORY_SIZE_A64_S */ i32imm, /* anonymous_8883DATA_DROP */ i32imm_op, /* anonymous_8883DATA_DROP_S */ i32imm_op, /* anonymous_8883MEMORY_COPY_A32 */ i32imm_op, i32imm_op, I32, I32, I32, /* anonymous_8883MEMORY_COPY_A32_S */ i32imm_op, i32imm_op, /* anonymous_8883MEMORY_FILL_A32 */ i32imm_op, I32, I32, I32, /* anonymous_8883MEMORY_FILL_A32_S */ i32imm_op, /* anonymous_8883MEMORY_INIT_A32 */ i32imm_op, i32imm_op, I32, I32, I32, /* anonymous_8883MEMORY_INIT_A32_S */ i32imm_op, i32imm_op, /* anonymous_8884DATA_DROP */ i32imm_op, /* anonymous_8884DATA_DROP_S */ i32imm_op, /* anonymous_8884MEMORY_COPY_A64 */ i32imm_op, i32imm_op, I64, I64, I64, /* anonymous_8884MEMORY_COPY_A64_S */ i32imm_op, i32imm_op, /* anonymous_8884MEMORY_FILL_A64 */ i32imm_op, I64, I32, I64, /* anonymous_8884MEMORY_FILL_A64_S */ i32imm_op, /* anonymous_8884MEMORY_INIT_A64 */ i32imm_op, i32imm_op, I64, I32, I32, /* anonymous_8884MEMORY_INIT_A64_S */ i32imm_op, i32imm_op, /* convert_low_s_F64x2 */ V128, V128, /* convert_low_s_F64x2_S */ /* convert_low_u_F64x2 */ V128, V128, /* convert_low_u_F64x2_S */ /* demote_zero_F32x4 */ V128, V128, /* demote_zero_F32x4_S */ /* extend_high_s_I16x8 */ V128, V128, /* extend_high_s_I16x8_S */ /* extend_high_s_I32x4 */ V128, V128, /* extend_high_s_I32x4_S */ /* extend_high_s_I64x2 */ V128, V128, /* extend_high_s_I64x2_S */ /* extend_high_u_I16x8 */ V128, V128, /* extend_high_u_I16x8_S */ /* extend_high_u_I32x4 */ V128, V128, /* extend_high_u_I32x4_S */ /* extend_high_u_I64x2 */ V128, V128, /* extend_high_u_I64x2_S */ /* extend_low_s_I16x8 */ V128, V128, /* extend_low_s_I16x8_S */ /* extend_low_s_I32x4 */ V128, V128, /* extend_low_s_I32x4_S */ /* extend_low_s_I64x2 */ V128, V128, /* extend_low_s_I64x2_S */ /* extend_low_u_I16x8 */ V128, V128, /* extend_low_u_I16x8_S */ /* extend_low_u_I32x4 */ V128, V128, /* extend_low_u_I32x4_S */ /* extend_low_u_I64x2 */ V128, V128, /* extend_low_u_I64x2_S */ /* fp_to_sint_I16x8 */ V128, V128, /* fp_to_sint_I16x8_S */ /* fp_to_sint_I32x4 */ V128, V128, /* fp_to_sint_I32x4_S */ /* fp_to_uint_I16x8 */ V128, V128, /* fp_to_uint_I16x8_S */ /* fp_to_uint_I32x4 */ V128, V128, /* fp_to_uint_I32x4_S */ /* int_wasm_extadd_pairwise_signed_I16x8 */ V128, V128, /* int_wasm_extadd_pairwise_signed_I16x8_S */ /* int_wasm_extadd_pairwise_signed_I32x4 */ V128, V128, /* int_wasm_extadd_pairwise_signed_I32x4_S */ /* int_wasm_extadd_pairwise_unsigned_I16x8 */ V128, V128, /* int_wasm_extadd_pairwise_unsigned_I16x8_S */ /* int_wasm_extadd_pairwise_unsigned_I32x4 */ V128, V128, /* int_wasm_extadd_pairwise_unsigned_I32x4_S */ /* int_wasm_relaxed_trunc_signed_I32x4 */ V128, V128, /* int_wasm_relaxed_trunc_signed_I32x4_S */ /* int_wasm_relaxed_trunc_signed_zero_I32x4 */ V128, V128, /* int_wasm_relaxed_trunc_signed_zero_I32x4_S */ /* int_wasm_relaxed_trunc_unsigned_I32x4 */ V128, V128, /* int_wasm_relaxed_trunc_unsigned_I32x4_S */ /* int_wasm_relaxed_trunc_unsigned_zero_I32x4 */ V128, V128, /* int_wasm_relaxed_trunc_unsigned_zero_I32x4_S */ /* promote_low_F64x2 */ V128, V128, /* promote_low_F64x2_S */ /* sint_to_fp_F16x8 */ V128, V128, /* sint_to_fp_F16x8_S */ /* sint_to_fp_F32x4 */ V128, V128, /* sint_to_fp_F32x4_S */ /* trunc_sat_zero_s_I32x4 */ V128, V128, /* trunc_sat_zero_s_I32x4_S */ /* trunc_sat_zero_u_I32x4 */ V128, V128, /* trunc_sat_zero_u_I32x4_S */ /* uint_to_fp_F16x8 */ V128, V128, /* uint_to_fp_F16x8_S */ /* uint_to_fp_F32x4 */ V128, V128, }; return OpcodeOperandTypes[Offsets[Opcode] + OpIdx]; } } // end namespace WebAssembly } // end namespace llvm #endif // GET_INSTRINFO_OPERAND_TYPE #ifdef GET_INSTRINFO_MEM_OPERAND_SIZE #undef GET_INSTRINFO_MEM_OPERAND_SIZE namespace llvm { namespace WebAssembly { LLVM_READONLY static int getMemOperandSize(int OpType) { switch (OpType) { default: return 0; } } } // end namespace WebAssembly } // end namespace llvm #endif // GET_INSTRINFO_MEM_OPERAND_SIZE #ifdef GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP #undef GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP namespace llvm { namespace WebAssembly { LLVM_READONLY static unsigned getLogicalOperandSize(uint16_t Opcode, uint16_t LogicalOpIdx) { return LogicalOpIdx; } LLVM_READONLY static inline unsigned getLogicalOperandIdx(uint16_t Opcode, uint16_t LogicalOpIdx) { auto S = 0U; for (auto i = 0U; i < LogicalOpIdx; ++i) S += getLogicalOperandSize(Opcode, i); return S; } } // end namespace WebAssembly } // end namespace llvm #endif // GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP #ifdef GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP #undef GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP namespace llvm { namespace WebAssembly { LLVM_READONLY static int getLogicalOperandType(uint16_t Opcode, uint16_t LogicalOpIdx) { return -1; } } // end namespace WebAssembly } // end namespace llvm #endif // GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP #ifdef GET_INSTRINFO_MC_HELPER_DECLS #undef GET_INSTRINFO_MC_HELPER_DECLS namespace llvm { class MCInst; class FeatureBitset; namespace WebAssembly_MC { void verifyInstructionPredicates(unsigned Opcode, const FeatureBitset &Features); } // end namespace WebAssembly_MC } // end namespace llvm #endif // GET_INSTRINFO_MC_HELPER_DECLS #ifdef GET_INSTRINFO_MC_HELPERS #undef GET_INSTRINFO_MC_HELPERS namespace llvm { namespace WebAssembly_MC { } // end namespace WebAssembly_MC } // end namespace llvm #endif // GET_GENISTRINFO_MC_HELPERS #if (defined(ENABLE_INSTR_PREDICATE_VERIFIER) && !defined(NDEBUG)) ||\ defined(GET_AVAILABLE_OPCODE_CHECKER) #define GET_COMPUTE_FEATURES #endif #ifdef GET_COMPUTE_FEATURES #undef GET_COMPUTE_FEATURES namespace llvm { namespace WebAssembly_MC { // Bits for subtarget features that participate in instruction matching. enum SubtargetFeatureBits : uint8_t { Feature_HasAtomicsBit = 0, Feature_HasBulkMemoryBit = 1, Feature_HasExceptionHandlingBit = 2, Feature_HasExtendedConstBit = 3, Feature_HasFP16Bit = 4, Feature_HasMultiMemoryBit = 5, Feature_HasMultivalueBit = 6, Feature_HasMutableGlobalsBit = 7, Feature_HasNontrappingFPToIntBit = 8, Feature_NotHasNontrappingFPToIntBit = 14, Feature_HasReferenceTypesBit = 9, Feature_HasRelaxedSIMDBit = 10, Feature_HasSignExtBit = 12, Feature_HasSIMD128Bit = 11, Feature_HasTailCallBit = 13, }; inline FeatureBitset computeAvailableFeatures(const FeatureBitset &FB) { FeatureBitset Features; if (FB[WebAssembly::FeatureAtomics]) Features.set(Feature_HasAtomicsBit); if (FB[WebAssembly::FeatureBulkMemory]) Features.set(Feature_HasBulkMemoryBit); if (FB[WebAssembly::FeatureExceptionHandling]) Features.set(Feature_HasExceptionHandlingBit); if (FB[WebAssembly::FeatureExtendedConst]) Features.set(Feature_HasExtendedConstBit); if (FB[WebAssembly::FeatureFP16]) Features.set(Feature_HasFP16Bit); if (FB[WebAssembly::FeatureMultiMemory]) Features.set(Feature_HasMultiMemoryBit); if (FB[WebAssembly::FeatureMultivalue]) Features.set(Feature_HasMultivalueBit); if (FB[WebAssembly::FeatureMutableGlobals]) Features.set(Feature_HasMutableGlobalsBit); if (FB[WebAssembly::FeatureNontrappingFPToInt]) Features.set(Feature_HasNontrappingFPToIntBit); if (!FB[WebAssembly::FeatureNontrappingFPToInt]) Features.set(Feature_NotHasNontrappingFPToIntBit); if (FB[WebAssembly::FeatureReferenceTypes]) Features.set(Feature_HasReferenceTypesBit); if (FB[WebAssembly::FeatureRelaxedSIMD]) Features.set(Feature_HasRelaxedSIMDBit); if (FB[WebAssembly::FeatureSignExt]) Features.set(Feature_HasSignExtBit); if (FB[WebAssembly::FeatureSIMD128] || FB[WebAssembly::FeatureRelaxedSIMD]) Features.set(Feature_HasSIMD128Bit); if (FB[WebAssembly::FeatureTailCall]) Features.set(Feature_HasTailCallBit); return Features; } inline FeatureBitset computeRequiredFeatures(unsigned Opcode) { enum : uint8_t { CEFBS_None, CEFBS_HasAtomics, CEFBS_HasBulkMemory, CEFBS_HasExceptionHandling, CEFBS_HasFP16, CEFBS_HasNontrappingFPToInt, CEFBS_HasReferenceTypes, CEFBS_HasRelaxedSIMD, CEFBS_HasSIMD128, CEFBS_HasSignExt, CEFBS_HasTailCall, CEFBS_NotHasNontrappingFPToInt, CEFBS_HasReferenceTypes_HasExceptionHandling, CEFBS_HasSIMD128_HasFP16, CEFBS_HasSIMD128_HasRelaxedSIMD, }; static constexpr FeatureBitset FeatureBitsets[] = { {}, // CEFBS_None {Feature_HasAtomicsBit, }, {Feature_HasBulkMemoryBit, }, {Feature_HasExceptionHandlingBit, }, {Feature_HasFP16Bit, }, {Feature_HasNontrappingFPToIntBit, }, {Feature_HasReferenceTypesBit, }, {Feature_HasRelaxedSIMDBit, }, {Feature_HasSIMD128Bit, }, {Feature_HasSignExtBit, }, {Feature_HasTailCallBit, }, {Feature_NotHasNontrappingFPToIntBit, }, {Feature_HasReferenceTypesBit, Feature_HasExceptionHandlingBit, }, {Feature_HasSIMD128Bit, Feature_HasFP16Bit, }, {Feature_HasSIMD128Bit, Feature_HasRelaxedSIMDBit, }, }; static constexpr uint8_t RequiredFeaturesRefs[] = { CEFBS_None, // PHI = 0 CEFBS_None, // INLINEASM = 1 CEFBS_None, // INLINEASM_BR = 2 CEFBS_None, // CFI_INSTRUCTION = 3 CEFBS_None, // EH_LABEL = 4 CEFBS_None, // GC_LABEL = 5 CEFBS_None, // ANNOTATION_LABEL = 6 CEFBS_None, // KILL = 7 CEFBS_None, // EXTRACT_SUBREG = 8 CEFBS_None, // INSERT_SUBREG = 9 CEFBS_None, // IMPLICIT_DEF = 10 CEFBS_None, // SUBREG_TO_REG = 11 CEFBS_None, // COPY_TO_REGCLASS = 12 CEFBS_None, // DBG_VALUE = 13 CEFBS_None, // DBG_VALUE_LIST = 14 CEFBS_None, // DBG_INSTR_REF = 15 CEFBS_None, // DBG_PHI = 16 CEFBS_None, // DBG_LABEL = 17 CEFBS_None, // REG_SEQUENCE = 18 CEFBS_None, // COPY = 19 CEFBS_None, // BUNDLE = 20 CEFBS_None, // LIFETIME_START = 21 CEFBS_None, // LIFETIME_END = 22 CEFBS_None, // PSEUDO_PROBE = 23 CEFBS_None, // ARITH_FENCE = 24 CEFBS_None, // STACKMAP = 25 CEFBS_None, // FENTRY_CALL = 26 CEFBS_None, // PATCHPOINT = 27 CEFBS_None, // LOAD_STACK_GUARD = 28 CEFBS_None, // PREALLOCATED_SETUP = 29 CEFBS_None, // PREALLOCATED_ARG = 30 CEFBS_None, // STATEPOINT = 31 CEFBS_None, // LOCAL_ESCAPE = 32 CEFBS_None, // FAULTING_OP = 33 CEFBS_None, // PATCHABLE_OP = 34 CEFBS_None, // PATCHABLE_FUNCTION_ENTER = 35 CEFBS_None, // PATCHABLE_RET = 36 CEFBS_None, // PATCHABLE_FUNCTION_EXIT = 37 CEFBS_None, // PATCHABLE_TAIL_CALL = 38 CEFBS_None, // PATCHABLE_EVENT_CALL = 39 CEFBS_None, // PATCHABLE_TYPED_EVENT_CALL = 40 CEFBS_None, // ICALL_BRANCH_FUNNEL = 41 CEFBS_None, // FAKE_USE = 42 CEFBS_None, // MEMBARRIER = 43 CEFBS_None, // JUMP_TABLE_DEBUG_INFO = 44 CEFBS_None, // CONVERGENCECTRL_ENTRY = 45 CEFBS_None, // CONVERGENCECTRL_ANCHOR = 46 CEFBS_None, // CONVERGENCECTRL_LOOP = 47 CEFBS_None, // CONVERGENCECTRL_GLUE = 48 CEFBS_None, // G_ASSERT_SEXT = 49 CEFBS_None, // G_ASSERT_ZEXT = 50 CEFBS_None, // G_ASSERT_ALIGN = 51 CEFBS_None, // G_ADD = 52 CEFBS_None, // G_SUB = 53 CEFBS_None, // G_MUL = 54 CEFBS_None, // G_SDIV = 55 CEFBS_None, // G_UDIV = 56 CEFBS_None, // G_SREM = 57 CEFBS_None, // G_UREM = 58 CEFBS_None, // G_SDIVREM = 59 CEFBS_None, // G_UDIVREM = 60 CEFBS_None, // G_AND = 61 CEFBS_None, // G_OR = 62 CEFBS_None, // G_XOR = 63 CEFBS_None, // G_IMPLICIT_DEF = 64 CEFBS_None, // G_PHI = 65 CEFBS_None, // G_FRAME_INDEX = 66 CEFBS_None, // G_GLOBAL_VALUE = 67 CEFBS_None, // G_PTRAUTH_GLOBAL_VALUE = 68 CEFBS_None, // G_CONSTANT_POOL = 69 CEFBS_None, // G_EXTRACT = 70 CEFBS_None, // G_UNMERGE_VALUES = 71 CEFBS_None, // G_INSERT = 72 CEFBS_None, // G_MERGE_VALUES = 73 CEFBS_None, // G_BUILD_VECTOR = 74 CEFBS_None, // G_BUILD_VECTOR_TRUNC = 75 CEFBS_None, // G_CONCAT_VECTORS = 76 CEFBS_None, // G_PTRTOINT = 77 CEFBS_None, // G_INTTOPTR = 78 CEFBS_None, // G_BITCAST = 79 CEFBS_None, // G_FREEZE = 80 CEFBS_None, // G_CONSTANT_FOLD_BARRIER = 81 CEFBS_None, // G_INTRINSIC_FPTRUNC_ROUND = 82 CEFBS_None, // G_INTRINSIC_TRUNC = 83 CEFBS_None, // G_INTRINSIC_ROUND = 84 CEFBS_None, // G_INTRINSIC_LRINT = 85 CEFBS_None, // G_INTRINSIC_LLRINT = 86 CEFBS_None, // G_INTRINSIC_ROUNDEVEN = 87 CEFBS_None, // G_READCYCLECOUNTER = 88 CEFBS_None, // G_READSTEADYCOUNTER = 89 CEFBS_None, // G_LOAD = 90 CEFBS_None, // G_SEXTLOAD = 91 CEFBS_None, // G_ZEXTLOAD = 92 CEFBS_None, // G_INDEXED_LOAD = 93 CEFBS_None, // G_INDEXED_SEXTLOAD = 94 CEFBS_None, // G_INDEXED_ZEXTLOAD = 95 CEFBS_None, // G_STORE = 96 CEFBS_None, // G_INDEXED_STORE = 97 CEFBS_None, // G_ATOMIC_CMPXCHG_WITH_SUCCESS = 98 CEFBS_None, // G_ATOMIC_CMPXCHG = 99 CEFBS_None, // G_ATOMICRMW_XCHG = 100 CEFBS_None, // G_ATOMICRMW_ADD = 101 CEFBS_None, // G_ATOMICRMW_SUB = 102 CEFBS_None, // G_ATOMICRMW_AND = 103 CEFBS_None, // G_ATOMICRMW_NAND = 104 CEFBS_None, // G_ATOMICRMW_OR = 105 CEFBS_None, // G_ATOMICRMW_XOR = 106 CEFBS_None, // G_ATOMICRMW_MAX = 107 CEFBS_None, // G_ATOMICRMW_MIN = 108 CEFBS_None, // G_ATOMICRMW_UMAX = 109 CEFBS_None, // G_ATOMICRMW_UMIN = 110 CEFBS_None, // G_ATOMICRMW_FADD = 111 CEFBS_None, // G_ATOMICRMW_FSUB = 112 CEFBS_None, // G_ATOMICRMW_FMAX = 113 CEFBS_None, // G_ATOMICRMW_FMIN = 114 CEFBS_None, // G_ATOMICRMW_UINC_WRAP = 115 CEFBS_None, // G_ATOMICRMW_UDEC_WRAP = 116 CEFBS_None, // G_FENCE = 117 CEFBS_None, // G_PREFETCH = 118 CEFBS_None, // G_BRCOND = 119 CEFBS_None, // G_BRINDIRECT = 120 CEFBS_None, // G_INVOKE_REGION_START = 121 CEFBS_None, // G_INTRINSIC = 122 CEFBS_None, // G_INTRINSIC_W_SIDE_EFFECTS = 123 CEFBS_None, // G_INTRINSIC_CONVERGENT = 124 CEFBS_None, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS = 125 CEFBS_None, // G_ANYEXT = 126 CEFBS_None, // G_TRUNC = 127 CEFBS_None, // G_CONSTANT = 128 CEFBS_None, // G_FCONSTANT = 129 CEFBS_None, // G_VASTART = 130 CEFBS_None, // G_VAARG = 131 CEFBS_None, // G_SEXT = 132 CEFBS_None, // G_SEXT_INREG = 133 CEFBS_None, // G_ZEXT = 134 CEFBS_None, // G_SHL = 135 CEFBS_None, // G_LSHR = 136 CEFBS_None, // G_ASHR = 137 CEFBS_None, // G_FSHL = 138 CEFBS_None, // G_FSHR = 139 CEFBS_None, // G_ROTR = 140 CEFBS_None, // G_ROTL = 141 CEFBS_None, // G_ICMP = 142 CEFBS_None, // G_FCMP = 143 CEFBS_None, // G_SCMP = 144 CEFBS_None, // G_UCMP = 145 CEFBS_None, // G_SELECT = 146 CEFBS_None, // G_UADDO = 147 CEFBS_None, // G_UADDE = 148 CEFBS_None, // G_USUBO = 149 CEFBS_None, // G_USUBE = 150 CEFBS_None, // G_SADDO = 151 CEFBS_None, // G_SADDE = 152 CEFBS_None, // G_SSUBO = 153 CEFBS_None, // G_SSUBE = 154 CEFBS_None, // G_UMULO = 155 CEFBS_None, // G_SMULO = 156 CEFBS_None, // G_UMULH = 157 CEFBS_None, // G_SMULH = 158 CEFBS_None, // G_UADDSAT = 159 CEFBS_None, // G_SADDSAT = 160 CEFBS_None, // G_USUBSAT = 161 CEFBS_None, // G_SSUBSAT = 162 CEFBS_None, // G_USHLSAT = 163 CEFBS_None, // G_SSHLSAT = 164 CEFBS_None, // G_SMULFIX = 165 CEFBS_None, // G_UMULFIX = 166 CEFBS_None, // G_SMULFIXSAT = 167 CEFBS_None, // G_UMULFIXSAT = 168 CEFBS_None, // G_SDIVFIX = 169 CEFBS_None, // G_UDIVFIX = 170 CEFBS_None, // G_SDIVFIXSAT = 171 CEFBS_None, // G_UDIVFIXSAT = 172 CEFBS_None, // G_FADD = 173 CEFBS_None, // G_FSUB = 174 CEFBS_None, // G_FMUL = 175 CEFBS_None, // G_FMA = 176 CEFBS_None, // G_FMAD = 177 CEFBS_None, // G_FDIV = 178 CEFBS_None, // G_FREM = 179 CEFBS_None, // G_FPOW = 180 CEFBS_None, // G_FPOWI = 181 CEFBS_None, // G_FEXP = 182 CEFBS_None, // G_FEXP2 = 183 CEFBS_None, // G_FEXP10 = 184 CEFBS_None, // G_FLOG = 185 CEFBS_None, // G_FLOG2 = 186 CEFBS_None, // G_FLOG10 = 187 CEFBS_None, // G_FLDEXP = 188 CEFBS_None, // G_FFREXP = 189 CEFBS_None, // G_FNEG = 190 CEFBS_None, // G_FPEXT = 191 CEFBS_None, // G_FPTRUNC = 192 CEFBS_None, // G_FPTOSI = 193 CEFBS_None, // G_FPTOUI = 194 CEFBS_None, // G_SITOFP = 195 CEFBS_None, // G_UITOFP = 196 CEFBS_None, // G_FABS = 197 CEFBS_None, // G_FCOPYSIGN = 198 CEFBS_None, // G_IS_FPCLASS = 199 CEFBS_None, // G_FCANONICALIZE = 200 CEFBS_None, // G_FMINNUM = 201 CEFBS_None, // G_FMAXNUM = 202 CEFBS_None, // G_FMINNUM_IEEE = 203 CEFBS_None, // G_FMAXNUM_IEEE = 204 CEFBS_None, // G_FMINIMUM = 205 CEFBS_None, // G_FMAXIMUM = 206 CEFBS_None, // G_GET_FPENV = 207 CEFBS_None, // G_SET_FPENV = 208 CEFBS_None, // G_RESET_FPENV = 209 CEFBS_None, // G_GET_FPMODE = 210 CEFBS_None, // G_SET_FPMODE = 211 CEFBS_None, // G_RESET_FPMODE = 212 CEFBS_None, // G_PTR_ADD = 213 CEFBS_None, // G_PTRMASK = 214 CEFBS_None, // G_SMIN = 215 CEFBS_None, // G_SMAX = 216 CEFBS_None, // G_UMIN = 217 CEFBS_None, // G_UMAX = 218 CEFBS_None, // G_ABS = 219 CEFBS_None, // G_LROUND = 220 CEFBS_None, // G_LLROUND = 221 CEFBS_None, // G_BR = 222 CEFBS_None, // G_BRJT = 223 CEFBS_None, // G_VSCALE = 224 CEFBS_None, // G_INSERT_SUBVECTOR = 225 CEFBS_None, // G_EXTRACT_SUBVECTOR = 226 CEFBS_None, // G_INSERT_VECTOR_ELT = 227 CEFBS_None, // G_EXTRACT_VECTOR_ELT = 228 CEFBS_None, // G_SHUFFLE_VECTOR = 229 CEFBS_None, // G_SPLAT_VECTOR = 230 CEFBS_None, // G_VECTOR_COMPRESS = 231 CEFBS_None, // G_CTTZ = 232 CEFBS_None, // G_CTTZ_ZERO_UNDEF = 233 CEFBS_None, // G_CTLZ = 234 CEFBS_None, // G_CTLZ_ZERO_UNDEF = 235 CEFBS_None, // G_CTPOP = 236 CEFBS_None, // G_BSWAP = 237 CEFBS_None, // G_BITREVERSE = 238 CEFBS_None, // G_FCEIL = 239 CEFBS_None, // G_FCOS = 240 CEFBS_None, // G_FSIN = 241 CEFBS_None, // G_FTAN = 242 CEFBS_None, // G_FACOS = 243 CEFBS_None, // G_FASIN = 244 CEFBS_None, // G_FATAN = 245 CEFBS_None, // G_FCOSH = 246 CEFBS_None, // G_FSINH = 247 CEFBS_None, // G_FTANH = 248 CEFBS_None, // G_FSQRT = 249 CEFBS_None, // G_FFLOOR = 250 CEFBS_None, // G_FRINT = 251 CEFBS_None, // G_FNEARBYINT = 252 CEFBS_None, // G_ADDRSPACE_CAST = 253 CEFBS_None, // G_BLOCK_ADDR = 254 CEFBS_None, // G_JUMP_TABLE = 255 CEFBS_None, // G_DYN_STACKALLOC = 256 CEFBS_None, // G_STACKSAVE = 257 CEFBS_None, // G_STACKRESTORE = 258 CEFBS_None, // G_STRICT_FADD = 259 CEFBS_None, // G_STRICT_FSUB = 260 CEFBS_None, // G_STRICT_FMUL = 261 CEFBS_None, // G_STRICT_FDIV = 262 CEFBS_None, // G_STRICT_FREM = 263 CEFBS_None, // G_STRICT_FMA = 264 CEFBS_None, // G_STRICT_FSQRT = 265 CEFBS_None, // G_STRICT_FLDEXP = 266 CEFBS_None, // G_READ_REGISTER = 267 CEFBS_None, // G_WRITE_REGISTER = 268 CEFBS_None, // G_MEMCPY = 269 CEFBS_None, // G_MEMCPY_INLINE = 270 CEFBS_None, // G_MEMMOVE = 271 CEFBS_None, // G_MEMSET = 272 CEFBS_None, // G_BZERO = 273 CEFBS_None, // G_TRAP = 274 CEFBS_None, // G_DEBUGTRAP = 275 CEFBS_None, // G_UBSANTRAP = 276 CEFBS_None, // G_VECREDUCE_SEQ_FADD = 277 CEFBS_None, // G_VECREDUCE_SEQ_FMUL = 278 CEFBS_None, // G_VECREDUCE_FADD = 279 CEFBS_None, // G_VECREDUCE_FMUL = 280 CEFBS_None, // G_VECREDUCE_FMAX = 281 CEFBS_None, // G_VECREDUCE_FMIN = 282 CEFBS_None, // G_VECREDUCE_FMAXIMUM = 283 CEFBS_None, // G_VECREDUCE_FMINIMUM = 284 CEFBS_None, // G_VECREDUCE_ADD = 285 CEFBS_None, // G_VECREDUCE_MUL = 286 CEFBS_None, // G_VECREDUCE_AND = 287 CEFBS_None, // G_VECREDUCE_OR = 288 CEFBS_None, // G_VECREDUCE_XOR = 289 CEFBS_None, // G_VECREDUCE_SMAX = 290 CEFBS_None, // G_VECREDUCE_SMIN = 291 CEFBS_None, // G_VECREDUCE_UMAX = 292 CEFBS_None, // G_VECREDUCE_UMIN = 293 CEFBS_None, // G_SBFX = 294 CEFBS_None, // G_UBFX = 295 CEFBS_None, // CALL_PARAMS = 296 CEFBS_None, // CALL_PARAMS_S = 297 CEFBS_None, // CALL_RESULTS = 298 CEFBS_None, // CALL_RESULTS_S = 299 CEFBS_HasExceptionHandling, // CATCHRET = 300 CEFBS_HasExceptionHandling, // CATCHRET_S = 301 CEFBS_HasExceptionHandling, // CLEANUPRET = 302 CEFBS_HasExceptionHandling, // CLEANUPRET_S = 303 CEFBS_HasAtomics, // COMPILER_FENCE = 304 CEFBS_HasAtomics, // COMPILER_FENCE_S = 305 CEFBS_None, // RET_CALL_RESULTS = 306 CEFBS_None, // RET_CALL_RESULTS_S = 307 CEFBS_HasSIMD128_HasFP16, // ABS_F16x8 = 308 CEFBS_HasSIMD128_HasFP16, // ABS_F16x8_S = 309 CEFBS_None, // ABS_F32 = 310 CEFBS_None, // ABS_F32_S = 311 CEFBS_HasSIMD128, // ABS_F32x4 = 312 CEFBS_HasSIMD128, // ABS_F32x4_S = 313 CEFBS_None, // ABS_F64 = 314 CEFBS_None, // ABS_F64_S = 315 CEFBS_HasSIMD128, // ABS_F64x2 = 316 CEFBS_HasSIMD128, // ABS_F64x2_S = 317 CEFBS_HasSIMD128, // ABS_I16x8 = 318 CEFBS_HasSIMD128, // ABS_I16x8_S = 319 CEFBS_HasSIMD128, // ABS_I32x4 = 320 CEFBS_HasSIMD128, // ABS_I32x4_S = 321 CEFBS_HasSIMD128, // ABS_I64x2 = 322 CEFBS_HasSIMD128, // ABS_I64x2_S = 323 CEFBS_HasSIMD128, // ABS_I8x16 = 324 CEFBS_HasSIMD128, // ABS_I8x16_S = 325 CEFBS_HasSIMD128_HasFP16, // ADD_F16x8 = 326 CEFBS_HasSIMD128_HasFP16, // ADD_F16x8_S = 327 CEFBS_None, // ADD_F32 = 328 CEFBS_None, // ADD_F32_S = 329 CEFBS_HasSIMD128, // ADD_F32x4 = 330 CEFBS_HasSIMD128, // ADD_F32x4_S = 331 CEFBS_None, // ADD_F64 = 332 CEFBS_None, // ADD_F64_S = 333 CEFBS_HasSIMD128, // ADD_F64x2 = 334 CEFBS_HasSIMD128, // ADD_F64x2_S = 335 CEFBS_HasSIMD128, // ADD_I16x8 = 336 CEFBS_HasSIMD128, // ADD_I16x8_S = 337 CEFBS_None, // ADD_I32 = 338 CEFBS_None, // ADD_I32_S = 339 CEFBS_HasSIMD128, // ADD_I32x4 = 340 CEFBS_HasSIMD128, // ADD_I32x4_S = 341 CEFBS_None, // ADD_I64 = 342 CEFBS_None, // ADD_I64_S = 343 CEFBS_HasSIMD128, // ADD_I64x2 = 344 CEFBS_HasSIMD128, // ADD_I64x2_S = 345 CEFBS_HasSIMD128, // ADD_I8x16 = 346 CEFBS_HasSIMD128, // ADD_I8x16_S = 347 CEFBS_HasSIMD128, // ADD_SAT_S_I16x8 = 348 CEFBS_HasSIMD128, // ADD_SAT_S_I16x8_S = 349 CEFBS_HasSIMD128, // ADD_SAT_S_I8x16 = 350 CEFBS_HasSIMD128, // ADD_SAT_S_I8x16_S = 351 CEFBS_HasSIMD128, // ADD_SAT_U_I16x8 = 352 CEFBS_HasSIMD128, // ADD_SAT_U_I16x8_S = 353 CEFBS_HasSIMD128, // ADD_SAT_U_I8x16 = 354 CEFBS_HasSIMD128, // ADD_SAT_U_I8x16_S = 355 CEFBS_None, // ADJCALLSTACKDOWN = 356 CEFBS_None, // ADJCALLSTACKDOWN_S = 357 CEFBS_None, // ADJCALLSTACKUP = 358 CEFBS_None, // ADJCALLSTACKUP_S = 359 CEFBS_HasSIMD128, // ALLTRUE_I16x8 = 360 CEFBS_HasSIMD128, // ALLTRUE_I16x8_S = 361 CEFBS_HasSIMD128, // ALLTRUE_I32x4 = 362 CEFBS_HasSIMD128, // ALLTRUE_I32x4_S = 363 CEFBS_HasSIMD128, // ALLTRUE_I64x2 = 364 CEFBS_HasSIMD128, // ALLTRUE_I64x2_S = 365 CEFBS_HasSIMD128, // ALLTRUE_I8x16 = 366 CEFBS_HasSIMD128, // ALLTRUE_I8x16_S = 367 CEFBS_HasSIMD128, // AND = 368 CEFBS_HasSIMD128, // ANDNOT = 369 CEFBS_HasSIMD128, // ANDNOT_S = 370 CEFBS_None, // AND_I32 = 371 CEFBS_None, // AND_I32_S = 372 CEFBS_None, // AND_I64 = 373 CEFBS_None, // AND_I64_S = 374 CEFBS_HasSIMD128, // AND_S = 375 CEFBS_HasSIMD128, // ANYTRUE = 376 CEFBS_HasSIMD128, // ANYTRUE_S = 377 CEFBS_None, // ARGUMENT_exnref = 378 CEFBS_None, // ARGUMENT_exnref_S = 379 CEFBS_None, // ARGUMENT_externref = 380 CEFBS_None, // ARGUMENT_externref_S = 381 CEFBS_None, // ARGUMENT_f32 = 382 CEFBS_None, // ARGUMENT_f32_S = 383 CEFBS_None, // ARGUMENT_f64 = 384 CEFBS_None, // ARGUMENT_f64_S = 385 CEFBS_None, // ARGUMENT_funcref = 386 CEFBS_None, // ARGUMENT_funcref_S = 387 CEFBS_None, // ARGUMENT_i32 = 388 CEFBS_None, // ARGUMENT_i32_S = 389 CEFBS_None, // ARGUMENT_i64 = 390 CEFBS_None, // ARGUMENT_i64_S = 391 CEFBS_None, // ARGUMENT_v16i8 = 392 CEFBS_None, // ARGUMENT_v16i8_S = 393 CEFBS_None, // ARGUMENT_v2f64 = 394 CEFBS_None, // ARGUMENT_v2f64_S = 395 CEFBS_None, // ARGUMENT_v2i64 = 396 CEFBS_None, // ARGUMENT_v2i64_S = 397 CEFBS_None, // ARGUMENT_v4f32 = 398 CEFBS_None, // ARGUMENT_v4f32_S = 399 CEFBS_None, // ARGUMENT_v4i32 = 400 CEFBS_None, // ARGUMENT_v4i32_S = 401 CEFBS_None, // ARGUMENT_v8f16 = 402 CEFBS_None, // ARGUMENT_v8f16_S = 403 CEFBS_None, // ARGUMENT_v8i16 = 404 CEFBS_None, // ARGUMENT_v8i16_S = 405 CEFBS_HasAtomics, // ATOMIC_FENCE = 406 CEFBS_HasAtomics, // ATOMIC_FENCE_S = 407 CEFBS_HasAtomics, // ATOMIC_LOAD16_U_I32_A32 = 408 CEFBS_HasAtomics, // ATOMIC_LOAD16_U_I32_A32_S = 409 CEFBS_HasAtomics, // ATOMIC_LOAD16_U_I32_A64 = 410 CEFBS_HasAtomics, // ATOMIC_LOAD16_U_I32_A64_S = 411 CEFBS_HasAtomics, // ATOMIC_LOAD16_U_I64_A32 = 412 CEFBS_HasAtomics, // ATOMIC_LOAD16_U_I64_A32_S = 413 CEFBS_HasAtomics, // ATOMIC_LOAD16_U_I64_A64 = 414 CEFBS_HasAtomics, // ATOMIC_LOAD16_U_I64_A64_S = 415 CEFBS_HasAtomics, // ATOMIC_LOAD32_U_I64_A32 = 416 CEFBS_HasAtomics, // ATOMIC_LOAD32_U_I64_A32_S = 417 CEFBS_HasAtomics, // ATOMIC_LOAD32_U_I64_A64 = 418 CEFBS_HasAtomics, // ATOMIC_LOAD32_U_I64_A64_S = 419 CEFBS_HasAtomics, // ATOMIC_LOAD8_U_I32_A32 = 420 CEFBS_HasAtomics, // ATOMIC_LOAD8_U_I32_A32_S = 421 CEFBS_HasAtomics, // ATOMIC_LOAD8_U_I32_A64 = 422 CEFBS_HasAtomics, // ATOMIC_LOAD8_U_I32_A64_S = 423 CEFBS_HasAtomics, // ATOMIC_LOAD8_U_I64_A32 = 424 CEFBS_HasAtomics, // ATOMIC_LOAD8_U_I64_A32_S = 425 CEFBS_HasAtomics, // ATOMIC_LOAD8_U_I64_A64 = 426 CEFBS_HasAtomics, // ATOMIC_LOAD8_U_I64_A64_S = 427 CEFBS_HasAtomics, // ATOMIC_LOAD_I32_A32 = 428 CEFBS_HasAtomics, // ATOMIC_LOAD_I32_A32_S = 429 CEFBS_HasAtomics, // ATOMIC_LOAD_I32_A64 = 430 CEFBS_HasAtomics, // ATOMIC_LOAD_I32_A64_S = 431 CEFBS_HasAtomics, // ATOMIC_LOAD_I64_A32 = 432 CEFBS_HasAtomics, // ATOMIC_LOAD_I64_A32_S = 433 CEFBS_HasAtomics, // ATOMIC_LOAD_I64_A64 = 434 CEFBS_HasAtomics, // ATOMIC_LOAD_I64_A64_S = 435 CEFBS_HasAtomics, // ATOMIC_RMW16_U_ADD_I32_A32 = 436 CEFBS_HasAtomics, // ATOMIC_RMW16_U_ADD_I32_A32_S = 437 CEFBS_HasAtomics, // ATOMIC_RMW16_U_ADD_I32_A64 = 438 CEFBS_HasAtomics, // ATOMIC_RMW16_U_ADD_I32_A64_S = 439 CEFBS_HasAtomics, // ATOMIC_RMW16_U_ADD_I64_A32 = 440 CEFBS_HasAtomics, // ATOMIC_RMW16_U_ADD_I64_A32_S = 441 CEFBS_HasAtomics, // ATOMIC_RMW16_U_ADD_I64_A64 = 442 CEFBS_HasAtomics, // ATOMIC_RMW16_U_ADD_I64_A64_S = 443 CEFBS_HasAtomics, // ATOMIC_RMW16_U_AND_I32_A32 = 444 CEFBS_HasAtomics, // ATOMIC_RMW16_U_AND_I32_A32_S = 445 CEFBS_HasAtomics, // ATOMIC_RMW16_U_AND_I32_A64 = 446 CEFBS_HasAtomics, // ATOMIC_RMW16_U_AND_I32_A64_S = 447 CEFBS_HasAtomics, // ATOMIC_RMW16_U_AND_I64_A32 = 448 CEFBS_HasAtomics, // ATOMIC_RMW16_U_AND_I64_A32_S = 449 CEFBS_HasAtomics, // ATOMIC_RMW16_U_AND_I64_A64 = 450 CEFBS_HasAtomics, // ATOMIC_RMW16_U_AND_I64_A64_S = 451 CEFBS_HasAtomics, // ATOMIC_RMW16_U_CMPXCHG_I32_A32 = 452 CEFBS_HasAtomics, // ATOMIC_RMW16_U_CMPXCHG_I32_A32_S = 453 CEFBS_HasAtomics, // ATOMIC_RMW16_U_CMPXCHG_I32_A64 = 454 CEFBS_HasAtomics, // ATOMIC_RMW16_U_CMPXCHG_I32_A64_S = 455 CEFBS_HasAtomics, // ATOMIC_RMW16_U_CMPXCHG_I64_A32 = 456 CEFBS_HasAtomics, // ATOMIC_RMW16_U_CMPXCHG_I64_A32_S = 457 CEFBS_HasAtomics, // ATOMIC_RMW16_U_CMPXCHG_I64_A64 = 458 CEFBS_HasAtomics, // ATOMIC_RMW16_U_CMPXCHG_I64_A64_S = 459 CEFBS_HasAtomics, // ATOMIC_RMW16_U_OR_I32_A32 = 460 CEFBS_HasAtomics, // ATOMIC_RMW16_U_OR_I32_A32_S = 461 CEFBS_HasAtomics, // ATOMIC_RMW16_U_OR_I32_A64 = 462 CEFBS_HasAtomics, // ATOMIC_RMW16_U_OR_I32_A64_S = 463 CEFBS_HasAtomics, // ATOMIC_RMW16_U_OR_I64_A32 = 464 CEFBS_HasAtomics, // ATOMIC_RMW16_U_OR_I64_A32_S = 465 CEFBS_HasAtomics, // ATOMIC_RMW16_U_OR_I64_A64 = 466 CEFBS_HasAtomics, // ATOMIC_RMW16_U_OR_I64_A64_S = 467 CEFBS_HasAtomics, // ATOMIC_RMW16_U_SUB_I32_A32 = 468 CEFBS_HasAtomics, // ATOMIC_RMW16_U_SUB_I32_A32_S = 469 CEFBS_HasAtomics, // ATOMIC_RMW16_U_SUB_I32_A64 = 470 CEFBS_HasAtomics, // ATOMIC_RMW16_U_SUB_I32_A64_S = 471 CEFBS_HasAtomics, // ATOMIC_RMW16_U_SUB_I64_A32 = 472 CEFBS_HasAtomics, // ATOMIC_RMW16_U_SUB_I64_A32_S = 473 CEFBS_HasAtomics, // ATOMIC_RMW16_U_SUB_I64_A64 = 474 CEFBS_HasAtomics, // ATOMIC_RMW16_U_SUB_I64_A64_S = 475 CEFBS_HasAtomics, // ATOMIC_RMW16_U_XCHG_I32_A32 = 476 CEFBS_HasAtomics, // ATOMIC_RMW16_U_XCHG_I32_A32_S = 477 CEFBS_HasAtomics, // ATOMIC_RMW16_U_XCHG_I32_A64 = 478 CEFBS_HasAtomics, // ATOMIC_RMW16_U_XCHG_I32_A64_S = 479 CEFBS_HasAtomics, // ATOMIC_RMW16_U_XCHG_I64_A32 = 480 CEFBS_HasAtomics, // ATOMIC_RMW16_U_XCHG_I64_A32_S = 481 CEFBS_HasAtomics, // ATOMIC_RMW16_U_XCHG_I64_A64 = 482 CEFBS_HasAtomics, // ATOMIC_RMW16_U_XCHG_I64_A64_S = 483 CEFBS_HasAtomics, // ATOMIC_RMW16_U_XOR_I32_A32 = 484 CEFBS_HasAtomics, // ATOMIC_RMW16_U_XOR_I32_A32_S = 485 CEFBS_HasAtomics, // ATOMIC_RMW16_U_XOR_I32_A64 = 486 CEFBS_HasAtomics, // ATOMIC_RMW16_U_XOR_I32_A64_S = 487 CEFBS_HasAtomics, // ATOMIC_RMW16_U_XOR_I64_A32 = 488 CEFBS_HasAtomics, // ATOMIC_RMW16_U_XOR_I64_A32_S = 489 CEFBS_HasAtomics, // ATOMIC_RMW16_U_XOR_I64_A64 = 490 CEFBS_HasAtomics, // ATOMIC_RMW16_U_XOR_I64_A64_S = 491 CEFBS_HasAtomics, // ATOMIC_RMW32_U_ADD_I64_A32 = 492 CEFBS_HasAtomics, // ATOMIC_RMW32_U_ADD_I64_A32_S = 493 CEFBS_HasAtomics, // ATOMIC_RMW32_U_ADD_I64_A64 = 494 CEFBS_HasAtomics, // ATOMIC_RMW32_U_ADD_I64_A64_S = 495 CEFBS_HasAtomics, // ATOMIC_RMW32_U_AND_I64_A32 = 496 CEFBS_HasAtomics, // ATOMIC_RMW32_U_AND_I64_A32_S = 497 CEFBS_HasAtomics, // ATOMIC_RMW32_U_AND_I64_A64 = 498 CEFBS_HasAtomics, // ATOMIC_RMW32_U_AND_I64_A64_S = 499 CEFBS_HasAtomics, // ATOMIC_RMW32_U_CMPXCHG_I64_A32 = 500 CEFBS_HasAtomics, // ATOMIC_RMW32_U_CMPXCHG_I64_A32_S = 501 CEFBS_HasAtomics, // ATOMIC_RMW32_U_CMPXCHG_I64_A64 = 502 CEFBS_HasAtomics, // ATOMIC_RMW32_U_CMPXCHG_I64_A64_S = 503 CEFBS_HasAtomics, // ATOMIC_RMW32_U_OR_I64_A32 = 504 CEFBS_HasAtomics, // ATOMIC_RMW32_U_OR_I64_A32_S = 505 CEFBS_HasAtomics, // ATOMIC_RMW32_U_OR_I64_A64 = 506 CEFBS_HasAtomics, // ATOMIC_RMW32_U_OR_I64_A64_S = 507 CEFBS_HasAtomics, // ATOMIC_RMW32_U_SUB_I64_A32 = 508 CEFBS_HasAtomics, // ATOMIC_RMW32_U_SUB_I64_A32_S = 509 CEFBS_HasAtomics, // ATOMIC_RMW32_U_SUB_I64_A64 = 510 CEFBS_HasAtomics, // ATOMIC_RMW32_U_SUB_I64_A64_S = 511 CEFBS_HasAtomics, // ATOMIC_RMW32_U_XCHG_I64_A32 = 512 CEFBS_HasAtomics, // ATOMIC_RMW32_U_XCHG_I64_A32_S = 513 CEFBS_HasAtomics, // ATOMIC_RMW32_U_XCHG_I64_A64 = 514 CEFBS_HasAtomics, // ATOMIC_RMW32_U_XCHG_I64_A64_S = 515 CEFBS_HasAtomics, // ATOMIC_RMW32_U_XOR_I64_A32 = 516 CEFBS_HasAtomics, // ATOMIC_RMW32_U_XOR_I64_A32_S = 517 CEFBS_HasAtomics, // ATOMIC_RMW32_U_XOR_I64_A64 = 518 CEFBS_HasAtomics, // ATOMIC_RMW32_U_XOR_I64_A64_S = 519 CEFBS_HasAtomics, // ATOMIC_RMW8_U_ADD_I32_A32 = 520 CEFBS_HasAtomics, // ATOMIC_RMW8_U_ADD_I32_A32_S = 521 CEFBS_HasAtomics, // ATOMIC_RMW8_U_ADD_I32_A64 = 522 CEFBS_HasAtomics, // ATOMIC_RMW8_U_ADD_I32_A64_S = 523 CEFBS_HasAtomics, // ATOMIC_RMW8_U_ADD_I64_A32 = 524 CEFBS_HasAtomics, // ATOMIC_RMW8_U_ADD_I64_A32_S = 525 CEFBS_HasAtomics, // ATOMIC_RMW8_U_ADD_I64_A64 = 526 CEFBS_HasAtomics, // ATOMIC_RMW8_U_ADD_I64_A64_S = 527 CEFBS_HasAtomics, // ATOMIC_RMW8_U_AND_I32_A32 = 528 CEFBS_HasAtomics, // ATOMIC_RMW8_U_AND_I32_A32_S = 529 CEFBS_HasAtomics, // ATOMIC_RMW8_U_AND_I32_A64 = 530 CEFBS_HasAtomics, // ATOMIC_RMW8_U_AND_I32_A64_S = 531 CEFBS_HasAtomics, // ATOMIC_RMW8_U_AND_I64_A32 = 532 CEFBS_HasAtomics, // ATOMIC_RMW8_U_AND_I64_A32_S = 533 CEFBS_HasAtomics, // ATOMIC_RMW8_U_AND_I64_A64 = 534 CEFBS_HasAtomics, // ATOMIC_RMW8_U_AND_I64_A64_S = 535 CEFBS_HasAtomics, // ATOMIC_RMW8_U_CMPXCHG_I32_A32 = 536 CEFBS_HasAtomics, // ATOMIC_RMW8_U_CMPXCHG_I32_A32_S = 537 CEFBS_HasAtomics, // ATOMIC_RMW8_U_CMPXCHG_I32_A64 = 538 CEFBS_HasAtomics, // ATOMIC_RMW8_U_CMPXCHG_I32_A64_S = 539 CEFBS_HasAtomics, // ATOMIC_RMW8_U_CMPXCHG_I64_A32 = 540 CEFBS_HasAtomics, // ATOMIC_RMW8_U_CMPXCHG_I64_A32_S = 541 CEFBS_HasAtomics, // ATOMIC_RMW8_U_CMPXCHG_I64_A64 = 542 CEFBS_HasAtomics, // ATOMIC_RMW8_U_CMPXCHG_I64_A64_S = 543 CEFBS_HasAtomics, // ATOMIC_RMW8_U_OR_I32_A32 = 544 CEFBS_HasAtomics, // ATOMIC_RMW8_U_OR_I32_A32_S = 545 CEFBS_HasAtomics, // ATOMIC_RMW8_U_OR_I32_A64 = 546 CEFBS_HasAtomics, // ATOMIC_RMW8_U_OR_I32_A64_S = 547 CEFBS_HasAtomics, // ATOMIC_RMW8_U_OR_I64_A32 = 548 CEFBS_HasAtomics, // ATOMIC_RMW8_U_OR_I64_A32_S = 549 CEFBS_HasAtomics, // ATOMIC_RMW8_U_OR_I64_A64 = 550 CEFBS_HasAtomics, // ATOMIC_RMW8_U_OR_I64_A64_S = 551 CEFBS_HasAtomics, // ATOMIC_RMW8_U_SUB_I32_A32 = 552 CEFBS_HasAtomics, // ATOMIC_RMW8_U_SUB_I32_A32_S = 553 CEFBS_HasAtomics, // ATOMIC_RMW8_U_SUB_I32_A64 = 554 CEFBS_HasAtomics, // ATOMIC_RMW8_U_SUB_I32_A64_S = 555 CEFBS_HasAtomics, // ATOMIC_RMW8_U_SUB_I64_A32 = 556 CEFBS_HasAtomics, // ATOMIC_RMW8_U_SUB_I64_A32_S = 557 CEFBS_HasAtomics, // ATOMIC_RMW8_U_SUB_I64_A64 = 558 CEFBS_HasAtomics, // ATOMIC_RMW8_U_SUB_I64_A64_S = 559 CEFBS_HasAtomics, // ATOMIC_RMW8_U_XCHG_I32_A32 = 560 CEFBS_HasAtomics, // ATOMIC_RMW8_U_XCHG_I32_A32_S = 561 CEFBS_HasAtomics, // ATOMIC_RMW8_U_XCHG_I32_A64 = 562 CEFBS_HasAtomics, // ATOMIC_RMW8_U_XCHG_I32_A64_S = 563 CEFBS_HasAtomics, // ATOMIC_RMW8_U_XCHG_I64_A32 = 564 CEFBS_HasAtomics, // ATOMIC_RMW8_U_XCHG_I64_A32_S = 565 CEFBS_HasAtomics, // ATOMIC_RMW8_U_XCHG_I64_A64 = 566 CEFBS_HasAtomics, // ATOMIC_RMW8_U_XCHG_I64_A64_S = 567 CEFBS_HasAtomics, // ATOMIC_RMW8_U_XOR_I32_A32 = 568 CEFBS_HasAtomics, // ATOMIC_RMW8_U_XOR_I32_A32_S = 569 CEFBS_HasAtomics, // ATOMIC_RMW8_U_XOR_I32_A64 = 570 CEFBS_HasAtomics, // ATOMIC_RMW8_U_XOR_I32_A64_S = 571 CEFBS_HasAtomics, // ATOMIC_RMW8_U_XOR_I64_A32 = 572 CEFBS_HasAtomics, // ATOMIC_RMW8_U_XOR_I64_A32_S = 573 CEFBS_HasAtomics, // ATOMIC_RMW8_U_XOR_I64_A64 = 574 CEFBS_HasAtomics, // ATOMIC_RMW8_U_XOR_I64_A64_S = 575 CEFBS_HasAtomics, // ATOMIC_RMW_ADD_I32_A32 = 576 CEFBS_HasAtomics, // ATOMIC_RMW_ADD_I32_A32_S = 577 CEFBS_HasAtomics, // ATOMIC_RMW_ADD_I32_A64 = 578 CEFBS_HasAtomics, // ATOMIC_RMW_ADD_I32_A64_S = 579 CEFBS_HasAtomics, // ATOMIC_RMW_ADD_I64_A32 = 580 CEFBS_HasAtomics, // ATOMIC_RMW_ADD_I64_A32_S = 581 CEFBS_HasAtomics, // ATOMIC_RMW_ADD_I64_A64 = 582 CEFBS_HasAtomics, // ATOMIC_RMW_ADD_I64_A64_S = 583 CEFBS_HasAtomics, // ATOMIC_RMW_AND_I32_A32 = 584 CEFBS_HasAtomics, // ATOMIC_RMW_AND_I32_A32_S = 585 CEFBS_HasAtomics, // ATOMIC_RMW_AND_I32_A64 = 586 CEFBS_HasAtomics, // ATOMIC_RMW_AND_I32_A64_S = 587 CEFBS_HasAtomics, // ATOMIC_RMW_AND_I64_A32 = 588 CEFBS_HasAtomics, // ATOMIC_RMW_AND_I64_A32_S = 589 CEFBS_HasAtomics, // ATOMIC_RMW_AND_I64_A64 = 590 CEFBS_HasAtomics, // ATOMIC_RMW_AND_I64_A64_S = 591 CEFBS_HasAtomics, // ATOMIC_RMW_CMPXCHG_I32_A32 = 592 CEFBS_HasAtomics, // ATOMIC_RMW_CMPXCHG_I32_A32_S = 593 CEFBS_HasAtomics, // ATOMIC_RMW_CMPXCHG_I32_A64 = 594 CEFBS_HasAtomics, // ATOMIC_RMW_CMPXCHG_I32_A64_S = 595 CEFBS_HasAtomics, // ATOMIC_RMW_CMPXCHG_I64_A32 = 596 CEFBS_HasAtomics, // ATOMIC_RMW_CMPXCHG_I64_A32_S = 597 CEFBS_HasAtomics, // ATOMIC_RMW_CMPXCHG_I64_A64 = 598 CEFBS_HasAtomics, // ATOMIC_RMW_CMPXCHG_I64_A64_S = 599 CEFBS_HasAtomics, // ATOMIC_RMW_OR_I32_A32 = 600 CEFBS_HasAtomics, // ATOMIC_RMW_OR_I32_A32_S = 601 CEFBS_HasAtomics, // ATOMIC_RMW_OR_I32_A64 = 602 CEFBS_HasAtomics, // ATOMIC_RMW_OR_I32_A64_S = 603 CEFBS_HasAtomics, // ATOMIC_RMW_OR_I64_A32 = 604 CEFBS_HasAtomics, // ATOMIC_RMW_OR_I64_A32_S = 605 CEFBS_HasAtomics, // ATOMIC_RMW_OR_I64_A64 = 606 CEFBS_HasAtomics, // ATOMIC_RMW_OR_I64_A64_S = 607 CEFBS_HasAtomics, // ATOMIC_RMW_SUB_I32_A32 = 608 CEFBS_HasAtomics, // ATOMIC_RMW_SUB_I32_A32_S = 609 CEFBS_HasAtomics, // ATOMIC_RMW_SUB_I32_A64 = 610 CEFBS_HasAtomics, // ATOMIC_RMW_SUB_I32_A64_S = 611 CEFBS_HasAtomics, // ATOMIC_RMW_SUB_I64_A32 = 612 CEFBS_HasAtomics, // ATOMIC_RMW_SUB_I64_A32_S = 613 CEFBS_HasAtomics, // ATOMIC_RMW_SUB_I64_A64 = 614 CEFBS_HasAtomics, // ATOMIC_RMW_SUB_I64_A64_S = 615 CEFBS_HasAtomics, // ATOMIC_RMW_XCHG_I32_A32 = 616 CEFBS_HasAtomics, // ATOMIC_RMW_XCHG_I32_A32_S = 617 CEFBS_HasAtomics, // ATOMIC_RMW_XCHG_I32_A64 = 618 CEFBS_HasAtomics, // ATOMIC_RMW_XCHG_I32_A64_S = 619 CEFBS_HasAtomics, // ATOMIC_RMW_XCHG_I64_A32 = 620 CEFBS_HasAtomics, // ATOMIC_RMW_XCHG_I64_A32_S = 621 CEFBS_HasAtomics, // ATOMIC_RMW_XCHG_I64_A64 = 622 CEFBS_HasAtomics, // ATOMIC_RMW_XCHG_I64_A64_S = 623 CEFBS_HasAtomics, // ATOMIC_RMW_XOR_I32_A32 = 624 CEFBS_HasAtomics, // ATOMIC_RMW_XOR_I32_A32_S = 625 CEFBS_HasAtomics, // ATOMIC_RMW_XOR_I32_A64 = 626 CEFBS_HasAtomics, // ATOMIC_RMW_XOR_I32_A64_S = 627 CEFBS_HasAtomics, // ATOMIC_RMW_XOR_I64_A32 = 628 CEFBS_HasAtomics, // ATOMIC_RMW_XOR_I64_A32_S = 629 CEFBS_HasAtomics, // ATOMIC_RMW_XOR_I64_A64 = 630 CEFBS_HasAtomics, // ATOMIC_RMW_XOR_I64_A64_S = 631 CEFBS_HasAtomics, // ATOMIC_STORE16_I32_A32 = 632 CEFBS_HasAtomics, // ATOMIC_STORE16_I32_A32_S = 633 CEFBS_HasAtomics, // ATOMIC_STORE16_I32_A64 = 634 CEFBS_HasAtomics, // ATOMIC_STORE16_I32_A64_S = 635 CEFBS_HasAtomics, // ATOMIC_STORE16_I64_A32 = 636 CEFBS_HasAtomics, // ATOMIC_STORE16_I64_A32_S = 637 CEFBS_HasAtomics, // ATOMIC_STORE16_I64_A64 = 638 CEFBS_HasAtomics, // ATOMIC_STORE16_I64_A64_S = 639 CEFBS_HasAtomics, // ATOMIC_STORE32_I64_A32 = 640 CEFBS_HasAtomics, // ATOMIC_STORE32_I64_A32_S = 641 CEFBS_HasAtomics, // ATOMIC_STORE32_I64_A64 = 642 CEFBS_HasAtomics, // ATOMIC_STORE32_I64_A64_S = 643 CEFBS_HasAtomics, // ATOMIC_STORE8_I32_A32 = 644 CEFBS_HasAtomics, // ATOMIC_STORE8_I32_A32_S = 645 CEFBS_HasAtomics, // ATOMIC_STORE8_I32_A64 = 646 CEFBS_HasAtomics, // ATOMIC_STORE8_I32_A64_S = 647 CEFBS_HasAtomics, // ATOMIC_STORE8_I64_A32 = 648 CEFBS_HasAtomics, // ATOMIC_STORE8_I64_A32_S = 649 CEFBS_HasAtomics, // ATOMIC_STORE8_I64_A64 = 650 CEFBS_HasAtomics, // ATOMIC_STORE8_I64_A64_S = 651 CEFBS_HasAtomics, // ATOMIC_STORE_I32_A32 = 652 CEFBS_HasAtomics, // ATOMIC_STORE_I32_A32_S = 653 CEFBS_HasAtomics, // ATOMIC_STORE_I32_A64 = 654 CEFBS_HasAtomics, // ATOMIC_STORE_I32_A64_S = 655 CEFBS_HasAtomics, // ATOMIC_STORE_I64_A32 = 656 CEFBS_HasAtomics, // ATOMIC_STORE_I64_A32_S = 657 CEFBS_HasAtomics, // ATOMIC_STORE_I64_A64 = 658 CEFBS_HasAtomics, // ATOMIC_STORE_I64_A64_S = 659 CEFBS_HasSIMD128, // AVGR_U_I16x8 = 660 CEFBS_HasSIMD128, // AVGR_U_I16x8_S = 661 CEFBS_HasSIMD128, // AVGR_U_I8x16 = 662 CEFBS_HasSIMD128, // AVGR_U_I8x16_S = 663 CEFBS_HasSIMD128, // BITMASK_I16x8 = 664 CEFBS_HasSIMD128, // BITMASK_I16x8_S = 665 CEFBS_HasSIMD128, // BITMASK_I32x4 = 666 CEFBS_HasSIMD128, // BITMASK_I32x4_S = 667 CEFBS_HasSIMD128, // BITMASK_I64x2 = 668 CEFBS_HasSIMD128, // BITMASK_I64x2_S = 669 CEFBS_HasSIMD128, // BITMASK_I8x16 = 670 CEFBS_HasSIMD128, // BITMASK_I8x16_S = 671 CEFBS_HasSIMD128, // BITSELECT = 672 CEFBS_HasSIMD128, // BITSELECT_S = 673 CEFBS_None, // BLOCK = 674 CEFBS_None, // BLOCK_S = 675 CEFBS_None, // BR = 676 CEFBS_None, // BR_IF = 677 CEFBS_None, // BR_IF_S = 678 CEFBS_None, // BR_S = 679 CEFBS_None, // BR_TABLE_I32 = 680 CEFBS_None, // BR_TABLE_I32_S = 681 CEFBS_None, // BR_TABLE_I64 = 682 CEFBS_None, // BR_TABLE_I64_S = 683 CEFBS_None, // BR_UNLESS = 684 CEFBS_None, // BR_UNLESS_S = 685 CEFBS_None, // CALL = 686 CEFBS_None, // CALL_INDIRECT = 687 CEFBS_None, // CALL_INDIRECT_S = 688 CEFBS_None, // CALL_S = 689 CEFBS_HasExceptionHandling, // CATCH = 690 CEFBS_HasExceptionHandling, // CATCH_ALL = 691 CEFBS_HasExceptionHandling, // CATCH_ALL_S = 692 CEFBS_HasExceptionHandling, // CATCH_S = 693 CEFBS_HasSIMD128_HasFP16, // CEIL_F16x8 = 694 CEFBS_HasSIMD128_HasFP16, // CEIL_F16x8_S = 695 CEFBS_None, // CEIL_F32 = 696 CEFBS_None, // CEIL_F32_S = 697 CEFBS_HasSIMD128, // CEIL_F32x4 = 698 CEFBS_HasSIMD128, // CEIL_F32x4_S = 699 CEFBS_None, // CEIL_F64 = 700 CEFBS_None, // CEIL_F64_S = 701 CEFBS_HasSIMD128, // CEIL_F64x2 = 702 CEFBS_HasSIMD128, // CEIL_F64x2_S = 703 CEFBS_None, // CLZ_I32 = 704 CEFBS_None, // CLZ_I32_S = 705 CEFBS_None, // CLZ_I64 = 706 CEFBS_None, // CLZ_I64_S = 707 CEFBS_None, // CONST_F32 = 708 CEFBS_None, // CONST_F32_S = 709 CEFBS_None, // CONST_F64 = 710 CEFBS_None, // CONST_F64_S = 711 CEFBS_None, // CONST_I32 = 712 CEFBS_None, // CONST_I32_S = 713 CEFBS_None, // CONST_I64 = 714 CEFBS_None, // CONST_I64_S = 715 CEFBS_HasSIMD128, // CONST_V128_F32x4 = 716 CEFBS_HasSIMD128, // CONST_V128_F32x4_S = 717 CEFBS_HasSIMD128, // CONST_V128_F64x2 = 718 CEFBS_HasSIMD128, // CONST_V128_F64x2_S = 719 CEFBS_HasSIMD128, // CONST_V128_I16x8 = 720 CEFBS_HasSIMD128, // CONST_V128_I16x8_S = 721 CEFBS_HasSIMD128, // CONST_V128_I32x4 = 722 CEFBS_HasSIMD128, // CONST_V128_I32x4_S = 723 CEFBS_HasSIMD128, // CONST_V128_I64x2 = 724 CEFBS_HasSIMD128, // CONST_V128_I64x2_S = 725 CEFBS_HasSIMD128, // CONST_V128_I8x16 = 726 CEFBS_HasSIMD128, // CONST_V128_I8x16_S = 727 CEFBS_None, // COPYSIGN_F32 = 728 CEFBS_None, // COPYSIGN_F32_S = 729 CEFBS_None, // COPYSIGN_F64 = 730 CEFBS_None, // COPYSIGN_F64_S = 731 CEFBS_HasReferenceTypes_HasExceptionHandling, // COPY_EXNREF = 732 CEFBS_HasReferenceTypes_HasExceptionHandling, // COPY_EXNREF_S = 733 CEFBS_HasReferenceTypes, // COPY_EXTERNREF = 734 CEFBS_HasReferenceTypes, // COPY_EXTERNREF_S = 735 CEFBS_None, // COPY_F32 = 736 CEFBS_None, // COPY_F32_S = 737 CEFBS_None, // COPY_F64 = 738 CEFBS_None, // COPY_F64_S = 739 CEFBS_HasReferenceTypes, // COPY_FUNCREF = 740 CEFBS_HasReferenceTypes, // COPY_FUNCREF_S = 741 CEFBS_None, // COPY_I32 = 742 CEFBS_None, // COPY_I32_S = 743 CEFBS_None, // COPY_I64 = 744 CEFBS_None, // COPY_I64_S = 745 CEFBS_HasSIMD128, // COPY_V128 = 746 CEFBS_HasSIMD128, // COPY_V128_S = 747 CEFBS_None, // CTZ_I32 = 748 CEFBS_None, // CTZ_I32_S = 749 CEFBS_None, // CTZ_I64 = 750 CEFBS_None, // CTZ_I64_S = 751 CEFBS_None, // DEBUG_UNREACHABLE = 752 CEFBS_None, // DEBUG_UNREACHABLE_S = 753 CEFBS_HasExceptionHandling, // DELEGATE = 754 CEFBS_HasExceptionHandling, // DELEGATE_S = 755 CEFBS_HasSIMD128_HasFP16, // DIV_F16x8 = 756 CEFBS_HasSIMD128_HasFP16, // DIV_F16x8_S = 757 CEFBS_None, // DIV_F32 = 758 CEFBS_None, // DIV_F32_S = 759 CEFBS_HasSIMD128, // DIV_F32x4 = 760 CEFBS_HasSIMD128, // DIV_F32x4_S = 761 CEFBS_None, // DIV_F64 = 762 CEFBS_None, // DIV_F64_S = 763 CEFBS_HasSIMD128, // DIV_F64x2 = 764 CEFBS_HasSIMD128, // DIV_F64x2_S = 765 CEFBS_None, // DIV_S_I32 = 766 CEFBS_None, // DIV_S_I32_S = 767 CEFBS_None, // DIV_S_I64 = 768 CEFBS_None, // DIV_S_I64_S = 769 CEFBS_None, // DIV_U_I32 = 770 CEFBS_None, // DIV_U_I32_S = 771 CEFBS_None, // DIV_U_I64 = 772 CEFBS_None, // DIV_U_I64_S = 773 CEFBS_HasSIMD128, // DOT = 774 CEFBS_HasSIMD128, // DOT_S = 775 CEFBS_HasReferenceTypes_HasExceptionHandling, // DROP_EXNREF = 776 CEFBS_HasReferenceTypes_HasExceptionHandling, // DROP_EXNREF_S = 777 CEFBS_HasReferenceTypes, // DROP_EXTERNREF = 778 CEFBS_HasReferenceTypes, // DROP_EXTERNREF_S = 779 CEFBS_None, // DROP_F32 = 780 CEFBS_None, // DROP_F32_S = 781 CEFBS_None, // DROP_F64 = 782 CEFBS_None, // DROP_F64_S = 783 CEFBS_HasReferenceTypes, // DROP_FUNCREF = 784 CEFBS_HasReferenceTypes, // DROP_FUNCREF_S = 785 CEFBS_None, // DROP_I32 = 786 CEFBS_None, // DROP_I32_S = 787 CEFBS_None, // DROP_I64 = 788 CEFBS_None, // DROP_I64_S = 789 CEFBS_HasSIMD128, // DROP_V128 = 790 CEFBS_HasSIMD128, // DROP_V128_S = 791 CEFBS_None, // ELSE = 792 CEFBS_None, // ELSE_S = 793 CEFBS_None, // END = 794 CEFBS_None, // END_BLOCK = 795 CEFBS_None, // END_BLOCK_S = 796 CEFBS_None, // END_FUNCTION = 797 CEFBS_None, // END_FUNCTION_S = 798 CEFBS_None, // END_IF = 799 CEFBS_None, // END_IF_S = 800 CEFBS_None, // END_LOOP = 801 CEFBS_None, // END_LOOP_S = 802 CEFBS_None, // END_S = 803 CEFBS_HasExceptionHandling, // END_TRY = 804 CEFBS_HasExceptionHandling, // END_TRY_S = 805 CEFBS_None, // EQZ_I32 = 806 CEFBS_None, // EQZ_I32_S = 807 CEFBS_None, // EQZ_I64 = 808 CEFBS_None, // EQZ_I64_S = 809 CEFBS_HasSIMD128_HasFP16, // EQ_F16x8 = 810 CEFBS_HasSIMD128_HasFP16, // EQ_F16x8_S = 811 CEFBS_None, // EQ_F32 = 812 CEFBS_None, // EQ_F32_S = 813 CEFBS_HasSIMD128, // EQ_F32x4 = 814 CEFBS_HasSIMD128, // EQ_F32x4_S = 815 CEFBS_None, // EQ_F64 = 816 CEFBS_None, // EQ_F64_S = 817 CEFBS_HasSIMD128, // EQ_F64x2 = 818 CEFBS_HasSIMD128, // EQ_F64x2_S = 819 CEFBS_HasSIMD128, // EQ_I16x8 = 820 CEFBS_HasSIMD128, // EQ_I16x8_S = 821 CEFBS_None, // EQ_I32 = 822 CEFBS_None, // EQ_I32_S = 823 CEFBS_HasSIMD128, // EQ_I32x4 = 824 CEFBS_HasSIMD128, // EQ_I32x4_S = 825 CEFBS_None, // EQ_I64 = 826 CEFBS_None, // EQ_I64_S = 827 CEFBS_HasSIMD128, // EQ_I64x2 = 828 CEFBS_HasSIMD128, // EQ_I64x2_S = 829 CEFBS_HasSIMD128, // EQ_I8x16 = 830 CEFBS_HasSIMD128, // EQ_I8x16_S = 831 CEFBS_HasSIMD128, // EXTMUL_HIGH_S_I16x8 = 832 CEFBS_HasSIMD128, // EXTMUL_HIGH_S_I16x8_S = 833 CEFBS_HasSIMD128, // EXTMUL_HIGH_S_I32x4 = 834 CEFBS_HasSIMD128, // EXTMUL_HIGH_S_I32x4_S = 835 CEFBS_HasSIMD128, // EXTMUL_HIGH_S_I64x2 = 836 CEFBS_HasSIMD128, // EXTMUL_HIGH_S_I64x2_S = 837 CEFBS_HasSIMD128, // EXTMUL_HIGH_U_I16x8 = 838 CEFBS_HasSIMD128, // EXTMUL_HIGH_U_I16x8_S = 839 CEFBS_HasSIMD128, // EXTMUL_HIGH_U_I32x4 = 840 CEFBS_HasSIMD128, // EXTMUL_HIGH_U_I32x4_S = 841 CEFBS_HasSIMD128, // EXTMUL_HIGH_U_I64x2 = 842 CEFBS_HasSIMD128, // EXTMUL_HIGH_U_I64x2_S = 843 CEFBS_HasSIMD128, // EXTMUL_LOW_S_I16x8 = 844 CEFBS_HasSIMD128, // EXTMUL_LOW_S_I16x8_S = 845 CEFBS_HasSIMD128, // EXTMUL_LOW_S_I32x4 = 846 CEFBS_HasSIMD128, // EXTMUL_LOW_S_I32x4_S = 847 CEFBS_HasSIMD128, // EXTMUL_LOW_S_I64x2 = 848 CEFBS_HasSIMD128, // EXTMUL_LOW_S_I64x2_S = 849 CEFBS_HasSIMD128, // EXTMUL_LOW_U_I16x8 = 850 CEFBS_HasSIMD128, // EXTMUL_LOW_U_I16x8_S = 851 CEFBS_HasSIMD128, // EXTMUL_LOW_U_I32x4 = 852 CEFBS_HasSIMD128, // EXTMUL_LOW_U_I32x4_S = 853 CEFBS_HasSIMD128, // EXTMUL_LOW_U_I64x2 = 854 CEFBS_HasSIMD128, // EXTMUL_LOW_U_I64x2_S = 855 CEFBS_HasFP16, // EXTRACT_LANE_F16x8 = 856 CEFBS_HasFP16, // EXTRACT_LANE_F16x8_S = 857 CEFBS_HasSIMD128, // EXTRACT_LANE_F32x4 = 858 CEFBS_HasSIMD128, // EXTRACT_LANE_F32x4_S = 859 CEFBS_HasSIMD128, // EXTRACT_LANE_F64x2 = 860 CEFBS_HasSIMD128, // EXTRACT_LANE_F64x2_S = 861 CEFBS_HasSIMD128, // EXTRACT_LANE_I16x8_s = 862 CEFBS_HasSIMD128, // EXTRACT_LANE_I16x8_s_S = 863 CEFBS_HasSIMD128, // EXTRACT_LANE_I16x8_u = 864 CEFBS_HasSIMD128, // EXTRACT_LANE_I16x8_u_S = 865 CEFBS_HasSIMD128, // EXTRACT_LANE_I32x4 = 866 CEFBS_HasSIMD128, // EXTRACT_LANE_I32x4_S = 867 CEFBS_HasSIMD128, // EXTRACT_LANE_I64x2 = 868 CEFBS_HasSIMD128, // EXTRACT_LANE_I64x2_S = 869 CEFBS_HasSIMD128, // EXTRACT_LANE_I8x16_s = 870 CEFBS_HasSIMD128, // EXTRACT_LANE_I8x16_s_S = 871 CEFBS_HasSIMD128, // EXTRACT_LANE_I8x16_u = 872 CEFBS_HasSIMD128, // EXTRACT_LANE_I8x16_u_S = 873 CEFBS_None, // F32_CONVERT_S_I32 = 874 CEFBS_None, // F32_CONVERT_S_I32_S = 875 CEFBS_None, // F32_CONVERT_S_I64 = 876 CEFBS_None, // F32_CONVERT_S_I64_S = 877 CEFBS_None, // F32_CONVERT_U_I32 = 878 CEFBS_None, // F32_CONVERT_U_I32_S = 879 CEFBS_None, // F32_CONVERT_U_I64 = 880 CEFBS_None, // F32_CONVERT_U_I64_S = 881 CEFBS_None, // F32_DEMOTE_F64 = 882 CEFBS_None, // F32_DEMOTE_F64_S = 883 CEFBS_None, // F32_REINTERPRET_I32 = 884 CEFBS_None, // F32_REINTERPRET_I32_S = 885 CEFBS_None, // F64_CONVERT_S_I32 = 886 CEFBS_None, // F64_CONVERT_S_I32_S = 887 CEFBS_None, // F64_CONVERT_S_I64 = 888 CEFBS_None, // F64_CONVERT_S_I64_S = 889 CEFBS_None, // F64_CONVERT_U_I32 = 890 CEFBS_None, // F64_CONVERT_U_I32_S = 891 CEFBS_None, // F64_CONVERT_U_I64 = 892 CEFBS_None, // F64_CONVERT_U_I64_S = 893 CEFBS_None, // F64_PROMOTE_F32 = 894 CEFBS_None, // F64_PROMOTE_F32_S = 895 CEFBS_None, // F64_REINTERPRET_I64 = 896 CEFBS_None, // F64_REINTERPRET_I64_S = 897 CEFBS_None, // FALLTHROUGH_RETURN = 898 CEFBS_None, // FALLTHROUGH_RETURN_S = 899 CEFBS_HasSIMD128_HasFP16, // FLOOR_F16x8 = 900 CEFBS_HasSIMD128_HasFP16, // FLOOR_F16x8_S = 901 CEFBS_None, // FLOOR_F32 = 902 CEFBS_None, // FLOOR_F32_S = 903 CEFBS_HasSIMD128, // FLOOR_F32x4 = 904 CEFBS_HasSIMD128, // FLOOR_F32x4_S = 905 CEFBS_None, // FLOOR_F64 = 906 CEFBS_None, // FLOOR_F64_S = 907 CEFBS_HasSIMD128, // FLOOR_F64x2 = 908 CEFBS_HasSIMD128, // FLOOR_F64x2_S = 909 CEFBS_NotHasNontrappingFPToInt, // FP_TO_SINT_I32_F32 = 910 CEFBS_NotHasNontrappingFPToInt, // FP_TO_SINT_I32_F32_S = 911 CEFBS_NotHasNontrappingFPToInt, // FP_TO_SINT_I32_F64 = 912 CEFBS_NotHasNontrappingFPToInt, // FP_TO_SINT_I32_F64_S = 913 CEFBS_NotHasNontrappingFPToInt, // FP_TO_SINT_I64_F32 = 914 CEFBS_NotHasNontrappingFPToInt, // FP_TO_SINT_I64_F32_S = 915 CEFBS_NotHasNontrappingFPToInt, // FP_TO_SINT_I64_F64 = 916 CEFBS_NotHasNontrappingFPToInt, // FP_TO_SINT_I64_F64_S = 917 CEFBS_NotHasNontrappingFPToInt, // FP_TO_UINT_I32_F32 = 918 CEFBS_NotHasNontrappingFPToInt, // FP_TO_UINT_I32_F32_S = 919 CEFBS_NotHasNontrappingFPToInt, // FP_TO_UINT_I32_F64 = 920 CEFBS_NotHasNontrappingFPToInt, // FP_TO_UINT_I32_F64_S = 921 CEFBS_NotHasNontrappingFPToInt, // FP_TO_UINT_I64_F32 = 922 CEFBS_NotHasNontrappingFPToInt, // FP_TO_UINT_I64_F32_S = 923 CEFBS_NotHasNontrappingFPToInt, // FP_TO_UINT_I64_F64 = 924 CEFBS_NotHasNontrappingFPToInt, // FP_TO_UINT_I64_F64_S = 925 CEFBS_HasSIMD128_HasFP16, // GE_F16x8 = 926 CEFBS_HasSIMD128_HasFP16, // GE_F16x8_S = 927 CEFBS_None, // GE_F32 = 928 CEFBS_None, // GE_F32_S = 929 CEFBS_HasSIMD128, // GE_F32x4 = 930 CEFBS_HasSIMD128, // GE_F32x4_S = 931 CEFBS_None, // GE_F64 = 932 CEFBS_None, // GE_F64_S = 933 CEFBS_HasSIMD128, // GE_F64x2 = 934 CEFBS_HasSIMD128, // GE_F64x2_S = 935 CEFBS_HasSIMD128, // GE_S_I16x8 = 936 CEFBS_HasSIMD128, // GE_S_I16x8_S = 937 CEFBS_None, // GE_S_I32 = 938 CEFBS_None, // GE_S_I32_S = 939 CEFBS_HasSIMD128, // GE_S_I32x4 = 940 CEFBS_HasSIMD128, // GE_S_I32x4_S = 941 CEFBS_None, // GE_S_I64 = 942 CEFBS_None, // GE_S_I64_S = 943 CEFBS_HasSIMD128, // GE_S_I64x2 = 944 CEFBS_HasSIMD128, // GE_S_I64x2_S = 945 CEFBS_HasSIMD128, // GE_S_I8x16 = 946 CEFBS_HasSIMD128, // GE_S_I8x16_S = 947 CEFBS_HasSIMD128, // GE_U_I16x8 = 948 CEFBS_HasSIMD128, // GE_U_I16x8_S = 949 CEFBS_None, // GE_U_I32 = 950 CEFBS_None, // GE_U_I32_S = 951 CEFBS_HasSIMD128, // GE_U_I32x4 = 952 CEFBS_HasSIMD128, // GE_U_I32x4_S = 953 CEFBS_None, // GE_U_I64 = 954 CEFBS_None, // GE_U_I64_S = 955 CEFBS_HasSIMD128, // GE_U_I8x16 = 956 CEFBS_HasSIMD128, // GE_U_I8x16_S = 957 CEFBS_HasReferenceTypes_HasExceptionHandling, // GLOBAL_GET_EXNREF = 958 CEFBS_HasReferenceTypes_HasExceptionHandling, // GLOBAL_GET_EXNREF_S = 959 CEFBS_HasReferenceTypes, // GLOBAL_GET_EXTERNREF = 960 CEFBS_HasReferenceTypes, // GLOBAL_GET_EXTERNREF_S = 961 CEFBS_None, // GLOBAL_GET_F32 = 962 CEFBS_None, // GLOBAL_GET_F32_S = 963 CEFBS_None, // GLOBAL_GET_F64 = 964 CEFBS_None, // GLOBAL_GET_F64_S = 965 CEFBS_HasReferenceTypes, // GLOBAL_GET_FUNCREF = 966 CEFBS_HasReferenceTypes, // GLOBAL_GET_FUNCREF_S = 967 CEFBS_None, // GLOBAL_GET_I32 = 968 CEFBS_None, // GLOBAL_GET_I32_S = 969 CEFBS_None, // GLOBAL_GET_I64 = 970 CEFBS_None, // GLOBAL_GET_I64_S = 971 CEFBS_HasSIMD128, // GLOBAL_GET_V128 = 972 CEFBS_HasSIMD128, // GLOBAL_GET_V128_S = 973 CEFBS_HasReferenceTypes_HasExceptionHandling, // GLOBAL_SET_EXNREF = 974 CEFBS_HasReferenceTypes_HasExceptionHandling, // GLOBAL_SET_EXNREF_S = 975 CEFBS_HasReferenceTypes, // GLOBAL_SET_EXTERNREF = 976 CEFBS_HasReferenceTypes, // GLOBAL_SET_EXTERNREF_S = 977 CEFBS_None, // GLOBAL_SET_F32 = 978 CEFBS_None, // GLOBAL_SET_F32_S = 979 CEFBS_None, // GLOBAL_SET_F64 = 980 CEFBS_None, // GLOBAL_SET_F64_S = 981 CEFBS_HasReferenceTypes, // GLOBAL_SET_FUNCREF = 982 CEFBS_HasReferenceTypes, // GLOBAL_SET_FUNCREF_S = 983 CEFBS_None, // GLOBAL_SET_I32 = 984 CEFBS_None, // GLOBAL_SET_I32_S = 985 CEFBS_None, // GLOBAL_SET_I64 = 986 CEFBS_None, // GLOBAL_SET_I64_S = 987 CEFBS_HasSIMD128, // GLOBAL_SET_V128 = 988 CEFBS_HasSIMD128, // GLOBAL_SET_V128_S = 989 CEFBS_HasSIMD128_HasFP16, // GT_F16x8 = 990 CEFBS_HasSIMD128_HasFP16, // GT_F16x8_S = 991 CEFBS_None, // GT_F32 = 992 CEFBS_None, // GT_F32_S = 993 CEFBS_HasSIMD128, // GT_F32x4 = 994 CEFBS_HasSIMD128, // GT_F32x4_S = 995 CEFBS_None, // GT_F64 = 996 CEFBS_None, // GT_F64_S = 997 CEFBS_HasSIMD128, // GT_F64x2 = 998 CEFBS_HasSIMD128, // GT_F64x2_S = 999 CEFBS_HasSIMD128, // GT_S_I16x8 = 1000 CEFBS_HasSIMD128, // GT_S_I16x8_S = 1001 CEFBS_None, // GT_S_I32 = 1002 CEFBS_None, // GT_S_I32_S = 1003 CEFBS_HasSIMD128, // GT_S_I32x4 = 1004 CEFBS_HasSIMD128, // GT_S_I32x4_S = 1005 CEFBS_None, // GT_S_I64 = 1006 CEFBS_None, // GT_S_I64_S = 1007 CEFBS_HasSIMD128, // GT_S_I64x2 = 1008 CEFBS_HasSIMD128, // GT_S_I64x2_S = 1009 CEFBS_HasSIMD128, // GT_S_I8x16 = 1010 CEFBS_HasSIMD128, // GT_S_I8x16_S = 1011 CEFBS_HasSIMD128, // GT_U_I16x8 = 1012 CEFBS_HasSIMD128, // GT_U_I16x8_S = 1013 CEFBS_None, // GT_U_I32 = 1014 CEFBS_None, // GT_U_I32_S = 1015 CEFBS_HasSIMD128, // GT_U_I32x4 = 1016 CEFBS_HasSIMD128, // GT_U_I32x4_S = 1017 CEFBS_None, // GT_U_I64 = 1018 CEFBS_None, // GT_U_I64_S = 1019 CEFBS_HasSIMD128, // GT_U_I8x16 = 1020 CEFBS_HasSIMD128, // GT_U_I8x16_S = 1021 CEFBS_HasSignExt, // I32_EXTEND16_S_I32 = 1022 CEFBS_HasSignExt, // I32_EXTEND16_S_I32_S = 1023 CEFBS_HasSignExt, // I32_EXTEND8_S_I32 = 1024 CEFBS_HasSignExt, // I32_EXTEND8_S_I32_S = 1025 CEFBS_None, // I32_REINTERPRET_F32 = 1026 CEFBS_None, // I32_REINTERPRET_F32_S = 1027 CEFBS_None, // I32_TRUNC_S_F32 = 1028 CEFBS_None, // I32_TRUNC_S_F32_S = 1029 CEFBS_None, // I32_TRUNC_S_F64 = 1030 CEFBS_None, // I32_TRUNC_S_F64_S = 1031 CEFBS_HasNontrappingFPToInt, // I32_TRUNC_S_SAT_F32 = 1032 CEFBS_HasNontrappingFPToInt, // I32_TRUNC_S_SAT_F32_S = 1033 CEFBS_HasNontrappingFPToInt, // I32_TRUNC_S_SAT_F64 = 1034 CEFBS_HasNontrappingFPToInt, // I32_TRUNC_S_SAT_F64_S = 1035 CEFBS_None, // I32_TRUNC_U_F32 = 1036 CEFBS_None, // I32_TRUNC_U_F32_S = 1037 CEFBS_None, // I32_TRUNC_U_F64 = 1038 CEFBS_None, // I32_TRUNC_U_F64_S = 1039 CEFBS_HasNontrappingFPToInt, // I32_TRUNC_U_SAT_F32 = 1040 CEFBS_HasNontrappingFPToInt, // I32_TRUNC_U_SAT_F32_S = 1041 CEFBS_HasNontrappingFPToInt, // I32_TRUNC_U_SAT_F64 = 1042 CEFBS_HasNontrappingFPToInt, // I32_TRUNC_U_SAT_F64_S = 1043 CEFBS_None, // I32_WRAP_I64 = 1044 CEFBS_None, // I32_WRAP_I64_S = 1045 CEFBS_HasSignExt, // I64_EXTEND16_S_I64 = 1046 CEFBS_HasSignExt, // I64_EXTEND16_S_I64_S = 1047 CEFBS_HasSignExt, // I64_EXTEND32_S_I64 = 1048 CEFBS_HasSignExt, // I64_EXTEND32_S_I64_S = 1049 CEFBS_HasSignExt, // I64_EXTEND8_S_I64 = 1050 CEFBS_HasSignExt, // I64_EXTEND8_S_I64_S = 1051 CEFBS_None, // I64_EXTEND_S_I32 = 1052 CEFBS_None, // I64_EXTEND_S_I32_S = 1053 CEFBS_None, // I64_EXTEND_U_I32 = 1054 CEFBS_None, // I64_EXTEND_U_I32_S = 1055 CEFBS_None, // I64_REINTERPRET_F64 = 1056 CEFBS_None, // I64_REINTERPRET_F64_S = 1057 CEFBS_None, // I64_TRUNC_S_F32 = 1058 CEFBS_None, // I64_TRUNC_S_F32_S = 1059 CEFBS_None, // I64_TRUNC_S_F64 = 1060 CEFBS_None, // I64_TRUNC_S_F64_S = 1061 CEFBS_HasNontrappingFPToInt, // I64_TRUNC_S_SAT_F32 = 1062 CEFBS_HasNontrappingFPToInt, // I64_TRUNC_S_SAT_F32_S = 1063 CEFBS_HasNontrappingFPToInt, // I64_TRUNC_S_SAT_F64 = 1064 CEFBS_HasNontrappingFPToInt, // I64_TRUNC_S_SAT_F64_S = 1065 CEFBS_None, // I64_TRUNC_U_F32 = 1066 CEFBS_None, // I64_TRUNC_U_F32_S = 1067 CEFBS_None, // I64_TRUNC_U_F64 = 1068 CEFBS_None, // I64_TRUNC_U_F64_S = 1069 CEFBS_HasNontrappingFPToInt, // I64_TRUNC_U_SAT_F32 = 1070 CEFBS_HasNontrappingFPToInt, // I64_TRUNC_U_SAT_F32_S = 1071 CEFBS_HasNontrappingFPToInt, // I64_TRUNC_U_SAT_F64 = 1072 CEFBS_HasNontrappingFPToInt, // I64_TRUNC_U_SAT_F64_S = 1073 CEFBS_None, // IF = 1074 CEFBS_None, // IF_S = 1075 CEFBS_HasRelaxedSIMD, // LANESELECT_I16x8 = 1076 CEFBS_HasRelaxedSIMD, // LANESELECT_I16x8_S = 1077 CEFBS_HasRelaxedSIMD, // LANESELECT_I32x4 = 1078 CEFBS_HasRelaxedSIMD, // LANESELECT_I32x4_S = 1079 CEFBS_HasRelaxedSIMD, // LANESELECT_I64x2 = 1080 CEFBS_HasRelaxedSIMD, // LANESELECT_I64x2_S = 1081 CEFBS_HasRelaxedSIMD, // LANESELECT_I8x16 = 1082 CEFBS_HasRelaxedSIMD, // LANESELECT_I8x16_S = 1083 CEFBS_HasSIMD128_HasFP16, // LE_F16x8 = 1084 CEFBS_HasSIMD128_HasFP16, // LE_F16x8_S = 1085 CEFBS_None, // LE_F32 = 1086 CEFBS_None, // LE_F32_S = 1087 CEFBS_HasSIMD128, // LE_F32x4 = 1088 CEFBS_HasSIMD128, // LE_F32x4_S = 1089 CEFBS_None, // LE_F64 = 1090 CEFBS_None, // LE_F64_S = 1091 CEFBS_HasSIMD128, // LE_F64x2 = 1092 CEFBS_HasSIMD128, // LE_F64x2_S = 1093 CEFBS_HasSIMD128, // LE_S_I16x8 = 1094 CEFBS_HasSIMD128, // LE_S_I16x8_S = 1095 CEFBS_None, // LE_S_I32 = 1096 CEFBS_None, // LE_S_I32_S = 1097 CEFBS_HasSIMD128, // LE_S_I32x4 = 1098 CEFBS_HasSIMD128, // LE_S_I32x4_S = 1099 CEFBS_None, // LE_S_I64 = 1100 CEFBS_None, // LE_S_I64_S = 1101 CEFBS_HasSIMD128, // LE_S_I64x2 = 1102 CEFBS_HasSIMD128, // LE_S_I64x2_S = 1103 CEFBS_HasSIMD128, // LE_S_I8x16 = 1104 CEFBS_HasSIMD128, // LE_S_I8x16_S = 1105 CEFBS_HasSIMD128, // LE_U_I16x8 = 1106 CEFBS_HasSIMD128, // LE_U_I16x8_S = 1107 CEFBS_None, // LE_U_I32 = 1108 CEFBS_None, // LE_U_I32_S = 1109 CEFBS_HasSIMD128, // LE_U_I32x4 = 1110 CEFBS_HasSIMD128, // LE_U_I32x4_S = 1111 CEFBS_None, // LE_U_I64 = 1112 CEFBS_None, // LE_U_I64_S = 1113 CEFBS_HasSIMD128, // LE_U_I8x16 = 1114 CEFBS_HasSIMD128, // LE_U_I8x16_S = 1115 CEFBS_HasSIMD128, // LOAD16_SPLAT_A32 = 1116 CEFBS_HasSIMD128, // LOAD16_SPLAT_A32_S = 1117 CEFBS_HasSIMD128, // LOAD16_SPLAT_A64 = 1118 CEFBS_HasSIMD128, // LOAD16_SPLAT_A64_S = 1119 CEFBS_None, // LOAD16_S_I32_A32 = 1120 CEFBS_None, // LOAD16_S_I32_A32_S = 1121 CEFBS_None, // LOAD16_S_I32_A64 = 1122 CEFBS_None, // LOAD16_S_I32_A64_S = 1123 CEFBS_None, // LOAD16_S_I64_A32 = 1124 CEFBS_None, // LOAD16_S_I64_A32_S = 1125 CEFBS_None, // LOAD16_S_I64_A64 = 1126 CEFBS_None, // LOAD16_S_I64_A64_S = 1127 CEFBS_None, // LOAD16_U_I32_A32 = 1128 CEFBS_None, // LOAD16_U_I32_A32_S = 1129 CEFBS_None, // LOAD16_U_I32_A64 = 1130 CEFBS_None, // LOAD16_U_I32_A64_S = 1131 CEFBS_None, // LOAD16_U_I64_A32 = 1132 CEFBS_None, // LOAD16_U_I64_A32_S = 1133 CEFBS_None, // LOAD16_U_I64_A64 = 1134 CEFBS_None, // LOAD16_U_I64_A64_S = 1135 CEFBS_HasSIMD128, // LOAD32_SPLAT_A32 = 1136 CEFBS_HasSIMD128, // LOAD32_SPLAT_A32_S = 1137 CEFBS_HasSIMD128, // LOAD32_SPLAT_A64 = 1138 CEFBS_HasSIMD128, // LOAD32_SPLAT_A64_S = 1139 CEFBS_None, // LOAD32_S_I64_A32 = 1140 CEFBS_None, // LOAD32_S_I64_A32_S = 1141 CEFBS_None, // LOAD32_S_I64_A64 = 1142 CEFBS_None, // LOAD32_S_I64_A64_S = 1143 CEFBS_None, // LOAD32_U_I64_A32 = 1144 CEFBS_None, // LOAD32_U_I64_A32_S = 1145 CEFBS_None, // LOAD32_U_I64_A64 = 1146 CEFBS_None, // LOAD32_U_I64_A64_S = 1147 CEFBS_HasSIMD128, // LOAD64_SPLAT_A32 = 1148 CEFBS_HasSIMD128, // LOAD64_SPLAT_A32_S = 1149 CEFBS_HasSIMD128, // LOAD64_SPLAT_A64 = 1150 CEFBS_HasSIMD128, // LOAD64_SPLAT_A64_S = 1151 CEFBS_HasSIMD128, // LOAD8_SPLAT_A32 = 1152 CEFBS_HasSIMD128, // LOAD8_SPLAT_A32_S = 1153 CEFBS_HasSIMD128, // LOAD8_SPLAT_A64 = 1154 CEFBS_HasSIMD128, // LOAD8_SPLAT_A64_S = 1155 CEFBS_None, // LOAD8_S_I32_A32 = 1156 CEFBS_None, // LOAD8_S_I32_A32_S = 1157 CEFBS_None, // LOAD8_S_I32_A64 = 1158 CEFBS_None, // LOAD8_S_I32_A64_S = 1159 CEFBS_None, // LOAD8_S_I64_A32 = 1160 CEFBS_None, // LOAD8_S_I64_A32_S = 1161 CEFBS_None, // LOAD8_S_I64_A64 = 1162 CEFBS_None, // LOAD8_S_I64_A64_S = 1163 CEFBS_None, // LOAD8_U_I32_A32 = 1164 CEFBS_None, // LOAD8_U_I32_A32_S = 1165 CEFBS_None, // LOAD8_U_I32_A64 = 1166 CEFBS_None, // LOAD8_U_I32_A64_S = 1167 CEFBS_None, // LOAD8_U_I64_A32 = 1168 CEFBS_None, // LOAD8_U_I64_A32_S = 1169 CEFBS_None, // LOAD8_U_I64_A64 = 1170 CEFBS_None, // LOAD8_U_I64_A64_S = 1171 CEFBS_HasSIMD128, // LOAD_EXTEND_S_I16x8_A32 = 1172 CEFBS_HasSIMD128, // LOAD_EXTEND_S_I16x8_A32_S = 1173 CEFBS_HasSIMD128, // LOAD_EXTEND_S_I16x8_A64 = 1174 CEFBS_HasSIMD128, // LOAD_EXTEND_S_I16x8_A64_S = 1175 CEFBS_HasSIMD128, // LOAD_EXTEND_S_I32x4_A32 = 1176 CEFBS_HasSIMD128, // LOAD_EXTEND_S_I32x4_A32_S = 1177 CEFBS_HasSIMD128, // LOAD_EXTEND_S_I32x4_A64 = 1178 CEFBS_HasSIMD128, // LOAD_EXTEND_S_I32x4_A64_S = 1179 CEFBS_HasSIMD128, // LOAD_EXTEND_S_I64x2_A32 = 1180 CEFBS_HasSIMD128, // LOAD_EXTEND_S_I64x2_A32_S = 1181 CEFBS_HasSIMD128, // LOAD_EXTEND_S_I64x2_A64 = 1182 CEFBS_HasSIMD128, // LOAD_EXTEND_S_I64x2_A64_S = 1183 CEFBS_HasSIMD128, // LOAD_EXTEND_U_I16x8_A32 = 1184 CEFBS_HasSIMD128, // LOAD_EXTEND_U_I16x8_A32_S = 1185 CEFBS_HasSIMD128, // LOAD_EXTEND_U_I16x8_A64 = 1186 CEFBS_HasSIMD128, // LOAD_EXTEND_U_I16x8_A64_S = 1187 CEFBS_HasSIMD128, // LOAD_EXTEND_U_I32x4_A32 = 1188 CEFBS_HasSIMD128, // LOAD_EXTEND_U_I32x4_A32_S = 1189 CEFBS_HasSIMD128, // LOAD_EXTEND_U_I32x4_A64 = 1190 CEFBS_HasSIMD128, // LOAD_EXTEND_U_I32x4_A64_S = 1191 CEFBS_HasSIMD128, // LOAD_EXTEND_U_I64x2_A32 = 1192 CEFBS_HasSIMD128, // LOAD_EXTEND_U_I64x2_A32_S = 1193 CEFBS_HasSIMD128, // LOAD_EXTEND_U_I64x2_A64 = 1194 CEFBS_HasSIMD128, // LOAD_EXTEND_U_I64x2_A64_S = 1195 CEFBS_HasFP16, // LOAD_F16_F32_A32 = 1196 CEFBS_HasFP16, // LOAD_F16_F32_A32_S = 1197 CEFBS_HasFP16, // LOAD_F16_F32_A64 = 1198 CEFBS_HasFP16, // LOAD_F16_F32_A64_S = 1199 CEFBS_None, // LOAD_F32_A32 = 1200 CEFBS_None, // LOAD_F32_A32_S = 1201 CEFBS_None, // LOAD_F32_A64 = 1202 CEFBS_None, // LOAD_F32_A64_S = 1203 CEFBS_None, // LOAD_F64_A32 = 1204 CEFBS_None, // LOAD_F64_A32_S = 1205 CEFBS_None, // LOAD_F64_A64 = 1206 CEFBS_None, // LOAD_F64_A64_S = 1207 CEFBS_None, // LOAD_I32_A32 = 1208 CEFBS_None, // LOAD_I32_A32_S = 1209 CEFBS_None, // LOAD_I32_A64 = 1210 CEFBS_None, // LOAD_I32_A64_S = 1211 CEFBS_None, // LOAD_I64_A32 = 1212 CEFBS_None, // LOAD_I64_A32_S = 1213 CEFBS_None, // LOAD_I64_A64 = 1214 CEFBS_None, // LOAD_I64_A64_S = 1215 CEFBS_HasSIMD128, // LOAD_LANE_16_A32 = 1216 CEFBS_HasSIMD128, // LOAD_LANE_16_A32_S = 1217 CEFBS_HasSIMD128, // LOAD_LANE_16_A64 = 1218 CEFBS_HasSIMD128, // LOAD_LANE_16_A64_S = 1219 CEFBS_HasSIMD128, // LOAD_LANE_32_A32 = 1220 CEFBS_HasSIMD128, // LOAD_LANE_32_A32_S = 1221 CEFBS_HasSIMD128, // LOAD_LANE_32_A64 = 1222 CEFBS_HasSIMD128, // LOAD_LANE_32_A64_S = 1223 CEFBS_HasSIMD128, // LOAD_LANE_64_A32 = 1224 CEFBS_HasSIMD128, // LOAD_LANE_64_A32_S = 1225 CEFBS_HasSIMD128, // LOAD_LANE_64_A64 = 1226 CEFBS_HasSIMD128, // LOAD_LANE_64_A64_S = 1227 CEFBS_HasSIMD128, // LOAD_LANE_8_A32 = 1228 CEFBS_HasSIMD128, // LOAD_LANE_8_A32_S = 1229 CEFBS_HasSIMD128, // LOAD_LANE_8_A64 = 1230 CEFBS_HasSIMD128, // LOAD_LANE_8_A64_S = 1231 CEFBS_HasSIMD128, // LOAD_V128_A32 = 1232 CEFBS_HasSIMD128, // LOAD_V128_A32_S = 1233 CEFBS_HasSIMD128, // LOAD_V128_A64 = 1234 CEFBS_HasSIMD128, // LOAD_V128_A64_S = 1235 CEFBS_HasSIMD128, // LOAD_ZERO_32_A32 = 1236 CEFBS_HasSIMD128, // LOAD_ZERO_32_A32_S = 1237 CEFBS_HasSIMD128, // LOAD_ZERO_32_A64 = 1238 CEFBS_HasSIMD128, // LOAD_ZERO_32_A64_S = 1239 CEFBS_HasSIMD128, // LOAD_ZERO_64_A32 = 1240 CEFBS_HasSIMD128, // LOAD_ZERO_64_A32_S = 1241 CEFBS_HasSIMD128, // LOAD_ZERO_64_A64 = 1242 CEFBS_HasSIMD128, // LOAD_ZERO_64_A64_S = 1243 CEFBS_HasReferenceTypes_HasExceptionHandling, // LOCAL_GET_EXNREF = 1244 CEFBS_HasReferenceTypes_HasExceptionHandling, // LOCAL_GET_EXNREF_S = 1245 CEFBS_HasReferenceTypes, // LOCAL_GET_EXTERNREF = 1246 CEFBS_HasReferenceTypes, // LOCAL_GET_EXTERNREF_S = 1247 CEFBS_None, // LOCAL_GET_F32 = 1248 CEFBS_None, // LOCAL_GET_F32_S = 1249 CEFBS_None, // LOCAL_GET_F64 = 1250 CEFBS_None, // LOCAL_GET_F64_S = 1251 CEFBS_HasReferenceTypes, // LOCAL_GET_FUNCREF = 1252 CEFBS_HasReferenceTypes, // LOCAL_GET_FUNCREF_S = 1253 CEFBS_None, // LOCAL_GET_I32 = 1254 CEFBS_None, // LOCAL_GET_I32_S = 1255 CEFBS_None, // LOCAL_GET_I64 = 1256 CEFBS_None, // LOCAL_GET_I64_S = 1257 CEFBS_HasSIMD128, // LOCAL_GET_V128 = 1258 CEFBS_HasSIMD128, // LOCAL_GET_V128_S = 1259 CEFBS_HasReferenceTypes_HasExceptionHandling, // LOCAL_SET_EXNREF = 1260 CEFBS_HasReferenceTypes_HasExceptionHandling, // LOCAL_SET_EXNREF_S = 1261 CEFBS_HasReferenceTypes, // LOCAL_SET_EXTERNREF = 1262 CEFBS_HasReferenceTypes, // LOCAL_SET_EXTERNREF_S = 1263 CEFBS_None, // LOCAL_SET_F32 = 1264 CEFBS_None, // LOCAL_SET_F32_S = 1265 CEFBS_None, // LOCAL_SET_F64 = 1266 CEFBS_None, // LOCAL_SET_F64_S = 1267 CEFBS_HasReferenceTypes, // LOCAL_SET_FUNCREF = 1268 CEFBS_HasReferenceTypes, // LOCAL_SET_FUNCREF_S = 1269 CEFBS_None, // LOCAL_SET_I32 = 1270 CEFBS_None, // LOCAL_SET_I32_S = 1271 CEFBS_None, // LOCAL_SET_I64 = 1272 CEFBS_None, // LOCAL_SET_I64_S = 1273 CEFBS_HasSIMD128, // LOCAL_SET_V128 = 1274 CEFBS_HasSIMD128, // LOCAL_SET_V128_S = 1275 CEFBS_HasReferenceTypes_HasExceptionHandling, // LOCAL_TEE_EXNREF = 1276 CEFBS_HasReferenceTypes_HasExceptionHandling, // LOCAL_TEE_EXNREF_S = 1277 CEFBS_HasReferenceTypes, // LOCAL_TEE_EXTERNREF = 1278 CEFBS_HasReferenceTypes, // LOCAL_TEE_EXTERNREF_S = 1279 CEFBS_None, // LOCAL_TEE_F32 = 1280 CEFBS_None, // LOCAL_TEE_F32_S = 1281 CEFBS_None, // LOCAL_TEE_F64 = 1282 CEFBS_None, // LOCAL_TEE_F64_S = 1283 CEFBS_HasReferenceTypes, // LOCAL_TEE_FUNCREF = 1284 CEFBS_HasReferenceTypes, // LOCAL_TEE_FUNCREF_S = 1285 CEFBS_None, // LOCAL_TEE_I32 = 1286 CEFBS_None, // LOCAL_TEE_I32_S = 1287 CEFBS_None, // LOCAL_TEE_I64 = 1288 CEFBS_None, // LOCAL_TEE_I64_S = 1289 CEFBS_HasSIMD128, // LOCAL_TEE_V128 = 1290 CEFBS_HasSIMD128, // LOCAL_TEE_V128_S = 1291 CEFBS_None, // LOOP = 1292 CEFBS_None, // LOOP_S = 1293 CEFBS_HasSIMD128_HasFP16, // LT_F16x8 = 1294 CEFBS_HasSIMD128_HasFP16, // LT_F16x8_S = 1295 CEFBS_None, // LT_F32 = 1296 CEFBS_None, // LT_F32_S = 1297 CEFBS_HasSIMD128, // LT_F32x4 = 1298 CEFBS_HasSIMD128, // LT_F32x4_S = 1299 CEFBS_None, // LT_F64 = 1300 CEFBS_None, // LT_F64_S = 1301 CEFBS_HasSIMD128, // LT_F64x2 = 1302 CEFBS_HasSIMD128, // LT_F64x2_S = 1303 CEFBS_HasSIMD128, // LT_S_I16x8 = 1304 CEFBS_HasSIMD128, // LT_S_I16x8_S = 1305 CEFBS_None, // LT_S_I32 = 1306 CEFBS_None, // LT_S_I32_S = 1307 CEFBS_HasSIMD128, // LT_S_I32x4 = 1308 CEFBS_HasSIMD128, // LT_S_I32x4_S = 1309 CEFBS_None, // LT_S_I64 = 1310 CEFBS_None, // LT_S_I64_S = 1311 CEFBS_HasSIMD128, // LT_S_I64x2 = 1312 CEFBS_HasSIMD128, // LT_S_I64x2_S = 1313 CEFBS_HasSIMD128, // LT_S_I8x16 = 1314 CEFBS_HasSIMD128, // LT_S_I8x16_S = 1315 CEFBS_HasSIMD128, // LT_U_I16x8 = 1316 CEFBS_HasSIMD128, // LT_U_I16x8_S = 1317 CEFBS_None, // LT_U_I32 = 1318 CEFBS_None, // LT_U_I32_S = 1319 CEFBS_HasSIMD128, // LT_U_I32x4 = 1320 CEFBS_HasSIMD128, // LT_U_I32x4_S = 1321 CEFBS_None, // LT_U_I64 = 1322 CEFBS_None, // LT_U_I64_S = 1323 CEFBS_HasSIMD128, // LT_U_I8x16 = 1324 CEFBS_HasSIMD128, // LT_U_I8x16_S = 1325 CEFBS_HasSIMD128_HasFP16, // MADD_F16x8 = 1326 CEFBS_HasSIMD128_HasFP16, // MADD_F16x8_S = 1327 CEFBS_HasSIMD128_HasRelaxedSIMD, // MADD_F32x4 = 1328 CEFBS_HasSIMD128_HasRelaxedSIMD, // MADD_F32x4_S = 1329 CEFBS_HasSIMD128_HasRelaxedSIMD, // MADD_F64x2 = 1330 CEFBS_HasSIMD128_HasRelaxedSIMD, // MADD_F64x2_S = 1331 CEFBS_HasSIMD128_HasFP16, // MAX_F16x8 = 1332 CEFBS_HasSIMD128_HasFP16, // MAX_F16x8_S = 1333 CEFBS_None, // MAX_F32 = 1334 CEFBS_None, // MAX_F32_S = 1335 CEFBS_HasSIMD128, // MAX_F32x4 = 1336 CEFBS_HasSIMD128, // MAX_F32x4_S = 1337 CEFBS_None, // MAX_F64 = 1338 CEFBS_None, // MAX_F64_S = 1339 CEFBS_HasSIMD128, // MAX_F64x2 = 1340 CEFBS_HasSIMD128, // MAX_F64x2_S = 1341 CEFBS_HasSIMD128, // MAX_S_I16x8 = 1342 CEFBS_HasSIMD128, // MAX_S_I16x8_S = 1343 CEFBS_HasSIMD128, // MAX_S_I32x4 = 1344 CEFBS_HasSIMD128, // MAX_S_I32x4_S = 1345 CEFBS_HasSIMD128, // MAX_S_I8x16 = 1346 CEFBS_HasSIMD128, // MAX_S_I8x16_S = 1347 CEFBS_HasSIMD128, // MAX_U_I16x8 = 1348 CEFBS_HasSIMD128, // MAX_U_I16x8_S = 1349 CEFBS_HasSIMD128, // MAX_U_I32x4 = 1350 CEFBS_HasSIMD128, // MAX_U_I32x4_S = 1351 CEFBS_HasSIMD128, // MAX_U_I8x16 = 1352 CEFBS_HasSIMD128, // MAX_U_I8x16_S = 1353 CEFBS_HasAtomics, // MEMORY_ATOMIC_NOTIFY_A32 = 1354 CEFBS_HasAtomics, // MEMORY_ATOMIC_NOTIFY_A32_S = 1355 CEFBS_HasAtomics, // MEMORY_ATOMIC_NOTIFY_A64 = 1356 CEFBS_HasAtomics, // MEMORY_ATOMIC_NOTIFY_A64_S = 1357 CEFBS_HasAtomics, // MEMORY_ATOMIC_WAIT32_A32 = 1358 CEFBS_HasAtomics, // MEMORY_ATOMIC_WAIT32_A32_S = 1359 CEFBS_HasAtomics, // MEMORY_ATOMIC_WAIT32_A64 = 1360 CEFBS_HasAtomics, // MEMORY_ATOMIC_WAIT32_A64_S = 1361 CEFBS_HasAtomics, // MEMORY_ATOMIC_WAIT64_A32 = 1362 CEFBS_HasAtomics, // MEMORY_ATOMIC_WAIT64_A32_S = 1363 CEFBS_HasAtomics, // MEMORY_ATOMIC_WAIT64_A64 = 1364 CEFBS_HasAtomics, // MEMORY_ATOMIC_WAIT64_A64_S = 1365 CEFBS_HasSIMD128_HasFP16, // MIN_F16x8 = 1366 CEFBS_HasSIMD128_HasFP16, // MIN_F16x8_S = 1367 CEFBS_None, // MIN_F32 = 1368 CEFBS_None, // MIN_F32_S = 1369 CEFBS_HasSIMD128, // MIN_F32x4 = 1370 CEFBS_HasSIMD128, // MIN_F32x4_S = 1371 CEFBS_None, // MIN_F64 = 1372 CEFBS_None, // MIN_F64_S = 1373 CEFBS_HasSIMD128, // MIN_F64x2 = 1374 CEFBS_HasSIMD128, // MIN_F64x2_S = 1375 CEFBS_HasSIMD128, // MIN_S_I16x8 = 1376 CEFBS_HasSIMD128, // MIN_S_I16x8_S = 1377 CEFBS_HasSIMD128, // MIN_S_I32x4 = 1378 CEFBS_HasSIMD128, // MIN_S_I32x4_S = 1379 CEFBS_HasSIMD128, // MIN_S_I8x16 = 1380 CEFBS_HasSIMD128, // MIN_S_I8x16_S = 1381 CEFBS_HasSIMD128, // MIN_U_I16x8 = 1382 CEFBS_HasSIMD128, // MIN_U_I16x8_S = 1383 CEFBS_HasSIMD128, // MIN_U_I32x4 = 1384 CEFBS_HasSIMD128, // MIN_U_I32x4_S = 1385 CEFBS_HasSIMD128, // MIN_U_I8x16 = 1386 CEFBS_HasSIMD128, // MIN_U_I8x16_S = 1387 CEFBS_HasSIMD128_HasFP16, // MUL_F16x8 = 1388 CEFBS_HasSIMD128_HasFP16, // MUL_F16x8_S = 1389 CEFBS_None, // MUL_F32 = 1390 CEFBS_None, // MUL_F32_S = 1391 CEFBS_HasSIMD128, // MUL_F32x4 = 1392 CEFBS_HasSIMD128, // MUL_F32x4_S = 1393 CEFBS_None, // MUL_F64 = 1394 CEFBS_None, // MUL_F64_S = 1395 CEFBS_HasSIMD128, // MUL_F64x2 = 1396 CEFBS_HasSIMD128, // MUL_F64x2_S = 1397 CEFBS_HasSIMD128, // MUL_I16x8 = 1398 CEFBS_HasSIMD128, // MUL_I16x8_S = 1399 CEFBS_None, // MUL_I32 = 1400 CEFBS_None, // MUL_I32_S = 1401 CEFBS_HasSIMD128, // MUL_I32x4 = 1402 CEFBS_HasSIMD128, // MUL_I32x4_S = 1403 CEFBS_None, // MUL_I64 = 1404 CEFBS_None, // MUL_I64_S = 1405 CEFBS_HasSIMD128, // MUL_I64x2 = 1406 CEFBS_HasSIMD128, // MUL_I64x2_S = 1407 CEFBS_HasSIMD128, // NARROW_S_I16x8 = 1408 CEFBS_HasSIMD128, // NARROW_S_I16x8_S = 1409 CEFBS_HasSIMD128, // NARROW_S_I8x16 = 1410 CEFBS_HasSIMD128, // NARROW_S_I8x16_S = 1411 CEFBS_HasSIMD128, // NARROW_U_I16x8 = 1412 CEFBS_HasSIMD128, // NARROW_U_I16x8_S = 1413 CEFBS_HasSIMD128, // NARROW_U_I8x16 = 1414 CEFBS_HasSIMD128, // NARROW_U_I8x16_S = 1415 CEFBS_HasSIMD128_HasFP16, // NEAREST_F16x8 = 1416 CEFBS_HasSIMD128_HasFP16, // NEAREST_F16x8_S = 1417 CEFBS_None, // NEAREST_F32 = 1418 CEFBS_None, // NEAREST_F32_S = 1419 CEFBS_HasSIMD128, // NEAREST_F32x4 = 1420 CEFBS_HasSIMD128, // NEAREST_F32x4_S = 1421 CEFBS_None, // NEAREST_F64 = 1422 CEFBS_None, // NEAREST_F64_S = 1423 CEFBS_HasSIMD128, // NEAREST_F64x2 = 1424 CEFBS_HasSIMD128, // NEAREST_F64x2_S = 1425 CEFBS_HasSIMD128_HasFP16, // NEG_F16x8 = 1426 CEFBS_HasSIMD128_HasFP16, // NEG_F16x8_S = 1427 CEFBS_None, // NEG_F32 = 1428 CEFBS_None, // NEG_F32_S = 1429 CEFBS_HasSIMD128, // NEG_F32x4 = 1430 CEFBS_HasSIMD128, // NEG_F32x4_S = 1431 CEFBS_None, // NEG_F64 = 1432 CEFBS_None, // NEG_F64_S = 1433 CEFBS_HasSIMD128, // NEG_F64x2 = 1434 CEFBS_HasSIMD128, // NEG_F64x2_S = 1435 CEFBS_HasSIMD128, // NEG_I16x8 = 1436 CEFBS_HasSIMD128, // NEG_I16x8_S = 1437 CEFBS_HasSIMD128, // NEG_I32x4 = 1438 CEFBS_HasSIMD128, // NEG_I32x4_S = 1439 CEFBS_HasSIMD128, // NEG_I64x2 = 1440 CEFBS_HasSIMD128, // NEG_I64x2_S = 1441 CEFBS_HasSIMD128, // NEG_I8x16 = 1442 CEFBS_HasSIMD128, // NEG_I8x16_S = 1443 CEFBS_HasSIMD128_HasFP16, // NE_F16x8 = 1444 CEFBS_HasSIMD128_HasFP16, // NE_F16x8_S = 1445 CEFBS_None, // NE_F32 = 1446 CEFBS_None, // NE_F32_S = 1447 CEFBS_HasSIMD128, // NE_F32x4 = 1448 CEFBS_HasSIMD128, // NE_F32x4_S = 1449 CEFBS_None, // NE_F64 = 1450 CEFBS_None, // NE_F64_S = 1451 CEFBS_HasSIMD128, // NE_F64x2 = 1452 CEFBS_HasSIMD128, // NE_F64x2_S = 1453 CEFBS_HasSIMD128, // NE_I16x8 = 1454 CEFBS_HasSIMD128, // NE_I16x8_S = 1455 CEFBS_None, // NE_I32 = 1456 CEFBS_None, // NE_I32_S = 1457 CEFBS_HasSIMD128, // NE_I32x4 = 1458 CEFBS_HasSIMD128, // NE_I32x4_S = 1459 CEFBS_None, // NE_I64 = 1460 CEFBS_None, // NE_I64_S = 1461 CEFBS_HasSIMD128, // NE_I64x2 = 1462 CEFBS_HasSIMD128, // NE_I64x2_S = 1463 CEFBS_HasSIMD128, // NE_I8x16 = 1464 CEFBS_HasSIMD128, // NE_I8x16_S = 1465 CEFBS_HasSIMD128_HasFP16, // NMADD_F16x8 = 1466 CEFBS_HasSIMD128_HasFP16, // NMADD_F16x8_S = 1467 CEFBS_HasSIMD128_HasRelaxedSIMD, // NMADD_F32x4 = 1468 CEFBS_HasSIMD128_HasRelaxedSIMD, // NMADD_F32x4_S = 1469 CEFBS_HasSIMD128_HasRelaxedSIMD, // NMADD_F64x2 = 1470 CEFBS_HasSIMD128_HasRelaxedSIMD, // NMADD_F64x2_S = 1471 CEFBS_None, // NOP = 1472 CEFBS_None, // NOP_S = 1473 CEFBS_HasSIMD128, // NOT = 1474 CEFBS_HasSIMD128, // NOT_S = 1475 CEFBS_HasSIMD128, // OR = 1476 CEFBS_None, // OR_I32 = 1477 CEFBS_None, // OR_I32_S = 1478 CEFBS_None, // OR_I64 = 1479 CEFBS_None, // OR_I64_S = 1480 CEFBS_HasSIMD128, // OR_S = 1481 CEFBS_HasSIMD128_HasFP16, // PMAX_F16x8 = 1482 CEFBS_HasSIMD128_HasFP16, // PMAX_F16x8_S = 1483 CEFBS_HasSIMD128, // PMAX_F32x4 = 1484 CEFBS_HasSIMD128, // PMAX_F32x4_S = 1485 CEFBS_HasSIMD128, // PMAX_F64x2 = 1486 CEFBS_HasSIMD128, // PMAX_F64x2_S = 1487 CEFBS_HasSIMD128_HasFP16, // PMIN_F16x8 = 1488 CEFBS_HasSIMD128_HasFP16, // PMIN_F16x8_S = 1489 CEFBS_HasSIMD128, // PMIN_F32x4 = 1490 CEFBS_HasSIMD128, // PMIN_F32x4_S = 1491 CEFBS_HasSIMD128, // PMIN_F64x2 = 1492 CEFBS_HasSIMD128, // PMIN_F64x2_S = 1493 CEFBS_None, // POPCNT_I32 = 1494 CEFBS_None, // POPCNT_I32_S = 1495 CEFBS_None, // POPCNT_I64 = 1496 CEFBS_None, // POPCNT_I64_S = 1497 CEFBS_HasSIMD128, // POPCNT_I8x16 = 1498 CEFBS_HasSIMD128, // POPCNT_I8x16_S = 1499 CEFBS_HasSIMD128, // Q15MULR_SAT_S_I16x8 = 1500 CEFBS_HasSIMD128, // Q15MULR_SAT_S_I16x8_S = 1501 CEFBS_HasReferenceTypes, // REF_IS_NULL_EXNREF = 1502 CEFBS_HasReferenceTypes, // REF_IS_NULL_EXNREF_S = 1503 CEFBS_HasReferenceTypes, // REF_IS_NULL_EXTERNREF = 1504 CEFBS_HasReferenceTypes, // REF_IS_NULL_EXTERNREF_S = 1505 CEFBS_HasReferenceTypes, // REF_IS_NULL_FUNCREF = 1506 CEFBS_HasReferenceTypes, // REF_IS_NULL_FUNCREF_S = 1507 CEFBS_HasReferenceTypes, // REF_NULL_EXNREF = 1508 CEFBS_HasReferenceTypes, // REF_NULL_EXNREF_S = 1509 CEFBS_HasReferenceTypes, // REF_NULL_EXTERNREF = 1510 CEFBS_HasReferenceTypes, // REF_NULL_EXTERNREF_S = 1511 CEFBS_HasReferenceTypes, // REF_NULL_FUNCREF = 1512 CEFBS_HasReferenceTypes, // REF_NULL_FUNCREF_S = 1513 CEFBS_HasRelaxedSIMD, // RELAXED_DOT = 1514 CEFBS_HasRelaxedSIMD, // RELAXED_DOT_ADD = 1515 CEFBS_HasRelaxedSIMD, // RELAXED_DOT_ADD_S = 1516 CEFBS_HasRelaxedSIMD, // RELAXED_DOT_BFLOAT = 1517 CEFBS_HasRelaxedSIMD, // RELAXED_DOT_BFLOAT_S = 1518 CEFBS_HasRelaxedSIMD, // RELAXED_DOT_S = 1519 CEFBS_HasRelaxedSIMD, // RELAXED_Q15MULR_S_I16x8 = 1520 CEFBS_HasRelaxedSIMD, // RELAXED_Q15MULR_S_I16x8_S = 1521 CEFBS_HasRelaxedSIMD, // RELAXED_SWIZZLE = 1522 CEFBS_HasRelaxedSIMD, // RELAXED_SWIZZLE_S = 1523 CEFBS_None, // REM_S_I32 = 1524 CEFBS_None, // REM_S_I32_S = 1525 CEFBS_None, // REM_S_I64 = 1526 CEFBS_None, // REM_S_I64_S = 1527 CEFBS_None, // REM_U_I32 = 1528 CEFBS_None, // REM_U_I32_S = 1529 CEFBS_None, // REM_U_I64 = 1530 CEFBS_None, // REM_U_I64_S = 1531 CEFBS_HasFP16, // REPLACE_LANE_F16x8 = 1532 CEFBS_HasFP16, // REPLACE_LANE_F16x8_S = 1533 CEFBS_HasSIMD128, // REPLACE_LANE_F32x4 = 1534 CEFBS_HasSIMD128, // REPLACE_LANE_F32x4_S = 1535 CEFBS_HasSIMD128, // REPLACE_LANE_F64x2 = 1536 CEFBS_HasSIMD128, // REPLACE_LANE_F64x2_S = 1537 CEFBS_HasSIMD128, // REPLACE_LANE_I16x8 = 1538 CEFBS_HasSIMD128, // REPLACE_LANE_I16x8_S = 1539 CEFBS_HasSIMD128, // REPLACE_LANE_I32x4 = 1540 CEFBS_HasSIMD128, // REPLACE_LANE_I32x4_S = 1541 CEFBS_HasSIMD128, // REPLACE_LANE_I64x2 = 1542 CEFBS_HasSIMD128, // REPLACE_LANE_I64x2_S = 1543 CEFBS_HasSIMD128, // REPLACE_LANE_I8x16 = 1544 CEFBS_HasSIMD128, // REPLACE_LANE_I8x16_S = 1545 CEFBS_HasExceptionHandling, // RETHROW = 1546 CEFBS_HasExceptionHandling, // RETHROW_S = 1547 CEFBS_None, // RETURN = 1548 CEFBS_None, // RETURN_S = 1549 CEFBS_HasTailCall, // RET_CALL = 1550 CEFBS_HasTailCall, // RET_CALL_INDIRECT = 1551 CEFBS_HasTailCall, // RET_CALL_INDIRECT_S = 1552 CEFBS_HasTailCall, // RET_CALL_S = 1553 CEFBS_None, // ROTL_I32 = 1554 CEFBS_None, // ROTL_I32_S = 1555 CEFBS_None, // ROTL_I64 = 1556 CEFBS_None, // ROTL_I64_S = 1557 CEFBS_None, // ROTR_I32 = 1558 CEFBS_None, // ROTR_I32_S = 1559 CEFBS_None, // ROTR_I64 = 1560 CEFBS_None, // ROTR_I64_S = 1561 CEFBS_HasReferenceTypes, // SELECT_EXNREF = 1562 CEFBS_HasReferenceTypes, // SELECT_EXNREF_S = 1563 CEFBS_HasReferenceTypes, // SELECT_EXTERNREF = 1564 CEFBS_HasReferenceTypes, // SELECT_EXTERNREF_S = 1565 CEFBS_None, // SELECT_F32 = 1566 CEFBS_None, // SELECT_F32_S = 1567 CEFBS_None, // SELECT_F64 = 1568 CEFBS_None, // SELECT_F64_S = 1569 CEFBS_HasReferenceTypes, // SELECT_FUNCREF = 1570 CEFBS_HasReferenceTypes, // SELECT_FUNCREF_S = 1571 CEFBS_None, // SELECT_I32 = 1572 CEFBS_None, // SELECT_I32_S = 1573 CEFBS_None, // SELECT_I64 = 1574 CEFBS_None, // SELECT_I64_S = 1575 CEFBS_None, // SELECT_V128 = 1576 CEFBS_None, // SELECT_V128_S = 1577 CEFBS_HasSIMD128, // SHL_I16x8 = 1578 CEFBS_HasSIMD128, // SHL_I16x8_S = 1579 CEFBS_None, // SHL_I32 = 1580 CEFBS_None, // SHL_I32_S = 1581 CEFBS_HasSIMD128, // SHL_I32x4 = 1582 CEFBS_HasSIMD128, // SHL_I32x4_S = 1583 CEFBS_None, // SHL_I64 = 1584 CEFBS_None, // SHL_I64_S = 1585 CEFBS_HasSIMD128, // SHL_I64x2 = 1586 CEFBS_HasSIMD128, // SHL_I64x2_S = 1587 CEFBS_HasSIMD128, // SHL_I8x16 = 1588 CEFBS_HasSIMD128, // SHL_I8x16_S = 1589 CEFBS_HasSIMD128, // SHR_S_I16x8 = 1590 CEFBS_HasSIMD128, // SHR_S_I16x8_S = 1591 CEFBS_None, // SHR_S_I32 = 1592 CEFBS_None, // SHR_S_I32_S = 1593 CEFBS_HasSIMD128, // SHR_S_I32x4 = 1594 CEFBS_HasSIMD128, // SHR_S_I32x4_S = 1595 CEFBS_None, // SHR_S_I64 = 1596 CEFBS_None, // SHR_S_I64_S = 1597 CEFBS_HasSIMD128, // SHR_S_I64x2 = 1598 CEFBS_HasSIMD128, // SHR_S_I64x2_S = 1599 CEFBS_HasSIMD128, // SHR_S_I8x16 = 1600 CEFBS_HasSIMD128, // SHR_S_I8x16_S = 1601 CEFBS_HasSIMD128, // SHR_U_I16x8 = 1602 CEFBS_HasSIMD128, // SHR_U_I16x8_S = 1603 CEFBS_None, // SHR_U_I32 = 1604 CEFBS_None, // SHR_U_I32_S = 1605 CEFBS_HasSIMD128, // SHR_U_I32x4 = 1606 CEFBS_HasSIMD128, // SHR_U_I32x4_S = 1607 CEFBS_None, // SHR_U_I64 = 1608 CEFBS_None, // SHR_U_I64_S = 1609 CEFBS_HasSIMD128, // SHR_U_I64x2 = 1610 CEFBS_HasSIMD128, // SHR_U_I64x2_S = 1611 CEFBS_HasSIMD128, // SHR_U_I8x16 = 1612 CEFBS_HasSIMD128, // SHR_U_I8x16_S = 1613 CEFBS_HasSIMD128, // SHUFFLE = 1614 CEFBS_HasSIMD128, // SHUFFLE_S = 1615 CEFBS_HasRelaxedSIMD, // SIMD_RELAXED_FMAX_F32x4 = 1616 CEFBS_HasRelaxedSIMD, // SIMD_RELAXED_FMAX_F32x4_S = 1617 CEFBS_HasRelaxedSIMD, // SIMD_RELAXED_FMAX_F64x2 = 1618 CEFBS_HasRelaxedSIMD, // SIMD_RELAXED_FMAX_F64x2_S = 1619 CEFBS_HasRelaxedSIMD, // SIMD_RELAXED_FMIN_F32x4 = 1620 CEFBS_HasRelaxedSIMD, // SIMD_RELAXED_FMIN_F32x4_S = 1621 CEFBS_HasRelaxedSIMD, // SIMD_RELAXED_FMIN_F64x2 = 1622 CEFBS_HasRelaxedSIMD, // SIMD_RELAXED_FMIN_F64x2_S = 1623 CEFBS_HasFP16, // SPLAT_F16x8 = 1624 CEFBS_HasFP16, // SPLAT_F16x8_S = 1625 CEFBS_HasSIMD128, // SPLAT_F32x4 = 1626 CEFBS_HasSIMD128, // SPLAT_F32x4_S = 1627 CEFBS_HasSIMD128, // SPLAT_F64x2 = 1628 CEFBS_HasSIMD128, // SPLAT_F64x2_S = 1629 CEFBS_HasSIMD128, // SPLAT_I16x8 = 1630 CEFBS_HasSIMD128, // SPLAT_I16x8_S = 1631 CEFBS_HasSIMD128, // SPLAT_I32x4 = 1632 CEFBS_HasSIMD128, // SPLAT_I32x4_S = 1633 CEFBS_HasSIMD128, // SPLAT_I64x2 = 1634 CEFBS_HasSIMD128, // SPLAT_I64x2_S = 1635 CEFBS_HasSIMD128, // SPLAT_I8x16 = 1636 CEFBS_HasSIMD128, // SPLAT_I8x16_S = 1637 CEFBS_HasSIMD128_HasFP16, // SQRT_F16x8 = 1638 CEFBS_HasSIMD128_HasFP16, // SQRT_F16x8_S = 1639 CEFBS_None, // SQRT_F32 = 1640 CEFBS_None, // SQRT_F32_S = 1641 CEFBS_HasSIMD128, // SQRT_F32x4 = 1642 CEFBS_HasSIMD128, // SQRT_F32x4_S = 1643 CEFBS_None, // SQRT_F64 = 1644 CEFBS_None, // SQRT_F64_S = 1645 CEFBS_HasSIMD128, // SQRT_F64x2 = 1646 CEFBS_HasSIMD128, // SQRT_F64x2_S = 1647 CEFBS_None, // STORE16_I32_A32 = 1648 CEFBS_None, // STORE16_I32_A32_S = 1649 CEFBS_None, // STORE16_I32_A64 = 1650 CEFBS_None, // STORE16_I32_A64_S = 1651 CEFBS_None, // STORE16_I64_A32 = 1652 CEFBS_None, // STORE16_I64_A32_S = 1653 CEFBS_None, // STORE16_I64_A64 = 1654 CEFBS_None, // STORE16_I64_A64_S = 1655 CEFBS_None, // STORE32_I64_A32 = 1656 CEFBS_None, // STORE32_I64_A32_S = 1657 CEFBS_None, // STORE32_I64_A64 = 1658 CEFBS_None, // STORE32_I64_A64_S = 1659 CEFBS_None, // STORE8_I32_A32 = 1660 CEFBS_None, // STORE8_I32_A32_S = 1661 CEFBS_None, // STORE8_I32_A64 = 1662 CEFBS_None, // STORE8_I32_A64_S = 1663 CEFBS_None, // STORE8_I64_A32 = 1664 CEFBS_None, // STORE8_I64_A32_S = 1665 CEFBS_None, // STORE8_I64_A64 = 1666 CEFBS_None, // STORE8_I64_A64_S = 1667 CEFBS_HasFP16, // STORE_F16_F32_A32 = 1668 CEFBS_HasFP16, // STORE_F16_F32_A32_S = 1669 CEFBS_HasFP16, // STORE_F16_F32_A64 = 1670 CEFBS_HasFP16, // STORE_F16_F32_A64_S = 1671 CEFBS_None, // STORE_F32_A32 = 1672 CEFBS_None, // STORE_F32_A32_S = 1673 CEFBS_None, // STORE_F32_A64 = 1674 CEFBS_None, // STORE_F32_A64_S = 1675 CEFBS_None, // STORE_F64_A32 = 1676 CEFBS_None, // STORE_F64_A32_S = 1677 CEFBS_None, // STORE_F64_A64 = 1678 CEFBS_None, // STORE_F64_A64_S = 1679 CEFBS_None, // STORE_I32_A32 = 1680 CEFBS_None, // STORE_I32_A32_S = 1681 CEFBS_None, // STORE_I32_A64 = 1682 CEFBS_None, // STORE_I32_A64_S = 1683 CEFBS_None, // STORE_I64_A32 = 1684 CEFBS_None, // STORE_I64_A32_S = 1685 CEFBS_None, // STORE_I64_A64 = 1686 CEFBS_None, // STORE_I64_A64_S = 1687 CEFBS_HasSIMD128, // STORE_LANE_I16x8_A32 = 1688 CEFBS_HasSIMD128, // STORE_LANE_I16x8_A32_S = 1689 CEFBS_HasSIMD128, // STORE_LANE_I16x8_A64 = 1690 CEFBS_HasSIMD128, // STORE_LANE_I16x8_A64_S = 1691 CEFBS_HasSIMD128, // STORE_LANE_I32x4_A32 = 1692 CEFBS_HasSIMD128, // STORE_LANE_I32x4_A32_S = 1693 CEFBS_HasSIMD128, // STORE_LANE_I32x4_A64 = 1694 CEFBS_HasSIMD128, // STORE_LANE_I32x4_A64_S = 1695 CEFBS_HasSIMD128, // STORE_LANE_I64x2_A32 = 1696 CEFBS_HasSIMD128, // STORE_LANE_I64x2_A32_S = 1697 CEFBS_HasSIMD128, // STORE_LANE_I64x2_A64 = 1698 CEFBS_HasSIMD128, // STORE_LANE_I64x2_A64_S = 1699 CEFBS_HasSIMD128, // STORE_LANE_I8x16_A32 = 1700 CEFBS_HasSIMD128, // STORE_LANE_I8x16_A32_S = 1701 CEFBS_HasSIMD128, // STORE_LANE_I8x16_A64 = 1702 CEFBS_HasSIMD128, // STORE_LANE_I8x16_A64_S = 1703 CEFBS_HasSIMD128, // STORE_V128_A32 = 1704 CEFBS_HasSIMD128, // STORE_V128_A32_S = 1705 CEFBS_HasSIMD128, // STORE_V128_A64 = 1706 CEFBS_HasSIMD128, // STORE_V128_A64_S = 1707 CEFBS_HasSIMD128_HasFP16, // SUB_F16x8 = 1708 CEFBS_HasSIMD128_HasFP16, // SUB_F16x8_S = 1709 CEFBS_None, // SUB_F32 = 1710 CEFBS_None, // SUB_F32_S = 1711 CEFBS_HasSIMD128, // SUB_F32x4 = 1712 CEFBS_HasSIMD128, // SUB_F32x4_S = 1713 CEFBS_None, // SUB_F64 = 1714 CEFBS_None, // SUB_F64_S = 1715 CEFBS_HasSIMD128, // SUB_F64x2 = 1716 CEFBS_HasSIMD128, // SUB_F64x2_S = 1717 CEFBS_HasSIMD128, // SUB_I16x8 = 1718 CEFBS_HasSIMD128, // SUB_I16x8_S = 1719 CEFBS_None, // SUB_I32 = 1720 CEFBS_None, // SUB_I32_S = 1721 CEFBS_HasSIMD128, // SUB_I32x4 = 1722 CEFBS_HasSIMD128, // SUB_I32x4_S = 1723 CEFBS_None, // SUB_I64 = 1724 CEFBS_None, // SUB_I64_S = 1725 CEFBS_HasSIMD128, // SUB_I64x2 = 1726 CEFBS_HasSIMD128, // SUB_I64x2_S = 1727 CEFBS_HasSIMD128, // SUB_I8x16 = 1728 CEFBS_HasSIMD128, // SUB_I8x16_S = 1729 CEFBS_HasSIMD128, // SUB_SAT_S_I16x8 = 1730 CEFBS_HasSIMD128, // SUB_SAT_S_I16x8_S = 1731 CEFBS_HasSIMD128, // SUB_SAT_S_I8x16 = 1732 CEFBS_HasSIMD128, // SUB_SAT_S_I8x16_S = 1733 CEFBS_HasSIMD128, // SUB_SAT_U_I16x8 = 1734 CEFBS_HasSIMD128, // SUB_SAT_U_I16x8_S = 1735 CEFBS_HasSIMD128, // SUB_SAT_U_I8x16 = 1736 CEFBS_HasSIMD128, // SUB_SAT_U_I8x16_S = 1737 CEFBS_HasSIMD128, // SWIZZLE = 1738 CEFBS_HasSIMD128, // SWIZZLE_S = 1739 CEFBS_HasReferenceTypes, // TABLE_COPY = 1740 CEFBS_HasReferenceTypes, // TABLE_COPY_S = 1741 CEFBS_HasReferenceTypes_HasExceptionHandling, // TABLE_FILL_EXNREF = 1742 CEFBS_HasReferenceTypes_HasExceptionHandling, // TABLE_FILL_EXNREF_S = 1743 CEFBS_HasReferenceTypes, // TABLE_FILL_EXTERNREF = 1744 CEFBS_HasReferenceTypes, // TABLE_FILL_EXTERNREF_S = 1745 CEFBS_HasReferenceTypes, // TABLE_FILL_FUNCREF = 1746 CEFBS_HasReferenceTypes, // TABLE_FILL_FUNCREF_S = 1747 CEFBS_HasReferenceTypes_HasExceptionHandling, // TABLE_GET_EXNREF = 1748 CEFBS_HasReferenceTypes_HasExceptionHandling, // TABLE_GET_EXNREF_S = 1749 CEFBS_HasReferenceTypes, // TABLE_GET_EXTERNREF = 1750 CEFBS_HasReferenceTypes, // TABLE_GET_EXTERNREF_S = 1751 CEFBS_HasReferenceTypes, // TABLE_GET_FUNCREF = 1752 CEFBS_HasReferenceTypes, // TABLE_GET_FUNCREF_S = 1753 CEFBS_HasReferenceTypes_HasExceptionHandling, // TABLE_GROW_EXNREF = 1754 CEFBS_HasReferenceTypes_HasExceptionHandling, // TABLE_GROW_EXNREF_S = 1755 CEFBS_HasReferenceTypes, // TABLE_GROW_EXTERNREF = 1756 CEFBS_HasReferenceTypes, // TABLE_GROW_EXTERNREF_S = 1757 CEFBS_HasReferenceTypes, // TABLE_GROW_FUNCREF = 1758 CEFBS_HasReferenceTypes, // TABLE_GROW_FUNCREF_S = 1759 CEFBS_HasReferenceTypes_HasExceptionHandling, // TABLE_SET_EXNREF = 1760 CEFBS_HasReferenceTypes_HasExceptionHandling, // TABLE_SET_EXNREF_S = 1761 CEFBS_HasReferenceTypes, // TABLE_SET_EXTERNREF = 1762 CEFBS_HasReferenceTypes, // TABLE_SET_EXTERNREF_S = 1763 CEFBS_HasReferenceTypes, // TABLE_SET_FUNCREF = 1764 CEFBS_HasReferenceTypes, // TABLE_SET_FUNCREF_S = 1765 CEFBS_HasReferenceTypes, // TABLE_SIZE = 1766 CEFBS_HasReferenceTypes, // TABLE_SIZE_S = 1767 CEFBS_HasReferenceTypes_HasExceptionHandling, // TEE_EXNREF = 1768 CEFBS_HasReferenceTypes_HasExceptionHandling, // TEE_EXNREF_S = 1769 CEFBS_HasReferenceTypes, // TEE_EXTERNREF = 1770 CEFBS_HasReferenceTypes, // TEE_EXTERNREF_S = 1771 CEFBS_None, // TEE_F32 = 1772 CEFBS_None, // TEE_F32_S = 1773 CEFBS_None, // TEE_F64 = 1774 CEFBS_None, // TEE_F64_S = 1775 CEFBS_HasReferenceTypes, // TEE_FUNCREF = 1776 CEFBS_HasReferenceTypes, // TEE_FUNCREF_S = 1777 CEFBS_None, // TEE_I32 = 1778 CEFBS_None, // TEE_I32_S = 1779 CEFBS_None, // TEE_I64 = 1780 CEFBS_None, // TEE_I64_S = 1781 CEFBS_HasSIMD128, // TEE_V128 = 1782 CEFBS_HasSIMD128, // TEE_V128_S = 1783 CEFBS_HasExceptionHandling, // THROW = 1784 CEFBS_HasExceptionHandling, // THROW_S = 1785 CEFBS_HasSIMD128_HasFP16, // TRUNC_F16x8 = 1786 CEFBS_HasSIMD128_HasFP16, // TRUNC_F16x8_S = 1787 CEFBS_None, // TRUNC_F32 = 1788 CEFBS_None, // TRUNC_F32_S = 1789 CEFBS_HasSIMD128, // TRUNC_F32x4 = 1790 CEFBS_HasSIMD128, // TRUNC_F32x4_S = 1791 CEFBS_None, // TRUNC_F64 = 1792 CEFBS_None, // TRUNC_F64_S = 1793 CEFBS_HasSIMD128, // TRUNC_F64x2 = 1794 CEFBS_HasSIMD128, // TRUNC_F64x2_S = 1795 CEFBS_HasExceptionHandling, // TRY = 1796 CEFBS_HasExceptionHandling, // TRY_S = 1797 CEFBS_None, // UNREACHABLE = 1798 CEFBS_None, // UNREACHABLE_S = 1799 CEFBS_HasSIMD128, // XOR = 1800 CEFBS_None, // XOR_I32 = 1801 CEFBS_None, // XOR_I32_S = 1802 CEFBS_None, // XOR_I64 = 1803 CEFBS_None, // XOR_I64_S = 1804 CEFBS_HasSIMD128, // XOR_S = 1805 CEFBS_None, // anonymous_8166MEMORY_GROW_A32 = 1806 CEFBS_None, // anonymous_8166MEMORY_GROW_A32_S = 1807 CEFBS_None, // anonymous_8166MEMORY_SIZE_A32 = 1808 CEFBS_None, // anonymous_8166MEMORY_SIZE_A32_S = 1809 CEFBS_None, // anonymous_8167MEMORY_GROW_A64 = 1810 CEFBS_None, // anonymous_8167MEMORY_GROW_A64_S = 1811 CEFBS_None, // anonymous_8167MEMORY_SIZE_A64 = 1812 CEFBS_None, // anonymous_8167MEMORY_SIZE_A64_S = 1813 CEFBS_HasBulkMemory, // anonymous_8883DATA_DROP = 1814 CEFBS_HasBulkMemory, // anonymous_8883DATA_DROP_S = 1815 CEFBS_HasBulkMemory, // anonymous_8883MEMORY_COPY_A32 = 1816 CEFBS_HasBulkMemory, // anonymous_8883MEMORY_COPY_A32_S = 1817 CEFBS_HasBulkMemory, // anonymous_8883MEMORY_FILL_A32 = 1818 CEFBS_HasBulkMemory, // anonymous_8883MEMORY_FILL_A32_S = 1819 CEFBS_HasBulkMemory, // anonymous_8883MEMORY_INIT_A32 = 1820 CEFBS_HasBulkMemory, // anonymous_8883MEMORY_INIT_A32_S = 1821 CEFBS_HasBulkMemory, // anonymous_8884DATA_DROP = 1822 CEFBS_HasBulkMemory, // anonymous_8884DATA_DROP_S = 1823 CEFBS_HasBulkMemory, // anonymous_8884MEMORY_COPY_A64 = 1824 CEFBS_HasBulkMemory, // anonymous_8884MEMORY_COPY_A64_S = 1825 CEFBS_HasBulkMemory, // anonymous_8884MEMORY_FILL_A64 = 1826 CEFBS_HasBulkMemory, // anonymous_8884MEMORY_FILL_A64_S = 1827 CEFBS_HasBulkMemory, // anonymous_8884MEMORY_INIT_A64 = 1828 CEFBS_HasBulkMemory, // anonymous_8884MEMORY_INIT_A64_S = 1829 CEFBS_HasSIMD128, // convert_low_s_F64x2 = 1830 CEFBS_HasSIMD128, // convert_low_s_F64x2_S = 1831 CEFBS_HasSIMD128, // convert_low_u_F64x2 = 1832 CEFBS_HasSIMD128, // convert_low_u_F64x2_S = 1833 CEFBS_HasSIMD128, // demote_zero_F32x4 = 1834 CEFBS_HasSIMD128, // demote_zero_F32x4_S = 1835 CEFBS_HasSIMD128, // extend_high_s_I16x8 = 1836 CEFBS_HasSIMD128, // extend_high_s_I16x8_S = 1837 CEFBS_HasSIMD128, // extend_high_s_I32x4 = 1838 CEFBS_HasSIMD128, // extend_high_s_I32x4_S = 1839 CEFBS_HasSIMD128, // extend_high_s_I64x2 = 1840 CEFBS_HasSIMD128, // extend_high_s_I64x2_S = 1841 CEFBS_HasSIMD128, // extend_high_u_I16x8 = 1842 CEFBS_HasSIMD128, // extend_high_u_I16x8_S = 1843 CEFBS_HasSIMD128, // extend_high_u_I32x4 = 1844 CEFBS_HasSIMD128, // extend_high_u_I32x4_S = 1845 CEFBS_HasSIMD128, // extend_high_u_I64x2 = 1846 CEFBS_HasSIMD128, // extend_high_u_I64x2_S = 1847 CEFBS_HasSIMD128, // extend_low_s_I16x8 = 1848 CEFBS_HasSIMD128, // extend_low_s_I16x8_S = 1849 CEFBS_HasSIMD128, // extend_low_s_I32x4 = 1850 CEFBS_HasSIMD128, // extend_low_s_I32x4_S = 1851 CEFBS_HasSIMD128, // extend_low_s_I64x2 = 1852 CEFBS_HasSIMD128, // extend_low_s_I64x2_S = 1853 CEFBS_HasSIMD128, // extend_low_u_I16x8 = 1854 CEFBS_HasSIMD128, // extend_low_u_I16x8_S = 1855 CEFBS_HasSIMD128, // extend_low_u_I32x4 = 1856 CEFBS_HasSIMD128, // extend_low_u_I32x4_S = 1857 CEFBS_HasSIMD128, // extend_low_u_I64x2 = 1858 CEFBS_HasSIMD128, // extend_low_u_I64x2_S = 1859 CEFBS_HasSIMD128_HasFP16, // fp_to_sint_I16x8 = 1860 CEFBS_HasSIMD128_HasFP16, // fp_to_sint_I16x8_S = 1861 CEFBS_HasSIMD128, // fp_to_sint_I32x4 = 1862 CEFBS_HasSIMD128, // fp_to_sint_I32x4_S = 1863 CEFBS_HasSIMD128_HasFP16, // fp_to_uint_I16x8 = 1864 CEFBS_HasSIMD128_HasFP16, // fp_to_uint_I16x8_S = 1865 CEFBS_HasSIMD128, // fp_to_uint_I32x4 = 1866 CEFBS_HasSIMD128, // fp_to_uint_I32x4_S = 1867 CEFBS_HasSIMD128, // int_wasm_extadd_pairwise_signed_I16x8 = 1868 CEFBS_HasSIMD128, // int_wasm_extadd_pairwise_signed_I16x8_S = 1869 CEFBS_HasSIMD128, // int_wasm_extadd_pairwise_signed_I32x4 = 1870 CEFBS_HasSIMD128, // int_wasm_extadd_pairwise_signed_I32x4_S = 1871 CEFBS_HasSIMD128, // int_wasm_extadd_pairwise_unsigned_I16x8 = 1872 CEFBS_HasSIMD128, // int_wasm_extadd_pairwise_unsigned_I16x8_S = 1873 CEFBS_HasSIMD128, // int_wasm_extadd_pairwise_unsigned_I32x4 = 1874 CEFBS_HasSIMD128, // int_wasm_extadd_pairwise_unsigned_I32x4_S = 1875 CEFBS_HasRelaxedSIMD, // int_wasm_relaxed_trunc_signed_I32x4 = 1876 CEFBS_HasRelaxedSIMD, // int_wasm_relaxed_trunc_signed_I32x4_S = 1877 CEFBS_HasRelaxedSIMD, // int_wasm_relaxed_trunc_signed_zero_I32x4 = 1878 CEFBS_HasRelaxedSIMD, // int_wasm_relaxed_trunc_signed_zero_I32x4_S = 1879 CEFBS_HasRelaxedSIMD, // int_wasm_relaxed_trunc_unsigned_I32x4 = 1880 CEFBS_HasRelaxedSIMD, // int_wasm_relaxed_trunc_unsigned_I32x4_S = 1881 CEFBS_HasRelaxedSIMD, // int_wasm_relaxed_trunc_unsigned_zero_I32x4 = 1882 CEFBS_HasRelaxedSIMD, // int_wasm_relaxed_trunc_unsigned_zero_I32x4_S = 1883 CEFBS_HasSIMD128, // promote_low_F64x2 = 1884 CEFBS_HasSIMD128, // promote_low_F64x2_S = 1885 CEFBS_HasSIMD128_HasFP16, // sint_to_fp_F16x8 = 1886 CEFBS_HasSIMD128_HasFP16, // sint_to_fp_F16x8_S = 1887 CEFBS_HasSIMD128, // sint_to_fp_F32x4 = 1888 CEFBS_HasSIMD128, // sint_to_fp_F32x4_S = 1889 CEFBS_HasSIMD128, // trunc_sat_zero_s_I32x4 = 1890 CEFBS_HasSIMD128, // trunc_sat_zero_s_I32x4_S = 1891 CEFBS_HasSIMD128, // trunc_sat_zero_u_I32x4 = 1892 CEFBS_HasSIMD128, // trunc_sat_zero_u_I32x4_S = 1893 CEFBS_HasSIMD128_HasFP16, // uint_to_fp_F16x8 = 1894 CEFBS_HasSIMD128_HasFP16, // uint_to_fp_F16x8_S = 1895 CEFBS_HasSIMD128, // uint_to_fp_F32x4 = 1896 CEFBS_HasSIMD128, // uint_to_fp_F32x4_S = 1897 }; assert(Opcode < 1898); return FeatureBitsets[RequiredFeaturesRefs[Opcode]]; } } // end namespace WebAssembly_MC } // end namespace llvm #endif // GET_COMPUTE_FEATURES #ifdef GET_AVAILABLE_OPCODE_CHECKER #undef GET_AVAILABLE_OPCODE_CHECKER namespace llvm { namespace WebAssembly_MC { bool isOpcodeAvailable(unsigned Opcode, const FeatureBitset &Features) { FeatureBitset AvailableFeatures = computeAvailableFeatures(Features); FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode); FeatureBitset MissingFeatures = (AvailableFeatures & RequiredFeatures) ^ RequiredFeatures; return !MissingFeatures.any(); } } // end namespace WebAssembly_MC } // end namespace llvm #endif // GET_AVAILABLE_OPCODE_CHECKER #ifdef ENABLE_INSTR_PREDICATE_VERIFIER #undef ENABLE_INSTR_PREDICATE_VERIFIER #include <sstream> namespace llvm { namespace WebAssembly_MC { #ifndef NDEBUG static const char *SubtargetFeatureNames[] = { "Feature_HasAtomics", "Feature_HasBulkMemory", "Feature_HasExceptionHandling", "Feature_HasExtendedConst", "Feature_HasFP16", "Feature_HasMultiMemory", "Feature_HasMultivalue", "Feature_HasMutableGlobals", "Feature_HasNontrappingFPToInt", "Feature_HasReferenceTypes", "Feature_HasRelaxedSIMD", "Feature_HasSIMD128", "Feature_HasSignExt", "Feature_HasTailCall", "Feature_NotHasNontrappingFPToInt", nullptr }; #endif // NDEBUG void verifyInstructionPredicates( unsigned Opcode, const FeatureBitset &Features) { #ifndef NDEBUG FeatureBitset AvailableFeatures = computeAvailableFeatures(Features); FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode); FeatureBitset MissingFeatures = (AvailableFeatures & RequiredFeatures) ^ RequiredFeatures; if (MissingFeatures.any()) { std::ostringstream Msg; Msg << "Attempting to emit " << &WebAssemblyInstrNameData[WebAssemblyInstrNameIndices[Opcode]] << " instruction but the "; for (unsigned i = 0, e = MissingFeatures.size(); i != e; ++i) if (MissingFeatures.test(i)) Msg << SubtargetFeatureNames[i] << " "; Msg << "predicate(s) are not met"; report_fatal_error(Msg.str().c_str()); } #endif // NDEBUG } } // end namespace WebAssembly_MC } // end namespace llvm #endif // ENABLE_INSTR_PREDICATE_VERIFIER #ifdef GET_INSTRMAP_INFO #undef GET_INSTRMAP_INFO namespace llvm { namespace WebAssembly { enum IsWasm64 { IsWasm64_1 }; enum StackBased { StackBased_0, StackBased_1 }; // getRegisterOpcode LLVM_READONLY int getRegisterOpcode(uint16_t Opcode) { static const uint16_t getRegisterOpcodeTable[][2] = { { WebAssembly::CALL_PARAMS_S, WebAssembly::CALL_PARAMS }, { WebAssembly::CALL_RESULTS_S, WebAssembly::CALL_RESULTS }, { WebAssembly::CATCHRET_S, WebAssembly::CATCHRET }, { WebAssembly::CLEANUPRET_S, WebAssembly::CLEANUPRET }, { WebAssembly::COMPILER_FENCE_S, WebAssembly::COMPILER_FENCE }, { WebAssembly::RET_CALL_RESULTS_S, WebAssembly::RET_CALL_RESULTS }, { WebAssembly::ABS_F16x8_S, WebAssembly::ABS_F16x8 }, { WebAssembly::ABS_F32_S, WebAssembly::ABS_F32 }, { WebAssembly::ABS_F32x4_S, WebAssembly::ABS_F32x4 }, { WebAssembly::ABS_F64_S, WebAssembly::ABS_F64 }, { WebAssembly::ABS_F64x2_S, WebAssembly::ABS_F64x2 }, { WebAssembly::ABS_I16x8_S, WebAssembly::ABS_I16x8 }, { WebAssembly::ABS_I32x4_S, WebAssembly::ABS_I32x4 }, { WebAssembly::ABS_I64x2_S, WebAssembly::ABS_I64x2 }, { WebAssembly::ABS_I8x16_S, WebAssembly::ABS_I8x16 }, { WebAssembly::ADD_F16x8_S, WebAssembly::ADD_F16x8 }, { WebAssembly::ADD_F32_S, WebAssembly::ADD_F32 }, { WebAssembly::ADD_F32x4_S, WebAssembly::ADD_F32x4 }, { WebAssembly::ADD_F64_S, WebAssembly::ADD_F64 }, { WebAssembly::ADD_F64x2_S, WebAssembly::ADD_F64x2 }, { WebAssembly::ADD_I16x8_S, WebAssembly::ADD_I16x8 }, { WebAssembly::ADD_I32_S, WebAssembly::ADD_I32 }, { WebAssembly::ADD_I32x4_S, WebAssembly::ADD_I32x4 }, { WebAssembly::ADD_I64_S, WebAssembly::ADD_I64 }, { WebAssembly::ADD_I64x2_S, WebAssembly::ADD_I64x2 }, { WebAssembly::ADD_I8x16_S, WebAssembly::ADD_I8x16 }, { WebAssembly::ADD_SAT_S_I16x8_S, WebAssembly::ADD_SAT_S_I16x8 }, { WebAssembly::ADD_SAT_S_I8x16_S, WebAssembly::ADD_SAT_S_I8x16 }, { WebAssembly::ADD_SAT_U_I16x8_S, WebAssembly::ADD_SAT_U_I16x8 }, { WebAssembly::ADD_SAT_U_I8x16_S, WebAssembly::ADD_SAT_U_I8x16 }, { WebAssembly::ADJCALLSTACKDOWN_S, WebAssembly::ADJCALLSTACKDOWN }, { WebAssembly::ADJCALLSTACKUP_S, WebAssembly::ADJCALLSTACKUP }, { WebAssembly::ALLTRUE_I16x8_S, WebAssembly::ALLTRUE_I16x8 }, { WebAssembly::ALLTRUE_I32x4_S, WebAssembly::ALLTRUE_I32x4 }, { WebAssembly::ALLTRUE_I64x2_S, WebAssembly::ALLTRUE_I64x2 }, { WebAssembly::ALLTRUE_I8x16_S, WebAssembly::ALLTRUE_I8x16 }, { WebAssembly::ANDNOT_S, WebAssembly::ANDNOT }, { WebAssembly::AND_I32_S, WebAssembly::AND_I32 }, { WebAssembly::AND_I64_S, WebAssembly::AND_I64 }, { WebAssembly::AND_S, WebAssembly::AND }, { WebAssembly::ANYTRUE_S, WebAssembly::ANYTRUE }, { WebAssembly::ARGUMENT_exnref_S, WebAssembly::ARGUMENT_exnref }, { WebAssembly::ARGUMENT_externref_S, WebAssembly::ARGUMENT_externref }, { WebAssembly::ARGUMENT_f32_S, WebAssembly::ARGUMENT_f32 }, { WebAssembly::ARGUMENT_f64_S, WebAssembly::ARGUMENT_f64 }, { WebAssembly::ARGUMENT_funcref_S, WebAssembly::ARGUMENT_funcref }, { WebAssembly::ARGUMENT_i32_S, WebAssembly::ARGUMENT_i32 }, { WebAssembly::ARGUMENT_i64_S, WebAssembly::ARGUMENT_i64 }, { WebAssembly::ARGUMENT_v16i8_S, WebAssembly::ARGUMENT_v16i8 }, { WebAssembly::ARGUMENT_v2f64_S, WebAssembly::ARGUMENT_v2f64 }, { WebAssembly::ARGUMENT_v2i64_S, WebAssembly::ARGUMENT_v2i64 }, { WebAssembly::ARGUMENT_v4f32_S, WebAssembly::ARGUMENT_v4f32 }, { WebAssembly::ARGUMENT_v4i32_S, WebAssembly::ARGUMENT_v4i32 }, { WebAssembly::ARGUMENT_v8f16_S, WebAssembly::ARGUMENT_v8f16 }, { WebAssembly::ARGUMENT_v8i16_S, WebAssembly::ARGUMENT_v8i16 }, { WebAssembly::ATOMIC_FENCE_S, WebAssembly::ATOMIC_FENCE }, { WebAssembly::ATOMIC_LOAD16_U_I32_A32_S, WebAssembly::ATOMIC_LOAD16_U_I32_A32 }, { WebAssembly::ATOMIC_LOAD16_U_I32_A64_S, WebAssembly::ATOMIC_LOAD16_U_I32_A64 }, { WebAssembly::ATOMIC_LOAD16_U_I64_A32_S, WebAssembly::ATOMIC_LOAD16_U_I64_A32 }, { WebAssembly::ATOMIC_LOAD16_U_I64_A64_S, WebAssembly::ATOMIC_LOAD16_U_I64_A64 }, { WebAssembly::ATOMIC_LOAD32_U_I64_A32_S, WebAssembly::ATOMIC_LOAD32_U_I64_A32 }, { WebAssembly::ATOMIC_LOAD32_U_I64_A64_S, WebAssembly::ATOMIC_LOAD32_U_I64_A64 }, { WebAssembly::ATOMIC_LOAD8_U_I32_A32_S, WebAssembly::ATOMIC_LOAD8_U_I32_A32 }, { WebAssembly::ATOMIC_LOAD8_U_I32_A64_S, WebAssembly::ATOMIC_LOAD8_U_I32_A64 }, { WebAssembly::ATOMIC_LOAD8_U_I64_A32_S, WebAssembly::ATOMIC_LOAD8_U_I64_A32 }, { WebAssembly::ATOMIC_LOAD8_U_I64_A64_S, WebAssembly::ATOMIC_LOAD8_U_I64_A64 }, { WebAssembly::ATOMIC_LOAD_I32_A32_S, WebAssembly::ATOMIC_LOAD_I32_A32 }, { WebAssembly::ATOMIC_LOAD_I32_A64_S, WebAssembly::ATOMIC_LOAD_I32_A64 }, { WebAssembly::ATOMIC_LOAD_I64_A32_S, WebAssembly::ATOMIC_LOAD_I64_A32 }, { WebAssembly::ATOMIC_LOAD_I64_A64_S, WebAssembly::ATOMIC_LOAD_I64_A64 }, { WebAssembly::ATOMIC_RMW16_U_ADD_I32_A32_S, WebAssembly::ATOMIC_RMW16_U_ADD_I32_A32 }, { WebAssembly::ATOMIC_RMW16_U_ADD_I32_A64_S, WebAssembly::ATOMIC_RMW16_U_ADD_I32_A64 }, { WebAssembly::ATOMIC_RMW16_U_ADD_I64_A32_S, WebAssembly::ATOMIC_RMW16_U_ADD_I64_A32 }, { WebAssembly::ATOMIC_RMW16_U_ADD_I64_A64_S, WebAssembly::ATOMIC_RMW16_U_ADD_I64_A64 }, { WebAssembly::ATOMIC_RMW16_U_AND_I32_A32_S, WebAssembly::ATOMIC_RMW16_U_AND_I32_A32 }, { WebAssembly::ATOMIC_RMW16_U_AND_I32_A64_S, WebAssembly::ATOMIC_RMW16_U_AND_I32_A64 }, { WebAssembly::ATOMIC_RMW16_U_AND_I64_A32_S, WebAssembly::ATOMIC_RMW16_U_AND_I64_A32 }, { WebAssembly::ATOMIC_RMW16_U_AND_I64_A64_S, WebAssembly::ATOMIC_RMW16_U_AND_I64_A64 }, { WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I32_A32_S, WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I32_A32 }, { WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I32_A64_S, WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I32_A64 }, { WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I64_A32_S, WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I64_A32 }, { WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I64_A64_S, WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I64_A64 }, { WebAssembly::ATOMIC_RMW16_U_OR_I32_A32_S, WebAssembly::ATOMIC_RMW16_U_OR_I32_A32 }, { WebAssembly::ATOMIC_RMW16_U_OR_I32_A64_S, WebAssembly::ATOMIC_RMW16_U_OR_I32_A64 }, { WebAssembly::ATOMIC_RMW16_U_OR_I64_A32_S, WebAssembly::ATOMIC_RMW16_U_OR_I64_A32 }, { WebAssembly::ATOMIC_RMW16_U_OR_I64_A64_S, WebAssembly::ATOMIC_RMW16_U_OR_I64_A64 }, { WebAssembly::ATOMIC_RMW16_U_SUB_I32_A32_S, WebAssembly::ATOMIC_RMW16_U_SUB_I32_A32 }, { WebAssembly::ATOMIC_RMW16_U_SUB_I32_A64_S, WebAssembly::ATOMIC_RMW16_U_SUB_I32_A64 }, { WebAssembly::ATOMIC_RMW16_U_SUB_I64_A32_S, WebAssembly::ATOMIC_RMW16_U_SUB_I64_A32 }, { WebAssembly::ATOMIC_RMW16_U_SUB_I64_A64_S, WebAssembly::ATOMIC_RMW16_U_SUB_I64_A64 }, { WebAssembly::ATOMIC_RMW16_U_XCHG_I32_A32_S, WebAssembly::ATOMIC_RMW16_U_XCHG_I32_A32 }, { WebAssembly::ATOMIC_RMW16_U_XCHG_I32_A64_S, WebAssembly::ATOMIC_RMW16_U_XCHG_I32_A64 }, { WebAssembly::ATOMIC_RMW16_U_XCHG_I64_A32_S, WebAssembly::ATOMIC_RMW16_U_XCHG_I64_A32 }, { WebAssembly::ATOMIC_RMW16_U_XCHG_I64_A64_S, WebAssembly::ATOMIC_RMW16_U_XCHG_I64_A64 }, { WebAssembly::ATOMIC_RMW16_U_XOR_I32_A32_S, WebAssembly::ATOMIC_RMW16_U_XOR_I32_A32 }, { WebAssembly::ATOMIC_RMW16_U_XOR_I32_A64_S, WebAssembly::ATOMIC_RMW16_U_XOR_I32_A64 }, { WebAssembly::ATOMIC_RMW16_U_XOR_I64_A32_S, WebAssembly::ATOMIC_RMW16_U_XOR_I64_A32 }, { WebAssembly::ATOMIC_RMW16_U_XOR_I64_A64_S, WebAssembly::ATOMIC_RMW16_U_XOR_I64_A64 }, { WebAssembly::ATOMIC_RMW32_U_ADD_I64_A32_S, WebAssembly::ATOMIC_RMW32_U_ADD_I64_A32 }, { WebAssembly::ATOMIC_RMW32_U_ADD_I64_A64_S, WebAssembly::ATOMIC_RMW32_U_ADD_I64_A64 }, { WebAssembly::ATOMIC_RMW32_U_AND_I64_A32_S, WebAssembly::ATOMIC_RMW32_U_AND_I64_A32 }, { WebAssembly::ATOMIC_RMW32_U_AND_I64_A64_S, WebAssembly::ATOMIC_RMW32_U_AND_I64_A64 }, { WebAssembly::ATOMIC_RMW32_U_CMPXCHG_I64_A32_S, WebAssembly::ATOMIC_RMW32_U_CMPXCHG_I64_A32 }, { WebAssembly::ATOMIC_RMW32_U_CMPXCHG_I64_A64_S, WebAssembly::ATOMIC_RMW32_U_CMPXCHG_I64_A64 }, { WebAssembly::ATOMIC_RMW32_U_OR_I64_A32_S, WebAssembly::ATOMIC_RMW32_U_OR_I64_A32 }, { WebAssembly::ATOMIC_RMW32_U_OR_I64_A64_S, WebAssembly::ATOMIC_RMW32_U_OR_I64_A64 }, { WebAssembly::ATOMIC_RMW32_U_SUB_I64_A32_S, WebAssembly::ATOMIC_RMW32_U_SUB_I64_A32 }, { WebAssembly::ATOMIC_RMW32_U_SUB_I64_A64_S, WebAssembly::ATOMIC_RMW32_U_SUB_I64_A64 }, { WebAssembly::ATOMIC_RMW32_U_XCHG_I64_A32_S, WebAssembly::ATOMIC_RMW32_U_XCHG_I64_A32 }, { WebAssembly::ATOMIC_RMW32_U_XCHG_I64_A64_S, WebAssembly::ATOMIC_RMW32_U_XCHG_I64_A64 }, { WebAssembly::ATOMIC_RMW32_U_XOR_I64_A32_S, WebAssembly::ATOMIC_RMW32_U_XOR_I64_A32 }, { WebAssembly::ATOMIC_RMW32_U_XOR_I64_A64_S, WebAssembly::ATOMIC_RMW32_U_XOR_I64_A64 }, { WebAssembly::ATOMIC_RMW8_U_ADD_I32_A32_S, WebAssembly::ATOMIC_RMW8_U_ADD_I32_A32 }, { WebAssembly::ATOMIC_RMW8_U_ADD_I32_A64_S, WebAssembly::ATOMIC_RMW8_U_ADD_I32_A64 }, { WebAssembly::ATOMIC_RMW8_U_ADD_I64_A32_S, WebAssembly::ATOMIC_RMW8_U_ADD_I64_A32 }, { WebAssembly::ATOMIC_RMW8_U_ADD_I64_A64_S, WebAssembly::ATOMIC_RMW8_U_ADD_I64_A64 }, { WebAssembly::ATOMIC_RMW8_U_AND_I32_A32_S, WebAssembly::ATOMIC_RMW8_U_AND_I32_A32 }, { WebAssembly::ATOMIC_RMW8_U_AND_I32_A64_S, WebAssembly::ATOMIC_RMW8_U_AND_I32_A64 }, { WebAssembly::ATOMIC_RMW8_U_AND_I64_A32_S, WebAssembly::ATOMIC_RMW8_U_AND_I64_A32 }, { WebAssembly::ATOMIC_RMW8_U_AND_I64_A64_S, WebAssembly::ATOMIC_RMW8_U_AND_I64_A64 }, { WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I32_A32_S, WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I32_A32 }, { WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I32_A64_S, WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I32_A64 }, { WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I64_A32_S, WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I64_A32 }, { WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I64_A64_S, WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I64_A64 }, { WebAssembly::ATOMIC_RMW8_U_OR_I32_A32_S, WebAssembly::ATOMIC_RMW8_U_OR_I32_A32 }, { WebAssembly::ATOMIC_RMW8_U_OR_I32_A64_S, WebAssembly::ATOMIC_RMW8_U_OR_I32_A64 }, { WebAssembly::ATOMIC_RMW8_U_OR_I64_A32_S, WebAssembly::ATOMIC_RMW8_U_OR_I64_A32 }, { WebAssembly::ATOMIC_RMW8_U_OR_I64_A64_S, WebAssembly::ATOMIC_RMW8_U_OR_I64_A64 }, { WebAssembly::ATOMIC_RMW8_U_SUB_I32_A32_S, WebAssembly::ATOMIC_RMW8_U_SUB_I32_A32 }, { WebAssembly::ATOMIC_RMW8_U_SUB_I32_A64_S, WebAssembly::ATOMIC_RMW8_U_SUB_I32_A64 }, { WebAssembly::ATOMIC_RMW8_U_SUB_I64_A32_S, WebAssembly::ATOMIC_RMW8_U_SUB_I64_A32 }, { WebAssembly::ATOMIC_RMW8_U_SUB_I64_A64_S, WebAssembly::ATOMIC_RMW8_U_SUB_I64_A64 }, { WebAssembly::ATOMIC_RMW8_U_XCHG_I32_A32_S, WebAssembly::ATOMIC_RMW8_U_XCHG_I32_A32 }, { WebAssembly::ATOMIC_RMW8_U_XCHG_I32_A64_S, WebAssembly::ATOMIC_RMW8_U_XCHG_I32_A64 }, { WebAssembly::ATOMIC_RMW8_U_XCHG_I64_A32_S, WebAssembly::ATOMIC_RMW8_U_XCHG_I64_A32 }, { WebAssembly::ATOMIC_RMW8_U_XCHG_I64_A64_S, WebAssembly::ATOMIC_RMW8_U_XCHG_I64_A64 }, { WebAssembly::ATOMIC_RMW8_U_XOR_I32_A32_S, WebAssembly::ATOMIC_RMW8_U_XOR_I32_A32 }, { WebAssembly::ATOMIC_RMW8_U_XOR_I32_A64_S, WebAssembly::ATOMIC_RMW8_U_XOR_I32_A64 }, { WebAssembly::ATOMIC_RMW8_U_XOR_I64_A32_S, WebAssembly::ATOMIC_RMW8_U_XOR_I64_A32 }, { WebAssembly::ATOMIC_RMW8_U_XOR_I64_A64_S, WebAssembly::ATOMIC_RMW8_U_XOR_I64_A64 }, { WebAssembly::ATOMIC_RMW_ADD_I32_A32_S, WebAssembly::ATOMIC_RMW_ADD_I32_A32 }, { WebAssembly::ATOMIC_RMW_ADD_I32_A64_S, WebAssembly::ATOMIC_RMW_ADD_I32_A64 }, { WebAssembly::ATOMIC_RMW_ADD_I64_A32_S, WebAssembly::ATOMIC_RMW_ADD_I64_A32 }, { WebAssembly::ATOMIC_RMW_ADD_I64_A64_S, WebAssembly::ATOMIC_RMW_ADD_I64_A64 }, { WebAssembly::ATOMIC_RMW_AND_I32_A32_S, WebAssembly::ATOMIC_RMW_AND_I32_A32 }, { WebAssembly::ATOMIC_RMW_AND_I32_A64_S, WebAssembly::ATOMIC_RMW_AND_I32_A64 }, { WebAssembly::ATOMIC_RMW_AND_I64_A32_S, WebAssembly::ATOMIC_RMW_AND_I64_A32 }, { WebAssembly::ATOMIC_RMW_AND_I64_A64_S, WebAssembly::ATOMIC_RMW_AND_I64_A64 }, { WebAssembly::ATOMIC_RMW_CMPXCHG_I32_A32_S, WebAssembly::ATOMIC_RMW_CMPXCHG_I32_A32 }, { WebAssembly::ATOMIC_RMW_CMPXCHG_I32_A64_S, WebAssembly::ATOMIC_RMW_CMPXCHG_I32_A64 }, { WebAssembly::ATOMIC_RMW_CMPXCHG_I64_A32_S, WebAssembly::ATOMIC_RMW_CMPXCHG_I64_A32 }, { WebAssembly::ATOMIC_RMW_CMPXCHG_I64_A64_S, WebAssembly::ATOMIC_RMW_CMPXCHG_I64_A64 }, { WebAssembly::ATOMIC_RMW_OR_I32_A32_S, WebAssembly::ATOMIC_RMW_OR_I32_A32 }, { WebAssembly::ATOMIC_RMW_OR_I32_A64_S, WebAssembly::ATOMIC_RMW_OR_I32_A64 }, { WebAssembly::ATOMIC_RMW_OR_I64_A32_S, WebAssembly::ATOMIC_RMW_OR_I64_A32 }, { WebAssembly::ATOMIC_RMW_OR_I64_A64_S, WebAssembly::ATOMIC_RMW_OR_I64_A64 }, { WebAssembly::ATOMIC_RMW_SUB_I32_A32_S, WebAssembly::ATOMIC_RMW_SUB_I32_A32 }, { WebAssembly::ATOMIC_RMW_SUB_I32_A64_S, WebAssembly::ATOMIC_RMW_SUB_I32_A64 }, { WebAssembly::ATOMIC_RMW_SUB_I64_A32_S, WebAssembly::ATOMIC_RMW_SUB_I64_A32 }, { WebAssembly::ATOMIC_RMW_SUB_I64_A64_S, WebAssembly::ATOMIC_RMW_SUB_I64_A64 }, { WebAssembly::ATOMIC_RMW_XCHG_I32_A32_S, WebAssembly::ATOMIC_RMW_XCHG_I32_A32 }, { WebAssembly::ATOMIC_RMW_XCHG_I32_A64_S, WebAssembly::ATOMIC_RMW_XCHG_I32_A64 }, { WebAssembly::ATOMIC_RMW_XCHG_I64_A32_S, WebAssembly::ATOMIC_RMW_XCHG_I64_A32 }, { WebAssembly::ATOMIC_RMW_XCHG_I64_A64_S, WebAssembly::ATOMIC_RMW_XCHG_I64_A64 }, { WebAssembly::ATOMIC_RMW_XOR_I32_A32_S, WebAssembly::ATOMIC_RMW_XOR_I32_A32 }, { WebAssembly::ATOMIC_RMW_XOR_I32_A64_S, WebAssembly::ATOMIC_RMW_XOR_I32_A64 }, { WebAssembly::ATOMIC_RMW_XOR_I64_A32_S, WebAssembly::ATOMIC_RMW_XOR_I64_A32 }, { WebAssembly::ATOMIC_RMW_XOR_I64_A64_S, WebAssembly::ATOMIC_RMW_XOR_I64_A64 }, { WebAssembly::ATOMIC_STORE16_I32_A32_S, WebAssembly::ATOMIC_STORE16_I32_A32 }, { WebAssembly::ATOMIC_STORE16_I32_A64_S, WebAssembly::ATOMIC_STORE16_I32_A64 }, { WebAssembly::ATOMIC_STORE16_I64_A32_S, WebAssembly::ATOMIC_STORE16_I64_A32 }, { WebAssembly::ATOMIC_STORE16_I64_A64_S, WebAssembly::ATOMIC_STORE16_I64_A64 }, { WebAssembly::ATOMIC_STORE32_I64_A32_S, WebAssembly::ATOMIC_STORE32_I64_A32 }, { WebAssembly::ATOMIC_STORE32_I64_A64_S, WebAssembly::ATOMIC_STORE32_I64_A64 }, { WebAssembly::ATOMIC_STORE8_I32_A32_S, WebAssembly::ATOMIC_STORE8_I32_A32 }, { WebAssembly::ATOMIC_STORE8_I32_A64_S, WebAssembly::ATOMIC_STORE8_I32_A64 }, { WebAssembly::ATOMIC_STORE8_I64_A32_S, WebAssembly::ATOMIC_STORE8_I64_A32 }, { WebAssembly::ATOMIC_STORE8_I64_A64_S, WebAssembly::ATOMIC_STORE8_I64_A64 }, { WebAssembly::ATOMIC_STORE_I32_A32_S, WebAssembly::ATOMIC_STORE_I32_A32 }, { WebAssembly::ATOMIC_STORE_I32_A64_S, WebAssembly::ATOMIC_STORE_I32_A64 }, { WebAssembly::ATOMIC_STORE_I64_A32_S, WebAssembly::ATOMIC_STORE_I64_A32 }, { WebAssembly::ATOMIC_STORE_I64_A64_S, WebAssembly::ATOMIC_STORE_I64_A64 }, { WebAssembly::AVGR_U_I16x8_S, WebAssembly::AVGR_U_I16x8 }, { WebAssembly::AVGR_U_I8x16_S, WebAssembly::AVGR_U_I8x16 }, { WebAssembly::BITMASK_I16x8_S, WebAssembly::BITMASK_I16x8 }, { WebAssembly::BITMASK_I32x4_S, WebAssembly::BITMASK_I32x4 }, { WebAssembly::BITMASK_I64x2_S, WebAssembly::BITMASK_I64x2 }, { WebAssembly::BITMASK_I8x16_S, WebAssembly::BITMASK_I8x16 }, { WebAssembly::BITSELECT_S, WebAssembly::BITSELECT }, { WebAssembly::BLOCK_S, WebAssembly::BLOCK }, { WebAssembly::BR_IF_S, WebAssembly::BR_IF }, { WebAssembly::BR_S, WebAssembly::BR }, { WebAssembly::BR_TABLE_I32_S, WebAssembly::BR_TABLE_I32 }, { WebAssembly::BR_TABLE_I64_S, WebAssembly::BR_TABLE_I64 }, { WebAssembly::BR_UNLESS_S, WebAssembly::BR_UNLESS }, { WebAssembly::CALL_INDIRECT_S, WebAssembly::CALL_INDIRECT }, { WebAssembly::CALL_S, WebAssembly::CALL }, { WebAssembly::CATCH_ALL_S, WebAssembly::CATCH_ALL }, { WebAssembly::CATCH_S, WebAssembly::CATCH }, { WebAssembly::CEIL_F16x8_S, WebAssembly::CEIL_F16x8 }, { WebAssembly::CEIL_F32_S, WebAssembly::CEIL_F32 }, { WebAssembly::CEIL_F32x4_S, WebAssembly::CEIL_F32x4 }, { WebAssembly::CEIL_F64_S, WebAssembly::CEIL_F64 }, { WebAssembly::CEIL_F64x2_S, WebAssembly::CEIL_F64x2 }, { WebAssembly::CLZ_I32_S, WebAssembly::CLZ_I32 }, { WebAssembly::CLZ_I64_S, WebAssembly::CLZ_I64 }, { WebAssembly::CONST_F32_S, WebAssembly::CONST_F32 }, { WebAssembly::CONST_F64_S, WebAssembly::CONST_F64 }, { WebAssembly::CONST_I32_S, WebAssembly::CONST_I32 }, { WebAssembly::CONST_I64_S, WebAssembly::CONST_I64 }, { WebAssembly::CONST_V128_F32x4_S, WebAssembly::CONST_V128_F32x4 }, { WebAssembly::CONST_V128_F64x2_S, WebAssembly::CONST_V128_F64x2 }, { WebAssembly::CONST_V128_I16x8_S, WebAssembly::CONST_V128_I16x8 }, { WebAssembly::CONST_V128_I32x4_S, WebAssembly::CONST_V128_I32x4 }, { WebAssembly::CONST_V128_I64x2_S, WebAssembly::CONST_V128_I64x2 }, { WebAssembly::CONST_V128_I8x16_S, WebAssembly::CONST_V128_I8x16 }, { WebAssembly::COPYSIGN_F32_S, WebAssembly::COPYSIGN_F32 }, { WebAssembly::COPYSIGN_F64_S, WebAssembly::COPYSIGN_F64 }, { WebAssembly::COPY_EXNREF_S, WebAssembly::COPY_EXNREF }, { WebAssembly::COPY_EXTERNREF_S, WebAssembly::COPY_EXTERNREF }, { WebAssembly::COPY_F32_S, WebAssembly::COPY_F32 }, { WebAssembly::COPY_F64_S, WebAssembly::COPY_F64 }, { WebAssembly::COPY_FUNCREF_S, WebAssembly::COPY_FUNCREF }, { WebAssembly::COPY_I32_S, WebAssembly::COPY_I32 }, { WebAssembly::COPY_I64_S, WebAssembly::COPY_I64 }, { WebAssembly::COPY_V128_S, WebAssembly::COPY_V128 }, { WebAssembly::CTZ_I32_S, WebAssembly::CTZ_I32 }, { WebAssembly::CTZ_I64_S, WebAssembly::CTZ_I64 }, { WebAssembly::DEBUG_UNREACHABLE_S, WebAssembly::DEBUG_UNREACHABLE }, { WebAssembly::DELEGATE_S, WebAssembly::DELEGATE }, { WebAssembly::DIV_F16x8_S, WebAssembly::DIV_F16x8 }, { WebAssembly::DIV_F32_S, WebAssembly::DIV_F32 }, { WebAssembly::DIV_F32x4_S, WebAssembly::DIV_F32x4 }, { WebAssembly::DIV_F64_S, WebAssembly::DIV_F64 }, { WebAssembly::DIV_F64x2_S, WebAssembly::DIV_F64x2 }, { WebAssembly::DIV_S_I32_S, WebAssembly::DIV_S_I32 }, { WebAssembly::DIV_S_I64_S, WebAssembly::DIV_S_I64 }, { WebAssembly::DIV_U_I32_S, WebAssembly::DIV_U_I32 }, { WebAssembly::DIV_U_I64_S, WebAssembly::DIV_U_I64 }, { WebAssembly::DOT_S, WebAssembly::DOT }, { WebAssembly::DROP_EXNREF_S, WebAssembly::DROP_EXNREF }, { WebAssembly::DROP_EXTERNREF_S, WebAssembly::DROP_EXTERNREF }, { WebAssembly::DROP_F32_S, WebAssembly::DROP_F32 }, { WebAssembly::DROP_F64_S, WebAssembly::DROP_F64 }, { WebAssembly::DROP_FUNCREF_S, WebAssembly::DROP_FUNCREF }, { WebAssembly::DROP_I32_S, WebAssembly::DROP_I32 }, { WebAssembly::DROP_I64_S, WebAssembly::DROP_I64 }, { WebAssembly::DROP_V128_S, WebAssembly::DROP_V128 }, { WebAssembly::ELSE_S, WebAssembly::ELSE }, { WebAssembly::END_BLOCK_S, WebAssembly::END_BLOCK }, { WebAssembly::END_FUNCTION_S, WebAssembly::END_FUNCTION }, { WebAssembly::END_IF_S, WebAssembly::END_IF }, { WebAssembly::END_LOOP_S, WebAssembly::END_LOOP }, { WebAssembly::END_S, WebAssembly::END }, { WebAssembly::END_TRY_S, WebAssembly::END_TRY }, { WebAssembly::EQZ_I32_S, WebAssembly::EQZ_I32 }, { WebAssembly::EQZ_I64_S, WebAssembly::EQZ_I64 }, { WebAssembly::EQ_F16x8_S, WebAssembly::EQ_F16x8 }, { WebAssembly::EQ_F32_S, WebAssembly::EQ_F32 }, { WebAssembly::EQ_F32x4_S, WebAssembly::EQ_F32x4 }, { WebAssembly::EQ_F64_S, WebAssembly::EQ_F64 }, { WebAssembly::EQ_F64x2_S, WebAssembly::EQ_F64x2 }, { WebAssembly::EQ_I16x8_S, WebAssembly::EQ_I16x8 }, { WebAssembly::EQ_I32_S, WebAssembly::EQ_I32 }, { WebAssembly::EQ_I32x4_S, WebAssembly::EQ_I32x4 }, { WebAssembly::EQ_I64_S, WebAssembly::EQ_I64 }, { WebAssembly::EQ_I64x2_S, WebAssembly::EQ_I64x2 }, { WebAssembly::EQ_I8x16_S, WebAssembly::EQ_I8x16 }, { WebAssembly::EXTMUL_HIGH_S_I16x8_S, WebAssembly::EXTMUL_HIGH_S_I16x8 }, { WebAssembly::EXTMUL_HIGH_S_I32x4_S, WebAssembly::EXTMUL_HIGH_S_I32x4 }, { WebAssembly::EXTMUL_HIGH_S_I64x2_S, WebAssembly::EXTMUL_HIGH_S_I64x2 }, { WebAssembly::EXTMUL_HIGH_U_I16x8_S, WebAssembly::EXTMUL_HIGH_U_I16x8 }, { WebAssembly::EXTMUL_HIGH_U_I32x4_S, WebAssembly::EXTMUL_HIGH_U_I32x4 }, { WebAssembly::EXTMUL_HIGH_U_I64x2_S, WebAssembly::EXTMUL_HIGH_U_I64x2 }, { WebAssembly::EXTMUL_LOW_S_I16x8_S, WebAssembly::EXTMUL_LOW_S_I16x8 }, { WebAssembly::EXTMUL_LOW_S_I32x4_S, WebAssembly::EXTMUL_LOW_S_I32x4 }, { WebAssembly::EXTMUL_LOW_S_I64x2_S, WebAssembly::EXTMUL_LOW_S_I64x2 }, { WebAssembly::EXTMUL_LOW_U_I16x8_S, WebAssembly::EXTMUL_LOW_U_I16x8 }, { WebAssembly::EXTMUL_LOW_U_I32x4_S, WebAssembly::EXTMUL_LOW_U_I32x4 }, { WebAssembly::EXTMUL_LOW_U_I64x2_S, WebAssembly::EXTMUL_LOW_U_I64x2 }, { WebAssembly::EXTRACT_LANE_F16x8_S, WebAssembly::EXTRACT_LANE_F16x8 }, { WebAssembly::EXTRACT_LANE_F32x4_S, WebAssembly::EXTRACT_LANE_F32x4 }, { WebAssembly::EXTRACT_LANE_F64x2_S, WebAssembly::EXTRACT_LANE_F64x2 }, { WebAssembly::EXTRACT_LANE_I16x8_s_S, WebAssembly::EXTRACT_LANE_I16x8_s }, { WebAssembly::EXTRACT_LANE_I16x8_u_S, WebAssembly::EXTRACT_LANE_I16x8_u }, { WebAssembly::EXTRACT_LANE_I32x4_S, WebAssembly::EXTRACT_LANE_I32x4 }, { WebAssembly::EXTRACT_LANE_I64x2_S, WebAssembly::EXTRACT_LANE_I64x2 }, { WebAssembly::EXTRACT_LANE_I8x16_s_S, WebAssembly::EXTRACT_LANE_I8x16_s }, { WebAssembly::EXTRACT_LANE_I8x16_u_S, WebAssembly::EXTRACT_LANE_I8x16_u }, { WebAssembly::F32_CONVERT_S_I32_S, WebAssembly::F32_CONVERT_S_I32 }, { WebAssembly::F32_CONVERT_S_I64_S, WebAssembly::F32_CONVERT_S_I64 }, { WebAssembly::F32_CONVERT_U_I32_S, WebAssembly::F32_CONVERT_U_I32 }, { WebAssembly::F32_CONVERT_U_I64_S, WebAssembly::F32_CONVERT_U_I64 }, { WebAssembly::F32_DEMOTE_F64_S, WebAssembly::F32_DEMOTE_F64 }, { WebAssembly::F32_REINTERPRET_I32_S, WebAssembly::F32_REINTERPRET_I32 }, { WebAssembly::F64_CONVERT_S_I32_S, WebAssembly::F64_CONVERT_S_I32 }, { WebAssembly::F64_CONVERT_S_I64_S, WebAssembly::F64_CONVERT_S_I64 }, { WebAssembly::F64_CONVERT_U_I32_S, WebAssembly::F64_CONVERT_U_I32 }, { WebAssembly::F64_CONVERT_U_I64_S, WebAssembly::F64_CONVERT_U_I64 }, { WebAssembly::F64_PROMOTE_F32_S, WebAssembly::F64_PROMOTE_F32 }, { WebAssembly::F64_REINTERPRET_I64_S, WebAssembly::F64_REINTERPRET_I64 }, { WebAssembly::FALLTHROUGH_RETURN_S, WebAssembly::FALLTHROUGH_RETURN }, { WebAssembly::FLOOR_F16x8_S, WebAssembly::FLOOR_F16x8 }, { WebAssembly::FLOOR_F32_S, WebAssembly::FLOOR_F32 }, { WebAssembly::FLOOR_F32x4_S, WebAssembly::FLOOR_F32x4 }, { WebAssembly::FLOOR_F64_S, WebAssembly::FLOOR_F64 }, { WebAssembly::FLOOR_F64x2_S, WebAssembly::FLOOR_F64x2 }, { WebAssembly::FP_TO_SINT_I32_F32_S, WebAssembly::FP_TO_SINT_I32_F32 }, { WebAssembly::FP_TO_SINT_I32_F64_S, WebAssembly::FP_TO_SINT_I32_F64 }, { WebAssembly::FP_TO_SINT_I64_F32_S, WebAssembly::FP_TO_SINT_I64_F32 }, { WebAssembly::FP_TO_SINT_I64_F64_S, WebAssembly::FP_TO_SINT_I64_F64 }, { WebAssembly::FP_TO_UINT_I32_F32_S, WebAssembly::FP_TO_UINT_I32_F32 }, { WebAssembly::FP_TO_UINT_I32_F64_S, WebAssembly::FP_TO_UINT_I32_F64 }, { WebAssembly::FP_TO_UINT_I64_F32_S, WebAssembly::FP_TO_UINT_I64_F32 }, { WebAssembly::FP_TO_UINT_I64_F64_S, WebAssembly::FP_TO_UINT_I64_F64 }, { WebAssembly::GE_F16x8_S, WebAssembly::GE_F16x8 }, { WebAssembly::GE_F32_S, WebAssembly::GE_F32 }, { WebAssembly::GE_F32x4_S, WebAssembly::GE_F32x4 }, { WebAssembly::GE_F64_S, WebAssembly::GE_F64 }, { WebAssembly::GE_F64x2_S, WebAssembly::GE_F64x2 }, { WebAssembly::GE_S_I16x8_S, WebAssembly::GE_S_I16x8 }, { WebAssembly::GE_S_I32_S, WebAssembly::GE_S_I32 }, { WebAssembly::GE_S_I32x4_S, WebAssembly::GE_S_I32x4 }, { WebAssembly::GE_S_I64_S, WebAssembly::GE_S_I64 }, { WebAssembly::GE_S_I64x2_S, WebAssembly::GE_S_I64x2 }, { WebAssembly::GE_S_I8x16_S, WebAssembly::GE_S_I8x16 }, { WebAssembly::GE_U_I16x8_S, WebAssembly::GE_U_I16x8 }, { WebAssembly::GE_U_I32_S, WebAssembly::GE_U_I32 }, { WebAssembly::GE_U_I32x4_S, WebAssembly::GE_U_I32x4 }, { WebAssembly::GE_U_I64_S, WebAssembly::GE_U_I64 }, { WebAssembly::GE_U_I8x16_S, WebAssembly::GE_U_I8x16 }, { WebAssembly::GLOBAL_GET_EXNREF_S, WebAssembly::GLOBAL_GET_EXNREF }, { WebAssembly::GLOBAL_GET_EXTERNREF_S, WebAssembly::GLOBAL_GET_EXTERNREF }, { WebAssembly::GLOBAL_GET_F32_S, WebAssembly::GLOBAL_GET_F32 }, { WebAssembly::GLOBAL_GET_F64_S, WebAssembly::GLOBAL_GET_F64 }, { WebAssembly::GLOBAL_GET_FUNCREF_S, WebAssembly::GLOBAL_GET_FUNCREF }, { WebAssembly::GLOBAL_GET_I32_S, WebAssembly::GLOBAL_GET_I32 }, { WebAssembly::GLOBAL_GET_I64_S, WebAssembly::GLOBAL_GET_I64 }, { WebAssembly::GLOBAL_GET_V128_S, WebAssembly::GLOBAL_GET_V128 }, { WebAssembly::GLOBAL_SET_EXNREF_S, WebAssembly::GLOBAL_SET_EXNREF }, { WebAssembly::GLOBAL_SET_EXTERNREF_S, WebAssembly::GLOBAL_SET_EXTERNREF }, { WebAssembly::GLOBAL_SET_F32_S, WebAssembly::GLOBAL_SET_F32 }, { WebAssembly::GLOBAL_SET_F64_S, WebAssembly::GLOBAL_SET_F64 }, { WebAssembly::GLOBAL_SET_FUNCREF_S, WebAssembly::GLOBAL_SET_FUNCREF }, { WebAssembly::GLOBAL_SET_I32_S, WebAssembly::GLOBAL_SET_I32 }, { WebAssembly::GLOBAL_SET_I64_S, WebAssembly::GLOBAL_SET_I64 }, { WebAssembly::GLOBAL_SET_V128_S, WebAssembly::GLOBAL_SET_V128 }, { WebAssembly::GT_F16x8_S, WebAssembly::GT_F16x8 }, { WebAssembly::GT_F32_S, WebAssembly::GT_F32 }, { WebAssembly::GT_F32x4_S, WebAssembly::GT_F32x4 }, { WebAssembly::GT_F64_S, WebAssembly::GT_F64 }, { WebAssembly::GT_F64x2_S, WebAssembly::GT_F64x2 }, { WebAssembly::GT_S_I16x8_S, WebAssembly::GT_S_I16x8 }, { WebAssembly::GT_S_I32_S, WebAssembly::GT_S_I32 }, { WebAssembly::GT_S_I32x4_S, WebAssembly::GT_S_I32x4 }, { WebAssembly::GT_S_I64_S, WebAssembly::GT_S_I64 }, { WebAssembly::GT_S_I64x2_S, WebAssembly::GT_S_I64x2 }, { WebAssembly::GT_S_I8x16_S, WebAssembly::GT_S_I8x16 }, { WebAssembly::GT_U_I16x8_S, WebAssembly::GT_U_I16x8 }, { WebAssembly::GT_U_I32_S, WebAssembly::GT_U_I32 }, { WebAssembly::GT_U_I32x4_S, WebAssembly::GT_U_I32x4 }, { WebAssembly::GT_U_I64_S, WebAssembly::GT_U_I64 }, { WebAssembly::GT_U_I8x16_S, WebAssembly::GT_U_I8x16 }, { WebAssembly::I32_EXTEND16_S_I32_S, WebAssembly::I32_EXTEND16_S_I32 }, { WebAssembly::I32_EXTEND8_S_I32_S, WebAssembly::I32_EXTEND8_S_I32 }, { WebAssembly::I32_REINTERPRET_F32_S, WebAssembly::I32_REINTERPRET_F32 }, { WebAssembly::I32_TRUNC_S_F32_S, WebAssembly::I32_TRUNC_S_F32 }, { WebAssembly::I32_TRUNC_S_F64_S, WebAssembly::I32_TRUNC_S_F64 }, { WebAssembly::I32_TRUNC_S_SAT_F32_S, WebAssembly::I32_TRUNC_S_SAT_F32 }, { WebAssembly::I32_TRUNC_S_SAT_F64_S, WebAssembly::I32_TRUNC_S_SAT_F64 }, { WebAssembly::I32_TRUNC_U_F32_S, WebAssembly::I32_TRUNC_U_F32 }, { WebAssembly::I32_TRUNC_U_F64_S, WebAssembly::I32_TRUNC_U_F64 }, { WebAssembly::I32_TRUNC_U_SAT_F32_S, WebAssembly::I32_TRUNC_U_SAT_F32 }, { WebAssembly::I32_TRUNC_U_SAT_F64_S, WebAssembly::I32_TRUNC_U_SAT_F64 }, { WebAssembly::I32_WRAP_I64_S, WebAssembly::I32_WRAP_I64 }, { WebAssembly::I64_EXTEND16_S_I64_S, WebAssembly::I64_EXTEND16_S_I64 }, { WebAssembly::I64_EXTEND32_S_I64_S, WebAssembly::I64_EXTEND32_S_I64 }, { WebAssembly::I64_EXTEND8_S_I64_S, WebAssembly::I64_EXTEND8_S_I64 }, { WebAssembly::I64_EXTEND_S_I32_S, WebAssembly::I64_EXTEND_S_I32 }, { WebAssembly::I64_EXTEND_U_I32_S, WebAssembly::I64_EXTEND_U_I32 }, { WebAssembly::I64_REINTERPRET_F64_S, WebAssembly::I64_REINTERPRET_F64 }, { WebAssembly::I64_TRUNC_S_F32_S, WebAssembly::I64_TRUNC_S_F32 }, { WebAssembly::I64_TRUNC_S_F64_S, WebAssembly::I64_TRUNC_S_F64 }, { WebAssembly::I64_TRUNC_S_SAT_F32_S, WebAssembly::I64_TRUNC_S_SAT_F32 }, { WebAssembly::I64_TRUNC_S_SAT_F64_S, WebAssembly::I64_TRUNC_S_SAT_F64 }, { WebAssembly::I64_TRUNC_U_F32_S, WebAssembly::I64_TRUNC_U_F32 }, { WebAssembly::I64_TRUNC_U_F64_S, WebAssembly::I64_TRUNC_U_F64 }, { WebAssembly::I64_TRUNC_U_SAT_F32_S, WebAssembly::I64_TRUNC_U_SAT_F32 }, { WebAssembly::I64_TRUNC_U_SAT_F64_S, WebAssembly::I64_TRUNC_U_SAT_F64 }, { WebAssembly::IF_S, WebAssembly::IF }, { WebAssembly::LANESELECT_I16x8_S, WebAssembly::LANESELECT_I16x8 }, { WebAssembly::LANESELECT_I32x4_S, WebAssembly::LANESELECT_I32x4 }, { WebAssembly::LANESELECT_I64x2_S, WebAssembly::LANESELECT_I64x2 }, { WebAssembly::LANESELECT_I8x16_S, WebAssembly::LANESELECT_I8x16 }, { WebAssembly::LE_F16x8_S, WebAssembly::LE_F16x8 }, { WebAssembly::LE_F32_S, WebAssembly::LE_F32 }, { WebAssembly::LE_F32x4_S, WebAssembly::LE_F32x4 }, { WebAssembly::LE_F64_S, WebAssembly::LE_F64 }, { WebAssembly::LE_F64x2_S, WebAssembly::LE_F64x2 }, { WebAssembly::LE_S_I16x8_S, WebAssembly::LE_S_I16x8 }, { WebAssembly::LE_S_I32_S, WebAssembly::LE_S_I32 }, { WebAssembly::LE_S_I32x4_S, WebAssembly::LE_S_I32x4 }, { WebAssembly::LE_S_I64_S, WebAssembly::LE_S_I64 }, { WebAssembly::LE_S_I64x2_S, WebAssembly::LE_S_I64x2 }, { WebAssembly::LE_S_I8x16_S, WebAssembly::LE_S_I8x16 }, { WebAssembly::LE_U_I16x8_S, WebAssembly::LE_U_I16x8 }, { WebAssembly::LE_U_I32_S, WebAssembly::LE_U_I32 }, { WebAssembly::LE_U_I32x4_S, WebAssembly::LE_U_I32x4 }, { WebAssembly::LE_U_I64_S, WebAssembly::LE_U_I64 }, { WebAssembly::LE_U_I8x16_S, WebAssembly::LE_U_I8x16 }, { WebAssembly::LOAD16_SPLAT_A32_S, WebAssembly::LOAD16_SPLAT_A32 }, { WebAssembly::LOAD16_SPLAT_A64_S, WebAssembly::LOAD16_SPLAT_A64 }, { WebAssembly::LOAD16_S_I32_A32_S, WebAssembly::LOAD16_S_I32_A32 }, { WebAssembly::LOAD16_S_I32_A64_S, WebAssembly::LOAD16_S_I32_A64 }, { WebAssembly::LOAD16_S_I64_A32_S, WebAssembly::LOAD16_S_I64_A32 }, { WebAssembly::LOAD16_S_I64_A64_S, WebAssembly::LOAD16_S_I64_A64 }, { WebAssembly::LOAD16_U_I32_A32_S, WebAssembly::LOAD16_U_I32_A32 }, { WebAssembly::LOAD16_U_I32_A64_S, WebAssembly::LOAD16_U_I32_A64 }, { WebAssembly::LOAD16_U_I64_A32_S, WebAssembly::LOAD16_U_I64_A32 }, { WebAssembly::LOAD16_U_I64_A64_S, WebAssembly::LOAD16_U_I64_A64 }, { WebAssembly::LOAD32_SPLAT_A32_S, WebAssembly::LOAD32_SPLAT_A32 }, { WebAssembly::LOAD32_SPLAT_A64_S, WebAssembly::LOAD32_SPLAT_A64 }, { WebAssembly::LOAD32_S_I64_A32_S, WebAssembly::LOAD32_S_I64_A32 }, { WebAssembly::LOAD32_S_I64_A64_S, WebAssembly::LOAD32_S_I64_A64 }, { WebAssembly::LOAD32_U_I64_A32_S, WebAssembly::LOAD32_U_I64_A32 }, { WebAssembly::LOAD32_U_I64_A64_S, WebAssembly::LOAD32_U_I64_A64 }, { WebAssembly::LOAD64_SPLAT_A32_S, WebAssembly::LOAD64_SPLAT_A32 }, { WebAssembly::LOAD64_SPLAT_A64_S, WebAssembly::LOAD64_SPLAT_A64 }, { WebAssembly::LOAD8_SPLAT_A32_S, WebAssembly::LOAD8_SPLAT_A32 }, { WebAssembly::LOAD8_SPLAT_A64_S, WebAssembly::LOAD8_SPLAT_A64 }, { WebAssembly::LOAD8_S_I32_A32_S, WebAssembly::LOAD8_S_I32_A32 }, { WebAssembly::LOAD8_S_I32_A64_S, WebAssembly::LOAD8_S_I32_A64 }, { WebAssembly::LOAD8_S_I64_A32_S, WebAssembly::LOAD8_S_I64_A32 }, { WebAssembly::LOAD8_S_I64_A64_S, WebAssembly::LOAD8_S_I64_A64 }, { WebAssembly::LOAD8_U_I32_A32_S, WebAssembly::LOAD8_U_I32_A32 }, { WebAssembly::LOAD8_U_I32_A64_S, WebAssembly::LOAD8_U_I32_A64 }, { WebAssembly::LOAD8_U_I64_A32_S, WebAssembly::LOAD8_U_I64_A32 }, { WebAssembly::LOAD8_U_I64_A64_S, WebAssembly::LOAD8_U_I64_A64 }, { WebAssembly::LOAD_EXTEND_S_I16x8_A32_S, WebAssembly::LOAD_EXTEND_S_I16x8_A32 }, { WebAssembly::LOAD_EXTEND_S_I16x8_A64_S, WebAssembly::LOAD_EXTEND_S_I16x8_A64 }, { WebAssembly::LOAD_EXTEND_S_I32x4_A32_S, WebAssembly::LOAD_EXTEND_S_I32x4_A32 }, { WebAssembly::LOAD_EXTEND_S_I32x4_A64_S, WebAssembly::LOAD_EXTEND_S_I32x4_A64 }, { WebAssembly::LOAD_EXTEND_S_I64x2_A32_S, WebAssembly::LOAD_EXTEND_S_I64x2_A32 }, { WebAssembly::LOAD_EXTEND_S_I64x2_A64_S, WebAssembly::LOAD_EXTEND_S_I64x2_A64 }, { WebAssembly::LOAD_EXTEND_U_I16x8_A32_S, WebAssembly::LOAD_EXTEND_U_I16x8_A32 }, { WebAssembly::LOAD_EXTEND_U_I16x8_A64_S, WebAssembly::LOAD_EXTEND_U_I16x8_A64 }, { WebAssembly::LOAD_EXTEND_U_I32x4_A32_S, WebAssembly::LOAD_EXTEND_U_I32x4_A32 }, { WebAssembly::LOAD_EXTEND_U_I32x4_A64_S, WebAssembly::LOAD_EXTEND_U_I32x4_A64 }, { WebAssembly::LOAD_EXTEND_U_I64x2_A32_S, WebAssembly::LOAD_EXTEND_U_I64x2_A32 }, { WebAssembly::LOAD_EXTEND_U_I64x2_A64_S, WebAssembly::LOAD_EXTEND_U_I64x2_A64 }, { WebAssembly::LOAD_F16_F32_A32_S, WebAssembly::LOAD_F16_F32_A32 }, { WebAssembly::LOAD_F16_F32_A64_S, WebAssembly::LOAD_F16_F32_A64 }, { WebAssembly::LOAD_F32_A32_S, WebAssembly::LOAD_F32_A32 }, { WebAssembly::LOAD_F32_A64_S, WebAssembly::LOAD_F32_A64 }, { WebAssembly::LOAD_F64_A32_S, WebAssembly::LOAD_F64_A32 }, { WebAssembly::LOAD_F64_A64_S, WebAssembly::LOAD_F64_A64 }, { WebAssembly::LOAD_I32_A32_S, WebAssembly::LOAD_I32_A32 }, { WebAssembly::LOAD_I32_A64_S, WebAssembly::LOAD_I32_A64 }, { WebAssembly::LOAD_I64_A32_S, WebAssembly::LOAD_I64_A32 }, { WebAssembly::LOAD_I64_A64_S, WebAssembly::LOAD_I64_A64 }, { WebAssembly::LOAD_LANE_16_A32_S, WebAssembly::LOAD_LANE_16_A32 }, { WebAssembly::LOAD_LANE_16_A64_S, WebAssembly::LOAD_LANE_16_A64 }, { WebAssembly::LOAD_LANE_32_A32_S, WebAssembly::LOAD_LANE_32_A32 }, { WebAssembly::LOAD_LANE_32_A64_S, WebAssembly::LOAD_LANE_32_A64 }, { WebAssembly::LOAD_LANE_64_A32_S, WebAssembly::LOAD_LANE_64_A32 }, { WebAssembly::LOAD_LANE_64_A64_S, WebAssembly::LOAD_LANE_64_A64 }, { WebAssembly::LOAD_LANE_8_A32_S, WebAssembly::LOAD_LANE_8_A32 }, { WebAssembly::LOAD_LANE_8_A64_S, WebAssembly::LOAD_LANE_8_A64 }, { WebAssembly::LOAD_V128_A32_S, WebAssembly::LOAD_V128_A32 }, { WebAssembly::LOAD_V128_A64_S, WebAssembly::LOAD_V128_A64 }, { WebAssembly::LOAD_ZERO_32_A32_S, WebAssembly::LOAD_ZERO_32_A32 }, { WebAssembly::LOAD_ZERO_32_A64_S, WebAssembly::LOAD_ZERO_32_A64 }, { WebAssembly::LOAD_ZERO_64_A32_S, WebAssembly::LOAD_ZERO_64_A32 }, { WebAssembly::LOAD_ZERO_64_A64_S, WebAssembly::LOAD_ZERO_64_A64 }, { WebAssembly::LOCAL_GET_EXNREF_S, WebAssembly::LOCAL_GET_EXNREF }, { WebAssembly::LOCAL_GET_EXTERNREF_S, WebAssembly::LOCAL_GET_EXTERNREF }, { WebAssembly::LOCAL_GET_F32_S, WebAssembly::LOCAL_GET_F32 }, { WebAssembly::LOCAL_GET_F64_S, WebAssembly::LOCAL_GET_F64 }, { WebAssembly::LOCAL_GET_FUNCREF_S, WebAssembly::LOCAL_GET_FUNCREF }, { WebAssembly::LOCAL_GET_I32_S, WebAssembly::LOCAL_GET_I32 }, { WebAssembly::LOCAL_GET_I64_S, WebAssembly::LOCAL_GET_I64 }, { WebAssembly::LOCAL_GET_V128_S, WebAssembly::LOCAL_GET_V128 }, { WebAssembly::LOCAL_SET_EXNREF_S, WebAssembly::LOCAL_SET_EXNREF }, { WebAssembly::LOCAL_SET_EXTERNREF_S, WebAssembly::LOCAL_SET_EXTERNREF }, { WebAssembly::LOCAL_SET_F32_S, WebAssembly::LOCAL_SET_F32 }, { WebAssembly::LOCAL_SET_F64_S, WebAssembly::LOCAL_SET_F64 }, { WebAssembly::LOCAL_SET_FUNCREF_S, WebAssembly::LOCAL_SET_FUNCREF }, { WebAssembly::LOCAL_SET_I32_S, WebAssembly::LOCAL_SET_I32 }, { WebAssembly::LOCAL_SET_I64_S, WebAssembly::LOCAL_SET_I64 }, { WebAssembly::LOCAL_SET_V128_S, WebAssembly::LOCAL_SET_V128 }, { WebAssembly::LOCAL_TEE_EXNREF_S, WebAssembly::LOCAL_TEE_EXNREF }, { WebAssembly::LOCAL_TEE_EXTERNREF_S, WebAssembly::LOCAL_TEE_EXTERNREF }, { WebAssembly::LOCAL_TEE_F32_S, WebAssembly::LOCAL_TEE_F32 }, { WebAssembly::LOCAL_TEE_F64_S, WebAssembly::LOCAL_TEE_F64 }, { WebAssembly::LOCAL_TEE_FUNCREF_S, WebAssembly::LOCAL_TEE_FUNCREF }, { WebAssembly::LOCAL_TEE_I32_S, WebAssembly::LOCAL_TEE_I32 }, { WebAssembly::LOCAL_TEE_I64_S, WebAssembly::LOCAL_TEE_I64 }, { WebAssembly::LOCAL_TEE_V128_S, WebAssembly::LOCAL_TEE_V128 }, { WebAssembly::LOOP_S, WebAssembly::LOOP }, { WebAssembly::LT_F16x8_S, WebAssembly::LT_F16x8 }, { WebAssembly::LT_F32_S, WebAssembly::LT_F32 }, { WebAssembly::LT_F32x4_S, WebAssembly::LT_F32x4 }, { WebAssembly::LT_F64_S, WebAssembly::LT_F64 }, { WebAssembly::LT_F64x2_S, WebAssembly::LT_F64x2 }, { WebAssembly::LT_S_I16x8_S, WebAssembly::LT_S_I16x8 }, { WebAssembly::LT_S_I32_S, WebAssembly::LT_S_I32 }, { WebAssembly::LT_S_I32x4_S, WebAssembly::LT_S_I32x4 }, { WebAssembly::LT_S_I64_S, WebAssembly::LT_S_I64 }, { WebAssembly::LT_S_I64x2_S, WebAssembly::LT_S_I64x2 }, { WebAssembly::LT_S_I8x16_S, WebAssembly::LT_S_I8x16 }, { WebAssembly::LT_U_I16x8_S, WebAssembly::LT_U_I16x8 }, { WebAssembly::LT_U_I32_S, WebAssembly::LT_U_I32 }, { WebAssembly::LT_U_I32x4_S, WebAssembly::LT_U_I32x4 }, { WebAssembly::LT_U_I64_S, WebAssembly::LT_U_I64 }, { WebAssembly::LT_U_I8x16_S, WebAssembly::LT_U_I8x16 }, { WebAssembly::MADD_F16x8_S, WebAssembly::MADD_F16x8 }, { WebAssembly::MADD_F32x4_S, WebAssembly::MADD_F32x4 }, { WebAssembly::MADD_F64x2_S, WebAssembly::MADD_F64x2 }, { WebAssembly::MAX_F16x8_S, WebAssembly::MAX_F16x8 }, { WebAssembly::MAX_F32_S, WebAssembly::MAX_F32 }, { WebAssembly::MAX_F32x4_S, WebAssembly::MAX_F32x4 }, { WebAssembly::MAX_F64_S, WebAssembly::MAX_F64 }, { WebAssembly::MAX_F64x2_S, WebAssembly::MAX_F64x2 }, { WebAssembly::MAX_S_I16x8_S, WebAssembly::MAX_S_I16x8 }, { WebAssembly::MAX_S_I32x4_S, WebAssembly::MAX_S_I32x4 }, { WebAssembly::MAX_S_I8x16_S, WebAssembly::MAX_S_I8x16 }, { WebAssembly::MAX_U_I16x8_S, WebAssembly::MAX_U_I16x8 }, { WebAssembly::MAX_U_I32x4_S, WebAssembly::MAX_U_I32x4 }, { WebAssembly::MAX_U_I8x16_S, WebAssembly::MAX_U_I8x16 }, { WebAssembly::MEMORY_ATOMIC_NOTIFY_A32_S, WebAssembly::MEMORY_ATOMIC_NOTIFY_A32 }, { WebAssembly::MEMORY_ATOMIC_NOTIFY_A64_S, WebAssembly::MEMORY_ATOMIC_NOTIFY_A64 }, { WebAssembly::MEMORY_ATOMIC_WAIT32_A32_S, WebAssembly::MEMORY_ATOMIC_WAIT32_A32 }, { WebAssembly::MEMORY_ATOMIC_WAIT32_A64_S, WebAssembly::MEMORY_ATOMIC_WAIT32_A64 }, { WebAssembly::MEMORY_ATOMIC_WAIT64_A32_S, WebAssembly::MEMORY_ATOMIC_WAIT64_A32 }, { WebAssembly::MEMORY_ATOMIC_WAIT64_A64_S, WebAssembly::MEMORY_ATOMIC_WAIT64_A64 }, { WebAssembly::MIN_F16x8_S, WebAssembly::MIN_F16x8 }, { WebAssembly::MIN_F32_S, WebAssembly::MIN_F32 }, { WebAssembly::MIN_F32x4_S, WebAssembly::MIN_F32x4 }, { WebAssembly::MIN_F64_S, WebAssembly::MIN_F64 }, { WebAssembly::MIN_F64x2_S, WebAssembly::MIN_F64x2 }, { WebAssembly::MIN_S_I16x8_S, WebAssembly::MIN_S_I16x8 }, { WebAssembly::MIN_S_I32x4_S, WebAssembly::MIN_S_I32x4 }, { WebAssembly::MIN_S_I8x16_S, WebAssembly::MIN_S_I8x16 }, { WebAssembly::MIN_U_I16x8_S, WebAssembly::MIN_U_I16x8 }, { WebAssembly::MIN_U_I32x4_S, WebAssembly::MIN_U_I32x4 }, { WebAssembly::MIN_U_I8x16_S, WebAssembly::MIN_U_I8x16 }, { WebAssembly::MUL_F16x8_S, WebAssembly::MUL_F16x8 }, { WebAssembly::MUL_F32_S, WebAssembly::MUL_F32 }, { WebAssembly::MUL_F32x4_S, WebAssembly::MUL_F32x4 }, { WebAssembly::MUL_F64_S, WebAssembly::MUL_F64 }, { WebAssembly::MUL_F64x2_S, WebAssembly::MUL_F64x2 }, { WebAssembly::MUL_I16x8_S, WebAssembly::MUL_I16x8 }, { WebAssembly::MUL_I32_S, WebAssembly::MUL_I32 }, { WebAssembly::MUL_I32x4_S, WebAssembly::MUL_I32x4 }, { WebAssembly::MUL_I64_S, WebAssembly::MUL_I64 }, { WebAssembly::MUL_I64x2_S, WebAssembly::MUL_I64x2 }, { WebAssembly::NARROW_S_I16x8_S, WebAssembly::NARROW_S_I16x8 }, { WebAssembly::NARROW_S_I8x16_S, WebAssembly::NARROW_S_I8x16 }, { WebAssembly::NARROW_U_I16x8_S, WebAssembly::NARROW_U_I16x8 }, { WebAssembly::NARROW_U_I8x16_S, WebAssembly::NARROW_U_I8x16 }, { WebAssembly::NEAREST_F16x8_S, WebAssembly::NEAREST_F16x8 }, { WebAssembly::NEAREST_F32_S, WebAssembly::NEAREST_F32 }, { WebAssembly::NEAREST_F32x4_S, WebAssembly::NEAREST_F32x4 }, { WebAssembly::NEAREST_F64_S, WebAssembly::NEAREST_F64 }, { WebAssembly::NEAREST_F64x2_S, WebAssembly::NEAREST_F64x2 }, { WebAssembly::NEG_F16x8_S, WebAssembly::NEG_F16x8 }, { WebAssembly::NEG_F32_S, WebAssembly::NEG_F32 }, { WebAssembly::NEG_F32x4_S, WebAssembly::NEG_F32x4 }, { WebAssembly::NEG_F64_S, WebAssembly::NEG_F64 }, { WebAssembly::NEG_F64x2_S, WebAssembly::NEG_F64x2 }, { WebAssembly::NEG_I16x8_S, WebAssembly::NEG_I16x8 }, { WebAssembly::NEG_I32x4_S, WebAssembly::NEG_I32x4 }, { WebAssembly::NEG_I64x2_S, WebAssembly::NEG_I64x2 }, { WebAssembly::NEG_I8x16_S, WebAssembly::NEG_I8x16 }, { WebAssembly::NE_F16x8_S, WebAssembly::NE_F16x8 }, { WebAssembly::NE_F32_S, WebAssembly::NE_F32 }, { WebAssembly::NE_F32x4_S, WebAssembly::NE_F32x4 }, { WebAssembly::NE_F64_S, WebAssembly::NE_F64 }, { WebAssembly::NE_F64x2_S, WebAssembly::NE_F64x2 }, { WebAssembly::NE_I16x8_S, WebAssembly::NE_I16x8 }, { WebAssembly::NE_I32_S, WebAssembly::NE_I32 }, { WebAssembly::NE_I32x4_S, WebAssembly::NE_I32x4 }, { WebAssembly::NE_I64_S, WebAssembly::NE_I64 }, { WebAssembly::NE_I64x2_S, WebAssembly::NE_I64x2 }, { WebAssembly::NE_I8x16_S, WebAssembly::NE_I8x16 }, { WebAssembly::NMADD_F16x8_S, WebAssembly::NMADD_F16x8 }, { WebAssembly::NMADD_F32x4_S, WebAssembly::NMADD_F32x4 }, { WebAssembly::NMADD_F64x2_S, WebAssembly::NMADD_F64x2 }, { WebAssembly::NOP_S, WebAssembly::NOP }, { WebAssembly::NOT_S, WebAssembly::NOT }, { WebAssembly::OR_I32_S, WebAssembly::OR_I32 }, { WebAssembly::OR_I64_S, WebAssembly::OR_I64 }, { WebAssembly::OR_S, WebAssembly::OR }, { WebAssembly::PMAX_F16x8_S, WebAssembly::PMAX_F16x8 }, { WebAssembly::PMAX_F32x4_S, WebAssembly::PMAX_F32x4 }, { WebAssembly::PMAX_F64x2_S, WebAssembly::PMAX_F64x2 }, { WebAssembly::PMIN_F16x8_S, WebAssembly::PMIN_F16x8 }, { WebAssembly::PMIN_F32x4_S, WebAssembly::PMIN_F32x4 }, { WebAssembly::PMIN_F64x2_S, WebAssembly::PMIN_F64x2 }, { WebAssembly::POPCNT_I32_S, WebAssembly::POPCNT_I32 }, { WebAssembly::POPCNT_I64_S, WebAssembly::POPCNT_I64 }, { WebAssembly::POPCNT_I8x16_S, WebAssembly::POPCNT_I8x16 }, { WebAssembly::Q15MULR_SAT_S_I16x8_S, WebAssembly::Q15MULR_SAT_S_I16x8 }, { WebAssembly::REF_IS_NULL_EXNREF_S, WebAssembly::REF_IS_NULL_EXNREF }, { WebAssembly::REF_IS_NULL_EXTERNREF_S, WebAssembly::REF_IS_NULL_EXTERNREF }, { WebAssembly::REF_IS_NULL_FUNCREF_S, WebAssembly::REF_IS_NULL_FUNCREF }, { WebAssembly::REF_NULL_EXNREF_S, WebAssembly::REF_NULL_EXNREF }, { WebAssembly::REF_NULL_EXTERNREF_S, WebAssembly::REF_NULL_EXTERNREF }, { WebAssembly::REF_NULL_FUNCREF_S, WebAssembly::REF_NULL_FUNCREF }, { WebAssembly::RELAXED_DOT_ADD_S, WebAssembly::RELAXED_DOT_ADD }, { WebAssembly::RELAXED_DOT_BFLOAT_S, WebAssembly::RELAXED_DOT_BFLOAT }, { WebAssembly::RELAXED_DOT_S, WebAssembly::RELAXED_DOT }, { WebAssembly::RELAXED_Q15MULR_S_I16x8_S, WebAssembly::RELAXED_Q15MULR_S_I16x8 }, { WebAssembly::RELAXED_SWIZZLE_S, WebAssembly::RELAXED_SWIZZLE }, { WebAssembly::REM_S_I32_S, WebAssembly::REM_S_I32 }, { WebAssembly::REM_S_I64_S, WebAssembly::REM_S_I64 }, { WebAssembly::REM_U_I32_S, WebAssembly::REM_U_I32 }, { WebAssembly::REM_U_I64_S, WebAssembly::REM_U_I64 }, { WebAssembly::REPLACE_LANE_F16x8_S, WebAssembly::REPLACE_LANE_F16x8 }, { WebAssembly::REPLACE_LANE_F32x4_S, WebAssembly::REPLACE_LANE_F32x4 }, { WebAssembly::REPLACE_LANE_F64x2_S, WebAssembly::REPLACE_LANE_F64x2 }, { WebAssembly::REPLACE_LANE_I16x8_S, WebAssembly::REPLACE_LANE_I16x8 }, { WebAssembly::REPLACE_LANE_I32x4_S, WebAssembly::REPLACE_LANE_I32x4 }, { WebAssembly::REPLACE_LANE_I64x2_S, WebAssembly::REPLACE_LANE_I64x2 }, { WebAssembly::REPLACE_LANE_I8x16_S, WebAssembly::REPLACE_LANE_I8x16 }, { WebAssembly::RETHROW_S, WebAssembly::RETHROW }, { WebAssembly::RETURN_S, WebAssembly::RETURN }, { WebAssembly::RET_CALL_INDIRECT_S, WebAssembly::RET_CALL_INDIRECT }, { WebAssembly::RET_CALL_S, WebAssembly::RET_CALL }, { WebAssembly::ROTL_I32_S, WebAssembly::ROTL_I32 }, { WebAssembly::ROTL_I64_S, WebAssembly::ROTL_I64 }, { WebAssembly::ROTR_I32_S, WebAssembly::ROTR_I32 }, { WebAssembly::ROTR_I64_S, WebAssembly::ROTR_I64 }, { WebAssembly::SELECT_EXNREF_S, WebAssembly::SELECT_EXNREF }, { WebAssembly::SELECT_EXTERNREF_S, WebAssembly::SELECT_EXTERNREF }, { WebAssembly::SELECT_F32_S, WebAssembly::SELECT_F32 }, { WebAssembly::SELECT_F64_S, WebAssembly::SELECT_F64 }, { WebAssembly::SELECT_FUNCREF_S, WebAssembly::SELECT_FUNCREF }, { WebAssembly::SELECT_I32_S, WebAssembly::SELECT_I32 }, { WebAssembly::SELECT_I64_S, WebAssembly::SELECT_I64 }, { WebAssembly::SELECT_V128_S, WebAssembly::SELECT_V128 }, { WebAssembly::SHL_I16x8_S, WebAssembly::SHL_I16x8 }, { WebAssembly::SHL_I32_S, WebAssembly::SHL_I32 }, { WebAssembly::SHL_I32x4_S, WebAssembly::SHL_I32x4 }, { WebAssembly::SHL_I64_S, WebAssembly::SHL_I64 }, { WebAssembly::SHL_I64x2_S, WebAssembly::SHL_I64x2 }, { WebAssembly::SHL_I8x16_S, WebAssembly::SHL_I8x16 }, { WebAssembly::SHR_S_I16x8_S, WebAssembly::SHR_S_I16x8 }, { WebAssembly::SHR_S_I32_S, WebAssembly::SHR_S_I32 }, { WebAssembly::SHR_S_I32x4_S, WebAssembly::SHR_S_I32x4 }, { WebAssembly::SHR_S_I64_S, WebAssembly::SHR_S_I64 }, { WebAssembly::SHR_S_I64x2_S, WebAssembly::SHR_S_I64x2 }, { WebAssembly::SHR_S_I8x16_S, WebAssembly::SHR_S_I8x16 }, { WebAssembly::SHR_U_I16x8_S, WebAssembly::SHR_U_I16x8 }, { WebAssembly::SHR_U_I32_S, WebAssembly::SHR_U_I32 }, { WebAssembly::SHR_U_I32x4_S, WebAssembly::SHR_U_I32x4 }, { WebAssembly::SHR_U_I64_S, WebAssembly::SHR_U_I64 }, { WebAssembly::SHR_U_I64x2_S, WebAssembly::SHR_U_I64x2 }, { WebAssembly::SHR_U_I8x16_S, WebAssembly::SHR_U_I8x16 }, { WebAssembly::SHUFFLE_S, WebAssembly::SHUFFLE }, { WebAssembly::SIMD_RELAXED_FMAX_F32x4_S, WebAssembly::SIMD_RELAXED_FMAX_F32x4 }, { WebAssembly::SIMD_RELAXED_FMAX_F64x2_S, WebAssembly::SIMD_RELAXED_FMAX_F64x2 }, { WebAssembly::SIMD_RELAXED_FMIN_F32x4_S, WebAssembly::SIMD_RELAXED_FMIN_F32x4 }, { WebAssembly::SIMD_RELAXED_FMIN_F64x2_S, WebAssembly::SIMD_RELAXED_FMIN_F64x2 }, { WebAssembly::SPLAT_F16x8_S, WebAssembly::SPLAT_F16x8 }, { WebAssembly::SPLAT_F32x4_S, WebAssembly::SPLAT_F32x4 }, { WebAssembly::SPLAT_F64x2_S, WebAssembly::SPLAT_F64x2 }, { WebAssembly::SPLAT_I16x8_S, WebAssembly::SPLAT_I16x8 }, { WebAssembly::SPLAT_I32x4_S, WebAssembly::SPLAT_I32x4 }, { WebAssembly::SPLAT_I64x2_S, WebAssembly::SPLAT_I64x2 }, { WebAssembly::SPLAT_I8x16_S, WebAssembly::SPLAT_I8x16 }, { WebAssembly::SQRT_F16x8_S, WebAssembly::SQRT_F16x8 }, { WebAssembly::SQRT_F32_S, WebAssembly::SQRT_F32 }, { WebAssembly::SQRT_F32x4_S, WebAssembly::SQRT_F32x4 }, { WebAssembly::SQRT_F64_S, WebAssembly::SQRT_F64 }, { WebAssembly::SQRT_F64x2_S, WebAssembly::SQRT_F64x2 }, { WebAssembly::STORE16_I32_A32_S, WebAssembly::STORE16_I32_A32 }, { WebAssembly::STORE16_I32_A64_S, WebAssembly::STORE16_I32_A64 }, { WebAssembly::STORE16_I64_A32_S, WebAssembly::STORE16_I64_A32 }, { WebAssembly::STORE16_I64_A64_S, WebAssembly::STORE16_I64_A64 }, { WebAssembly::STORE32_I64_A32_S, WebAssembly::STORE32_I64_A32 }, { WebAssembly::STORE32_I64_A64_S, WebAssembly::STORE32_I64_A64 }, { WebAssembly::STORE8_I32_A32_S, WebAssembly::STORE8_I32_A32 }, { WebAssembly::STORE8_I32_A64_S, WebAssembly::STORE8_I32_A64 }, { WebAssembly::STORE8_I64_A32_S, WebAssembly::STORE8_I64_A32 }, { WebAssembly::STORE8_I64_A64_S, WebAssembly::STORE8_I64_A64 }, { WebAssembly::STORE_F16_F32_A32_S, WebAssembly::STORE_F16_F32_A32 }, { WebAssembly::STORE_F16_F32_A64_S, WebAssembly::STORE_F16_F32_A64 }, { WebAssembly::STORE_F32_A32_S, WebAssembly::STORE_F32_A32 }, { WebAssembly::STORE_F32_A64_S, WebAssembly::STORE_F32_A64 }, { WebAssembly::STORE_F64_A32_S, WebAssembly::STORE_F64_A32 }, { WebAssembly::STORE_F64_A64_S, WebAssembly::STORE_F64_A64 }, { WebAssembly::STORE_I32_A32_S, WebAssembly::STORE_I32_A32 }, { WebAssembly::STORE_I32_A64_S, WebAssembly::STORE_I32_A64 }, { WebAssembly::STORE_I64_A32_S, WebAssembly::STORE_I64_A32 }, { WebAssembly::STORE_I64_A64_S, WebAssembly::STORE_I64_A64 }, { WebAssembly::STORE_LANE_I16x8_A32_S, WebAssembly::STORE_LANE_I16x8_A32 }, { WebAssembly::STORE_LANE_I16x8_A64_S, WebAssembly::STORE_LANE_I16x8_A64 }, { WebAssembly::STORE_LANE_I32x4_A32_S, WebAssembly::STORE_LANE_I32x4_A32 }, { WebAssembly::STORE_LANE_I32x4_A64_S, WebAssembly::STORE_LANE_I32x4_A64 }, { WebAssembly::STORE_LANE_I64x2_A32_S, WebAssembly::STORE_LANE_I64x2_A32 }, { WebAssembly::STORE_LANE_I64x2_A64_S, WebAssembly::STORE_LANE_I64x2_A64 }, { WebAssembly::STORE_LANE_I8x16_A32_S, WebAssembly::STORE_LANE_I8x16_A32 }, { WebAssembly::STORE_LANE_I8x16_A64_S, WebAssembly::STORE_LANE_I8x16_A64 }, { WebAssembly::STORE_V128_A32_S, WebAssembly::STORE_V128_A32 }, { WebAssembly::STORE_V128_A64_S, WebAssembly::STORE_V128_A64 }, { WebAssembly::SUB_F16x8_S, WebAssembly::SUB_F16x8 }, { WebAssembly::SUB_F32_S, WebAssembly::SUB_F32 }, { WebAssembly::SUB_F32x4_S, WebAssembly::SUB_F32x4 }, { WebAssembly::SUB_F64_S, WebAssembly::SUB_F64 }, { WebAssembly::SUB_F64x2_S, WebAssembly::SUB_F64x2 }, { WebAssembly::SUB_I16x8_S, WebAssembly::SUB_I16x8 }, { WebAssembly::SUB_I32_S, WebAssembly::SUB_I32 }, { WebAssembly::SUB_I32x4_S, WebAssembly::SUB_I32x4 }, { WebAssembly::SUB_I64_S, WebAssembly::SUB_I64 }, { WebAssembly::SUB_I64x2_S, WebAssembly::SUB_I64x2 }, { WebAssembly::SUB_I8x16_S, WebAssembly::SUB_I8x16 }, { WebAssembly::SUB_SAT_S_I16x8_S, WebAssembly::SUB_SAT_S_I16x8 }, { WebAssembly::SUB_SAT_S_I8x16_S, WebAssembly::SUB_SAT_S_I8x16 }, { WebAssembly::SUB_SAT_U_I16x8_S, WebAssembly::SUB_SAT_U_I16x8 }, { WebAssembly::SUB_SAT_U_I8x16_S, WebAssembly::SUB_SAT_U_I8x16 }, { WebAssembly::SWIZZLE_S, WebAssembly::SWIZZLE }, { WebAssembly::TABLE_COPY_S, WebAssembly::TABLE_COPY }, { WebAssembly::TABLE_FILL_EXNREF_S, WebAssembly::TABLE_FILL_EXNREF }, { WebAssembly::TABLE_FILL_EXTERNREF_S, WebAssembly::TABLE_FILL_EXTERNREF }, { WebAssembly::TABLE_FILL_FUNCREF_S, WebAssembly::TABLE_FILL_FUNCREF }, { WebAssembly::TABLE_GET_EXNREF_S, WebAssembly::TABLE_GET_EXNREF }, { WebAssembly::TABLE_GET_EXTERNREF_S, WebAssembly::TABLE_GET_EXTERNREF }, { WebAssembly::TABLE_GET_FUNCREF_S, WebAssembly::TABLE_GET_FUNCREF }, { WebAssembly::TABLE_GROW_EXNREF_S, WebAssembly::TABLE_GROW_EXNREF }, { WebAssembly::TABLE_GROW_EXTERNREF_S, WebAssembly::TABLE_GROW_EXTERNREF }, { WebAssembly::TABLE_GROW_FUNCREF_S, WebAssembly::TABLE_GROW_FUNCREF }, { WebAssembly::TABLE_SET_EXNREF_S, WebAssembly::TABLE_SET_EXNREF }, { WebAssembly::TABLE_SET_EXTERNREF_S, WebAssembly::TABLE_SET_EXTERNREF }, { WebAssembly::TABLE_SET_FUNCREF_S, WebAssembly::TABLE_SET_FUNCREF }, { WebAssembly::TABLE_SIZE_S, WebAssembly::TABLE_SIZE }, { WebAssembly::TEE_EXNREF_S, WebAssembly::TEE_EXNREF }, { WebAssembly::TEE_EXTERNREF_S, WebAssembly::TEE_EXTERNREF }, { WebAssembly::TEE_F32_S, WebAssembly::TEE_F32 }, { WebAssembly::TEE_F64_S, WebAssembly::TEE_F64 }, { WebAssembly::TEE_FUNCREF_S, WebAssembly::TEE_FUNCREF }, { WebAssembly::TEE_I32_S, WebAssembly::TEE_I32 }, { WebAssembly::TEE_I64_S, WebAssembly::TEE_I64 }, { WebAssembly::TEE_V128_S, WebAssembly::TEE_V128 }, { WebAssembly::THROW_S, WebAssembly::THROW }, { WebAssembly::TRUNC_F16x8_S, WebAssembly::TRUNC_F16x8 }, { WebAssembly::TRUNC_F32_S, WebAssembly::TRUNC_F32 }, { WebAssembly::TRUNC_F32x4_S, WebAssembly::TRUNC_F32x4 }, { WebAssembly::TRUNC_F64_S, WebAssembly::TRUNC_F64 }, { WebAssembly::TRUNC_F64x2_S, WebAssembly::TRUNC_F64x2 }, { WebAssembly::TRY_S, WebAssembly::TRY }, { WebAssembly::UNREACHABLE_S, WebAssembly::UNREACHABLE }, { WebAssembly::XOR_I32_S, WebAssembly::XOR_I32 }, { WebAssembly::XOR_I64_S, WebAssembly::XOR_I64 }, { WebAssembly::XOR_S, WebAssembly::XOR }, { WebAssembly::anonymous_8166MEMORY_GROW_A32_S, WebAssembly::anonymous_8166MEMORY_GROW_A32 }, { WebAssembly::anonymous_8166MEMORY_SIZE_A32_S, WebAssembly::anonymous_8166MEMORY_SIZE_A32 }, { WebAssembly::anonymous_8167MEMORY_GROW_A64_S, WebAssembly::anonymous_8167MEMORY_GROW_A64 }, { WebAssembly::anonymous_8167MEMORY_SIZE_A64_S, WebAssembly::anonymous_8167MEMORY_SIZE_A64 }, { WebAssembly::anonymous_8883DATA_DROP_S, WebAssembly::anonymous_8883DATA_DROP }, { WebAssembly::anonymous_8883MEMORY_COPY_A32_S, WebAssembly::anonymous_8883MEMORY_COPY_A32 }, { WebAssembly::anonymous_8883MEMORY_FILL_A32_S, WebAssembly::anonymous_8883MEMORY_FILL_A32 }, { WebAssembly::anonymous_8883MEMORY_INIT_A32_S, WebAssembly::anonymous_8883MEMORY_INIT_A32 }, { WebAssembly::anonymous_8884DATA_DROP_S, WebAssembly::anonymous_8884DATA_DROP }, { WebAssembly::anonymous_8884MEMORY_COPY_A64_S, WebAssembly::anonymous_8884MEMORY_COPY_A64 }, { WebAssembly::anonymous_8884MEMORY_FILL_A64_S, WebAssembly::anonymous_8884MEMORY_FILL_A64 }, { WebAssembly::anonymous_8884MEMORY_INIT_A64_S, WebAssembly::anonymous_8884MEMORY_INIT_A64 }, { WebAssembly::convert_low_s_F64x2_S, WebAssembly::convert_low_s_F64x2 }, { WebAssembly::convert_low_u_F64x2_S, WebAssembly::convert_low_u_F64x2 }, { WebAssembly::demote_zero_F32x4_S, WebAssembly::demote_zero_F32x4 }, { WebAssembly::extend_high_s_I16x8_S, WebAssembly::extend_high_s_I16x8 }, { WebAssembly::extend_high_s_I32x4_S, WebAssembly::extend_high_s_I32x4 }, { WebAssembly::extend_high_s_I64x2_S, WebAssembly::extend_high_s_I64x2 }, { WebAssembly::extend_high_u_I16x8_S, WebAssembly::extend_high_u_I16x8 }, { WebAssembly::extend_high_u_I32x4_S, WebAssembly::extend_high_u_I32x4 }, { WebAssembly::extend_high_u_I64x2_S, WebAssembly::extend_high_u_I64x2 }, { WebAssembly::extend_low_s_I16x8_S, WebAssembly::extend_low_s_I16x8 }, { WebAssembly::extend_low_s_I32x4_S, WebAssembly::extend_low_s_I32x4 }, { WebAssembly::extend_low_s_I64x2_S, WebAssembly::extend_low_s_I64x2 }, { WebAssembly::extend_low_u_I16x8_S, WebAssembly::extend_low_u_I16x8 }, { WebAssembly::extend_low_u_I32x4_S, WebAssembly::extend_low_u_I32x4 }, { WebAssembly::extend_low_u_I64x2_S, WebAssembly::extend_low_u_I64x2 }, { WebAssembly::fp_to_sint_I16x8_S, WebAssembly::fp_to_sint_I16x8 }, { WebAssembly::fp_to_sint_I32x4_S, WebAssembly::fp_to_sint_I32x4 }, { WebAssembly::fp_to_uint_I16x8_S, WebAssembly::fp_to_uint_I16x8 }, { WebAssembly::fp_to_uint_I32x4_S, WebAssembly::fp_to_uint_I32x4 }, { WebAssembly::int_wasm_extadd_pairwise_signed_I16x8_S, WebAssembly::int_wasm_extadd_pairwise_signed_I16x8 }, { WebAssembly::int_wasm_extadd_pairwise_signed_I32x4_S, WebAssembly::int_wasm_extadd_pairwise_signed_I32x4 }, { WebAssembly::int_wasm_extadd_pairwise_unsigned_I16x8_S, WebAssembly::int_wasm_extadd_pairwise_unsigned_I16x8 }, { WebAssembly::int_wasm_extadd_pairwise_unsigned_I32x4_S, WebAssembly::int_wasm_extadd_pairwise_unsigned_I32x4 }, { WebAssembly::int_wasm_relaxed_trunc_signed_I32x4_S, WebAssembly::int_wasm_relaxed_trunc_signed_I32x4 }, { WebAssembly::int_wasm_relaxed_trunc_signed_zero_I32x4_S, WebAssembly::int_wasm_relaxed_trunc_signed_zero_I32x4 }, { WebAssembly::int_wasm_relaxed_trunc_unsigned_I32x4_S, WebAssembly::int_wasm_relaxed_trunc_unsigned_I32x4 }, { WebAssembly::int_wasm_relaxed_trunc_unsigned_zero_I32x4_S, WebAssembly::int_wasm_relaxed_trunc_unsigned_zero_I32x4 }, { WebAssembly::promote_low_F64x2_S, WebAssembly::promote_low_F64x2 }, { WebAssembly::sint_to_fp_F16x8_S, WebAssembly::sint_to_fp_F16x8 }, { WebAssembly::sint_to_fp_F32x4_S, WebAssembly::sint_to_fp_F32x4 }, { WebAssembly::trunc_sat_zero_s_I32x4_S, WebAssembly::trunc_sat_zero_s_I32x4 }, { WebAssembly::trunc_sat_zero_u_I32x4_S, WebAssembly::trunc_sat_zero_u_I32x4 }, { WebAssembly::uint_to_fp_F16x8_S, WebAssembly::uint_to_fp_F16x8 }, { WebAssembly::uint_to_fp_F32x4_S, WebAssembly::uint_to_fp_F32x4 }, }; // End of getRegisterOpcodeTable unsigned mid; unsigned start = 0; unsigned end = 801; while (start < end) { mid = start + (end - start) / 2; if (Opcode == getRegisterOpcodeTable[mid][0]) { break; } if (Opcode < getRegisterOpcodeTable[mid][0]) end = mid; else start = mid + 1; } if (start == end) return -1; // Instruction doesn't exist in this table. return getRegisterOpcodeTable[mid][1]; } // getStackOpcode LLVM_READONLY int getStackOpcode(uint16_t Opcode) { static const uint16_t getStackOpcodeTable[][2] = { { WebAssembly::CALL_PARAMS, WebAssembly::CALL_PARAMS_S }, { WebAssembly::CALL_RESULTS, WebAssembly::CALL_RESULTS_S }, { WebAssembly::CATCHRET, WebAssembly::CATCHRET_S }, { WebAssembly::CLEANUPRET, WebAssembly::CLEANUPRET_S }, { WebAssembly::COMPILER_FENCE, WebAssembly::COMPILER_FENCE_S }, { WebAssembly::RET_CALL_RESULTS, WebAssembly::RET_CALL_RESULTS_S }, { WebAssembly::ABS_F16x8, WebAssembly::ABS_F16x8_S }, { WebAssembly::ABS_F32, WebAssembly::ABS_F32_S }, { WebAssembly::ABS_F32x4, WebAssembly::ABS_F32x4_S }, { WebAssembly::ABS_F64, WebAssembly::ABS_F64_S }, { WebAssembly::ABS_F64x2, WebAssembly::ABS_F64x2_S }, { WebAssembly::ABS_I16x8, WebAssembly::ABS_I16x8_S }, { WebAssembly::ABS_I32x4, WebAssembly::ABS_I32x4_S }, { WebAssembly::ABS_I64x2, WebAssembly::ABS_I64x2_S }, { WebAssembly::ABS_I8x16, WebAssembly::ABS_I8x16_S }, { WebAssembly::ADD_F16x8, WebAssembly::ADD_F16x8_S }, { WebAssembly::ADD_F32, WebAssembly::ADD_F32_S }, { WebAssembly::ADD_F32x4, WebAssembly::ADD_F32x4_S }, { WebAssembly::ADD_F64, WebAssembly::ADD_F64_S }, { WebAssembly::ADD_F64x2, WebAssembly::ADD_F64x2_S }, { WebAssembly::ADD_I16x8, WebAssembly::ADD_I16x8_S }, { WebAssembly::ADD_I32, WebAssembly::ADD_I32_S }, { WebAssembly::ADD_I32x4, WebAssembly::ADD_I32x4_S }, { WebAssembly::ADD_I64, WebAssembly::ADD_I64_S }, { WebAssembly::ADD_I64x2, WebAssembly::ADD_I64x2_S }, { WebAssembly::ADD_I8x16, WebAssembly::ADD_I8x16_S }, { WebAssembly::ADD_SAT_S_I16x8, WebAssembly::ADD_SAT_S_I16x8_S }, { WebAssembly::ADD_SAT_S_I8x16, WebAssembly::ADD_SAT_S_I8x16_S }, { WebAssembly::ADD_SAT_U_I16x8, WebAssembly::ADD_SAT_U_I16x8_S }, { WebAssembly::ADD_SAT_U_I8x16, WebAssembly::ADD_SAT_U_I8x16_S }, { WebAssembly::ADJCALLSTACKDOWN, WebAssembly::ADJCALLSTACKDOWN_S }, { WebAssembly::ADJCALLSTACKUP, WebAssembly::ADJCALLSTACKUP_S }, { WebAssembly::ALLTRUE_I16x8, WebAssembly::ALLTRUE_I16x8_S }, { WebAssembly::ALLTRUE_I32x4, WebAssembly::ALLTRUE_I32x4_S }, { WebAssembly::ALLTRUE_I64x2, WebAssembly::ALLTRUE_I64x2_S }, { WebAssembly::ALLTRUE_I8x16, WebAssembly::ALLTRUE_I8x16_S }, { WebAssembly::AND, WebAssembly::AND_S }, { WebAssembly::ANDNOT, WebAssembly::ANDNOT_S }, { WebAssembly::AND_I32, WebAssembly::AND_I32_S }, { WebAssembly::AND_I64, WebAssembly::AND_I64_S }, { WebAssembly::ANYTRUE, WebAssembly::ANYTRUE_S }, { WebAssembly::ARGUMENT_exnref, WebAssembly::ARGUMENT_exnref_S }, { WebAssembly::ARGUMENT_externref, WebAssembly::ARGUMENT_externref_S }, { WebAssembly::ARGUMENT_f32, WebAssembly::ARGUMENT_f32_S }, { WebAssembly::ARGUMENT_f64, WebAssembly::ARGUMENT_f64_S }, { WebAssembly::ARGUMENT_funcref, WebAssembly::ARGUMENT_funcref_S }, { WebAssembly::ARGUMENT_i32, WebAssembly::ARGUMENT_i32_S }, { WebAssembly::ARGUMENT_i64, WebAssembly::ARGUMENT_i64_S }, { WebAssembly::ARGUMENT_v16i8, WebAssembly::ARGUMENT_v16i8_S }, { WebAssembly::ARGUMENT_v2f64, WebAssembly::ARGUMENT_v2f64_S }, { WebAssembly::ARGUMENT_v2i64, WebAssembly::ARGUMENT_v2i64_S }, { WebAssembly::ARGUMENT_v4f32, WebAssembly::ARGUMENT_v4f32_S }, { WebAssembly::ARGUMENT_v4i32, WebAssembly::ARGUMENT_v4i32_S }, { WebAssembly::ARGUMENT_v8f16, WebAssembly::ARGUMENT_v8f16_S }, { WebAssembly::ARGUMENT_v8i16, WebAssembly::ARGUMENT_v8i16_S }, { WebAssembly::ATOMIC_FENCE, WebAssembly::ATOMIC_FENCE_S }, { WebAssembly::ATOMIC_LOAD16_U_I32_A32, WebAssembly::ATOMIC_LOAD16_U_I32_A32_S }, { WebAssembly::ATOMIC_LOAD16_U_I32_A64, WebAssembly::ATOMIC_LOAD16_U_I32_A64_S }, { WebAssembly::ATOMIC_LOAD16_U_I64_A32, WebAssembly::ATOMIC_LOAD16_U_I64_A32_S }, { WebAssembly::ATOMIC_LOAD16_U_I64_A64, WebAssembly::ATOMIC_LOAD16_U_I64_A64_S }, { WebAssembly::ATOMIC_LOAD32_U_I64_A32, WebAssembly::ATOMIC_LOAD32_U_I64_A32_S }, { WebAssembly::ATOMIC_LOAD32_U_I64_A64, WebAssembly::ATOMIC_LOAD32_U_I64_A64_S }, { WebAssembly::ATOMIC_LOAD8_U_I32_A32, WebAssembly::ATOMIC_LOAD8_U_I32_A32_S }, { WebAssembly::ATOMIC_LOAD8_U_I32_A64, WebAssembly::ATOMIC_LOAD8_U_I32_A64_S }, { WebAssembly::ATOMIC_LOAD8_U_I64_A32, WebAssembly::ATOMIC_LOAD8_U_I64_A32_S }, { WebAssembly::ATOMIC_LOAD8_U_I64_A64, WebAssembly::ATOMIC_LOAD8_U_I64_A64_S }, { WebAssembly::ATOMIC_LOAD_I32_A32, WebAssembly::ATOMIC_LOAD_I32_A32_S }, { WebAssembly::ATOMIC_LOAD_I32_A64, WebAssembly::ATOMIC_LOAD_I32_A64_S }, { WebAssembly::ATOMIC_LOAD_I64_A32, WebAssembly::ATOMIC_LOAD_I64_A32_S }, { WebAssembly::ATOMIC_LOAD_I64_A64, WebAssembly::ATOMIC_LOAD_I64_A64_S }, { WebAssembly::ATOMIC_RMW16_U_ADD_I32_A32, WebAssembly::ATOMIC_RMW16_U_ADD_I32_A32_S }, { WebAssembly::ATOMIC_RMW16_U_ADD_I32_A64, WebAssembly::ATOMIC_RMW16_U_ADD_I32_A64_S }, { WebAssembly::ATOMIC_RMW16_U_ADD_I64_A32, WebAssembly::ATOMIC_RMW16_U_ADD_I64_A32_S }, { WebAssembly::ATOMIC_RMW16_U_ADD_I64_A64, WebAssembly::ATOMIC_RMW16_U_ADD_I64_A64_S }, { WebAssembly::ATOMIC_RMW16_U_AND_I32_A32, WebAssembly::ATOMIC_RMW16_U_AND_I32_A32_S }, { WebAssembly::ATOMIC_RMW16_U_AND_I32_A64, WebAssembly::ATOMIC_RMW16_U_AND_I32_A64_S }, { WebAssembly::ATOMIC_RMW16_U_AND_I64_A32, WebAssembly::ATOMIC_RMW16_U_AND_I64_A32_S }, { WebAssembly::ATOMIC_RMW16_U_AND_I64_A64, WebAssembly::ATOMIC_RMW16_U_AND_I64_A64_S }, { WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I32_A32, WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I32_A32_S }, { WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I32_A64, WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I32_A64_S }, { WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I64_A32, WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I64_A32_S }, { WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I64_A64, WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I64_A64_S }, { WebAssembly::ATOMIC_RMW16_U_OR_I32_A32, WebAssembly::ATOMIC_RMW16_U_OR_I32_A32_S }, { WebAssembly::ATOMIC_RMW16_U_OR_I32_A64, WebAssembly::ATOMIC_RMW16_U_OR_I32_A64_S }, { WebAssembly::ATOMIC_RMW16_U_OR_I64_A32, WebAssembly::ATOMIC_RMW16_U_OR_I64_A32_S }, { WebAssembly::ATOMIC_RMW16_U_OR_I64_A64, WebAssembly::ATOMIC_RMW16_U_OR_I64_A64_S }, { WebAssembly::ATOMIC_RMW16_U_SUB_I32_A32, WebAssembly::ATOMIC_RMW16_U_SUB_I32_A32_S }, { WebAssembly::ATOMIC_RMW16_U_SUB_I32_A64, WebAssembly::ATOMIC_RMW16_U_SUB_I32_A64_S }, { WebAssembly::ATOMIC_RMW16_U_SUB_I64_A32, WebAssembly::ATOMIC_RMW16_U_SUB_I64_A32_S }, { WebAssembly::ATOMIC_RMW16_U_SUB_I64_A64, WebAssembly::ATOMIC_RMW16_U_SUB_I64_A64_S }, { WebAssembly::ATOMIC_RMW16_U_XCHG_I32_A32, WebAssembly::ATOMIC_RMW16_U_XCHG_I32_A32_S }, { WebAssembly::ATOMIC_RMW16_U_XCHG_I32_A64, WebAssembly::ATOMIC_RMW16_U_XCHG_I32_A64_S }, { WebAssembly::ATOMIC_RMW16_U_XCHG_I64_A32, WebAssembly::ATOMIC_RMW16_U_XCHG_I64_A32_S }, { WebAssembly::ATOMIC_RMW16_U_XCHG_I64_A64, WebAssembly::ATOMIC_RMW16_U_XCHG_I64_A64_S }, { WebAssembly::ATOMIC_RMW16_U_XOR_I32_A32, WebAssembly::ATOMIC_RMW16_U_XOR_I32_A32_S }, { WebAssembly::ATOMIC_RMW16_U_XOR_I32_A64, WebAssembly::ATOMIC_RMW16_U_XOR_I32_A64_S }, { WebAssembly::ATOMIC_RMW16_U_XOR_I64_A32, WebAssembly::ATOMIC_RMW16_U_XOR_I64_A32_S }, { WebAssembly::ATOMIC_RMW16_U_XOR_I64_A64, WebAssembly::ATOMIC_RMW16_U_XOR_I64_A64_S }, { WebAssembly::ATOMIC_RMW32_U_ADD_I64_A32, WebAssembly::ATOMIC_RMW32_U_ADD_I64_A32_S }, { WebAssembly::ATOMIC_RMW32_U_ADD_I64_A64, WebAssembly::ATOMIC_RMW32_U_ADD_I64_A64_S }, { WebAssembly::ATOMIC_RMW32_U_AND_I64_A32, WebAssembly::ATOMIC_RMW32_U_AND_I64_A32_S }, { WebAssembly::ATOMIC_RMW32_U_AND_I64_A64, WebAssembly::ATOMIC_RMW32_U_AND_I64_A64_S }, { WebAssembly::ATOMIC_RMW32_U_CMPXCHG_I64_A32, WebAssembly::ATOMIC_RMW32_U_CMPXCHG_I64_A32_S }, { WebAssembly::ATOMIC_RMW32_U_CMPXCHG_I64_A64, WebAssembly::ATOMIC_RMW32_U_CMPXCHG_I64_A64_S }, { WebAssembly::ATOMIC_RMW32_U_OR_I64_A32, WebAssembly::ATOMIC_RMW32_U_OR_I64_A32_S }, { WebAssembly::ATOMIC_RMW32_U_OR_I64_A64, WebAssembly::ATOMIC_RMW32_U_OR_I64_A64_S }, { WebAssembly::ATOMIC_RMW32_U_SUB_I64_A32, WebAssembly::ATOMIC_RMW32_U_SUB_I64_A32_S }, { WebAssembly::ATOMIC_RMW32_U_SUB_I64_A64, WebAssembly::ATOMIC_RMW32_U_SUB_I64_A64_S }, { WebAssembly::ATOMIC_RMW32_U_XCHG_I64_A32, WebAssembly::ATOMIC_RMW32_U_XCHG_I64_A32_S }, { WebAssembly::ATOMIC_RMW32_U_XCHG_I64_A64, WebAssembly::ATOMIC_RMW32_U_XCHG_I64_A64_S }, { WebAssembly::ATOMIC_RMW32_U_XOR_I64_A32, WebAssembly::ATOMIC_RMW32_U_XOR_I64_A32_S }, { WebAssembly::ATOMIC_RMW32_U_XOR_I64_A64, WebAssembly::ATOMIC_RMW32_U_XOR_I64_A64_S }, { WebAssembly::ATOMIC_RMW8_U_ADD_I32_A32, WebAssembly::ATOMIC_RMW8_U_ADD_I32_A32_S }, { WebAssembly::ATOMIC_RMW8_U_ADD_I32_A64, WebAssembly::ATOMIC_RMW8_U_ADD_I32_A64_S }, { WebAssembly::ATOMIC_RMW8_U_ADD_I64_A32, WebAssembly::ATOMIC_RMW8_U_ADD_I64_A32_S }, { WebAssembly::ATOMIC_RMW8_U_ADD_I64_A64, WebAssembly::ATOMIC_RMW8_U_ADD_I64_A64_S }, { WebAssembly::ATOMIC_RMW8_U_AND_I32_A32, WebAssembly::ATOMIC_RMW8_U_AND_I32_A32_S }, { WebAssembly::ATOMIC_RMW8_U_AND_I32_A64, WebAssembly::ATOMIC_RMW8_U_AND_I32_A64_S }, { WebAssembly::ATOMIC_RMW8_U_AND_I64_A32, WebAssembly::ATOMIC_RMW8_U_AND_I64_A32_S }, { WebAssembly::ATOMIC_RMW8_U_AND_I64_A64, WebAssembly::ATOMIC_RMW8_U_AND_I64_A64_S }, { WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I32_A32, WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I32_A32_S }, { WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I32_A64, WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I32_A64_S }, { WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I64_A32, WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I64_A32_S }, { WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I64_A64, WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I64_A64_S }, { WebAssembly::ATOMIC_RMW8_U_OR_I32_A32, WebAssembly::ATOMIC_RMW8_U_OR_I32_A32_S }, { WebAssembly::ATOMIC_RMW8_U_OR_I32_A64, WebAssembly::ATOMIC_RMW8_U_OR_I32_A64_S }, { WebAssembly::ATOMIC_RMW8_U_OR_I64_A32, WebAssembly::ATOMIC_RMW8_U_OR_I64_A32_S }, { WebAssembly::ATOMIC_RMW8_U_OR_I64_A64, WebAssembly::ATOMIC_RMW8_U_OR_I64_A64_S }, { WebAssembly::ATOMIC_RMW8_U_SUB_I32_A32, WebAssembly::ATOMIC_RMW8_U_SUB_I32_A32_S }, { WebAssembly::ATOMIC_RMW8_U_SUB_I32_A64, WebAssembly::ATOMIC_RMW8_U_SUB_I32_A64_S }, { WebAssembly::ATOMIC_RMW8_U_SUB_I64_A32, WebAssembly::ATOMIC_RMW8_U_SUB_I64_A32_S }, { WebAssembly::ATOMIC_RMW8_U_SUB_I64_A64, WebAssembly::ATOMIC_RMW8_U_SUB_I64_A64_S }, { WebAssembly::ATOMIC_RMW8_U_XCHG_I32_A32, WebAssembly::ATOMIC_RMW8_U_XCHG_I32_A32_S }, { WebAssembly::ATOMIC_RMW8_U_XCHG_I32_A64, WebAssembly::ATOMIC_RMW8_U_XCHG_I32_A64_S }, { WebAssembly::ATOMIC_RMW8_U_XCHG_I64_A32, WebAssembly::ATOMIC_RMW8_U_XCHG_I64_A32_S }, { WebAssembly::ATOMIC_RMW8_U_XCHG_I64_A64, WebAssembly::ATOMIC_RMW8_U_XCHG_I64_A64_S }, { WebAssembly::ATOMIC_RMW8_U_XOR_I32_A32, WebAssembly::ATOMIC_RMW8_U_XOR_I32_A32_S }, { WebAssembly::ATOMIC_RMW8_U_XOR_I32_A64, WebAssembly::ATOMIC_RMW8_U_XOR_I32_A64_S }, { WebAssembly::ATOMIC_RMW8_U_XOR_I64_A32, WebAssembly::ATOMIC_RMW8_U_XOR_I64_A32_S }, { WebAssembly::ATOMIC_RMW8_U_XOR_I64_A64, WebAssembly::ATOMIC_RMW8_U_XOR_I64_A64_S }, { WebAssembly::ATOMIC_RMW_ADD_I32_A32, WebAssembly::ATOMIC_RMW_ADD_I32_A32_S }, { WebAssembly::ATOMIC_RMW_ADD_I32_A64, WebAssembly::ATOMIC_RMW_ADD_I32_A64_S }, { WebAssembly::ATOMIC_RMW_ADD_I64_A32, WebAssembly::ATOMIC_RMW_ADD_I64_A32_S }, { WebAssembly::ATOMIC_RMW_ADD_I64_A64, WebAssembly::ATOMIC_RMW_ADD_I64_A64_S }, { WebAssembly::ATOMIC_RMW_AND_I32_A32, WebAssembly::ATOMIC_RMW_AND_I32_A32_S }, { WebAssembly::ATOMIC_RMW_AND_I32_A64, WebAssembly::ATOMIC_RMW_AND_I32_A64_S }, { WebAssembly::ATOMIC_RMW_AND_I64_A32, WebAssembly::ATOMIC_RMW_AND_I64_A32_S }, { WebAssembly::ATOMIC_RMW_AND_I64_A64, WebAssembly::ATOMIC_RMW_AND_I64_A64_S }, { WebAssembly::ATOMIC_RMW_CMPXCHG_I32_A32, WebAssembly::ATOMIC_RMW_CMPXCHG_I32_A32_S }, { WebAssembly::ATOMIC_RMW_CMPXCHG_I32_A64, WebAssembly::ATOMIC_RMW_CMPXCHG_I32_A64_S }, { WebAssembly::ATOMIC_RMW_CMPXCHG_I64_A32, WebAssembly::ATOMIC_RMW_CMPXCHG_I64_A32_S }, { WebAssembly::ATOMIC_RMW_CMPXCHG_I64_A64, WebAssembly::ATOMIC_RMW_CMPXCHG_I64_A64_S }, { WebAssembly::ATOMIC_RMW_OR_I32_A32, WebAssembly::ATOMIC_RMW_OR_I32_A32_S }, { WebAssembly::ATOMIC_RMW_OR_I32_A64, WebAssembly::ATOMIC_RMW_OR_I32_A64_S }, { WebAssembly::ATOMIC_RMW_OR_I64_A32, WebAssembly::ATOMIC_RMW_OR_I64_A32_S }, { WebAssembly::ATOMIC_RMW_OR_I64_A64, WebAssembly::ATOMIC_RMW_OR_I64_A64_S }, { WebAssembly::ATOMIC_RMW_SUB_I32_A32, WebAssembly::ATOMIC_RMW_SUB_I32_A32_S }, { WebAssembly::ATOMIC_RMW_SUB_I32_A64, WebAssembly::ATOMIC_RMW_SUB_I32_A64_S }, { WebAssembly::ATOMIC_RMW_SUB_I64_A32, WebAssembly::ATOMIC_RMW_SUB_I64_A32_S }, { WebAssembly::ATOMIC_RMW_SUB_I64_A64, WebAssembly::ATOMIC_RMW_SUB_I64_A64_S }, { WebAssembly::ATOMIC_RMW_XCHG_I32_A32, WebAssembly::ATOMIC_RMW_XCHG_I32_A32_S }, { WebAssembly::ATOMIC_RMW_XCHG_I32_A64, WebAssembly::ATOMIC_RMW_XCHG_I32_A64_S }, { WebAssembly::ATOMIC_RMW_XCHG_I64_A32, WebAssembly::ATOMIC_RMW_XCHG_I64_A32_S }, { WebAssembly::ATOMIC_RMW_XCHG_I64_A64, WebAssembly::ATOMIC_RMW_XCHG_I64_A64_S }, { WebAssembly::ATOMIC_RMW_XOR_I32_A32, WebAssembly::ATOMIC_RMW_XOR_I32_A32_S }, { WebAssembly::ATOMIC_RMW_XOR_I32_A64, WebAssembly::ATOMIC_RMW_XOR_I32_A64_S }, { WebAssembly::ATOMIC_RMW_XOR_I64_A32, WebAssembly::ATOMIC_RMW_XOR_I64_A32_S }, { WebAssembly::ATOMIC_RMW_XOR_I64_A64, WebAssembly::ATOMIC_RMW_XOR_I64_A64_S }, { WebAssembly::ATOMIC_STORE16_I32_A32, WebAssembly::ATOMIC_STORE16_I32_A32_S }, { WebAssembly::ATOMIC_STORE16_I32_A64, WebAssembly::ATOMIC_STORE16_I32_A64_S }, { WebAssembly::ATOMIC_STORE16_I64_A32, WebAssembly::ATOMIC_STORE16_I64_A32_S }, { WebAssembly::ATOMIC_STORE16_I64_A64, WebAssembly::ATOMIC_STORE16_I64_A64_S }, { WebAssembly::ATOMIC_STORE32_I64_A32, WebAssembly::ATOMIC_STORE32_I64_A32_S }, { WebAssembly::ATOMIC_STORE32_I64_A64, WebAssembly::ATOMIC_STORE32_I64_A64_S }, { WebAssembly::ATOMIC_STORE8_I32_A32, WebAssembly::ATOMIC_STORE8_I32_A32_S }, { WebAssembly::ATOMIC_STORE8_I32_A64, WebAssembly::ATOMIC_STORE8_I32_A64_S }, { WebAssembly::ATOMIC_STORE8_I64_A32, WebAssembly::ATOMIC_STORE8_I64_A32_S }, { WebAssembly::ATOMIC_STORE8_I64_A64, WebAssembly::ATOMIC_STORE8_I64_A64_S }, { WebAssembly::ATOMIC_STORE_I32_A32, WebAssembly::ATOMIC_STORE_I32_A32_S }, { WebAssembly::ATOMIC_STORE_I32_A64, WebAssembly::ATOMIC_STORE_I32_A64_S }, { WebAssembly::ATOMIC_STORE_I64_A32, WebAssembly::ATOMIC_STORE_I64_A32_S }, { WebAssembly::ATOMIC_STORE_I64_A64, WebAssembly::ATOMIC_STORE_I64_A64_S }, { WebAssembly::AVGR_U_I16x8, WebAssembly::AVGR_U_I16x8_S }, { WebAssembly::AVGR_U_I8x16, WebAssembly::AVGR_U_I8x16_S }, { WebAssembly::BITMASK_I16x8, WebAssembly::BITMASK_I16x8_S }, { WebAssembly::BITMASK_I32x4, WebAssembly::BITMASK_I32x4_S }, { WebAssembly::BITMASK_I64x2, WebAssembly::BITMASK_I64x2_S }, { WebAssembly::BITMASK_I8x16, WebAssembly::BITMASK_I8x16_S }, { WebAssembly::BITSELECT, WebAssembly::BITSELECT_S }, { WebAssembly::BLOCK, WebAssembly::BLOCK_S }, { WebAssembly::BR, WebAssembly::BR_S }, { WebAssembly::BR_IF, WebAssembly::BR_IF_S }, { WebAssembly::BR_TABLE_I32, WebAssembly::BR_TABLE_I32_S }, { WebAssembly::BR_TABLE_I64, WebAssembly::BR_TABLE_I64_S }, { WebAssembly::BR_UNLESS, WebAssembly::BR_UNLESS_S }, { WebAssembly::CALL, WebAssembly::CALL_S }, { WebAssembly::CALL_INDIRECT, WebAssembly::CALL_INDIRECT_S }, { WebAssembly::CATCH, WebAssembly::CATCH_S }, { WebAssembly::CATCH_ALL, WebAssembly::CATCH_ALL_S }, { WebAssembly::CEIL_F16x8, WebAssembly::CEIL_F16x8_S }, { WebAssembly::CEIL_F32, WebAssembly::CEIL_F32_S }, { WebAssembly::CEIL_F32x4, WebAssembly::CEIL_F32x4_S }, { WebAssembly::CEIL_F64, WebAssembly::CEIL_F64_S }, { WebAssembly::CEIL_F64x2, WebAssembly::CEIL_F64x2_S }, { WebAssembly::CLZ_I32, WebAssembly::CLZ_I32_S }, { WebAssembly::CLZ_I64, WebAssembly::CLZ_I64_S }, { WebAssembly::CONST_F32, WebAssembly::CONST_F32_S }, { WebAssembly::CONST_F64, WebAssembly::CONST_F64_S }, { WebAssembly::CONST_I32, WebAssembly::CONST_I32_S }, { WebAssembly::CONST_I64, WebAssembly::CONST_I64_S }, { WebAssembly::CONST_V128_F32x4, WebAssembly::CONST_V128_F32x4_S }, { WebAssembly::CONST_V128_F64x2, WebAssembly::CONST_V128_F64x2_S }, { WebAssembly::CONST_V128_I16x8, WebAssembly::CONST_V128_I16x8_S }, { WebAssembly::CONST_V128_I32x4, WebAssembly::CONST_V128_I32x4_S }, { WebAssembly::CONST_V128_I64x2, WebAssembly::CONST_V128_I64x2_S }, { WebAssembly::CONST_V128_I8x16, WebAssembly::CONST_V128_I8x16_S }, { WebAssembly::COPYSIGN_F32, WebAssembly::COPYSIGN_F32_S }, { WebAssembly::COPYSIGN_F64, WebAssembly::COPYSIGN_F64_S }, { WebAssembly::COPY_EXNREF, WebAssembly::COPY_EXNREF_S }, { WebAssembly::COPY_EXTERNREF, WebAssembly::COPY_EXTERNREF_S }, { WebAssembly::COPY_F32, WebAssembly::COPY_F32_S }, { WebAssembly::COPY_F64, WebAssembly::COPY_F64_S }, { WebAssembly::COPY_FUNCREF, WebAssembly::COPY_FUNCREF_S }, { WebAssembly::COPY_I32, WebAssembly::COPY_I32_S }, { WebAssembly::COPY_I64, WebAssembly::COPY_I64_S }, { WebAssembly::COPY_V128, WebAssembly::COPY_V128_S }, { WebAssembly::CTZ_I32, WebAssembly::CTZ_I32_S }, { WebAssembly::CTZ_I64, WebAssembly::CTZ_I64_S }, { WebAssembly::DEBUG_UNREACHABLE, WebAssembly::DEBUG_UNREACHABLE_S }, { WebAssembly::DELEGATE, WebAssembly::DELEGATE_S }, { WebAssembly::DIV_F16x8, WebAssembly::DIV_F16x8_S }, { WebAssembly::DIV_F32, WebAssembly::DIV_F32_S }, { WebAssembly::DIV_F32x4, WebAssembly::DIV_F32x4_S }, { WebAssembly::DIV_F64, WebAssembly::DIV_F64_S }, { WebAssembly::DIV_F64x2, WebAssembly::DIV_F64x2_S }, { WebAssembly::DIV_S_I32, WebAssembly::DIV_S_I32_S }, { WebAssembly::DIV_S_I64, WebAssembly::DIV_S_I64_S }, { WebAssembly::DIV_U_I32, WebAssembly::DIV_U_I32_S }, { WebAssembly::DIV_U_I64, WebAssembly::DIV_U_I64_S }, { WebAssembly::DOT, WebAssembly::DOT_S }, { WebAssembly::DROP_EXNREF, WebAssembly::DROP_EXNREF_S }, { WebAssembly::DROP_EXTERNREF, WebAssembly::DROP_EXTERNREF_S }, { WebAssembly::DROP_F32, WebAssembly::DROP_F32_S }, { WebAssembly::DROP_F64, WebAssembly::DROP_F64_S }, { WebAssembly::DROP_FUNCREF, WebAssembly::DROP_FUNCREF_S }, { WebAssembly::DROP_I32, WebAssembly::DROP_I32_S }, { WebAssembly::DROP_I64, WebAssembly::DROP_I64_S }, { WebAssembly::DROP_V128, WebAssembly::DROP_V128_S }, { WebAssembly::ELSE, WebAssembly::ELSE_S }, { WebAssembly::END, WebAssembly::END_S }, { WebAssembly::END_BLOCK, WebAssembly::END_BLOCK_S }, { WebAssembly::END_FUNCTION, WebAssembly::END_FUNCTION_S }, { WebAssembly::END_IF, WebAssembly::END_IF_S }, { WebAssembly::END_LOOP, WebAssembly::END_LOOP_S }, { WebAssembly::END_TRY, WebAssembly::END_TRY_S }, { WebAssembly::EQZ_I32, WebAssembly::EQZ_I32_S }, { WebAssembly::EQZ_I64, WebAssembly::EQZ_I64_S }, { WebAssembly::EQ_F16x8, WebAssembly::EQ_F16x8_S }, { WebAssembly::EQ_F32, WebAssembly::EQ_F32_S }, { WebAssembly::EQ_F32x4, WebAssembly::EQ_F32x4_S }, { WebAssembly::EQ_F64, WebAssembly::EQ_F64_S }, { WebAssembly::EQ_F64x2, WebAssembly::EQ_F64x2_S }, { WebAssembly::EQ_I16x8, WebAssembly::EQ_I16x8_S }, { WebAssembly::EQ_I32, WebAssembly::EQ_I32_S }, { WebAssembly::EQ_I32x4, WebAssembly::EQ_I32x4_S }, { WebAssembly::EQ_I64, WebAssembly::EQ_I64_S }, { WebAssembly::EQ_I64x2, WebAssembly::EQ_I64x2_S }, { WebAssembly::EQ_I8x16, WebAssembly::EQ_I8x16_S }, { WebAssembly::EXTMUL_HIGH_S_I16x8, WebAssembly::EXTMUL_HIGH_S_I16x8_S }, { WebAssembly::EXTMUL_HIGH_S_I32x4, WebAssembly::EXTMUL_HIGH_S_I32x4_S }, { WebAssembly::EXTMUL_HIGH_S_I64x2, WebAssembly::EXTMUL_HIGH_S_I64x2_S }, { WebAssembly::EXTMUL_HIGH_U_I16x8, WebAssembly::EXTMUL_HIGH_U_I16x8_S }, { WebAssembly::EXTMUL_HIGH_U_I32x4, WebAssembly::EXTMUL_HIGH_U_I32x4_S }, { WebAssembly::EXTMUL_HIGH_U_I64x2, WebAssembly::EXTMUL_HIGH_U_I64x2_S }, { WebAssembly::EXTMUL_LOW_S_I16x8, WebAssembly::EXTMUL_LOW_S_I16x8_S }, { WebAssembly::EXTMUL_LOW_S_I32x4, WebAssembly::EXTMUL_LOW_S_I32x4_S }, { WebAssembly::EXTMUL_LOW_S_I64x2, WebAssembly::EXTMUL_LOW_S_I64x2_S }, { WebAssembly::EXTMUL_LOW_U_I16x8, WebAssembly::EXTMUL_LOW_U_I16x8_S }, { WebAssembly::EXTMUL_LOW_U_I32x4, WebAssembly::EXTMUL_LOW_U_I32x4_S }, { WebAssembly::EXTMUL_LOW_U_I64x2, WebAssembly::EXTMUL_LOW_U_I64x2_S }, { WebAssembly::EXTRACT_LANE_F16x8, WebAssembly::EXTRACT_LANE_F16x8_S }, { WebAssembly::EXTRACT_LANE_F32x4, WebAssembly::EXTRACT_LANE_F32x4_S }, { WebAssembly::EXTRACT_LANE_F64x2, WebAssembly::EXTRACT_LANE_F64x2_S }, { WebAssembly::EXTRACT_LANE_I16x8_s, WebAssembly::EXTRACT_LANE_I16x8_s_S }, { WebAssembly::EXTRACT_LANE_I16x8_u, WebAssembly::EXTRACT_LANE_I16x8_u_S }, { WebAssembly::EXTRACT_LANE_I32x4, WebAssembly::EXTRACT_LANE_I32x4_S }, { WebAssembly::EXTRACT_LANE_I64x2, WebAssembly::EXTRACT_LANE_I64x2_S }, { WebAssembly::EXTRACT_LANE_I8x16_s, WebAssembly::EXTRACT_LANE_I8x16_s_S }, { WebAssembly::EXTRACT_LANE_I8x16_u, WebAssembly::EXTRACT_LANE_I8x16_u_S }, { WebAssembly::F32_CONVERT_S_I32, WebAssembly::F32_CONVERT_S_I32_S }, { WebAssembly::F32_CONVERT_S_I64, WebAssembly::F32_CONVERT_S_I64_S }, { WebAssembly::F32_CONVERT_U_I32, WebAssembly::F32_CONVERT_U_I32_S }, { WebAssembly::F32_CONVERT_U_I64, WebAssembly::F32_CONVERT_U_I64_S }, { WebAssembly::F32_DEMOTE_F64, WebAssembly::F32_DEMOTE_F64_S }, { WebAssembly::F32_REINTERPRET_I32, WebAssembly::F32_REINTERPRET_I32_S }, { WebAssembly::F64_CONVERT_S_I32, WebAssembly::F64_CONVERT_S_I32_S }, { WebAssembly::F64_CONVERT_S_I64, WebAssembly::F64_CONVERT_S_I64_S }, { WebAssembly::F64_CONVERT_U_I32, WebAssembly::F64_CONVERT_U_I32_S }, { WebAssembly::F64_CONVERT_U_I64, WebAssembly::F64_CONVERT_U_I64_S }, { WebAssembly::F64_PROMOTE_F32, WebAssembly::F64_PROMOTE_F32_S }, { WebAssembly::F64_REINTERPRET_I64, WebAssembly::F64_REINTERPRET_I64_S }, { WebAssembly::FALLTHROUGH_RETURN, WebAssembly::FALLTHROUGH_RETURN_S }, { WebAssembly::FLOOR_F16x8, WebAssembly::FLOOR_F16x8_S }, { WebAssembly::FLOOR_F32, WebAssembly::FLOOR_F32_S }, { WebAssembly::FLOOR_F32x4, WebAssembly::FLOOR_F32x4_S }, { WebAssembly::FLOOR_F64, WebAssembly::FLOOR_F64_S }, { WebAssembly::FLOOR_F64x2, WebAssembly::FLOOR_F64x2_S }, { WebAssembly::FP_TO_SINT_I32_F32, WebAssembly::FP_TO_SINT_I32_F32_S }, { WebAssembly::FP_TO_SINT_I32_F64, WebAssembly::FP_TO_SINT_I32_F64_S }, { WebAssembly::FP_TO_SINT_I64_F32, WebAssembly::FP_TO_SINT_I64_F32_S }, { WebAssembly::FP_TO_SINT_I64_F64, WebAssembly::FP_TO_SINT_I64_F64_S }, { WebAssembly::FP_TO_UINT_I32_F32, WebAssembly::FP_TO_UINT_I32_F32_S }, { WebAssembly::FP_TO_UINT_I32_F64, WebAssembly::FP_TO_UINT_I32_F64_S }, { WebAssembly::FP_TO_UINT_I64_F32, WebAssembly::FP_TO_UINT_I64_F32_S }, { WebAssembly::FP_TO_UINT_I64_F64, WebAssembly::FP_TO_UINT_I64_F64_S }, { WebAssembly::GE_F16x8, WebAssembly::GE_F16x8_S }, { WebAssembly::GE_F32, WebAssembly::GE_F32_S }, { WebAssembly::GE_F32x4, WebAssembly::GE_F32x4_S }, { WebAssembly::GE_F64, WebAssembly::GE_F64_S }, { WebAssembly::GE_F64x2, WebAssembly::GE_F64x2_S }, { WebAssembly::GE_S_I16x8, WebAssembly::GE_S_I16x8_S }, { WebAssembly::GE_S_I32, WebAssembly::GE_S_I32_S }, { WebAssembly::GE_S_I32x4, WebAssembly::GE_S_I32x4_S }, { WebAssembly::GE_S_I64, WebAssembly::GE_S_I64_S }, { WebAssembly::GE_S_I64x2, WebAssembly::GE_S_I64x2_S }, { WebAssembly::GE_S_I8x16, WebAssembly::GE_S_I8x16_S }, { WebAssembly::GE_U_I16x8, WebAssembly::GE_U_I16x8_S }, { WebAssembly::GE_U_I32, WebAssembly::GE_U_I32_S }, { WebAssembly::GE_U_I32x4, WebAssembly::GE_U_I32x4_S }, { WebAssembly::GE_U_I64, WebAssembly::GE_U_I64_S }, { WebAssembly::GE_U_I8x16, WebAssembly::GE_U_I8x16_S }, { WebAssembly::GLOBAL_GET_EXNREF, WebAssembly::GLOBAL_GET_EXNREF_S }, { WebAssembly::GLOBAL_GET_EXTERNREF, WebAssembly::GLOBAL_GET_EXTERNREF_S }, { WebAssembly::GLOBAL_GET_F32, WebAssembly::GLOBAL_GET_F32_S }, { WebAssembly::GLOBAL_GET_F64, WebAssembly::GLOBAL_GET_F64_S }, { WebAssembly::GLOBAL_GET_FUNCREF, WebAssembly::GLOBAL_GET_FUNCREF_S }, { WebAssembly::GLOBAL_GET_I32, WebAssembly::GLOBAL_GET_I32_S }, { WebAssembly::GLOBAL_GET_I64, WebAssembly::GLOBAL_GET_I64_S }, { WebAssembly::GLOBAL_GET_V128, WebAssembly::GLOBAL_GET_V128_S }, { WebAssembly::GLOBAL_SET_EXNREF, WebAssembly::GLOBAL_SET_EXNREF_S }, { WebAssembly::GLOBAL_SET_EXTERNREF, WebAssembly::GLOBAL_SET_EXTERNREF_S }, { WebAssembly::GLOBAL_SET_F32, WebAssembly::GLOBAL_SET_F32_S }, { WebAssembly::GLOBAL_SET_F64, WebAssembly::GLOBAL_SET_F64_S }, { WebAssembly::GLOBAL_SET_FUNCREF, WebAssembly::GLOBAL_SET_FUNCREF_S }, { WebAssembly::GLOBAL_SET_I32, WebAssembly::GLOBAL_SET_I32_S }, { WebAssembly::GLOBAL_SET_I64, WebAssembly::GLOBAL_SET_I64_S }, { WebAssembly::GLOBAL_SET_V128, WebAssembly::GLOBAL_SET_V128_S }, { WebAssembly::GT_F16x8, WebAssembly::GT_F16x8_S }, { WebAssembly::GT_F32, WebAssembly::GT_F32_S }, { WebAssembly::GT_F32x4, WebAssembly::GT_F32x4_S }, { WebAssembly::GT_F64, WebAssembly::GT_F64_S }, { WebAssembly::GT_F64x2, WebAssembly::GT_F64x2_S }, { WebAssembly::GT_S_I16x8, WebAssembly::GT_S_I16x8_S }, { WebAssembly::GT_S_I32, WebAssembly::GT_S_I32_S }, { WebAssembly::GT_S_I32x4, WebAssembly::GT_S_I32x4_S }, { WebAssembly::GT_S_I64, WebAssembly::GT_S_I64_S }, { WebAssembly::GT_S_I64x2, WebAssembly::GT_S_I64x2_S }, { WebAssembly::GT_S_I8x16, WebAssembly::GT_S_I8x16_S }, { WebAssembly::GT_U_I16x8, WebAssembly::GT_U_I16x8_S }, { WebAssembly::GT_U_I32, WebAssembly::GT_U_I32_S }, { WebAssembly::GT_U_I32x4, WebAssembly::GT_U_I32x4_S }, { WebAssembly::GT_U_I64, WebAssembly::GT_U_I64_S }, { WebAssembly::GT_U_I8x16, WebAssembly::GT_U_I8x16_S }, { WebAssembly::I32_EXTEND16_S_I32, WebAssembly::I32_EXTEND16_S_I32_S }, { WebAssembly::I32_EXTEND8_S_I32, WebAssembly::I32_EXTEND8_S_I32_S }, { WebAssembly::I32_REINTERPRET_F32, WebAssembly::I32_REINTERPRET_F32_S }, { WebAssembly::I32_TRUNC_S_F32, WebAssembly::I32_TRUNC_S_F32_S }, { WebAssembly::I32_TRUNC_S_F64, WebAssembly::I32_TRUNC_S_F64_S }, { WebAssembly::I32_TRUNC_S_SAT_F32, WebAssembly::I32_TRUNC_S_SAT_F32_S }, { WebAssembly::I32_TRUNC_S_SAT_F64, WebAssembly::I32_TRUNC_S_SAT_F64_S }, { WebAssembly::I32_TRUNC_U_F32, WebAssembly::I32_TRUNC_U_F32_S }, { WebAssembly::I32_TRUNC_U_F64, WebAssembly::I32_TRUNC_U_F64_S }, { WebAssembly::I32_TRUNC_U_SAT_F32, WebAssembly::I32_TRUNC_U_SAT_F32_S }, { WebAssembly::I32_TRUNC_U_SAT_F64, WebAssembly::I32_TRUNC_U_SAT_F64_S }, { WebAssembly::I32_WRAP_I64, WebAssembly::I32_WRAP_I64_S }, { WebAssembly::I64_EXTEND16_S_I64, WebAssembly::I64_EXTEND16_S_I64_S }, { WebAssembly::I64_EXTEND32_S_I64, WebAssembly::I64_EXTEND32_S_I64_S }, { WebAssembly::I64_EXTEND8_S_I64, WebAssembly::I64_EXTEND8_S_I64_S }, { WebAssembly::I64_EXTEND_S_I32, WebAssembly::I64_EXTEND_S_I32_S }, { WebAssembly::I64_EXTEND_U_I32, WebAssembly::I64_EXTEND_U_I32_S }, { WebAssembly::I64_REINTERPRET_F64, WebAssembly::I64_REINTERPRET_F64_S }, { WebAssembly::I64_TRUNC_S_F32, WebAssembly::I64_TRUNC_S_F32_S }, { WebAssembly::I64_TRUNC_S_F64, WebAssembly::I64_TRUNC_S_F64_S }, { WebAssembly::I64_TRUNC_S_SAT_F32, WebAssembly::I64_TRUNC_S_SAT_F32_S }, { WebAssembly::I64_TRUNC_S_SAT_F64, WebAssembly::I64_TRUNC_S_SAT_F64_S }, { WebAssembly::I64_TRUNC_U_F32, WebAssembly::I64_TRUNC_U_F32_S }, { WebAssembly::I64_TRUNC_U_F64, WebAssembly::I64_TRUNC_U_F64_S }, { WebAssembly::I64_TRUNC_U_SAT_F32, WebAssembly::I64_TRUNC_U_SAT_F32_S }, { WebAssembly::I64_TRUNC_U_SAT_F64, WebAssembly::I64_TRUNC_U_SAT_F64_S }, { WebAssembly::IF, WebAssembly::IF_S }, { WebAssembly::LANESELECT_I16x8, WebAssembly::LANESELECT_I16x8_S }, { WebAssembly::LANESELECT_I32x4, WebAssembly::LANESELECT_I32x4_S }, { WebAssembly::LANESELECT_I64x2, WebAssembly::LANESELECT_I64x2_S }, { WebAssembly::LANESELECT_I8x16, WebAssembly::LANESELECT_I8x16_S }, { WebAssembly::LE_F16x8, WebAssembly::LE_F16x8_S }, { WebAssembly::LE_F32, WebAssembly::LE_F32_S }, { WebAssembly::LE_F32x4, WebAssembly::LE_F32x4_S }, { WebAssembly::LE_F64, WebAssembly::LE_F64_S }, { WebAssembly::LE_F64x2, WebAssembly::LE_F64x2_S }, { WebAssembly::LE_S_I16x8, WebAssembly::LE_S_I16x8_S }, { WebAssembly::LE_S_I32, WebAssembly::LE_S_I32_S }, { WebAssembly::LE_S_I32x4, WebAssembly::LE_S_I32x4_S }, { WebAssembly::LE_S_I64, WebAssembly::LE_S_I64_S }, { WebAssembly::LE_S_I64x2, WebAssembly::LE_S_I64x2_S }, { WebAssembly::LE_S_I8x16, WebAssembly::LE_S_I8x16_S }, { WebAssembly::LE_U_I16x8, WebAssembly::LE_U_I16x8_S }, { WebAssembly::LE_U_I32, WebAssembly::LE_U_I32_S }, { WebAssembly::LE_U_I32x4, WebAssembly::LE_U_I32x4_S }, { WebAssembly::LE_U_I64, WebAssembly::LE_U_I64_S }, { WebAssembly::LE_U_I8x16, WebAssembly::LE_U_I8x16_S }, { WebAssembly::LOAD16_SPLAT_A32, WebAssembly::LOAD16_SPLAT_A32_S }, { WebAssembly::LOAD16_SPLAT_A64, WebAssembly::LOAD16_SPLAT_A64_S }, { WebAssembly::LOAD16_S_I32_A32, WebAssembly::LOAD16_S_I32_A32_S }, { WebAssembly::LOAD16_S_I32_A64, WebAssembly::LOAD16_S_I32_A64_S }, { WebAssembly::LOAD16_S_I64_A32, WebAssembly::LOAD16_S_I64_A32_S }, { WebAssembly::LOAD16_S_I64_A64, WebAssembly::LOAD16_S_I64_A64_S }, { WebAssembly::LOAD16_U_I32_A32, WebAssembly::LOAD16_U_I32_A32_S }, { WebAssembly::LOAD16_U_I32_A64, WebAssembly::LOAD16_U_I32_A64_S }, { WebAssembly::LOAD16_U_I64_A32, WebAssembly::LOAD16_U_I64_A32_S }, { WebAssembly::LOAD16_U_I64_A64, WebAssembly::LOAD16_U_I64_A64_S }, { WebAssembly::LOAD32_SPLAT_A32, WebAssembly::LOAD32_SPLAT_A32_S }, { WebAssembly::LOAD32_SPLAT_A64, WebAssembly::LOAD32_SPLAT_A64_S }, { WebAssembly::LOAD32_S_I64_A32, WebAssembly::LOAD32_S_I64_A32_S }, { WebAssembly::LOAD32_S_I64_A64, WebAssembly::LOAD32_S_I64_A64_S }, { WebAssembly::LOAD32_U_I64_A32, WebAssembly::LOAD32_U_I64_A32_S }, { WebAssembly::LOAD32_U_I64_A64, WebAssembly::LOAD32_U_I64_A64_S }, { WebAssembly::LOAD64_SPLAT_A32, WebAssembly::LOAD64_SPLAT_A32_S }, { WebAssembly::LOAD64_SPLAT_A64, WebAssembly::LOAD64_SPLAT_A64_S }, { WebAssembly::LOAD8_SPLAT_A32, WebAssembly::LOAD8_SPLAT_A32_S }, { WebAssembly::LOAD8_SPLAT_A64, WebAssembly::LOAD8_SPLAT_A64_S }, { WebAssembly::LOAD8_S_I32_A32, WebAssembly::LOAD8_S_I32_A32_S }, { WebAssembly::LOAD8_S_I32_A64, WebAssembly::LOAD8_S_I32_A64_S }, { WebAssembly::LOAD8_S_I64_A32, WebAssembly::LOAD8_S_I64_A32_S }, { WebAssembly::LOAD8_S_I64_A64, WebAssembly::LOAD8_S_I64_A64_S }, { WebAssembly::LOAD8_U_I32_A32, WebAssembly::LOAD8_U_I32_A32_S }, { WebAssembly::LOAD8_U_I32_A64, WebAssembly::LOAD8_U_I32_A64_S }, { WebAssembly::LOAD8_U_I64_A32, WebAssembly::LOAD8_U_I64_A32_S }, { WebAssembly::LOAD8_U_I64_A64, WebAssembly::LOAD8_U_I64_A64_S }, { WebAssembly::LOAD_EXTEND_S_I16x8_A32, WebAssembly::LOAD_EXTEND_S_I16x8_A32_S }, { WebAssembly::LOAD_EXTEND_S_I16x8_A64, WebAssembly::LOAD_EXTEND_S_I16x8_A64_S }, { WebAssembly::LOAD_EXTEND_S_I32x4_A32, WebAssembly::LOAD_EXTEND_S_I32x4_A32_S }, { WebAssembly::LOAD_EXTEND_S_I32x4_A64, WebAssembly::LOAD_EXTEND_S_I32x4_A64_S }, { WebAssembly::LOAD_EXTEND_S_I64x2_A32, WebAssembly::LOAD_EXTEND_S_I64x2_A32_S }, { WebAssembly::LOAD_EXTEND_S_I64x2_A64, WebAssembly::LOAD_EXTEND_S_I64x2_A64_S }, { WebAssembly::LOAD_EXTEND_U_I16x8_A32, WebAssembly::LOAD_EXTEND_U_I16x8_A32_S }, { WebAssembly::LOAD_EXTEND_U_I16x8_A64, WebAssembly::LOAD_EXTEND_U_I16x8_A64_S }, { WebAssembly::LOAD_EXTEND_U_I32x4_A32, WebAssembly::LOAD_EXTEND_U_I32x4_A32_S }, { WebAssembly::LOAD_EXTEND_U_I32x4_A64, WebAssembly::LOAD_EXTEND_U_I32x4_A64_S }, { WebAssembly::LOAD_EXTEND_U_I64x2_A32, WebAssembly::LOAD_EXTEND_U_I64x2_A32_S }, { WebAssembly::LOAD_EXTEND_U_I64x2_A64, WebAssembly::LOAD_EXTEND_U_I64x2_A64_S }, { WebAssembly::LOAD_F16_F32_A32, WebAssembly::LOAD_F16_F32_A32_S }, { WebAssembly::LOAD_F16_F32_A64, WebAssembly::LOAD_F16_F32_A64_S }, { WebAssembly::LOAD_F32_A32, WebAssembly::LOAD_F32_A32_S }, { WebAssembly::LOAD_F32_A64, WebAssembly::LOAD_F32_A64_S }, { WebAssembly::LOAD_F64_A32, WebAssembly::LOAD_F64_A32_S }, { WebAssembly::LOAD_F64_A64, WebAssembly::LOAD_F64_A64_S }, { WebAssembly::LOAD_I32_A32, WebAssembly::LOAD_I32_A32_S }, { WebAssembly::LOAD_I32_A64, WebAssembly::LOAD_I32_A64_S }, { WebAssembly::LOAD_I64_A32, WebAssembly::LOAD_I64_A32_S }, { WebAssembly::LOAD_I64_A64, WebAssembly::LOAD_I64_A64_S }, { WebAssembly::LOAD_LANE_16_A32, WebAssembly::LOAD_LANE_16_A32_S }, { WebAssembly::LOAD_LANE_16_A64, WebAssembly::LOAD_LANE_16_A64_S }, { WebAssembly::LOAD_LANE_32_A32, WebAssembly::LOAD_LANE_32_A32_S }, { WebAssembly::LOAD_LANE_32_A64, WebAssembly::LOAD_LANE_32_A64_S }, { WebAssembly::LOAD_LANE_64_A32, WebAssembly::LOAD_LANE_64_A32_S }, { WebAssembly::LOAD_LANE_64_A64, WebAssembly::LOAD_LANE_64_A64_S }, { WebAssembly::LOAD_LANE_8_A32, WebAssembly::LOAD_LANE_8_A32_S }, { WebAssembly::LOAD_LANE_8_A64, WebAssembly::LOAD_LANE_8_A64_S }, { WebAssembly::LOAD_V128_A32, WebAssembly::LOAD_V128_A32_S }, { WebAssembly::LOAD_V128_A64, WebAssembly::LOAD_V128_A64_S }, { WebAssembly::LOAD_ZERO_32_A32, WebAssembly::LOAD_ZERO_32_A32_S }, { WebAssembly::LOAD_ZERO_32_A64, WebAssembly::LOAD_ZERO_32_A64_S }, { WebAssembly::LOAD_ZERO_64_A32, WebAssembly::LOAD_ZERO_64_A32_S }, { WebAssembly::LOAD_ZERO_64_A64, WebAssembly::LOAD_ZERO_64_A64_S }, { WebAssembly::LOCAL_GET_EXNREF, WebAssembly::LOCAL_GET_EXNREF_S }, { WebAssembly::LOCAL_GET_EXTERNREF, WebAssembly::LOCAL_GET_EXTERNREF_S }, { WebAssembly::LOCAL_GET_F32, WebAssembly::LOCAL_GET_F32_S }, { WebAssembly::LOCAL_GET_F64, WebAssembly::LOCAL_GET_F64_S }, { WebAssembly::LOCAL_GET_FUNCREF, WebAssembly::LOCAL_GET_FUNCREF_S }, { WebAssembly::LOCAL_GET_I32, WebAssembly::LOCAL_GET_I32_S }, { WebAssembly::LOCAL_GET_I64, WebAssembly::LOCAL_GET_I64_S }, { WebAssembly::LOCAL_GET_V128, WebAssembly::LOCAL_GET_V128_S }, { WebAssembly::LOCAL_SET_EXNREF, WebAssembly::LOCAL_SET_EXNREF_S }, { WebAssembly::LOCAL_SET_EXTERNREF, WebAssembly::LOCAL_SET_EXTERNREF_S }, { WebAssembly::LOCAL_SET_F32, WebAssembly::LOCAL_SET_F32_S }, { WebAssembly::LOCAL_SET_F64, WebAssembly::LOCAL_SET_F64_S }, { WebAssembly::LOCAL_SET_FUNCREF, WebAssembly::LOCAL_SET_FUNCREF_S }, { WebAssembly::LOCAL_SET_I32, WebAssembly::LOCAL_SET_I32_S }, { WebAssembly::LOCAL_SET_I64, WebAssembly::LOCAL_SET_I64_S }, { WebAssembly::LOCAL_SET_V128, WebAssembly::LOCAL_SET_V128_S }, { WebAssembly::LOCAL_TEE_EXNREF, WebAssembly::LOCAL_TEE_EXNREF_S }, { WebAssembly::LOCAL_TEE_EXTERNREF, WebAssembly::LOCAL_TEE_EXTERNREF_S }, { WebAssembly::LOCAL_TEE_F32, WebAssembly::LOCAL_TEE_F32_S }, { WebAssembly::LOCAL_TEE_F64, WebAssembly::LOCAL_TEE_F64_S }, { WebAssembly::LOCAL_TEE_FUNCREF, WebAssembly::LOCAL_TEE_FUNCREF_S }, { WebAssembly::LOCAL_TEE_I32, WebAssembly::LOCAL_TEE_I32_S }, { WebAssembly::LOCAL_TEE_I64, WebAssembly::LOCAL_TEE_I64_S }, { WebAssembly::LOCAL_TEE_V128, WebAssembly::LOCAL_TEE_V128_S }, { WebAssembly::LOOP, WebAssembly::LOOP_S }, { WebAssembly::LT_F16x8, WebAssembly::LT_F16x8_S }, { WebAssembly::LT_F32, WebAssembly::LT_F32_S }, { WebAssembly::LT_F32x4, WebAssembly::LT_F32x4_S }, { WebAssembly::LT_F64, WebAssembly::LT_F64_S }, { WebAssembly::LT_F64x2, WebAssembly::LT_F64x2_S }, { WebAssembly::LT_S_I16x8, WebAssembly::LT_S_I16x8_S }, { WebAssembly::LT_S_I32, WebAssembly::LT_S_I32_S }, { WebAssembly::LT_S_I32x4, WebAssembly::LT_S_I32x4_S }, { WebAssembly::LT_S_I64, WebAssembly::LT_S_I64_S }, { WebAssembly::LT_S_I64x2, WebAssembly::LT_S_I64x2_S }, { WebAssembly::LT_S_I8x16, WebAssembly::LT_S_I8x16_S }, { WebAssembly::LT_U_I16x8, WebAssembly::LT_U_I16x8_S }, { WebAssembly::LT_U_I32, WebAssembly::LT_U_I32_S }, { WebAssembly::LT_U_I32x4, WebAssembly::LT_U_I32x4_S }, { WebAssembly::LT_U_I64, WebAssembly::LT_U_I64_S }, { WebAssembly::LT_U_I8x16, WebAssembly::LT_U_I8x16_S }, { WebAssembly::MADD_F16x8, WebAssembly::MADD_F16x8_S }, { WebAssembly::MADD_F32x4, WebAssembly::MADD_F32x4_S }, { WebAssembly::MADD_F64x2, WebAssembly::MADD_F64x2_S }, { WebAssembly::MAX_F16x8, WebAssembly::MAX_F16x8_S }, { WebAssembly::MAX_F32, WebAssembly::MAX_F32_S }, { WebAssembly::MAX_F32x4, WebAssembly::MAX_F32x4_S }, { WebAssembly::MAX_F64, WebAssembly::MAX_F64_S }, { WebAssembly::MAX_F64x2, WebAssembly::MAX_F64x2_S }, { WebAssembly::MAX_S_I16x8, WebAssembly::MAX_S_I16x8_S }, { WebAssembly::MAX_S_I32x4, WebAssembly::MAX_S_I32x4_S }, { WebAssembly::MAX_S_I8x16, WebAssembly::MAX_S_I8x16_S }, { WebAssembly::MAX_U_I16x8, WebAssembly::MAX_U_I16x8_S }, { WebAssembly::MAX_U_I32x4, WebAssembly::MAX_U_I32x4_S }, { WebAssembly::MAX_U_I8x16, WebAssembly::MAX_U_I8x16_S }, { WebAssembly::MEMORY_ATOMIC_NOTIFY_A32, WebAssembly::MEMORY_ATOMIC_NOTIFY_A32_S }, { WebAssembly::MEMORY_ATOMIC_NOTIFY_A64, WebAssembly::MEMORY_ATOMIC_NOTIFY_A64_S }, { WebAssembly::MEMORY_ATOMIC_WAIT32_A32, WebAssembly::MEMORY_ATOMIC_WAIT32_A32_S }, { WebAssembly::MEMORY_ATOMIC_WAIT32_A64, WebAssembly::MEMORY_ATOMIC_WAIT32_A64_S }, { WebAssembly::MEMORY_ATOMIC_WAIT64_A32, WebAssembly::MEMORY_ATOMIC_WAIT64_A32_S }, { WebAssembly::MEMORY_ATOMIC_WAIT64_A64, WebAssembly::MEMORY_ATOMIC_WAIT64_A64_S }, { WebAssembly::MIN_F16x8, WebAssembly::MIN_F16x8_S }, { WebAssembly::MIN_F32, WebAssembly::MIN_F32_S }, { WebAssembly::MIN_F32x4, WebAssembly::MIN_F32x4_S }, { WebAssembly::MIN_F64, WebAssembly::MIN_F64_S }, { WebAssembly::MIN_F64x2, WebAssembly::MIN_F64x2_S }, { WebAssembly::MIN_S_I16x8, WebAssembly::MIN_S_I16x8_S }, { WebAssembly::MIN_S_I32x4, WebAssembly::MIN_S_I32x4_S }, { WebAssembly::MIN_S_I8x16, WebAssembly::MIN_S_I8x16_S }, { WebAssembly::MIN_U_I16x8, WebAssembly::MIN_U_I16x8_S }, { WebAssembly::MIN_U_I32x4, WebAssembly::MIN_U_I32x4_S }, { WebAssembly::MIN_U_I8x16, WebAssembly::MIN_U_I8x16_S }, { WebAssembly::MUL_F16x8, WebAssembly::MUL_F16x8_S }, { WebAssembly::MUL_F32, WebAssembly::MUL_F32_S }, { WebAssembly::MUL_F32x4, WebAssembly::MUL_F32x4_S }, { WebAssembly::MUL_F64, WebAssembly::MUL_F64_S }, { WebAssembly::MUL_F64x2, WebAssembly::MUL_F64x2_S }, { WebAssembly::MUL_I16x8, WebAssembly::MUL_I16x8_S }, { WebAssembly::MUL_I32, WebAssembly::MUL_I32_S }, { WebAssembly::MUL_I32x4, WebAssembly::MUL_I32x4_S }, { WebAssembly::MUL_I64, WebAssembly::MUL_I64_S }, { WebAssembly::MUL_I64x2, WebAssembly::MUL_I64x2_S }, { WebAssembly::NARROW_S_I16x8, WebAssembly::NARROW_S_I16x8_S }, { WebAssembly::NARROW_S_I8x16, WebAssembly::NARROW_S_I8x16_S }, { WebAssembly::NARROW_U_I16x8, WebAssembly::NARROW_U_I16x8_S }, { WebAssembly::NARROW_U_I8x16, WebAssembly::NARROW_U_I8x16_S }, { WebAssembly::NEAREST_F16x8, WebAssembly::NEAREST_F16x8_S }, { WebAssembly::NEAREST_F32, WebAssembly::NEAREST_F32_S }, { WebAssembly::NEAREST_F32x4, WebAssembly::NEAREST_F32x4_S }, { WebAssembly::NEAREST_F64, WebAssembly::NEAREST_F64_S }, { WebAssembly::NEAREST_F64x2, WebAssembly::NEAREST_F64x2_S }, { WebAssembly::NEG_F16x8, WebAssembly::NEG_F16x8_S }, { WebAssembly::NEG_F32, WebAssembly::NEG_F32_S }, { WebAssembly::NEG_F32x4, WebAssembly::NEG_F32x4_S }, { WebAssembly::NEG_F64, WebAssembly::NEG_F64_S }, { WebAssembly::NEG_F64x2, WebAssembly::NEG_F64x2_S }, { WebAssembly::NEG_I16x8, WebAssembly::NEG_I16x8_S }, { WebAssembly::NEG_I32x4, WebAssembly::NEG_I32x4_S }, { WebAssembly::NEG_I64x2, WebAssembly::NEG_I64x2_S }, { WebAssembly::NEG_I8x16, WebAssembly::NEG_I8x16_S }, { WebAssembly::NE_F16x8, WebAssembly::NE_F16x8_S }, { WebAssembly::NE_F32, WebAssembly::NE_F32_S }, { WebAssembly::NE_F32x4, WebAssembly::NE_F32x4_S }, { WebAssembly::NE_F64, WebAssembly::NE_F64_S }, { WebAssembly::NE_F64x2, WebAssembly::NE_F64x2_S }, { WebAssembly::NE_I16x8, WebAssembly::NE_I16x8_S }, { WebAssembly::NE_I32, WebAssembly::NE_I32_S }, { WebAssembly::NE_I32x4, WebAssembly::NE_I32x4_S }, { WebAssembly::NE_I64, WebAssembly::NE_I64_S }, { WebAssembly::NE_I64x2, WebAssembly::NE_I64x2_S }, { WebAssembly::NE_I8x16, WebAssembly::NE_I8x16_S }, { WebAssembly::NMADD_F16x8, WebAssembly::NMADD_F16x8_S }, { WebAssembly::NMADD_F32x4, WebAssembly::NMADD_F32x4_S }, { WebAssembly::NMADD_F64x2, WebAssembly::NMADD_F64x2_S }, { WebAssembly::NOP, WebAssembly::NOP_S }, { WebAssembly::NOT, WebAssembly::NOT_S }, { WebAssembly::OR, WebAssembly::OR_S }, { WebAssembly::OR_I32, WebAssembly::OR_I32_S }, { WebAssembly::OR_I64, WebAssembly::OR_I64_S }, { WebAssembly::PMAX_F16x8, WebAssembly::PMAX_F16x8_S }, { WebAssembly::PMAX_F32x4, WebAssembly::PMAX_F32x4_S }, { WebAssembly::PMAX_F64x2, WebAssembly::PMAX_F64x2_S }, { WebAssembly::PMIN_F16x8, WebAssembly::PMIN_F16x8_S }, { WebAssembly::PMIN_F32x4, WebAssembly::PMIN_F32x4_S }, { WebAssembly::PMIN_F64x2, WebAssembly::PMIN_F64x2_S }, { WebAssembly::POPCNT_I32, WebAssembly::POPCNT_I32_S }, { WebAssembly::POPCNT_I64, WebAssembly::POPCNT_I64_S }, { WebAssembly::POPCNT_I8x16, WebAssembly::POPCNT_I8x16_S }, { WebAssembly::Q15MULR_SAT_S_I16x8, WebAssembly::Q15MULR_SAT_S_I16x8_S }, { WebAssembly::REF_IS_NULL_EXNREF, WebAssembly::REF_IS_NULL_EXNREF_S }, { WebAssembly::REF_IS_NULL_EXTERNREF, WebAssembly::REF_IS_NULL_EXTERNREF_S }, { WebAssembly::REF_IS_NULL_FUNCREF, WebAssembly::REF_IS_NULL_FUNCREF_S }, { WebAssembly::REF_NULL_EXNREF, WebAssembly::REF_NULL_EXNREF_S }, { WebAssembly::REF_NULL_EXTERNREF, WebAssembly::REF_NULL_EXTERNREF_S }, { WebAssembly::REF_NULL_FUNCREF, WebAssembly::REF_NULL_FUNCREF_S }, { WebAssembly::RELAXED_DOT, WebAssembly::RELAXED_DOT_S }, { WebAssembly::RELAXED_DOT_ADD, WebAssembly::RELAXED_DOT_ADD_S }, { WebAssembly::RELAXED_DOT_BFLOAT, WebAssembly::RELAXED_DOT_BFLOAT_S }, { WebAssembly::RELAXED_Q15MULR_S_I16x8, WebAssembly::RELAXED_Q15MULR_S_I16x8_S }, { WebAssembly::RELAXED_SWIZZLE, WebAssembly::RELAXED_SWIZZLE_S }, { WebAssembly::REM_S_I32, WebAssembly::REM_S_I32_S }, { WebAssembly::REM_S_I64, WebAssembly::REM_S_I64_S }, { WebAssembly::REM_U_I32, WebAssembly::REM_U_I32_S }, { WebAssembly::REM_U_I64, WebAssembly::REM_U_I64_S }, { WebAssembly::REPLACE_LANE_F16x8, WebAssembly::REPLACE_LANE_F16x8_S }, { WebAssembly::REPLACE_LANE_F32x4, WebAssembly::REPLACE_LANE_F32x4_S }, { WebAssembly::REPLACE_LANE_F64x2, WebAssembly::REPLACE_LANE_F64x2_S }, { WebAssembly::REPLACE_LANE_I16x8, WebAssembly::REPLACE_LANE_I16x8_S }, { WebAssembly::REPLACE_LANE_I32x4, WebAssembly::REPLACE_LANE_I32x4_S }, { WebAssembly::REPLACE_LANE_I64x2, WebAssembly::REPLACE_LANE_I64x2_S }, { WebAssembly::REPLACE_LANE_I8x16, WebAssembly::REPLACE_LANE_I8x16_S }, { WebAssembly::RETHROW, WebAssembly::RETHROW_S }, { WebAssembly::RETURN, WebAssembly::RETURN_S }, { WebAssembly::RET_CALL, WebAssembly::RET_CALL_S }, { WebAssembly::RET_CALL_INDIRECT, WebAssembly::RET_CALL_INDIRECT_S }, { WebAssembly::ROTL_I32, WebAssembly::ROTL_I32_S }, { WebAssembly::ROTL_I64, WebAssembly::ROTL_I64_S }, { WebAssembly::ROTR_I32, WebAssembly::ROTR_I32_S }, { WebAssembly::ROTR_I64, WebAssembly::ROTR_I64_S }, { WebAssembly::SELECT_EXNREF, WebAssembly::SELECT_EXNREF_S }, { WebAssembly::SELECT_EXTERNREF, WebAssembly::SELECT_EXTERNREF_S }, { WebAssembly::SELECT_F32, WebAssembly::SELECT_F32_S }, { WebAssembly::SELECT_F64, WebAssembly::SELECT_F64_S }, { WebAssembly::SELECT_FUNCREF, WebAssembly::SELECT_FUNCREF_S }, { WebAssembly::SELECT_I32, WebAssembly::SELECT_I32_S }, { WebAssembly::SELECT_I64, WebAssembly::SELECT_I64_S }, { WebAssembly::SELECT_V128, WebAssembly::SELECT_V128_S }, { WebAssembly::SHL_I16x8, WebAssembly::SHL_I16x8_S }, { WebAssembly::SHL_I32, WebAssembly::SHL_I32_S }, { WebAssembly::SHL_I32x4, WebAssembly::SHL_I32x4_S }, { WebAssembly::SHL_I64, WebAssembly::SHL_I64_S }, { WebAssembly::SHL_I64x2, WebAssembly::SHL_I64x2_S }, { WebAssembly::SHL_I8x16, WebAssembly::SHL_I8x16_S }, { WebAssembly::SHR_S_I16x8, WebAssembly::SHR_S_I16x8_S }, { WebAssembly::SHR_S_I32, WebAssembly::SHR_S_I32_S }, { WebAssembly::SHR_S_I32x4, WebAssembly::SHR_S_I32x4_S }, { WebAssembly::SHR_S_I64, WebAssembly::SHR_S_I64_S }, { WebAssembly::SHR_S_I64x2, WebAssembly::SHR_S_I64x2_S }, { WebAssembly::SHR_S_I8x16, WebAssembly::SHR_S_I8x16_S }, { WebAssembly::SHR_U_I16x8, WebAssembly::SHR_U_I16x8_S }, { WebAssembly::SHR_U_I32, WebAssembly::SHR_U_I32_S }, { WebAssembly::SHR_U_I32x4, WebAssembly::SHR_U_I32x4_S }, { WebAssembly::SHR_U_I64, WebAssembly::SHR_U_I64_S }, { WebAssembly::SHR_U_I64x2, WebAssembly::SHR_U_I64x2_S }, { WebAssembly::SHR_U_I8x16, WebAssembly::SHR_U_I8x16_S }, { WebAssembly::SHUFFLE, WebAssembly::SHUFFLE_S }, { WebAssembly::SIMD_RELAXED_FMAX_F32x4, WebAssembly::SIMD_RELAXED_FMAX_F32x4_S }, { WebAssembly::SIMD_RELAXED_FMAX_F64x2, WebAssembly::SIMD_RELAXED_FMAX_F64x2_S }, { WebAssembly::SIMD_RELAXED_FMIN_F32x4, WebAssembly::SIMD_RELAXED_FMIN_F32x4_S }, { WebAssembly::SIMD_RELAXED_FMIN_F64x2, WebAssembly::SIMD_RELAXED_FMIN_F64x2_S }, { WebAssembly::SPLAT_F16x8, WebAssembly::SPLAT_F16x8_S }, { WebAssembly::SPLAT_F32x4, WebAssembly::SPLAT_F32x4_S }, { WebAssembly::SPLAT_F64x2, WebAssembly::SPLAT_F64x2_S }, { WebAssembly::SPLAT_I16x8, WebAssembly::SPLAT_I16x8_S }, { WebAssembly::SPLAT_I32x4, WebAssembly::SPLAT_I32x4_S }, { WebAssembly::SPLAT_I64x2, WebAssembly::SPLAT_I64x2_S }, { WebAssembly::SPLAT_I8x16, WebAssembly::SPLAT_I8x16_S }, { WebAssembly::SQRT_F16x8, WebAssembly::SQRT_F16x8_S }, { WebAssembly::SQRT_F32, WebAssembly::SQRT_F32_S }, { WebAssembly::SQRT_F32x4, WebAssembly::SQRT_F32x4_S }, { WebAssembly::SQRT_F64, WebAssembly::SQRT_F64_S }, { WebAssembly::SQRT_F64x2, WebAssembly::SQRT_F64x2_S }, { WebAssembly::STORE16_I32_A32, WebAssembly::STORE16_I32_A32_S }, { WebAssembly::STORE16_I32_A64, WebAssembly::STORE16_I32_A64_S }, { WebAssembly::STORE16_I64_A32, WebAssembly::STORE16_I64_A32_S }, { WebAssembly::STORE16_I64_A64, WebAssembly::STORE16_I64_A64_S }, { WebAssembly::STORE32_I64_A32, WebAssembly::STORE32_I64_A32_S }, { WebAssembly::STORE32_I64_A64, WebAssembly::STORE32_I64_A64_S }, { WebAssembly::STORE8_I32_A32, WebAssembly::STORE8_I32_A32_S }, { WebAssembly::STORE8_I32_A64, WebAssembly::STORE8_I32_A64_S }, { WebAssembly::STORE8_I64_A32, WebAssembly::STORE8_I64_A32_S }, { WebAssembly::STORE8_I64_A64, WebAssembly::STORE8_I64_A64_S }, { WebAssembly::STORE_F16_F32_A32, WebAssembly::STORE_F16_F32_A32_S }, { WebAssembly::STORE_F16_F32_A64, WebAssembly::STORE_F16_F32_A64_S }, { WebAssembly::STORE_F32_A32, WebAssembly::STORE_F32_A32_S }, { WebAssembly::STORE_F32_A64, WebAssembly::STORE_F32_A64_S }, { WebAssembly::STORE_F64_A32, WebAssembly::STORE_F64_A32_S }, { WebAssembly::STORE_F64_A64, WebAssembly::STORE_F64_A64_S }, { WebAssembly::STORE_I32_A32, WebAssembly::STORE_I32_A32_S }, { WebAssembly::STORE_I32_A64, WebAssembly::STORE_I32_A64_S }, { WebAssembly::STORE_I64_A32, WebAssembly::STORE_I64_A32_S }, { WebAssembly::STORE_I64_A64, WebAssembly::STORE_I64_A64_S }, { WebAssembly::STORE_LANE_I16x8_A32, WebAssembly::STORE_LANE_I16x8_A32_S }, { WebAssembly::STORE_LANE_I16x8_A64, WebAssembly::STORE_LANE_I16x8_A64_S }, { WebAssembly::STORE_LANE_I32x4_A32, WebAssembly::STORE_LANE_I32x4_A32_S }, { WebAssembly::STORE_LANE_I32x4_A64, WebAssembly::STORE_LANE_I32x4_A64_S }, { WebAssembly::STORE_LANE_I64x2_A32, WebAssembly::STORE_LANE_I64x2_A32_S }, { WebAssembly::STORE_LANE_I64x2_A64, WebAssembly::STORE_LANE_I64x2_A64_S }, { WebAssembly::STORE_LANE_I8x16_A32, WebAssembly::STORE_LANE_I8x16_A32_S }, { WebAssembly::STORE_LANE_I8x16_A64, WebAssembly::STORE_LANE_I8x16_A64_S }, { WebAssembly::STORE_V128_A32, WebAssembly::STORE_V128_A32_S }, { WebAssembly::STORE_V128_A64, WebAssembly::STORE_V128_A64_S }, { WebAssembly::SUB_F16x8, WebAssembly::SUB_F16x8_S }, { WebAssembly::SUB_F32, WebAssembly::SUB_F32_S }, { WebAssembly::SUB_F32x4, WebAssembly::SUB_F32x4_S }, { WebAssembly::SUB_F64, WebAssembly::SUB_F64_S }, { WebAssembly::SUB_F64x2, WebAssembly::SUB_F64x2_S }, { WebAssembly::SUB_I16x8, WebAssembly::SUB_I16x8_S }, { WebAssembly::SUB_I32, WebAssembly::SUB_I32_S }, { WebAssembly::SUB_I32x4, WebAssembly::SUB_I32x4_S }, { WebAssembly::SUB_I64, WebAssembly::SUB_I64_S }, { WebAssembly::SUB_I64x2, WebAssembly::SUB_I64x2_S }, { WebAssembly::SUB_I8x16, WebAssembly::SUB_I8x16_S }, { WebAssembly::SUB_SAT_S_I16x8, WebAssembly::SUB_SAT_S_I16x8_S }, { WebAssembly::SUB_SAT_S_I8x16, WebAssembly::SUB_SAT_S_I8x16_S }, { WebAssembly::SUB_SAT_U_I16x8, WebAssembly::SUB_SAT_U_I16x8_S }, { WebAssembly::SUB_SAT_U_I8x16, WebAssembly::SUB_SAT_U_I8x16_S }, { WebAssembly::SWIZZLE, WebAssembly::SWIZZLE_S }, { WebAssembly::TABLE_COPY, WebAssembly::TABLE_COPY_S }, { WebAssembly::TABLE_FILL_EXNREF, WebAssembly::TABLE_FILL_EXNREF_S }, { WebAssembly::TABLE_FILL_EXTERNREF, WebAssembly::TABLE_FILL_EXTERNREF_S }, { WebAssembly::TABLE_FILL_FUNCREF, WebAssembly::TABLE_FILL_FUNCREF_S }, { WebAssembly::TABLE_GET_EXNREF, WebAssembly::TABLE_GET_EXNREF_S }, { WebAssembly::TABLE_GET_EXTERNREF, WebAssembly::TABLE_GET_EXTERNREF_S }, { WebAssembly::TABLE_GET_FUNCREF, WebAssembly::TABLE_GET_FUNCREF_S }, { WebAssembly::TABLE_GROW_EXNREF, WebAssembly::TABLE_GROW_EXNREF_S }, { WebAssembly::TABLE_GROW_EXTERNREF, WebAssembly::TABLE_GROW_EXTERNREF_S }, { WebAssembly::TABLE_GROW_FUNCREF, WebAssembly::TABLE_GROW_FUNCREF_S }, { WebAssembly::TABLE_SET_EXNREF, WebAssembly::TABLE_SET_EXNREF_S }, { WebAssembly::TABLE_SET_EXTERNREF, WebAssembly::TABLE_SET_EXTERNREF_S }, { WebAssembly::TABLE_SET_FUNCREF, WebAssembly::TABLE_SET_FUNCREF_S }, { WebAssembly::TABLE_SIZE, WebAssembly::TABLE_SIZE_S }, { WebAssembly::TEE_EXNREF, WebAssembly::TEE_EXNREF_S }, { WebAssembly::TEE_EXTERNREF, WebAssembly::TEE_EXTERNREF_S }, { WebAssembly::TEE_F32, WebAssembly::TEE_F32_S }, { WebAssembly::TEE_F64, WebAssembly::TEE_F64_S }, { WebAssembly::TEE_FUNCREF, WebAssembly::TEE_FUNCREF_S }, { WebAssembly::TEE_I32, WebAssembly::TEE_I32_S }, { WebAssembly::TEE_I64, WebAssembly::TEE_I64_S }, { WebAssembly::TEE_V128, WebAssembly::TEE_V128_S }, { WebAssembly::THROW, WebAssembly::THROW_S }, { WebAssembly::TRUNC_F16x8, WebAssembly::TRUNC_F16x8_S }, { WebAssembly::TRUNC_F32, WebAssembly::TRUNC_F32_S }, { WebAssembly::TRUNC_F32x4, WebAssembly::TRUNC_F32x4_S }, { WebAssembly::TRUNC_F64, WebAssembly::TRUNC_F64_S }, { WebAssembly::TRUNC_F64x2, WebAssembly::TRUNC_F64x2_S }, { WebAssembly::TRY, WebAssembly::TRY_S }, { WebAssembly::UNREACHABLE, WebAssembly::UNREACHABLE_S }, { WebAssembly::XOR, WebAssembly::XOR_S }, { WebAssembly::XOR_I32, WebAssembly::XOR_I32_S }, { WebAssembly::XOR_I64, WebAssembly::XOR_I64_S }, { WebAssembly::anonymous_8166MEMORY_GROW_A32, WebAssembly::anonymous_8166MEMORY_GROW_A32_S }, { WebAssembly::anonymous_8166MEMORY_SIZE_A32, WebAssembly::anonymous_8166MEMORY_SIZE_A32_S }, { WebAssembly::anonymous_8167MEMORY_GROW_A64, WebAssembly::anonymous_8167MEMORY_GROW_A64_S }, { WebAssembly::anonymous_8167MEMORY_SIZE_A64, WebAssembly::anonymous_8167MEMORY_SIZE_A64_S }, { WebAssembly::anonymous_8883DATA_DROP, WebAssembly::anonymous_8883DATA_DROP_S }, { WebAssembly::anonymous_8883MEMORY_COPY_A32, WebAssembly::anonymous_8883MEMORY_COPY_A32_S }, { WebAssembly::anonymous_8883MEMORY_FILL_A32, WebAssembly::anonymous_8883MEMORY_FILL_A32_S }, { WebAssembly::anonymous_8883MEMORY_INIT_A32, WebAssembly::anonymous_8883MEMORY_INIT_A32_S }, { WebAssembly::anonymous_8884DATA_DROP, WebAssembly::anonymous_8884DATA_DROP_S }, { WebAssembly::anonymous_8884MEMORY_COPY_A64, WebAssembly::anonymous_8884MEMORY_COPY_A64_S }, { WebAssembly::anonymous_8884MEMORY_FILL_A64, WebAssembly::anonymous_8884MEMORY_FILL_A64_S }, { WebAssembly::anonymous_8884MEMORY_INIT_A64, WebAssembly::anonymous_8884MEMORY_INIT_A64_S }, { WebAssembly::convert_low_s_F64x2, WebAssembly::convert_low_s_F64x2_S }, { WebAssembly::convert_low_u_F64x2, WebAssembly::convert_low_u_F64x2_S }, { WebAssembly::demote_zero_F32x4, WebAssembly::demote_zero_F32x4_S }, { WebAssembly::extend_high_s_I16x8, WebAssembly::extend_high_s_I16x8_S }, { WebAssembly::extend_high_s_I32x4, WebAssembly::extend_high_s_I32x4_S }, { WebAssembly::extend_high_s_I64x2, WebAssembly::extend_high_s_I64x2_S }, { WebAssembly::extend_high_u_I16x8, WebAssembly::extend_high_u_I16x8_S }, { WebAssembly::extend_high_u_I32x4, WebAssembly::extend_high_u_I32x4_S }, { WebAssembly::extend_high_u_I64x2, WebAssembly::extend_high_u_I64x2_S }, { WebAssembly::extend_low_s_I16x8, WebAssembly::extend_low_s_I16x8_S }, { WebAssembly::extend_low_s_I32x4, WebAssembly::extend_low_s_I32x4_S }, { WebAssembly::extend_low_s_I64x2, WebAssembly::extend_low_s_I64x2_S }, { WebAssembly::extend_low_u_I16x8, WebAssembly::extend_low_u_I16x8_S }, { WebAssembly::extend_low_u_I32x4, WebAssembly::extend_low_u_I32x4_S }, { WebAssembly::extend_low_u_I64x2, WebAssembly::extend_low_u_I64x2_S }, { WebAssembly::fp_to_sint_I16x8, WebAssembly::fp_to_sint_I16x8_S }, { WebAssembly::fp_to_sint_I32x4, WebAssembly::fp_to_sint_I32x4_S }, { WebAssembly::fp_to_uint_I16x8, WebAssembly::fp_to_uint_I16x8_S }, { WebAssembly::fp_to_uint_I32x4, WebAssembly::fp_to_uint_I32x4_S }, { WebAssembly::int_wasm_extadd_pairwise_signed_I16x8, WebAssembly::int_wasm_extadd_pairwise_signed_I16x8_S }, { WebAssembly::int_wasm_extadd_pairwise_signed_I32x4, WebAssembly::int_wasm_extadd_pairwise_signed_I32x4_S }, { WebAssembly::int_wasm_extadd_pairwise_unsigned_I16x8, WebAssembly::int_wasm_extadd_pairwise_unsigned_I16x8_S }, { WebAssembly::int_wasm_extadd_pairwise_unsigned_I32x4, WebAssembly::int_wasm_extadd_pairwise_unsigned_I32x4_S }, { WebAssembly::int_wasm_relaxed_trunc_signed_I32x4, WebAssembly::int_wasm_relaxed_trunc_signed_I32x4_S }, { WebAssembly::int_wasm_relaxed_trunc_signed_zero_I32x4, WebAssembly::int_wasm_relaxed_trunc_signed_zero_I32x4_S }, { WebAssembly::int_wasm_relaxed_trunc_unsigned_I32x4, WebAssembly::int_wasm_relaxed_trunc_unsigned_I32x4_S }, { WebAssembly::int_wasm_relaxed_trunc_unsigned_zero_I32x4, WebAssembly::int_wasm_relaxed_trunc_unsigned_zero_I32x4_S }, { WebAssembly::promote_low_F64x2, WebAssembly::promote_low_F64x2_S }, { WebAssembly::sint_to_fp_F16x8, WebAssembly::sint_to_fp_F16x8_S }, { WebAssembly::sint_to_fp_F32x4, WebAssembly::sint_to_fp_F32x4_S }, { WebAssembly::trunc_sat_zero_s_I32x4, WebAssembly::trunc_sat_zero_s_I32x4_S }, { WebAssembly::trunc_sat_zero_u_I32x4, WebAssembly::trunc_sat_zero_u_I32x4_S }, { WebAssembly::uint_to_fp_F16x8, WebAssembly::uint_to_fp_F16x8_S }, { WebAssembly::uint_to_fp_F32x4, WebAssembly::uint_to_fp_F32x4_S }, }; // End of getStackOpcodeTable unsigned mid; unsigned start = 0; unsigned end = 801; while (start < end) { mid = start + (end - start) / 2; if (Opcode == getStackOpcodeTable[mid][0]) { break; } if (Opcode < getStackOpcodeTable[mid][0]) end = mid; else start = mid + 1; } if (start == end) return -1; // Instruction doesn't exist in this table. return getStackOpcodeTable[mid][1]; } // getWasm64Opcode LLVM_READONLY int getWasm64Opcode(uint16_t Opcode) { static const uint16_t getWasm64OpcodeTable[][2] = { { WebAssembly::ATOMIC_LOAD16_U_I32_A32, WebAssembly::ATOMIC_LOAD16_U_I32_A64 }, { WebAssembly::ATOMIC_LOAD16_U_I32_A32_S, WebAssembly::ATOMIC_LOAD16_U_I32_A64_S }, { WebAssembly::ATOMIC_LOAD16_U_I64_A32, WebAssembly::ATOMIC_LOAD16_U_I64_A64 }, { WebAssembly::ATOMIC_LOAD16_U_I64_A32_S, WebAssembly::ATOMIC_LOAD16_U_I64_A64_S }, { WebAssembly::ATOMIC_LOAD32_U_I64_A32, WebAssembly::ATOMIC_LOAD32_U_I64_A64 }, { WebAssembly::ATOMIC_LOAD32_U_I64_A32_S, WebAssembly::ATOMIC_LOAD32_U_I64_A64_S }, { WebAssembly::ATOMIC_LOAD8_U_I32_A32, WebAssembly::ATOMIC_LOAD8_U_I32_A64 }, { WebAssembly::ATOMIC_LOAD8_U_I32_A32_S, WebAssembly::ATOMIC_LOAD8_U_I32_A64_S }, { WebAssembly::ATOMIC_LOAD8_U_I64_A32, WebAssembly::ATOMIC_LOAD8_U_I64_A64 }, { WebAssembly::ATOMIC_LOAD8_U_I64_A32_S, WebAssembly::ATOMIC_LOAD8_U_I64_A64_S }, { WebAssembly::ATOMIC_LOAD_I32_A32, WebAssembly::ATOMIC_LOAD_I32_A64 }, { WebAssembly::ATOMIC_LOAD_I32_A32_S, WebAssembly::ATOMIC_LOAD_I32_A64_S }, { WebAssembly::ATOMIC_LOAD_I64_A32, WebAssembly::ATOMIC_LOAD_I64_A64 }, { WebAssembly::ATOMIC_LOAD_I64_A32_S, WebAssembly::ATOMIC_LOAD_I64_A64_S }, { WebAssembly::ATOMIC_RMW16_U_ADD_I32_A32, WebAssembly::ATOMIC_RMW16_U_ADD_I32_A64 }, { WebAssembly::ATOMIC_RMW16_U_ADD_I32_A32_S, WebAssembly::ATOMIC_RMW16_U_ADD_I32_A64_S }, { WebAssembly::ATOMIC_RMW16_U_ADD_I64_A32, WebAssembly::ATOMIC_RMW16_U_ADD_I64_A64 }, { WebAssembly::ATOMIC_RMW16_U_ADD_I64_A32_S, WebAssembly::ATOMIC_RMW16_U_ADD_I64_A64_S }, { WebAssembly::ATOMIC_RMW16_U_AND_I32_A32, WebAssembly::ATOMIC_RMW16_U_AND_I32_A64 }, { WebAssembly::ATOMIC_RMW16_U_AND_I32_A32_S, WebAssembly::ATOMIC_RMW16_U_AND_I32_A64_S }, { WebAssembly::ATOMIC_RMW16_U_AND_I64_A32, WebAssembly::ATOMIC_RMW16_U_AND_I64_A64 }, { WebAssembly::ATOMIC_RMW16_U_AND_I64_A32_S, WebAssembly::ATOMIC_RMW16_U_AND_I64_A64_S }, { WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I32_A32, WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I32_A64 }, { WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I32_A32_S, WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I32_A64_S }, { WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I64_A32, WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I64_A64 }, { WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I64_A32_S, WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I64_A64_S }, { WebAssembly::ATOMIC_RMW16_U_OR_I32_A32, WebAssembly::ATOMIC_RMW16_U_OR_I32_A64 }, { WebAssembly::ATOMIC_RMW16_U_OR_I32_A32_S, WebAssembly::ATOMIC_RMW16_U_OR_I32_A64_S }, { WebAssembly::ATOMIC_RMW16_U_OR_I64_A32, WebAssembly::ATOMIC_RMW16_U_OR_I64_A64 }, { WebAssembly::ATOMIC_RMW16_U_OR_I64_A32_S, WebAssembly::ATOMIC_RMW16_U_OR_I64_A64_S }, { WebAssembly::ATOMIC_RMW16_U_SUB_I32_A32, WebAssembly::ATOMIC_RMW16_U_SUB_I32_A64 }, { WebAssembly::ATOMIC_RMW16_U_SUB_I32_A32_S, WebAssembly::ATOMIC_RMW16_U_SUB_I32_A64_S }, { WebAssembly::ATOMIC_RMW16_U_SUB_I64_A32, WebAssembly::ATOMIC_RMW16_U_SUB_I64_A64 }, { WebAssembly::ATOMIC_RMW16_U_SUB_I64_A32_S, WebAssembly::ATOMIC_RMW16_U_SUB_I64_A64_S }, { WebAssembly::ATOMIC_RMW16_U_XCHG_I32_A32, WebAssembly::ATOMIC_RMW16_U_XCHG_I32_A64 }, { WebAssembly::ATOMIC_RMW16_U_XCHG_I32_A32_S, WebAssembly::ATOMIC_RMW16_U_XCHG_I32_A64_S }, { WebAssembly::ATOMIC_RMW16_U_XCHG_I64_A32, WebAssembly::ATOMIC_RMW16_U_XCHG_I64_A64 }, { WebAssembly::ATOMIC_RMW16_U_XCHG_I64_A32_S, WebAssembly::ATOMIC_RMW16_U_XCHG_I64_A64_S }, { WebAssembly::ATOMIC_RMW16_U_XOR_I32_A32, WebAssembly::ATOMIC_RMW16_U_XOR_I32_A64 }, { WebAssembly::ATOMIC_RMW16_U_XOR_I32_A32_S, WebAssembly::ATOMIC_RMW16_U_XOR_I32_A64_S }, { WebAssembly::ATOMIC_RMW16_U_XOR_I64_A32, WebAssembly::ATOMIC_RMW16_U_XOR_I64_A64 }, { WebAssembly::ATOMIC_RMW16_U_XOR_I64_A32_S, WebAssembly::ATOMIC_RMW16_U_XOR_I64_A64_S }, { WebAssembly::ATOMIC_RMW32_U_ADD_I64_A32, WebAssembly::ATOMIC_RMW32_U_ADD_I64_A64 }, { WebAssembly::ATOMIC_RMW32_U_ADD_I64_A32_S, WebAssembly::ATOMIC_RMW32_U_ADD_I64_A64_S }, { WebAssembly::ATOMIC_RMW32_U_AND_I64_A32, WebAssembly::ATOMIC_RMW32_U_AND_I64_A64 }, { WebAssembly::ATOMIC_RMW32_U_AND_I64_A32_S, WebAssembly::ATOMIC_RMW32_U_AND_I64_A64_S }, { WebAssembly::ATOMIC_RMW32_U_CMPXCHG_I64_A32, WebAssembly::ATOMIC_RMW32_U_CMPXCHG_I64_A64 }, { WebAssembly::ATOMIC_RMW32_U_CMPXCHG_I64_A32_S, WebAssembly::ATOMIC_RMW32_U_CMPXCHG_I64_A64_S }, { WebAssembly::ATOMIC_RMW32_U_OR_I64_A32, WebAssembly::ATOMIC_RMW32_U_OR_I64_A64 }, { WebAssembly::ATOMIC_RMW32_U_OR_I64_A32_S, WebAssembly::ATOMIC_RMW32_U_OR_I64_A64_S }, { WebAssembly::ATOMIC_RMW32_U_SUB_I64_A32, WebAssembly::ATOMIC_RMW32_U_SUB_I64_A64 }, { WebAssembly::ATOMIC_RMW32_U_SUB_I64_A32_S, WebAssembly::ATOMIC_RMW32_U_SUB_I64_A64_S }, { WebAssembly::ATOMIC_RMW32_U_XCHG_I64_A32, WebAssembly::ATOMIC_RMW32_U_XCHG_I64_A64 }, { WebAssembly::ATOMIC_RMW32_U_XCHG_I64_A32_S, WebAssembly::ATOMIC_RMW32_U_XCHG_I64_A64_S }, { WebAssembly::ATOMIC_RMW32_U_XOR_I64_A32, WebAssembly::ATOMIC_RMW32_U_XOR_I64_A64 }, { WebAssembly::ATOMIC_RMW32_U_XOR_I64_A32_S, WebAssembly::ATOMIC_RMW32_U_XOR_I64_A64_S }, { WebAssembly::ATOMIC_RMW8_U_ADD_I32_A32, WebAssembly::ATOMIC_RMW8_U_ADD_I32_A64 }, { WebAssembly::ATOMIC_RMW8_U_ADD_I32_A32_S, WebAssembly::ATOMIC_RMW8_U_ADD_I32_A64_S }, { WebAssembly::ATOMIC_RMW8_U_ADD_I64_A32, WebAssembly::ATOMIC_RMW8_U_ADD_I64_A64 }, { WebAssembly::ATOMIC_RMW8_U_ADD_I64_A32_S, WebAssembly::ATOMIC_RMW8_U_ADD_I64_A64_S }, { WebAssembly::ATOMIC_RMW8_U_AND_I32_A32, WebAssembly::ATOMIC_RMW8_U_AND_I32_A64 }, { WebAssembly::ATOMIC_RMW8_U_AND_I32_A32_S, WebAssembly::ATOMIC_RMW8_U_AND_I32_A64_S }, { WebAssembly::ATOMIC_RMW8_U_AND_I64_A32, WebAssembly::ATOMIC_RMW8_U_AND_I64_A64 }, { WebAssembly::ATOMIC_RMW8_U_AND_I64_A32_S, WebAssembly::ATOMIC_RMW8_U_AND_I64_A64_S }, { WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I32_A32, WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I32_A64 }, { WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I32_A32_S, WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I32_A64_S }, { WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I64_A32, WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I64_A64 }, { WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I64_A32_S, WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I64_A64_S }, { WebAssembly::ATOMIC_RMW8_U_OR_I32_A32, WebAssembly::ATOMIC_RMW8_U_OR_I32_A64 }, { WebAssembly::ATOMIC_RMW8_U_OR_I32_A32_S, WebAssembly::ATOMIC_RMW8_U_OR_I32_A64_S }, { WebAssembly::ATOMIC_RMW8_U_OR_I64_A32, WebAssembly::ATOMIC_RMW8_U_OR_I64_A64 }, { WebAssembly::ATOMIC_RMW8_U_OR_I64_A32_S, WebAssembly::ATOMIC_RMW8_U_OR_I64_A64_S }, { WebAssembly::ATOMIC_RMW8_U_SUB_I32_A32, WebAssembly::ATOMIC_RMW8_U_SUB_I32_A64 }, { WebAssembly::ATOMIC_RMW8_U_SUB_I32_A32_S, WebAssembly::ATOMIC_RMW8_U_SUB_I32_A64_S }, { WebAssembly::ATOMIC_RMW8_U_SUB_I64_A32, WebAssembly::ATOMIC_RMW8_U_SUB_I64_A64 }, { WebAssembly::ATOMIC_RMW8_U_SUB_I64_A32_S, WebAssembly::ATOMIC_RMW8_U_SUB_I64_A64_S }, { WebAssembly::ATOMIC_RMW8_U_XCHG_I32_A32, WebAssembly::ATOMIC_RMW8_U_XCHG_I32_A64 }, { WebAssembly::ATOMIC_RMW8_U_XCHG_I32_A32_S, WebAssembly::ATOMIC_RMW8_U_XCHG_I32_A64_S }, { WebAssembly::ATOMIC_RMW8_U_XCHG_I64_A32, WebAssembly::ATOMIC_RMW8_U_XCHG_I64_A64 }, { WebAssembly::ATOMIC_RMW8_U_XCHG_I64_A32_S, WebAssembly::ATOMIC_RMW8_U_XCHG_I64_A64_S }, { WebAssembly::ATOMIC_RMW8_U_XOR_I32_A32, WebAssembly::ATOMIC_RMW8_U_XOR_I32_A64 }, { WebAssembly::ATOMIC_RMW8_U_XOR_I32_A32_S, WebAssembly::ATOMIC_RMW8_U_XOR_I32_A64_S }, { WebAssembly::ATOMIC_RMW8_U_XOR_I64_A32, WebAssembly::ATOMIC_RMW8_U_XOR_I64_A64 }, { WebAssembly::ATOMIC_RMW8_U_XOR_I64_A32_S, WebAssembly::ATOMIC_RMW8_U_XOR_I64_A64_S }, { WebAssembly::ATOMIC_RMW_ADD_I32_A32, WebAssembly::ATOMIC_RMW_ADD_I32_A64 }, { WebAssembly::ATOMIC_RMW_ADD_I32_A32_S, WebAssembly::ATOMIC_RMW_ADD_I32_A64_S }, { WebAssembly::ATOMIC_RMW_ADD_I64_A32, WebAssembly::ATOMIC_RMW_ADD_I64_A64 }, { WebAssembly::ATOMIC_RMW_ADD_I64_A32_S, WebAssembly::ATOMIC_RMW_ADD_I64_A64_S }, { WebAssembly::ATOMIC_RMW_AND_I32_A32, WebAssembly::ATOMIC_RMW_AND_I32_A64 }, { WebAssembly::ATOMIC_RMW_AND_I32_A32_S, WebAssembly::ATOMIC_RMW_AND_I32_A64_S }, { WebAssembly::ATOMIC_RMW_AND_I64_A32, WebAssembly::ATOMIC_RMW_AND_I64_A64 }, { WebAssembly::ATOMIC_RMW_AND_I64_A32_S, WebAssembly::ATOMIC_RMW_AND_I64_A64_S }, { WebAssembly::ATOMIC_RMW_CMPXCHG_I32_A32, WebAssembly::ATOMIC_RMW_CMPXCHG_I32_A64 }, { WebAssembly::ATOMIC_RMW_CMPXCHG_I32_A32_S, WebAssembly::ATOMIC_RMW_CMPXCHG_I32_A64_S }, { WebAssembly::ATOMIC_RMW_CMPXCHG_I64_A32, WebAssembly::ATOMIC_RMW_CMPXCHG_I64_A64 }, { WebAssembly::ATOMIC_RMW_CMPXCHG_I64_A32_S, WebAssembly::ATOMIC_RMW_CMPXCHG_I64_A64_S }, { WebAssembly::ATOMIC_RMW_OR_I32_A32, WebAssembly::ATOMIC_RMW_OR_I32_A64 }, { WebAssembly::ATOMIC_RMW_OR_I32_A32_S, WebAssembly::ATOMIC_RMW_OR_I32_A64_S }, { WebAssembly::ATOMIC_RMW_OR_I64_A32, WebAssembly::ATOMIC_RMW_OR_I64_A64 }, { WebAssembly::ATOMIC_RMW_OR_I64_A32_S, WebAssembly::ATOMIC_RMW_OR_I64_A64_S }, { WebAssembly::ATOMIC_RMW_SUB_I32_A32, WebAssembly::ATOMIC_RMW_SUB_I32_A64 }, { WebAssembly::ATOMIC_RMW_SUB_I32_A32_S, WebAssembly::ATOMIC_RMW_SUB_I32_A64_S }, { WebAssembly::ATOMIC_RMW_SUB_I64_A32, WebAssembly::ATOMIC_RMW_SUB_I64_A64 }, { WebAssembly::ATOMIC_RMW_SUB_I64_A32_S, WebAssembly::ATOMIC_RMW_SUB_I64_A64_S }, { WebAssembly::ATOMIC_RMW_XCHG_I32_A32, WebAssembly::ATOMIC_RMW_XCHG_I32_A64 }, { WebAssembly::ATOMIC_RMW_XCHG_I32_A32_S, WebAssembly::ATOMIC_RMW_XCHG_I32_A64_S }, { WebAssembly::ATOMIC_RMW_XCHG_I64_A32, WebAssembly::ATOMIC_RMW_XCHG_I64_A64 }, { WebAssembly::ATOMIC_RMW_XCHG_I64_A32_S, WebAssembly::ATOMIC_RMW_XCHG_I64_A64_S }, { WebAssembly::ATOMIC_RMW_XOR_I32_A32, WebAssembly::ATOMIC_RMW_XOR_I32_A64 }, { WebAssembly::ATOMIC_RMW_XOR_I32_A32_S, WebAssembly::ATOMIC_RMW_XOR_I32_A64_S }, { WebAssembly::ATOMIC_RMW_XOR_I64_A32, WebAssembly::ATOMIC_RMW_XOR_I64_A64 }, { WebAssembly::ATOMIC_RMW_XOR_I64_A32_S, WebAssembly::ATOMIC_RMW_XOR_I64_A64_S }, { WebAssembly::ATOMIC_STORE16_I32_A32, WebAssembly::ATOMIC_STORE16_I32_A64 }, { WebAssembly::ATOMIC_STORE16_I32_A32_S, WebAssembly::ATOMIC_STORE16_I32_A64_S }, { WebAssembly::ATOMIC_STORE16_I64_A32, WebAssembly::ATOMIC_STORE16_I64_A64 }, { WebAssembly::ATOMIC_STORE16_I64_A32_S, WebAssembly::ATOMIC_STORE16_I64_A64_S }, { WebAssembly::ATOMIC_STORE32_I64_A32, WebAssembly::ATOMIC_STORE32_I64_A64 }, { WebAssembly::ATOMIC_STORE32_I64_A32_S, WebAssembly::ATOMIC_STORE32_I64_A64_S }, { WebAssembly::ATOMIC_STORE8_I32_A32, WebAssembly::ATOMIC_STORE8_I32_A64 }, { WebAssembly::ATOMIC_STORE8_I32_A32_S, WebAssembly::ATOMIC_STORE8_I32_A64_S }, { WebAssembly::ATOMIC_STORE8_I64_A32, WebAssembly::ATOMIC_STORE8_I64_A64 }, { WebAssembly::ATOMIC_STORE8_I64_A32_S, WebAssembly::ATOMIC_STORE8_I64_A64_S }, { WebAssembly::ATOMIC_STORE_I32_A32, WebAssembly::ATOMIC_STORE_I32_A64 }, { WebAssembly::ATOMIC_STORE_I32_A32_S, WebAssembly::ATOMIC_STORE_I32_A64_S }, { WebAssembly::ATOMIC_STORE_I64_A32, WebAssembly::ATOMIC_STORE_I64_A64 }, { WebAssembly::ATOMIC_STORE_I64_A32_S, WebAssembly::ATOMIC_STORE_I64_A64_S }, { WebAssembly::LOAD16_S_I32_A32, WebAssembly::LOAD16_S_I32_A64 }, { WebAssembly::LOAD16_S_I32_A32_S, WebAssembly::LOAD16_S_I32_A64_S }, { WebAssembly::LOAD16_S_I64_A32, WebAssembly::LOAD16_S_I64_A64 }, { WebAssembly::LOAD16_S_I64_A32_S, WebAssembly::LOAD16_S_I64_A64_S }, { WebAssembly::LOAD16_U_I32_A32, WebAssembly::LOAD16_U_I32_A64 }, { WebAssembly::LOAD16_U_I32_A32_S, WebAssembly::LOAD16_U_I32_A64_S }, { WebAssembly::LOAD16_U_I64_A32, WebAssembly::LOAD16_U_I64_A64 }, { WebAssembly::LOAD16_U_I64_A32_S, WebAssembly::LOAD16_U_I64_A64_S }, { WebAssembly::LOAD32_S_I64_A32, WebAssembly::LOAD32_S_I64_A64 }, { WebAssembly::LOAD32_S_I64_A32_S, WebAssembly::LOAD32_S_I64_A64_S }, { WebAssembly::LOAD32_U_I64_A32, WebAssembly::LOAD32_U_I64_A64 }, { WebAssembly::LOAD32_U_I64_A32_S, WebAssembly::LOAD32_U_I64_A64_S }, { WebAssembly::LOAD8_S_I32_A32, WebAssembly::LOAD8_S_I32_A64 }, { WebAssembly::LOAD8_S_I32_A32_S, WebAssembly::LOAD8_S_I32_A64_S }, { WebAssembly::LOAD8_S_I64_A32, WebAssembly::LOAD8_S_I64_A64 }, { WebAssembly::LOAD8_S_I64_A32_S, WebAssembly::LOAD8_S_I64_A64_S }, { WebAssembly::LOAD8_U_I32_A32, WebAssembly::LOAD8_U_I32_A64 }, { WebAssembly::LOAD8_U_I32_A32_S, WebAssembly::LOAD8_U_I32_A64_S }, { WebAssembly::LOAD8_U_I64_A32, WebAssembly::LOAD8_U_I64_A64 }, { WebAssembly::LOAD8_U_I64_A32_S, WebAssembly::LOAD8_U_I64_A64_S }, { WebAssembly::LOAD_F16_F32_A32, WebAssembly::LOAD_F16_F32_A64 }, { WebAssembly::LOAD_F16_F32_A32_S, WebAssembly::LOAD_F16_F32_A64_S }, { WebAssembly::LOAD_F32_A32, WebAssembly::LOAD_F32_A64 }, { WebAssembly::LOAD_F32_A32_S, WebAssembly::LOAD_F32_A64_S }, { WebAssembly::LOAD_F64_A32, WebAssembly::LOAD_F64_A64 }, { WebAssembly::LOAD_F64_A32_S, WebAssembly::LOAD_F64_A64_S }, { WebAssembly::LOAD_I32_A32, WebAssembly::LOAD_I32_A64 }, { WebAssembly::LOAD_I32_A32_S, WebAssembly::LOAD_I32_A64_S }, { WebAssembly::LOAD_I64_A32, WebAssembly::LOAD_I64_A64 }, { WebAssembly::LOAD_I64_A32_S, WebAssembly::LOAD_I64_A64_S }, { WebAssembly::MEMORY_ATOMIC_NOTIFY_A32, WebAssembly::MEMORY_ATOMIC_NOTIFY_A64 }, { WebAssembly::MEMORY_ATOMIC_NOTIFY_A32_S, WebAssembly::MEMORY_ATOMIC_NOTIFY_A64_S }, { WebAssembly::MEMORY_ATOMIC_WAIT32_A32, WebAssembly::MEMORY_ATOMIC_WAIT32_A64 }, { WebAssembly::MEMORY_ATOMIC_WAIT32_A32_S, WebAssembly::MEMORY_ATOMIC_WAIT32_A64_S }, { WebAssembly::MEMORY_ATOMIC_WAIT64_A32, WebAssembly::MEMORY_ATOMIC_WAIT64_A64 }, { WebAssembly::MEMORY_ATOMIC_WAIT64_A32_S, WebAssembly::MEMORY_ATOMIC_WAIT64_A64_S }, { WebAssembly::STORE16_I32_A32, WebAssembly::STORE16_I32_A64 }, { WebAssembly::STORE16_I32_A32_S, WebAssembly::STORE16_I32_A64_S }, { WebAssembly::STORE16_I64_A32, WebAssembly::STORE16_I64_A64 }, { WebAssembly::STORE16_I64_A32_S, WebAssembly::STORE16_I64_A64_S }, { WebAssembly::STORE32_I64_A32, WebAssembly::STORE32_I64_A64 }, { WebAssembly::STORE32_I64_A32_S, WebAssembly::STORE32_I64_A64_S }, { WebAssembly::STORE8_I32_A32, WebAssembly::STORE8_I32_A64 }, { WebAssembly::STORE8_I32_A32_S, WebAssembly::STORE8_I32_A64_S }, { WebAssembly::STORE8_I64_A32, WebAssembly::STORE8_I64_A64 }, { WebAssembly::STORE8_I64_A32_S, WebAssembly::STORE8_I64_A64_S }, { WebAssembly::STORE_F16_F32_A32, WebAssembly::STORE_F16_F32_A64 }, { WebAssembly::STORE_F16_F32_A32_S, WebAssembly::STORE_F16_F32_A64_S }, { WebAssembly::STORE_F32_A32, WebAssembly::STORE_F32_A64 }, { WebAssembly::STORE_F32_A32_S, WebAssembly::STORE_F32_A64_S }, { WebAssembly::STORE_F64_A32, WebAssembly::STORE_F64_A64 }, { WebAssembly::STORE_F64_A32_S, WebAssembly::STORE_F64_A64_S }, { WebAssembly::STORE_I32_A32, WebAssembly::STORE_I32_A64 }, { WebAssembly::STORE_I32_A32_S, WebAssembly::STORE_I32_A64_S }, { WebAssembly::STORE_I64_A32, WebAssembly::STORE_I64_A64 }, { WebAssembly::STORE_I64_A32_S, WebAssembly::STORE_I64_A64_S }, }; // End of getWasm64OpcodeTable unsigned mid; unsigned start = 0; unsigned end = 182; while (start < end) { mid = start + (end - start) / 2; if (Opcode == getWasm64OpcodeTable[mid][0]) { break; } if (Opcode < getWasm64OpcodeTable[mid][0]) end = mid; else start = mid + 1; } if (start == end) return -1; // Instruction doesn't exist in this table. return getWasm64OpcodeTable[mid][1]; } } // end namespace WebAssembly } // end namespace llvm #endif // GET_INSTRMAP_INFO
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