llvm/lib/Target/XCore/XCoreGenInstrInfo.inc

/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
|*                                                                            *|
|* Target Instruction Enum Values and Descriptors                             *|
|*                                                                            *|
|* Automatically generated file, do not edit!                                 *|
|*                                                                            *|
\*===----------------------------------------------------------------------===*/

#ifdef GET_INSTRINFO_ENUM
#undef GET_INSTRINFO_ENUM
namespace llvm {

namespace XCore {
  enum { … };

} // end namespace XCore
} // end namespace llvm
#endif // GET_INSTRINFO_ENUM

#ifdef GET_INSTRINFO_SCHED_ENUM
#undef GET_INSTRINFO_SCHED_ENUM
namespace llvm {

namespace XCore {
namespace Sched {
  enum {
    NoInstrModel	= 0,
    SCHED_LIST_END = 1
  };
} // end namespace Sched
} // end namespace XCore
} // end namespace llvm
#endif // GET_INSTRINFO_SCHED_ENUM

#if defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
namespace llvm {

struct XCoreInstrTable {
  MCInstrDesc Insts[520];
  static_assert(alignof(MCInstrDesc) >= alignof(MCOperandInfo), "Unwanted padding between Insts and OperandInfo");
  MCOperandInfo OperandInfo[213];
  static_assert(alignof(MCOperandInfo) >= alignof(MCPhysReg), "Unwanted padding between OperandInfo and ImplicitOps");
  MCPhysReg ImplicitOps[11];
};

} // end namespace llvm
#endif // defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)

#ifdef GET_INSTRINFO_MC_DESC
#undef GET_INSTRINFO_MC_DESC
namespace llvm {

static_assert(sizeof(MCOperandInfo) % sizeof(MCPhysReg) == 0);
static constexpr unsigned XCoreImpOpBase = sizeof XCoreInstrTable::OperandInfo / (sizeof(MCPhysReg));

extern const XCoreInstrTable XCoreDescs = {
  {
    { 519,	3,	1,	2,	0,	0,	0,	XCoreImpOpBase + 0,	205,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #519 = ZEXT_rus
    { 518,	3,	1,	2,	0,	0,	0,	XCoreImpOpBase + 0,	170,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #518 = ZEXT_2r
    { 517,	3,	1,	4,	0,	0,	0,	XCoreImpOpBase + 0,	167,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #517 = XOR_l3r
    { 516,	0,	0,	2,	0,	0,	0,	XCoreImpOpBase + 0,	1,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #516 = WAITEU_0R
    { 515,	1,	0,	2,	0,	0,	0,	XCoreImpOpBase + 0,	156,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #515 = WAITET_1R
    { 514,	1,	0,	2,	0,	0,	0,	XCoreImpOpBase + 0,	156,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #514 = WAITEF_1R
    { 513,	1,	0,	2,	0,	0,	0,	XCoreImpOpBase + 0,	156,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #513 = TSTART_1R
    { 512,	3,	0,	2,	0,	0,	0,	XCoreImpOpBase + 0,	210,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #512 = TSETR_3r
    { 511,	2,	0,	2,	0,	0,	0,	XCoreImpOpBase + 0,	208,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #511 = TSETMR_2r
    { 510,	2,	1,	2,	0,	0,	0,	XCoreImpOpBase + 0,	154,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #510 = TESTWCT_2r
    { 509,	2,	1,	4,	0,	0,	0,	XCoreImpOpBase + 0,	154,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #509 = TESTLCL_l2r
    { 508,	2,	1,	2,	0,	0,	0,	XCoreImpOpBase + 0,	154,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #508 = TESTCT_2r
    { 507,	1,	0,	2,	0,	0,	0,	XCoreImpOpBase + 0,	156,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #507 = SYNCR_1r
    { 506,	3,	1,	2,	0,	0,	0,	XCoreImpOpBase + 0,	167,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #506 = SUB_3r
    { 505,	3,	1,	2,	0,	0,	0,	XCoreImpOpBase + 0,	164,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #505 = SUB_2rus
    { 504,	3,	0,	4,	0,	0,	0,	XCoreImpOpBase + 0,	167,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #504 = STW_l3r
    { 503,	3,	0,	2,	0,	0,	0,	XCoreImpOpBase + 0,	164,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #503 = STW_2rus
    { 502,	2,	0,	2,	0,	1,	0,	XCoreImpOpBase + 10,	191,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #502 = STWSP_ru6
    { 501,	2,	0,	4,	0,	1,	0,	XCoreImpOpBase + 10,	191,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #501 = STWSP_lru6
    { 500,	2,	0,	2,	0,	0,	0,	XCoreImpOpBase + 0,	191,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #500 = STWDP_ru6
    { 499,	2,	0,	4,	0,	0,	0,	XCoreImpOpBase + 0,	191,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #499 = STWDP_lru6
    { 498,	0,	0,	2,	0,	1,	0,	XCoreImpOpBase + 10,	1,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #498 = STSSR_0R
    { 497,	0,	0,	2,	0,	1,	0,	XCoreImpOpBase + 10,	1,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #497 = STSPC_0R
    { 496,	0,	0,	2,	0,	1,	0,	XCoreImpOpBase + 10,	1,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #496 = STSED_0R
    { 495,	0,	0,	2,	0,	1,	0,	XCoreImpOpBase + 10,	1,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #495 = STET_0R
    { 494,	3,	0,	4,	0,	0,	0,	XCoreImpOpBase + 0,	167,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #494 = ST8_l3r
    { 493,	3,	0,	4,	0,	0,	0,	XCoreImpOpBase + 0,	167,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #493 = ST16_l3r
    { 492,	0,	0,	2,	0,	0,	0,	XCoreImpOpBase + 0,	1,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #492 = SSYNC_0r
    { 491,	3,	1,	2,	0,	0,	0,	XCoreImpOpBase + 0,	167,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #491 = SHR_3r
    { 490,	3,	1,	2,	0,	0,	0,	XCoreImpOpBase + 0,	164,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #490 = SHR_2rus
    { 489,	3,	1,	2,	0,	0,	0,	XCoreImpOpBase + 0,	167,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #489 = SHL_3r
    { 488,	3,	1,	2,	0,	0,	0,	XCoreImpOpBase + 0,	164,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #488 = SHL_2rus
    { 487,	3,	1,	2,	0,	0,	0,	XCoreImpOpBase + 0,	205,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #487 = SEXT_rus
    { 486,	3,	1,	2,	0,	0,	0,	XCoreImpOpBase + 0,	170,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #486 = SEXT_2r
    { 485,	1,	0,	2,	0,	1,	0,	XCoreImpOpBase + 9,	156,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #485 = SETV_1r
    { 484,	2,	0,	4,	0,	0,	0,	XCoreImpOpBase + 0,	154,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #484 = SETTW_l2r
    { 483,	1,	0,	2,	0,	0,	0,	XCoreImpOpBase + 0,	1,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #483 = SETSR_u6
    { 482,	1,	0,	4,	0,	0,	0,	XCoreImpOpBase + 0,	1,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #482 = SETSR_lu6
    { 481,	1,	0,	2,	0,	0,	0,	XCoreImpOpBase + 0,	1,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #481 = SETSR_branch_u6
    { 480,	1,	0,	4,	0,	0,	0,	XCoreImpOpBase + 0,	1,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #480 = SETSR_branch_lu6
    { 479,	1,	0,	2,	0,	0,	1,	XCoreImpOpBase + 10,	156,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #479 = SETSP_1r
    { 478,	2,	0,	4,	0,	0,	0,	XCoreImpOpBase + 0,	154,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #478 = SETRDY_l2r
    { 477,	2,	0,	2,	0,	0,	0,	XCoreImpOpBase + 0,	154,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #477 = SETPT_2r
    { 476,	2,	0,	4,	0,	0,	0,	XCoreImpOpBase + 0,	154,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #476 = SETPS_l2r
    { 475,	2,	0,	2,	0,	0,	0,	XCoreImpOpBase + 0,	154,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #475 = SETPSC_2r
    { 474,	2,	0,	4,	0,	0,	0,	XCoreImpOpBase + 0,	154,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #474 = SETN_l2r
    { 473,	0,	0,	2,	0,	1,	0,	XCoreImpOpBase + 9,	1,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #473 = SETKEP_0R
    { 472,	1,	0,	2,	0,	1,	0,	XCoreImpOpBase + 9,	156,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #472 = SETEV_1r
    { 471,	2,	0,	2,	0,	0,	0,	XCoreImpOpBase + 0,	154,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #471 = SETD_2r
    { 470,	1,	0,	2,	0,	0,	0,	XCoreImpOpBase + 0,	156,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #470 = SETDP_1r
    { 469,	2,	0,	2,	0,	0,	0,	XCoreImpOpBase + 0,	175,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #469 = SETC_ru6
    { 468,	2,	0,	4,	0,	0,	0,	XCoreImpOpBase + 0,	175,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #468 = SETC_lru6
    { 467,	2,	0,	4,	0,	0,	0,	XCoreImpOpBase + 0,	154,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #467 = SETC_l2r
    { 466,	1,	0,	2,	0,	0,	0,	XCoreImpOpBase + 0,	156,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #466 = SETCP_1r
    { 465,	2,	0,	4,	0,	0,	0,	XCoreImpOpBase + 0,	154,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #465 = SETCLK_l2r
    { 464,	1,	0,	2,	0,	1,	1,	XCoreImpOpBase + 0,	1,	0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #464 = RETSP_u6
    { 463,	1,	0,	4,	0,	1,	1,	XCoreImpOpBase + 0,	1,	0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #463 = RETSP_lu6
    { 462,	3,	1,	4,	0,	0,	0,	XCoreImpOpBase + 0,	167,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #462 = REMU_l3r
    { 461,	3,	1,	4,	0,	0,	0,	XCoreImpOpBase + 0,	167,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #461 = REMS_l3r
    { 460,	2,	1,	2,	0,	0,	0,	XCoreImpOpBase + 0,	154,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #460 = PEEK_2r
    { 459,	2,	0,	2,	0,	0,	0,	XCoreImpOpBase + 0,	154,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #459 = OUT_2r
    { 458,	2,	0,	2,	0,	0,	0,	XCoreImpOpBase + 0,	154,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #458 = OUTT_2r
    { 457,	3,	1,	2,	0,	0,	0,	XCoreImpOpBase + 0,	170,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #457 = OUTSHR_2r
    { 456,	3,	0,	4,	0,	0,	0,	XCoreImpOpBase + 0,	164,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #456 = OUTPW_l2rus
    { 455,	2,	0,	2,	0,	0,	0,	XCoreImpOpBase + 0,	175,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #455 = OUTCT_rus
    { 454,	2,	0,	2,	0,	0,	0,	XCoreImpOpBase + 0,	154,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #454 = OUTCT_2r
    { 453,	3,	1,	2,	0,	0,	0,	XCoreImpOpBase + 0,	167,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #453 = OR_3r
    { 452,	2,	1,	2,	0,	0,	0,	XCoreImpOpBase + 0,	154,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #452 = NOT
    { 451,	2,	1,	2,	0,	0,	0,	XCoreImpOpBase + 0,	154,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #451 = NEG
    { 450,	3,	1,	4,	0,	0,	0,	XCoreImpOpBase + 0,	167,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #450 = MUL_l3r
    { 449,	1,	0,	2,	0,	0,	0,	XCoreImpOpBase + 0,	156,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #449 = MSYNC_1r
    { 448,	2,	1,	2,	0,	0,	0,	XCoreImpOpBase + 0,	175,	0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #448 = MKMSK_rus
    { 447,	2,	1,	2,	0,	0,	0,	XCoreImpOpBase + 0,	154,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #447 = MKMSK_2r
    { 446,	1,	0,	2,	0,	0,	0,	XCoreImpOpBase + 0,	156,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #446 = MJOIN_1r
    { 445,	6,	2,	4,	0,	0,	0,	XCoreImpOpBase + 0,	199,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #445 = MACCU_l4r
    { 444,	6,	2,	4,	0,	0,	0,	XCoreImpOpBase + 0,	199,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #444 = MACCS_l4r
    { 443,	3,	1,	2,	0,	0,	0,	XCoreImpOpBase + 0,	167,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #443 = LSU_3r
    { 442,	5,	2,	4,	0,	0,	0,	XCoreImpOpBase + 0,	186,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #442 = LSUB_l5r
    { 441,	3,	1,	2,	0,	0,	0,	XCoreImpOpBase + 0,	167,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #441 = LSS_3r
    { 440,	6,	2,	4,	0,	0,	0,	XCoreImpOpBase + 0,	193,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #440 = LMUL_l6r
    { 439,	3,	1,	2,	0,	0,	0,	XCoreImpOpBase + 0,	167,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #439 = LDW_3r
    { 438,	3,	1,	2,	0,	0,	0,	XCoreImpOpBase + 0,	164,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #438 = LDW_2rus
    { 437,	2,	1,	2,	0,	1,	0,	XCoreImpOpBase + 10,	191,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #437 = LDWSP_ru6
    { 436,	2,	1,	4,	0,	1,	0,	XCoreImpOpBase + 10,	191,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #436 = LDWSP_lru6
    { 435,	2,	1,	2,	0,	0,	0,	XCoreImpOpBase + 0,	191,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #435 = LDWDP_ru6
    { 434,	2,	1,	4,	0,	0,	0,	XCoreImpOpBase + 0,	191,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #434 = LDWDP_lru6
    { 433,	1,	0,	2,	0,	0,	1,	XCoreImpOpBase + 9,	1,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #433 = LDWCP_u10
    { 432,	2,	1,	2,	0,	0,	0,	XCoreImpOpBase + 0,	191,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #432 = LDWCP_ru6
    { 431,	1,	0,	4,	0,	0,	1,	XCoreImpOpBase + 9,	1,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #431 = LDWCP_lu10
    { 430,	2,	1,	4,	0,	0,	0,	XCoreImpOpBase + 0,	191,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #430 = LDWCP_lru6
    { 429,	0,	0,	2,	0,	1,	0,	XCoreImpOpBase + 10,	1,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #429 = LDSSR_0R
    { 428,	0,	0,	2,	0,	1,	0,	XCoreImpOpBase + 10,	1,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #428 = LDSPC_0R
    { 427,	0,	0,	2,	0,	1,	0,	XCoreImpOpBase + 10,	1,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #427 = LDSED_0R
    { 426,	5,	2,	4,	0,	0,	0,	XCoreImpOpBase + 0,	186,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #426 = LDIVU_l5r
    { 425,	0,	0,	2,	0,	1,	0,	XCoreImpOpBase + 10,	1,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #425 = LDET_0R
    { 424,	2,	1,	2,	0,	0,	0,	XCoreImpOpBase + 0,	191,	0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #424 = LDC_ru6
    { 423,	2,	1,	4,	0,	0,	0,	XCoreImpOpBase + 0,	191,	0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #423 = LDC_lru6
    { 422,	2,	1,	2,	0,	1,	0,	XCoreImpOpBase + 10,	191,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #422 = LDAWSP_ru6
    { 421,	2,	1,	4,	0,	1,	0,	XCoreImpOpBase + 10,	191,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #421 = LDAWSP_lru6
    { 420,	3,	1,	4,	0,	0,	0,	XCoreImpOpBase + 0,	167,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #420 = LDAWF_l3r
    { 419,	3,	1,	4,	0,	0,	0,	XCoreImpOpBase + 0,	164,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #419 = LDAWF_l2rus
    { 418,	2,	1,	2,	0,	0,	0,	XCoreImpOpBase + 0,	191,	0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #418 = LDAWDP_ru6
    { 417,	2,	1,	4,	0,	0,	0,	XCoreImpOpBase + 0,	191,	0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #417 = LDAWDP_lru6
    { 416,	1,	0,	2,	0,	0,	1,	XCoreImpOpBase + 9,	1,	0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #416 = LDAWCP_u6
    { 415,	1,	0,	4,	0,	0,	1,	XCoreImpOpBase + 9,	1,	0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #415 = LDAWCP_lu6
    { 414,	3,	1,	4,	0,	0,	0,	XCoreImpOpBase + 0,	167,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #414 = LDAWB_l3r
    { 413,	3,	1,	4,	0,	0,	0,	XCoreImpOpBase + 0,	164,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #413 = LDAWB_l2rus
    { 412,	1,	0,	2,	0,	0,	1,	XCoreImpOpBase + 9,	0,	0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #412 = LDAPF_u10
    { 411,	1,	0,	4,	0,	0,	1,	XCoreImpOpBase + 9,	0,	0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #411 = LDAPF_lu10_ba
    { 410,	1,	0,	4,	0,	0,	1,	XCoreImpOpBase + 9,	0,	0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #410 = LDAPF_lu10
    { 409,	1,	0,	2,	0,	0,	1,	XCoreImpOpBase + 9,	0,	0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #409 = LDAPB_u10
    { 408,	1,	0,	4,	0,	0,	1,	XCoreImpOpBase + 9,	0,	0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #408 = LDAPB_lu10
    { 407,	3,	1,	4,	0,	0,	0,	XCoreImpOpBase + 0,	167,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #407 = LDA16F_l3r
    { 406,	3,	1,	4,	0,	0,	0,	XCoreImpOpBase + 0,	167,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #406 = LDA16B_l3r
    { 405,	3,	1,	2,	0,	0,	0,	XCoreImpOpBase + 0,	167,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #405 = LD8U_3r
    { 404,	3,	1,	2,	0,	0,	0,	XCoreImpOpBase + 0,	167,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #404 = LD16S_3r
    { 403,	5,	2,	4,	0,	0,	0,	XCoreImpOpBase + 0,	186,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #403 = LADD_l5r
    { 402,	0,	0,	2,	0,	0,	1,	XCoreImpOpBase + 10,	1,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #402 = KRET_0R
    { 401,	1,	0,	2,	0,	1,	1,	XCoreImpOpBase + 0,	1,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #401 = KRESTSP_u6
    { 400,	1,	0,	4,	0,	1,	1,	XCoreImpOpBase + 0,	1,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #400 = KRESTSP_lu6
    { 399,	1,	0,	2,	0,	1,	1,	XCoreImpOpBase + 0,	1,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #399 = KENTSP_u6
    { 398,	1,	0,	4,	0,	1,	1,	XCoreImpOpBase + 0,	1,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #398 = KENTSP_lu6
    { 397,	1,	0,	2,	0,	0,	0,	XCoreImpOpBase + 0,	1,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #397 = KCALL_u6
    { 396,	1,	0,	4,	0,	0,	0,	XCoreImpOpBase + 0,	1,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #396 = KCALL_lu6
    { 395,	1,	0,	2,	0,	0,	0,	XCoreImpOpBase + 0,	156,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #395 = KCALL_1r
    { 394,	2,	1,	2,	0,	0,	0,	XCoreImpOpBase + 0,	154,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #394 = IN_2r
    { 393,	2,	1,	2,	0,	0,	0,	XCoreImpOpBase + 0,	154,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #393 = INT_2r
    { 392,	3,	1,	2,	0,	0,	0,	XCoreImpOpBase + 0,	170,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #392 = INSHR_2r
    { 391,	3,	1,	4,	0,	0,	0,	XCoreImpOpBase + 0,	164,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #391 = INPW_l2rus
    { 390,	2,	0,	2,	0,	0,	0,	XCoreImpOpBase + 0,	154,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #390 = INITSP_2r
    { 389,	2,	0,	2,	0,	0,	0,	XCoreImpOpBase + 0,	154,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #389 = INITPC_2r
    { 388,	2,	0,	4,	0,	0,	0,	XCoreImpOpBase + 0,	154,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #388 = INITLR_l2r
    { 387,	2,	0,	2,	0,	0,	0,	XCoreImpOpBase + 0,	154,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #387 = INITDP_2r
    { 386,	2,	0,	2,	0,	0,	0,	XCoreImpOpBase + 0,	154,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #386 = INITCP_2r
    { 385,	2,	1,	2,	0,	0,	0,	XCoreImpOpBase + 0,	154,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #385 = INCT_2r
    { 384,	2,	1,	2,	0,	0,	0,	XCoreImpOpBase + 0,	154,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #384 = GETTS_2r
    { 383,	2,	1,	2,	0,	0,	0,	XCoreImpOpBase + 0,	154,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #383 = GETST_2r
    { 382,	1,	0,	2,	0,	0,	1,	XCoreImpOpBase + 9,	1,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #382 = GETSR_u6
    { 381,	1,	0,	4,	0,	0,	1,	XCoreImpOpBase + 9,	1,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #381 = GETSR_lu6
    { 380,	2,	1,	2,	0,	0,	0,	XCoreImpOpBase + 0,	175,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #380 = GETR_rus
    { 379,	2,	1,	4,	0,	0,	0,	XCoreImpOpBase + 0,	154,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #379 = GETPS_l2r
    { 378,	2,	1,	4,	0,	0,	0,	XCoreImpOpBase + 0,	154,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #378 = GETN_l2r
    { 377,	0,	0,	2,	0,	0,	1,	XCoreImpOpBase + 9,	1,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #377 = GETKSP_0R
    { 376,	0,	0,	2,	0,	0,	1,	XCoreImpOpBase + 9,	1,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #376 = GETKEP_0R
    { 375,	0,	0,	2,	0,	0,	1,	XCoreImpOpBase + 9,	1,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #375 = GETID_0R
    { 374,	0,	0,	2,	0,	0,	1,	XCoreImpOpBase + 9,	1,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #374 = GETET_0R
    { 373,	0,	0,	2,	0,	0,	1,	XCoreImpOpBase + 9,	1,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #373 = GETED_0R
    { 372,	2,	1,	4,	0,	0,	0,	XCoreImpOpBase + 0,	154,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #372 = GETD_l2r
    { 371,	0,	0,	2,	0,	0,	0,	XCoreImpOpBase + 0,	1,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #371 = FREET_0R
    { 370,	1,	0,	2,	0,	0,	0,	XCoreImpOpBase + 0,	156,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #370 = FREER_1r
    { 369,	1,	0,	2,	0,	1,	1,	XCoreImpOpBase + 0,	1,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #369 = EXTSP_u6
    { 368,	1,	0,	4,	0,	1,	1,	XCoreImpOpBase + 0,	1,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #368 = EXTSP_lu6
    { 367,	1,	0,	2,	0,	0,	0,	XCoreImpOpBase + 0,	1,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #367 = EXTDP_u6
    { 366,	1,	0,	4,	0,	0,	0,	XCoreImpOpBase + 0,	1,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #366 = EXTDP_lu6
    { 365,	3,	1,	2,	0,	0,	0,	XCoreImpOpBase + 0,	167,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #365 = EQ_3r
    { 364,	3,	1,	2,	0,	0,	0,	XCoreImpOpBase + 0,	164,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #364 = EQ_2rus
    { 363,	1,	0,	2,	0,	1,	1,	XCoreImpOpBase + 0,	1,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #363 = ENTSP_u6
    { 362,	1,	0,	4,	0,	1,	1,	XCoreImpOpBase + 0,	1,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #362 = ENTSP_lu6
    { 361,	2,	1,	2,	0,	0,	0,	XCoreImpOpBase + 0,	154,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #361 = ENDIN_2r
    { 360,	1,	0,	2,	0,	0,	0,	XCoreImpOpBase + 0,	156,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #360 = EEU_1r
    { 359,	2,	0,	2,	0,	0,	0,	XCoreImpOpBase + 0,	154,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #359 = EET_2r
    { 358,	2,	0,	2,	0,	0,	0,	XCoreImpOpBase + 0,	154,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #358 = EEF_2r
    { 357,	1,	0,	2,	0,	0,	0,	XCoreImpOpBase + 0,	156,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #357 = EDU_1r
    { 356,	1,	0,	2,	0,	0,	0,	XCoreImpOpBase + 0,	156,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #356 = ECALLT_1r
    { 355,	1,	0,	2,	0,	0,	0,	XCoreImpOpBase + 0,	156,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #355 = ECALLF_1r
    { 354,	0,	0,	2,	0,	0,	0,	XCoreImpOpBase + 0,	1,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #354 = DRET_0R
    { 353,	0,	0,	2,	0,	0,	1,	XCoreImpOpBase + 10,	1,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #353 = DRESTSP_0R
    { 352,	3,	1,	4,	0,	0,	0,	XCoreImpOpBase + 0,	167,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #352 = DIVU_l3r
    { 351,	3,	1,	4,	0,	0,	0,	XCoreImpOpBase + 0,	167,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #351 = DIVS_l3r
    { 350,	1,	1,	2,	0,	0,	0,	XCoreImpOpBase + 0,	156,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #350 = DGETREG_1r
    { 349,	0,	0,	2,	0,	1,	1,	XCoreImpOpBase + 0,	1,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #349 = DENTSP_0R
    { 348,	0,	0,	2,	0,	0,	0,	XCoreImpOpBase + 0,	1,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #348 = DCALL_0R
    { 347,	4,	1,	4,	0,	0,	0,	XCoreImpOpBase + 0,	182,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #347 = CRC_l3r
    { 346,	5,	2,	4,	0,	0,	0,	XCoreImpOpBase + 0,	177,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #346 = CRC8_l4r
    { 345,	2,	1,	4,	0,	0,	0,	XCoreImpOpBase + 0,	154,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #345 = CLZ_l2r
    { 344,	1,	0,	2,	0,	0,	0,	XCoreImpOpBase + 0,	1,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #344 = CLRSR_u6
    { 343,	1,	0,	4,	0,	0,	0,	XCoreImpOpBase + 0,	1,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #343 = CLRSR_lu6
    { 342,	1,	0,	2,	0,	0,	0,	XCoreImpOpBase + 0,	1,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #342 = CLRSR_branch_u6
    { 341,	1,	0,	4,	0,	0,	0,	XCoreImpOpBase + 0,	1,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #341 = CLRSR_branch_lu6
    { 340,	1,	0,	2,	0,	0,	0,	XCoreImpOpBase + 0,	156,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #340 = CLRPT_1R
    { 339,	0,	0,	2,	0,	0,	0,	XCoreImpOpBase + 0,	1,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #339 = CLRE_0R
    { 338,	2,	0,	2,	0,	0,	0,	XCoreImpOpBase + 0,	175,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #338 = CHKCT_rus
    { 337,	2,	0,	2,	0,	0,	0,	XCoreImpOpBase + 0,	154,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #337 = CHKCT_2r
    { 336,	2,	1,	4,	0,	0,	0,	XCoreImpOpBase + 0,	154,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #336 = BYTEREV_l2r
    { 335,	1,	0,	2,	0,	0,	0,	XCoreImpOpBase + 0,	156,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #335 = BRU_1r
    { 334,	1,	0,	2,	0,	0,	0,	XCoreImpOpBase + 0,	0,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #334 = BRFU_u6
    { 333,	1,	0,	4,	0,	0,	0,	XCoreImpOpBase + 0,	0,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #333 = BRFU_lu6
    { 332,	2,	0,	2,	0,	0,	0,	XCoreImpOpBase + 0,	173,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #332 = BRFT_ru6
    { 331,	2,	0,	4,	0,	0,	0,	XCoreImpOpBase + 0,	173,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #331 = BRFT_lru6
    { 330,	2,	0,	2,	0,	0,	0,	XCoreImpOpBase + 0,	173,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #330 = BRFF_ru6
    { 329,	2,	0,	4,	0,	0,	0,	XCoreImpOpBase + 0,	173,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #329 = BRFF_lru6
    { 328,	1,	0,	2,	0,	0,	0,	XCoreImpOpBase + 0,	0,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #328 = BRBU_u6
    { 327,	1,	0,	4,	0,	0,	0,	XCoreImpOpBase + 0,	0,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #327 = BRBU_lu6
    { 326,	2,	0,	2,	0,	0,	0,	XCoreImpOpBase + 0,	173,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #326 = BRBT_ru6
    { 325,	2,	0,	4,	0,	0,	0,	XCoreImpOpBase + 0,	173,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #325 = BRBT_lru6
    { 324,	2,	0,	2,	0,	0,	0,	XCoreImpOpBase + 0,	173,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #324 = BRBF_ru6
    { 323,	2,	0,	4,	0,	0,	0,	XCoreImpOpBase + 0,	173,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #323 = BRBF_lru6
    { 322,	1,	0,	2,	0,	1,	6,	XCoreImpOpBase + 2,	0,	0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #322 = BLRF_u10
    { 321,	1,	0,	4,	0,	1,	6,	XCoreImpOpBase + 2,	0,	0|(1ULL<<MCID::Call)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #321 = BLRF_lu10
    { 320,	1,	0,	2,	0,	1,	6,	XCoreImpOpBase + 2,	0,	0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #320 = BLRB_u10
    { 319,	1,	0,	4,	0,	1,	6,	XCoreImpOpBase + 2,	0,	0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #319 = BLRB_lu10
    { 318,	1,	0,	2,	0,	1,	6,	XCoreImpOpBase + 2,	156,	0|(1ULL<<MCID::Call)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #318 = BLA_1r
    { 317,	1,	0,	2,	0,	1,	0,	XCoreImpOpBase + 9,	1,	0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #317 = BLAT_u6
    { 316,	1,	0,	4,	0,	1,	0,	XCoreImpOpBase + 9,	1,	0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #316 = BLAT_lu6
    { 315,	1,	0,	2,	0,	1,	6,	XCoreImpOpBase + 2,	1,	0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #315 = BLACP_u10
    { 314,	1,	0,	4,	0,	1,	6,	XCoreImpOpBase + 2,	1,	0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #314 = BLACP_lu10
    { 313,	2,	1,	4,	0,	0,	0,	XCoreImpOpBase + 0,	154,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #313 = BITREV_l2r
    { 312,	1,	0,	2,	0,	0,	0,	XCoreImpOpBase + 0,	156,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #312 = BAU_1r
    { 311,	3,	1,	4,	0,	0,	0,	XCoreImpOpBase + 0,	167,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #311 = ASHR_l3r
    { 310,	3,	1,	4,	0,	0,	0,	XCoreImpOpBase + 0,	164,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #310 = ASHR_l2rus
    { 309,	3,	1,	2,	0,	0,	0,	XCoreImpOpBase + 0,	167,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #309 = AND_3r
    { 308,	3,	1,	2,	0,	0,	0,	XCoreImpOpBase + 0,	170,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #308 = ANDNOT_2r
    { 307,	3,	1,	2,	0,	0,	0,	XCoreImpOpBase + 0,	167,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #307 = ADD_3r
    { 306,	3,	1,	2,	0,	0,	0,	XCoreImpOpBase + 0,	164,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #306 = ADD_2rus
    { 305,	3,	0,	0,	0,	0,	0,	XCoreImpOpBase + 0,	157,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #305 = STWFI
    { 304,	4,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	160,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #304 = SELECT_CC
    { 303,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	157,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #303 = LDWFI
    { 302,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	157,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #302 = LDAWFI
    { 301,	1,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	156,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #301 = FRAME_TO_ARGS_OFFSET
    { 300,	2,	0,	0,	0,	0,	0,	XCoreImpOpBase + 0,	154,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #300 = EH_RETURN
    { 299,	2,	0,	0,	0,	0,	0,	XCoreImpOpBase + 0,	152,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #299 = BR_JT32
    { 298,	2,	0,	0,	0,	0,	0,	XCoreImpOpBase + 0,	152,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #298 = BR_JT
    { 297,	2,	0,	0,	0,	1,	1,	XCoreImpOpBase + 0,	21,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #297 = ADJCALLSTACKUP
    { 296,	2,	0,	0,	0,	1,	1,	XCoreImpOpBase + 0,	21,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #296 = ADJCALLSTACKDOWN
    { 295,	4,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	148,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #295 = G_UBFX
    { 294,	4,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	148,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #294 = G_SBFX
    { 293,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #293 = G_VECREDUCE_UMIN
    { 292,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #292 = G_VECREDUCE_UMAX
    { 291,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #291 = G_VECREDUCE_SMIN
    { 290,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #290 = G_VECREDUCE_SMAX
    { 289,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #289 = G_VECREDUCE_XOR
    { 288,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #288 = G_VECREDUCE_OR
    { 287,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #287 = G_VECREDUCE_AND
    { 286,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #286 = G_VECREDUCE_MUL
    { 285,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #285 = G_VECREDUCE_ADD
    { 284,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #284 = G_VECREDUCE_FMINIMUM
    { 283,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #283 = G_VECREDUCE_FMAXIMUM
    { 282,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #282 = G_VECREDUCE_FMIN
    { 281,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #281 = G_VECREDUCE_FMAX
    { 280,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #280 = G_VECREDUCE_FMUL
    { 279,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #279 = G_VECREDUCE_FADD
    { 278,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	131,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #278 = G_VECREDUCE_SEQ_FMUL
    { 277,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	131,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #277 = G_VECREDUCE_SEQ_FADD
    { 276,	1,	0,	0,	0,	0,	0,	XCoreImpOpBase + 0,	1,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #276 = G_UBSANTRAP
    { 275,	0,	0,	0,	0,	0,	0,	XCoreImpOpBase + 0,	1,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #275 = G_DEBUGTRAP
    { 274,	0,	0,	0,	0,	0,	0,	XCoreImpOpBase + 0,	1,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #274 = G_TRAP
    { 273,	3,	0,	0,	0,	0,	0,	XCoreImpOpBase + 0,	58,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #273 = G_BZERO
    { 272,	4,	0,	0,	0,	0,	0,	XCoreImpOpBase + 0,	144,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #272 = G_MEMSET
    { 271,	4,	0,	0,	0,	0,	0,	XCoreImpOpBase + 0,	144,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #271 = G_MEMMOVE
    { 270,	3,	0,	0,	0,	0,	0,	XCoreImpOpBase + 0,	131,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #270 = G_MEMCPY_INLINE
    { 269,	4,	0,	0,	0,	0,	0,	XCoreImpOpBase + 0,	144,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #269 = G_MEMCPY
    { 268,	2,	0,	0,	0,	0,	0,	XCoreImpOpBase + 0,	142,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL },  // Inst #268 = G_WRITE_REGISTER
    { 267,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	51,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL },  // Inst #267 = G_READ_REGISTER
    { 266,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	101,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #266 = G_STRICT_FLDEXP
    { 265,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #265 = G_STRICT_FSQRT
    { 264,	4,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	46,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #264 = G_STRICT_FMA
    { 263,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #263 = G_STRICT_FREM
    { 262,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #262 = G_STRICT_FDIV
    { 261,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #261 = G_STRICT_FMUL
    { 260,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #260 = G_STRICT_FSUB
    { 259,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #259 = G_STRICT_FADD
    { 258,	1,	0,	0,	0,	0,	0,	XCoreImpOpBase + 0,	50,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #258 = G_STACKRESTORE
    { 257,	1,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	50,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #257 = G_STACKSAVE
    { 256,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	69,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #256 = G_DYN_STACKALLOC
    { 255,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	51,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #255 = G_JUMP_TABLE
    { 254,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	51,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #254 = G_BLOCK_ADDR
    { 253,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #253 = G_ADDRSPACE_CAST
    { 252,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #252 = G_FNEARBYINT
    { 251,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #251 = G_FRINT
    { 250,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #250 = G_FFLOOR
    { 249,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #249 = G_FSQRT
    { 248,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #248 = G_FTANH
    { 247,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #247 = G_FSINH
    { 246,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #246 = G_FCOSH
    { 245,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #245 = G_FATAN
    { 244,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #244 = G_FASIN
    { 243,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #243 = G_FACOS
    { 242,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #242 = G_FTAN
    { 241,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #241 = G_FSIN
    { 240,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #240 = G_FCOS
    { 239,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #239 = G_FCEIL
    { 238,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #238 = G_BITREVERSE
    { 237,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #237 = G_BSWAP
    { 236,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #236 = G_CTPOP
    { 235,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #235 = G_CTLZ_ZERO_UNDEF
    { 234,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #234 = G_CTLZ
    { 233,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #233 = G_CTTZ_ZERO_UNDEF
    { 232,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #232 = G_CTTZ
    { 231,	4,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	138,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #231 = G_VECTOR_COMPRESS
    { 230,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #230 = G_SPLAT_VECTOR
    { 229,	4,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	134,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #229 = G_SHUFFLE_VECTOR
    { 228,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	131,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #228 = G_EXTRACT_VECTOR_ELT
    { 227,	4,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	127,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #227 = G_INSERT_VECTOR_ELT
    { 226,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	40,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #226 = G_EXTRACT_SUBVECTOR
    { 225,	4,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	63,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #225 = G_INSERT_SUBVECTOR
    { 224,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	51,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #224 = G_VSCALE
    { 223,	3,	0,	0,	0,	0,	0,	XCoreImpOpBase + 0,	124,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #223 = G_BRJT
    { 222,	1,	0,	0,	0,	0,	0,	XCoreImpOpBase + 0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #222 = G_BR
    { 221,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #221 = G_LLROUND
    { 220,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #220 = G_LROUND
    { 219,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #219 = G_ABS
    { 218,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #218 = G_UMAX
    { 217,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #217 = G_UMIN
    { 216,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #216 = G_SMAX
    { 215,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #215 = G_SMIN
    { 214,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	101,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #214 = G_PTRMASK
    { 213,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	101,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #213 = G_PTR_ADD
    { 212,	0,	0,	0,	0,	0,	0,	XCoreImpOpBase + 0,	1,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #212 = G_RESET_FPMODE
    { 211,	1,	0,	0,	0,	0,	0,	XCoreImpOpBase + 0,	50,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #211 = G_SET_FPMODE
    { 210,	1,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	50,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #210 = G_GET_FPMODE
    { 209,	0,	0,	0,	0,	0,	0,	XCoreImpOpBase + 0,	1,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #209 = G_RESET_FPENV
    { 208,	1,	0,	0,	0,	0,	0,	XCoreImpOpBase + 0,	50,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #208 = G_SET_FPENV
    { 207,	1,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	50,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #207 = G_GET_FPENV
    { 206,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #206 = G_FMAXIMUM
    { 205,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #205 = G_FMINIMUM
    { 204,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #204 = G_FMAXNUM_IEEE
    { 203,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #203 = G_FMINNUM_IEEE
    { 202,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #202 = G_FMAXNUM
    { 201,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #201 = G_FMINNUM
    { 200,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #200 = G_FCANONICALIZE
    { 199,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	98,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #199 = G_IS_FPCLASS
    { 198,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	101,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #198 = G_FCOPYSIGN
    { 197,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #197 = G_FABS
    { 196,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #196 = G_UITOFP
    { 195,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #195 = G_SITOFP
    { 194,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #194 = G_FPTOUI
    { 193,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #193 = G_FPTOSI
    { 192,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #192 = G_FPTRUNC
    { 191,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #191 = G_FPEXT
    { 190,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #190 = G_FNEG
    { 189,	3,	2,	0,	0,	0,	0,	XCoreImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #189 = G_FFREXP
    { 188,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	101,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #188 = G_FLDEXP
    { 187,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #187 = G_FLOG10
    { 186,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #186 = G_FLOG2
    { 185,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #185 = G_FLOG
    { 184,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #184 = G_FEXP10
    { 183,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #183 = G_FEXP2
    { 182,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #182 = G_FEXP
    { 181,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	101,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #181 = G_FPOWI
    { 180,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #180 = G_FPOW
    { 179,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #179 = G_FREM
    { 178,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #178 = G_FDIV
    { 177,	4,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	46,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #177 = G_FMAD
    { 176,	4,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	46,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #176 = G_FMA
    { 175,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #175 = G_FMUL
    { 174,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #174 = G_FSUB
    { 173,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #173 = G_FADD
    { 172,	4,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	120,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #172 = G_UDIVFIXSAT
    { 171,	4,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	120,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #171 = G_SDIVFIXSAT
    { 170,	4,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	120,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #170 = G_UDIVFIX
    { 169,	4,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	120,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #169 = G_SDIVFIX
    { 168,	4,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	120,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #168 = G_UMULFIXSAT
    { 167,	4,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	120,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #167 = G_SMULFIXSAT
    { 166,	4,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	120,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #166 = G_UMULFIX
    { 165,	4,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	120,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #165 = G_SMULFIX
    { 164,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	101,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #164 = G_SSHLSAT
    { 163,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	101,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #163 = G_USHLSAT
    { 162,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #162 = G_SSUBSAT
    { 161,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #161 = G_USUBSAT
    { 160,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #160 = G_SADDSAT
    { 159,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #159 = G_UADDSAT
    { 158,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #158 = G_SMULH
    { 157,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #157 = G_UMULH
    { 156,	4,	2,	0,	0,	0,	0,	XCoreImpOpBase + 0,	87,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #156 = G_SMULO
    { 155,	4,	2,	0,	0,	0,	0,	XCoreImpOpBase + 0,	87,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #155 = G_UMULO
    { 154,	5,	2,	0,	0,	0,	0,	XCoreImpOpBase + 0,	115,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #154 = G_SSUBE
    { 153,	4,	2,	0,	0,	0,	0,	XCoreImpOpBase + 0,	87,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #153 = G_SSUBO
    { 152,	5,	2,	0,	0,	0,	0,	XCoreImpOpBase + 0,	115,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #152 = G_SADDE
    { 151,	4,	2,	0,	0,	0,	0,	XCoreImpOpBase + 0,	87,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #151 = G_SADDO
    { 150,	5,	2,	0,	0,	0,	0,	XCoreImpOpBase + 0,	115,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #150 = G_USUBE
    { 149,	4,	2,	0,	0,	0,	0,	XCoreImpOpBase + 0,	87,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #149 = G_USUBO
    { 148,	5,	2,	0,	0,	0,	0,	XCoreImpOpBase + 0,	115,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #148 = G_UADDE
    { 147,	4,	2,	0,	0,	0,	0,	XCoreImpOpBase + 0,	87,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #147 = G_UADDO
    { 146,	4,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	87,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #146 = G_SELECT
    { 145,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	112,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #145 = G_UCMP
    { 144,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	112,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #144 = G_SCMP
    { 143,	4,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	108,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #143 = G_FCMP
    { 142,	4,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	108,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #142 = G_ICMP
    { 141,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	101,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #141 = G_ROTL
    { 140,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	101,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #140 = G_ROTR
    { 139,	4,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	104,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #139 = G_FSHR
    { 138,	4,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	104,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #138 = G_FSHL
    { 137,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	101,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #137 = G_ASHR
    { 136,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	101,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #136 = G_LSHR
    { 135,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	101,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #135 = G_SHL
    { 134,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #134 = G_ZEXT
    { 133,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	40,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #133 = G_SEXT_INREG
    { 132,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #132 = G_SEXT
    { 131,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	98,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #131 = G_VAARG
    { 130,	1,	0,	0,	0,	0,	0,	XCoreImpOpBase + 0,	50,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #130 = G_VASTART
    { 129,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	51,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #129 = G_FCONSTANT
    { 128,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	51,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #128 = G_CONSTANT
    { 127,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #127 = G_TRUNC
    { 126,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #126 = G_ANYEXT
    { 125,	1,	0,	0,	0,	0,	0,	XCoreImpOpBase + 0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL },  // Inst #125 = G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
    { 124,	1,	0,	0,	0,	0,	0,	XCoreImpOpBase + 0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL },  // Inst #124 = G_INTRINSIC_CONVERGENT
    { 123,	1,	0,	0,	0,	0,	0,	XCoreImpOpBase + 0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #123 = G_INTRINSIC_W_SIDE_EFFECTS
    { 122,	1,	0,	0,	0,	0,	0,	XCoreImpOpBase + 0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #122 = G_INTRINSIC
    { 121,	0,	0,	0,	0,	0,	0,	XCoreImpOpBase + 0,	1,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #121 = G_INVOKE_REGION_START
    { 120,	1,	0,	0,	0,	0,	0,	XCoreImpOpBase + 0,	50,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #120 = G_BRINDIRECT
    { 119,	2,	0,	0,	0,	0,	0,	XCoreImpOpBase + 0,	51,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #119 = G_BRCOND
    { 118,	4,	0,	0,	0,	0,	0,	XCoreImpOpBase + 0,	94,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #118 = G_PREFETCH
    { 117,	2,	0,	0,	0,	0,	0,	XCoreImpOpBase + 0,	21,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #117 = G_FENCE
    { 116,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #116 = G_ATOMICRMW_UDEC_WRAP
    { 115,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #115 = G_ATOMICRMW_UINC_WRAP
    { 114,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #114 = G_ATOMICRMW_FMIN
    { 113,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #113 = G_ATOMICRMW_FMAX
    { 112,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #112 = G_ATOMICRMW_FSUB
    { 111,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #111 = G_ATOMICRMW_FADD
    { 110,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #110 = G_ATOMICRMW_UMIN
    { 109,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #109 = G_ATOMICRMW_UMAX
    { 108,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #108 = G_ATOMICRMW_MIN
    { 107,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #107 = G_ATOMICRMW_MAX
    { 106,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #106 = G_ATOMICRMW_XOR
    { 105,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #105 = G_ATOMICRMW_OR
    { 104,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #104 = G_ATOMICRMW_NAND
    { 103,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #103 = G_ATOMICRMW_AND
    { 102,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #102 = G_ATOMICRMW_SUB
    { 101,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #101 = G_ATOMICRMW_ADD
    { 100,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	91,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #100 = G_ATOMICRMW_XCHG
    { 99,	4,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	87,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #99 = G_ATOMIC_CMPXCHG
    { 98,	5,	2,	0,	0,	0,	0,	XCoreImpOpBase + 0,	82,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #98 = G_ATOMIC_CMPXCHG_WITH_SUCCESS
    { 97,	5,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	77,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #97 = G_INDEXED_STORE
    { 96,	2,	0,	0,	0,	0,	0,	XCoreImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #96 = G_STORE
    { 95,	5,	2,	0,	0,	0,	0,	XCoreImpOpBase + 0,	72,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #95 = G_INDEXED_ZEXTLOAD
    { 94,	5,	2,	0,	0,	0,	0,	XCoreImpOpBase + 0,	72,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #94 = G_INDEXED_SEXTLOAD
    { 93,	5,	2,	0,	0,	0,	0,	XCoreImpOpBase + 0,	72,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #93 = G_INDEXED_LOAD
    { 92,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #92 = G_ZEXTLOAD
    { 91,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #91 = G_SEXTLOAD
    { 90,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #90 = G_LOAD
    { 89,	1,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	50,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #89 = G_READSTEADYCOUNTER
    { 88,	1,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	50,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #88 = G_READCYCLECOUNTER
    { 87,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #87 = G_INTRINSIC_ROUNDEVEN
    { 86,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #86 = G_INTRINSIC_LLRINT
    { 85,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #85 = G_INTRINSIC_LRINT
    { 84,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #84 = G_INTRINSIC_ROUND
    { 83,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #83 = G_INTRINSIC_TRUNC
    { 82,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	69,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #82 = G_INTRINSIC_FPTRUNC_ROUND
    { 81,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #81 = G_CONSTANT_FOLD_BARRIER
    { 80,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	67,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #80 = G_FREEZE
    { 79,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #79 = G_BITCAST
    { 78,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #78 = G_INTTOPTR
    { 77,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #77 = G_PTRTOINT
    { 76,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #76 = G_CONCAT_VECTORS
    { 75,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #75 = G_BUILD_VECTOR_TRUNC
    { 74,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #74 = G_BUILD_VECTOR
    { 73,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #73 = G_MERGE_VALUES
    { 72,	4,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	63,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #72 = G_INSERT
    { 71,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	61,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #71 = G_UNMERGE_VALUES
    { 70,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	58,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #70 = G_EXTRACT
    { 69,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	51,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #69 = G_CONSTANT_POOL
    { 68,	5,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	53,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #68 = G_PTRAUTH_GLOBAL_VALUE
    { 67,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	51,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #67 = G_GLOBAL_VALUE
    { 66,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	51,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #66 = G_FRAME_INDEX
    { 65,	1,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	50,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #65 = G_PHI
    { 64,	1,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	50,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #64 = G_IMPLICIT_DEF
    { 63,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #63 = G_XOR
    { 62,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #62 = G_OR
    { 61,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #61 = G_AND
    { 60,	4,	2,	0,	0,	0,	0,	XCoreImpOpBase + 0,	46,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #60 = G_UDIVREM
    { 59,	4,	2,	0,	0,	0,	0,	XCoreImpOpBase + 0,	46,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #59 = G_SDIVREM
    { 58,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #58 = G_UREM
    { 57,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #57 = G_SREM
    { 56,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #56 = G_UDIV
    { 55,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #55 = G_SDIV
    { 54,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #54 = G_MUL
    { 53,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #53 = G_SUB
    { 52,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	43,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #52 = G_ADD
    { 51,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	40,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #51 = G_ASSERT_ALIGN
    { 50,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	40,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #50 = G_ASSERT_ZEXT
    { 49,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	40,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #49 = G_ASSERT_SEXT
    { 48,	1,	0,	0,	0,	0,	0,	XCoreImpOpBase + 0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL },  // Inst #48 = CONVERGENCECTRL_GLUE
    { 47,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	13,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL },  // Inst #47 = CONVERGENCECTRL_LOOP
    { 46,	1,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL },  // Inst #46 = CONVERGENCECTRL_ANCHOR
    { 45,	1,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL },  // Inst #45 = CONVERGENCECTRL_ENTRY
    { 44,	1,	0,	0,	0,	0,	0,	XCoreImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #44 = JUMP_TABLE_DEBUG_INFO
    { 43,	0,	0,	0,	0,	0,	0,	XCoreImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #43 = MEMBARRIER
    { 42,	0,	0,	0,	0,	0,	0,	XCoreImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #42 = FAKE_USE
    { 41,	0,	0,	0,	0,	0,	0,	XCoreImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #41 = ICALL_BRANCH_FUNNEL
    { 40,	3,	0,	0,	0,	0,	0,	XCoreImpOpBase + 0,	37,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #40 = PATCHABLE_TYPED_EVENT_CALL
    { 39,	2,	0,	0,	0,	0,	0,	XCoreImpOpBase + 0,	35,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #39 = PATCHABLE_EVENT_CALL
    { 38,	0,	0,	0,	0,	0,	0,	XCoreImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #38 = PATCHABLE_TAIL_CALL
    { 37,	0,	0,	0,	0,	0,	0,	XCoreImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #37 = PATCHABLE_FUNCTION_EXIT
    { 36,	0,	0,	0,	0,	0,	0,	XCoreImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #36 = PATCHABLE_RET
    { 35,	0,	0,	0,	0,	0,	0,	XCoreImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #35 = PATCHABLE_FUNCTION_ENTER
    { 34,	0,	0,	0,	0,	0,	0,	XCoreImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #34 = PATCHABLE_OP
    { 33,	1,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #33 = FAULTING_OP
    { 32,	2,	0,	0,	0,	0,	0,	XCoreImpOpBase + 0,	33,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #32 = LOCAL_ESCAPE
    { 31,	0,	0,	0,	0,	0,	0,	XCoreImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #31 = STATEPOINT
    { 30,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	30,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #30 = PREALLOCATED_ARG
    { 29,	1,	0,	0,	0,	0,	0,	XCoreImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #29 = PREALLOCATED_SETUP
    { 28,	1,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	29,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #28 = LOAD_STACK_GUARD
    { 27,	6,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	23,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #27 = PATCHPOINT
    { 26,	0,	0,	0,	0,	0,	0,	XCoreImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #26 = FENTRY_CALL
    { 25,	2,	0,	0,	0,	0,	0,	XCoreImpOpBase + 0,	21,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #25 = STACKMAP
    { 24,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	19,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #24 = ARITH_FENCE
    { 23,	4,	0,	0,	0,	0,	0,	XCoreImpOpBase + 0,	15,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #23 = PSEUDO_PROBE
    { 22,	1,	0,	0,	0,	0,	0,	XCoreImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #22 = LIFETIME_END
    { 21,	1,	0,	0,	0,	0,	0,	XCoreImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #21 = LIFETIME_START
    { 20,	0,	0,	0,	0,	0,	0,	XCoreImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #20 = BUNDLE
    { 19,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	13,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #19 = COPY
    { 18,	2,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	13,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #18 = REG_SEQUENCE
    { 17,	1,	0,	0,	0,	0,	0,	XCoreImpOpBase + 0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #17 = DBG_LABEL
    { 16,	0,	0,	0,	0,	0,	0,	XCoreImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #16 = DBG_PHI
    { 15,	0,	0,	0,	0,	0,	0,	XCoreImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #15 = DBG_INSTR_REF
    { 14,	0,	0,	0,	0,	0,	0,	XCoreImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #14 = DBG_VALUE_LIST
    { 13,	0,	0,	0,	0,	0,	0,	XCoreImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #13 = DBG_VALUE
    { 12,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #12 = COPY_TO_REGCLASS
    { 11,	4,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	9,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #11 = SUBREG_TO_REG
    { 10,	1,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #10 = IMPLICIT_DEF
    { 9,	4,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	5,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #9 = INSERT_SUBREG
    { 8,	3,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #8 = EXTRACT_SUBREG
    { 7,	0,	0,	0,	0,	0,	0,	XCoreImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #7 = KILL
    { 6,	1,	0,	0,	0,	0,	0,	XCoreImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #6 = ANNOTATION_LABEL
    { 5,	1,	0,	0,	0,	0,	0,	XCoreImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #5 = GC_LABEL
    { 4,	1,	0,	0,	0,	0,	0,	XCoreImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #4 = EH_LABEL
    { 3,	1,	0,	0,	0,	0,	0,	XCoreImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #3 = CFI_INSTRUCTION
    { 2,	0,	0,	0,	0,	0,	0,	XCoreImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #2 = INLINEASM_BR
    { 1,	0,	0,	0,	0,	0,	0,	XCoreImpOpBase + 0,	1,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1 = INLINEASM
    { 0,	1,	1,	0,	0,	0,	0,	XCoreImpOpBase + 0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #0 = PHI
  }, {
    /* 0 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 1 */
    /* 1 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 2 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 5 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 9 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 13 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 15 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 19 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) },
    /* 21 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 23 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 29 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 },
    /* 30 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 33 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 35 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 37 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 40 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
    /* 43 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
    /* 46 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
    /* 50 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
    /* 51 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 53 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 58 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
    /* 61 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
    /* 63 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
    /* 67 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
    /* 69 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 72 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 77 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 82 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
    /* 87 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
    /* 91 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
    /* 94 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 98 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 101 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
    /* 104 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
    /* 108 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
    /* 112 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
    /* 115 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
    /* 120 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
    /* 124 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
    /* 127 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
    /* 131 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
    /* 134 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 138 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
    /* 142 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
    /* 144 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
    /* 148 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
    /* 152 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 154 */ { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 156 */ { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 157 */ { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 160 */ { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 164 */ { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 167 */ { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 170 */ { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 173 */ { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 175 */ { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 177 */ { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 182 */ { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 186 */ { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 191 */ { XCore::RRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 193 */ { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 199 */ { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 205 */ { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 208 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 210 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
  }, {
    /* 0 */
    /* 0 */ XCore::SP, XCore::SP,
    /* 2 */ XCore::SP, XCore::R0, XCore::R1, XCore::R2, XCore::R3, XCore::R11, XCore::LR,
    /* 9 */ XCore::R11,
    /* 10 */ XCore::SP,
  }
};


#ifdef __GNUC__
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Woverlength-strings"
#endif
extern const char XCoreInstrNameData[] = {
  /* 0 */ "G_FLOG10\0"
  /* 9 */ "G_FEXP10\0"
  /* 18 */ "LDAPB_u10\0"
  /* 28 */ "BLRB_u10\0"
  /* 37 */ "LDAPF_u10\0"
  /* 47 */ "BLRF_u10\0"
  /* 56 */ "BLACP_u10\0"
  /* 66 */ "LDWCP_u10\0"
  /* 76 */ "LDAPB_lu10\0"
  /* 87 */ "BLRB_lu10\0"
  /* 97 */ "LDAPF_lu10\0"
  /* 108 */ "BLRF_lu10\0"
  /* 118 */ "BLACP_lu10\0"
  /* 129 */ "LDWCP_lu10\0"
  /* 140 */ "BR_JT32\0"
  /* 148 */ "G_FLOG2\0"
  /* 156 */ "G_FEXP2\0"
  /* 164 */ "KCALL_u6\0"
  /* 173 */ "LDAWCP_u6\0"
  /* 183 */ "EXTDP_u6\0"
  /* 192 */ "RETSP_u6\0"
  /* 201 */ "KENTSP_u6\0"
  /* 211 */ "KRESTSP_u6\0"
  /* 222 */ "EXTSP_u6\0"
  /* 231 */ "CLRSR_u6\0"
  /* 240 */ "GETSR_u6\0"
  /* 249 */ "SETSR_u6\0"
  /* 258 */ "BLAT_u6\0"
  /* 266 */ "BRBU_u6\0"
  /* 274 */ "BRFU_u6\0"
  /* 282 */ "CLRSR_branch_u6\0"
  /* 298 */ "SETSR_branch_u6\0"
  /* 314 */ "KCALL_lu6\0"
  /* 324 */ "LDAWCP_lu6\0"
  /* 335 */ "EXTDP_lu6\0"
  /* 345 */ "RETSP_lu6\0"
  /* 355 */ "KENTSP_lu6\0"
  /* 366 */ "KRESTSP_lu6\0"
  /* 378 */ "EXTSP_lu6\0"
  /* 388 */ "CLRSR_lu6\0"
  /* 398 */ "GETSR_lu6\0"
  /* 408 */ "SETSR_lu6\0"
  /* 418 */ "BLAT_lu6\0"
  /* 427 */ "BRBU_lu6\0"
  /* 436 */ "BRFU_lu6\0"
  /* 445 */ "CLRSR_branch_lu6\0"
  /* 462 */ "SETSR_branch_lu6\0"
  /* 479 */ "LDC_ru6\0"
  /* 487 */ "SETC_ru6\0"
  /* 496 */ "BRBF_ru6\0"
  /* 505 */ "BRFF_ru6\0"
  /* 514 */ "LDWCP_ru6\0"
  /* 524 */ "LDAWDP_ru6\0"
  /* 535 */ "LDWDP_ru6\0"
  /* 545 */ "STWDP_ru6\0"
  /* 555 */ "LDAWSP_ru6\0"
  /* 566 */ "LDWSP_ru6\0"
  /* 576 */ "STWSP_ru6\0"
  /* 586 */ "BRBT_ru6\0"
  /* 595 */ "BRFT_ru6\0"
  /* 604 */ "LDC_lru6\0"
  /* 613 */ "SETC_lru6\0"
  /* 623 */ "BRBF_lru6\0"
  /* 633 */ "BRFF_lru6\0"
  /* 643 */ "LDWCP_lru6\0"
  /* 654 */ "LDAWDP_lru6\0"
  /* 666 */ "LDWDP_lru6\0"
  /* 677 */ "STWDP_lru6\0"
  /* 688 */ "LDAWSP_lru6\0"
  /* 700 */ "LDWSP_lru6\0"
  /* 711 */ "STWSP_lru6\0"
  /* 722 */ "BRBT_lru6\0"
  /* 732 */ "BRFT_lru6\0"
  /* 742 */ "G_FMA\0"
  /* 748 */ "G_STRICT_FMA\0"
  /* 761 */ "G_FSUB\0"
  /* 768 */ "G_STRICT_FSUB\0"
  /* 782 */ "G_ATOMICRMW_FSUB\0"
  /* 799 */ "G_SUB\0"
  /* 805 */ "G_ATOMICRMW_SUB\0"
  /* 821 */ "SELECT_CC\0"
  /* 831 */ "G_INTRINSIC\0"
  /* 843 */ "G_FPTRUNC\0"
  /* 853 */ "G_INTRINSIC_TRUNC\0"
  /* 871 */ "G_TRUNC\0"
  /* 879 */ "G_BUILD_VECTOR_TRUNC\0"
  /* 900 */ "G_DYN_STACKALLOC\0"
  /* 917 */ "G_FMAD\0"
  /* 924 */ "G_INDEXED_SEXTLOAD\0"
  /* 943 */ "G_SEXTLOAD\0"
  /* 954 */ "G_INDEXED_ZEXTLOAD\0"
  /* 973 */ "G_ZEXTLOAD\0"
  /* 984 */ "G_INDEXED_LOAD\0"
  /* 999 */ "G_LOAD\0"
  /* 1006 */ "G_VECREDUCE_FADD\0"
  /* 1023 */ "G_FADD\0"
  /* 1030 */ "G_VECREDUCE_SEQ_FADD\0"
  /* 1051 */ "G_STRICT_FADD\0"
  /* 1065 */ "G_ATOMICRMW_FADD\0"
  /* 1082 */ "G_VECREDUCE_ADD\0"
  /* 1098 */ "G_ADD\0"
  /* 1104 */ "G_PTR_ADD\0"
  /* 1114 */ "G_ATOMICRMW_ADD\0"
  /* 1130 */ "G_ATOMICRMW_NAND\0"
  /* 1147 */ "G_VECREDUCE_AND\0"
  /* 1163 */ "G_AND\0"
  /* 1169 */ "G_ATOMICRMW_AND\0"
  /* 1185 */ "LIFETIME_END\0"
  /* 1198 */ "G_BRCOND\0"
  /* 1207 */ "G_LLROUND\0"
  /* 1217 */ "G_LROUND\0"
  /* 1226 */ "G_INTRINSIC_ROUND\0"
  /* 1244 */ "G_INTRINSIC_FPTRUNC_ROUND\0"
  /* 1270 */ "LOAD_STACK_GUARD\0"
  /* 1287 */ "PSEUDO_PROBE\0"
  /* 1300 */ "G_SSUBE\0"
  /* 1308 */ "G_USUBE\0"
  /* 1316 */ "G_FENCE\0"
  /* 1324 */ "ARITH_FENCE\0"
  /* 1336 */ "REG_SEQUENCE\0"
  /* 1349 */ "G_SADDE\0"
  /* 1357 */ "G_UADDE\0"
  /* 1365 */ "G_GET_FPMODE\0"
  /* 1378 */ "G_RESET_FPMODE\0"
  /* 1393 */ "G_SET_FPMODE\0"
  /* 1406 */ "G_FMINNUM_IEEE\0"
  /* 1421 */ "G_FMAXNUM_IEEE\0"
  /* 1436 */ "G_VSCALE\0"
  /* 1445 */ "G_JUMP_TABLE\0"
  /* 1458 */ "BUNDLE\0"
  /* 1465 */ "G_MEMCPY_INLINE\0"
  /* 1481 */ "LOCAL_ESCAPE\0"
  /* 1494 */ "G_STACKRESTORE\0"
  /* 1509 */ "G_INDEXED_STORE\0"
  /* 1525 */ "G_STORE\0"
  /* 1533 */ "G_BITREVERSE\0"
  /* 1546 */ "FAKE_USE\0"
  /* 1555 */ "DBG_VALUE\0"
  /* 1565 */ "G_GLOBAL_VALUE\0"
  /* 1580 */ "G_PTRAUTH_GLOBAL_VALUE\0"
  /* 1603 */ "CONVERGENCECTRL_GLUE\0"
  /* 1624 */ "G_STACKSAVE\0"
  /* 1636 */ "G_MEMMOVE\0"
  /* 1646 */ "G_FREEZE\0"
  /* 1655 */ "G_FCANONICALIZE\0"
  /* 1671 */ "G_CTLZ_ZERO_UNDEF\0"
  /* 1689 */ "G_CTTZ_ZERO_UNDEF\0"
  /* 1707 */ "G_IMPLICIT_DEF\0"
  /* 1722 */ "DBG_INSTR_REF\0"
  /* 1736 */ "G_FNEG\0"
  /* 1743 */ "EXTRACT_SUBREG\0"
  /* 1758 */ "INSERT_SUBREG\0"
  /* 1772 */ "G_SEXT_INREG\0"
  /* 1785 */ "SUBREG_TO_REG\0"
  /* 1799 */ "G_ATOMIC_CMPXCHG\0"
  /* 1816 */ "G_ATOMICRMW_XCHG\0"
  /* 1833 */ "G_FLOG\0"
  /* 1840 */ "G_VAARG\0"
  /* 1848 */ "PREALLOCATED_ARG\0"
  /* 1865 */ "G_PREFETCH\0"
  /* 1876 */ "G_SMULH\0"
  /* 1884 */ "G_UMULH\0"
  /* 1892 */ "G_FTANH\0"
  /* 1900 */ "G_FSINH\0"
  /* 1908 */ "G_FCOSH\0"
  /* 1916 */ "LDAWFI\0"
  /* 1923 */ "LDWFI\0"
  /* 1929 */ "STWFI\0"
  /* 1935 */ "DBG_PHI\0"
  /* 1943 */ "G_FPTOSI\0"
  /* 1952 */ "G_FPTOUI\0"
  /* 1961 */ "G_FPOWI\0"
  /* 1969 */ "G_PTRMASK\0"
  /* 1979 */ "GC_LABEL\0"
  /* 1988 */ "DBG_LABEL\0"
  /* 1998 */ "EH_LABEL\0"
  /* 2007 */ "ANNOTATION_LABEL\0"
  /* 2024 */ "ICALL_BRANCH_FUNNEL\0"
  /* 2044 */ "G_FSHL\0"
  /* 2051 */ "G_SHL\0"
  /* 2057 */ "G_FCEIL\0"
  /* 2065 */ "PATCHABLE_TAIL_CALL\0"
  /* 2085 */ "PATCHABLE_TYPED_EVENT_CALL\0"
  /* 2112 */ "PATCHABLE_EVENT_CALL\0"
  /* 2133 */ "FENTRY_CALL\0"
  /* 2145 */ "KILL\0"
  /* 2150 */ "G_CONSTANT_POOL\0"
  /* 2166 */ "G_ROTL\0"
  /* 2173 */ "G_VECREDUCE_FMUL\0"
  /* 2190 */ "G_FMUL\0"
  /* 2197 */ "G_VECREDUCE_SEQ_FMUL\0"
  /* 2218 */ "G_STRICT_FMUL\0"
  /* 2232 */ "G_VECREDUCE_MUL\0"
  /* 2248 */ "G_MUL\0"
  /* 2254 */ "G_FREM\0"
  /* 2261 */ "G_STRICT_FREM\0"
  /* 2275 */ "G_SREM\0"
  /* 2282 */ "G_UREM\0"
  /* 2289 */ "G_SDIVREM\0"
  /* 2299 */ "G_UDIVREM\0"
  /* 2309 */ "INLINEASM\0"
  /* 2319 */ "G_VECREDUCE_FMINIMUM\0"
  /* 2340 */ "G_FMINIMUM\0"
  /* 2351 */ "G_VECREDUCE_FMAXIMUM\0"
  /* 2372 */ "G_FMAXIMUM\0"
  /* 2383 */ "G_FMINNUM\0"
  /* 2393 */ "G_FMAXNUM\0"
  /* 2403 */ "G_FATAN\0"
  /* 2411 */ "G_FTAN\0"
  /* 2418 */ "G_INTRINSIC_ROUNDEVEN\0"
  /* 2440 */ "G_ASSERT_ALIGN\0"
  /* 2455 */ "G_FCOPYSIGN\0"
  /* 2467 */ "G_VECREDUCE_FMIN\0"
  /* 2484 */ "G_ATOMICRMW_FMIN\0"
  /* 2501 */ "G_VECREDUCE_SMIN\0"
  /* 2518 */ "G_SMIN\0"
  /* 2525 */ "G_VECREDUCE_UMIN\0"
  /* 2542 */ "G_UMIN\0"
  /* 2549 */ "G_ATOMICRMW_UMIN\0"
  /* 2566 */ "G_ATOMICRMW_MIN\0"
  /* 2582 */ "G_FASIN\0"
  /* 2590 */ "G_FSIN\0"
  /* 2597 */ "CFI_INSTRUCTION\0"
  /* 2613 */ "EH_RETURN\0"
  /* 2623 */ "ADJCALLSTACKDOWN\0"
  /* 2640 */ "G_SSUBO\0"
  /* 2648 */ "G_USUBO\0"
  /* 2656 */ "G_SADDO\0"
  /* 2664 */ "G_UADDO\0"
  /* 2672 */ "JUMP_TABLE_DEBUG_INFO\0"
  /* 2694 */ "G_SMULO\0"
  /* 2702 */ "G_UMULO\0"
  /* 2710 */ "G_BZERO\0"
  /* 2718 */ "STACKMAP\0"
  /* 2727 */ "G_DEBUGTRAP\0"
  /* 2739 */ "G_UBSANTRAP\0"
  /* 2751 */ "G_TRAP\0"
  /* 2758 */ "G_ATOMICRMW_UDEC_WRAP\0"
  /* 2780 */ "G_ATOMICRMW_UINC_WRAP\0"
  /* 2802 */ "G_BSWAP\0"
  /* 2810 */ "G_SITOFP\0"
  /* 2819 */ "G_UITOFP\0"
  /* 2828 */ "G_FCMP\0"
  /* 2835 */ "G_ICMP\0"
  /* 2842 */ "G_SCMP\0"
  /* 2849 */ "G_UCMP\0"
  /* 2856 */ "CONVERGENCECTRL_LOOP\0"
  /* 2877 */ "G_CTPOP\0"
  /* 2885 */ "PATCHABLE_OP\0"
  /* 2898 */ "FAULTING_OP\0"
  /* 2910 */ "ADJCALLSTACKUP\0"
  /* 2925 */ "PREALLOCATED_SETUP\0"
  /* 2944 */ "G_FLDEXP\0"
  /* 2953 */ "G_STRICT_FLDEXP\0"
  /* 2969 */ "G_FEXP\0"
  /* 2976 */ "G_FFREXP\0"
  /* 2985 */ "LDSPC_0R\0"
  /* 2994 */ "STSPC_0R\0"
  /* 3003 */ "LDSED_0R\0"
  /* 3012 */ "STSED_0R\0"
  /* 3021 */ "GETED_0R\0"
  /* 3030 */ "GETID_0R\0"
  /* 3039 */ "CLRE_0R\0"
  /* 3047 */ "DCALL_0R\0"
  /* 3056 */ "GETKEP_0R\0"
  /* 3066 */ "SETKEP_0R\0"
  /* 3076 */ "GETKSP_0R\0"
  /* 3086 */ "DENTSP_0R\0"
  /* 3096 */ "DRESTSP_0R\0"
  /* 3107 */ "LDSSR_0R\0"
  /* 3116 */ "STSSR_0R\0"
  /* 3125 */ "LDET_0R\0"
  /* 3133 */ "FREET_0R\0"
  /* 3142 */ "DRET_0R\0"
  /* 3150 */ "KRET_0R\0"
  /* 3158 */ "GETET_0R\0"
  /* 3167 */ "STET_0R\0"
  /* 3175 */ "WAITEU_0R\0"
  /* 3185 */ "WAITEF_1R\0"
  /* 3195 */ "WAITET_1R\0"
  /* 3205 */ "CLRPT_1R\0"
  /* 3214 */ "TSTART_1R\0"
  /* 3224 */ "G_BR\0"
  /* 3229 */ "INLINEASM_BR\0"
  /* 3242 */ "G_BLOCK_ADDR\0"
  /* 3255 */ "MEMBARRIER\0"
  /* 3266 */ "G_CONSTANT_FOLD_BARRIER\0"
  /* 3290 */ "PATCHABLE_FUNCTION_ENTER\0"
  /* 3315 */ "G_READCYCLECOUNTER\0"
  /* 3334 */ "G_READSTEADYCOUNTER\0"
  /* 3354 */ "G_READ_REGISTER\0"
  /* 3370 */ "G_WRITE_REGISTER\0"
  /* 3387 */ "G_ASHR\0"
  /* 3394 */ "G_FSHR\0"
  /* 3401 */ "G_LSHR\0"
  /* 3408 */ "CONVERGENCECTRL_ANCHOR\0"
  /* 3431 */ "G_FFLOOR\0"
  /* 3440 */ "G_EXTRACT_SUBVECTOR\0"
  /* 3460 */ "G_INSERT_SUBVECTOR\0"
  /* 3479 */ "G_BUILD_VECTOR\0"
  /* 3494 */ "G_SHUFFLE_VECTOR\0"
  /* 3511 */ "G_SPLAT_VECTOR\0"
  /* 3526 */ "G_VECREDUCE_XOR\0"
  /* 3542 */ "G_XOR\0"
  /* 3548 */ "G_ATOMICRMW_XOR\0"
  /* 3564 */ "G_VECREDUCE_OR\0"
  /* 3579 */ "G_OR\0"
  /* 3584 */ "G_ATOMICRMW_OR\0"
  /* 3599 */ "G_ROTR\0"
  /* 3606 */ "G_INTTOPTR\0"
  /* 3617 */ "G_FABS\0"
  /* 3624 */ "G_ABS\0"
  /* 3630 */ "G_UNMERGE_VALUES\0"
  /* 3647 */ "G_MERGE_VALUES\0"
  /* 3662 */ "G_FACOS\0"
  /* 3670 */ "G_FCOS\0"
  /* 3677 */ "G_CONCAT_VECTORS\0"
  /* 3694 */ "COPY_TO_REGCLASS\0"
  /* 3711 */ "G_IS_FPCLASS\0"
  /* 3724 */ "G_ATOMIC_CMPXCHG_WITH_SUCCESS\0"
  /* 3754 */ "G_VECTOR_COMPRESS\0"
  /* 3772 */ "G_INTRINSIC_W_SIDE_EFFECTS\0"
  /* 3799 */ "G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS\0"
  /* 3837 */ "G_SSUBSAT\0"
  /* 3847 */ "G_USUBSAT\0"
  /* 3857 */ "G_SADDSAT\0"
  /* 3867 */ "G_UADDSAT\0"
  /* 3877 */ "G_SSHLSAT\0"
  /* 3887 */ "G_USHLSAT\0"
  /* 3897 */ "G_SMULFIXSAT\0"
  /* 3910 */ "G_UMULFIXSAT\0"
  /* 3923 */ "G_SDIVFIXSAT\0"
  /* 3936 */ "G_UDIVFIXSAT\0"
  /* 3949 */ "G_EXTRACT\0"
  /* 3959 */ "G_SELECT\0"
  /* 3968 */ "G_BRINDIRECT\0"
  /* 3981 */ "PATCHABLE_RET\0"
  /* 3995 */ "FRAME_TO_ARGS_OFFSET\0"
  /* 4016 */ "G_MEMSET\0"
  /* 4025 */ "PATCHABLE_FUNCTION_EXIT\0"
  /* 4049 */ "G_BRJT\0"
  /* 4056 */ "BR_JT\0"
  /* 4062 */ "G_EXTRACT_VECTOR_ELT\0"
  /* 4083 */ "G_INSERT_VECTOR_ELT\0"
  /* 4103 */ "G_FCONSTANT\0"
  /* 4115 */ "G_CONSTANT\0"
  /* 4126 */ "G_INTRINSIC_CONVERGENT\0"
  /* 4149 */ "STATEPOINT\0"
  /* 4160 */ "PATCHPOINT\0"
  /* 4171 */ "G_PTRTOINT\0"
  /* 4182 */ "G_FRINT\0"
  /* 4190 */ "G_INTRINSIC_LLRINT\0"
  /* 4209 */ "G_INTRINSIC_LRINT\0"
  /* 4227 */ "G_FNEARBYINT\0"
  /* 4240 */ "NOT\0"
  /* 4244 */ "G_VASTART\0"
  /* 4254 */ "LIFETIME_START\0"
  /* 4269 */ "G_INVOKE_REGION_START\0"
  /* 4291 */ "G_INSERT\0"
  /* 4300 */ "G_FSQRT\0"
  /* 4308 */ "G_STRICT_FSQRT\0"
  /* 4323 */ "G_BITCAST\0"
  /* 4333 */ "G_ADDRSPACE_CAST\0"
  /* 4350 */ "DBG_VALUE_LIST\0"
  /* 4365 */ "G_FPEXT\0"
  /* 4373 */ "G_SEXT\0"
  /* 4380 */ "G_ASSERT_SEXT\0"
  /* 4394 */ "G_ANYEXT\0"
  /* 4403 */ "G_ZEXT\0"
  /* 4410 */ "G_ASSERT_ZEXT\0"
  /* 4424 */ "G_FDIV\0"
  /* 4431 */ "G_STRICT_FDIV\0"
  /* 4445 */ "G_SDIV\0"
  /* 4452 */ "G_UDIV\0"
  /* 4459 */ "G_GET_FPENV\0"
  /* 4471 */ "G_RESET_FPENV\0"
  /* 4485 */ "G_SET_FPENV\0"
  /* 4497 */ "G_FPOW\0"
  /* 4504 */ "G_VECREDUCE_FMAX\0"
  /* 4521 */ "G_ATOMICRMW_FMAX\0"
  /* 4538 */ "G_VECREDUCE_SMAX\0"
  /* 4555 */ "G_SMAX\0"
  /* 4562 */ "G_VECREDUCE_UMAX\0"
  /* 4579 */ "G_UMAX\0"
  /* 4586 */ "G_ATOMICRMW_UMAX\0"
  /* 4603 */ "G_ATOMICRMW_MAX\0"
  /* 4619 */ "G_FRAME_INDEX\0"
  /* 4633 */ "G_SBFX\0"
  /* 4640 */ "G_UBFX\0"
  /* 4647 */ "G_SMULFIX\0"
  /* 4657 */ "G_UMULFIX\0"
  /* 4667 */ "G_SDIVFIX\0"
  /* 4677 */ "G_UDIVFIX\0"
  /* 4687 */ "G_MEMCPY\0"
  /* 4696 */ "COPY\0"
  /* 4701 */ "CONVERGENCECTRL_ENTRY\0"
  /* 4723 */ "G_CTLZ\0"
  /* 4730 */ "G_CTTZ\0"
  /* 4737 */ "LDAPF_lu10_ba\0"
  /* 4751 */ "SSYNC_0r\0"
  /* 4760 */ "BLA_1r\0"
  /* 4767 */ "MSYNC_1r\0"
  /* 4776 */ "ECALLF_1r\0"
  /* 4786 */ "DGETREG_1r\0"
  /* 4797 */ "KCALL_1r\0"
  /* 4806 */ "MJOIN_1r\0"
  /* 4815 */ "SETCP_1r\0"
  /* 4824 */ "SETDP_1r\0"
  /* 4833 */ "SETSP_1r\0"
  /* 4842 */ "SYNCR_1r\0"
  /* 4851 */ "FREER_1r\0"
  /* 4860 */ "ECALLT_1r\0"
  /* 4870 */ "BAU_1r\0"
  /* 4877 */ "EDU_1r\0"
  /* 4884 */ "EEU_1r\0"
  /* 4891 */ "BRU_1r\0"
  /* 4898 */ "SETEV_1r\0"
  /* 4907 */ "SETV_1r\0"
  /* 4915 */ "INITPC_2r\0"
  /* 4925 */ "SETPSC_2r\0"
  /* 4935 */ "SETD_2r\0"
  /* 4943 */ "EEF_2r\0"
  /* 4950 */ "PEEK_2r\0"
  /* 4958 */ "MKMSK_2r\0"
  /* 4967 */ "ENDIN_2r\0"
  /* 4976 */ "INITCP_2r\0"
  /* 4986 */ "INITDP_2r\0"
  /* 4996 */ "INITSP_2r\0"
  /* 5006 */ "INSHR_2r\0"
  /* 5015 */ "OUTSHR_2r\0"
  /* 5025 */ "TSETMR_2r\0"
  /* 5035 */ "GETTS_2r\0"
  /* 5044 */ "CHKCT_2r\0"
  /* 5053 */ "INCT_2r\0"
  /* 5061 */ "TESTCT_2r\0"
  /* 5071 */ "OUTCT_2r\0"
  /* 5080 */ "TESTWCT_2r\0"
  /* 5091 */ "EET_2r\0"
  /* 5098 */ "INT_2r\0"
  /* 5105 */ "ANDNOT_2r\0"
  /* 5115 */ "SETPT_2r\0"
  /* 5124 */ "GETST_2r\0"
  /* 5133 */ "OUTT_2r\0"
  /* 5141 */ "OUT_2r\0"
  /* 5148 */ "SEXT_2r\0"
  /* 5156 */ "ZEXT_2r\0"
  /* 5164 */ "SETC_l2r\0"
  /* 5173 */ "GETD_l2r\0"
  /* 5182 */ "SETCLK_l2r\0"
  /* 5193 */ "TESTLCL_l2r\0"
  /* 5205 */ "GETN_l2r\0"
  /* 5214 */ "SETN_l2r\0"
  /* 5223 */ "INITLR_l2r\0"
  /* 5234 */ "GETPS_l2r\0"
  /* 5244 */ "SETPS_l2r\0"
  /* 5254 */ "BYTEREV_l2r\0"
  /* 5266 */ "BITREV_l2r\0"
  /* 5277 */ "SETTW_l2r\0"
  /* 5287 */ "SETRDY_l2r\0"
  /* 5298 */ "CLZ_l2r\0"
  /* 5306 */ "SUB_3r\0"
  /* 5313 */ "ADD_3r\0"
  /* 5320 */ "AND_3r\0"
  /* 5327 */ "SHL_3r\0"
  /* 5334 */ "EQ_3r\0"
  /* 5340 */ "SHR_3r\0"
  /* 5347 */ "OR_3r\0"
  /* 5353 */ "TSETR_3r\0"
  /* 5362 */ "LD16S_3r\0"
  /* 5371 */ "LSS_3r\0"
  /* 5378 */ "LD8U_3r\0"
  /* 5386 */ "LSU_3r\0"
  /* 5393 */ "LDW_3r\0"
  /* 5400 */ "ST16_l3r\0"
  /* 5409 */ "ST8_l3r\0"
  /* 5417 */ "LDA16B_l3r\0"
  /* 5428 */ "LDAWB_l3r\0"
  /* 5438 */ "CRC_l3r\0"
  /* 5446 */ "LDA16F_l3r\0"
  /* 5457 */ "LDAWF_l3r\0"
  /* 5467 */ "MUL_l3r\0"
  /* 5475 */ "ASHR_l3r\0"
  /* 5484 */ "XOR_l3r\0"
  /* 5492 */ "REMS_l3r\0"
  /* 5501 */ "DIVS_l3r\0"
  /* 5510 */ "REMU_l3r\0"
  /* 5519 */ "DIVU_l3r\0"
  /* 5528 */ "STW_l3r\0"
  /* 5536 */ "CRC8_l4r\0"
  /* 5545 */ "MACCS_l4r\0"
  /* 5555 */ "MACCU_l4r\0"
  /* 5565 */ "LSUB_l5r\0"
  /* 5574 */ "LADD_l5r\0"
  /* 5583 */ "LDIVU_l5r\0"
  /* 5593 */ "LMUL_l6r\0"
  /* 5602 */ "SUB_2rus\0"
  /* 5611 */ "ADD_2rus\0"
  /* 5620 */ "SHL_2rus\0"
  /* 5629 */ "EQ_2rus\0"
  /* 5637 */ "SHR_2rus\0"
  /* 5646 */ "LDW_2rus\0"
  /* 5655 */ "STW_2rus\0"
  /* 5664 */ "LDAWB_l2rus\0"
  /* 5676 */ "LDAWF_l2rus\0"
  /* 5688 */ "ASHR_l2rus\0"
  /* 5699 */ "INPW_l2rus\0"
  /* 5710 */ "OUTPW_l2rus\0"
  /* 5722 */ "MKMSK_rus\0"
  /* 5732 */ "GETR_rus\0"
  /* 5741 */ "CHKCT_rus\0"
  /* 5751 */ "OUTCT_rus\0"
  /* 5761 */ "SEXT_rus\0"
  /* 5770 */ "ZEXT_rus\0"
};
#ifdef __GNUC__
#pragma GCC diagnostic pop
#endif

extern const unsigned XCoreInstrNameIndices[] = {
    1939U, 2309U, 3229U, 2597U, 1998U, 1979U, 2007U, 2145U, 
    1743U, 1758U, 1709U, 1785U, 3694U, 1555U, 4350U, 1722U, 
    1935U, 1988U, 1336U, 4696U, 1458U, 4254U, 1185U, 1287U, 
    1324U, 2718U, 2133U, 4160U, 1270U, 2925U, 1848U, 4149U, 
    1481U, 2898U, 2885U, 3290U, 3981U, 4025U, 2065U, 2112U, 
    2085U, 2024U, 1546U, 3255U, 2672U, 4701U, 3408U, 2856U, 
    1603U, 4380U, 4410U, 2440U, 1098U, 799U, 2248U, 4445U, 
    4452U, 2275U, 2282U, 2289U, 2299U, 1163U, 3579U, 3542U, 
    1707U, 1937U, 4619U, 1565U, 1580U, 2150U, 3949U, 3630U, 
    4291U, 3647U, 3479U, 879U, 3677U, 4171U, 3606U, 4323U, 
    1646U, 3266U, 1244U, 853U, 1226U, 4209U, 4190U, 2418U, 
    3315U, 3334U, 999U, 943U, 973U, 984U, 924U, 954U, 
    1525U, 1509U, 3724U, 1799U, 1816U, 1114U, 805U, 1169U, 
    1130U, 3584U, 3548U, 4603U, 2566U, 4586U, 2549U, 1065U, 
    782U, 4521U, 2484U, 2780U, 2758U, 1316U, 1865U, 1198U, 
    3968U, 4269U, 831U, 3772U, 4126U, 3799U, 4394U, 871U, 
    4115U, 4103U, 4244U, 1840U, 4373U, 1772U, 4403U, 2051U, 
    3401U, 3387U, 2044U, 3394U, 3599U, 2166U, 2835U, 2828U, 
    2842U, 2849U, 3959U, 2664U, 1357U, 2648U, 1308U, 2656U, 
    1349U, 2640U, 1300U, 2702U, 2694U, 1884U, 1876U, 3867U, 
    3857U, 3847U, 3837U, 3887U, 3877U, 4647U, 4657U, 3897U, 
    3910U, 4667U, 4677U, 3923U, 3936U, 1023U, 761U, 2190U, 
    742U, 917U, 4424U, 2254U, 4497U, 1961U, 2969U, 156U, 
    9U, 1833U, 148U, 0U, 2944U, 2976U, 1736U, 4365U, 
    843U, 1943U, 1952U, 2810U, 2819U, 3617U, 2455U, 3711U, 
    1655U, 2383U, 2393U, 1406U, 1421U, 2340U, 2372U, 4459U, 
    4485U, 4471U, 1365U, 1393U, 1378U, 1104U, 1969U, 2518U, 
    4555U, 2542U, 4579U, 3624U, 1217U, 1207U, 3224U, 4049U, 
    1436U, 3460U, 3440U, 4083U, 4062U, 3494U, 3511U, 3754U, 
    4730U, 1689U, 4723U, 1671U, 2877U, 2802U, 1533U, 2057U, 
    3670U, 2590U, 2411U, 3662U, 2582U, 2403U, 1908U, 1900U, 
    1892U, 4300U, 3431U, 4182U, 4227U, 4333U, 3242U, 1445U, 
    900U, 1624U, 1494U, 1051U, 768U, 2218U, 4431U, 2261U, 
    748U, 4308U, 2953U, 3354U, 3370U, 4687U, 1465U, 1636U, 
    4016U, 2710U, 2751U, 2727U, 2739U, 1030U, 2197U, 1006U, 
    2173U, 4504U, 2467U, 2351U, 2319U, 1082U, 2232U, 1147U, 
    3564U, 3526U, 4538U, 2501U, 4562U, 2525U, 4633U, 4640U, 
    2623U, 2910U, 4056U, 140U, 2613U, 3995U, 1916U, 1923U, 
    821U, 1929U, 5611U, 5313U, 5105U, 5320U, 5688U, 5475U, 
    4870U, 5266U, 118U, 56U, 418U, 258U, 4760U, 87U, 
    28U, 108U, 47U, 623U, 496U, 722U, 586U, 427U, 
    266U, 633U, 505U, 732U, 595U, 436U, 274U, 4891U, 
    5254U, 5044U, 5741U, 3039U, 3205U, 445U, 282U, 388U, 
    231U, 5298U, 5536U, 5438U, 3047U, 3086U, 4786U, 5501U, 
    5519U, 3096U, 3142U, 4776U, 4860U, 4877U, 4943U, 5091U, 
    4884U, 4967U, 356U, 202U, 5629U, 5334U, 335U, 183U, 
    378U, 222U, 4851U, 3133U, 5173U, 3021U, 3158U, 3030U, 
    3056U, 3076U, 5205U, 5234U, 5732U, 398U, 240U, 5124U, 
    5035U, 5053U, 4976U, 4986U, 5223U, 4915U, 4996U, 5699U, 
    5006U, 5098U, 4970U, 4797U, 314U, 164U, 355U, 201U, 
    366U, 211U, 3150U, 5574U, 5362U, 5378U, 5417U, 5446U, 
    76U, 18U, 97U, 4737U, 37U, 5664U, 5428U, 324U, 
    173U, 654U, 524U, 5676U, 5457U, 688U, 555U, 604U, 
    479U, 3125U, 5583U, 3003U, 2985U, 3107U, 643U, 129U, 
    514U, 66U, 666U, 535U, 700U, 566U, 5646U, 5393U, 
    5593U, 5371U, 5565U, 5386U, 5545U, 5555U, 4806U, 4958U, 
    5722U, 4767U, 5467U, 1739U, 4240U, 5347U, 5071U, 5751U, 
    5710U, 5015U, 5133U, 5141U, 4950U, 5492U, 5510U, 345U, 
    192U, 5182U, 4815U, 5164U, 613U, 487U, 4824U, 4935U, 
    4898U, 3066U, 5214U, 4925U, 5244U, 5115U, 5287U, 4833U, 
    462U, 298U, 408U, 249U, 5277U, 4907U, 5148U, 5761U, 
    5620U, 5327U, 5637U, 5340U, 4751U, 5400U, 5409U, 3167U, 
    3012U, 2994U, 3116U, 677U, 545U, 711U, 576U, 5655U, 
    5528U, 5602U, 5306U, 4842U, 5061U, 5193U, 5080U, 5025U, 
    5353U, 3214U, 3185U, 3195U, 3175U, 5484U, 5156U, 5770U, 
};

static inline void InitXCoreMCInstrInfo(MCInstrInfo *II) {
  II->InitMCInstrInfo(XCoreDescs.Insts, XCoreInstrNameIndices, XCoreInstrNameData, nullptr, nullptr, 520);
}

} // end namespace llvm
#endif // GET_INSTRINFO_MC_DESC

#ifdef GET_INSTRINFO_HEADER
#undef GET_INSTRINFO_HEADER
namespace llvm {
struct XCoreGenInstrInfo : public TargetInstrInfo {
  explicit XCoreGenInstrInfo(unsigned CFSetupOpcode = ~0u, unsigned CFDestroyOpcode = ~0u, unsigned CatchRetOpcode = ~0u, unsigned ReturnOpcode = ~0u);
  ~XCoreGenInstrInfo() override = default;

};
} // end namespace llvm
#endif // GET_INSTRINFO_HEADER

#ifdef GET_INSTRINFO_HELPER_DECLS
#undef GET_INSTRINFO_HELPER_DECLS


#endif // GET_INSTRINFO_HELPER_DECLS

#ifdef GET_INSTRINFO_HELPERS
#undef GET_INSTRINFO_HELPERS

#endif // GET_INSTRINFO_HELPERS

#ifdef GET_INSTRINFO_CTOR_DTOR
#undef GET_INSTRINFO_CTOR_DTOR
namespace llvm {
extern const XCoreInstrTable XCoreDescs;
extern const unsigned XCoreInstrNameIndices[];
extern const char XCoreInstrNameData[];
XCoreGenInstrInfo::XCoreGenInstrInfo(unsigned CFSetupOpcode, unsigned CFDestroyOpcode, unsigned CatchRetOpcode, unsigned ReturnOpcode)
  : TargetInstrInfo(CFSetupOpcode, CFDestroyOpcode, CatchRetOpcode, ReturnOpcode) {
  InitMCInstrInfo(XCoreDescs.Insts, XCoreInstrNameIndices, XCoreInstrNameData, nullptr, nullptr, 520);
}
} // end namespace llvm
#endif // GET_INSTRINFO_CTOR_DTOR

#ifdef GET_INSTRINFO_OPERAND_ENUM
#undef GET_INSTRINFO_OPERAND_ENUM
namespace llvm {
namespace XCore {
namespace OpName {
enum {
  OPERAND_LAST
};
} // end namespace OpName
} // end namespace XCore
} // end namespace llvm
#endif //GET_INSTRINFO_OPERAND_ENUM

#ifdef GET_INSTRINFO_NAMED_OPS
#undef GET_INSTRINFO_NAMED_OPS
namespace llvm {
namespace XCore {
LLVM_READONLY
int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx) {
  return -1;
}
} // end namespace XCore
} // end namespace llvm
#endif //GET_INSTRINFO_NAMED_OPS

#ifdef GET_INSTRINFO_OPERAND_TYPES_ENUM
#undef GET_INSTRINFO_OPERAND_TYPES_ENUM
namespace llvm {
namespace XCore {
namespace OpTypes {
enum OperandType {
  InlineJT = 0,
  InlineJT32 = 1,
  MEMii = 2,
  brtarget = 3,
  brtarget_neg = 4,
  f32imm = 5,
  f64imm = 6,
  i1imm = 7,
  i8imm = 8,
  i16imm = 9,
  i32imm = 10,
  i64imm = 11,
  pcrel_imm = 12,
  pcrel_imm_neg = 13,
  ptype0 = 14,
  ptype1 = 15,
  ptype2 = 16,
  ptype3 = 17,
  ptype4 = 18,
  ptype5 = 19,
  type0 = 20,
  type1 = 21,
  type2 = 22,
  type3 = 23,
  type4 = 24,
  type5 = 25,
  untyped_imm_0 = 26,
  GRRegs = 27,
  RRegs = 28,
  OPERAND_TYPE_LIST_END
};
} // end namespace OpTypes
} // end namespace XCore
} // end namespace llvm
#endif // GET_INSTRINFO_OPERAND_TYPES_ENUM

#ifdef GET_INSTRINFO_OPERAND_TYPE
#undef GET_INSTRINFO_OPERAND_TYPE
namespace llvm {
namespace XCore {
LLVM_READONLY
static int getOperandType(uint16_t Opcode, uint16_t OpIdx) {
  static const uint16_t Offsets[] = {
    /* PHI */
    0,
    /* INLINEASM */
    1,
    /* INLINEASM_BR */
    1,
    /* CFI_INSTRUCTION */
    1,
    /* EH_LABEL */
    2,
    /* GC_LABEL */
    3,
    /* ANNOTATION_LABEL */
    4,
    /* KILL */
    5,
    /* EXTRACT_SUBREG */
    5,
    /* INSERT_SUBREG */
    8,
    /* IMPLICIT_DEF */
    12,
    /* SUBREG_TO_REG */
    13,
    /* COPY_TO_REGCLASS */
    17,
    /* DBG_VALUE */
    20,
    /* DBG_VALUE_LIST */
    20,
    /* DBG_INSTR_REF */
    20,
    /* DBG_PHI */
    20,
    /* DBG_LABEL */
    20,
    /* REG_SEQUENCE */
    21,
    /* COPY */
    23,
    /* BUNDLE */
    25,
    /* LIFETIME_START */
    25,
    /* LIFETIME_END */
    26,
    /* PSEUDO_PROBE */
    27,
    /* ARITH_FENCE */
    31,
    /* STACKMAP */
    33,
    /* FENTRY_CALL */
    35,
    /* PATCHPOINT */
    35,
    /* LOAD_STACK_GUARD */
    41,
    /* PREALLOCATED_SETUP */
    42,
    /* PREALLOCATED_ARG */
    43,
    /* STATEPOINT */
    46,
    /* LOCAL_ESCAPE */
    46,
    /* FAULTING_OP */
    48,
    /* PATCHABLE_OP */
    49,
    /* PATCHABLE_FUNCTION_ENTER */
    49,
    /* PATCHABLE_RET */
    49,
    /* PATCHABLE_FUNCTION_EXIT */
    49,
    /* PATCHABLE_TAIL_CALL */
    49,
    /* PATCHABLE_EVENT_CALL */
    49,
    /* PATCHABLE_TYPED_EVENT_CALL */
    51,
    /* ICALL_BRANCH_FUNNEL */
    54,
    /* FAKE_USE */
    54,
    /* MEMBARRIER */
    54,
    /* JUMP_TABLE_DEBUG_INFO */
    54,
    /* CONVERGENCECTRL_ENTRY */
    55,
    /* CONVERGENCECTRL_ANCHOR */
    56,
    /* CONVERGENCECTRL_LOOP */
    57,
    /* CONVERGENCECTRL_GLUE */
    59,
    /* G_ASSERT_SEXT */
    60,
    /* G_ASSERT_ZEXT */
    63,
    /* G_ASSERT_ALIGN */
    66,
    /* G_ADD */
    69,
    /* G_SUB */
    72,
    /* G_MUL */
    75,
    /* G_SDIV */
    78,
    /* G_UDIV */
    81,
    /* G_SREM */
    84,
    /* G_UREM */
    87,
    /* G_SDIVREM */
    90,
    /* G_UDIVREM */
    94,
    /* G_AND */
    98,
    /* G_OR */
    101,
    /* G_XOR */
    104,
    /* G_IMPLICIT_DEF */
    107,
    /* G_PHI */
    108,
    /* G_FRAME_INDEX */
    109,
    /* G_GLOBAL_VALUE */
    111,
    /* G_PTRAUTH_GLOBAL_VALUE */
    113,
    /* G_CONSTANT_POOL */
    118,
    /* G_EXTRACT */
    120,
    /* G_UNMERGE_VALUES */
    123,
    /* G_INSERT */
    125,
    /* G_MERGE_VALUES */
    129,
    /* G_BUILD_VECTOR */
    131,
    /* G_BUILD_VECTOR_TRUNC */
    133,
    /* G_CONCAT_VECTORS */
    135,
    /* G_PTRTOINT */
    137,
    /* G_INTTOPTR */
    139,
    /* G_BITCAST */
    141,
    /* G_FREEZE */
    143,
    /* G_CONSTANT_FOLD_BARRIER */
    145,
    /* G_INTRINSIC_FPTRUNC_ROUND */
    147,
    /* G_INTRINSIC_TRUNC */
    150,
    /* G_INTRINSIC_ROUND */
    152,
    /* G_INTRINSIC_LRINT */
    154,
    /* G_INTRINSIC_LLRINT */
    156,
    /* G_INTRINSIC_ROUNDEVEN */
    158,
    /* G_READCYCLECOUNTER */
    160,
    /* G_READSTEADYCOUNTER */
    161,
    /* G_LOAD */
    162,
    /* G_SEXTLOAD */
    164,
    /* G_ZEXTLOAD */
    166,
    /* G_INDEXED_LOAD */
    168,
    /* G_INDEXED_SEXTLOAD */
    173,
    /* G_INDEXED_ZEXTLOAD */
    178,
    /* G_STORE */
    183,
    /* G_INDEXED_STORE */
    185,
    /* G_ATOMIC_CMPXCHG_WITH_SUCCESS */
    190,
    /* G_ATOMIC_CMPXCHG */
    195,
    /* G_ATOMICRMW_XCHG */
    199,
    /* G_ATOMICRMW_ADD */
    202,
    /* G_ATOMICRMW_SUB */
    205,
    /* G_ATOMICRMW_AND */
    208,
    /* G_ATOMICRMW_NAND */
    211,
    /* G_ATOMICRMW_OR */
    214,
    /* G_ATOMICRMW_XOR */
    217,
    /* G_ATOMICRMW_MAX */
    220,
    /* G_ATOMICRMW_MIN */
    223,
    /* G_ATOMICRMW_UMAX */
    226,
    /* G_ATOMICRMW_UMIN */
    229,
    /* G_ATOMICRMW_FADD */
    232,
    /* G_ATOMICRMW_FSUB */
    235,
    /* G_ATOMICRMW_FMAX */
    238,
    /* G_ATOMICRMW_FMIN */
    241,
    /* G_ATOMICRMW_UINC_WRAP */
    244,
    /* G_ATOMICRMW_UDEC_WRAP */
    247,
    /* G_FENCE */
    250,
    /* G_PREFETCH */
    252,
    /* G_BRCOND */
    256,
    /* G_BRINDIRECT */
    258,
    /* G_INVOKE_REGION_START */
    259,
    /* G_INTRINSIC */
    259,
    /* G_INTRINSIC_W_SIDE_EFFECTS */
    260,
    /* G_INTRINSIC_CONVERGENT */
    261,
    /* G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS */
    262,
    /* G_ANYEXT */
    263,
    /* G_TRUNC */
    265,
    /* G_CONSTANT */
    267,
    /* G_FCONSTANT */
    269,
    /* G_VASTART */
    271,
    /* G_VAARG */
    272,
    /* G_SEXT */
    275,
    /* G_SEXT_INREG */
    277,
    /* G_ZEXT */
    280,
    /* G_SHL */
    282,
    /* G_LSHR */
    285,
    /* G_ASHR */
    288,
    /* G_FSHL */
    291,
    /* G_FSHR */
    295,
    /* G_ROTR */
    299,
    /* G_ROTL */
    302,
    /* G_ICMP */
    305,
    /* G_FCMP */
    309,
    /* G_SCMP */
    313,
    /* G_UCMP */
    316,
    /* G_SELECT */
    319,
    /* G_UADDO */
    323,
    /* G_UADDE */
    327,
    /* G_USUBO */
    332,
    /* G_USUBE */
    336,
    /* G_SADDO */
    341,
    /* G_SADDE */
    345,
    /* G_SSUBO */
    350,
    /* G_SSUBE */
    354,
    /* G_UMULO */
    359,
    /* G_SMULO */
    363,
    /* G_UMULH */
    367,
    /* G_SMULH */
    370,
    /* G_UADDSAT */
    373,
    /* G_SADDSAT */
    376,
    /* G_USUBSAT */
    379,
    /* G_SSUBSAT */
    382,
    /* G_USHLSAT */
    385,
    /* G_SSHLSAT */
    388,
    /* G_SMULFIX */
    391,
    /* G_UMULFIX */
    395,
    /* G_SMULFIXSAT */
    399,
    /* G_UMULFIXSAT */
    403,
    /* G_SDIVFIX */
    407,
    /* G_UDIVFIX */
    411,
    /* G_SDIVFIXSAT */
    415,
    /* G_UDIVFIXSAT */
    419,
    /* G_FADD */
    423,
    /* G_FSUB */
    426,
    /* G_FMUL */
    429,
    /* G_FMA */
    432,
    /* G_FMAD */
    436,
    /* G_FDIV */
    440,
    /* G_FREM */
    443,
    /* G_FPOW */
    446,
    /* G_FPOWI */
    449,
    /* G_FEXP */
    452,
    /* G_FEXP2 */
    454,
    /* G_FEXP10 */
    456,
    /* G_FLOG */
    458,
    /* G_FLOG2 */
    460,
    /* G_FLOG10 */
    462,
    /* G_FLDEXP */
    464,
    /* G_FFREXP */
    467,
    /* G_FNEG */
    470,
    /* G_FPEXT */
    472,
    /* G_FPTRUNC */
    474,
    /* G_FPTOSI */
    476,
    /* G_FPTOUI */
    478,
    /* G_SITOFP */
    480,
    /* G_UITOFP */
    482,
    /* G_FABS */
    484,
    /* G_FCOPYSIGN */
    486,
    /* G_IS_FPCLASS */
    489,
    /* G_FCANONICALIZE */
    492,
    /* G_FMINNUM */
    494,
    /* G_FMAXNUM */
    497,
    /* G_FMINNUM_IEEE */
    500,
    /* G_FMAXNUM_IEEE */
    503,
    /* G_FMINIMUM */
    506,
    /* G_FMAXIMUM */
    509,
    /* G_GET_FPENV */
    512,
    /* G_SET_FPENV */
    513,
    /* G_RESET_FPENV */
    514,
    /* G_GET_FPMODE */
    514,
    /* G_SET_FPMODE */
    515,
    /* G_RESET_FPMODE */
    516,
    /* G_PTR_ADD */
    516,
    /* G_PTRMASK */
    519,
    /* G_SMIN */
    522,
    /* G_SMAX */
    525,
    /* G_UMIN */
    528,
    /* G_UMAX */
    531,
    /* G_ABS */
    534,
    /* G_LROUND */
    536,
    /* G_LLROUND */
    538,
    /* G_BR */
    540,
    /* G_BRJT */
    541,
    /* G_VSCALE */
    544,
    /* G_INSERT_SUBVECTOR */
    546,
    /* G_EXTRACT_SUBVECTOR */
    550,
    /* G_INSERT_VECTOR_ELT */
    553,
    /* G_EXTRACT_VECTOR_ELT */
    557,
    /* G_SHUFFLE_VECTOR */
    560,
    /* G_SPLAT_VECTOR */
    564,
    /* G_VECTOR_COMPRESS */
    566,
    /* G_CTTZ */
    570,
    /* G_CTTZ_ZERO_UNDEF */
    572,
    /* G_CTLZ */
    574,
    /* G_CTLZ_ZERO_UNDEF */
    576,
    /* G_CTPOP */
    578,
    /* G_BSWAP */
    580,
    /* G_BITREVERSE */
    582,
    /* G_FCEIL */
    584,
    /* G_FCOS */
    586,
    /* G_FSIN */
    588,
    /* G_FTAN */
    590,
    /* G_FACOS */
    592,
    /* G_FASIN */
    594,
    /* G_FATAN */
    596,
    /* G_FCOSH */
    598,
    /* G_FSINH */
    600,
    /* G_FTANH */
    602,
    /* G_FSQRT */
    604,
    /* G_FFLOOR */
    606,
    /* G_FRINT */
    608,
    /* G_FNEARBYINT */
    610,
    /* G_ADDRSPACE_CAST */
    612,
    /* G_BLOCK_ADDR */
    614,
    /* G_JUMP_TABLE */
    616,
    /* G_DYN_STACKALLOC */
    618,
    /* G_STACKSAVE */
    621,
    /* G_STACKRESTORE */
    622,
    /* G_STRICT_FADD */
    623,
    /* G_STRICT_FSUB */
    626,
    /* G_STRICT_FMUL */
    629,
    /* G_STRICT_FDIV */
    632,
    /* G_STRICT_FREM */
    635,
    /* G_STRICT_FMA */
    638,
    /* G_STRICT_FSQRT */
    642,
    /* G_STRICT_FLDEXP */
    644,
    /* G_READ_REGISTER */
    647,
    /* G_WRITE_REGISTER */
    649,
    /* G_MEMCPY */
    651,
    /* G_MEMCPY_INLINE */
    655,
    /* G_MEMMOVE */
    658,
    /* G_MEMSET */
    662,
    /* G_BZERO */
    666,
    /* G_TRAP */
    669,
    /* G_DEBUGTRAP */
    669,
    /* G_UBSANTRAP */
    669,
    /* G_VECREDUCE_SEQ_FADD */
    670,
    /* G_VECREDUCE_SEQ_FMUL */
    673,
    /* G_VECREDUCE_FADD */
    676,
    /* G_VECREDUCE_FMUL */
    678,
    /* G_VECREDUCE_FMAX */
    680,
    /* G_VECREDUCE_FMIN */
    682,
    /* G_VECREDUCE_FMAXIMUM */
    684,
    /* G_VECREDUCE_FMINIMUM */
    686,
    /* G_VECREDUCE_ADD */
    688,
    /* G_VECREDUCE_MUL */
    690,
    /* G_VECREDUCE_AND */
    692,
    /* G_VECREDUCE_OR */
    694,
    /* G_VECREDUCE_XOR */
    696,
    /* G_VECREDUCE_SMAX */
    698,
    /* G_VECREDUCE_SMIN */
    700,
    /* G_VECREDUCE_UMAX */
    702,
    /* G_VECREDUCE_UMIN */
    704,
    /* G_SBFX */
    706,
    /* G_UBFX */
    710,
    /* ADJCALLSTACKDOWN */
    714,
    /* ADJCALLSTACKUP */
    716,
    /* BR_JT */
    718,
    /* BR_JT32 */
    720,
    /* EH_RETURN */
    722,
    /* FRAME_TO_ARGS_OFFSET */
    724,
    /* LDAWFI */
    725,
    /* LDWFI */
    728,
    /* SELECT_CC */
    731,
    /* STWFI */
    735,
    /* ADD_2rus */
    738,
    /* ADD_3r */
    741,
    /* ANDNOT_2r */
    744,
    /* AND_3r */
    747,
    /* ASHR_l2rus */
    750,
    /* ASHR_l3r */
    753,
    /* BAU_1r */
    756,
    /* BITREV_l2r */
    757,
    /* BLACP_lu10 */
    759,
    /* BLACP_u10 */
    760,
    /* BLAT_lu6 */
    761,
    /* BLAT_u6 */
    762,
    /* BLA_1r */
    763,
    /* BLRB_lu10 */
    764,
    /* BLRB_u10 */
    765,
    /* BLRF_lu10 */
    766,
    /* BLRF_u10 */
    767,
    /* BRBF_lru6 */
    768,
    /* BRBF_ru6 */
    770,
    /* BRBT_lru6 */
    772,
    /* BRBT_ru6 */
    774,
    /* BRBU_lu6 */
    776,
    /* BRBU_u6 */
    777,
    /* BRFF_lru6 */
    778,
    /* BRFF_ru6 */
    780,
    /* BRFT_lru6 */
    782,
    /* BRFT_ru6 */
    784,
    /* BRFU_lu6 */
    786,
    /* BRFU_u6 */
    787,
    /* BRU_1r */
    788,
    /* BYTEREV_l2r */
    789,
    /* CHKCT_2r */
    791,
    /* CHKCT_rus */
    793,
    /* CLRE_0R */
    795,
    /* CLRPT_1R */
    795,
    /* CLRSR_branch_lu6 */
    796,
    /* CLRSR_branch_u6 */
    797,
    /* CLRSR_lu6 */
    798,
    /* CLRSR_u6 */
    799,
    /* CLZ_l2r */
    800,
    /* CRC8_l4r */
    802,
    /* CRC_l3r */
    807,
    /* DCALL_0R */
    811,
    /* DENTSP_0R */
    811,
    /* DGETREG_1r */
    811,
    /* DIVS_l3r */
    812,
    /* DIVU_l3r */
    815,
    /* DRESTSP_0R */
    818,
    /* DRET_0R */
    818,
    /* ECALLF_1r */
    818,
    /* ECALLT_1r */
    819,
    /* EDU_1r */
    820,
    /* EEF_2r */
    821,
    /* EET_2r */
    823,
    /* EEU_1r */
    825,
    /* ENDIN_2r */
    826,
    /* ENTSP_lu6 */
    828,
    /* ENTSP_u6 */
    829,
    /* EQ_2rus */
    830,
    /* EQ_3r */
    833,
    /* EXTDP_lu6 */
    836,
    /* EXTDP_u6 */
    837,
    /* EXTSP_lu6 */
    838,
    /* EXTSP_u6 */
    839,
    /* FREER_1r */
    840,
    /* FREET_0R */
    841,
    /* GETD_l2r */
    841,
    /* GETED_0R */
    843,
    /* GETET_0R */
    843,
    /* GETID_0R */
    843,
    /* GETKEP_0R */
    843,
    /* GETKSP_0R */
    843,
    /* GETN_l2r */
    843,
    /* GETPS_l2r */
    845,
    /* GETR_rus */
    847,
    /* GETSR_lu6 */
    849,
    /* GETSR_u6 */
    850,
    /* GETST_2r */
    851,
    /* GETTS_2r */
    853,
    /* INCT_2r */
    855,
    /* INITCP_2r */
    857,
    /* INITDP_2r */
    859,
    /* INITLR_l2r */
    861,
    /* INITPC_2r */
    863,
    /* INITSP_2r */
    865,
    /* INPW_l2rus */
    867,
    /* INSHR_2r */
    870,
    /* INT_2r */
    873,
    /* IN_2r */
    875,
    /* KCALL_1r */
    877,
    /* KCALL_lu6 */
    878,
    /* KCALL_u6 */
    879,
    /* KENTSP_lu6 */
    880,
    /* KENTSP_u6 */
    881,
    /* KRESTSP_lu6 */
    882,
    /* KRESTSP_u6 */
    883,
    /* KRET_0R */
    884,
    /* LADD_l5r */
    884,
    /* LD16S_3r */
    889,
    /* LD8U_3r */
    892,
    /* LDA16B_l3r */
    895,
    /* LDA16F_l3r */
    898,
    /* LDAPB_lu10 */
    901,
    /* LDAPB_u10 */
    902,
    /* LDAPF_lu10 */
    903,
    /* LDAPF_lu10_ba */
    904,
    /* LDAPF_u10 */
    905,
    /* LDAWB_l2rus */
    906,
    /* LDAWB_l3r */
    909,
    /* LDAWCP_lu6 */
    912,
    /* LDAWCP_u6 */
    913,
    /* LDAWDP_lru6 */
    914,
    /* LDAWDP_ru6 */
    916,
    /* LDAWF_l2rus */
    918,
    /* LDAWF_l3r */
    921,
    /* LDAWSP_lru6 */
    924,
    /* LDAWSP_ru6 */
    926,
    /* LDC_lru6 */
    928,
    /* LDC_ru6 */
    930,
    /* LDET_0R */
    932,
    /* LDIVU_l5r */
    932,
    /* LDSED_0R */
    937,
    /* LDSPC_0R */
    937,
    /* LDSSR_0R */
    937,
    /* LDWCP_lru6 */
    937,
    /* LDWCP_lu10 */
    939,
    /* LDWCP_ru6 */
    940,
    /* LDWCP_u10 */
    942,
    /* LDWDP_lru6 */
    943,
    /* LDWDP_ru6 */
    945,
    /* LDWSP_lru6 */
    947,
    /* LDWSP_ru6 */
    949,
    /* LDW_2rus */
    951,
    /* LDW_3r */
    954,
    /* LMUL_l6r */
    957,
    /* LSS_3r */
    963,
    /* LSUB_l5r */
    966,
    /* LSU_3r */
    971,
    /* MACCS_l4r */
    974,
    /* MACCU_l4r */
    980,
    /* MJOIN_1r */
    986,
    /* MKMSK_2r */
    987,
    /* MKMSK_rus */
    989,
    /* MSYNC_1r */
    991,
    /* MUL_l3r */
    992,
    /* NEG */
    995,
    /* NOT */
    997,
    /* OR_3r */
    999,
    /* OUTCT_2r */
    1002,
    /* OUTCT_rus */
    1004,
    /* OUTPW_l2rus */
    1006,
    /* OUTSHR_2r */
    1009,
    /* OUTT_2r */
    1012,
    /* OUT_2r */
    1014,
    /* PEEK_2r */
    1016,
    /* REMS_l3r */
    1018,
    /* REMU_l3r */
    1021,
    /* RETSP_lu6 */
    1024,
    /* RETSP_u6 */
    1025,
    /* SETCLK_l2r */
    1026,
    /* SETCP_1r */
    1028,
    /* SETC_l2r */
    1029,
    /* SETC_lru6 */
    1031,
    /* SETC_ru6 */
    1033,
    /* SETDP_1r */
    1035,
    /* SETD_2r */
    1036,
    /* SETEV_1r */
    1038,
    /* SETKEP_0R */
    1039,
    /* SETN_l2r */
    1039,
    /* SETPSC_2r */
    1041,
    /* SETPS_l2r */
    1043,
    /* SETPT_2r */
    1045,
    /* SETRDY_l2r */
    1047,
    /* SETSP_1r */
    1049,
    /* SETSR_branch_lu6 */
    1050,
    /* SETSR_branch_u6 */
    1051,
    /* SETSR_lu6 */
    1052,
    /* SETSR_u6 */
    1053,
    /* SETTW_l2r */
    1054,
    /* SETV_1r */
    1056,
    /* SEXT_2r */
    1057,
    /* SEXT_rus */
    1060,
    /* SHL_2rus */
    1063,
    /* SHL_3r */
    1066,
    /* SHR_2rus */
    1069,
    /* SHR_3r */
    1072,
    /* SSYNC_0r */
    1075,
    /* ST16_l3r */
    1075,
    /* ST8_l3r */
    1078,
    /* STET_0R */
    1081,
    /* STSED_0R */
    1081,
    /* STSPC_0R */
    1081,
    /* STSSR_0R */
    1081,
    /* STWDP_lru6 */
    1081,
    /* STWDP_ru6 */
    1083,
    /* STWSP_lru6 */
    1085,
    /* STWSP_ru6 */
    1087,
    /* STW_2rus */
    1089,
    /* STW_l3r */
    1092,
    /* SUB_2rus */
    1095,
    /* SUB_3r */
    1098,
    /* SYNCR_1r */
    1101,
    /* TESTCT_2r */
    1102,
    /* TESTLCL_l2r */
    1104,
    /* TESTWCT_2r */
    1106,
    /* TSETMR_2r */
    1108,
    /* TSETR_3r */
    1110,
    /* TSTART_1R */
    1113,
    /* WAITEF_1R */
    1114,
    /* WAITET_1R */
    1115,
    /* WAITEU_0R */
    1116,
    /* XOR_l3r */
    1116,
    /* ZEXT_2r */
    1119,
    /* ZEXT_rus */
    1122,
  };

  using namespace OpTypes;
  static const int8_t OpcodeOperandTypes[] = {
    
    /* PHI */
    -1, 
    /* INLINEASM */
    /* INLINEASM_BR */
    /* CFI_INSTRUCTION */
    i32imm, 
    /* EH_LABEL */
    i32imm, 
    /* GC_LABEL */
    i32imm, 
    /* ANNOTATION_LABEL */
    i32imm, 
    /* KILL */
    /* EXTRACT_SUBREG */
    -1, -1, i32imm, 
    /* INSERT_SUBREG */
    -1, -1, -1, i32imm, 
    /* IMPLICIT_DEF */
    -1, 
    /* SUBREG_TO_REG */
    -1, -1, -1, i32imm, 
    /* COPY_TO_REGCLASS */
    -1, -1, i32imm, 
    /* DBG_VALUE */
    /* DBG_VALUE_LIST */
    /* DBG_INSTR_REF */
    /* DBG_PHI */
    /* DBG_LABEL */
    -1, 
    /* REG_SEQUENCE */
    -1, -1, 
    /* COPY */
    -1, -1, 
    /* BUNDLE */
    /* LIFETIME_START */
    i32imm, 
    /* LIFETIME_END */
    i32imm, 
    /* PSEUDO_PROBE */
    i64imm, i64imm, i8imm, i32imm, 
    /* ARITH_FENCE */
    -1, -1, 
    /* STACKMAP */
    i64imm, i32imm, 
    /* FENTRY_CALL */
    /* PATCHPOINT */
    -1, i64imm, i32imm, -1, i32imm, i32imm, 
    /* LOAD_STACK_GUARD */
    -1, 
    /* PREALLOCATED_SETUP */
    i32imm, 
    /* PREALLOCATED_ARG */
    -1, i32imm, i32imm, 
    /* STATEPOINT */
    /* LOCAL_ESCAPE */
    -1, i32imm, 
    /* FAULTING_OP */
    -1, 
    /* PATCHABLE_OP */
    /* PATCHABLE_FUNCTION_ENTER */
    /* PATCHABLE_RET */
    /* PATCHABLE_FUNCTION_EXIT */
    /* PATCHABLE_TAIL_CALL */
    /* PATCHABLE_EVENT_CALL */
    -1, -1, 
    /* PATCHABLE_TYPED_EVENT_CALL */
    -1, -1, -1, 
    /* ICALL_BRANCH_FUNNEL */
    /* FAKE_USE */
    /* MEMBARRIER */
    /* JUMP_TABLE_DEBUG_INFO */
    i64imm, 
    /* CONVERGENCECTRL_ENTRY */
    -1, 
    /* CONVERGENCECTRL_ANCHOR */
    -1, 
    /* CONVERGENCECTRL_LOOP */
    -1, -1, 
    /* CONVERGENCECTRL_GLUE */
    -1, 
    /* G_ASSERT_SEXT */
    type0, type0, untyped_imm_0, 
    /* G_ASSERT_ZEXT */
    type0, type0, untyped_imm_0, 
    /* G_ASSERT_ALIGN */
    type0, type0, untyped_imm_0, 
    /* G_ADD */
    type0, type0, type0, 
    /* G_SUB */
    type0, type0, type0, 
    /* G_MUL */
    type0, type0, type0, 
    /* G_SDIV */
    type0, type0, type0, 
    /* G_UDIV */
    type0, type0, type0, 
    /* G_SREM */
    type0, type0, type0, 
    /* G_UREM */
    type0, type0, type0, 
    /* G_SDIVREM */
    type0, type0, type0, type0, 
    /* G_UDIVREM */
    type0, type0, type0, type0, 
    /* G_AND */
    type0, type0, type0, 
    /* G_OR */
    type0, type0, type0, 
    /* G_XOR */
    type0, type0, type0, 
    /* G_IMPLICIT_DEF */
    type0, 
    /* G_PHI */
    type0, 
    /* G_FRAME_INDEX */
    type0, -1, 
    /* G_GLOBAL_VALUE */
    type0, -1, 
    /* G_PTRAUTH_GLOBAL_VALUE */
    type0, -1, i32imm, type1, i64imm, 
    /* G_CONSTANT_POOL */
    type0, -1, 
    /* G_EXTRACT */
    type0, type1, untyped_imm_0, 
    /* G_UNMERGE_VALUES */
    type0, type1, 
    /* G_INSERT */
    type0, type0, type1, untyped_imm_0, 
    /* G_MERGE_VALUES */
    type0, type1, 
    /* G_BUILD_VECTOR */
    type0, type1, 
    /* G_BUILD_VECTOR_TRUNC */
    type0, type1, 
    /* G_CONCAT_VECTORS */
    type0, type1, 
    /* G_PTRTOINT */
    type0, type1, 
    /* G_INTTOPTR */
    type0, type1, 
    /* G_BITCAST */
    type0, type1, 
    /* G_FREEZE */
    type0, type0, 
    /* G_CONSTANT_FOLD_BARRIER */
    type0, type0, 
    /* G_INTRINSIC_FPTRUNC_ROUND */
    type0, type1, i32imm, 
    /* G_INTRINSIC_TRUNC */
    type0, type0, 
    /* G_INTRINSIC_ROUND */
    type0, type0, 
    /* G_INTRINSIC_LRINT */
    type0, type1, 
    /* G_INTRINSIC_LLRINT */
    type0, type1, 
    /* G_INTRINSIC_ROUNDEVEN */
    type0, type0, 
    /* G_READCYCLECOUNTER */
    type0, 
    /* G_READSTEADYCOUNTER */
    type0, 
    /* G_LOAD */
    type0, ptype1, 
    /* G_SEXTLOAD */
    type0, ptype1, 
    /* G_ZEXTLOAD */
    type0, ptype1, 
    /* G_INDEXED_LOAD */
    type0, ptype1, ptype1, type2, -1, 
    /* G_INDEXED_SEXTLOAD */
    type0, ptype1, ptype1, type2, -1, 
    /* G_INDEXED_ZEXTLOAD */
    type0, ptype1, ptype1, type2, -1, 
    /* G_STORE */
    type0, ptype1, 
    /* G_INDEXED_STORE */
    ptype0, type1, ptype0, ptype2, -1, 
    /* G_ATOMIC_CMPXCHG_WITH_SUCCESS */
    type0, type1, type2, type0, type0, 
    /* G_ATOMIC_CMPXCHG */
    type0, ptype1, type0, type0, 
    /* G_ATOMICRMW_XCHG */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_ADD */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_SUB */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_AND */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_NAND */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_OR */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_XOR */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_MAX */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_MIN */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_UMAX */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_UMIN */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_FADD */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_FSUB */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_FMAX */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_FMIN */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_UINC_WRAP */
    type0, ptype1, type0, 
    /* G_ATOMICRMW_UDEC_WRAP */
    type0, ptype1, type0, 
    /* G_FENCE */
    i32imm, i32imm, 
    /* G_PREFETCH */
    ptype0, i32imm, i32imm, i32imm, 
    /* G_BRCOND */
    type0, -1, 
    /* G_BRINDIRECT */
    type0, 
    /* G_INVOKE_REGION_START */
    /* G_INTRINSIC */
    -1, 
    /* G_INTRINSIC_W_SIDE_EFFECTS */
    -1, 
    /* G_INTRINSIC_CONVERGENT */
    -1, 
    /* G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS */
    -1, 
    /* G_ANYEXT */
    type0, type1, 
    /* G_TRUNC */
    type0, type1, 
    /* G_CONSTANT */
    type0, -1, 
    /* G_FCONSTANT */
    type0, -1, 
    /* G_VASTART */
    type0, 
    /* G_VAARG */
    type0, type1, -1, 
    /* G_SEXT */
    type0, type1, 
    /* G_SEXT_INREG */
    type0, type0, untyped_imm_0, 
    /* G_ZEXT */
    type0, type1, 
    /* G_SHL */
    type0, type0, type1, 
    /* G_LSHR */
    type0, type0, type1, 
    /* G_ASHR */
    type0, type0, type1, 
    /* G_FSHL */
    type0, type0, type0, type1, 
    /* G_FSHR */
    type0, type0, type0, type1, 
    /* G_ROTR */
    type0, type0, type1, 
    /* G_ROTL */
    type0, type0, type1, 
    /* G_ICMP */
    type0, -1, type1, type1, 
    /* G_FCMP */
    type0, -1, type1, type1, 
    /* G_SCMP */
    type0, type1, type1, 
    /* G_UCMP */
    type0, type1, type1, 
    /* G_SELECT */
    type0, type1, type0, type0, 
    /* G_UADDO */
    type0, type1, type0, type0, 
    /* G_UADDE */
    type0, type1, type0, type0, type1, 
    /* G_USUBO */
    type0, type1, type0, type0, 
    /* G_USUBE */
    type0, type1, type0, type0, type1, 
    /* G_SADDO */
    type0, type1, type0, type0, 
    /* G_SADDE */
    type0, type1, type0, type0, type1, 
    /* G_SSUBO */
    type0, type1, type0, type0, 
    /* G_SSUBE */
    type0, type1, type0, type0, type1, 
    /* G_UMULO */
    type0, type1, type0, type0, 
    /* G_SMULO */
    type0, type1, type0, type0, 
    /* G_UMULH */
    type0, type0, type0, 
    /* G_SMULH */
    type0, type0, type0, 
    /* G_UADDSAT */
    type0, type0, type0, 
    /* G_SADDSAT */
    type0, type0, type0, 
    /* G_USUBSAT */
    type0, type0, type0, 
    /* G_SSUBSAT */
    type0, type0, type0, 
    /* G_USHLSAT */
    type0, type0, type1, 
    /* G_SSHLSAT */
    type0, type0, type1, 
    /* G_SMULFIX */
    type0, type0, type0, untyped_imm_0, 
    /* G_UMULFIX */
    type0, type0, type0, untyped_imm_0, 
    /* G_SMULFIXSAT */
    type0, type0, type0, untyped_imm_0, 
    /* G_UMULFIXSAT */
    type0, type0, type0, untyped_imm_0, 
    /* G_SDIVFIX */
    type0, type0, type0, untyped_imm_0, 
    /* G_UDIVFIX */
    type0, type0, type0, untyped_imm_0, 
    /* G_SDIVFIXSAT */
    type0, type0, type0, untyped_imm_0, 
    /* G_UDIVFIXSAT */
    type0, type0, type0, untyped_imm_0, 
    /* G_FADD */
    type0, type0, type0, 
    /* G_FSUB */
    type0, type0, type0, 
    /* G_FMUL */
    type0, type0, type0, 
    /* G_FMA */
    type0, type0, type0, type0, 
    /* G_FMAD */
    type0, type0, type0, type0, 
    /* G_FDIV */
    type0, type0, type0, 
    /* G_FREM */
    type0, type0, type0, 
    /* G_FPOW */
    type0, type0, type0, 
    /* G_FPOWI */
    type0, type0, type1, 
    /* G_FEXP */
    type0, type0, 
    /* G_FEXP2 */
    type0, type0, 
    /* G_FEXP10 */
    type0, type0, 
    /* G_FLOG */
    type0, type0, 
    /* G_FLOG2 */
    type0, type0, 
    /* G_FLOG10 */
    type0, type0, 
    /* G_FLDEXP */
    type0, type0, type1, 
    /* G_FFREXP */
    type0, type1, type0, 
    /* G_FNEG */
    type0, type0, 
    /* G_FPEXT */
    type0, type1, 
    /* G_FPTRUNC */
    type0, type1, 
    /* G_FPTOSI */
    type0, type1, 
    /* G_FPTOUI */
    type0, type1, 
    /* G_SITOFP */
    type0, type1, 
    /* G_UITOFP */
    type0, type1, 
    /* G_FABS */
    type0, type0, 
    /* G_FCOPYSIGN */
    type0, type0, type1, 
    /* G_IS_FPCLASS */
    type0, type1, -1, 
    /* G_FCANONICALIZE */
    type0, type0, 
    /* G_FMINNUM */
    type0, type0, type0, 
    /* G_FMAXNUM */
    type0, type0, type0, 
    /* G_FMINNUM_IEEE */
    type0, type0, type0, 
    /* G_FMAXNUM_IEEE */
    type0, type0, type0, 
    /* G_FMINIMUM */
    type0, type0, type0, 
    /* G_FMAXIMUM */
    type0, type0, type0, 
    /* G_GET_FPENV */
    type0, 
    /* G_SET_FPENV */
    type0, 
    /* G_RESET_FPENV */
    /* G_GET_FPMODE */
    type0, 
    /* G_SET_FPMODE */
    type0, 
    /* G_RESET_FPMODE */
    /* G_PTR_ADD */
    ptype0, ptype0, type1, 
    /* G_PTRMASK */
    ptype0, ptype0, type1, 
    /* G_SMIN */
    type0, type0, type0, 
    /* G_SMAX */
    type0, type0, type0, 
    /* G_UMIN */
    type0, type0, type0, 
    /* G_UMAX */
    type0, type0, type0, 
    /* G_ABS */
    type0, type0, 
    /* G_LROUND */
    type0, type1, 
    /* G_LLROUND */
    type0, type1, 
    /* G_BR */
    -1, 
    /* G_BRJT */
    ptype0, -1, type1, 
    /* G_VSCALE */
    type0, -1, 
    /* G_INSERT_SUBVECTOR */
    type0, type0, type1, untyped_imm_0, 
    /* G_EXTRACT_SUBVECTOR */
    type0, type0, untyped_imm_0, 
    /* G_INSERT_VECTOR_ELT */
    type0, type0, type1, type2, 
    /* G_EXTRACT_VECTOR_ELT */
    type0, type1, type2, 
    /* G_SHUFFLE_VECTOR */
    type0, type1, type1, -1, 
    /* G_SPLAT_VECTOR */
    type0, type1, 
    /* G_VECTOR_COMPRESS */
    type0, type0, type1, type0, 
    /* G_CTTZ */
    type0, type1, 
    /* G_CTTZ_ZERO_UNDEF */
    type0, type1, 
    /* G_CTLZ */
    type0, type1, 
    /* G_CTLZ_ZERO_UNDEF */
    type0, type1, 
    /* G_CTPOP */
    type0, type1, 
    /* G_BSWAP */
    type0, type0, 
    /* G_BITREVERSE */
    type0, type0, 
    /* G_FCEIL */
    type0, type0, 
    /* G_FCOS */
    type0, type0, 
    /* G_FSIN */
    type0, type0, 
    /* G_FTAN */
    type0, type0, 
    /* G_FACOS */
    type0, type0, 
    /* G_FASIN */
    type0, type0, 
    /* G_FATAN */
    type0, type0, 
    /* G_FCOSH */
    type0, type0, 
    /* G_FSINH */
    type0, type0, 
    /* G_FTANH */
    type0, type0, 
    /* G_FSQRT */
    type0, type0, 
    /* G_FFLOOR */
    type0, type0, 
    /* G_FRINT */
    type0, type0, 
    /* G_FNEARBYINT */
    type0, type0, 
    /* G_ADDRSPACE_CAST */
    type0, type1, 
    /* G_BLOCK_ADDR */
    type0, -1, 
    /* G_JUMP_TABLE */
    type0, -1, 
    /* G_DYN_STACKALLOC */
    ptype0, type1, i32imm, 
    /* G_STACKSAVE */
    ptype0, 
    /* G_STACKRESTORE */
    ptype0, 
    /* G_STRICT_FADD */
    type0, type0, type0, 
    /* G_STRICT_FSUB */
    type0, type0, type0, 
    /* G_STRICT_FMUL */
    type0, type0, type0, 
    /* G_STRICT_FDIV */
    type0, type0, type0, 
    /* G_STRICT_FREM */
    type0, type0, type0, 
    /* G_STRICT_FMA */
    type0, type0, type0, type0, 
    /* G_STRICT_FSQRT */
    type0, type0, 
    /* G_STRICT_FLDEXP */
    type0, type0, type1, 
    /* G_READ_REGISTER */
    type0, -1, 
    /* G_WRITE_REGISTER */
    -1, type0, 
    /* G_MEMCPY */
    ptype0, ptype1, type2, untyped_imm_0, 
    /* G_MEMCPY_INLINE */
    ptype0, ptype1, type2, 
    /* G_MEMMOVE */
    ptype0, ptype1, type2, untyped_imm_0, 
    /* G_MEMSET */
    ptype0, type1, type2, untyped_imm_0, 
    /* G_BZERO */
    ptype0, type1, untyped_imm_0, 
    /* G_TRAP */
    /* G_DEBUGTRAP */
    /* G_UBSANTRAP */
    i8imm, 
    /* G_VECREDUCE_SEQ_FADD */
    type0, type1, type2, 
    /* G_VECREDUCE_SEQ_FMUL */
    type0, type1, type2, 
    /* G_VECREDUCE_FADD */
    type0, type1, 
    /* G_VECREDUCE_FMUL */
    type0, type1, 
    /* G_VECREDUCE_FMAX */
    type0, type1, 
    /* G_VECREDUCE_FMIN */
    type0, type1, 
    /* G_VECREDUCE_FMAXIMUM */
    type0, type1, 
    /* G_VECREDUCE_FMINIMUM */
    type0, type1, 
    /* G_VECREDUCE_ADD */
    type0, type1, 
    /* G_VECREDUCE_MUL */
    type0, type1, 
    /* G_VECREDUCE_AND */
    type0, type1, 
    /* G_VECREDUCE_OR */
    type0, type1, 
    /* G_VECREDUCE_XOR */
    type0, type1, 
    /* G_VECREDUCE_SMAX */
    type0, type1, 
    /* G_VECREDUCE_SMIN */
    type0, type1, 
    /* G_VECREDUCE_UMAX */
    type0, type1, 
    /* G_VECREDUCE_UMIN */
    type0, type1, 
    /* G_SBFX */
    type0, type0, type1, type1, 
    /* G_UBFX */
    type0, type0, type1, type1, 
    /* ADJCALLSTACKDOWN */
    i32imm, i32imm, 
    /* ADJCALLSTACKUP */
    i32imm, i32imm, 
    /* BR_JT */
    InlineJT, GRRegs, 
    /* BR_JT32 */
    InlineJT32, GRRegs, 
    /* EH_RETURN */
    GRRegs, GRRegs, 
    /* FRAME_TO_ARGS_OFFSET */
    GRRegs, 
    /* LDAWFI */
    GRRegs, i32imm, i32imm, 
    /* LDWFI */
    GRRegs, i32imm, i32imm, 
    /* SELECT_CC */
    GRRegs, GRRegs, GRRegs, GRRegs, 
    /* STWFI */
    GRRegs, i32imm, i32imm, 
    /* ADD_2rus */
    GRRegs, GRRegs, i32imm, 
    /* ADD_3r */
    GRRegs, GRRegs, GRRegs, 
    /* ANDNOT_2r */
    GRRegs, GRRegs, GRRegs, 
    /* AND_3r */
    GRRegs, GRRegs, GRRegs, 
    /* ASHR_l2rus */
    GRRegs, GRRegs, i32imm, 
    /* ASHR_l3r */
    GRRegs, GRRegs, GRRegs, 
    /* BAU_1r */
    GRRegs, 
    /* BITREV_l2r */
    GRRegs, GRRegs, 
    /* BLACP_lu10 */
    i32imm, 
    /* BLACP_u10 */
    i32imm, 
    /* BLAT_lu6 */
    i32imm, 
    /* BLAT_u6 */
    i32imm, 
    /* BLA_1r */
    GRRegs, 
    /* BLRB_lu10 */
    pcrel_imm_neg, 
    /* BLRB_u10 */
    pcrel_imm_neg, 
    /* BLRF_lu10 */
    pcrel_imm, 
    /* BLRF_u10 */
    pcrel_imm, 
    /* BRBF_lru6 */
    GRRegs, brtarget_neg, 
    /* BRBF_ru6 */
    GRRegs, brtarget_neg, 
    /* BRBT_lru6 */
    GRRegs, brtarget_neg, 
    /* BRBT_ru6 */
    GRRegs, brtarget_neg, 
    /* BRBU_lu6 */
    brtarget_neg, 
    /* BRBU_u6 */
    brtarget_neg, 
    /* BRFF_lru6 */
    GRRegs, brtarget, 
    /* BRFF_ru6 */
    GRRegs, brtarget, 
    /* BRFT_lru6 */
    GRRegs, brtarget, 
    /* BRFT_ru6 */
    GRRegs, brtarget, 
    /* BRFU_lu6 */
    brtarget, 
    /* BRFU_u6 */
    brtarget, 
    /* BRU_1r */
    GRRegs, 
    /* BYTEREV_l2r */
    GRRegs, GRRegs, 
    /* CHKCT_2r */
    GRRegs, GRRegs, 
    /* CHKCT_rus */
    GRRegs, i32imm, 
    /* CLRE_0R */
    /* CLRPT_1R */
    GRRegs, 
    /* CLRSR_branch_lu6 */
    i32imm, 
    /* CLRSR_branch_u6 */
    i32imm, 
    /* CLRSR_lu6 */
    i32imm, 
    /* CLRSR_u6 */
    i32imm, 
    /* CLZ_l2r */
    GRRegs, GRRegs, 
    /* CRC8_l4r */
    GRRegs, GRRegs, GRRegs, GRRegs, GRRegs, 
    /* CRC_l3r */
    GRRegs, GRRegs, GRRegs, GRRegs, 
    /* DCALL_0R */
    /* DENTSP_0R */
    /* DGETREG_1r */
    GRRegs, 
    /* DIVS_l3r */
    GRRegs, GRRegs, GRRegs, 
    /* DIVU_l3r */
    GRRegs, GRRegs, GRRegs, 
    /* DRESTSP_0R */
    /* DRET_0R */
    /* ECALLF_1r */
    GRRegs, 
    /* ECALLT_1r */
    GRRegs, 
    /* EDU_1r */
    GRRegs, 
    /* EEF_2r */
    GRRegs, GRRegs, 
    /* EET_2r */
    GRRegs, GRRegs, 
    /* EEU_1r */
    GRRegs, 
    /* ENDIN_2r */
    GRRegs, GRRegs, 
    /* ENTSP_lu6 */
    i32imm, 
    /* ENTSP_u6 */
    i32imm, 
    /* EQ_2rus */
    GRRegs, GRRegs, i32imm, 
    /* EQ_3r */
    GRRegs, GRRegs, GRRegs, 
    /* EXTDP_lu6 */
    i32imm, 
    /* EXTDP_u6 */
    i32imm, 
    /* EXTSP_lu6 */
    i32imm, 
    /* EXTSP_u6 */
    i32imm, 
    /* FREER_1r */
    GRRegs, 
    /* FREET_0R */
    /* GETD_l2r */
    GRRegs, GRRegs, 
    /* GETED_0R */
    /* GETET_0R */
    /* GETID_0R */
    /* GETKEP_0R */
    /* GETKSP_0R */
    /* GETN_l2r */
    GRRegs, GRRegs, 
    /* GETPS_l2r */
    GRRegs, GRRegs, 
    /* GETR_rus */
    GRRegs, i32imm, 
    /* GETSR_lu6 */
    i32imm, 
    /* GETSR_u6 */
    i32imm, 
    /* GETST_2r */
    GRRegs, GRRegs, 
    /* GETTS_2r */
    GRRegs, GRRegs, 
    /* INCT_2r */
    GRRegs, GRRegs, 
    /* INITCP_2r */
    GRRegs, GRRegs, 
    /* INITDP_2r */
    GRRegs, GRRegs, 
    /* INITLR_l2r */
    GRRegs, GRRegs, 
    /* INITPC_2r */
    GRRegs, GRRegs, 
    /* INITSP_2r */
    GRRegs, GRRegs, 
    /* INPW_l2rus */
    GRRegs, GRRegs, i32imm, 
    /* INSHR_2r */
    GRRegs, GRRegs, GRRegs, 
    /* INT_2r */
    GRRegs, GRRegs, 
    /* IN_2r */
    GRRegs, GRRegs, 
    /* KCALL_1r */
    GRRegs, 
    /* KCALL_lu6 */
    i32imm, 
    /* KCALL_u6 */
    i32imm, 
    /* KENTSP_lu6 */
    i32imm, 
    /* KENTSP_u6 */
    i32imm, 
    /* KRESTSP_lu6 */
    i32imm, 
    /* KRESTSP_u6 */
    i32imm, 
    /* KRET_0R */
    /* LADD_l5r */
    GRRegs, GRRegs, GRRegs, GRRegs, GRRegs, 
    /* LD16S_3r */
    GRRegs, GRRegs, GRRegs, 
    /* LD8U_3r */
    GRRegs, GRRegs, GRRegs, 
    /* LDA16B_l3r */
    GRRegs, GRRegs, GRRegs, 
    /* LDA16F_l3r */
    GRRegs, GRRegs, GRRegs, 
    /* LDAPB_lu10 */
    pcrel_imm_neg, 
    /* LDAPB_u10 */
    pcrel_imm_neg, 
    /* LDAPF_lu10 */
    pcrel_imm, 
    /* LDAPF_lu10_ba */
    pcrel_imm, 
    /* LDAPF_u10 */
    pcrel_imm, 
    /* LDAWB_l2rus */
    GRRegs, GRRegs, i32imm, 
    /* LDAWB_l3r */
    GRRegs, GRRegs, GRRegs, 
    /* LDAWCP_lu6 */
    i32imm, 
    /* LDAWCP_u6 */
    i32imm, 
    /* LDAWDP_lru6 */
    RRegs, i32imm, 
    /* LDAWDP_ru6 */
    RRegs, i32imm, 
    /* LDAWF_l2rus */
    GRRegs, GRRegs, i32imm, 
    /* LDAWF_l3r */
    GRRegs, GRRegs, GRRegs, 
    /* LDAWSP_lru6 */
    RRegs, i32imm, 
    /* LDAWSP_ru6 */
    RRegs, i32imm, 
    /* LDC_lru6 */
    RRegs, i32imm, 
    /* LDC_ru6 */
    RRegs, i32imm, 
    /* LDET_0R */
    /* LDIVU_l5r */
    GRRegs, GRRegs, GRRegs, GRRegs, GRRegs, 
    /* LDSED_0R */
    /* LDSPC_0R */
    /* LDSSR_0R */
    /* LDWCP_lru6 */
    RRegs, i32imm, 
    /* LDWCP_lu10 */
    i32imm, 
    /* LDWCP_ru6 */
    RRegs, i32imm, 
    /* LDWCP_u10 */
    i32imm, 
    /* LDWDP_lru6 */
    RRegs, i32imm, 
    /* LDWDP_ru6 */
    RRegs, i32imm, 
    /* LDWSP_lru6 */
    RRegs, i32imm, 
    /* LDWSP_ru6 */
    RRegs, i32imm, 
    /* LDW_2rus */
    GRRegs, GRRegs, i32imm, 
    /* LDW_3r */
    GRRegs, GRRegs, GRRegs, 
    /* LMUL_l6r */
    GRRegs, GRRegs, GRRegs, GRRegs, GRRegs, GRRegs, 
    /* LSS_3r */
    GRRegs, GRRegs, GRRegs, 
    /* LSUB_l5r */
    GRRegs, GRRegs, GRRegs, GRRegs, GRRegs, 
    /* LSU_3r */
    GRRegs, GRRegs, GRRegs, 
    /* MACCS_l4r */
    GRRegs, GRRegs, GRRegs, GRRegs, GRRegs, GRRegs, 
    /* MACCU_l4r */
    GRRegs, GRRegs, GRRegs, GRRegs, GRRegs, GRRegs, 
    /* MJOIN_1r */
    GRRegs, 
    /* MKMSK_2r */
    GRRegs, GRRegs, 
    /* MKMSK_rus */
    GRRegs, i32imm, 
    /* MSYNC_1r */
    GRRegs, 
    /* MUL_l3r */
    GRRegs, GRRegs, GRRegs, 
    /* NEG */
    GRRegs, GRRegs, 
    /* NOT */
    GRRegs, GRRegs, 
    /* OR_3r */
    GRRegs, GRRegs, GRRegs, 
    /* OUTCT_2r */
    GRRegs, GRRegs, 
    /* OUTCT_rus */
    GRRegs, i32imm, 
    /* OUTPW_l2rus */
    GRRegs, GRRegs, i32imm, 
    /* OUTSHR_2r */
    GRRegs, GRRegs, GRRegs, 
    /* OUTT_2r */
    GRRegs, GRRegs, 
    /* OUT_2r */
    GRRegs, GRRegs, 
    /* PEEK_2r */
    GRRegs, GRRegs, 
    /* REMS_l3r */
    GRRegs, GRRegs, GRRegs, 
    /* REMU_l3r */
    GRRegs, GRRegs, GRRegs, 
    /* RETSP_lu6 */
    i32imm, 
    /* RETSP_u6 */
    i32imm, 
    /* SETCLK_l2r */
    GRRegs, GRRegs, 
    /* SETCP_1r */
    GRRegs, 
    /* SETC_l2r */
    GRRegs, GRRegs, 
    /* SETC_lru6 */
    GRRegs, i32imm, 
    /* SETC_ru6 */
    GRRegs, i32imm, 
    /* SETDP_1r */
    GRRegs, 
    /* SETD_2r */
    GRRegs, GRRegs, 
    /* SETEV_1r */
    GRRegs, 
    /* SETKEP_0R */
    /* SETN_l2r */
    GRRegs, GRRegs, 
    /* SETPSC_2r */
    GRRegs, GRRegs, 
    /* SETPS_l2r */
    GRRegs, GRRegs, 
    /* SETPT_2r */
    GRRegs, GRRegs, 
    /* SETRDY_l2r */
    GRRegs, GRRegs, 
    /* SETSP_1r */
    GRRegs, 
    /* SETSR_branch_lu6 */
    i32imm, 
    /* SETSR_branch_u6 */
    i32imm, 
    /* SETSR_lu6 */
    i32imm, 
    /* SETSR_u6 */
    i32imm, 
    /* SETTW_l2r */
    GRRegs, GRRegs, 
    /* SETV_1r */
    GRRegs, 
    /* SEXT_2r */
    GRRegs, GRRegs, GRRegs, 
    /* SEXT_rus */
    GRRegs, GRRegs, i32imm, 
    /* SHL_2rus */
    GRRegs, GRRegs, i32imm, 
    /* SHL_3r */
    GRRegs, GRRegs, GRRegs, 
    /* SHR_2rus */
    GRRegs, GRRegs, i32imm, 
    /* SHR_3r */
    GRRegs, GRRegs, GRRegs, 
    /* SSYNC_0r */
    /* ST16_l3r */
    GRRegs, GRRegs, GRRegs, 
    /* ST8_l3r */
    GRRegs, GRRegs, GRRegs, 
    /* STET_0R */
    /* STSED_0R */
    /* STSPC_0R */
    /* STSSR_0R */
    /* STWDP_lru6 */
    RRegs, i32imm, 
    /* STWDP_ru6 */
    RRegs, i32imm, 
    /* STWSP_lru6 */
    RRegs, i32imm, 
    /* STWSP_ru6 */
    RRegs, i32imm, 
    /* STW_2rus */
    GRRegs, GRRegs, i32imm, 
    /* STW_l3r */
    GRRegs, GRRegs, GRRegs, 
    /* SUB_2rus */
    GRRegs, GRRegs, i32imm, 
    /* SUB_3r */
    GRRegs, GRRegs, GRRegs, 
    /* SYNCR_1r */
    GRRegs, 
    /* TESTCT_2r */
    GRRegs, GRRegs, 
    /* TESTLCL_l2r */
    GRRegs, GRRegs, 
    /* TESTWCT_2r */
    GRRegs, GRRegs, 
    /* TSETMR_2r */
    i32imm, GRRegs, 
    /* TSETR_3r */
    i32imm, GRRegs, GRRegs, 
    /* TSTART_1R */
    GRRegs, 
    /* WAITEF_1R */
    GRRegs, 
    /* WAITET_1R */
    GRRegs, 
    /* WAITEU_0R */
    /* XOR_l3r */
    GRRegs, GRRegs, GRRegs, 
    /* ZEXT_2r */
    GRRegs, GRRegs, GRRegs, 
    /* ZEXT_rus */
    GRRegs, GRRegs, i32imm, 
  };
  return OpcodeOperandTypes[Offsets[Opcode] + OpIdx];
}
} // end namespace XCore
} // end namespace llvm
#endif // GET_INSTRINFO_OPERAND_TYPE

#ifdef GET_INSTRINFO_MEM_OPERAND_SIZE
#undef GET_INSTRINFO_MEM_OPERAND_SIZE
namespace llvm {
namespace XCore {
LLVM_READONLY
static int getMemOperandSize(int OpType) {
  switch (OpType) {
  default: return 0;
  }
}
} // end namespace XCore
} // end namespace llvm
#endif // GET_INSTRINFO_MEM_OPERAND_SIZE

#ifdef GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP
#undef GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP
namespace llvm {
namespace XCore {
LLVM_READONLY static unsigned
getLogicalOperandSize(uint16_t Opcode, uint16_t LogicalOpIdx) {
  return LogicalOpIdx;
}
LLVM_READONLY static inline unsigned
getLogicalOperandIdx(uint16_t Opcode, uint16_t LogicalOpIdx) {
  auto S = 0U;
  for (auto i = 0U; i < LogicalOpIdx; ++i)
    S += getLogicalOperandSize(Opcode, i);
  return S;
}
} // end namespace XCore
} // end namespace llvm
#endif // GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP

#ifdef GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP
#undef GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP
namespace llvm {
namespace XCore {
LLVM_READONLY static int
getLogicalOperandType(uint16_t Opcode, uint16_t LogicalOpIdx) {
  return -1;
}
} // end namespace XCore
} // end namespace llvm
#endif // GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP

#ifdef GET_INSTRINFO_MC_HELPER_DECLS
#undef GET_INSTRINFO_MC_HELPER_DECLS

namespace llvm {
class MCInst;
class FeatureBitset;

namespace XCore_MC {

void verifyInstructionPredicates(unsigned Opcode, const FeatureBitset &Features);

} // end namespace XCore_MC
} // end namespace llvm

#endif // GET_INSTRINFO_MC_HELPER_DECLS

#ifdef GET_INSTRINFO_MC_HELPERS
#undef GET_INSTRINFO_MC_HELPERS

namespace llvm {
namespace XCore_MC {

} // end namespace XCore_MC
} // end namespace llvm

#endif // GET_GENISTRINFO_MC_HELPERS

#if (defined(ENABLE_INSTR_PREDICATE_VERIFIER) && !defined(NDEBUG)) ||\
    defined(GET_AVAILABLE_OPCODE_CHECKER)
#define GET_COMPUTE_FEATURES
#endif
#ifdef GET_COMPUTE_FEATURES
#undef GET_COMPUTE_FEATURES
namespace llvm {
namespace XCore_MC {

// Bits for subtarget features that participate in instruction matching.
enum SubtargetFeatureBits : uint8_t {
};

inline FeatureBitset computeAvailableFeatures(const FeatureBitset &FB) {
  FeatureBitset Features;
  return Features;
}

inline FeatureBitset computeRequiredFeatures(unsigned Opcode) {
  enum : uint8_t {
    CEFBS_None,
  };

  static constexpr FeatureBitset FeatureBitsets[] = {
    {}, // CEFBS_None
  };
  static constexpr uint8_t RequiredFeaturesRefs[] = {
    CEFBS_None, // PHI = 0
    CEFBS_None, // INLINEASM = 1
    CEFBS_None, // INLINEASM_BR = 2
    CEFBS_None, // CFI_INSTRUCTION = 3
    CEFBS_None, // EH_LABEL = 4
    CEFBS_None, // GC_LABEL = 5
    CEFBS_None, // ANNOTATION_LABEL = 6
    CEFBS_None, // KILL = 7
    CEFBS_None, // EXTRACT_SUBREG = 8
    CEFBS_None, // INSERT_SUBREG = 9
    CEFBS_None, // IMPLICIT_DEF = 10
    CEFBS_None, // SUBREG_TO_REG = 11
    CEFBS_None, // COPY_TO_REGCLASS = 12
    CEFBS_None, // DBG_VALUE = 13
    CEFBS_None, // DBG_VALUE_LIST = 14
    CEFBS_None, // DBG_INSTR_REF = 15
    CEFBS_None, // DBG_PHI = 16
    CEFBS_None, // DBG_LABEL = 17
    CEFBS_None, // REG_SEQUENCE = 18
    CEFBS_None, // COPY = 19
    CEFBS_None, // BUNDLE = 20
    CEFBS_None, // LIFETIME_START = 21
    CEFBS_None, // LIFETIME_END = 22
    CEFBS_None, // PSEUDO_PROBE = 23
    CEFBS_None, // ARITH_FENCE = 24
    CEFBS_None, // STACKMAP = 25
    CEFBS_None, // FENTRY_CALL = 26
    CEFBS_None, // PATCHPOINT = 27
    CEFBS_None, // LOAD_STACK_GUARD = 28
    CEFBS_None, // PREALLOCATED_SETUP = 29
    CEFBS_None, // PREALLOCATED_ARG = 30
    CEFBS_None, // STATEPOINT = 31
    CEFBS_None, // LOCAL_ESCAPE = 32
    CEFBS_None, // FAULTING_OP = 33
    CEFBS_None, // PATCHABLE_OP = 34
    CEFBS_None, // PATCHABLE_FUNCTION_ENTER = 35
    CEFBS_None, // PATCHABLE_RET = 36
    CEFBS_None, // PATCHABLE_FUNCTION_EXIT = 37
    CEFBS_None, // PATCHABLE_TAIL_CALL = 38
    CEFBS_None, // PATCHABLE_EVENT_CALL = 39
    CEFBS_None, // PATCHABLE_TYPED_EVENT_CALL = 40
    CEFBS_None, // ICALL_BRANCH_FUNNEL = 41
    CEFBS_None, // FAKE_USE = 42
    CEFBS_None, // MEMBARRIER = 43
    CEFBS_None, // JUMP_TABLE_DEBUG_INFO = 44
    CEFBS_None, // CONVERGENCECTRL_ENTRY = 45
    CEFBS_None, // CONVERGENCECTRL_ANCHOR = 46
    CEFBS_None, // CONVERGENCECTRL_LOOP = 47
    CEFBS_None, // CONVERGENCECTRL_GLUE = 48
    CEFBS_None, // G_ASSERT_SEXT = 49
    CEFBS_None, // G_ASSERT_ZEXT = 50
    CEFBS_None, // G_ASSERT_ALIGN = 51
    CEFBS_None, // G_ADD = 52
    CEFBS_None, // G_SUB = 53
    CEFBS_None, // G_MUL = 54
    CEFBS_None, // G_SDIV = 55
    CEFBS_None, // G_UDIV = 56
    CEFBS_None, // G_SREM = 57
    CEFBS_None, // G_UREM = 58
    CEFBS_None, // G_SDIVREM = 59
    CEFBS_None, // G_UDIVREM = 60
    CEFBS_None, // G_AND = 61
    CEFBS_None, // G_OR = 62
    CEFBS_None, // G_XOR = 63
    CEFBS_None, // G_IMPLICIT_DEF = 64
    CEFBS_None, // G_PHI = 65
    CEFBS_None, // G_FRAME_INDEX = 66
    CEFBS_None, // G_GLOBAL_VALUE = 67
    CEFBS_None, // G_PTRAUTH_GLOBAL_VALUE = 68
    CEFBS_None, // G_CONSTANT_POOL = 69
    CEFBS_None, // G_EXTRACT = 70
    CEFBS_None, // G_UNMERGE_VALUES = 71
    CEFBS_None, // G_INSERT = 72
    CEFBS_None, // G_MERGE_VALUES = 73
    CEFBS_None, // G_BUILD_VECTOR = 74
    CEFBS_None, // G_BUILD_VECTOR_TRUNC = 75
    CEFBS_None, // G_CONCAT_VECTORS = 76
    CEFBS_None, // G_PTRTOINT = 77
    CEFBS_None, // G_INTTOPTR = 78
    CEFBS_None, // G_BITCAST = 79
    CEFBS_None, // G_FREEZE = 80
    CEFBS_None, // G_CONSTANT_FOLD_BARRIER = 81
    CEFBS_None, // G_INTRINSIC_FPTRUNC_ROUND = 82
    CEFBS_None, // G_INTRINSIC_TRUNC = 83
    CEFBS_None, // G_INTRINSIC_ROUND = 84
    CEFBS_None, // G_INTRINSIC_LRINT = 85
    CEFBS_None, // G_INTRINSIC_LLRINT = 86
    CEFBS_None, // G_INTRINSIC_ROUNDEVEN = 87
    CEFBS_None, // G_READCYCLECOUNTER = 88
    CEFBS_None, // G_READSTEADYCOUNTER = 89
    CEFBS_None, // G_LOAD = 90
    CEFBS_None, // G_SEXTLOAD = 91
    CEFBS_None, // G_ZEXTLOAD = 92
    CEFBS_None, // G_INDEXED_LOAD = 93
    CEFBS_None, // G_INDEXED_SEXTLOAD = 94
    CEFBS_None, // G_INDEXED_ZEXTLOAD = 95
    CEFBS_None, // G_STORE = 96
    CEFBS_None, // G_INDEXED_STORE = 97
    CEFBS_None, // G_ATOMIC_CMPXCHG_WITH_SUCCESS = 98
    CEFBS_None, // G_ATOMIC_CMPXCHG = 99
    CEFBS_None, // G_ATOMICRMW_XCHG = 100
    CEFBS_None, // G_ATOMICRMW_ADD = 101
    CEFBS_None, // G_ATOMICRMW_SUB = 102
    CEFBS_None, // G_ATOMICRMW_AND = 103
    CEFBS_None, // G_ATOMICRMW_NAND = 104
    CEFBS_None, // G_ATOMICRMW_OR = 105
    CEFBS_None, // G_ATOMICRMW_XOR = 106
    CEFBS_None, // G_ATOMICRMW_MAX = 107
    CEFBS_None, // G_ATOMICRMW_MIN = 108
    CEFBS_None, // G_ATOMICRMW_UMAX = 109
    CEFBS_None, // G_ATOMICRMW_UMIN = 110
    CEFBS_None, // G_ATOMICRMW_FADD = 111
    CEFBS_None, // G_ATOMICRMW_FSUB = 112
    CEFBS_None, // G_ATOMICRMW_FMAX = 113
    CEFBS_None, // G_ATOMICRMW_FMIN = 114
    CEFBS_None, // G_ATOMICRMW_UINC_WRAP = 115
    CEFBS_None, // G_ATOMICRMW_UDEC_WRAP = 116
    CEFBS_None, // G_FENCE = 117
    CEFBS_None, // G_PREFETCH = 118
    CEFBS_None, // G_BRCOND = 119
    CEFBS_None, // G_BRINDIRECT = 120
    CEFBS_None, // G_INVOKE_REGION_START = 121
    CEFBS_None, // G_INTRINSIC = 122
    CEFBS_None, // G_INTRINSIC_W_SIDE_EFFECTS = 123
    CEFBS_None, // G_INTRINSIC_CONVERGENT = 124
    CEFBS_None, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS = 125
    CEFBS_None, // G_ANYEXT = 126
    CEFBS_None, // G_TRUNC = 127
    CEFBS_None, // G_CONSTANT = 128
    CEFBS_None, // G_FCONSTANT = 129
    CEFBS_None, // G_VASTART = 130
    CEFBS_None, // G_VAARG = 131
    CEFBS_None, // G_SEXT = 132
    CEFBS_None, // G_SEXT_INREG = 133
    CEFBS_None, // G_ZEXT = 134
    CEFBS_None, // G_SHL = 135
    CEFBS_None, // G_LSHR = 136
    CEFBS_None, // G_ASHR = 137
    CEFBS_None, // G_FSHL = 138
    CEFBS_None, // G_FSHR = 139
    CEFBS_None, // G_ROTR = 140
    CEFBS_None, // G_ROTL = 141
    CEFBS_None, // G_ICMP = 142
    CEFBS_None, // G_FCMP = 143
    CEFBS_None, // G_SCMP = 144
    CEFBS_None, // G_UCMP = 145
    CEFBS_None, // G_SELECT = 146
    CEFBS_None, // G_UADDO = 147
    CEFBS_None, // G_UADDE = 148
    CEFBS_None, // G_USUBO = 149
    CEFBS_None, // G_USUBE = 150
    CEFBS_None, // G_SADDO = 151
    CEFBS_None, // G_SADDE = 152
    CEFBS_None, // G_SSUBO = 153
    CEFBS_None, // G_SSUBE = 154
    CEFBS_None, // G_UMULO = 155
    CEFBS_None, // G_SMULO = 156
    CEFBS_None, // G_UMULH = 157
    CEFBS_None, // G_SMULH = 158
    CEFBS_None, // G_UADDSAT = 159
    CEFBS_None, // G_SADDSAT = 160
    CEFBS_None, // G_USUBSAT = 161
    CEFBS_None, // G_SSUBSAT = 162
    CEFBS_None, // G_USHLSAT = 163
    CEFBS_None, // G_SSHLSAT = 164
    CEFBS_None, // G_SMULFIX = 165
    CEFBS_None, // G_UMULFIX = 166
    CEFBS_None, // G_SMULFIXSAT = 167
    CEFBS_None, // G_UMULFIXSAT = 168
    CEFBS_None, // G_SDIVFIX = 169
    CEFBS_None, // G_UDIVFIX = 170
    CEFBS_None, // G_SDIVFIXSAT = 171
    CEFBS_None, // G_UDIVFIXSAT = 172
    CEFBS_None, // G_FADD = 173
    CEFBS_None, // G_FSUB = 174
    CEFBS_None, // G_FMUL = 175
    CEFBS_None, // G_FMA = 176
    CEFBS_None, // G_FMAD = 177
    CEFBS_None, // G_FDIV = 178
    CEFBS_None, // G_FREM = 179
    CEFBS_None, // G_FPOW = 180
    CEFBS_None, // G_FPOWI = 181
    CEFBS_None, // G_FEXP = 182
    CEFBS_None, // G_FEXP2 = 183
    CEFBS_None, // G_FEXP10 = 184
    CEFBS_None, // G_FLOG = 185
    CEFBS_None, // G_FLOG2 = 186
    CEFBS_None, // G_FLOG10 = 187
    CEFBS_None, // G_FLDEXP = 188
    CEFBS_None, // G_FFREXP = 189
    CEFBS_None, // G_FNEG = 190
    CEFBS_None, // G_FPEXT = 191
    CEFBS_None, // G_FPTRUNC = 192
    CEFBS_None, // G_FPTOSI = 193
    CEFBS_None, // G_FPTOUI = 194
    CEFBS_None, // G_SITOFP = 195
    CEFBS_None, // G_UITOFP = 196
    CEFBS_None, // G_FABS = 197
    CEFBS_None, // G_FCOPYSIGN = 198
    CEFBS_None, // G_IS_FPCLASS = 199
    CEFBS_None, // G_FCANONICALIZE = 200
    CEFBS_None, // G_FMINNUM = 201
    CEFBS_None, // G_FMAXNUM = 202
    CEFBS_None, // G_FMINNUM_IEEE = 203
    CEFBS_None, // G_FMAXNUM_IEEE = 204
    CEFBS_None, // G_FMINIMUM = 205
    CEFBS_None, // G_FMAXIMUM = 206
    CEFBS_None, // G_GET_FPENV = 207
    CEFBS_None, // G_SET_FPENV = 208
    CEFBS_None, // G_RESET_FPENV = 209
    CEFBS_None, // G_GET_FPMODE = 210
    CEFBS_None, // G_SET_FPMODE = 211
    CEFBS_None, // G_RESET_FPMODE = 212
    CEFBS_None, // G_PTR_ADD = 213
    CEFBS_None, // G_PTRMASK = 214
    CEFBS_None, // G_SMIN = 215
    CEFBS_None, // G_SMAX = 216
    CEFBS_None, // G_UMIN = 217
    CEFBS_None, // G_UMAX = 218
    CEFBS_None, // G_ABS = 219
    CEFBS_None, // G_LROUND = 220
    CEFBS_None, // G_LLROUND = 221
    CEFBS_None, // G_BR = 222
    CEFBS_None, // G_BRJT = 223
    CEFBS_None, // G_VSCALE = 224
    CEFBS_None, // G_INSERT_SUBVECTOR = 225
    CEFBS_None, // G_EXTRACT_SUBVECTOR = 226
    CEFBS_None, // G_INSERT_VECTOR_ELT = 227
    CEFBS_None, // G_EXTRACT_VECTOR_ELT = 228
    CEFBS_None, // G_SHUFFLE_VECTOR = 229
    CEFBS_None, // G_SPLAT_VECTOR = 230
    CEFBS_None, // G_VECTOR_COMPRESS = 231
    CEFBS_None, // G_CTTZ = 232
    CEFBS_None, // G_CTTZ_ZERO_UNDEF = 233
    CEFBS_None, // G_CTLZ = 234
    CEFBS_None, // G_CTLZ_ZERO_UNDEF = 235
    CEFBS_None, // G_CTPOP = 236
    CEFBS_None, // G_BSWAP = 237
    CEFBS_None, // G_BITREVERSE = 238
    CEFBS_None, // G_FCEIL = 239
    CEFBS_None, // G_FCOS = 240
    CEFBS_None, // G_FSIN = 241
    CEFBS_None, // G_FTAN = 242
    CEFBS_None, // G_FACOS = 243
    CEFBS_None, // G_FASIN = 244
    CEFBS_None, // G_FATAN = 245
    CEFBS_None, // G_FCOSH = 246
    CEFBS_None, // G_FSINH = 247
    CEFBS_None, // G_FTANH = 248
    CEFBS_None, // G_FSQRT = 249
    CEFBS_None, // G_FFLOOR = 250
    CEFBS_None, // G_FRINT = 251
    CEFBS_None, // G_FNEARBYINT = 252
    CEFBS_None, // G_ADDRSPACE_CAST = 253
    CEFBS_None, // G_BLOCK_ADDR = 254
    CEFBS_None, // G_JUMP_TABLE = 255
    CEFBS_None, // G_DYN_STACKALLOC = 256
    CEFBS_None, // G_STACKSAVE = 257
    CEFBS_None, // G_STACKRESTORE = 258
    CEFBS_None, // G_STRICT_FADD = 259
    CEFBS_None, // G_STRICT_FSUB = 260
    CEFBS_None, // G_STRICT_FMUL = 261
    CEFBS_None, // G_STRICT_FDIV = 262
    CEFBS_None, // G_STRICT_FREM = 263
    CEFBS_None, // G_STRICT_FMA = 264
    CEFBS_None, // G_STRICT_FSQRT = 265
    CEFBS_None, // G_STRICT_FLDEXP = 266
    CEFBS_None, // G_READ_REGISTER = 267
    CEFBS_None, // G_WRITE_REGISTER = 268
    CEFBS_None, // G_MEMCPY = 269
    CEFBS_None, // G_MEMCPY_INLINE = 270
    CEFBS_None, // G_MEMMOVE = 271
    CEFBS_None, // G_MEMSET = 272
    CEFBS_None, // G_BZERO = 273
    CEFBS_None, // G_TRAP = 274
    CEFBS_None, // G_DEBUGTRAP = 275
    CEFBS_None, // G_UBSANTRAP = 276
    CEFBS_None, // G_VECREDUCE_SEQ_FADD = 277
    CEFBS_None, // G_VECREDUCE_SEQ_FMUL = 278
    CEFBS_None, // G_VECREDUCE_FADD = 279
    CEFBS_None, // G_VECREDUCE_FMUL = 280
    CEFBS_None, // G_VECREDUCE_FMAX = 281
    CEFBS_None, // G_VECREDUCE_FMIN = 282
    CEFBS_None, // G_VECREDUCE_FMAXIMUM = 283
    CEFBS_None, // G_VECREDUCE_FMINIMUM = 284
    CEFBS_None, // G_VECREDUCE_ADD = 285
    CEFBS_None, // G_VECREDUCE_MUL = 286
    CEFBS_None, // G_VECREDUCE_AND = 287
    CEFBS_None, // G_VECREDUCE_OR = 288
    CEFBS_None, // G_VECREDUCE_XOR = 289
    CEFBS_None, // G_VECREDUCE_SMAX = 290
    CEFBS_None, // G_VECREDUCE_SMIN = 291
    CEFBS_None, // G_VECREDUCE_UMAX = 292
    CEFBS_None, // G_VECREDUCE_UMIN = 293
    CEFBS_None, // G_SBFX = 294
    CEFBS_None, // G_UBFX = 295
    CEFBS_None, // ADJCALLSTACKDOWN = 296
    CEFBS_None, // ADJCALLSTACKUP = 297
    CEFBS_None, // BR_JT = 298
    CEFBS_None, // BR_JT32 = 299
    CEFBS_None, // EH_RETURN = 300
    CEFBS_None, // FRAME_TO_ARGS_OFFSET = 301
    CEFBS_None, // LDAWFI = 302
    CEFBS_None, // LDWFI = 303
    CEFBS_None, // SELECT_CC = 304
    CEFBS_None, // STWFI = 305
    CEFBS_None, // ADD_2rus = 306
    CEFBS_None, // ADD_3r = 307
    CEFBS_None, // ANDNOT_2r = 308
    CEFBS_None, // AND_3r = 309
    CEFBS_None, // ASHR_l2rus = 310
    CEFBS_None, // ASHR_l3r = 311
    CEFBS_None, // BAU_1r = 312
    CEFBS_None, // BITREV_l2r = 313
    CEFBS_None, // BLACP_lu10 = 314
    CEFBS_None, // BLACP_u10 = 315
    CEFBS_None, // BLAT_lu6 = 316
    CEFBS_None, // BLAT_u6 = 317
    CEFBS_None, // BLA_1r = 318
    CEFBS_None, // BLRB_lu10 = 319
    CEFBS_None, // BLRB_u10 = 320
    CEFBS_None, // BLRF_lu10 = 321
    CEFBS_None, // BLRF_u10 = 322
    CEFBS_None, // BRBF_lru6 = 323
    CEFBS_None, // BRBF_ru6 = 324
    CEFBS_None, // BRBT_lru6 = 325
    CEFBS_None, // BRBT_ru6 = 326
    CEFBS_None, // BRBU_lu6 = 327
    CEFBS_None, // BRBU_u6 = 328
    CEFBS_None, // BRFF_lru6 = 329
    CEFBS_None, // BRFF_ru6 = 330
    CEFBS_None, // BRFT_lru6 = 331
    CEFBS_None, // BRFT_ru6 = 332
    CEFBS_None, // BRFU_lu6 = 333
    CEFBS_None, // BRFU_u6 = 334
    CEFBS_None, // BRU_1r = 335
    CEFBS_None, // BYTEREV_l2r = 336
    CEFBS_None, // CHKCT_2r = 337
    CEFBS_None, // CHKCT_rus = 338
    CEFBS_None, // CLRE_0R = 339
    CEFBS_None, // CLRPT_1R = 340
    CEFBS_None, // CLRSR_branch_lu6 = 341
    CEFBS_None, // CLRSR_branch_u6 = 342
    CEFBS_None, // CLRSR_lu6 = 343
    CEFBS_None, // CLRSR_u6 = 344
    CEFBS_None, // CLZ_l2r = 345
    CEFBS_None, // CRC8_l4r = 346
    CEFBS_None, // CRC_l3r = 347
    CEFBS_None, // DCALL_0R = 348
    CEFBS_None, // DENTSP_0R = 349
    CEFBS_None, // DGETREG_1r = 350
    CEFBS_None, // DIVS_l3r = 351
    CEFBS_None, // DIVU_l3r = 352
    CEFBS_None, // DRESTSP_0R = 353
    CEFBS_None, // DRET_0R = 354
    CEFBS_None, // ECALLF_1r = 355
    CEFBS_None, // ECALLT_1r = 356
    CEFBS_None, // EDU_1r = 357
    CEFBS_None, // EEF_2r = 358
    CEFBS_None, // EET_2r = 359
    CEFBS_None, // EEU_1r = 360
    CEFBS_None, // ENDIN_2r = 361
    CEFBS_None, // ENTSP_lu6 = 362
    CEFBS_None, // ENTSP_u6 = 363
    CEFBS_None, // EQ_2rus = 364
    CEFBS_None, // EQ_3r = 365
    CEFBS_None, // EXTDP_lu6 = 366
    CEFBS_None, // EXTDP_u6 = 367
    CEFBS_None, // EXTSP_lu6 = 368
    CEFBS_None, // EXTSP_u6 = 369
    CEFBS_None, // FREER_1r = 370
    CEFBS_None, // FREET_0R = 371
    CEFBS_None, // GETD_l2r = 372
    CEFBS_None, // GETED_0R = 373
    CEFBS_None, // GETET_0R = 374
    CEFBS_None, // GETID_0R = 375
    CEFBS_None, // GETKEP_0R = 376
    CEFBS_None, // GETKSP_0R = 377
    CEFBS_None, // GETN_l2r = 378
    CEFBS_None, // GETPS_l2r = 379
    CEFBS_None, // GETR_rus = 380
    CEFBS_None, // GETSR_lu6 = 381
    CEFBS_None, // GETSR_u6 = 382
    CEFBS_None, // GETST_2r = 383
    CEFBS_None, // GETTS_2r = 384
    CEFBS_None, // INCT_2r = 385
    CEFBS_None, // INITCP_2r = 386
    CEFBS_None, // INITDP_2r = 387
    CEFBS_None, // INITLR_l2r = 388
    CEFBS_None, // INITPC_2r = 389
    CEFBS_None, // INITSP_2r = 390
    CEFBS_None, // INPW_l2rus = 391
    CEFBS_None, // INSHR_2r = 392
    CEFBS_None, // INT_2r = 393
    CEFBS_None, // IN_2r = 394
    CEFBS_None, // KCALL_1r = 395
    CEFBS_None, // KCALL_lu6 = 396
    CEFBS_None, // KCALL_u6 = 397
    CEFBS_None, // KENTSP_lu6 = 398
    CEFBS_None, // KENTSP_u6 = 399
    CEFBS_None, // KRESTSP_lu6 = 400
    CEFBS_None, // KRESTSP_u6 = 401
    CEFBS_None, // KRET_0R = 402
    CEFBS_None, // LADD_l5r = 403
    CEFBS_None, // LD16S_3r = 404
    CEFBS_None, // LD8U_3r = 405
    CEFBS_None, // LDA16B_l3r = 406
    CEFBS_None, // LDA16F_l3r = 407
    CEFBS_None, // LDAPB_lu10 = 408
    CEFBS_None, // LDAPB_u10 = 409
    CEFBS_None, // LDAPF_lu10 = 410
    CEFBS_None, // LDAPF_lu10_ba = 411
    CEFBS_None, // LDAPF_u10 = 412
    CEFBS_None, // LDAWB_l2rus = 413
    CEFBS_None, // LDAWB_l3r = 414
    CEFBS_None, // LDAWCP_lu6 = 415
    CEFBS_None, // LDAWCP_u6 = 416
    CEFBS_None, // LDAWDP_lru6 = 417
    CEFBS_None, // LDAWDP_ru6 = 418
    CEFBS_None, // LDAWF_l2rus = 419
    CEFBS_None, // LDAWF_l3r = 420
    CEFBS_None, // LDAWSP_lru6 = 421
    CEFBS_None, // LDAWSP_ru6 = 422
    CEFBS_None, // LDC_lru6 = 423
    CEFBS_None, // LDC_ru6 = 424
    CEFBS_None, // LDET_0R = 425
    CEFBS_None, // LDIVU_l5r = 426
    CEFBS_None, // LDSED_0R = 427
    CEFBS_None, // LDSPC_0R = 428
    CEFBS_None, // LDSSR_0R = 429
    CEFBS_None, // LDWCP_lru6 = 430
    CEFBS_None, // LDWCP_lu10 = 431
    CEFBS_None, // LDWCP_ru6 = 432
    CEFBS_None, // LDWCP_u10 = 433
    CEFBS_None, // LDWDP_lru6 = 434
    CEFBS_None, // LDWDP_ru6 = 435
    CEFBS_None, // LDWSP_lru6 = 436
    CEFBS_None, // LDWSP_ru6 = 437
    CEFBS_None, // LDW_2rus = 438
    CEFBS_None, // LDW_3r = 439
    CEFBS_None, // LMUL_l6r = 440
    CEFBS_None, // LSS_3r = 441
    CEFBS_None, // LSUB_l5r = 442
    CEFBS_None, // LSU_3r = 443
    CEFBS_None, // MACCS_l4r = 444
    CEFBS_None, // MACCU_l4r = 445
    CEFBS_None, // MJOIN_1r = 446
    CEFBS_None, // MKMSK_2r = 447
    CEFBS_None, // MKMSK_rus = 448
    CEFBS_None, // MSYNC_1r = 449
    CEFBS_None, // MUL_l3r = 450
    CEFBS_None, // NEG = 451
    CEFBS_None, // NOT = 452
    CEFBS_None, // OR_3r = 453
    CEFBS_None, // OUTCT_2r = 454
    CEFBS_None, // OUTCT_rus = 455
    CEFBS_None, // OUTPW_l2rus = 456
    CEFBS_None, // OUTSHR_2r = 457
    CEFBS_None, // OUTT_2r = 458
    CEFBS_None, // OUT_2r = 459
    CEFBS_None, // PEEK_2r = 460
    CEFBS_None, // REMS_l3r = 461
    CEFBS_None, // REMU_l3r = 462
    CEFBS_None, // RETSP_lu6 = 463
    CEFBS_None, // RETSP_u6 = 464
    CEFBS_None, // SETCLK_l2r = 465
    CEFBS_None, // SETCP_1r = 466
    CEFBS_None, // SETC_l2r = 467
    CEFBS_None, // SETC_lru6 = 468
    CEFBS_None, // SETC_ru6 = 469
    CEFBS_None, // SETDP_1r = 470
    CEFBS_None, // SETD_2r = 471
    CEFBS_None, // SETEV_1r = 472
    CEFBS_None, // SETKEP_0R = 473
    CEFBS_None, // SETN_l2r = 474
    CEFBS_None, // SETPSC_2r = 475
    CEFBS_None, // SETPS_l2r = 476
    CEFBS_None, // SETPT_2r = 477
    CEFBS_None, // SETRDY_l2r = 478
    CEFBS_None, // SETSP_1r = 479
    CEFBS_None, // SETSR_branch_lu6 = 480
    CEFBS_None, // SETSR_branch_u6 = 481
    CEFBS_None, // SETSR_lu6 = 482
    CEFBS_None, // SETSR_u6 = 483
    CEFBS_None, // SETTW_l2r = 484
    CEFBS_None, // SETV_1r = 485
    CEFBS_None, // SEXT_2r = 486
    CEFBS_None, // SEXT_rus = 487
    CEFBS_None, // SHL_2rus = 488
    CEFBS_None, // SHL_3r = 489
    CEFBS_None, // SHR_2rus = 490
    CEFBS_None, // SHR_3r = 491
    CEFBS_None, // SSYNC_0r = 492
    CEFBS_None, // ST16_l3r = 493
    CEFBS_None, // ST8_l3r = 494
    CEFBS_None, // STET_0R = 495
    CEFBS_None, // STSED_0R = 496
    CEFBS_None, // STSPC_0R = 497
    CEFBS_None, // STSSR_0R = 498
    CEFBS_None, // STWDP_lru6 = 499
    CEFBS_None, // STWDP_ru6 = 500
    CEFBS_None, // STWSP_lru6 = 501
    CEFBS_None, // STWSP_ru6 = 502
    CEFBS_None, // STW_2rus = 503
    CEFBS_None, // STW_l3r = 504
    CEFBS_None, // SUB_2rus = 505
    CEFBS_None, // SUB_3r = 506
    CEFBS_None, // SYNCR_1r = 507
    CEFBS_None, // TESTCT_2r = 508
    CEFBS_None, // TESTLCL_l2r = 509
    CEFBS_None, // TESTWCT_2r = 510
    CEFBS_None, // TSETMR_2r = 511
    CEFBS_None, // TSETR_3r = 512
    CEFBS_None, // TSTART_1R = 513
    CEFBS_None, // WAITEF_1R = 514
    CEFBS_None, // WAITET_1R = 515
    CEFBS_None, // WAITEU_0R = 516
    CEFBS_None, // XOR_l3r = 517
    CEFBS_None, // ZEXT_2r = 518
    CEFBS_None, // ZEXT_rus = 519
  };

  assert(Opcode < 520);
  return FeatureBitsets[RequiredFeaturesRefs[Opcode]];
}

} // end namespace XCore_MC
} // end namespace llvm
#endif // GET_COMPUTE_FEATURES

#ifdef GET_AVAILABLE_OPCODE_CHECKER
#undef GET_AVAILABLE_OPCODE_CHECKER
namespace llvm {
namespace XCore_MC {
bool isOpcodeAvailable(unsigned Opcode, const FeatureBitset &Features) {
  FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
  FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
  FeatureBitset MissingFeatures =
      (AvailableFeatures & RequiredFeatures) ^
      RequiredFeatures;
  return !MissingFeatures.any();
}
} // end namespace XCore_MC
} // end namespace llvm
#endif // GET_AVAILABLE_OPCODE_CHECKER

#ifdef ENABLE_INSTR_PREDICATE_VERIFIER
#undef ENABLE_INSTR_PREDICATE_VERIFIER
#include <sstream>

namespace llvm {
namespace XCore_MC {

#ifndef NDEBUG
static const char *SubtargetFeatureNames[] = {
  nullptr
};

#endif // NDEBUG

void verifyInstructionPredicates(
    unsigned Opcode, const FeatureBitset &Features) {
#ifndef NDEBUG
  FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
  FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
  FeatureBitset MissingFeatures =
      (AvailableFeatures & RequiredFeatures) ^
      RequiredFeatures;
  if (MissingFeatures.any()) {
    std::ostringstream Msg;
    Msg << "Attempting to emit " << &XCoreInstrNameData[XCoreInstrNameIndices[Opcode]]
        << " instruction but the ";
    for (unsigned i = 0, e = MissingFeatures.size(); i != e; ++i)
      if (MissingFeatures.test(i))
        Msg << SubtargetFeatureNames[i] << " ";
    Msg << "predicate(s) are not met";
    report_fatal_error(Msg.str().c_str());
  }
#endif // NDEBUG
}
} // end namespace XCore_MC
} // end namespace llvm
#endif // ENABLE_INSTR_PREDICATE_VERIFIER