llvm/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp

//===- RISCVTargetDefEmitter.cpp - Generate lists of RISC-V CPUs ----------===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
// This tablegen backend emits the include file needed by RISCVTargetParser.cpp
// and RISCVISAInfo.cpp to parse the RISC-V CPUs and extensions.
//
//===----------------------------------------------------------------------===//

#include "llvm/ADT/DenseSet.h"
#include "llvm/Support/RISCVISAUtils.h"
#include "llvm/TableGen/Record.h"
#include "llvm/TableGen/TableGenBackend.h"

usingnamespacellvm;

static StringRef getExtensionName(const Record *R) { … }

static void printExtensionTable(raw_ostream &OS,
                                const std::vector<Record *> &Extensions,
                                bool Experimental) { … }

static void emitRISCVExtensions(RecordKeeper &Records, raw_ostream &OS) { … }

// We can generate march string from target features as what has been described
// in RISC-V ISA specification (version 20191213) 'Chapter 27. ISA Extension
// Naming Conventions'.
//
// This is almost the same as RISCVFeatures::parseFeatureBits, except that we
// get feature name from feature records instead of feature bits.
static void printMArch(raw_ostream &OS, const std::vector<Record *> &Features) { … }

static void printProfileTable(raw_ostream &OS,
                              const std::vector<Record *> &Profiles,
                              bool Experimental) { … }

static void emitRISCVProfiles(RecordKeeper &Records, raw_ostream &OS) { … }

static void emitRISCVProcs(RecordKeeper &RK, raw_ostream &OS) { … }

static void emitRISCVExtensionBitmask(RecordKeeper &RK, raw_ostream &OS) { … }

static void EmitRISCVTargetDef(RecordKeeper &RK, raw_ostream &OS) { … }

static TableGen::Emitter::Opt X("gen-riscv-target-def", EmitRISCVTargetDef,
                                "Generate the list of CPUs and extensions for "
                                "RISC-V");