llvm/llvm/test/CodeGen/AMDGPU/frame-lowering-entry-all-sgpr-used.mir

# RUN: llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs -run-pass=prologepilog %s -o - | FileCheck %s

# CHECK-LABEL: all_sgpr_used
# CHECK: V_CMP_LT_U32_e64
--- |
  define amdgpu_kernel void @all_sgpr_used() #0 {
    ret void
  }
  attributes #0 = { "amdgpu-num-sgpr"="8" "frame-pointer"="all"}
...
---
name:            all_sgpr_used
tracksRegLiveness: true
liveins:         
  - { reg: '$vgpr0' }
  - { reg: '$vgpr1' }
  - { reg: '$vgpr2' }
  - { reg: '$sgpr4_sgpr5' }
  - { reg: '$sgpr6_sgpr7' }
  - { reg: '$sgpr8' }
  - { reg: '$sgpr9' }
machineFunctionInfo: 
  explicitKernArgSize: 84
  maxKernArgAlign: 8
  ldsSize:         20496
  isEntryFunction: true
  waveLimiter:     true
  scratchRSrcReg:  '$sgpr96_sgpr97_sgpr98_sgpr99'
  frameOffsetReg:  '$sgpr101'
  stackPtrOffsetReg: '$sgpr32'
  argumentInfo:    
    privateSegmentBuffer: { reg: '$sgpr0_sgpr1_sgpr2_sgpr3' }
    dispatchPtr:     { reg: '$sgpr4_sgpr5' }
    kernargSegmentPtr: { reg: '$sgpr6_sgpr7' }
    workGroupIDX:    { reg: '$sgpr8' }
    workGroupIDY:    { reg: '$sgpr9' }
    privateSegmentWaveByteOffset: { reg: '$sgpr10' }
    workItemIDX:     { reg: '$vgpr0' }
    workItemIDY:     { reg: '$vgpr1' }
    workItemIDZ:     { reg: '$vgpr2' }
body:             |
  bb.0:
    liveins: $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7
    $sgpr0 = S_MOV_B32 0
    $sgpr1 = S_MOV_B32 0
    $sgpr2 = S_MOV_B32 0
    $sgpr3 = S_MOV_B32 0
    $sgpr4 = S_MOV_B32 0
    $sgpr5 = S_MOV_B32 0
    $sgpr6 = S_MOV_B32 0
    $sgpr7 = S_MOV_B32 0
    $vcc = V_CMP_LT_U32_e64 $sgpr8, $vgpr1, implicit $exec
...