# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs -run-pass=si-i1-copies %s -o - | FileCheck -check-prefix=GCN %s
---
name: kernel_i1_copy_phi_with_phi_incoming_value
tracksRegLiveness: true
body: |
; GCN-LABEL: name: kernel_i1_copy_phi_with_phi_incoming_value
; GCN: bb.0:
; GCN-NEXT: successors: %bb.1(0x40000000), %bb.5(0x40000000)
; GCN-NEXT: liveins: $vgpr0, $sgpr4_sgpr5
; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:sgpr_64(p4) = COPY $sgpr4_sgpr5
; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr0
; GCN-NEXT: [[S_LOAD_DWORD_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM [[COPY]](p4), 0, 0 :: (dereferenceable invariant load (s32), align 16, addrspace 4)
; GCN-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[S_LOAD_DWORD_IMM]]
; GCN-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY1]](s32)
; GCN-NEXT: [[V_CMP_LT_I32_e64_:%[0-9]+]]:sreg_64 = V_CMP_LT_I32_e64 [[COPY1]](s32), [[S_LOAD_DWORD_IMM]], implicit $exec
; GCN-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 0
; GCN-NEXT: [[SI_IF:%[0-9]+]]:sreg_64 = SI_IF killed [[V_CMP_LT_I32_e64_]], %bb.5, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
; GCN-NEXT: S_BRANCH %bb.1
; GCN-NEXT: {{ $}}
; GCN-NEXT: bb.1:
; GCN-NEXT: successors: %bb.6(0x80000000)
; GCN-NEXT: {{ $}}
; GCN-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 16
; GCN-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[COPY3]], killed [[S_MOV_B32_]], 0, implicit $exec
; GCN-NEXT: [[V_CMP_GE_I32_e64_:%[0-9]+]]:sreg_64 = V_CMP_GE_I32_e64 [[V_ADD_U32_e64_]], [[COPY2]], implicit $exec
; GCN-NEXT: [[S_MOV_B64_1:%[0-9]+]]:sreg_64 = S_MOV_B64 0
; GCN-NEXT: [[COPY4:%[0-9]+]]:sreg_64 = COPY [[V_CMP_GE_I32_e64_]]
; GCN-NEXT: S_BRANCH %bb.6
; GCN-NEXT: {{ $}}
; GCN-NEXT: bb.2:
; GCN-NEXT: successors: %bb.5(0x80000000)
; GCN-NEXT: {{ $}}
; GCN-NEXT: [[PHI:%[0-9]+]]:sreg_64 = PHI %15, %bb.6
; GCN-NEXT: SI_END_CF [[PHI]], implicit-def dead $exec, implicit-def dead $scc, implicit $exec
; GCN-NEXT: [[S_MOV_B64_2:%[0-9]+]]:sreg_64 = S_MOV_B64 -1
; GCN-NEXT: [[COPY5:%[0-9]+]]:sreg_64 = COPY $exec
; GCN-NEXT: S_BRANCH %bb.5
; GCN-NEXT: {{ $}}
; GCN-NEXT: bb.3:
; GCN-NEXT: successors: %bb.4(0x40000000), %bb.7(0x40000000)
; GCN-NEXT: {{ $}}
; GCN-NEXT: ATOMIC_FENCE 5, 2
; GCN-NEXT: S_BARRIER
; GCN-NEXT: ATOMIC_FENCE 4, 2
; GCN-NEXT: [[COPY6:%[0-9]+]]:sreg_64 = COPY %18
; GCN-NEXT: [[SI_IF1:%[0-9]+]]:sreg_64 = SI_IF [[COPY6]], %bb.7, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
; GCN-NEXT: S_BRANCH %bb.4
; GCN-NEXT: {{ $}}
; GCN-NEXT: bb.4:
; GCN-NEXT: successors: %bb.7(0x80000000)
; GCN-NEXT: {{ $}}
; GCN-NEXT: S_BRANCH %bb.7
; GCN-NEXT: {{ $}}
; GCN-NEXT: bb.5:
; GCN-NEXT: successors: %bb.3(0x80000000)
; GCN-NEXT: {{ $}}
; GCN-NEXT: [[PHI1:%[0-9]+]]:sreg_64 = PHI [[S_MOV_B64_]], %bb.0, [[COPY5]], %bb.2
; GCN-NEXT: SI_END_CF [[SI_IF]], implicit-def dead $exec, implicit-def dead $scc, implicit $exec
; GCN-NEXT: S_BRANCH %bb.3
; GCN-NEXT: {{ $}}
; GCN-NEXT: bb.6:
; GCN-NEXT: successors: %bb.2(0x40000000), %bb.6(0x40000000)
; GCN-NEXT: {{ $}}
; GCN-NEXT: [[PHI2:%[0-9]+]]:sreg_64 = PHI [[S_MOV_B64_1]], %bb.1, %15, %bb.6
; GCN-NEXT: [[COPY7:%[0-9]+]]:sreg_64 = COPY [[COPY4]]
; GCN-NEXT: [[SI_IF_BREAK:%[0-9]+]]:sreg_64 = SI_IF_BREAK [[COPY7]], [[PHI2]], implicit-def dead $scc
; GCN-NEXT: SI_LOOP [[SI_IF_BREAK]], %bb.6, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
; GCN-NEXT: S_BRANCH %bb.2
; GCN-NEXT: {{ $}}
; GCN-NEXT: bb.7:
; GCN-NEXT: SI_END_CF [[SI_IF1]], implicit-def dead $exec, implicit-def dead $scc, implicit $exec
; GCN-NEXT: S_ENDPGM 0
bb.0:
successors: %bb.1, %bb.5
liveins: $vgpr0, $sgpr4_sgpr5
%1:sgpr_64(p4) = COPY $sgpr4_sgpr5
%2:vgpr_32(s32) = COPY $vgpr0
%3:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM %1:sgpr_64(p4), 0, 0 :: (dereferenceable invariant load (s32), align 16, addrspace 4)
%8:sreg_32 = COPY %3:sreg_32_xm0_xexec
%14:vgpr_32 = COPY %2:vgpr_32(s32)
%9:sreg_64 = V_CMP_LT_I32_e64 %2:vgpr_32(s32), %3:sreg_32_xm0_xexec, implicit $exec
%4:sreg_64 = S_MOV_B64 0
%17:vreg_1 = COPY %4:sreg_64, implicit $exec
%16:sreg_64 = SI_IF killed %9:sreg_64, %bb.5, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
S_BRANCH %bb.1
bb.1:
; predecessors: %bb.0
successors: %bb.6
%10:sreg_32 = S_MOV_B32 16
%18:vgpr_32 = V_ADD_U32_e64 %14:vgpr_32, killed %10:sreg_32, 0, implicit $exec
%11:sreg_64 = V_CMP_GE_I32_e64 %18:vgpr_32, %8:sreg_32, implicit $exec
%12:sreg_64 = S_MOV_B64 0
%19:vreg_1 = COPY %11:sreg_64
S_BRANCH %bb.6
bb.2:
; predecessors: %bb.6
successors: %bb.5
%20:sreg_64 = PHI %6:sreg_64, %bb.6
SI_END_CF %20:sreg_64, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
%15:sreg_64 = S_MOV_B64 -1
%21:vreg_1 = COPY %15:sreg_64, implicit $exec
S_BRANCH %bb.5
bb.3:
; predecessors: %bb.5
successors: %bb.4, %bb.7
%22:vreg_1 = PHI %7:vreg_1, %bb.5
ATOMIC_FENCE 5, 2
S_BARRIER
ATOMIC_FENCE 4, 2
%23:sreg_64 = COPY %22:vreg_1
%24:sreg_64 = SI_IF %23:sreg_64, %bb.7, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
S_BRANCH %bb.4
bb.4:
; predecessors: %bb.3
successors: %bb.7
S_BRANCH %bb.7
bb.5:
; predecessors: %bb.0, %bb.2
successors: %bb.3
%7:vreg_1 = PHI %17:vreg_1, %bb.0, %21:vreg_1, %bb.2
SI_END_CF %16:sreg_64, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
S_BRANCH %bb.3
bb.6:
; predecessors: %bb.1, %bb.6
successors: %bb.2, %bb.6
%5:sreg_64 = PHI %12:sreg_64, %bb.1, %6:sreg_64, %bb.6
%13:sreg_64 = COPY %19:vreg_1
%6:sreg_64 = SI_IF_BREAK %13:sreg_64, %5:sreg_64, implicit-def dead $scc
SI_LOOP %6:sreg_64, %bb.6, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
S_BRANCH %bb.2
bb.7:
; predecessors: %bb.3, %bb.4
SI_END_CF %24:sreg_64, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
S_ENDPGM 0
...
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