llvm/llvm/test/CodeGen/AArch64/GlobalISel/regbank-ceil.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=aarch64 -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s

...
---
name:            load_gets_fpr
legalized:       true
regBankSelected: false
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $x0
    ; CHECK-LABEL: name: load_gets_fpr
    ; CHECK: liveins: $x0
    ; CHECK: %ptr:gpr(p0) = COPY $x0
    ; CHECK: %load:fpr(s32) = G_LOAD %ptr(p0) :: (load (s32))
    ; CHECK: %fceil:fpr(s32) = G_FCEIL %load
    ; CHECK: $s0 = COPY %fceil(s32)
    ; CHECK: RET_ReallyLR implicit $s0
    %ptr:_(p0) = COPY $x0
    %load:_(s32) = G_LOAD %ptr(p0) :: (load (s32))
    %fceil:_(s32) = G_FCEIL %load
    $s0 = COPY %fceil:_(s32)
    RET_ReallyLR implicit $s0

...