postlegalizer-lowering-trn.mir | Explore in Territory

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple aarch64 -run-pass=aarch64-postlegalizer-lowering -verify-machineinstrs %s -o - | FileCheck %s
#
# Check that we produce G_TRN1 or G_TRN2 when we have an appropriate shuffle
# mask.
#

...
---
name:            trn1_v8s8
alignment:       4
legalized:       true
tracksRegLiveness: true
body:             |
  bb.1.entry:
    liveins: $d0, $d1
    ; CHECK-LABEL: name: trn1_v8s8
    ; CHECK: liveins: $d0, $d1
    ; CHECK: [[COPY:%[0-9]+]]:_(<8 x s8>) = COPY $d0
    ; CHECK: [[COPY1:%[0-9]+]]:_(<8 x s8>) = COPY $d1
    ; CHECK: [[TRN1_:%[0-9]+]]:_(<8 x s8>) = G_TRN1 [[COPY]], [[COPY1]]
    ; CHECK: $d0 = COPY [[TRN1_]](<8 x s8>)
    ; CHECK: RET_ReallyLR implicit $q0
    %0:_(<8 x s8>) = COPY $d0
    %1:_(<8 x s8>) = COPY $d1
    %2:_(<8 x s8>) = G_SHUFFLE_VECTOR %0(<8 x s8>), %1, shufflemask(0, 8, 2, 10, 4, 12, 6, 14)
    $d0 = COPY %2(<8 x s8>)
    RET_ReallyLR implicit $q0

...
---
name:            trn2_v8s8
alignment:       4
legalized:       true
tracksRegLiveness: true
body:             |
  bb.1.entry:
    liveins: $d0, $d1
    ; CHECK-LABEL: name: trn2_v8s8
    ; CHECK: liveins: $d0, $d1
    ; CHECK: [[COPY:%[0-9]+]]:_(<8 x s8>) = COPY $d0
    ; CHECK: [[COPY1:%[0-9]+]]:_(<8 x s8>) = COPY $d1
    ; CHECK: [[TRN2_:%[0-9]+]]:_(<8 x s8>) = G_TRN2 [[COPY]], [[COPY1]]
    ; CHECK: $d0 = COPY [[TRN2_]](<8 x s8>)
    ; CHECK: RET_ReallyLR implicit $q0
    %0:_(<8 x s8>) = COPY $d0
    %1:_(<8 x s8>) = COPY $d1
    %2:_(<8 x s8>) = G_SHUFFLE_VECTOR %0(<8 x s8>), %1, shufflemask(1, 9, 3, 11, 5, 13, 7, 15)
    $d0 = COPY %2(<8 x s8>)
    RET_ReallyLR implicit $q0

...
---
name:            trn1_v16s8
alignment:       4
legalized:       true
tracksRegLiveness: true
body:             |
  bb.1.entry:
    liveins: $q0, $q1
    ; CHECK-LABEL: name: trn1_v16s8
    ; CHECK: liveins: $q0, $q1
    ; CHECK: [[COPY:%[0-9]+]]:_(<16 x s8>) = COPY $q0
    ; CHECK: [[COPY1:%[0-9]+]]:_(<16 x s8>) = COPY $q1
    ; CHECK: [[TRN1_:%[0-9]+]]:_(<16 x s8>) = G_TRN1 [[COPY]], [[COPY1]]
    ; CHECK: $q0 = COPY [[TRN1_]](<16 x s8>)
    ; CHECK: RET_ReallyLR implicit $q0
    %0:_(<16 x s8>) = COPY $q0
    %1:_(<16 x s8>) = COPY $q1
    %2:_(<16 x s8>) = G_SHUFFLE_VECTOR %0(<16 x s8>), %1, shufflemask(0, 16, 2, 18, 4, 20, 6, 22, 8, 24, 10, 26, 12, 28, 14, 30)
    $q0 = COPY %2(<16 x s8>)
    RET_ReallyLR implicit $q0

...
---
name:            trn2_v16s8
alignment:       4
legalized:       true
tracksRegLiveness: true
body:             |
  bb.1.entry:
    liveins: $q0, $q1
    ; CHECK-LABEL: name: trn2_v16s8
    ; CHECK: liveins: $q0, $q1
    ; CHECK: [[COPY:%[0-9]+]]:_(<16 x s8>) = COPY $q0
    ; CHECK: [[COPY1:%[0-9]+]]:_(<16 x s8>) = COPY $q1
    ; CHECK: [[TRN2_:%[0-9]+]]:_(<16 x s8>) = G_TRN2 [[COPY]], [[COPY1]]
    ; CHECK: $q0 = COPY [[TRN2_]](<16 x s8>)
    ; CHECK: RET_ReallyLR implicit $q0
    %0:_(<16 x s8>) = COPY $q0
    %1:_(<16 x s8>) = COPY $q1
    %2:_(<16 x s8>) = G_SHUFFLE_VECTOR %0(<16 x s8>), %1, shufflemask(1, 17, 3, 19, 5, 21, 7, 23, 9, 25, 11, 27, 13, 29, 15, 31)
    $q0 = COPY %2(<16 x s8>)
    RET_ReallyLR implicit $q0

...
---
name:            trn1_v4s32
alignment:       4
legalized:       true
tracksRegLiveness: true
body:             |
  bb.1.entry:
    liveins: $q0, $q1
    ; CHECK-LABEL: name: trn1_v4s32
    ; CHECK: liveins: $q0, $q1
    ; CHECK: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
    ; CHECK: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $q1
    ; CHECK: [[TRN1_:%[0-9]+]]:_(<4 x s32>) = G_TRN1 [[COPY]], [[COPY1]]
    ; CHECK: $q0 = COPY [[TRN1_]](<4 x s32>)
    ; CHECK: RET_ReallyLR implicit $q0
    %0:_(<4 x s32>) = COPY $q0
    %1:_(<4 x s32>) = COPY $q1
    %2:_(<4 x s32>) = G_SHUFFLE_VECTOR %0(<4 x s32>), %1, shufflemask(0, 4, 2, 6)
    $q0 = COPY %2(<4 x s32>)
    RET_ReallyLR implicit $q0

...
---
name:            trn2_v4s32
alignment:       4
legalized:       true
tracksRegLiveness: true
body:             |
  bb.1.entry:
    liveins: $q0, $q1
    ; CHECK-LABEL: name: trn2_v4s32
    ; CHECK: liveins: $q0, $q1
    ; CHECK: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
    ; CHECK: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $q1
    ; CHECK: [[TRN2_:%[0-9]+]]:_(<4 x s32>) = G_TRN2 [[COPY]], [[COPY1]]
    ; CHECK: $q0 = COPY [[TRN2_]](<4 x s32>)
    ; CHECK: RET_ReallyLR implicit $q0
    %0:_(<4 x s32>) = COPY $q0
    %1:_(<4 x s32>) = COPY $q1
    %2:_(<4 x s32>) = G_SHUFFLE_VECTOR %0(<4 x s32>), %1, shufflemask(1, 5, 3, 7)
    $q0 = COPY %2(<4 x s32>)
    RET_ReallyLR implicit $q0

...
---
name:            redundant_with_zip1
alignment:       4
legalized:       true
tracksRegLiveness: true
body:             |
  bb.1.entry:
    liveins: $d0, $d1
    ; 2 x s32 TRN is redundant with ZIP. Make sure we prioritize ZIP.
    ;
    ; CHECK-LABEL: name: redundant_with_zip1
    ; CHECK: liveins: $d0, $d1
    ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
    ; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $d1
    ; CHECK: [[ZIP1_:%[0-9]+]]:_(<2 x s32>) = G_ZIP1 [[COPY]], [[COPY1]]
    ; CHECK: $d0 = COPY [[ZIP1_]](<2 x s32>)
    ; CHECK: RET_ReallyLR implicit $d0
    %0:_(<2 x s32>) = COPY $d0
    %1:_(<2 x s32>) = COPY $d1
    %2:_(<2 x s32>) = G_SHUFFLE_VECTOR %0(<2 x s32>), %1, shufflemask(0, 2)
    $d0 = COPY %2(<2 x s32>)
    RET_ReallyLR implicit $d0

...
---
name:            redundant_with_zip2
alignment:       4
legalized:       true
tracksRegLiveness: true
body:             |
  bb.1.entry:
    liveins: $d0, $d1
    ; 2 x s32 TRN is redundant with ZIP. Make sure we prioritize ZIP.
    ;
    ; CHECK-LABEL: name: redundant_with_zip2
    ; CHECK: liveins: $d0, $d1
    ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
    ; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $d1
    ; CHECK: [[ZIP2_:%[0-9]+]]:_(<2 x s32>) = G_ZIP2 [[COPY]], [[COPY1]]
    ; CHECK: $d0 = COPY [[ZIP2_]](<2 x s32>)
    ; CHECK: RET_ReallyLR implicit $d0
    %0:_(<2 x s32>) = COPY $d0
    %1:_(<2 x s32>) = COPY $d1
    %2:_(<2 x s32>) = G_SHUFFLE_VECTOR %0(<2 x s32>), %1, shufflemask(1, 3)
    $d0 = COPY %2(<2 x s32>)
    RET_ReallyLR implicit $d0

...
---
name:            trn1_undef
alignment:       4
legalized:       true
tracksRegLiveness: true
body:             |
  bb.1.entry:
    liveins: $d0, $d1
    ; Undef shuffle indices should not prevent matching to G_TRN1.
    ;
    ; CHECK-LABEL: name: trn1_undef
    ; CHECK: liveins: $d0, $d1
    ; CHECK: [[COPY:%[0-9]+]]:_(<8 x s8>) = COPY $d0
    ; CHECK: [[COPY1:%[0-9]+]]:_(<8 x s8>) = COPY $d1
    ; CHECK: [[TRN1_:%[0-9]+]]:_(<8 x s8>) = G_TRN1 [[COPY]], [[COPY1]]
    ; CHECK: $d0 = COPY [[TRN1_]](<8 x s8>)
    ; CHECK: RET_ReallyLR implicit $d0
    %0:_(<8 x s8>) = COPY $d0
    %1:_(<8 x s8>) = COPY $d1
    %2:_(<8 x s8>) = G_SHUFFLE_VECTOR %0(<8 x s8>), %1, shufflemask(0, 8, -1, -1, 4, 12, 6, 14)
    $d0 = COPY %2(<8 x s8>)
    RET_ReallyLR implicit $d0

...
---
name:            trn2_undef
alignment:       4
legalized:       true
tracksRegLiveness: true
body:             |
  bb.1.entry:
    liveins: $d0, $d1
    ; Undef shuffle indices should not prevent matching to G_TRN2.
    ;
    ; CHECK-LABEL: name: trn2_undef
    ; CHECK: liveins: $d0, $d1
    ; CHECK: [[COPY:%[0-9]+]]:_(<8 x s8>) = COPY $d0
    ; CHECK: [[COPY1:%[0-9]+]]:_(<8 x s8>) = COPY $d1
    ; CHECK: [[TRN2_:%[0-9]+]]:_(<8 x s8>) = G_TRN2 [[COPY]], [[COPY1]]
    ; CHECK: $d0 = COPY [[TRN2_]](<8 x s8>)
    ; CHECK: RET_ReallyLR implicit $d0
    %0:_(<8 x s8>) = COPY $d0
    %1:_(<8 x s8>) = COPY $d1
    %2:_(<8 x s8>) = G_SHUFFLE_VECTOR %0(<8 x s8>), %1, shufflemask(1, -1, 3, 11, 5, 13, -1, -1)
    $d0 = COPY %2(<8 x s8>)
    RET_ReallyLR implicit $d0
llvm/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-trn.mir
