llvm/llvm/test/CodeGen/AArch64/GlobalISel/combine-vscale.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -o - -mtriple=aarch64 -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs %s | FileCheck %s

...
---
name:            sum_of_vscale
body:             |
  bb.1:
    liveins: $x0, $x1
    ; CHECK-LABEL: name: sum_of_vscale
    ; CHECK: liveins: $x0, $x1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: %sum:_(s64) = G_VSCALE i64 20
    ; CHECK-NEXT: $x0 = COPY %sum(s64)
    ; CHECK-NEXT: RET_ReallyLR implicit $x0
    %rhs:_(s64) = G_VSCALE i64 11
    %lhs:_(s64) = G_VSCALE i64 9
    %sum:_(s64) = nsw G_ADD %lhs(s64), %rhs(s64)
    $x0 = COPY %sum(s64)
    RET_ReallyLR implicit $x0
...
---
name:            sum_of_vscale_multi_use
body:             |
  bb.1:
    liveins: $x0, $x1
    ; CHECK-LABEL: name: sum_of_vscale_multi_use
    ; CHECK: liveins: $x0, $x1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: %rhs:_(s64) = G_VSCALE i64 11
    ; CHECK-NEXT: %lhs:_(s64) = G_VSCALE i64 9
    ; CHECK-NEXT: %sum:_(s64) = nsw G_ADD %lhs, %rhs
    ; CHECK-NEXT: $x0 = COPY %sum(s64)
    ; CHECK-NEXT: $x1 = COPY %rhs(s64)
    ; CHECK-NEXT: RET_ReallyLR implicit $x0
    %rhs:_(s64) = G_VSCALE i64 11
    %lhs:_(s64) = G_VSCALE i64 9
    %sum:_(s64) = nsw G_ADD %lhs(s64), %rhs(s64)
    $x0 = COPY %sum(s64)
    $x1 = COPY %rhs(s64)
    RET_ReallyLR implicit $x0
...
---
name:            mul_of_vscale
body:             |
  bb.1:
    liveins: $x0, $x1
    ; CHECK-LABEL: name: mul_of_vscale
    ; CHECK: liveins: $x0, $x1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: %mul:_(s64) = G_VSCALE i64 99
    ; CHECK-NEXT: $x0 = COPY %mul(s64)
    ; CHECK-NEXT: RET_ReallyLR implicit $x0
    %rhs:_(s64) = G_CONSTANT i64 11
    %lhs:_(s64) = G_VSCALE i64 9
    %mul:_(s64) = nsw G_MUL %lhs(s64), %rhs(s64)
    $x0 = COPY %mul(s64)
    RET_ReallyLR implicit $x0
...
---
name:            sub_of_vscale
body:             |
  bb.1:
    liveins: $x0, $x1
    ; CHECK-LABEL: name: sub_of_vscale
    ; CHECK: liveins: $x0, $x1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: %x:_(s64) = COPY $x0
    ; CHECK-NEXT: [[VSCALE:%[0-9]+]]:_(s64) = G_VSCALE i64 -9
    ; CHECK-NEXT: %sub:_(s64) = nsw G_ADD %x, [[VSCALE]]
    ; CHECK-NEXT: $x0 = COPY %sub(s64)
    ; CHECK-NEXT: RET_ReallyLR implicit $x0
    %x:_(s64) = COPY $x0
    %rhs:_(s64) = G_VSCALE i64 9
    %sub:_(s64) = nsw G_SUB %x(s64), %rhs(s64)
    $x0 = COPY %sub(s64)
    RET_ReallyLR implicit $x0
...
---
name:            shl_of_vscale
body:             |
  bb.1:
    liveins: $x0, $x1
    ; CHECK-LABEL: name: shl_of_vscale
    ; CHECK: liveins: $x0, $x1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: %shl:_(s64) = G_VSCALE i64 44
    ; CHECK-NEXT: $x0 = COPY %shl(s64)
    ; CHECK-NEXT: RET_ReallyLR implicit $x0
    %rhs:_(s64) = G_CONSTANT i64 2
    %lhs:_(s64) = G_VSCALE i64 11
    %shl:_(s64) = nsw G_SHL %lhs(s64), %rhs(s64)
    $x0 = COPY %shl(s64)
    RET_ReallyLR implicit $x0
...
---
name:            shl_of_vscale_wrong_flag
body:             |
  bb.1:
    liveins: $x0, $x1
    ; CHECK-LABEL: name: shl_of_vscale_wrong_flag
    ; CHECK: liveins: $x0, $x1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: %rhs:_(s64) = G_CONSTANT i64 2
    ; CHECK-NEXT: %lhs:_(s64) = G_VSCALE i64 11
    ; CHECK-NEXT: %shl:_(s64) = nuw G_SHL %lhs, %rhs(s64)
    ; CHECK-NEXT: $x0 = COPY %shl(s64)
    ; CHECK-NEXT: RET_ReallyLR implicit $x0
    %rhs:_(s64) = G_CONSTANT i64 2
    %lhs:_(s64) = G_VSCALE i64 11
    %shl:_(s64) = nuw G_SHL %lhs(s64), %rhs(s64)
    $x0 = COPY %shl(s64)
    RET_ReallyLR implicit $x0