# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=aarch64 -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=1 %s -o - | FileCheck %s
---
name: add_B
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
liveins:
- { reg: '$x0' }
body: |
bb.1:
liveins: $x0
; CHECK-LABEL: name: add_B
; CHECK: liveins: $x0
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
; CHECK: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[COPY]], 0 :: (load (<16 x s8>))
; CHECK: [[ADDVv16i8v:%[0-9]+]]:fpr8 = ADDVv16i8v [[LDRQui]]
; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:fpr32 = SUBREG_TO_REG 0, [[ADDVv16i8v]], %subreg.bsub
; CHECK: [[COPY1:%[0-9]+]]:gpr32all = COPY [[SUBREG_TO_REG]]
; CHECK: $w0 = COPY [[COPY1]]
; CHECK: RET_ReallyLR implicit $w0
%0:gpr(p0) = COPY $x0
%1:fpr(<16 x s8>) = G_LOAD %0(p0) :: (load (<16 x s8>))
%2:fpr(s8) = G_VECREDUCE_ADD %1(<16 x s8>)
%4:gpr(s8) = COPY %2(s8)
%3:gpr(s32) = G_ANYEXT %4(s8)
$w0 = COPY %3(s32)
RET_ReallyLR implicit $w0
...
---
name: add_H
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
liveins:
- { reg: '$x0' }
body: |
bb.1:
liveins: $x0
; CHECK-LABEL: name: add_H
; CHECK: liveins: $x0
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
; CHECK: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[COPY]], 0 :: (load (<8 x s16>))
; CHECK: [[ADDVv8i16v:%[0-9]+]]:fpr16 = ADDVv8i16v [[LDRQui]]
; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:fpr32 = SUBREG_TO_REG 0, [[ADDVv8i16v]], %subreg.hsub
; CHECK: [[COPY1:%[0-9]+]]:gpr32all = COPY [[SUBREG_TO_REG]]
; CHECK: $w0 = COPY [[COPY1]]
; CHECK: RET_ReallyLR implicit $w0
%0:gpr(p0) = COPY $x0
%1:fpr(<8 x s16>) = G_LOAD %0(p0) :: (load (<8 x s16>))
%2:fpr(s16) = G_VECREDUCE_ADD %1(<8 x s16>)
%4:gpr(s16) = COPY %2(s16)
%3:gpr(s32) = G_ANYEXT %4(s16)
$w0 = COPY %3(s32)
RET_ReallyLR implicit $w0
...
---
name: add_S
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
liveins:
- { reg: '$x0' }
body: |
bb.1:
liveins: $x0
; CHECK-LABEL: name: add_S
; CHECK: liveins: $x0
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
; CHECK: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[COPY]], 0 :: (load (<4 x s32>))
; CHECK: [[ADDVv4i32v:%[0-9]+]]:fpr32 = ADDVv4i32v [[LDRQui]]
; CHECK: $w0 = COPY [[ADDVv4i32v]]
; CHECK: RET_ReallyLR implicit $w0
%0:gpr(p0) = COPY $x0
%1:fpr(<4 x s32>) = G_LOAD %0(p0) :: (load (<4 x s32>))
%2:fpr(s32) = G_VECREDUCE_ADD %1(<4 x s32>)
$w0 = COPY %2(s32)
RET_ReallyLR implicit $w0
...
---
name: add_S_v2i32
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
liveins:
- { reg: '$x0' }
body: |
bb.1:
liveins: $x0
; CHECK-LABEL: name: add_S_v2i32
; CHECK: liveins: $x0
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
; CHECK: [[LDRDui:%[0-9]+]]:fpr64 = LDRDui [[COPY]], 0 :: (load (<2 x s32>))
; CHECK: [[ADDPv2i32_:%[0-9]+]]:fpr64 = ADDPv2i32 [[LDRDui]], [[LDRDui]]
; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY [[ADDPv2i32_]].ssub
; CHECK: $w0 = COPY [[COPY1]]
; CHECK: RET_ReallyLR implicit $w0
%0:gpr(p0) = COPY $x0
%1:fpr(<2 x s32>) = G_LOAD %0(p0) :: (load (<2 x s32>))
%2:fpr(s32) = G_VECREDUCE_ADD %1(<2 x s32>)
$w0 = COPY %2(s32)
RET_ReallyLR implicit $w0
...
---
name: add_D
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
liveins:
- { reg: '$x0' }
body: |
bb.1:
liveins: $x0
; CHECK-LABEL: name: add_D
; CHECK: liveins: $x0
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
; CHECK: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[COPY]], 0 :: (load (<2 x s64>))
; CHECK: [[ADDPv2i64p:%[0-9]+]]:fpr64 = ADDPv2i64p [[LDRQui]]
; CHECK: $x0 = COPY [[ADDPv2i64p]]
; CHECK: RET_ReallyLR implicit $x0
%0:gpr(p0) = COPY $x0
%1:fpr(<2 x s64>) = G_LOAD %0(p0) :: (load (<2 x s64>))
%2:fpr(s64) = G_VECREDUCE_ADD %1(<2 x s64>)
$x0 = COPY %2(s64)
RET_ReallyLR implicit $x0
...
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