combine-add.mir | Explore in Territory

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs -mtriple aarch64-unknown-unknown %s -o - | FileCheck %s

---
name:            add_lhs_sub_reg
alignment:       4
tracksRegLiveness: true
frameInfo:
  maxAlignment:    1
machineFunctionInfo: {}
body:             |
  bb.0:
    liveins: $w0, $w1
    ; CHECK-LABEL: name: add_lhs_sub_reg
    ; CHECK: liveins: $w0, $w1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
    ; CHECK-NEXT: $w0 = COPY [[COPY]](s32)
    %0:_(s32) = COPY $w0
    %1:_(s32) = COPY $w1
    %2:_(s32) = G_SUB %0, %1
    %3:_(s32) = G_ADD %2, %1
    $w0 = COPY %3
...
---
name:            add_lhs_sub_reg_wide
alignment:       4
tracksRegLiveness: true
frameInfo:
  maxAlignment:    1
machineFunctionInfo: {}
body:             |
  bb.0:
    liveins: $q0, $q1
    ; CHECK-LABEL: name: add_lhs_sub_reg_wide
    ; CHECK: liveins: $q0, $q1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s128) = COPY $q0
    ; CHECK-NEXT: $q0 = COPY [[COPY]](s128)
    %0:_(s128) = COPY $q0
    %1:_(s128) = COPY $q1
    %2:_(s128) = G_SUB %0, %1
    %3:_(s128) = G_ADD %2, %1
    $q0 = COPY %3
...
---
name:            add_lhs_sub_reg_vec
alignment:       4
tracksRegLiveness: true
frameInfo:
  maxAlignment:    1
machineFunctionInfo: {}
body:             |
  bb.0:
    liveins: $x0, $x1
    ; CHECK-LABEL: name: add_lhs_sub_reg_vec
    ; CHECK: liveins: $x0, $x1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $x0
    ; CHECK-NEXT: $x0 = COPY [[COPY]](<4 x s16>)
    %0:_(<4 x s16>) = COPY $x0
    %1:_(<4 x s16>) = COPY $x1
    %2:_(<4 x s16>) = G_SUB %0, %1
    %3:_(<4 x s16>) = G_ADD %2, %1
    $x0 = COPY %3
...
---
name:            add_rhs_sub_reg
alignment:       4
tracksRegLiveness: true
frameInfo:
  maxAlignment:    1
machineFunctionInfo: {}
body:             |
  bb.0:
    liveins: $w0, $w1
    ; CHECK-LABEL: name: add_rhs_sub_reg
    ; CHECK: liveins: $w0, $w1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
    ; CHECK-NEXT: $w0 = COPY [[COPY]](s32)
    %0:_(s32) = COPY $w0
    %1:_(s32) = COPY $w1
    %2:_(s32) = G_SUB %0, %1
    %3:_(s32) = G_ADD %1, %2
    $w0 = COPY %3
...
---
name:            add_rhs_sub_reg_wide
alignment:       4
tracksRegLiveness: true
frameInfo:
  maxAlignment:    1
machineFunctionInfo: {}
body:             |
  bb.0:
    liveins: $q0, $q1
    ; CHECK-LABEL: name: add_rhs_sub_reg_wide
    ; CHECK: liveins: $q0, $q1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s128) = COPY $q0
    ; CHECK-NEXT: $q0 = COPY [[COPY]](s128)
    %0:_(s128) = COPY $q0
    %1:_(s128) = COPY $q1
    %2:_(s128) = G_SUB %0, %1
    %3:_(s128) = G_ADD %1, %2
    $q0 = COPY %3
...
---
name:            add_rhs_sub_reg_vec
alignment:       4
tracksRegLiveness: true
frameInfo:
  maxAlignment:    1
machineFunctionInfo: {}
body:             |
  bb.0:
    liveins: $x0, $x1
    ; CHECK-LABEL: name: add_rhs_sub_reg_vec
    ; CHECK: liveins: $x0, $x1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $x0
    ; CHECK-NEXT: $x0 = COPY [[COPY]](<4 x s16>)
    %0:_(<4 x s16>) = COPY $x0
    %1:_(<4 x s16>) = COPY $x1
    %2:_(<4 x s16>) = G_SUB %0, %1
    %3:_(<4 x s16>) = G_ADD %1, %2
    $x0 = COPY %3
...
---
name:            fadd_by_zero
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $d0
    ; CHECK-LABEL: name: fadd_by_zero
    ; CHECK: liveins: $d0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $d0
    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 0.000000e+00
    ; CHECK-NEXT: [[FADD:%[0-9]+]]:_(s64) = G_FADD [[COPY]], [[C]]
    ; CHECK-NEXT: $d0 = COPY [[FADD]](s64)
    %0:_(s64) = COPY $d0
    %1:_(s64) = G_FCONSTANT double 0.000000e+00
    %2:_(s64) = G_FADD %0, %1(s64)
    $d0 = COPY %2(s64)
...
---
name:            fadd_vector_by_zero
alignment:       4
tracksRegLiveness: true
frameInfo:
  maxAlignment:    1
machineFunctionInfo: {}
body:             |
  bb.0:
    liveins: $q0
    ; CHECK-LABEL: name: fadd_vector_by_zero
    ; CHECK: liveins: $q0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00
    ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32)
    ; CHECK-NEXT: [[FADD:%[0-9]+]]:_(<4 x s32>) = G_FADD [[COPY]], [[BUILD_VECTOR]]
    ; CHECK-NEXT: $q0 = COPY [[FADD]](<4 x s32>)
    %0:_(<4 x s32>) = COPY $q0
    %1:_(s32) = G_FCONSTANT float 0.0
    %2:_(<4 x s32>) = G_BUILD_VECTOR %1(s32), %1(s32), %1(s32), %1(s32)
    %3:_(<4 x s32>) = G_FADD %0, %2(<4 x s32>)
    $q0 = COPY %3(<4 x s32>)
...

---
name:            fadd_by_neg_zero
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $d0
    ; CHECK-LABEL: name: fadd_by_neg_zero
    ; CHECK: liveins: $d0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $d0
    ; CHECK-NEXT: $d0 = COPY [[COPY]](s64)
    %0:_(s64) = COPY $d0
    %1:_(s64) = G_FCONSTANT double -0.000000e+00
    %2:_(s64) = G_FADD %0, %1(s64)
    $d0 = COPY %2(s64)
...
---
name:            fadd_vector_by_neg_zero
alignment:       4
tracksRegLiveness: true
frameInfo:
  maxAlignment:    1
machineFunctionInfo: {}
body:             |
  bb.0:
    liveins: $q0
    ; CHECK-LABEL: name: fadd_vector_by_neg_zero
    ; CHECK: liveins: $q0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
    ; CHECK-NEXT: $q0 = COPY [[COPY]](<4 x s32>)
    %0:_(<4 x s32>) = COPY $q0
    %1:_(s32) = G_FCONSTANT float -0.0
    %2:_(<4 x s32>) = G_BUILD_VECTOR %1(s32), %1(s32), %1(s32), %1(s32)
    %3:_(<4 x s32>) = G_FADD %0, %2(<4 x s32>)
    $q0 = COPY %3(<4 x s32>)
...
---
name:            saddl_v8i8_v8i32
tracksRegLiveness: true
body:             |
  bb.1:
    liveins: $d0, $d1

    ; CHECK-LABEL: name: saddl_v8i8_v8i32
    ; CHECK: liveins: $d0, $d1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s8>) = COPY $d0
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<8 x s8>) = COPY $d1
    ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(<8 x s16>) = G_SEXT [[COPY]](<8 x s8>)
    ; CHECK-NEXT: [[SEXT1:%[0-9]+]]:_(<8 x s16>) = G_SEXT [[COPY1]](<8 x s8>)
    ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(<8 x s16>) = G_ADD [[SEXT]], [[SEXT1]]
    ; CHECK-NEXT: [[SEXT2:%[0-9]+]]:_(<8 x s32>) = G_SEXT [[ADD]](<8 x s16>)
    ; CHECK-NEXT: [[UV:%[0-9]+]]:_(<4 x s32>), [[UV1:%[0-9]+]]:_(<4 x s32>) = G_UNMERGE_VALUES [[SEXT2]](<8 x s32>)
    ; CHECK-NEXT: $q0 = COPY [[UV]](<4 x s32>)
    ; CHECK-NEXT: $q1 = COPY [[UV1]](<4 x s32>)
    ; CHECK-NEXT: RET_ReallyLR implicit $q0, implicit $q1
    %0:_(<8 x s8>) = COPY $d0
    %1:_(<8 x s8>) = COPY $d1
    %2:_(<8 x s32>) = G_SEXT %0(<8 x s8>)
    %3:_(<8 x s32>) = G_SEXT %1(<8 x s8>)
    %4:_(<8 x s32>) = G_ADD %2, %3
    %5:_(<4 x s32>), %6:_(<4 x s32>) = G_UNMERGE_VALUES %4(<8 x s32>)
    $q0 = COPY %5(<4 x s32>)
    $q1 = COPY %6(<4 x s32>)
    RET_ReallyLR implicit $q0, implicit $q1
...

---
name:            uaddl_v8i8_v8i32
tracksRegLiveness: true
body:             |
  bb.1:
    liveins: $d0, $d1

    ; CHECK-LABEL: name: uaddl_v8i8_v8i32
    ; CHECK: liveins: $d0, $d1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s8>) = COPY $d0
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<8 x s8>) = COPY $d1
    ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(<8 x s16>) = G_ZEXT [[COPY]](<8 x s8>)
    ; CHECK-NEXT: [[ZEXT1:%[0-9]+]]:_(<8 x s16>) = G_ZEXT [[COPY1]](<8 x s8>)
    ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(<8 x s16>) = G_ADD [[ZEXT]], [[ZEXT1]]
    ; CHECK-NEXT: [[ZEXT2:%[0-9]+]]:_(<8 x s32>) = G_ZEXT [[ADD]](<8 x s16>)
    ; CHECK-NEXT: [[UV:%[0-9]+]]:_(<4 x s32>), [[UV1:%[0-9]+]]:_(<4 x s32>) = G_UNMERGE_VALUES [[ZEXT2]](<8 x s32>)
    ; CHECK-NEXT: $q0 = COPY [[UV]](<4 x s32>)
    ; CHECK-NEXT: $q1 = COPY [[UV1]](<4 x s32>)
    ; CHECK-NEXT: RET_ReallyLR implicit $q0, implicit $q1
    %0:_(<8 x s8>) = COPY $d0
    %1:_(<8 x s8>) = COPY $d1
    %2:_(<8 x s32>) = G_ZEXT %0(<8 x s8>)
    %3:_(<8 x s32>) = G_ZEXT %1(<8 x s8>)
    %4:_(<8 x s32>) = G_ADD %2, %3
    %5:_(<4 x s32>), %6:_(<4 x s32>) = G_UNMERGE_VALUES %4(<8 x s32>)
    $q0 = COPY %5(<4 x s32>)
    $q1 = COPY %6(<4 x s32>)
    RET_ReallyLR implicit $q0, implicit $q1
...

---
name:            ssubl_v8i8_v8i32
tracksRegLiveness: true
body:             |
  bb.1:
    liveins: $d0, $d1

    ; CHECK-LABEL: name: ssubl_v8i8_v8i32
    ; CHECK: liveins: $d0, $d1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s8>) = COPY $d0
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<8 x s8>) = COPY $d1
    ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(<8 x s16>) = G_SEXT [[COPY]](<8 x s8>)
    ; CHECK-NEXT: [[SEXT1:%[0-9]+]]:_(<8 x s16>) = G_SEXT [[COPY1]](<8 x s8>)
    ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(<8 x s16>) = G_SUB [[SEXT]], [[SEXT1]]
    ; CHECK-NEXT: [[SEXT2:%[0-9]+]]:_(<8 x s32>) = G_SEXT [[SUB]](<8 x s16>)
    ; CHECK-NEXT: [[UV:%[0-9]+]]:_(<4 x s32>), [[UV1:%[0-9]+]]:_(<4 x s32>) = G_UNMERGE_VALUES [[SEXT2]](<8 x s32>)
    ; CHECK-NEXT: $q0 = COPY [[UV]](<4 x s32>)
    ; CHECK-NEXT: $q1 = COPY [[UV1]](<4 x s32>)
    ; CHECK-NEXT: RET_ReallyLR implicit $q0, implicit $q1
    %0:_(<8 x s8>) = COPY $d0
    %1:_(<8 x s8>) = COPY $d1
    %2:_(<8 x s32>) = G_SEXT %0(<8 x s8>)
    %3:_(<8 x s32>) = G_SEXT %1(<8 x s8>)
    %4:_(<8 x s32>) = G_SUB %2, %3
    %5:_(<4 x s32>), %6:_(<4 x s32>) = G_UNMERGE_VALUES %4(<8 x s32>)
    $q0 = COPY %5(<4 x s32>)
    $q1 = COPY %6(<4 x s32>)
    RET_ReallyLR implicit $q0, implicit $q1
...

---
name:            usubl_v8i8_v8i32
tracksRegLiveness: true
body:             |
  bb.1:
    liveins: $d0, $d1

    ; CHECK-LABEL: name: usubl_v8i8_v8i32
    ; CHECK: liveins: $d0, $d1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s8>) = COPY $d0
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<8 x s8>) = COPY $d1
    ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(<8 x s16>) = G_ZEXT [[COPY]](<8 x s8>)
    ; CHECK-NEXT: [[ZEXT1:%[0-9]+]]:_(<8 x s16>) = G_ZEXT [[COPY1]](<8 x s8>)
    ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(<8 x s16>) = G_SUB [[ZEXT]], [[ZEXT1]]
    ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(<8 x s32>) = G_SEXT [[SUB]](<8 x s16>)
    ; CHECK-NEXT: [[UV:%[0-9]+]]:_(<4 x s32>), [[UV1:%[0-9]+]]:_(<4 x s32>) = G_UNMERGE_VALUES [[SEXT]](<8 x s32>)
    ; CHECK-NEXT: $q0 = COPY [[UV]](<4 x s32>)
    ; CHECK-NEXT: $q1 = COPY [[UV1]](<4 x s32>)
    ; CHECK-NEXT: RET_ReallyLR implicit $q0, implicit $q1
    %0:_(<8 x s8>) = COPY $d0
    %1:_(<8 x s8>) = COPY $d1
    %2:_(<8 x s32>) = G_ZEXT %0(<8 x s8>)
    %3:_(<8 x s32>) = G_ZEXT %1(<8 x s8>)
    %4:_(<8 x s32>) = G_SUB %2, %3
    %5:_(<4 x s32>), %6:_(<4 x s32>) = G_UNMERGE_VALUES %4(<8 x s32>)
    $q0 = COPY %5(<4 x s32>)
    $q1 = COPY %6(<4 x s32>)
    RET_ReallyLR implicit $q0, implicit $q1
...
llvm/llvm/test/CodeGen/AArch64/GlobalISel/combine-add.mir
