llvm/llvm/test/CodeGen/AArch64/GlobalISel/no-reduce-shl-of-ext.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
; RUN: llc %s -verify-machineinstrs -mtriple aarch64-apple-darwin -global-isel -o - | FileCheck %s
target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"

%struct.mszip_stream = type { i32, i32, i8, i32, ptr, i32, i32, i32, i32, ptr, ptr, ptr, ptr, ptr, i32, i32, i32, [288 x i8], [32 x i8], [1152 x i16], [128 x i16], [32768 x i8], ptr, ptr }

define i16 @test(i32 %bit_buffer.6.lcssa, ptr %zip, ptr %.out) {
; CHECK-LABEL: test:
; CHECK:       ; %bb.0:
; CHECK-NEXT:    and w8, w0, #0x1ff
; CHECK-NEXT:    add x8, x1, w8, uxtw #1
; CHECK-NEXT:    ldrh w0, [x8, #412]
; CHECK-NEXT:    ret
  %and274 = and i32 %bit_buffer.6.lcssa, 511
  %idxprom275 = zext i32 %and274 to i64
  %arrayidx276 = getelementptr inbounds %struct.mszip_stream, ptr %zip, i64 0, i32 19, i64 %idxprom275
  %ld = load i16, ptr %arrayidx276, align 2
  ret i16 %ld
}