# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=aarch64 -run-pass=legalizer -global-isel-abort=1 -O0 %s -o - | FileCheck %s
---
name: test_freeze_s64
body: |
bb.0.entry:
liveins: $x0
; CHECK-LABEL: name: test_freeze_s64
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %x0:_(s64) = COPY $x0
; CHECK-NEXT: [[FREEZE:%[0-9]+]]:_(s64) = G_FREEZE %x0
; CHECK-NEXT: $x0 = COPY [[FREEZE]](s64)
%x0:_(s64) = COPY $x0
%1:_(s64) = G_FREEZE %x0
$x0 = COPY %1(s64)
...
---
name: test_freeze_v4s32
body: |
bb.0:
liveins: $q0
; CHECK-LABEL: name: test_freeze_v4s32
; CHECK: liveins: $q0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %q0:_(<4 x s32>) = COPY $q0
; CHECK-NEXT: [[FREEZE:%[0-9]+]]:_(<4 x s32>) = G_FREEZE %q0
; CHECK-NEXT: [[UV:%[0-9]+]]:_(<2 x s32>), [[UV1:%[0-9]+]]:_(<2 x s32>) = G_UNMERGE_VALUES [[FREEZE]](<4 x s32>)
; CHECK-NEXT: $x0 = COPY [[UV]](<2 x s32>)
; CHECK-NEXT: $x1 = COPY [[UV1]](<2 x s32>)
%q0:_(<4 x s32>) = COPY $q0
%0:_(<4 x s32>) = G_FREEZE %q0
%1:_(<2 x s32> ), %2:_(<2 x s32>) = G_UNMERGE_VALUES %0
$x0 = COPY %1
$x1 = COPY %2
...
---
name: test_freeze_v4s64
body: |
bb.0:
; CHECK-LABEL: name: test_freeze_v4s64
; CHECK: [[DEF:%[0-9]+]]:_(<2 x s64>) = G_IMPLICIT_DEF
; CHECK-NEXT: [[FREEZE:%[0-9]+]]:_(<2 x s64>) = G_FREEZE [[DEF]]
; CHECK-NEXT: [[FREEZE1:%[0-9]+]]:_(<2 x s64>) = G_FREEZE [[DEF]]
; CHECK-NEXT: $q0 = COPY [[FREEZE]](<2 x s64>)
; CHECK-NEXT: $q1 = COPY [[FREEZE1]](<2 x s64>)
%undef:_(<4 x s64>) = G_IMPLICIT_DEF
%0:_(<4 x s64>) = G_FREEZE %undef
%1:_(<2 x s64> ), %2:_(<2 x s64>) = G_UNMERGE_VALUES %0
$q0 = COPY %1
$q1 = COPY %2
...
---
name: test_freeze_v2s32
body: |
bb.0:
liveins: $d0
; CHECK-LABEL: name: test_freeze_v2s32
; CHECK: liveins: $d0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %d0:_(<2 x s32>) = COPY $d0
; CHECK-NEXT: [[FREEZE:%[0-9]+]]:_(<2 x s32>) = G_FREEZE %d0
; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[FREEZE]](<2 x s32>)
; CHECK-NEXT: $w0 = COPY [[UV]](s32)
; CHECK-NEXT: $w1 = COPY [[UV1]](s32)
%d0:_(<2 x s32>) = COPY $d0
%0:_(<2 x s32>) = G_FREEZE %d0
%1:_(s32), %2:_(s32) = G_UNMERGE_VALUES %0
$w0 = COPY %1
$w1 = COPY %2
...
---
name: test_freeze_v8s8
body: |
bb.0:
liveins: $d0
; CHECK-LABEL: name: test_freeze_v8s8
; CHECK: liveins: $d0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %d0:_(<8 x s8>) = COPY $d0
; CHECK-NEXT: [[FREEZE:%[0-9]+]]:_(<8 x s8>) = G_FREEZE %d0
; CHECK-NEXT: [[UV:%[0-9]+]]:_(<4 x s8>), [[UV1:%[0-9]+]]:_(<4 x s8>) = G_UNMERGE_VALUES [[FREEZE]](<8 x s8>)
; CHECK-NEXT: $w0 = COPY [[UV]](<4 x s8>)
; CHECK-NEXT: $w1 = COPY [[UV1]](<4 x s8>)
%d0:_(<8 x s8>) = COPY $d0
%0:_(<8 x s8>) = G_FREEZE %d0
%1:_(<4 x s8>), %2:_(<4 x s8>) = G_UNMERGE_VALUES %0
$w0 = COPY %1
$w1 = COPY %2
...
---
name: test_freeze_s1
body: |
bb.0.entry:
liveins: $x0
; CHECK-LABEL: name: test_freeze_s1
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s8) = G_IMPLICIT_DEF
; CHECK-NEXT: [[FREEZE:%[0-9]+]]:_(s8) = G_FREEZE [[DEF]]
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[FREEZE]](s8)
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; CHECK-NEXT: %ext:_(s64) = G_AND [[ANYEXT]], [[C]]
; CHECK-NEXT: $x0 = COPY %ext(s64)
%x:_(s1) = G_IMPLICIT_DEF
%freeze:_(s1) = G_FREEZE %x
%ext:_(s64) = G_ZEXT %freeze
$x0 = COPY %ext(s64)
...
---
name: test_freeze_s2
body: |
bb.0.entry:
liveins: $x0
; CHECK-LABEL: name: test_freeze_s2
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s8) = G_IMPLICIT_DEF
; CHECK-NEXT: [[FREEZE:%[0-9]+]]:_(s8) = G_FREEZE [[DEF]]
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[FREEZE]](s8)
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 3
; CHECK-NEXT: %ext:_(s64) = G_AND [[ANYEXT]], [[C]]
; CHECK-NEXT: $x0 = COPY %ext(s64)
%x:_(s2) = G_IMPLICIT_DEF
%freeze:_(s2) = G_FREEZE %x
%ext:_(s64) = G_ZEXT %freeze
$x0 = COPY %ext(s64)
...
---
name: test_freeze_v4s1
body: |
bb.0.entry:
liveins: $q0
; CHECK-LABEL: name: test_freeze_v4s1
; CHECK: liveins: $q0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
; CHECK-NEXT: [[FREEZE:%[0-9]+]]:_(<4 x s16>) = G_FREEZE [[DEF]]
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(<4 x s32>) = G_ANYEXT [[FREEZE]](<4 x s16>)
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32)
; CHECK-NEXT: %ext:_(<4 x s32>) = G_AND [[ANYEXT]], [[BUILD_VECTOR]]
; CHECK-NEXT: $q0 = COPY %ext(<4 x s32>)
%x:_(<4 x s1>) = G_IMPLICIT_DEF
%freeze:_(<4 x s1>) = G_FREEZE %x
%ext:_(<4 x s32>) = G_ZEXT %freeze
$q0 = COPY %ext(<4 x s32>)
...
---
name: test_freeze_v3s8
body: |
bb.0.entry:
liveins: $q0
; CHECK-LABEL: name: test_freeze_v3s8
; CHECK: liveins: $q0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
; CHECK-NEXT: [[UV:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16), [[UV2:%[0-9]+]]:_(s16), [[UV3:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[DEF]](<4 x s16>)
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[UV]](s16)
; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[UV1]](s16)
; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:_(s8) = G_TRUNC [[UV2]](s16)
; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(s8) = G_IMPLICIT_DEF
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s8>) = G_BUILD_VECTOR [[TRUNC]](s8), [[TRUNC1]](s8), [[TRUNC2]](s8), [[DEF1]](s8), [[DEF1]](s8), [[DEF1]](s8), [[DEF1]](s8), [[DEF1]](s8)
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(<8 x s16>) = G_ANYEXT [[BUILD_VECTOR]](<8 x s8>)
; CHECK-NEXT: [[UV4:%[0-9]+]]:_(<4 x s16>), [[UV5:%[0-9]+]]:_(<4 x s16>) = G_UNMERGE_VALUES [[ANYEXT]](<8 x s16>)
; CHECK-NEXT: [[FREEZE:%[0-9]+]]:_(<4 x s16>) = G_FREEZE [[UV4]]
; CHECK-NEXT: [[UV6:%[0-9]+]]:_(s16), [[UV7:%[0-9]+]]:_(s16), [[UV8:%[0-9]+]]:_(s16), [[UV9:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[FREEZE]](<4 x s16>)
; CHECK-NEXT: %undef:_(s32) = G_IMPLICIT_DEF
; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[UV6]](s16)
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; CHECK-NEXT: %ext0:_(s32) = G_AND [[ANYEXT1]], [[C]]
; CHECK-NEXT: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[UV7]](s16)
; CHECK-NEXT: %ext1:_(s32) = G_AND [[ANYEXT2]], [[C]]
; CHECK-NEXT: [[ANYEXT3:%[0-9]+]]:_(s32) = G_ANYEXT [[UV8]](s16)
; CHECK-NEXT: %ext2:_(s32) = G_AND [[ANYEXT3]], [[C]]
; CHECK-NEXT: %res:_(<4 x s32>) = G_BUILD_VECTOR %ext0(s32), %ext1(s32), %ext2(s32), %undef(s32)
; CHECK-NEXT: $q0 = COPY %res(<4 x s32>)
%x:_(<3 x s8>) = G_IMPLICIT_DEF
%freeze:_(<3 x s8>) = G_FREEZE %x
%ext:_(<3 x s32>) = G_ZEXT %freeze
%undef:_(s32) = G_IMPLICIT_DEF
%ext0:_(s32), %ext1:_(s32), %ext2:_(s32) = G_UNMERGE_VALUES %ext
%res:_(<4 x s32>) = G_BUILD_VECTOR %ext0, %ext1, %ext2, %undef
$q0 = COPY %res(<4 x s32>)
...
---
name: test_freeze_v4s1_select
body: |
bb.0.entry:
liveins: $q0, $q1
; CHECK-LABEL: name: test_freeze_v4s1_select
; CHECK: liveins: $q0, $q1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $q1
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32)
; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(<4 x s32>) = nnan ninf nsz arcp contract afn reassoc G_FCMP floatpred(olt), [[COPY]](<4 x s32>), [[BUILD_VECTOR]]
; CHECK-NEXT: [[FCMP1:%[0-9]+]]:_(<4 x s32>) = nnan ninf nsz arcp contract afn reassoc G_FCMP floatpred(ogt), [[COPY1]](<4 x s32>), [[COPY]]
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(<4 x s16>) = G_TRUNC [[FCMP1]](<4 x s32>)
; CHECK-NEXT: [[FREEZE:%[0-9]+]]:_(<4 x s16>) = G_FREEZE [[TRUNC]]
; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(<4 x s16>) = G_TRUNC [[FCMP]](<4 x s32>)
; CHECK-NEXT: [[AND:%[0-9]+]]:_(<4 x s16>) = G_AND [[TRUNC1]], [[FREEZE]]
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(<4 x s32>) = G_ANYEXT [[AND]](<4 x s16>)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[C1]](s32), [[C1]](s32), [[C1]](s32), [[C1]](s32)
; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<4 x s32>) = G_AND [[ANYEXT]], [[BUILD_VECTOR1]]
; CHECK-NEXT: $q0 = COPY [[AND1]](<4 x s32>)
%1:_(<4 x s32>) = COPY $q0
%2:_(<4 x s32>) = COPY $q1
%3:_(s32) = G_CONSTANT i32 0
%4:_(<4 x s32>) = G_BUILD_VECTOR %3, %3, %3, %3
%5:_(s1) = G_CONSTANT i1 false
%6:_(<4 x s1>) = nnan ninf nsz arcp contract afn reassoc G_FCMP floatpred(olt), %1:_(<4 x s32>), %4:_
%7:_(<4 x s1>) = nnan ninf nsz arcp contract afn reassoc G_FCMP floatpred(ogt), %2:_(<4 x s32>), %1:_
%8:_(<4 x s1>) = G_FREEZE %7
%9:_(<4 x s1>) = G_AND %6, %8
%10:_(<4 x s32>) = G_ZEXT %9
$q0 = COPY %10
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