ssub_sat.ll | Explore in Territory

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=aarch64-- | FileCheck %s --check-prefixes=CHECK,CHECK-SD
; RUN: llc < %s -mtriple=aarch64-- -global-isel -global-isel-abort=2 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI

declare i4 @llvm.ssub.sat.i4(i4, i4)
declare i8 @llvm.ssub.sat.i8(i8, i8)
declare i16 @llvm.ssub.sat.i16(i16, i16)
declare i32 @llvm.ssub.sat.i32(i32, i32)
declare i64 @llvm.ssub.sat.i64(i64, i64)
declare <4 x i32> @llvm.ssub.sat.v4i32(<4 x i32>, <4 x i32>)

define i32 @func(i32 %x, i32 %y) nounwind {
; CHECK-SD-LABEL: func:
; CHECK-SD:       // %bb.0:
; CHECK-SD-NEXT:    subs w8, w0, w1
; CHECK-SD-NEXT:    asr w9, w8, #31
; CHECK-SD-NEXT:    eor w9, w9, #0x80000000
; CHECK-SD-NEXT:    csel w0, w9, w8, vs
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: func:
; CHECK-GI:       // %bb.0:
; CHECK-GI-NEXT:    mov w8, #-2147483648 // =0x80000000
; CHECK-GI-NEXT:    subs w9, w0, w1
; CHECK-GI-NEXT:    cset w10, vs
; CHECK-GI-NEXT:    add w8, w8, w9, asr #31
; CHECK-GI-NEXT:    tst w10, #0x1
; CHECK-GI-NEXT:    csel w0, w8, w9, ne
; CHECK-GI-NEXT:    ret
  %tmp = call i32 @llvm.ssub.sat.i32(i32 %x, i32 %y);
  ret i32 %tmp;
}

define i64 @func2(i64 %x, i64 %y) nounwind {
; CHECK-SD-LABEL: func2:
; CHECK-SD:       // %bb.0:
; CHECK-SD-NEXT:    subs x8, x0, x1
; CHECK-SD-NEXT:    asr x9, x8, #63
; CHECK-SD-NEXT:    eor x9, x9, #0x8000000000000000
; CHECK-SD-NEXT:    csel x0, x9, x8, vs
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: func2:
; CHECK-GI:       // %bb.0:
; CHECK-GI-NEXT:    mov x8, #-9223372036854775808 // =0x8000000000000000
; CHECK-GI-NEXT:    subs x9, x0, x1
; CHECK-GI-NEXT:    cset w10, vs
; CHECK-GI-NEXT:    add x8, x8, x9, asr #63
; CHECK-GI-NEXT:    tst w10, #0x1
; CHECK-GI-NEXT:    csel x0, x8, x9, ne
; CHECK-GI-NEXT:    ret
  %tmp = call i64 @llvm.ssub.sat.i64(i64 %x, i64 %y);
  ret i64 %tmp;
}

define i16 @func16(i16 %x, i16 %y) nounwind {
; CHECK-SD-LABEL: func16:
; CHECK-SD:       // %bb.0:
; CHECK-SD-NEXT:    sxth w8, w0
; CHECK-SD-NEXT:    mov w9, #32767 // =0x7fff
; CHECK-SD-NEXT:    sub w8, w8, w1, sxth
; CHECK-SD-NEXT:    cmp w8, w9
; CHECK-SD-NEXT:    csel w8, w8, w9, lt
; CHECK-SD-NEXT:    mov w9, #-32768 // =0xffff8000
; CHECK-SD-NEXT:    cmn w8, #8, lsl #12 // =32768
; CHECK-SD-NEXT:    csel w0, w8, w9, gt
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: func16:
; CHECK-GI:       // %bb.0:
; CHECK-GI-NEXT:    sxth w8, w0
; CHECK-GI-NEXT:    sub w8, w8, w1, sxth
; CHECK-GI-NEXT:    sxth w9, w8
; CHECK-GI-NEXT:    asr w10, w9, #15
; CHECK-GI-NEXT:    cmp w8, w9
; CHECK-GI-NEXT:    sub w10, w10, #8, lsl #12 // =32768
; CHECK-GI-NEXT:    csel w0, w10, w8, ne
; CHECK-GI-NEXT:    ret
  %tmp = call i16 @llvm.ssub.sat.i16(i16 %x, i16 %y);
  ret i16 %tmp;
}

define i8 @func8(i8 %x, i8 %y) nounwind {
; CHECK-SD-LABEL: func8:
; CHECK-SD:       // %bb.0:
; CHECK-SD-NEXT:    sxtb w9, w0
; CHECK-SD-NEXT:    mov w8, #127 // =0x7f
; CHECK-SD-NEXT:    sub w9, w9, w1, sxtb
; CHECK-SD-NEXT:    cmp w9, #127
; CHECK-SD-NEXT:    csel w8, w9, w8, lt
; CHECK-SD-NEXT:    mov w9, #-128 // =0xffffff80
; CHECK-SD-NEXT:    cmn w8, #128
; CHECK-SD-NEXT:    csel w0, w8, w9, gt
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: func8:
; CHECK-GI:       // %bb.0:
; CHECK-GI-NEXT:    sxtb w8, w0
; CHECK-GI-NEXT:    sub w8, w8, w1, sxtb
; CHECK-GI-NEXT:    sxtb w9, w8
; CHECK-GI-NEXT:    asr w10, w9, #7
; CHECK-GI-NEXT:    cmp w8, w9
; CHECK-GI-NEXT:    sub w10, w10, #128
; CHECK-GI-NEXT:    csel w0, w10, w8, ne
; CHECK-GI-NEXT:    ret
  %tmp = call i8 @llvm.ssub.sat.i8(i8 %x, i8 %y);
  ret i8 %tmp;
}

define i4 @func3(i4 %x, i4 %y) nounwind {
; CHECK-SD-LABEL: func3:
; CHECK-SD:       // %bb.0:
; CHECK-SD-NEXT:    lsl w9, w1, #28
; CHECK-SD-NEXT:    sbfx w10, w0, #0, #4
; CHECK-SD-NEXT:    mov w8, #7 // =0x7
; CHECK-SD-NEXT:    sub w9, w10, w9, asr #28
; CHECK-SD-NEXT:    cmp w9, #7
; CHECK-SD-NEXT:    csel w8, w9, w8, lt
; CHECK-SD-NEXT:    mov w9, #-8 // =0xfffffff8
; CHECK-SD-NEXT:    cmn w8, #8
; CHECK-SD-NEXT:    csel w0, w8, w9, gt
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: func3:
; CHECK-GI:       // %bb.0:
; CHECK-GI-NEXT:    sbfx w8, w0, #0, #4
; CHECK-GI-NEXT:    sbfx w9, w1, #0, #4
; CHECK-GI-NEXT:    sub w8, w8, w9
; CHECK-GI-NEXT:    sbfx w9, w8, #0, #4
; CHECK-GI-NEXT:    asr w10, w9, #3
; CHECK-GI-NEXT:    cmp w8, w9
; CHECK-GI-NEXT:    add w10, w10, #8
; CHECK-GI-NEXT:    csel w0, w10, w8, ne
; CHECK-GI-NEXT:    ret
  %tmp = call i4 @llvm.ssub.sat.i4(i4 %x, i4 %y);
  ret i4 %tmp;
}

define <4 x i32> @vec(<4 x i32> %x, <4 x i32> %y) nounwind {
; CHECK-LABEL: vec:
; CHECK:       // %bb.0:
; CHECK-NEXT:    sqsub v0.4s, v0.4s, v1.4s
; CHECK-NEXT:    ret
  %tmp = call <4 x i32> @llvm.ssub.sat.v4i32(<4 x i32> %x, <4 x i32> %y);
  ret <4 x i32> %tmp;
}
llvm/llvm/test/CodeGen/AArch64/ssub_sat.ll
